diff --git a/BENCHMARK/Simon_bit_serial_top_module/Simon_bit_serial_top_module_yosys.blif b/BENCHMARK/Simon_bit_serial_top_module/Simon_bit_serial_top_module_yosys.blif
new file mode 100644
index 0000000..e7ff4ae
--- /dev/null
+++ b/BENCHMARK/Simon_bit_serial_top_module/Simon_bit_serial_top_module_yosys.blif
@@ -0,0 +1,1180 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model Simon_bit_serial_top
+.inputs clk data_in data_rdy(0) data_rdy(1)
+.outputs cipher_out
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_1 a=key_exp.Z(0)
+.subckt logic_0 a=key_exp.Z(1)
+.subckt out_buff A=datapath.cipher_out Q=cipher_out
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=clk Q=datapath.clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_in Q=datapath.data_in
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_rdy(0) Q=datapath.shifter_enable1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_rdy(1) Q=key_exp.fifo_ff_enable
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt LUT4 I0=datapath.cipher_out I1=datapath.shift_in2 I2=datapath.shift_in1_LUT4_O_I2 I3=datapath.round_counter O=datapath.fifo_ff_input_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=cipher_out_LUT4_O_I0 I1=cipher_out_LUT4_O_I1 I2=datapath.key_in I3=datapath.shift_out2 O=datapath.cipher_out
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.fifo_ff_enable I2=datapath.data_in I3=datapath.shifter_enable1 O=key_exp.shift_in1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=bit_counter(5) D=datapath.bit_counter_ff_CQZ_D QCK=datapath.clk QEN=datapath.bit_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:210.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=bit_counter(4) D=datapath.bit_counter_ff_CQZ_1_D QCK=datapath.clk QEN=datapath.bit_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:210.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=datapath.shifter_enable1 I1=key_exp.fifo_ff_enable I2=datapath.bit_counter_ff_CQZ_1_D_LUT4_O_I2 I3=bit_counter(4) O=datapath.bit_counter_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011100000
+.subckt LUT4 I0=bit_counter(1) I1=bit_counter(0) I2=bit_counter(2) I3=bit_counter(3) O=datapath.bit_counter_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=bit_counter(3) D=datapath.bit_counter_ff_CQZ_2_D QCK=datapath.clk QEN=datapath.bit_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:210.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.bit_counter_ff_CQZ_2_D_LUT4_O_I1 I2=key_exp.fifo_ff_enable I3=datapath.shifter_enable1 O=datapath.bit_counter_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=bit_counter(1) I1=bit_counter(0) I2=bit_counter(2) I3=bit_counter(3) O=datapath.bit_counter_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=bit_counter(2) D=datapath.bit_counter_ff_CQZ_3_D QCK=datapath.clk QEN=datapath.bit_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:210.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.bit_counter_ff_CQZ_3_D_LUT4_O_I1 I2=key_exp.fifo_ff_enable I3=datapath.shifter_enable1 O=datapath.bit_counter_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=key_exp.Z(1) I1=bit_counter(2) I2=bit_counter(0) I3=bit_counter(1) O=datapath.bit_counter_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt ff CQZ=bit_counter(1) D=datapath.bit_counter_ff_CQZ_4_D QCK=datapath.clk QEN=datapath.bit_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:210.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=datapath.shifter_enable1 I1=key_exp.fifo_ff_enable I2=bit_counter(1) I3=bit_counter(0) O=datapath.bit_counter_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011100000
+.subckt ff CQZ=bit_counter(0) D=datapath.bit_counter_ff_CQZ_5_D QCK=datapath.clk QEN=datapath.bit_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:210.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=bit_counter(0) I2=key_exp.fifo_ff_enable I3=datapath.shifter_enable1 O=datapath.bit_counter_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=datapath.shifter_enable1 I1=key_exp.fifo_ff_enable I2=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2 I3=bit_counter(5) O=datapath.bit_counter_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011100000
+.subckt LUT4 I0=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2 I1=datapath.shifter_enable1 I2=key_exp.fifo_ff_enable I3=bit_counter(5) O=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2_LUT4_I0_O I2=datapath.shifter_enable1 I3=key_exp.fifo_ff_enable O=key_exp.round_counter_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=bit_counter(4) I3=datapath.bit_counter_ff_CQZ_1_D_LUT4_O_I2 O=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=key_exp.fifo_ff_enable I3=datapath.shifter_enable1 O=datapath.bit_counter_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=datapath.fifo_ff56 D=datapath.fifo_ff57 QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:76.1-89.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.fifo_ff57 D=datapath.fifo_ff58 QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:76.1-89.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.fifo_ff58 D=datapath.fifo_ff59 QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:76.1-89.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.fifo_ff59 D=datapath.fifo_ff60 QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:76.1-89.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.fifo_ff60 D=datapath.fifo_ff61 QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:76.1-89.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.fifo_ff61 D=datapath.fifo_ff62 QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:76.1-89.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.fifo_ff62 D=datapath.fifo_ff63 QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:76.1-89.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.fifo_ff63 I2=datapath.fifo_ff56 I3=datapath.round_counter O=datapath.fifo_ff63_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=datapath.fifo_ff63 D=datapath.fifo_ff_input QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:76.1-89.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.fifo_ff_input_LUT4_O_I1 I2=datapath.shift_in1_LUT4_O_I2 I3=datapath.data_in O=datapath.fifo_ff_input
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=datapath.key_in I3=key_exp.shift_out1 O=datapath.key_in_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=datapath.key_in D=key_exp.shifter2(1) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=datapath.lut_ff56 I1=datapath.lut_ff63 I2=datapath.round_counter I3=datapath.fifo_ff63_LUT4_I1_O O=cipher_out_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt ff CQZ=datapath.lut_ff56 D=datapath.lut_ff57 QCK=datapath.clk QEN=key_exp.Z(0) QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:93.1-103.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=datapath.lut_ff57 D=datapath.lut_ff58 QCK=datapath.clk QEN=key_exp.Z(0) QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:93.1-103.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=datapath.lut_ff58 D=datapath.lut_ff59 QCK=datapath.clk QEN=key_exp.Z(0) QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:93.1-103.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=datapath.lut_ff59 D=datapath.lut_ff60 QCK=datapath.clk QEN=key_exp.Z(0) QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:93.1-103.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=datapath.lut_ff60 D=datapath.lut_ff61 QCK=datapath.clk QEN=key_exp.Z(0) QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:93.1-103.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=datapath.lut_ff61 D=datapath.lut_ff62 QCK=datapath.clk QEN=key_exp.Z(0) QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:93.1-103.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.round_counter I2=datapath.fifo_ff62 I3=datapath.lut_ff62 O=cipher_out_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=datapath.lut_ff62 D=datapath.lut_ff63 QCK=datapath.clk QEN=key_exp.Z(0) QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:93.1-103.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=datapath.lut_ff63 D=datapath.lut_ff_input QCK=datapath.clk QEN=key_exp.Z(0) QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:93.1-103.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.round_counter I2=datapath.shift_in2 I3=datapath.cipher_out O=datapath.lut_ff_input
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt ff CQZ=datapath.round_counter D=datapath.round_counter_ff_CQZ_D QCK=datapath.clk QEN=key_exp.round_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:207.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2_LUT4_I0_O I3=datapath.round_counter O=datapath.round_counter_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=datapath.lut_ff56 I1=datapath.fifo_ff56 I2=datapath.shift_in1_LUT4_O_I2 I3=datapath.shift_in1_LUT4_O_I3 O=datapath.shift_in1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=datapath.shifter_enable1 I3=key_exp.fifo_ff_enable O=datapath.shift_in1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=bit_counter(5) I1=bit_counter(3) I2=bit_counter(4) I3=datapath.round_counter O=datapath.shift_in1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000001
+.subckt ff CQZ=datapath.shift_in2 D=datapath.shifter1(1) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shift_out2 D=datapath.shifter2(1) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(55) D=datapath.shift_in1 QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(54) D=datapath.shifter1(55) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(45) D=datapath.shifter1(46) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(44) D=datapath.shifter1(45) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(43) D=datapath.shifter1(44) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(42) D=datapath.shifter1(43) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(41) D=datapath.shifter1(42) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(40) D=datapath.shifter1(41) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(39) D=datapath.shifter1(40) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(38) D=datapath.shifter1(39) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(37) D=datapath.shifter1(38) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(36) D=datapath.shifter1(37) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(53) D=datapath.shifter1(54) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(35) D=datapath.shifter1(36) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(34) D=datapath.shifter1(35) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(33) D=datapath.shifter1(34) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(32) D=datapath.shifter1(33) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(31) D=datapath.shifter1(32) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(30) D=datapath.shifter1(31) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(29) D=datapath.shifter1(30) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(28) D=datapath.shifter1(29) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(27) D=datapath.shifter1(28) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(26) D=datapath.shifter1(27) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(52) D=datapath.shifter1(53) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(25) D=datapath.shifter1(26) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(24) D=datapath.shifter1(25) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(23) D=datapath.shifter1(24) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(22) D=datapath.shifter1(23) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(21) D=datapath.shifter1(22) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(20) D=datapath.shifter1(21) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(19) D=datapath.shifter1(20) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(18) D=datapath.shifter1(19) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(17) D=datapath.shifter1(18) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(16) D=datapath.shifter1(17) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(51) D=datapath.shifter1(52) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(15) D=datapath.shifter1(16) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(14) D=datapath.shifter1(15) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(13) D=datapath.shifter1(14) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(12) D=datapath.shifter1(13) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(11) D=datapath.shifter1(12) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(10) D=datapath.shifter1(11) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(9) D=datapath.shifter1(10) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(8) D=datapath.shifter1(9) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(7) D=datapath.shifter1(8) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(6) D=datapath.shifter1(7) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(50) D=datapath.shifter1(51) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(5) D=datapath.shifter1(6) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(4) D=datapath.shifter1(5) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(3) D=datapath.shifter1(4) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(2) D=datapath.shifter1(3) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(1) D=datapath.shifter1(2) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(49) D=datapath.shifter1(50) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(48) D=datapath.shifter1(49) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(47) D=datapath.shifter1(48) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter1(46) D=datapath.shifter1(47) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:49.1-55.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(63) D=datapath.shift_in2 QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(62) D=datapath.shifter2(63) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(53) D=datapath.shifter2(54) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(52) D=datapath.shifter2(53) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(51) D=datapath.shifter2(52) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(50) D=datapath.shifter2(51) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(49) D=datapath.shifter2(50) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(48) D=datapath.shifter2(49) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(47) D=datapath.shifter2(48) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(46) D=datapath.shifter2(47) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(45) D=datapath.shifter2(46) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(44) D=datapath.shifter2(45) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(61) D=datapath.shifter2(62) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(43) D=datapath.shifter2(44) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(42) D=datapath.shifter2(43) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(41) D=datapath.shifter2(42) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(40) D=datapath.shifter2(41) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(39) D=datapath.shifter2(40) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(38) D=datapath.shifter2(39) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(37) D=datapath.shifter2(38) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(36) D=datapath.shifter2(37) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(35) D=datapath.shifter2(36) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(34) D=datapath.shifter2(35) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(60) D=datapath.shifter2(61) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(33) D=datapath.shifter2(34) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(32) D=datapath.shifter2(33) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(31) D=datapath.shifter2(32) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(30) D=datapath.shifter2(31) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(29) D=datapath.shifter2(30) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(28) D=datapath.shifter2(29) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(27) D=datapath.shifter2(28) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(26) D=datapath.shifter2(27) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(25) D=datapath.shifter2(26) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(24) D=datapath.shifter2(25) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(59) D=datapath.shifter2(60) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(23) D=datapath.shifter2(24) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(22) D=datapath.shifter2(23) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(21) D=datapath.shifter2(22) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(20) D=datapath.shifter2(21) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(19) D=datapath.shifter2(20) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(18) D=datapath.shifter2(19) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(17) D=datapath.shifter2(18) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(16) D=datapath.shifter2(17) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(15) D=datapath.shifter2(16) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(14) D=datapath.shifter2(15) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(58) D=datapath.shifter2(59) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(13) D=datapath.shifter2(14) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(12) D=datapath.shifter2(13) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(11) D=datapath.shifter2(12) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(10) D=datapath.shifter2(11) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(9) D=datapath.shifter2(10) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(8) D=datapath.shifter2(9) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(7) D=datapath.shifter2(8) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(6) D=datapath.shifter2(7) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(5) D=datapath.shifter2(6) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(4) D=datapath.shifter2(5) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(57) D=datapath.shifter2(58) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(3) D=datapath.shifter2(4) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(2) D=datapath.shifter2(3) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(1) D=datapath.shifter2(2) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(56) D=datapath.shifter2(57) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(55) D=datapath.shifter2(56) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=datapath.shifter2(54) D=datapath.shifter2(55) QCK=datapath.clk QEN=datapath.shifter_enable1 QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:38.25-39.97|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v:62.1-68.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.fifo_ff0 D=key_exp.fifo_ff1 QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:89.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.fifo_ff1 D=key_exp.fifo_ff2 QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:89.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.fifo_ff2 D=key_exp.fifo_ff3 QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:89.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.fifo_ff3 D=key_exp.shift_out1 QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:89.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.lut_ff0 I1=key_exp.lut_ff0_LUT4_I0_I1 I2=datapath.shifter_enable1 I3=key_exp.fifo_ff_enable O=key_exp.lut_ff0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=bit_counter(5) I1=bit_counter(2) I2=bit_counter(3) I3=bit_counter(4) O=key_exp.lut_ff0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=key_exp.lut_ff0 D=key_exp.lut_ff1 QCK=datapath.clk QEN=key_exp.lut_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:101.1-110.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.lut_ff1 D=key_exp.lut_ff2 QCK=datapath.clk QEN=key_exp.lut_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:101.1-110.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.lut_ff2 D=key_exp.lut_ff3 QCK=datapath.clk QEN=key_exp.lut_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:101.1-110.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.lut_ff3 I1=key_exp.fifo_ff3 I2=key_exp.lut_ff3_LUT4_I0_I2 I3=datapath.key_in_LUT4_I2_O O=key_exp.lut_out_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110001010011
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.lut_out_LUT4_O_I3_LUT4_O_I3 I2=bit_counter(0) I3=key_exp.shift_in2_LUT4_O_I1_LUT4_O_I0 O=key_exp.lut_ff3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=key_exp.lut_ff3 D=key_exp.lut_out QCK=datapath.clk QEN=key_exp.lut_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:101.1-110.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.fifo_ff_enable I2=datapath.shifter_enable1 I3=key_exp.lut_ff0_LUT4_I0_I1 O=key_exp.lut_ff_enable
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=key_exp.lut_out_LUT4_O_I2 I3=key_exp.lut_out_LUT4_O_I3 O=key_exp.lut_out
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0 I1=key_exp.round_counter(1) I2=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2 I3=key_exp.lut_out_LUT4_O_I3_LUT4_O_I3 O=key_exp.lut_out_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=key_exp.round_counter(5) I3=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111110100000
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.round_counter(2) I2=key_exp.round_counter(3) I3=datapath.round_counter O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101001
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.round_counter I2=key_exp.round_counter(2) I3=key_exp.round_counter(3) O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011100
+.subckt LUT4 I0=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=key_exp.round_counter(5) I3=key_exp.round_counter(4) O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110000001010
+.subckt LUT4 I0=key_exp.round_counter(6) I1=datapath.round_counter I2=key_exp.round_counter(3) I3=key_exp.round_counter(2) O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111111011
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.round_counter(2) I2=datapath.round_counter I3=key_exp.round_counter(3) O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=key_exp.Z(1) I1=bit_counter(0) I2=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=key_exp.round_counter(1) O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=datapath.round_counter O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=key_exp.round_counter(4) I1=key_exp.round_counter(3) I2=key_exp.round_counter(5) I3=key_exp.round_counter(2) O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110001100000000
+.subckt LUT4 I0=key_exp.round_counter(2) I1=key_exp.round_counter(4) I2=key_exp.round_counter(5) I3=key_exp.round_counter(3) O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=key_exp.round_counter(2) I1=key_exp.round_counter(4) I2=key_exp.round_counter(5) I3=key_exp.round_counter(3) O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110110001010011
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=key_exp.lut_ff0_LUT4_I0_I1 I3=bit_counter(1) O=key_exp.lut_out_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=key_exp.round_counter(6) D=key_exp.round_counter_ff_CQZ_D QCK=datapath.clk QEN=key_exp.round_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:207.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.round_counter(5) D=key_exp.round_counter_ff_CQZ_1_D QCK=datapath.clk QEN=key_exp.round_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:207.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.round_counter_ff_CQZ_2_D_LUT4_O_I3 I1=key_exp.round_counter(4) I2=key_exp.round_counter(5) I3=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2_LUT4_I0_O O=key_exp.round_counter_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=key_exp.round_counter(4) D=key_exp.round_counter_ff_CQZ_2_D QCK=datapath.clk QEN=key_exp.round_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:207.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2_LUT4_I0_O I2=key_exp.round_counter(4) I3=key_exp.round_counter_ff_CQZ_2_D_LUT4_O_I3 O=key_exp.round_counter_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=datapath.round_counter I1=key_exp.round_counter(1) I2=key_exp.round_counter(2) I3=key_exp.round_counter(3) O=key_exp.round_counter_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=key_exp.round_counter(3) D=key_exp.round_counter_ff_CQZ_3_D QCK=datapath.clk QEN=key_exp.round_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:207.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2_LUT4_I0_O I3=key_exp.round_counter_ff_CQZ_3_D_LUT4_O_I3 O=key_exp.round_counter_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=datapath.round_counter I1=key_exp.round_counter(1) I2=key_exp.round_counter(2) I3=key_exp.round_counter(3) O=key_exp.round_counter_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=key_exp.round_counter(2) D=key_exp.round_counter_ff_CQZ_4_D QCK=datapath.clk QEN=key_exp.round_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:207.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=datapath.round_counter I1=key_exp.round_counter(1) I2=key_exp.round_counter(2) I3=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2_LUT4_I0_O O=key_exp.round_counter_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=key_exp.round_counter(1) D=key_exp.round_counter_ff_CQZ_5_D QCK=datapath.clk QEN=key_exp.round_counter_ff_CQZ_QEN QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:207.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=key_exp.Z(1) I1=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2_LUT4_I0_O I2=key_exp.round_counter(1) I3=datapath.round_counter O=key_exp.round_counter_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=datapath.bit_counter_ff_CQZ_D_LUT4_O_I2_LUT4_I0_O I3=key_exp.round_counter_ff_CQZ_D_LUT4_O_I3 O=key_exp.round_counter_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_exp.round_counter_ff_CQZ_2_D_LUT4_O_I3 I1=key_exp.round_counter(4) I2=key_exp.round_counter(5) I3=key_exp.round_counter(6) O=key_exp.round_counter_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=key_exp.shift_in1_LUT4_O_I0 I1=key_exp.shift_in1_LUT4_O_I1 I2=key_exp.fifo_ff0 I3=key_exp.shift_in1_LUT4_O_I3 O=key_exp.shift_in1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=key_exp.lut_ff_enable I1=key_exp.lut_out_LUT4_O_I2 I2=key_exp.lut_out_LUT4_O_I3 I3=key_exp.lut_ff0_LUT4_I0_O O=key_exp.shift_in1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=key_exp.shift_in2_LUT4_O_I1_LUT4_O_I0 I3=key_exp.lut_ff_enable O=key_exp.shift_in1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.shift_in2_LUT4_O_I1 I2=key_exp.lut_ff0 I3=key_exp.fifo_ff0 O=key_exp.shift_in2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=key_exp.shift_in2_LUT4_O_I1_LUT4_O_I0 I1=key_exp.lut_ff0_LUT4_I0_I1 I2=datapath.shifter_enable1 I3=key_exp.fifo_ff_enable O=key_exp.shift_in2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.shift_in2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=key_exp.shift_in2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=key_exp.round_counter(5) O=key_exp.shift_in2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=key_exp.Z(1) I1=key_exp.Z(1) I2=key_exp.round_counter(3) I3=key_exp.round_counter(2) O=key_exp.shift_in2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=datapath.round_counter I1=key_exp.round_counter(1) I2=key_exp.round_counter(4) I3=key_exp.round_counter(6) O=key_exp.shift_in2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=key_exp.shift_out1 D=key_exp.shifter1(1) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(59) D=key_exp.shift_in1 QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(58) D=key_exp.shifter1(59) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(49) D=key_exp.shifter1(50) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(48) D=key_exp.shifter1(49) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(47) D=key_exp.shifter1(48) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(46) D=key_exp.shifter1(47) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(45) D=key_exp.shifter1(46) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(44) D=key_exp.shifter1(45) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(43) D=key_exp.shifter1(44) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(42) D=key_exp.shifter1(43) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(41) D=key_exp.shifter1(42) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(40) D=key_exp.shifter1(41) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(57) D=key_exp.shifter1(58) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(39) D=key_exp.shifter1(40) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(38) D=key_exp.shifter1(39) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(37) D=key_exp.shifter1(38) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(36) D=key_exp.shifter1(37) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(35) D=key_exp.shifter1(36) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(34) D=key_exp.shifter1(35) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(33) D=key_exp.shifter1(34) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(32) D=key_exp.shifter1(33) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(31) D=key_exp.shifter1(32) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(30) D=key_exp.shifter1(31) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(56) D=key_exp.shifter1(57) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(29) D=key_exp.shifter1(30) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(28) D=key_exp.shifter1(29) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(27) D=key_exp.shifter1(28) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(26) D=key_exp.shifter1(27) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(25) D=key_exp.shifter1(26) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(24) D=key_exp.shifter1(25) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(23) D=key_exp.shifter1(24) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(22) D=key_exp.shifter1(23) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(21) D=key_exp.shifter1(22) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(20) D=key_exp.shifter1(21) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(55) D=key_exp.shifter1(56) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(19) D=key_exp.shifter1(20) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(18) D=key_exp.shifter1(19) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(17) D=key_exp.shifter1(18) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(16) D=key_exp.shifter1(17) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(15) D=key_exp.shifter1(16) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(14) D=key_exp.shifter1(15) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(13) D=key_exp.shifter1(14) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(12) D=key_exp.shifter1(13) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(11) D=key_exp.shifter1(12) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(10) D=key_exp.shifter1(11) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(54) D=key_exp.shifter1(55) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(9) D=key_exp.shifter1(10) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(8) D=key_exp.shifter1(9) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(7) D=key_exp.shifter1(8) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(6) D=key_exp.shifter1(7) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(5) D=key_exp.shifter1(6) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(4) D=key_exp.shifter1(5) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(3) D=key_exp.shifter1(4) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(2) D=key_exp.shifter1(3) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(1) D=key_exp.shifter1(2) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(53) D=key_exp.shifter1(54) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(52) D=key_exp.shifter1(53) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(51) D=key_exp.shifter1(52) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter1(50) D=key_exp.shifter1(51) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:64.1-70.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(10) D=key_exp.shifter2(11) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(9) D=key_exp.shifter2(10) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(63) D=key_exp.shift_in2 QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(62) D=key_exp.shifter2(63) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(61) D=key_exp.shifter2(62) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(60) D=key_exp.shifter2(61) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(59) D=key_exp.shifter2(60) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(58) D=key_exp.shifter2(59) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(57) D=key_exp.shifter2(58) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(56) D=key_exp.shifter2(57) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(55) D=key_exp.shifter2(56) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(54) D=key_exp.shifter2(55) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(8) D=key_exp.shifter2(9) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(53) D=key_exp.shifter2(54) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(52) D=key_exp.shifter2(53) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(51) D=key_exp.shifter2(52) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(50) D=key_exp.shifter2(51) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(49) D=key_exp.shifter2(50) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(48) D=key_exp.shifter2(49) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(47) D=key_exp.shifter2(48) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(46) D=key_exp.shifter2(47) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(45) D=key_exp.shifter2(46) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(44) D=key_exp.shifter2(45) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(7) D=key_exp.shifter2(8) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(43) D=key_exp.shifter2(44) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(42) D=key_exp.shifter2(43) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(41) D=key_exp.shifter2(42) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(40) D=key_exp.shifter2(41) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(39) D=key_exp.shifter2(40) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(38) D=key_exp.shifter2(39) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(37) D=key_exp.shifter2(38) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(36) D=key_exp.shifter2(37) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(35) D=key_exp.shifter2(36) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(34) D=key_exp.shifter2(35) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(6) D=key_exp.shifter2(7) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(33) D=key_exp.shifter2(34) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(32) D=key_exp.shifter2(33) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(31) D=key_exp.shifter2(32) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(30) D=key_exp.shifter2(31) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(29) D=key_exp.shifter2(30) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(28) D=key_exp.shifter2(29) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(27) D=key_exp.shifter2(28) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(26) D=key_exp.shifter2(27) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(25) D=key_exp.shifter2(26) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(24) D=key_exp.shifter2(25) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(5) D=key_exp.shifter2(6) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(23) D=key_exp.shifter2(24) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(22) D=key_exp.shifter2(23) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(21) D=key_exp.shifter2(22) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(20) D=key_exp.shifter2(21) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(19) D=key_exp.shifter2(20) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(18) D=key_exp.shifter2(19) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(17) D=key_exp.shifter2(18) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(16) D=key_exp.shifter2(17) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(15) D=key_exp.shifter2(16) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(14) D=key_exp.shifter2(15) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(4) D=key_exp.shifter2(5) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(13) D=key_exp.shifter2(14) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(12) D=key_exp.shifter2(13) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(11) D=key_exp.shifter2(12) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(3) D=key_exp.shifter2(4) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(2) D=key_exp.shifter2(3) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=key_exp.shifter2(1) D=key_exp.shifter2(2) QCK=datapath.clk QEN=key_exp.fifo_ff_enable QRT=key_exp.Z(1) QST=key_exp.Z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v:41.30-42.49|/home/tpagarani/git/yosys-testing/Designs/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v:77.1-83.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.end
diff --git a/BENCHMARK/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v b/BENCHMARK/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v
new file mode 100644
index 0000000..e48564b
--- /dev/null
+++ b/BENCHMARK/Simon_bit_serial_top_module/rtl/Simon_bit_serial_datapath_FPGA.v
@@ -0,0 +1,225 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Team: Virginia Tech Secure Embedded Systems (SES) Lab 
+// Implementer: Ege Gulcan 
+// 
+// Create Date:    17:21:26 11/13/2013 
+// Design Name: 
+// Module Name:    simon_datapath_shiftreg 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module simon_datapath_shiftreg(clk,data_in,data_rdy,key_in,cipher_out,round_counter,bit_counter);
+
+input clk,data_in,key_in;
+input [1:0] data_rdy;
+input round_counter;
+output cipher_out;
+output [5:0] bit_counter;
+
+reg [55:0] shifter1;
+reg [63:0] shifter2;
+reg shift_in1,shift_in2;
+wire shift_out1,shift_out2;
+reg shifter_enable1,shifter_enable2;
+
+reg fifo_ff63,fifo_ff62,fifo_ff61,fifo_ff60,fifo_ff59,fifo_ff58,fifo_ff57,fifo_ff56;
+reg lut_ff63,lut_ff62,lut_ff61,lut_ff60,lut_ff59,lut_ff58,lut_ff57,lut_ff56;
+
+reg lut_ff_input,fifo_ff_input;
+reg lut_rol1,lut_rol2,lut_rol8;
+reg s1,s4,s5,s6,s7;
+reg [1:0] s3;
+reg [5:0] bit_counter;
+wire lut_out;
+
+
+
+// Shift Register1 FIFO 56x1 Begin
+// 56x1 Shift register to store the upper word
+always @(posedge clk)
+begin
+	if(shifter_enable1)
+	begin
+		shifter1 <= {shift_in1, shifter1[55:1]};
+	end
+end
+
+assign shift_out1 = shifter1[0];
+// Shift Register1 End
+
+// Shift Register2 FIFO 64x1 Begin
+// 64x1 Shift register to store the lower word
+always @(posedge clk)
+begin
+	if(shifter_enable2)
+	begin
+		shifter2 <= {shift_in2, shifter2[63:1]};
+	end
+end
+
+assign shift_out2 = shifter2[0];
+// Shift Register2 End
+
+
+// 8 Flip-Flops to store the most significant 8 bits of the upper word at even rounds
+// Denoted as Shift Register Up (SRU) in Figure 5
+always@(posedge clk)
+begin
+	if(shifter_enable1)
+	begin
+		fifo_ff63 <= fifo_ff_input;
+		fifo_ff62 <= fifo_ff63;
+		fifo_ff61 <= fifo_ff62;
+		fifo_ff60 <= fifo_ff61;
+		fifo_ff59 <= fifo_ff60;
+		fifo_ff58 <= fifo_ff59;
+		fifo_ff57 <= fifo_ff58;
+		fifo_ff56 <= fifo_ff57;
+	end
+end
+
+// 8 Flip-Flops to store the most significant 8 bits of the upper word at odd rounds
+// Denoted as Shift Register Down (SRD) in Figure 5
+always@(posedge clk)
+begin
+	lut_ff63 <= lut_ff_input;
+	lut_ff62 <= lut_ff63;
+	lut_ff61 <= lut_ff62;
+	lut_ff60 <= lut_ff61;
+	lut_ff59 <= lut_ff60;
+	lut_ff58 <= lut_ff59;
+	lut_ff57 <= lut_ff58;
+	lut_ff56 <= lut_ff57;
+end
+
+// FIFO 64x1 Input MUX
+// Input of the lower FIFO is always the output of the upper FIFO
+always@(*)
+begin
+		shift_in2 = shift_out1;
+end
+
+// FIFO 56x1 Input MUX
+// Input of the upper FIFO depends on the select line S1
+always@(*)
+begin
+	if(s1==0)
+		shift_in1 = lut_ff56;
+	else
+		shift_in1 = fifo_ff56;
+end
+
+// FIFO FF Input MUX
+// The input of FIFO_FF can be the input plaintext, output of 56x1 FIFO or the output of LUT
+always@(*)
+begin
+	if(s3==0)
+		fifo_ff_input = data_in;
+	else if(s3==1)
+		fifo_ff_input = shift_out1;
+	else if(s3==2)
+		fifo_ff_input = lut_out;
+	else
+		fifo_ff_input = 1'bx; // Debugging
+end
+
+// LUT FF Input MUX
+// The input of the LUT_FF is either the output of 56x1 FIFO or the output of LUT
+always@(*)
+begin
+	if(s5==0)
+		lut_ff_input = shift_out1;
+	else
+		lut_ff_input = lut_out;
+end
+
+// LUT Input MUX
+always@(*)
+begin
+	if(s7==0)
+		lut_rol1 = fifo_ff63;
+	else
+		lut_rol1 = lut_ff63;
+		
+	if(s4==0)
+		lut_rol2 = fifo_ff62;
+	else
+		lut_rol2 = lut_ff62;
+		
+	if(s6==0)
+		lut_rol8 = fifo_ff56;
+	else
+		lut_rol8 = lut_ff56;
+end
+
+//Selection MUX
+always@(*)
+begin
+	// For the first 8 bits of each even round OR for all the bits after the first 8 bits in odd rounds OR loading the plaintext  
+	if((round_counter==0 && bit_counter<8)||(round_counter==1 && bit_counter>7)||(data_rdy==1))
+		s1 = 1;
+	else 
+		s1 = 0;
+		
+	if(data_rdy==1) // Loading plaintext
+		s3 = 0;
+	else if(round_counter==0) // Even rounds
+		s3 = 1;
+	else if(round_counter==1) // Odd rounds
+		s3 = 2;
+	else 
+		s3 = 1'bx; // For debugging
+		
+	if(round_counter==0) // Even rounds
+		s6 = 0;
+	else
+		s6 = 1;
+	
+	s4 = s6;
+	s7 = s6;
+	s5 = ~s6;
+end
+
+// SHIFTER ENABLES
+// Two shift registers are enabled when the plaintext is being loaded (1) or when the block cipher is running (3)
+always@(*)
+begin
+	if(data_rdy==1 || data_rdy==3)
+	begin
+		shifter_enable1 = 1;
+		shifter_enable2 = 1;
+	end
+	else
+	begin
+		shifter_enable1 = 0;
+		shifter_enable2 = 0;
+	end
+end
+
+// The bit_counter value is incremented in each clock cycle when the block cipher is running
+always@(posedge clk)
+begin
+	if(data_rdy==0)
+		bit_counter <= 0;
+	else if(data_rdy==3)
+		bit_counter <= bit_counter + 1;
+	else 
+		bit_counter <= bit_counter;
+end
+
+// The new computed value
+assign lut_out = (lut_rol1 & lut_rol8) ^ shift_out2 ^ lut_rol2 ^ key_in;
+
+// The global output that gives the ciphertext value
+assign cipher_out = lut_out;
+endmodule
diff --git a/BENCHMARK/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v b/BENCHMARK/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v
new file mode 100644
index 0000000..12b906b
--- /dev/null
+++ b/BENCHMARK/Simon_bit_serial_top_module/rtl/Simon_bit_serial_key_expansion_FPGA.v
@@ -0,0 +1,241 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Team: Virginia Tech Secure Embedded Systems (SES) Lab 
+// Implementer: Ege Gulcan
+// 
+// Create Date:    16:55:06 11/12/2013 
+// Design Name: 
+// Module Name:    simon_key_expansion_shiftreg 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module simon_key_expansion_shiftreg(clk,data_in,key_out,data_rdy,bit_counter,round_counter_out);
+
+input clk;
+input data_in;
+input [1:0] data_rdy;
+input [5:0] bit_counter;
+output key_out;
+output round_counter_out;
+
+
+reg [59:0] shifter1;
+reg [63:0] shifter2;
+reg shift_in1,shift_in2;
+wire shift_out1,shift_out2;
+reg shifter_enable1,shifter_enable2;
+
+reg lut_ff_enable,fifo_ff_enable;
+wire lut_out;
+reg lut_in3;
+reg s2,s3;
+reg [1:0] s1;
+reg [6:0] round_counter;
+reg z_value;
+
+reg fifo_ff0,fifo_ff1,fifo_ff2,fifo_ff3;
+
+//(* shreg_extract = "no" *)
+reg lut_ff0,lut_ff1,lut_ff2,lut_ff3;
+//Constant value Z ROM
+reg [0:67] Z = 68'b10101111011100000011010010011000101000010001111110010110110011101011;
+reg c;
+
+
+/////////////////////////////////////////
+//// BEGIN CODE ////////////////////////
+///////////////////////////////////////
+
+// Least bit of the round counter is sent to the datapath to check if it is even or odd
+assign round_counter_out = round_counter[0];
+
+// Shift Register1 FIFO 60x1 Begin
+// 60x1 shift register storing the 60 most significant bits of the upper word of the key
+always @(posedge clk)
+begin
+	if(shifter_enable1)
+	begin
+		shifter1 <= {shift_in1, shifter1[59:1]};
+	end
+end
+
+assign shift_out1 = shifter1[0];
+// Shift Register1 End
+
+// Shift Register2 FIFO 64x1 Begin
+// 64x1 shift register storing the lower word of the key
+always @(posedge clk)
+begin
+	if(shifter_enable2)
+	begin
+		shifter2 <= {shift_in2, shifter2[63:1]};
+	end
+end
+
+assign shift_out2 = shifter2[0];
+// Shift Register2 End
+
+// 4 flip-flops storing the least significant 4 bits of the upper word in the first round
+always @(posedge clk)
+begin
+	if(fifo_ff_enable)
+	begin
+		fifo_ff3 <= shift_out1;
+		fifo_ff2 <= fifo_ff3;
+		fifo_ff1 <= fifo_ff2;
+		fifo_ff0 <= fifo_ff1;
+	end
+end
+
+// 4 flip-flops storing the least significant 4 bits of the upper word after the first round
+always@(posedge clk)
+begin
+	if(lut_ff_enable)
+	begin
+		lut_ff3 <= lut_out;
+		lut_ff2 <= lut_ff3;
+		lut_ff1 <= lut_ff2;
+		lut_ff0 <= lut_ff1;
+	end
+end
+
+//FIFO 64x1 Input MUX
+always@(*)
+begin
+	if(data_rdy==2)
+		shift_in2 = fifo_ff0;
+	else if(data_rdy==3 && (round_counter<1 || bit_counter>3))
+		shift_in2 = fifo_ff0;
+	else if(data_rdy==3 && bit_counter<4 && round_counter>0) 
+		shift_in2 = lut_ff0; 
+	else
+		shift_in2 = 1'bx;
+end
+
+//LUT >>3 Input MUX
+always@(*)
+begin
+	if(s2==0)
+		lut_in3 = fifo_ff3;
+	else
+		lut_in3 = lut_ff3;
+end
+
+//FIFO 60x1 Input MUX
+always@(*)
+begin
+	if(s1==0)
+		shift_in1 = fifo_ff0;
+	else if(s1==1)
+		shift_in1 = data_in;
+	else if(s1==2)
+		shift_in1 = lut_out;
+	else if(s1==3)
+		shift_in1 = lut_ff0;
+	else
+		shift_in1 = 1'bx;
+end
+
+//S2 MUX
+always@(*)
+begin
+	if(bit_counter==0 && round_counter!=0)
+		s2 = 1;
+	else
+		s2 = 0;
+end
+
+//S1 MUX
+always@(*)
+begin
+	if(data_rdy==2)
+		s1 = 1;
+	else if(data_rdy==3 && bit_counter<4 && round_counter==0)
+		s1 = 0;
+	else if(data_rdy==3 && bit_counter<4 && round_counter>0)
+		s1 = 3;
+	else
+		s1 = 2;
+end
+
+// LUT FF ENABLE MUX
+// LUT FFs are used only at the first four clock cycles of each round
+always@(*)
+begin
+	if(data_rdy==3 && bit_counter<4)
+		lut_ff_enable = 1;
+	else
+		lut_ff_enable = 0;
+end
+
+//FIFO FF ENABLE MUX
+always@(*)
+begin
+	if(data_rdy==2 || data_rdy==3)
+		fifo_ff_enable = 1;
+	else
+		fifo_ff_enable = 0;
+end
+
+//SHIFTER ENABLES
+// Shifters are enabled when the key is loaded or block cipher is running
+always@(*)
+begin
+	if(data_rdy==2 || data_rdy==3)
+		shifter_enable1 = 1;
+	else
+		shifter_enable1 = 0;
+	
+	if(data_rdy==2 || data_rdy==3)
+		shifter_enable2 = 1;
+	else
+		shifter_enable2 = 0;
+		
+end
+
+//Round Counter
+always@(posedge clk)
+begin
+	if(data_rdy==3 && bit_counter==63)
+		round_counter <= round_counter + 1;
+	else if(data_rdy==0)
+		round_counter <= 0;
+	else
+		round_counter <= round_counter;
+end
+
+// The necessary bit of the constant Z is selected by the round counter
+always @(*)
+begin
+	if(bit_counter==0)
+		z_value = Z[round_counter];
+	else
+		z_value = 0;
+end
+
+// The value of c is 1 at the first two cycles of each round only
+always @(*)
+begin
+	if(bit_counter==0 || bit_counter==1)
+		c = 0;
+	else 
+		c = 1;
+end
+
+// New computed key bit
+assign lut_out = shift_out2 ^ lut_in3 ^ shift_out1 ^ z_value ^ c;
+
+// Output key bit that is connected to the datapath	
+assign key_out = shift_out2;
+	
+endmodule
diff --git a/BENCHMARK/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v b/BENCHMARK/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v
new file mode 100644
index 0000000..c7a79a6
--- /dev/null
+++ b/BENCHMARK/Simon_bit_serial_top_module/rtl/Simon_bit_serial_top_module.v
@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Team: Virginia Tech Secure Embedded Systems (SES) Lab 
+// Implementer: Ege Gulcan
+// 
+// Create Date:    19:14:37 11/13/2013 
+// Design Name: 
+// Module Name:    top_module 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Simon_bit_serial_top(clk,data_in,data_rdy,cipher_out);
+
+input clk,data_in;
+input [1:0] data_rdy;
+output cipher_out;
+
+wire key;
+wire [5:0] bit_counter;
+wire round_counter_out;
+
+/*
+	data_rdy=0 -> Reset, Idle
+	data_rdy=1 -> Load Plaintext
+	data_rdy=2 -> Load Key
+	data_rdy=3 -> Run (keep at 3 while the block cipher is running)
+*/
+
+simon_datapath_shiftreg datapath(.clk(clk), .data_in(data_in), .data_rdy(data_rdy), .key_in(key), 
+								 . cipher_out(cipher_out), .round_counter(round_counter_out), .bit_counter(bit_counter));
+											
+simon_key_expansion_shiftreg key_exp(.clk(clk), .data_in(data_in), .data_rdy(data_rdy), .key_out(key), .bit_counter(bit_counter), 
+									 .round_counter_out(round_counter_out));
+
+
+endmodule
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/CM_FIFO_1x.v b/BENCHMARK/ULPSH_fabric/rtl/src/CM_FIFO_1x.v
new file mode 100644
index 0000000..5546314
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/CM_FIFO_1x.v
@@ -0,0 +1,143 @@
+/*-------------------------------------------------------------------
+CM_FIFO_1x
+	Communication Manager (CM) FIFO, using 1 RAM block.
+	18-bit write port (512 deep), 9-bit read port (1024 deep).
+	
+	The LSB on the write port will be the first byte to appear on
+	the read port.
+	
+	Valid data appears on the output data port without first
+	having to do a pop.
+	
+	Over-run and under-run protection are both implemented:
+	reads when empty will be ignored and provide invalid data,
+	writes when full will be ignored.
+
+-------------------------------------------------------------------*/
+
+
+`timescale 1ns / 10ps
+
+module CM_FIFO_1x (
+	rst,
+
+	push_clk,
+	push,
+	din,
+	full,
+	push_flag,
+	overflow,
+
+	pop_clk,
+	pop,
+	dout,
+	empty,
+	pop_flag,
+	
+	CM_FIFO_1x_din_o			,		
+	CM_FIFO_1x_push_int_o		,
+	CM_FIFO_1x_pop_int_o		,
+	CM_FIFO_1x_push_clk_o		,
+	CM_FIFO_1x_pop_clk_o		,
+	CM_FIFO_1x_rst_o			,
+	                           
+	CM_FIFO_1x_almost_full_i	,
+	CM_FIFO_1x_almost_empty_i	,
+	CM_FIFO_1x_push_flag_i		,
+	CM_FIFO_1x_pop_flag_i		,
+	CM_FIFO_1x_dout_i			
+	
+	
+);
+
+input			rst;
+
+input			push_clk;
+input			push;
+input	[17:0]	din;
+output			full;
+output	[3:0]	push_flag;
+output			overflow;
+
+input			pop_clk;
+input			pop;
+output	[8:0]	dout;
+output			empty;
+output	[3:0]	pop_flag;
+
+output 	[17:0]	CM_FIFO_1x_din_o			;
+output 			CM_FIFO_1x_push_int_o		;
+output 			CM_FIFO_1x_pop_int_o		;
+output 			CM_FIFO_1x_push_clk_o		;
+output 			CM_FIFO_1x_pop_clk_o		;
+output 			CM_FIFO_1x_rst_o			;
+
+input 			CM_FIFO_1x_almost_full_i	;
+input 			CM_FIFO_1x_almost_empty_i	;
+input 	[3:0]	CM_FIFO_1x_push_flag_i		;
+input 	[3:0]	CM_FIFO_1x_pop_flag_i		;
+input 	[8:0]	CM_FIFO_1x_dout_i			;
+
+
+
+reg				overflow;
+
+
+wire			push_int;
+wire			pop_int;
+reg				pop_r1, pop_r2, pop_r3;
+
+
+// over-run/under-run protection
+assign push_int = full ? 1'b0 : push;
+
+// changed to match the current S2 functionality
+//assign pop_int = empty ? 1'b0 : pop;
+assign pop_int = empty ? 1'b0 : (pop_r2 ^ pop_r3);
+
+
+assign CM_FIFO_1x_din_o 		= din;
+assign CM_FIFO_1x_push_int_o 	= push_int;
+assign CM_FIFO_1x_pop_int_o 	= pop_int;
+assign CM_FIFO_1x_push_clk_o 	= push_clk;
+assign CM_FIFO_1x_pop_clk_o 	= pop_clk;
+assign CM_FIFO_1x_rst_o 		= rst;
+assign almost_full 				= CM_FIFO_1x_almost_full_i;
+assign almost_empty 			= CM_FIFO_1x_almost_empty_i;
+assign push_flag 				= CM_FIFO_1x_push_flag_i;
+assign pop_flag 				= CM_FIFO_1x_pop_flag_i;
+assign dout 					= CM_FIFO_1x_dout_i;
+
+
+
+
+assign full = (push_flag == 4'h0);
+assign empty = (pop_flag == 4'h0);
+
+
+// overflow detection
+always @(posedge push_clk or posedge rst)
+	if (rst)
+		overflow <= 0;
+	else
+		if (push && full)
+			overflow <= 1;
+		else
+			overflow <= 0;
+
+/// Synchronize SPI FIFO Read to SPI CLock due to delay
+always @(posedge pop_clk or posedge rst)
+	if (rst) begin
+		pop_r1 <= 1'b0;
+		pop_r2 <= 1'b0;
+		pop_r3 <= 1'b0;
+	end
+	else begin
+		pop_r1 <= pop;
+		pop_r2 <= pop_r1;
+		pop_r3 <= pop_r2;
+	end
+
+
+endmodule
+
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/CM_FIFO_autodrain.v b/BENCHMARK/ULPSH_fabric/rtl/src/CM_FIFO_autodrain.v
new file mode 100644
index 0000000..bb9558b
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/CM_FIFO_autodrain.v
@@ -0,0 +1,152 @@
+/*-----------------------------------------------------------------------------
+CM_FIFO_autodrain
+	This module will auto-drain (read from) the CM FIFO when RingBufferMode
+	is enabled. It will stop on packet boundaries (designated by bit 8 of
+	the FIFO data).
+-----------------------------------------------------------------------------*/
+
+
+`timescale 1ns / 10ps
+
+
+module CM_FIFO_autodrain (
+	input			rst,
+	input			FFE_CLK_gclk,
+	
+	input			RingBufferMode,
+	input	[3:0]	CM_FIFO_PushFlags,
+	input			CM_FIFO_Empty,
+	input			CM_FIFO_PopFromTLC,
+	input	[8:0]	CM_FIFO_ReadData,
+	
+	output			CM_FIFO_Pop,
+	output			busy,
+	output			TP1,
+	output			TP2
+);
+
+
+// state definitions
+localparam ST_IDLE		= 3'b000;
+localparam ST_SETBUSY1	= 3'b001;
+localparam ST_SETBUSY2	= 3'b010;
+localparam ST_WAIT		= 3'b011;
+localparam ST_READ		= 3'b100;
+
+
+wire			SOP_Marker;
+wire			FIFO_AutoRead_Threshold;
+reg				RingBufferMode_r1;
+reg				RingBufferMode_r2;
+reg		[2:0]	state;
+reg				busy_reg;
+reg				CM_FIFO_PopAutoDrain;
+
+
+assign SOP_Marker = CM_FIFO_ReadData[8];
+
+
+/*	PUSH_FLAG:
+	0x0: full
+	0x1: empty
+	0x2: room for 1/2 to (full - 1)
+	0x3: room for 1/4 to (1/2 -1)
+	0x4: room for 64 to (1/4 - 1)
+	0xA: room for 32 to 63
+	0xB: room for 16 to 31
+	0xC: room for 8 to 15
+	0xD: room for 4 to 7
+	0xE: room for 2 to 3
+	0xF: room for 1
+	others: reserved					*/
+
+assign FIFO_AutoRead_Threshold = ((CM_FIFO_PushFlags == 4'h0) || (CM_FIFO_PushFlags[3]));	// full or (63 or less) 16-bit words
+
+
+// sync RingBufferMode to the FFE clk
+always @(posedge rst or posedge FFE_CLK_gclk)
+	if (rst) begin
+		RingBufferMode_r1 <= 0;
+		RingBufferMode_r2 <= 0;
+	end
+		else begin
+			RingBufferMode_r1 <= RingBufferMode;
+			RingBufferMode_r2 <= RingBufferMode_r1;
+		end
+
+
+// state machine
+always @(posedge rst or posedge FFE_CLK_gclk)
+	if (rst)
+		state <= ST_IDLE;
+	else
+		case (state)
+			ST_IDLE:		if (RingBufferMode_r2)
+								state <= ST_SETBUSY1;
+							else
+								state <= ST_IDLE;
+			
+			ST_SETBUSY1:	state <= ST_SETBUSY2;					// allow time for the FIFO read clock to switch safely
+			
+			ST_SETBUSY2:	state <= ST_WAIT;
+
+			ST_WAIT:		if (!RingBufferMode_r2)
+								state <= ST_IDLE;
+							else
+								state <= ST_READ;
+			
+			ST_READ:		if (SOP_Marker && !RingBufferMode_r2)
+								state <= ST_SETBUSY1;				// goto ST_SETBUSY1 to allow time to switch to SPI_SCLK
+							else
+								state <= ST_READ;
+		endcase
+
+
+// busy
+wire	busy_reg_reset;
+assign busy_reg_reset = rst || !RingBufferMode;
+always @(posedge busy_reg_reset or posedge FFE_CLK_gclk)
+	if (busy_reg_reset)
+		busy_reg <= 0;
+	else
+		case (busy_reg)
+			1'b0:	if ((state == ST_IDLE) && (RingBufferMode_r2))
+						busy_reg <= 1;
+					else	
+						busy_reg <= 0;
+			1'b1:	if (((state == ST_SETBUSY1) && !RingBufferMode_r2) || (state == ST_IDLE))
+						busy_reg <= 0;
+					else	
+						busy_reg <= 1;
+		endcase
+
+
+
+// FIFO Read control
+always @(*)
+	if (state == ST_READ)											// pop only allowed in ST_READ state...
+		if (!CM_FIFO_Empty)											// ...and FIFO not empty
+			if (!SOP_Marker)												// if not on SOP marker, keep reading
+				CM_FIFO_PopAutoDrain <= 1;
+			else	// (SOP_Marker)
+				if (FIFO_AutoRead_Threshold && RingBufferMode_r2)			// if SOP marker, read next packet if FIFO is at or past threshold and RingBufferMode still on
+					CM_FIFO_PopAutoDrain <= 1;
+				else
+					CM_FIFO_PopAutoDrain <= 0;						// else pop=0
+		else	// (CM_FIFO_Empty)
+			CM_FIFO_PopAutoDrain <= 0;
+	else	// (state != ST_READ)
+		CM_FIFO_PopAutoDrain <= 0;
+
+
+assign CM_FIFO_Pop = busy_reg ? CM_FIFO_PopAutoDrain : CM_FIFO_PopFromTLC;
+
+assign busy = busy_reg;
+
+
+assign TP1 = FIFO_AutoRead_Threshold;
+assign TP2 = 0;
+
+
+endmodule
+
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/FFEControlMemory_4k.v b/BENCHMARK/ULPSH_fabric/rtl/src/FFEControlMemory_4k.v
new file mode 100644
index 0000000..2748b89
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/FFEControlMemory_4k.v
@@ -0,0 +1,291 @@
+
+// 4k deep CM
+// This module bypasses the FFEControlMememoryMux since the addressing of the individual RAM blocks
+// is not the same when coming from the TLC vs. FFE, and dynamic code updates must be supported for
+// the fabric RAM's.
+
+// Note: in order for this to work correctly, RdClk and WrClk must be the same (tied together externally).
+
+
+`timescale 1ns / 10ps
+
+`include "ulpsh_rtl_defines.v"
+
+module FFEControlMemory_4k (
+	// General Interface
+	input			ResetIn,
+	input			SPI_clk,
+	input			TLC_FFE_clk2x_muxed,		// already muxed based on UseFastClock from TLC
+
+	input			MemSelect_en,				// MemorySelect and enable from TLC
+	input	[2:0]	MemSelect,
+
+	input			FFE_clock_halfperiod,
+
+	input	[11:0]	Address_TLC,				// TLC address is used for both TLC reads and writes
+
+	input	[35:0]	MemoryMux_in,
+	output	[35:0]	MemoryMux_out,
+
+	//Read Interface
+	input	[11:0]	ReadAddress_FFE,
+	output	[35:0]	ReadData,
+	input			ReadEnable_TLC,
+	input			ReadEnable_FFE,
+
+	//Write Interface
+	input	[35:0]	WriteData_TLC,
+	input			WriteEnable_TLC,
+
+	// ASSP RAM interface - left bank
+	output			assp_lb_ram0_clk,
+    output	[8:0]	assp_lb_ram0_addr,
+    output	[35:0]	assp_lb_ram0_wr_data,
+    input	[35:0]	assp_lb_ram0_rd_data,
+    output			assp_lb_ram0_wr_en,
+    output			assp_lb_ram0_rd_en,
+    output	[3:0]	assp_lb_ram0_wr_be,
+
+	// ASSP RAM interface - right bank
+	output			assp_rb_ram1_clk,
+    output	[8:0]	assp_rb_ram1_addr,
+    output	[35:0]	assp_rb_ram1_wr_data,
+    input	[35:0]	assp_rb_ram1_rd_data,
+    output			assp_rb_ram1_wr_en,
+    output			assp_rb_ram1_rd_en,
+    output	[3:0]	assp_rb_ram1_wr_be,
+
+	// ASSP RAM interface - 8k - left bank
+	output			assp_lb_ram8k_clk,
+    output	[11:0]	assp_lb_ram8k_addr,
+    output	[16:0]	assp_lb_ram8k_wr_data,
+    input	[16:0]	assp_lb_ram8k_rd_data,
+    output			assp_lb_ram8k_wr_en,
+    output			assp_lb_ram8k_rd_en,
+    output	[1:0]	assp_lb_ram8k_wr_be,
+	
+	//AP2
+	output  [8:0]   FFEControlMemory_4k_Address_TLC_o      ,		
+	output  [8:0]  	FFEControlMemory_4k_ReadAddress_muxed_o ,
+	output    		FFEControlMemory_4k_ram5_wr_en_o,  			
+	output    		FFEControlMemory_4k_ram5_rd_en_o,			
+	output    		FFEControlMemory_4k_SPI_clk_o, 				
+	output    		FFEControlMemory_4k_TLC_FFE_clk2x_muxed_o, 	
+	output  [35:0]  FFEControlMemory_4k_WriteData_TLC_o ,
+	input   [35:0]  FFEControlMemory_4k_ram5_rd_data_i	,
+	output    		FFEControlMemory_4k_ram4_wr_en_o	,	
+	output    		FFEControlMemory_4k_ram4_rd_en_o,
+	input  [35:0]  FFEControlMemory_4k_ram4_rd_data_i,
+	output [9:0]    FFEControlMemory_4k_fabric_ram1Kx9_addr_o,
+	output 			FFEControlMemory_4k_ram1_wr_en_o  ,		
+	output 			FFEControlMemory_4k_ram1_rd_en_o ,		
+	input  [8:0]    FFEControlMemory_4k_ram1_rd_data_i
+	
+	
+	
+);
+
+wire	[11:0]	ReadAddress_muxed;
+
+wire			Select_from_TLC;
+
+wire			ram0_wr_en;
+wire			ram1_wr_en;
+wire			ram2_wr_en;
+wire			ram3_wr_en;
+wire			ram4_wr_en;
+wire			ram5_wr_en;
+
+wire			ram0_rd_en;
+wire			ram1_rd_en;
+wire			ram2_rd_en;
+wire			ram3_rd_en;
+wire			ram4_rd_en;
+wire			ram5_rd_en;
+
+wire	[11:0]	assp_ram8k_addr;
+wire	[9:0]	fabric_ram1Kx9_addr;
+
+wire	[16:0]	ram0_rd_data;
+wire	[8:0]	ram1_rd_data;
+wire	[35:0]	ram2_rd_data;
+wire	[35:0]	ram3_rd_data;
+wire	[35:0]	ram4_rd_data;
+wire	[35:0]	ram5_rd_data;
+reg		[35:0]	lower2k_rd_data;
+reg		[16:0]	lower2k_rd_data_phase0, lower2k_rd_data_phase1;
+reg				ReadAddress_muxed_bit0_r1;
+
+reg		[2:0]	ram_rd_select;
+reg		[35:0]	ram_rd_data;
+wire	[8:0]	assp_ram_addr;
+
+
+// RAM blocks are arranged as follows:
+// RAM 0: 0-2k: 4Kx17 (double-clocked to create the lower 34 bits of each uInstruction)
+// RAM 1: 0-2k: 1024x9 (one-half of the 1024x9 word is used for the remaining 2 bits of each uInstruction)
+// RAM 2,3: 2k-3k: ASSP RAM's (formerly 0k-1k in the 2k CM)
+// RAM 4,5: 3k-4k: fabric RAM's (formerly 1k-2k in the 2k CM)
+
+
+assign Select_from_TLC = (MemSelect_en && (MemSelect == 3'h0 || MemSelect == 3'h4 || MemSelect == 3'h5));
+
+// memory mux to pass data back to TLC
+assign MemoryMux_out = Select_from_TLC ? ReadData : MemoryMux_in;
+
+
+// mux between the TLC and FFE control signals
+assign ReadAddress_muxed = Select_from_TLC ? Address_TLC : ReadAddress_FFE;
+assign ReadEnable_muxed = Select_from_TLC ? ReadEnable_TLC : ReadEnable_FFE;
+
+
+// generate the read address for the 4Kx17 ASSP RAM
+assign assp_ram8k_addr = Select_from_TLC ? Address_TLC : {ReadAddress_FFE[10:0], FFE_clock_halfperiod};
+
+/// generate the read address for the 1Kx9 fabric RAM
+assign fabric_ram1Kx9_addr = Select_from_TLC ? Address_TLC : ReadAddress_FFE[10:1];
+
+// write enables for each RAM block
+//		note: fabric RAM's cannot use MemSelect_en since these RAM's may be updated during run-time.
+assign ram0_wr_en = (MemSelect_en && MemSelect == 3'h4 && WriteEnable_TLC);
+assign ram1_wr_en = (MemSelect_en && MemSelect == 3'h5 && WriteEnable_TLC);
+assign ram2_wr_en = (MemSelect_en && MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b00);
+assign ram3_wr_en = (MemSelect_en && MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b01);
+assign ram4_wr_en = (                MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b10);
+assign ram5_wr_en = (                MemSelect == 3'h0 && WriteEnable_TLC && Address_TLC[10:9] == 2'b11);
+
+// read enables for each RAM block
+assign ram0_rd_en = (MemSelect_en && MemSelect == 3'h4) ? ReadEnable_TLC : (ReadEnable_FFE && ReadAddress_FFE[11] == 1'b0);
+assign ram1_rd_en = (MemSelect_en && MemSelect == 3'h5) ? ReadEnable_TLC : (ReadEnable_FFE && ReadAddress_FFE[11] == 1'b0 && FFE_clock_halfperiod);
+assign ram2_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b00) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b100 && FFE_clock_halfperiod);
+assign ram3_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b01) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b101 && FFE_clock_halfperiod);
+assign ram4_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b10) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b110 && FFE_clock_halfperiod);
+assign ram5_rd_en = (MemSelect_en && MemSelect == 3'h0) ? (ReadEnable_TLC && Address_TLC[10:9] == 2'b11) : (ReadEnable_FFE && FFE_clock_halfperiod && ReadAddress_FFE[11:9] == 3'b111 && FFE_clock_halfperiod);
+
+
+// RAM 5 (fabric)
+assign FFEControlMemory_4k_Address_TLC_o[8:0] 			= Address_TLC[8:0];
+assign FFEControlMemory_4k_ReadAddress_muxed_o[8:0] 	= ReadAddress_muxed[8:0];
+assign FFEControlMemory_4k_ram5_wr_en_o  				= ram5_wr_en ;
+assign FFEControlMemory_4k_ram5_rd_en_o 				= ram5_rd_en;
+assign FFEControlMemory_4k_SPI_clk_o 					= SPI_clk;
+assign FFEControlMemory_4k_TLC_FFE_clk2x_muxed_o 		= TLC_FFE_clk2x_muxed;
+assign FFEControlMemory_4k_WriteData_TLC_o 				= WriteData_TLC;
+assign ram5_rd_data 									= FFEControlMemory_4k_ram5_rd_data_i;
+
+
+assign FFEControlMemory_4k_ram4_wr_en_o  				= ram4_wr_en ;
+assign FFEControlMemory_4k_ram4_rd_en_o 				= ram4_rd_en;
+assign ram4_rd_data 									= FFEControlMemory_4k_ram4_rd_data_i;
+
+
+// mappings to the ASSP RAM's
+
+assign assp_ram_addr = (MemSelect_en && MemSelect == 3'h0) ? Address_TLC[8:0] : ReadAddress_muxed[8:0];
+
+// RAM 3 (ASSP right bank)
+//		note: the port names are still called "ram1" to maintain compatibility with the 2k CM variant
+assign assp_rb_ram1_clk		= TLC_FFE_clk2x_muxed;
+assign assp_rb_ram1_addr	= assp_ram_addr;
+assign assp_rb_ram1_wr_data	= WriteData_TLC;
+assign ram3_rd_data			= assp_rb_ram1_rd_data;
+assign assp_rb_ram1_wr_en	= ram3_wr_en;
+assign assp_rb_ram1_rd_en	= ram3_rd_en;
+assign assp_rb_ram1_wr_be	= 4'b1111;
+
+// RAM 2 (ASSP left bank)
+//		note: the port names are still called "ram0" to maintain compatibility with the 2k CM variant
+assign assp_lb_ram0_clk		= TLC_FFE_clk2x_muxed;
+assign assp_lb_ram0_addr	= assp_ram_addr;
+assign assp_lb_ram0_wr_data	= WriteData_TLC;
+assign ram2_rd_data			= assp_lb_ram0_rd_data;
+assign assp_lb_ram0_wr_en	= ram2_wr_en;
+assign assp_lb_ram0_rd_en	= ram2_rd_en;
+assign assp_lb_ram0_wr_be	= 4'b1111;
+
+assign FFEControlMemory_4k_fabric_ram1Kx9_addr_o		= fabric_ram1Kx9_addr;
+assign FFEControlMemory_4k_ram1_wr_en_o  				= ram1_wr_en ;
+assign FFEControlMemory_4k_ram1_rd_en_o 				= ram1_rd_en;
+assign FFEControlMemory_4k_SPI_clk_o 					= SPI_clk;
+assign ram1_rd_data 									= FFEControlMemory_4k_ram1_rd_data_i;
+
+
+// RAM 0 (ASSP 8k left bank)
+assign assp_lb_ram8k_clk		= TLC_FFE_clk2x_muxed;
+assign assp_lb_ram8k_addr		= assp_ram8k_addr;
+assign assp_lb_ram8k_wr_data	= WriteData_TLC;
+assign ram0_rd_data				= assp_lb_ram8k_rd_data;
+assign assp_lb_ram8k_wr_en		= ram0_wr_en;
+assign assp_lb_ram8k_rd_en		= ram0_rd_en;
+assign assp_lb_ram8k_wr_be		= 2'b11;
+
+
+// latch the 4Kx17 read data
+always @(posedge TLC_FFE_clk2x_muxed) begin
+	if (FFE_clock_halfperiod)
+		lower2k_rd_data_phase0 <= ram0_rd_data;
+	if (!FFE_clock_halfperiod)
+		lower2k_rd_data_phase1 <= ram0_rd_data;
+	if (FFE_clock_halfperiod)
+		ReadAddress_muxed_bit0_r1 <= ReadAddress_muxed[0];
+end
+
+// assemble the read data for the lower 2k (ram0/ram1)
+always @(*)
+	if (FFE_clock_halfperiod == 0)
+		if (ReadAddress_muxed_bit0_r1 == 0)
+			lower2k_rd_data <= {ram1_rd_data[1:0], ram0_rd_data[16:0], lower2k_rd_data_phase0[16:0]};
+		else
+			lower2k_rd_data <= {ram1_rd_data[3:2], ram0_rd_data[16:0], lower2k_rd_data_phase0[16:0]};
+	else
+		if (ReadAddress_muxed_bit0_r1 == 0)
+			lower2k_rd_data <= {ram1_rd_data[1:0], lower2k_rd_data_phase1[16:0], lower2k_rd_data_phase0[16:0]};
+		else
+			lower2k_rd_data <= {ram1_rd_data[3:2], lower2k_rd_data_phase1[16:0], lower2k_rd_data_phase0[16:0]};
+
+
+
+// mux the read data from each RAM block, for the FFE
+always @(posedge TLC_FFE_clk2x_muxed)
+	if (FFE_clock_halfperiod)
+		ram_rd_select <= ReadAddress_muxed[11:9];
+
+always @(*)
+	if (MemSelect_en)
+		// TLC is reading
+		if (MemSelect == 3'h0)
+			case (ram_rd_select[1:0])
+				2'b00:	ram_rd_data <= ram2_rd_data;
+				2'b01:	ram_rd_data <= ram3_rd_data;
+				2'b10:	ram_rd_data <= ram4_rd_data;
+				2'b11:	ram_rd_data <= ram5_rd_data;
+			endcase
+		else
+			if (MemSelect == 3'h4)
+				ram_rd_data <= ram0_rd_data;
+			else
+				// assume select=5 to reduce logic
+
+				//if (MemSelect == 3'h5)
+					ram_rd_data <= ram1_rd_data;
+				//else
+				//	ram_rd_data <= 0;
+	else
+		// FFE is reading
+		if (ram_rd_select[2])
+			// upper 2k
+			case(ram_rd_select[1:0])
+				2'b00:	ram_rd_data <= ram2_rd_data;
+				2'b01:	ram_rd_data <= ram3_rd_data;
+				2'b10:	ram_rd_data <= ram4_rd_data;
+				2'b11:	ram_rd_data <= ram5_rd_data;
+			endcase
+		else
+			// lower 2k
+			ram_rd_data <= lower2k_rd_data;
+
+assign ReadData = ram_rd_data;
+
+
+endmodule 
+
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/FFEDataMemoryMux.v b/BENCHMARK/ULPSH_fabric/rtl/src/FFEDataMemoryMux.v
new file mode 100644
index 0000000..0f59273
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/FFEDataMemoryMux.v
@@ -0,0 +1,38 @@
+`timescale 1ns / 10ps
+
+module FFEDataMemoryMux (
+	input		Select,
+	
+	input [9:0]		ReadAddressIn0,
+	input [9:0]		ReadAddressIn1,
+	output[9:0]		ReadAddressOut,
+	
+	input [9:0]		WriteAddressIn0,
+	input [9:0]		WriteAddressIn1,
+	output[9:0]		WriteAddressOut,
+	
+	input [35:0]	DataToMemoryIn0,
+	input [35:0]	DataToMemoryIn1,
+	output[35:0]	DataToMemoryOut,
+	
+	input [35:0]	DataFromMemoryIn0,
+	input [35:0]	DataFromMemoryIn1,
+	output[35:0]	DataFromMemoryOut,
+	
+	input			ReadEnable0,
+	input			ReadEnable1,
+	output			ReadEnable,
+	
+	input			WriteEnable0,
+	input			WriteEnable1,
+	output			WriteEnable
+	);
+	
+	assign ReadAddressOut = (Select) ? ReadAddressIn1 : ReadAddressIn0;
+	assign WriteAddressOut = (Select) ? WriteAddressIn1 : WriteAddressIn0;
+	assign DataToMemoryOut = (Select) ? DataToMemoryIn1 : DataToMemoryIn0;
+	assign DataFromMemoryOut = (Select) ? DataFromMemoryIn1 : DataFromMemoryIn0;
+	assign ReadEnable = (Select) ? ReadEnable1 : ReadEnable0;
+	assign WriteEnable = (Select) ? WriteEnable1 : WriteEnable0;
+
+endmodule
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/FFE_ALU.v b/BENCHMARK/ULPSH_fabric/rtl/src/FFE_ALU.v
new file mode 100644
index 0000000..5e5353b
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/FFE_ALU.v
@@ -0,0 +1,476 @@
+// -----------------------------------------------------------------------------
+// title          : FFE_ALU.v
+// project        : ULP Sensor Hub
+// description    : 32-bit ALU
+// -----------------------------------------------------------------------------
+// copyright (c) 2013, QuickLogic Corporation
+// -----------------------------------------------------------------------------
+// History        :
+// date            version    author         description
+//
+// -----------------------------------------------------------------------------
+// date            version    author         description
+// 10-31-2013	   1.1        Anthony Le	 Add AND function to code
+//	Details:
+//		1. Add new bus signal xT30 as 32-bit for output of AND function
+//		2. Assign a temporary 32bit bus to hold the concatenation of MailBox bit:
+//     			Mailbox32bit = {8'b0, MailBox[7:0], 16'h0};
+//	    3. Add code to perform AND function between Mailbox32bit and xT23
+//		4. Add mux function between xT30 and MailBox in using signal[38]
+//		5. Expected the Synthesis to remove all unused logics
+//
+// 11-29-2013	   1.2        Anthony Le	 Add additional comparison functions
+//	Details:
+//		1. Current system supports only three jump functions:
+//         a. JMP: jump
+//         b. JMPNEZ: jump when result is not equal to zero
+//         c. JMPGEZ: jump when result is greater or equal to zero
+//		2. Add four more compriason jump functions
+//         a. JMPEQZ: jump when result is equal to zero
+//         b. JMPLTZ: jump when result is less than zero
+//         c. JMPLEZ: jump when result is less than or equal to zero
+//         d. JMPGTZ: jump when result is greater than zero
+//	    3. Re-use the three control signals[19:17]
+//      4. Use an 8-to-1 mux for JUMP logic
+//      5. Update xJumpFlag from wire to reg type
+//
+//
+// -----------------------------------------------------------------------------
+
+`timescale 1ns / 10ps
+
+`include "ulpsh_rtl_defines.v"
+
+module FFE_ALU 	(	
+	input 		[31:0] 	xReadData1,
+	input 		[31:0] 	xReadData2,
+	input 		[63:0] 	signals,
+	input				ClockIn,
+	input				Clock_x2In,
+	input				FFE_clock_halfperiod,
+	input		[15:0]	TimeStampIn,
+	input		[31:0]	MailboxIn,
+	input		[3:0]	SM_InterruptIn,
+	input				MultClockIn,
+	input		[3:0]	MultStateIn,
+	output 		[8:0] 	xIndexRegister,
+	output 		[31:0] 	xWriteData,
+	output 	reg			xJumpFlag,
+	input 				Save_BG_registers,
+	input 				Restore_BG_registers,
+
+	output		[31:0]	mult_in1,
+	output		[31:0]	mult_in2,
+	output				mult_enable,
+	input		[63:0]	mult_out
+);
+ 
+
+wire		[31:0]	xT0, xT1, xT2;
+//wire		[31:0]	xT3;		// defined below, depending on the multiplier implementation
+wire		[31:0]	xT4;
+reg			[31:0]	xT5;
+wire		[31:0]	xT6, xT7, xT8, xT9;
+wire		[31:0]	xT10, xT11, xT12, xT13, xT14, xT15, xT16, xT17, xT18, xT19, xT20, xT21, xT22;
+reg			[31:0]	xT23;
+wire		[31:0]	xT24, xT25;
+wire		[8:0]	xT26, xT27, xT28;
+reg			[8:0]	xT29;
+wire		[31:0]	xT30;
+wire signed	[31:0]	xT12_signed;
+wire				f0;
+reg					f2, f5, f2_BG, f5_BG;
+wire				f3, f6;
+reg					f2_latched, f2_BG_latched;
+reg			[31:0]	xT5_latched;
+reg					f5_latched, f5_BG_latched;
+reg			[8:0]	xT29_latched;
+
+// compiler options, from rtl_defines.v
+// ENABLE_FFE_F0_EXTENDED_DM
+// ENABLE_FFE_F0_SINGLE_DM
+// ENABLE_FFE_F0_PROGRAMMABLE_SEG0_OFFSET
+// FFE_F0_SEG0_OFFSET  [value]
+
+// compiler directives related to CM size:
+// ENABLE_FFE_F0_CM_SIZE_2K
+// ENABLE_FFE_F0_CM_SIZE_4K
+// ENABLE_FFE_F0_CM_SIZE_3K	(future support if needed)
+
+
+
+// select the multiplier implementation
+`define ASSP_MULT
+
+`ifdef FullSingleCycle
+	wire	[63:0]	xT3;
+	wire	[63:0]	xT1extended, xT2extended;
+
+	assign xT1extended[63:0]	= { {32{xT1[31]}}, xT1[31:0] };
+	assign xT2extended[63:0]	= { {32{xT2[31]}}, xT2[31:0] };
+	assign xT3					= xT1extended * xT2extended;
+	assign xT4					= (xT3 >> 16);
+
+`elsif Handicapped
+	wire	[31:0]	xT3;
+	assign xT3	= xT1 + xT2;	// replace multiplier with adder
+	assign xT4	= xT3;
+
+`elsif MultiCycle
+	wire	[31:0]	xT3;
+	Multiplier Multiplier_1 (
+		.ClockIn	( MultClockIn	),
+		.StateIn	( MultStateIn	),
+		.Arg1In		( xT1			),
+		.Arg2In		( xT2			),
+		.ResultOut	( xT3			)
+	);
+	assign xT4	= xT3;
+
+`elsif ASSP_MULT
+	wire	[63:0]	xT3;
+
+	assign xT3 = mult_out;
+	assign xT4 = (xT3 >> 16);
+				
+`else
+	wire	[31:0]	xT3;
+
+	assign xT3 = 0;
+	assign xT4 = 0;
+
+`endif
+
+
+// drive the outputs for the ASSP multiplier
+assign mult_in1 = xT1;
+assign mult_in2 = xT2;
+assign mult_enable = signals[5];
+
+
+
+assign xT22			= signals[2] ? (xReadData1<<16) : xReadData1;
+
+always @(*)
+	case (signals[1:0])
+		2'b00:	xT23 <= xReadData2;
+		2'b01:	xT23 <= MailboxIn;
+		2'b10:	xT23 <= {TimeStampIn[15:0], 16'b0};
+		2'b11:	xT23 <= {7'b0, xT29[8:0], 16'b0};	// IndexReg
+	endcase
+
+assign xT24			= signals[3] ? {12'b0, SM_InterruptIn[3:0], 16'b0} : xT23;
+assign xT30			= xReadData1 & xT24;
+assign xT9			= signals[38] ? xT30 : xT24;
+assign xT21			= xReadData1 | xT24;
+assign xT25			= signals[39] ? xT21 : xT9;
+
+assign xT0			= signals[4] ? xT25 : xT22;
+
+assign xT12_signed	= xT12;
+// remove these muxes to save space
+//assign xT1	= signals[5] ? xT0 : xT1;		// this mux (latch) keeps the multiplier inputs stable, to save power
+//assign xT2	= signals[5] ? xT25 : xT2;		// this mux (latch) keeps the multiplier inputs stable, to save power
+assign xT1		= xT0;
+assign xT2		= xT25;
+
+assign xT7		= signals[5] ? xT4 : xT25;
+assign xT10		= signals[8] ? ~xT7 : xT7;
+assign xT11		= signals[8] ? 32'b1 : 32'b0;
+assign xT13		= signals[9] ? xT7 : xT10;
+assign xT6		= signals[6] ? xT22 : xT5;
+assign xT8		= signals[7] ? xT6 : 32'b0;
+assign xT12		= xT8 + xT10 + xT11;
+assign xT14		= (xT12_signed >>> 1);
+assign xT16		= signals[11] ? xT14 : xT12;
+assign xT19		= signals[12] ? xT16 : xT6;
+assign f0		= xT12[31];
+
+// Sign bit
+`ifndef ENABLE_FFE_F0_SINGLE_DM
+	// double DM, default behavior
+	
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		// 4k CM
+		always @(posedge Clock_x2In) begin
+			if (FFE_clock_halfperiod) begin
+				if (Restore_BG_registers)
+					f2 <= f2_BG;
+				else
+					f2 <= signals[10] ? f0 : f2;
+
+				if (Save_BG_registers)
+					f2_BG <= f2;
+				else
+					f2_BG <= f2_BG;
+			end
+		end
+
+	`else
+		// 2k CM
+		always @(posedge ClockIn) begin
+			if (Restore_BG_registers)
+				f2 <= f2_BG;
+			else
+				f2 <= signals[10] ? f0 : f2;
+
+			if (Save_BG_registers)
+				f2_BG <= f2;
+			else
+				f2_BG <= f2_BG;
+		end
+
+	`endif
+
+`else
+	// single DM
+
+	always @(posedge Clock_x2In) begin
+		if (!FFE_clock_halfperiod) begin
+			if (Restore_BG_registers)
+				f2_latched <= f2_BG;
+			else
+				f2_latched <= signals[10] ? f0 : f2;
+
+			if (Save_BG_registers)
+				f2_BG_latched <= f2;
+			else
+				f2_BG_latched <= f2_BG;
+		end
+	end
+
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		always @(posedge Clock_x2In) begin
+			if (FFE_clock_halfperiod) begin
+				f2 <= f2_latched;
+				f2_BG <= f2_BG_latched;
+			end
+		end
+	`else
+		always @(posedge ClockIn) begin
+			f2 <= f2_latched;
+			f2_BG <= f2_BG_latched;
+		end
+	`endif
+
+`endif
+
+
+assign f6		= signals[33] ? (f2) : (f0);
+assign f3		= signals[35] ? !f5 : f6;
+
+assign xT15		= (f3) ? xT13 : xT19;
+assign xT17		= signals[13] ? xT15 : xT16;
+assign xT18		= (xT17 << 1);
+assign xT20		= signals[14] ? xT18 : xT17;
+
+assign xWriteData	= xT20;
+
+// accumulator
+`ifndef ENABLE_FFE_F0_SINGLE_DM
+	// double DM, default behavior
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		always @(posedge Clock_x2In) begin
+			if (FFE_clock_halfperiod)
+				xT5 <= signals[16] ? xT20 : xT5;
+		end
+	`else
+		always @(posedge ClockIn) begin
+			xT5 <= signals[16] ? xT20 : xT5;
+		end
+	`endif
+`else
+	// single DM
+	always @(posedge Clock_x2In) begin
+		if (!FFE_clock_halfperiod)
+			xT5_latched <= signals[16] ? xT20 : xT5;
+	end
+
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		always @(posedge Clock_x2In)
+			if (FFE_clock_halfperiod)
+				xT5 <= xT5_latched;
+	`else
+		always @(posedge ClockIn)
+			xT5 <= xT5_latched;
+	`endif
+`endif
+
+
+// NEZ flag
+`ifndef ENABLE_FFE_F0_SINGLE_DM
+	// double DM, default behavior
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		always @(posedge Clock_x2In) begin
+			if (FFE_clock_halfperiod) begin
+				if (Restore_BG_registers)
+					f5 <= f5_BG;
+				else
+					f5 <= signals[15] ? f5 : (xT20 != 32'b0);
+
+				if (Save_BG_registers)
+					f5_BG <= f5;
+				else
+					f5_BG <= f5_BG;
+			end
+		end
+	`else
+		always @(posedge ClockIn) begin
+			if (Restore_BG_registers)
+				f5 <= f5_BG;
+			else
+				f5 <= signals[15] ? f5 : (xT20 != 32'b0);
+
+			if (Save_BG_registers)
+				f5_BG <= f5;
+			else
+				f5_BG <= f5_BG;
+		end
+	`endif
+`else
+	// single DM
+	always @(posedge Clock_x2In) begin
+		if (!FFE_clock_halfperiod) begin
+			if (Restore_BG_registers)
+				f5_latched <= f5_BG;
+				//f5_latched <= f5_BG_latched;
+			else
+				f5_latched <= signals[15] ? f5 : (xT20 != 32'b0);
+				//f5_latched <= signals[15] ? f5_latched : (xT20 != 32'b0);
+
+			if (Save_BG_registers)
+				f5_BG_latched <= f5;
+				//f5_BG_latched <= f5_latched;
+			else
+				f5_BG_latched <= f5_BG;
+				//f5_BG_latched <= f5_BG_latched;
+		end
+	end
+
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		always @(posedge Clock_x2In) begin
+			if (FFE_clock_halfperiod) begin
+				f5 <= f5_latched;
+				f5_BG <= f5_BG_latched;
+			end
+		end
+	`else
+		always @(posedge ClockIn) begin
+			f5 <= f5_latched;
+			f5_BG <= f5_BG_latched;
+		end
+	`endif
+`endif
+
+
+always @(*)
+begin
+	case ({signals[19], signals[18], signals[17]})
+		3'b000: xJumpFlag = 1'b0;			// no jump
+		3'b001: xJumpFlag = 1'b1;			// JMP			(unconditional jump)
+		3'b010: xJumpFlag = f5;				// JMPNEZ		(jump if NEZflag)
+		3'b011: xJumpFlag = !f5;			// JMPEQZ		(jump if !NEZflag)
+		3'b100: xJumpFlag = !f2;			// JMPGEZ		(jump if !SignBit)
+		3'b101: xJumpFlag = f2;				// JMPLTZ		(jump if SignBit)
+		3'b110: xJumpFlag = !(!f2 && f5);	// JMPLEZ		(jump if SignBit or !NEZflag)
+		3'b111: xJumpFlag = !f2 && f5;		// JMPGTZ		(jump if !SignBit and NEZflag)
+		default: xJumpFlag = 1'b0;
+	endcase
+end
+
+
+// Index register code
+assign xT26	= xT29 + 1;
+assign xT27	= signals[24] ? xT26 : 9'b0;
+assign xT28	= signals[26] ? xT20[24:16] : xT27;	// assign the integer portion of xT20, or xT27
+
+// Index Register
+`ifndef ENABLE_FFE_F0_SINGLE_DM
+	// double DM, default behavior
+
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		always @(posedge Clock_x2In) begin
+			if (FFE_clock_halfperiod) begin
+				if (signals[25])
+					xT29 <= xT28;
+				else
+					xT29 <= xT29;
+				end
+		end
+	`else
+		always @(posedge ClockIn) begin
+			if (signals[25])
+				xT29 <= xT28;
+			else
+				xT29 <= xT29;
+		end
+	`endif
+`else
+	// single DM
+
+	always @(posedge Clock_x2In) begin
+		if (!FFE_clock_halfperiod) begin
+			if (signals[25])
+				xT29_latched <= xT28;
+			else
+				xT29_latched <= xT29;
+		end
+	end
+
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		always @(posedge Clock_x2In)
+			if (FFE_clock_halfperiod)
+				xT29 <= xT29_latched;
+	`else
+		always @(posedge ClockIn)
+			xT29 <= xT29_latched;
+	`endif
+
+`endif
+
+assign xIndexRegister = xT29;
+
+
+// prevent logic duplication
+//pragma attribute xT0 preserve_driver true
+//pragma attribute xT1 preserve_driver true
+//pragma attribute xT2 preserve_driver true
+//pragma attribute xT3 preserve_driver true
+//pragma attribute xT4 preserve_driver true
+//pragma attribute xT5 preserve_driver true
+//pragma attribute xT6 preserve_driver true
+//pragma attribute xT7 preserve_driver true
+//pragma attribute xT8 preserve_driver true
+//pragma attribute xT9 preserve_driver true
+//pragma attribute xT10 preserve_driver true
+//pragma attribute xT11 preserve_driver true
+//pragma attribute xT12 preserve_driver true
+//pragma attribute xT13 preserve_driver true
+//pragma attribute xT14 preserve_driver true
+//pragma attribute xT15 preserve_driver true
+//pragma attribute xT16 preserve_driver true
+//pragma attribute xT17 preserve_driver true
+//pragma attribute xT18 preserve_driver true
+//pragma attribute xT19 preserve_driver true
+//pragma attribute xT20 preserve_driver true
+//pragma attribute xT20 preserve_driver true
+//pragma attribute xT21 preserve_driver true
+//pragma attribute xT22 preserve_driver true
+//pragma attribute xT23 preserve_driver true
+//pragma attribute xT24 preserve_driver true
+//pragma attribute xT25 preserve_driver true
+//pragma attribute xT26 preserve_driver true
+//pragma attribute xT27 preserve_driver true
+//pragma attribute xT28 preserve_driver true
+//pragma attribute xT29 preserve_driver true
+//pragma attribute xT30 preserve_driver true
+//pragma attribute xT12_signed preserve_driver true
+//pragma attribute f0 preserve_driver true
+//pragma attribute f2 preserve_driver true
+//pragma attribute f5 preserve_driver true
+//pragma attribute f3 preserve_driver true
+//pragma attribute f6 preserve_driver true
+
+
+endmodule
+
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/FFE_Control.v b/BENCHMARK/ULPSH_fabric/rtl/src/FFE_Control.v
new file mode 100644
index 0000000..21c5e56
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/FFE_Control.v
@@ -0,0 +1,964 @@
+/* -----------------------------------------------------------------------------
+ title     : FlexFusionEngine Control
+ project   : Jim-Bob Hardware Sensor Hub
+ -----------------------------------------------------------------------------
+ platform  : Alabama test chip
+ standard  : Verilog 2001
+ -----------------------------------------------------------------------------
+ description: Module for controlling the FlexFusionEngine
+ -----------------------------------------------------------------------------
+ copyright (c) 2013, QuickLogic Corporation
+ -----------------------------------------------------------------------------
+ History  :
+ Date         Version   Author       Description
+ 2013/03/21   1.0       Jason Lew    Created
+ 2013/05/02   1.1       Jason Lew    Migrated from FFEAT v21d
+ 2013/06/14   1.2       Randy O.     Corrected assignment to DataMemReadAddr's b/c it wasn't using IndexReg properly.
+                                     Corrected assignment to MemReadData's b/c it shouldn't use IndexReg.
+ 2013/06/26   1.3       Randy O.     Made the Signals bus 64 bits wide instead of 32, since it needs to be at least as wide as the one in microopdecodes.v
+ 2013/07/01   1.4       Randy O.     Cosmetic changes to improve readability.
+                                     Removed DataMem1WriteData_int & DataMem2WriteData_int since they were unused.
+ 2013/07/08   1.5       Randy O.     Added unit delays to aid in functional sim.
+ 2014/05/21   1.6       Glen  G.     Added ability to read/write expanded Sensor Manager Memory
+
+ -----------------------------------------------------------------------------
+ Comments: This solution is specifically for implementing into the Alabama
+           test chip. Verification will be done using the Jim-Bob Sensor Board
+------------------------------------------------------------------------------*/
+
+`include "ulpsh_rtl_defines.v"
+
+
+`timescale 1ns / 10ps
+
+module FFE_Control ( // named RunFlexFusionEngine in C source
+	input				ClockIn,
+	input				Clock_x2In,
+	input 				ResetIn,
+	input 				StartIn,
+	output				StartSMOut,
+	input		[15:0]	TimeStampIn,
+	input		[31:0]	MailboxIn,
+	input		[3:0]	SM_InterruptIn,
+	output		[11:0]	ControlMemAddressOut,
+	output	reg			ControlMemReadEnableOut,
+	output		[9:0]	SensorMemReadAddressOut,	// Expanded for Rel 0 on 6/18
+	output				SensorMemReadEnableOut,
+	output		[9:0]	SensorMemWriteAddressOut,	// New for Rel 0 on 6/18
+	output				SensorMemWriteEnableOut,	// New for Rel 0 on 6/18
+	input		[35:0]	ControlMemDataIn,
+	input		[35:0]	Mem1ReadData,
+	input		[35:0]	Mem2ReadData,
+	input		[17:0]	SensorMemReadDataIn,
+	input				SensorMemBusyIn,
+
+	output		[8:0]	SensorMemWriteDataOut,		// New for Rel 0 on 6/18
+	output 				BusyOut,
+	output 				DataMem1ReadEnable,
+	output 				DataMem2ReadEnable,
+	output 				DataMem1WriteEnable,
+	output 				DataMem2WriteEnable,
+	output 		[9:0] 	DataMem1ReadAddressOut,
+	output 		[9:0] 	DataMem1WriteAddressOut,
+	output 		[35:0] 	DataMem1WriteDataOut,
+	output 		[9:0] 	DataMem2ReadAddressOut,
+	output		[9:0] 	DataMem2WriteAddressOut,
+	output 		[35:0] 	DataMem2WriteDataOut,
+
+	output	reg			FFE_clock_halfperiod,
+
+	input				MultClockIn,
+	input		[3:0]	MultStateIn,
+		
+	// Status data
+	input				SMBusyIn,
+	output reg			SMOverrunOut,
+	
+	// CM FIFO controls
+	output		[17:0]	CMWriteDataOut,
+	output				CMWriteEnableOut,
+	
+	output		[7:0]	InterruptMsgOut,
+
+	// interface to ASSP multiplier
+	output		[31:0]	mult_in1,
+	output		[31:0]	mult_in2,
+	output				mult_enable,
+	input		[63:0]	mult_out,
+
+	
+	output				TP1,
+	output				TP2,
+	output				TP3
+);
+
+
+// compiler directives related to CM size:
+// ENABLE_FFE_F0_CM_SIZE_2K
+// ENABLE_FFE_F0_CM_SIZE_4K
+// ENABLE_FFE_F0_CM_SIZE_3K	(future support if needed)
+
+
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	// 4k CM
+	reg		[11:0]	xPC;
+	wire 	[11:0] 	xJumpAddress;
+	reg		[11:0]	PC_BG;
+`else
+	// 2k CM (3k CM support may be added in the future)
+	reg		[10:0]	xPC;
+	wire 	[10:0] 	xJumpAddress;
+	reg		[10:0]	PC_BG;
+`endif
+
+
+reg 			BusyOut_reg, BusyOut_r1;
+
+reg 			Start_r1, Start_r2, Start_r3;
+wire	[31:0] 	Mem1ReadDataToALU;
+wire 	[31:0] 	Mem2ReadDataToALU;
+wire 	[8:0] 	MicroOpCode;
+wire	[63:0] 	Signals;		// the width of Signals is defined to be way larger than it needs to be (today), extra bits should get optimized out.
+wire	[8:0] 	xIndexRegister;
+wire 	[31:0] 	xWriteData;
+wire 			xJumpFlag;
+wire 	[35:0] 	Mem1ReadDataX;
+wire 	[35:0] 	Mem2ReadDataX;
+
+reg		[7:0]	InterruptMsg_reg;
+reg				StartSM_reg;
+
+reg		[15:0]	TimeStamp_r1, TimeStamp_r2, TimeStamp_synced;
+
+
+reg				f5_BG;
+reg				f2_BG;
+reg				BGcontinue_pending;
+reg				BGsave_pending;
+reg				BGstop_pending;
+reg				BG_active;
+reg				Start_pending;
+wire			Start_detected;
+wire			Save_BG_registers;
+wire			Restore_BG_registers;
+wire			Clear_PC;
+wire			Disable_DataMem_WrEn;
+
+reg			[2:0]	Thread_switch_cnt;
+parameter	[2:0]	THREAD_SWITCH_CNT_DONE = 3'b111;
+
+
+// standard-depth DM addresses (9 bits)
+wire 		[8:0] 	DataMem1ReadAddressOut_std;
+wire 		[8:0] 	DataMem1WriteAddressOut_std;
+wire 		[8:0] 	DataMem2ReadAddressOut_std;
+wire		[8:0] 	DataMem2WriteAddressOut_std;
+
+wire		[9:0]	DataMem1WriteAddressOut_trans;
+wire		[9:0]	DataMem2WriteAddressOut_trans;
+wire		[9:0]	DataMem1ReadAddressOut_trans;
+wire		[9:0]	DataMem2ReadAddressOut_trans;
+reg			[9:0]	DataMem2ReadAddressOut_trans_hold;
+reg					DataMem1ReadAddressOut_trans_MSB_r1;
+
+wire		[9:0]	DataMem1WriteAddressOut_mux;
+wire		[9:0]	DataMem1ReadAddressOut_mux;
+
+wire				DataMem1ReadEnable_mux;
+wire				DataMem1WriteEnable_mux;
+
+wire		[9:0]	DataMem1WriteAddressOut_split;
+wire		[9:0]	DataMem2WriteAddressOut_split;
+wire		[9:0]	DataMem1ReadAddressOut_split;
+wire		[9:0]	DataMem2ReadAddressOut_split;
+
+wire				DataMem1ReadEnable_split;
+wire				DataMem1WriteEnable_split;
+wire				DataMem2ReadEnable_split;
+wire				DataMem2WriteEnable_split;
+
+//reg				FFE_clock_halfperiod;
+
+wire				DataMem1ReadEnable_std;
+wire				DataMem2ReadEnable_std;
+reg					DataMem2ReadEnable_std_hold;
+wire				DataMem1WriteEnable_std;
+wire				DataMem2WriteEnable_std;
+
+reg			[31:0]	Mem1ReadData_latched;
+reg			[31:0]	Mem2ReadData_latched;
+
+wire				ClockIn_dly1;
+wire				ClockIn_dly2;
+wire				ClockIn_dly3;
+
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	reg				SensorMemReadEnable_reg;
+	reg				SensorMemWriteEnable_reg;
+	reg	[9:0]		SensorMemReadAddress_reg;
+	reg	[9:0]		SensorMemWriteAddress_reg;
+	reg				CMWriteEnable_reg;
+`endif
+
+// compiler options, from rtl_defines.v
+// ENABLE_FFE_F0_EXTENDED_DM
+// ENABLE_FFE_F0_SINGLE_DM
+// ENABLE_FFE_F0_PROGRAMMABLE_SEG0_OFFSET
+// FFE_F0_SEG0_OFFSET  [value]
+
+`ifdef FFE_F0_SEG0_OFFSET
+	parameter	[8:0]	Segment0_offset = `FFE_F0_SEG0_OFFSET;
+`endif
+
+`ifdef ENABLE_FFE_F0_EXTENDED_DM
+	reg			[9:0]	CurrentSegment_offset;
+	reg					DataMem2ReadAddress_MSB_r1;
+`endif
+
+`ifdef ENABLE_FFE_F0_SINGLE_DM
+	reg			[31:16]	WriteData_latched;
+	reg			sig37_latched;
+`endif
+
+
+// sync the timestamp to this clock domain
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In) begin
+`else
+	always @(posedge ClockIn) begin
+`endif
+		TimeStamp_r1 <= TimeStampIn;
+		TimeStamp_r2 <= TimeStamp_r1;
+		if (TimeStamp_r1 == TimeStamp_r2)
+			TimeStamp_synced <= TimeStamp_r2;
+		else
+			TimeStamp_synced <= TimeStamp_synced;
+	end
+
+
+FFE_ALU u_FFE_ALU (
+	.xReadData1				( Mem1ReadDataToALU[31:0]	),
+	.xReadData2				( Mem2ReadDataToALU[31:0]	),
+	.signals				( Signals					),
+	.ClockIn				( ClockIn					),
+	.Clock_x2In				( Clock_x2In				),
+	.FFE_clock_halfperiod	( FFE_clock_halfperiod		),
+	.MultClockIn			( MultClockIn				),
+	.MultStateIn			( MultStateIn				),
+	.TimeStampIn			( TimeStamp_synced			),
+	.MailboxIn				( MailboxIn					),
+	.SM_InterruptIn			( SM_InterruptIn			),
+	.xIndexRegister			( xIndexRegister			),
+	.xWriteData				( xWriteData				),
+	.xJumpFlag				( xJumpFlag					),
+	.Save_BG_registers		( Save_BG_registers			),
+	.Restore_BG_registers	( Restore_BG_registers		),
+
+	.mult_in1				( mult_in1					),
+	.mult_in2				( mult_in2					),
+	.mult_enable			( mult_enable				),
+	.mult_out				( mult_out					)
+ );
+
+decodeMicroOpCode U_decodeMicroOpCode (
+	.MicroOpCode		( MicroOpCode				),
+	.Signals			( Signals					)
+);
+
+// Fetch Micro OpCode from Control Memory
+//  then needs to be decoded for the various control signals to the ALU (these are called 'signals')
+assign MicroOpCode = BusyOut_reg ? ControlMemDataIn[8:0] : 9'b0;   // xMicroOpCode (hold at zero if FFE is not running because of single port ASSP RAMs
+
+
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	// 4k CM
+	assign xJumpAddress = ControlMemDataIn[20:9];
+`else
+	// 2k CM
+	assign xJumpAddress = ControlMemDataIn[19:9];
+`endif
+
+
+// standard (legacy) control/address signals for the DM's
+
+assign DataMem1ReadEnable_std = Signals[20];
+assign DataMem2ReadEnable_std = Signals[21];
+assign DataMem1WriteEnable_std = Disable_DataMem_WrEn ? 1'b0 : (Signals[22] && BusyOut_reg);
+assign DataMem2WriteEnable_std = Disable_DataMem_WrEn ? 1'b0 : (Signals[23] && BusyOut_reg);
+
+assign DataMem1WriteAddressOut_std = Signals[34] ? (ControlMemDataIn[17:9] + xIndexRegister) : ControlMemDataIn[17:9];
+assign DataMem2WriteAddressOut_std = Signals[34] ? (ControlMemDataIn[17:9] + xIndexRegister) : ControlMemDataIn[17:9];
+assign DataMem1ReadAddressOut_std = Signals[28] ? (ControlMemDataIn[26:18] + xIndexRegister) : ControlMemDataIn[26:18];
+assign DataMem2ReadAddressOut_std = Signals[29] ? (ControlMemDataIn[35:27] + xIndexRegister) : ControlMemDataIn[35:27];
+
+
+// translate DM read/write addresses if an extended-length DM is specified
+`ifdef ENABLE_FFE_F0_EXTENDED_DM
+	// extended-length DM
+
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		always @(posedge Clock_x2In or posedge ResetIn)
+			if (ResetIn)
+				CurrentSegment_offset <= 0;
+			else
+				if (Signals[44] && FFE_clock_halfperiod)	// seg_offset being written
+					CurrentSegment_offset <= ControlMemDataIn[32:23];
+	`else
+		always @(posedge ClockIn or posedge ResetIn)
+			if (ResetIn)
+				CurrentSegment_offset <= 0;
+			else
+				if (Signals[44])	// seg_offset being written
+					CurrentSegment_offset <= ControlMemDataIn[32:23];
+	`endif
+
+	// translate addresses to handle extended data memory(ies)
+	assign DataMem1WriteAddressOut_trans = (DataMem1WriteAddressOut_std < Segment0_offset) ?
+												{1'b0, DataMem1WriteAddressOut_std[8:0]} :
+												({1'b0, DataMem1WriteAddressOut_std} + {1'b0, CurrentSegment_offset});
+	assign DataMem2WriteAddressOut_trans = (DataMem2WriteAddressOut_std < Segment0_offset) ?
+												{1'b0, DataMem2WriteAddressOut_std[8:0]} :
+												({1'b0, DataMem2WriteAddressOut_std} + {1'b0, CurrentSegment_offset});
+	assign DataMem1ReadAddressOut_trans = (DataMem1ReadAddressOut_std < Segment0_offset) ?
+												{1'b0, DataMem1ReadAddressOut_std[8:0]} :
+												({1'b0, DataMem1ReadAddressOut_std} + {1'b0, CurrentSegment_offset});
+	assign DataMem2ReadAddressOut_trans = (DataMem2ReadAddressOut_std < Segment0_offset) ?
+												{1'b0, DataMem2ReadAddressOut_std[8:0]} :
+												({1'b0, DataMem2ReadAddressOut_std} + {1'b0, CurrentSegment_offset});
+
+`else
+	// standard-length DM (could be single or double)
+
+	assign DataMem1WriteAddressOut_trans = {1'b0, DataMem1WriteAddressOut_std};
+	assign DataMem2WriteAddressOut_trans = {1'b0, DataMem2WriteAddressOut_std};
+	assign DataMem1ReadAddressOut_trans = {1'b0, DataMem1ReadAddressOut_std};
+	assign DataMem2ReadAddressOut_trans = {1'b0, DataMem2ReadAddressOut_std};
+
+`endif
+
+
+// mux the DM1/DM2 addresses into a single logical DM1 address if a single-DM design is specified
+`ifdef ENABLE_FFE_F0_SINGLE_DM
+	// single DM
+
+	// keep track of the half-period (0 or 1) within a single FFE clock, by using the 2x FFE clock.
+	// FFE_clock_halfperiod should be 0 when the 1x clock is low, 1 when the 1x clock is high (it's registered here to help eliminate timing issues).
+	buff buff_clockin_dly1 (.A(ClockIn), .Q(ClockIn_dly1));
+	buff buff_clockin_dly2 (.A(ClockIn_dly1), .Q(ClockIn_dly2));
+	buff buff_clockin_dly3 (.A(ClockIn_dly2), .Q(ClockIn_dly3));
+	//pragma attribute buff_clockin_dly1 dont_touch true
+	//pragma attribute buff_clockin_dly2 dont_touch true
+	//pragma attribute buff_clockin_dly3 dont_touch true
+	assign #3 ClockIn_dly4 = ClockIn_dly3;
+	always @(posedge Clock_x2In or posedge ResetIn)
+		if (ResetIn)
+			FFE_clock_halfperiod <= 0;
+		else
+			FFE_clock_halfperiod <= #1 ClockIn_dly4;
+			/*
+			if (BusyOut_reg)
+				FFE_clock_halfperiod <= !FFE_clock_halfperiod;
+			else
+				FFE_clock_halfperiod <= 0;
+			*/
+
+	always @(posedge Clock_x2In or posedge ResetIn)
+		if (ResetIn) begin
+			DataMem2ReadAddressOut_trans_hold <= 0;
+			DataMem2ReadEnable_std_hold <= 0;
+		end
+		else begin
+			if (!FFE_clock_halfperiod) begin
+				DataMem2ReadAddressOut_trans_hold <= DataMem2ReadAddressOut_trans;
+				DataMem2ReadEnable_std_hold <= DataMem2ReadEnable_std;
+			end
+		end
+
+	// on half-period 0, drive the DM1 read address and read enable
+	// on half-period 1, drive the DM2 read address and read enable
+	// drive the write address on both half-periods, and the write enable on half-period 0
+	assign DataMem1ReadAddressOut_mux = FFE_clock_halfperiod ? DataMem2ReadAddressOut_trans_hold : DataMem1ReadAddressOut_trans;
+	assign DataMem1ReadEnable_mux = FFE_clock_halfperiod  ? DataMem2ReadEnable_std_hold : DataMem1ReadEnable_std;
+	assign DataMem1WriteAddressOut_mux = DataMem1WriteAddressOut_trans;	// note: DM1 write address = DM2 write address
+	assign DataMem1WriteEnable_mux = FFE_clock_halfperiod ? 0 : DataMem1WriteEnable_std;
+
+`else
+	// double DM
+
+	// FFE_clock_halfperiod should never be used in this case. Assign it to 0.
+	always @(*)
+		FFE_clock_halfperiod <= 0;
+`endif
+
+
+// split the muxed RAM control signals across both physical memories if an extended-depth DM is specified.
+// (if an extended-depth DM is specified, it must also be a single DM)
+`ifdef ENABLE_FFE_F0_EXTENDED_DM
+	// extended-length DM
+	// note that the DM2 "_mux" signals are not defined, since it's assumed that an extended-length DM is also a single-DM
+
+	assign DataMem1ReadAddressOut_split = DataMem1ReadAddressOut_mux;
+	assign DataMem1ReadEnable_split = (DataMem1ReadAddressOut_mux[9] == 1'b0) ? DataMem1ReadEnable_mux : 1'b0;
+	assign DataMem1WriteAddressOut_split = DataMem1WriteAddressOut_mux;
+	// assign DataMem1WriteEnable_split = (DataMem1WriteAddressOut_mux[9] == 1'b0) ? DataMem1WriteEnable_split : 1'b0; // original
+	assign DataMem1WriteEnable_split = (DataMem1WriteAddressOut_mux[9] == 1'b0) ? DataMem1WriteEnable_mux : 1'b0;  // Anthony Le 11-01-2014
+
+	assign DataMem2ReadAddressOut_split = DataMem1ReadAddressOut_mux;
+	assign DataMem2ReadEnable_split = (DataMem1ReadAddressOut_mux[9] == 1'b1) ? DataMem1ReadEnable_mux : 1'b0;
+	assign DataMem2WriteAddressOut_split = DataMem1WriteAddressOut_mux;
+	// assign DataMem2WriteEnable_split = (DataMem1WriteAddressOut_mux[9] == 1'b1) ? DataMem1WriteEnable_split : 1'b0; // original
+	assign DataMem2WriteEnable_split = (DataMem1WriteAddressOut_mux[9] == 1'b1) ? DataMem1WriteEnable_mux : 1'b0; // Anthony Le 11-01-2014
+`endif
+
+
+// drive the outputs for the DM control/address
+`ifdef ENABLE_FFE_F0_EXTENDED_DM
+	// extended-length DM (must be single DM as well)
+
+	// must use the translated then muxed then split signals...
+
+	assign DataMem1ReadEnable = DataMem1ReadEnable_split;
+	assign DataMem1WriteEnable = DataMem1WriteEnable_split;
+	assign DataMem1WriteAddressOut = DataMem1WriteAddressOut_split;
+	assign DataMem1ReadAddressOut = DataMem1ReadAddressOut_split;
+
+	assign DataMem2ReadEnable = DataMem2ReadEnable_split;
+	assign DataMem2WriteEnable = DataMem2WriteEnable_split;
+	assign DataMem2WriteAddressOut = DataMem2WriteAddressOut_split;
+	assign DataMem2ReadAddressOut = DataMem2ReadAddressOut_split;
+
+`else
+	// standard-length DM
+
+	`ifdef ENABLE_FFE_F0_SINGLE_DM
+		// standard-length single DM
+
+		// must use the non-translated then muxed signals
+		// note that physical DM2 is unused, so those outputs are grounded.
+
+		assign DataMem1ReadEnable = DataMem1ReadEnable_mux;
+		assign DataMem1WriteEnable = DataMem1WriteEnable_mux;
+		assign DataMem1WriteAddressOut = DataMem1WriteAddressOut_mux;
+		assign DataMem1ReadAddressOut = DataMem1ReadAddressOut_mux;
+
+		assign DataMem2ReadEnable = 0;
+		assign DataMem2WriteEnable = 0;
+		assign DataMem2WriteAddressOut = 0;
+		assign DataMem2ReadAddressOut = 0;
+
+	`else
+		// standard-length double DM (legacy)
+
+		// use the standard signals
+
+		assign DataMem1WriteAddressOut = {1'b0, DataMem1WriteAddressOut_std};
+		assign DataMem2WriteAddressOut = {1'b0, DataMem2WriteAddressOut_std};
+		assign DataMem1ReadAddressOut = {1'b0, DataMem1ReadAddressOut_std};
+		assign DataMem2ReadAddressOut = {1'b0, DataMem2ReadAddressOut_std};
+
+		assign DataMem1ReadEnable = DataMem1ReadEnable_std;
+		assign DataMem2ReadEnable = DataMem2ReadEnable_std;
+		assign DataMem1WriteEnable = DataMem1WriteEnable_std;
+		assign DataMem2WriteEnable = DataMem2WriteEnable_std;
+
+	`endif
+
+`endif
+
+
+`ifdef ENABLE_FFE_F0_SINGLE_DM
+	// single DM, extended or standard length
+
+	// hold the write data so it can be written to the CM FIFO or SM Mem correctly, when a single DM is used
+	always @(posedge Clock_x2In or posedge ResetIn)
+		if (ResetIn) begin
+			WriteData_latched <= 0;
+			sig37_latched <= 0;
+		end
+		else begin
+			if (!FFE_clock_halfperiod) begin
+				sig37_latched <= Signals[37];
+				//if (!FFE_clock_halfperiod && (CMWriteEnableOut || SensorMemWriteEnableOut || Signals[36]))
+				if (Signals[30] || Signals[40] || Signals[36])	// CM write or SM write or Interrupt msg write
+					WriteData_latched <= xWriteData[31:16];
+			end
+		end
+
+	//assign CMWriteDataOut = {1'b0, WriteData_latched[31:24], Signals[37], WriteData_latched[23:16]};
+	assign CMWriteDataOut = {1'b0, WriteData_latched[31:24], sig37_latched, WriteData_latched[23:16]};
+	assign SensorMemWriteDataOut = WriteData_latched[24:16];
+
+`else
+	// double DM (legacy)
+	
+	assign CMWriteDataOut = {1'b0, xWriteData[31:24], Signals[37], xWriteData[23:16]};
+	assign SensorMemWriteDataOut = xWriteData[24:16];
+`endif
+
+
+
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	// 4k CM
+
+	// this is done to make sure that all of these signals are stable when the 1x clock occurs.
+	always @(posedge Clock_x2In or posedge ResetIn)
+		if (ResetIn) begin
+			SensorMemReadEnable_reg <= 0;
+			SensorMemWriteEnable_reg <= 0;
+			SensorMemReadAddress_reg <= 0;
+			SensorMemWriteAddress_reg <= 0;
+			CMWriteEnable_reg <= 0;
+		end
+		else begin
+			if (!FFE_clock_halfperiod ) begin
+				SensorMemReadEnable_reg <= DataMem1ReadEnable_std;
+				SensorMemWriteEnable_reg <= Disable_DataMem_WrEn ? 1'b0 : (Signals[40] && BusyOut_reg);
+				SensorMemReadAddress_reg <= Signals[28] ? (ControlMemDataIn[27:18] + xIndexRegister) : ControlMemDataIn[27:18];
+				SensorMemWriteAddress_reg <= Signals[34] ? (ControlMemDataIn[18:9] + xIndexRegister) : ControlMemDataIn[18:9];
+				CMWriteEnable_reg <= Disable_DataMem_WrEn ? 1'b0 : (Signals[30] && BusyOut_reg);	// Write enable to CM FIFO
+			end
+		end
+
+	assign SensorMemReadEnableOut = SensorMemReadEnable_reg;
+	assign SensorMemWriteEnableOut = SensorMemWriteEnable_reg;
+	assign SensorMemReadAddressOut = SensorMemReadAddress_reg;
+	assign SensorMemWriteAddressOut = SensorMemWriteAddress_reg;
+	assign CMWriteEnableOut = CMWriteEnable_reg;
+
+`else
+	// 2k CM
+
+	assign SensorMemReadEnableOut = DataMem1ReadEnable_std;
+	assign SensorMemWriteEnableOut = Disable_DataMem_WrEn ? 1'b0 : (Signals[40] && BusyOut_reg);
+	assign SensorMemReadAddressOut = (Signals[28] ? (ControlMemDataIn[27:18] + xIndexRegister) : ControlMemDataIn[27:18]);
+	assign SensorMemWriteAddressOut = Signals[34] ? (ControlMemDataIn[18:9] + xIndexRegister) : ControlMemDataIn[18:9];
+
+	assign CMWriteEnableOut = Disable_DataMem_WrEn ? 1'b0 : (Signals[30] && BusyOut_reg);	// Write enable to CM FIFO
+`endif
+
+
+
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	// 4k CM
+	assign ControlMemAddressOut = xPC;
+`else
+	// 2k CM
+	assign ControlMemAddressOut = {1'b0, xPC};
+`endif
+
+assign DataMem1WriteDataOut = {4'b0000,xWriteData};
+assign DataMem2WriteDataOut = {4'b0000,xWriteData};
+
+
+
+// latch the read data from the DM(s)
+`ifdef ENABLE_FFE_F0_SINGLE_DM
+	`ifdef ENABLE_FFE_F0_EXTENDED_DM
+		// extended-length single-DM
+
+		always @(posedge Clock_x2In or posedge ResetIn)
+			if (ResetIn)
+				DataMem1ReadAddressOut_trans_MSB_r1 <= 0;
+			else
+				if (!FFE_clock_halfperiod)
+					DataMem1ReadAddressOut_trans_MSB_r1 <= DataMem1ReadAddressOut_trans[9];
+
+
+		always @(posedge Clock_x2In or posedge ResetIn)
+			if (ResetIn)
+				Mem1ReadData_latched <= 0;
+			else
+				if (FFE_clock_halfperiod)
+					Mem1ReadData_latched <= DataMem1ReadAddressOut_trans_MSB_r1 ? Mem2ReadData : Mem1ReadData;	// read from the correct physical DM
+
+		// store the (logical) DM2 read address' MSB, so it can be used on the following clock to select the correct physical DM
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		always @(posedge Clock_x2In or posedge ResetIn)
+			if (ResetIn)
+				DataMem2ReadAddress_MSB_r1 <= 0;
+			else
+				if (FFE_clock_halfperiod)
+					DataMem2ReadAddress_MSB_r1 <= DataMem2ReadAddressOut_trans[9];
+`else
+		always @(posedge ClockIn or posedge ResetIn)
+			if (ResetIn)
+				DataMem2ReadAddress_MSB_r1 <= 0;
+			else
+				DataMem2ReadAddress_MSB_r1 <= DataMem2ReadAddressOut_trans[9];
+`endif
+
+
+
+
+		always @(*)
+			Mem2ReadData_latched <= DataMem2ReadAddress_MSB_r1 ? Mem2ReadData : Mem1ReadData;			// read from the correct physical DM
+		// note that Mem2ReadData_latched will only be valid on the first half-period
+		// note that ReadData2 can be registered as well, to make FFE clock-to-clock timing easier (at the cost of more FFs).
+
+	`else
+		// standard-length single-DM, latch & hold at the appropriate half-periods
+		always @(posedge Clock_x2In or posedge ResetIn)
+			if (ResetIn)
+				Mem1ReadData_latched <= 0;
+			else
+				if (FFE_clock_halfperiod)
+					Mem1ReadData_latched <= Mem1ReadData;
+				else
+					Mem1ReadData_latched <= Mem1ReadData_latched;
+
+		always @(*)
+			Mem2ReadData_latched <= Mem1ReadData;
+		// note that ReadData2 can be registered as well, to make FFE clock-to-clock timing easier (at the cost of more FFs).
+	`endif
+
+`else
+	// standard-length double-DM, pass-thru
+	always @(*) begin
+		Mem1ReadData_latched <= Mem1ReadData;
+		Mem2ReadData_latched <= Mem2ReadData;
+	end
+`endif
+
+
+assign Mem1ReadDataX = Mem1ReadData_latched[31:0];
+//a mux that switches between data read from FFEDM2 or SMSM
+assign Mem2ReadDataX = Signals[27] ? {SensorMemReadDataIn[16:9], SensorMemReadDataIn[7:0], 16'b0} : Mem2ReadData_latched[31:0];
+
+
+assign Mem1ReadDataToALU = Mem1ReadDataX;
+assign Mem2ReadDataToALU = Mem2ReadDataX;
+
+
+
+
+// toggle StartSM each time Signals[31] is active
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In or posedge ResetIn)
+		if (ResetIn)
+			StartSM_reg <= 0;
+		else
+			if (FFE_clock_halfperiod && Signals[31])
+				StartSM_reg <= !StartSM_reg;
+			else
+				StartSM_reg <= StartSM_reg;
+				
+`else
+	always @(posedge ClockIn or posedge ResetIn)
+		if (ResetIn)
+			StartSM_reg <= 0;
+		else
+			if (Signals[31])
+				StartSM_reg <= !StartSM_reg;
+			else
+				StartSM_reg <= StartSM_reg;
+				
+`endif
+
+assign StartSMOut = StartSM_reg;
+
+
+// de-glitch the interrupt msg signal since it comes out of the decoder and data mem
+`ifdef ENABLE_FFE_F0_SINGLE_DM
+	// single DM
+
+	`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+		// 4k CM
+		always @(posedge Clock_x2In)
+			InterruptMsg_reg <= (FFE_clock_halfperiod && Signals[36]) ? WriteData_latched[23:16] : 8'b0;
+	`else
+		// 2k CM
+		always @(posedge ClockIn)
+			InterruptMsg_reg <= Signals[36] ? WriteData_latched[23:16] : 8'b0;
+	`endif
+
+`else
+	// double DM, legacy behavior
+	always @(posedge ClockIn)
+		InterruptMsg_reg <= Signals[36] ? xWriteData[23:16] : 8'b0;
+`endif
+
+assign InterruptMsgOut = InterruptMsg_reg;
+
+
+// sync to local clock
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In) begin
+`else
+	always @(posedge ClockIn) begin
+`endif
+		Start_r1 <= StartIn;
+		Start_r2 <= Start_r1;
+		Start_r3 <= Start_r2;
+	end
+
+assign Start_detected = (Start_r1 != Start_r2) || (Start_r2 != Start_r3);
+
+
+// Program Counter to step through the Control Memory
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In or posedge ResetIn) begin
+`else
+	always @(posedge ClockIn or posedge ResetIn) begin
+`endif
+
+		if (ResetIn) begin
+			xPC <= 0;
+			BusyOut_reg <= 1'b0;
+			BusyOut_r1 <= 1'b0;
+			ControlMemReadEnableOut <= 1'b0;
+			SMOverrunOut <= 1'b0;
+		end else
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+			if (FFE_clock_halfperiod)
+`endif
+			begin
+				BusyOut_r1 <= BusyOut_reg;
+				if (BusyOut_reg && BusyOut_r1) begin		// make sure the 1st control word appears on the RAM outputs... requires one clock cycle after the read enable is turned on.
+					if (!Signals[32]) begin					// !Signals[32] = continue running = !STOP
+						if (Restore_BG_registers)
+							xPC <= PC_BG;
+						else
+							if (Clear_PC)
+								xPC <= 0;
+							else
+								// hold the PC while switching threads
+								if (BG_active && 
+										((Start_detected || BGsave_pending) ||
+										(BGcontinue_pending && (Thread_switch_cnt != THREAD_SWITCH_CNT_DONE))))
+									xPC <= xPC;
+								else
+									if (xJumpFlag)
+										xPC <= xJumpAddress;
+									else
+										xPC <= xPC + 1;
+					end else begin	// Signals[32] = STOP
+						xPC <= 0;
+						if (!BG_active) begin					// FG mode
+							BusyOut_reg <= 1'b0;
+							ControlMemReadEnableOut <= 1'b0;
+						end else begin							// BG mode
+							ControlMemReadEnableOut <= 1'b1;
+							if (BGstop_pending && (Thread_switch_cnt == THREAD_SWITCH_CNT_DONE) && !Start_pending && !Start_detected)
+								BusyOut_reg <= 1'b0;
+							else
+								BusyOut_reg <= 1'b1;
+						end
+					end
+				end else		// new start condition not detected, keep running
+					if (Start_detected) begin
+						if (SMBusyIn) begin
+							SMOverrunOut <= 1'b1;
+						end else begin
+							BusyOut_reg <= 1'b1;
+							ControlMemReadEnableOut <= 1'b1;
+						end
+					end
+
+			end
+	end
+
+assign BusyOut = BusyOut_reg;
+
+
+
+// --- BG thread support
+
+// Signals[42] = SetBGflag (instruction modifier)
+// Signals[43] = BGcontinue (instruction)
+
+
+// Start_pending, flag to latch the start event, in case it happens right as we're switching to the BG thread or while running the BG thread.
+//		This needs to be latched so the FG thread can be started immediately once we've switched out of the BG thread.
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In or posedge ResetIn)
+`else
+	always @(posedge ClockIn or posedge ResetIn)
+`endif
+		if (ResetIn)
+			Start_pending <= 0;
+		else
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+			if (FFE_clock_halfperiod)
+`endif
+				case (Start_pending)
+					1'b0:	if (Start_detected &&			// start detected AND...
+									(Signals[42] ||			//	...SetBGflag active (about to start or continue BG)...OR...
+									BG_active))				//	...BG active (switching to BG, running BG, about to stop/end BG, stopping BG)
+								Start_pending <= 1;
+					1'b1:	if (!BG_active)					// clear this flag when BG_active goes away
+								Start_pending <= 0;
+				endcase
+
+
+// BG_pending counter, used instead of individual state machines for each type of context switch
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In or posedge ResetIn)
+`else
+	always @(posedge ClockIn or posedge ResetIn)
+`endif
+		if (ResetIn)
+			Thread_switch_cnt <= 0;
+		else
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+			if (FFE_clock_halfperiod)
+`endif
+				if (BGsave_pending || BGcontinue_pending || BGstop_pending)
+					if (Thread_switch_cnt == THREAD_SWITCH_CNT_DONE)
+						Thread_switch_cnt <= 0;
+					else
+						Thread_switch_cnt <= Thread_switch_cnt + 1;
+				else
+					Thread_switch_cnt <= 0;
+
+
+// BGcontinue_pending, flag that goes active while resuming the BG thread (BGcontinue instruction)
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In or posedge ResetIn)
+`else
+	always @(posedge ClockIn or posedge ResetIn)
+`endif
+		if (ResetIn)
+			BGcontinue_pending <= 0;
+		else
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+			if (FFE_clock_halfperiod)
+`endif
+				case (BGcontinue_pending)
+					1'b0:	if (Signals[43])
+								BGcontinue_pending <= 1;
+					1'b1:	if (Thread_switch_cnt == THREAD_SWITCH_CNT_DONE)
+								BGcontinue_pending <= 0;
+				endcase
+
+
+// BGsave_pending, flag that goes active while saving the state of the BG thread (BG_continue or BG thread interrupted by the sample timer)
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In or posedge ResetIn)
+`else
+	always @(posedge ClockIn or posedge ResetIn)
+`endif
+		if (ResetIn)
+			BGsave_pending <= 0;
+		else
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+			if (FFE_clock_halfperiod)
+`endif
+				case (BGsave_pending)
+					1'b0:	if (BG_active &&																					// in the BG thread...AND...
+									(Start_detected ||																			// 		...started detected...OR...
+									(BGcontinue_pending && (Thread_switch_cnt == THREAD_SWITCH_CNT_DONE) && Start_pending)))	// ...about to complete BGcontinue AND start was detected
+								BGsave_pending <= 1;
+					1'b1:	if (Thread_switch_cnt == THREAD_SWITCH_CNT_DONE)
+								BGsave_pending <= 0;
+				endcase
+
+
+// BGstop_pending, flag that goes active while stopping the BG thread (normal completion)
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In or posedge ResetIn)
+`else
+	always @(posedge ClockIn or posedge ResetIn)
+`endif
+		if (ResetIn)
+			BGstop_pending <= 0;
+		else
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+			if (FFE_clock_halfperiod)
+`endif
+				case (BGstop_pending)
+					1'b0:	if (BG_active && Signals[32])
+								BGstop_pending <= 1;
+					1'b1:	if (Thread_switch_cnt == THREAD_SWITCH_CNT_DONE)
+								BGstop_pending <= 0;
+				endcase
+
+
+
+// BG_active, flag that is active while switching to, in, or switching from, the BG thread
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In or posedge ResetIn)
+`else
+	always @(posedge ClockIn or posedge ResetIn)
+`endif
+		if (ResetIn)
+			BG_active <= 0;
+		else
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+			if (FFE_clock_halfperiod)
+`endif
+				case (BG_active)
+					1'b0:	if (Signals[42])									// SetBGactive (entering BG mode, either via start BG or continue BG)
+								BG_active <= 1;
+					1'b1:	if ((BGsave_pending || BGstop_pending) && (Thread_switch_cnt == THREAD_SWITCH_CNT_DONE))	// done switching out of BG mode
+								BG_active <= 0;
+				endcase
+
+
+// Control signal used to save the BG copy of the PC and ALU flags
+assign Save_BG_registers = (BGsave_pending && (Thread_switch_cnt == 1));
+	// clock-by-clock sequence of events:
+	// {BGsave_pending,Thread_switch_cnt}
+	//  0,0 - Start detected, last BG instruction, hold PC
+	//  1,0 - hold PC, disable DataMemWrEn
+	//  1,1 - hold PC, save PC & flags (Save_BG_registers active), disable DataMemWrEn
+	//  1,2 - clear PC, disable DataMemWrEn
+	//  1,3 - hold PC (driving into CodeMem), disable DataMemWrEn
+	//  1,4 - hold PC (CodeMem available, driving DataMem), disable DataMemWrEn
+	//  1,5 - hold PC (DataMem available), disable DataMemWrEn
+	//  1,6 - hold PC (extraneous), disable DataMemWrEn
+	//  1,7 - hold PC (extraneous), disable DataMemWrEn
+	//  0,0 - continue running normally (now in FG thread)
+
+// Control signal used to restore the BG state of the PC and ALU flags
+assign Restore_BG_registers = (BGcontinue_pending && (Thread_switch_cnt == 1));
+	// clock-by-clock sequence of events:
+	// {BGcontinue_pending,Thread_switch_cnt} - action(s)
+	//  0,0 - BGcontinue();
+	//  1,0 - NOP;, disable DataMemWrEn
+	//  1,1 - load PC & flags (Restore_BG_registers active), disable DataMemWrEn
+	//  1,2 - hold PC (driving into CodeMem), disable DataMemWrEn
+	//  1,3 - hold PC (CodeMem available, driving DataMem), disable DataMemWrEn
+	//  1,4 - hold PC (DataMem available), disable DataMemWrEn
+	//  1,5 - hold PC (extraneous), disable DataMemWrEn
+	//  1,6 - hold PC (extraneous), disable DataMemWrEn
+	//  1,7 - increment PC, disable DataMemWrEn
+	//  0,0 - continue running normally (now in BG thread)
+
+
+// Control signal used to reset the PC (during BGstop or BGsave)
+assign Clear_PC = ((BGsave_pending && (Thread_switch_cnt == 2)) || (BGstop_pending));
+
+// Control signal used to disable the FFE DataMem write enable, while resuming the BG thread
+assign Disable_DataMem_WrEn = (BGcontinue_pending);
+
+
+// BG copy of the PC
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	always @(posedge Clock_x2In or posedge ResetIn)
+`else
+	always @(posedge ClockIn or posedge ResetIn)
+`endif
+	if (ResetIn)
+		PC_BG <= 0;
+	else
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+			if (FFE_clock_halfperiod)
+`endif
+			if (Save_BG_registers)
+				PC_BG <= xPC;
+			else
+				PC_BG <= PC_BG;
+
+
+
+// test points
+assign TP1 = 0;
+assign TP2 = 0;
+assign TP3 = 0;
+
+
+endmodule
+
+
+
+
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/MicroOpCodesDecode.v b/BENCHMARK/ULPSH_fabric/rtl/src/MicroOpCodesDecode.v
new file mode 100644
index 0000000..c8b58df
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/MicroOpCodesDecode.v
@@ -0,0 +1,59 @@
+`timescale 1ns / 10ps
+// algorithm file = 'ulpsh_s2_main_JB4_BMI160_AK09911_PD.alg'
+// UlpshType = S2_1KDM
+
+module decodeMicroOpCode (MicroOpCode, Signals);
+
+	input	[8:0]	MicroOpCode;
+	output	[45:0]	Signals;
+	wire	[45:0]	Signals;
+
+	assign Signals[0] = (MicroOpCode == 9'h00e) || 0;
+	assign Signals[1] = (MicroOpCode == 9'h012) || (MicroOpCode == 9'h013) || 0;
+	assign Signals[2] = 0;
+	assign Signals[3] = 0;
+	assign Signals[4] = (MicroOpCode == 9'h038) || 0;
+	assign Signals[5] = (MicroOpCode == 9'h016) || (MicroOpCode == 9'h017) || (MicroOpCode == 9'h021) || (MicroOpCode == 9'h034) || (MicroOpCode == 9'h035) || (MicroOpCode == 9'h036) || (MicroOpCode == 9'h038) || (MicroOpCode == 9'h040) || (MicroOpCode == 9'h041) || (MicroOpCode == 9'h042) || (MicroOpCode == 9'h045) || (MicroOpCode == 9'h04a) || (MicroOpCode == 9'h04e) || (MicroOpCode == 9'h04f) || 0;
+	assign Signals[6] = (MicroOpCode == 9'h00a) || (MicroOpCode == 9'h014) || (MicroOpCode == 9'h020) || (MicroOpCode == 9'h024) || (MicroOpCode == 9'h026) || (MicroOpCode == 9'h027) || (MicroOpCode == 9'h028) || (MicroOpCode == 9'h02d) || (MicroOpCode == 9'h033) || (MicroOpCode == 9'h037) || (MicroOpCode == 9'h038) || (MicroOpCode == 9'h039) || (MicroOpCode == 9'h03e) || (MicroOpCode == 9'h03f) || (MicroOpCode == 9'h044) || (MicroOpCode == 9'h047) || (MicroOpCode == 9'h049) || (MicroOpCode == 9'h04b) || (MicroOpCode == 9'h04c) || (MicroOpCode == 9'h050) || 0;
+	assign Signals[7] = (MicroOpCode == 9'h00a) || (MicroOpCode == 9'h014) || (MicroOpCode == 9'h020) || (MicroOpCode == 9'h024) || (MicroOpCode == 9'h026) || (MicroOpCode == 9'h027) || (MicroOpCode == 9'h028) || (MicroOpCode == 9'h02d) || (MicroOpCode == 9'h033) || (MicroOpCode == 9'h035) || (MicroOpCode == 9'h036) || (MicroOpCode == 9'h037) || (MicroOpCode == 9'h038) || (MicroOpCode == 9'h039) || (MicroOpCode == 9'h03e) || (MicroOpCode == 9'h03f) || (MicroOpCode == 9'h044) || (MicroOpCode == 9'h049) || (MicroOpCode == 9'h04a) || (MicroOpCode == 9'h050) || 0;
+	assign Signals[8] = (MicroOpCode == 9'h00a) || (MicroOpCode == 9'h024) || (MicroOpCode == 9'h026) || (MicroOpCode == 9'h033) || (MicroOpCode == 9'h037) || (MicroOpCode == 9'h038) || (MicroOpCode == 9'h03b) || (MicroOpCode == 9'h03f) || (MicroOpCode == 9'h043) || (MicroOpCode == 9'h047) || (MicroOpCode == 9'h049) || (MicroOpCode == 9'h04a) || (MicroOpCode == 9'h04b) || (MicroOpCode == 9'h04c) || 0;
+	assign Signals[9] = (MicroOpCode == 9'h027) || (MicroOpCode == 9'h028) || (MicroOpCode == 9'h039) || (MicroOpCode == 9'h03b) || (MicroOpCode == 9'h03e) || (MicroOpCode == 9'h043) || (MicroOpCode == 9'h044) || (MicroOpCode == 9'h047) || (MicroOpCode == 9'h04b) || (MicroOpCode == 9'h04c) || 0;
+	assign Signals[10] = (MicroOpCode == 9'h007) || (MicroOpCode == 9'h008) || (MicroOpCode == 9'h009) || (MicroOpCode == 9'h00a) || (MicroOpCode == 9'h00d) || (MicroOpCode == 9'h00e) || (MicroOpCode == 9'h010) || (MicroOpCode == 9'h012) || (MicroOpCode == 9'h013) || (MicroOpCode == 9'h014) || (MicroOpCode == 9'h020) || (MicroOpCode == 9'h022) || (MicroOpCode == 9'h024) || (MicroOpCode == 9'h025) || (MicroOpCode == 9'h026) || (MicroOpCode == 9'h036) || (MicroOpCode == 9'h038) || (MicroOpCode == 9'h03a) || (MicroOpCode == 9'h03c) || (MicroOpCode == 9'h03d) || (MicroOpCode == 9'h03f) || (MicroOpCode == 9'h040) || (MicroOpCode == 9'h041) || (MicroOpCode == 9'h042) || (MicroOpCode == 9'h046) || (MicroOpCode == 9'h047) || (MicroOpCode == 9'h049) || (MicroOpCode == 9'h04a) || (MicroOpCode == 9'h04e) || (MicroOpCode == 9'h04f) || (MicroOpCode == 9'h050) || 0;
+	assign Signals[11] = (MicroOpCode == 9'h037) || (MicroOpCode == 9'h049) || 0;
+	assign Signals[12] = (MicroOpCode == 9'h03b) || (MicroOpCode == 9'h043) || (MicroOpCode == 9'h047) || (MicroOpCode == 9'h04b) || (MicroOpCode == 9'h04c) || 0;
+	assign Signals[13] = (MicroOpCode == 9'h027) || (MicroOpCode == 9'h028) || (MicroOpCode == 9'h039) || (MicroOpCode == 9'h03b) || (MicroOpCode == 9'h03e) || (MicroOpCode == 9'h043) || (MicroOpCode == 9'h044) || (MicroOpCode == 9'h047) || (MicroOpCode == 9'h04b) || (MicroOpCode == 9'h04c) || 0;
+	assign Signals[14] = 0;
+	assign Signals[15] = (MicroOpCode == 9'h038) || (MicroOpCode == 9'h039) || (MicroOpCode == 9'h04a) || 0;
+	assign Signals[16] = (MicroOpCode == 9'h034) || (MicroOpCode == 9'h035) || (MicroOpCode == 9'h048) || 0;
+	assign Signals[17] = (MicroOpCode == 9'h00f) || (MicroOpCode == 9'h011) || (MicroOpCode == 9'h015) || (MicroOpCode == 9'h01c) || (MicroOpCode == 9'h029) || 0;
+	assign Signals[18] = (MicroOpCode == 9'h00b) || (MicroOpCode == 9'h00f) || (MicroOpCode == 9'h01f) || (MicroOpCode == 9'h029) || 0;
+	assign Signals[19] = (MicroOpCode == 9'h015) || (MicroOpCode == 9'h01f) || (MicroOpCode == 9'h029) || (MicroOpCode == 9'h031) || 0;
+	assign Signals[20] = (MicroOpCode == 9'h001) || (MicroOpCode == 9'h002) || (MicroOpCode == 9'h009) || (MicroOpCode == 9'h00c) || (MicroOpCode == 9'h016) || (MicroOpCode == 9'h020) || (MicroOpCode == 9'h025) || (MicroOpCode == 9'h026) || (MicroOpCode == 9'h02c) || (MicroOpCode == 9'h02d) || (MicroOpCode == 9'h032) || (MicroOpCode == 9'h033) || (MicroOpCode == 9'h034) || (MicroOpCode == 9'h035) || (MicroOpCode == 9'h037) || (MicroOpCode == 9'h038) || (MicroOpCode == 9'h03c) || (MicroOpCode == 9'h03f) || (MicroOpCode == 9'h042) || (MicroOpCode == 9'h043) || (MicroOpCode == 9'h044) || (MicroOpCode == 9'h047) || (MicroOpCode == 9'h048) || (MicroOpCode == 9'h049) || (MicroOpCode == 9'h04a) || (MicroOpCode == 9'h04b) || (MicroOpCode == 9'h04d) || (MicroOpCode == 9'h04f) || 0;
+	assign Signals[21] = (MicroOpCode == 9'h004) || (MicroOpCode == 9'h008) || (MicroOpCode == 9'h009) || (MicroOpCode == 9'h00c) || (MicroOpCode == 9'h010) || (MicroOpCode == 9'h013) || (MicroOpCode == 9'h016) || (MicroOpCode == 9'h019) || (MicroOpCode == 9'h01b) || (MicroOpCode == 9'h020) || (MicroOpCode == 9'h023) || (MicroOpCode == 9'h026) || (MicroOpCode == 9'h028) || (MicroOpCode == 9'h02a) || (MicroOpCode == 9'h02c) || (MicroOpCode == 9'h02d) || (MicroOpCode == 9'h02e) || (MicroOpCode == 9'h030) || (MicroOpCode == 9'h032) || (MicroOpCode == 9'h033) || (MicroOpCode == 9'h034) || (MicroOpCode == 9'h035) || (MicroOpCode == 9'h037) || (MicroOpCode == 9'h038) || (MicroOpCode == 9'h03a) || (MicroOpCode == 9'h03c) || (MicroOpCode == 9'h03d) || (MicroOpCode == 9'h03f) || (MicroOpCode == 9'h041) || (MicroOpCode == 9'h042) || (MicroOpCode == 9'h043) || (MicroOpCode == 9'h044) || (MicroOpCode == 9'h045) || (MicroOpCode == 9'h047) || (MicroOpCode == 9'h048) || (MicroOpCode == 9'h049) || (MicroOpCode == 9'h04a) || (MicroOpCode == 9'h04b) || (MicroOpCode == 9'h04d) || (MicroOpCode == 9'h04f) || (MicroOpCode == 9'h050) || 0;
+	assign Signals[22] = (MicroOpCode == 9'h002) || (MicroOpCode == 9'h003) || (MicroOpCode == 9'h007) || (MicroOpCode == 9'h008) || (MicroOpCode == 9'h009) || (MicroOpCode == 9'h00d) || (MicroOpCode == 9'h00e) || (MicroOpCode == 9'h010) || (MicroOpCode == 9'h012) || (MicroOpCode == 9'h013) || (MicroOpCode == 9'h014) || (MicroOpCode == 9'h016) || (MicroOpCode == 9'h017) || (MicroOpCode == 9'h020) || (MicroOpCode == 9'h022) || (MicroOpCode == 9'h024) || (MicroOpCode == 9'h025) || (MicroOpCode == 9'h027) || (MicroOpCode == 9'h028) || (MicroOpCode == 9'h02a) || (MicroOpCode == 9'h02b) || (MicroOpCode == 9'h02c) || (MicroOpCode == 9'h02d) || (MicroOpCode == 9'h02e) || (MicroOpCode == 9'h02f) || (MicroOpCode == 9'h030) || (MicroOpCode == 9'h032) || (MicroOpCode == 9'h033) || (MicroOpCode == 9'h036) || (MicroOpCode == 9'h037) || (MicroOpCode == 9'h039) || (MicroOpCode == 9'h03a) || (MicroOpCode == 9'h03b) || (MicroOpCode == 9'h03c) || (MicroOpCode == 9'h03d) || (MicroOpCode == 9'h03e) || (MicroOpCode == 9'h03f) || (MicroOpCode == 9'h040) || (MicroOpCode == 9'h041) || (MicroOpCode == 9'h042) || (MicroOpCode == 9'h043) || (MicroOpCode == 9'h044) || (MicroOpCode == 9'h045) || (MicroOpCode == 9'h047) || (MicroOpCode == 9'h049) || (MicroOpCode == 9'h04b) || (MicroOpCode == 9'h04c) || (MicroOpCode == 9'h04e) || (MicroOpCode == 9'h04f) || (MicroOpCode == 9'h050) || 0;
+	assign Signals[23] = 0;
+	assign Signals[24] = 0;
+	assign Signals[25] = (MicroOpCode == 9'h021) || 0;
+	assign Signals[26] = (MicroOpCode == 9'h021) || 0;
+	assign Signals[27] = (MicroOpCode == 9'h002) || (MicroOpCode == 9'h003) || 0;
+	assign Signals[28] = (MicroOpCode == 9'h04d) || 0;
+	assign Signals[29] = (MicroOpCode == 9'h023) || (MicroOpCode == 9'h02e) || (MicroOpCode == 9'h03d) || (MicroOpCode == 9'h04d) || 0;
+	assign Signals[30] = (MicroOpCode == 9'h018) || (MicroOpCode == 9'h019) || (MicroOpCode == 9'h01a) || (MicroOpCode == 9'h01b) || 0;
+	assign Signals[31] = (MicroOpCode == 9'h006) || 0;
+	assign Signals[32] = (MicroOpCode == 9'h01e) || 0;
+	assign Signals[33] = (MicroOpCode == 9'h039) || (MicroOpCode == 9'h03e) || (MicroOpCode == 9'h044) || (MicroOpCode == 9'h04b) || (MicroOpCode == 9'h04c) || 0;
+	assign Signals[34] = (MicroOpCode == 9'h022) || (MicroOpCode == 9'h02a) || (MicroOpCode == 9'h02b) || (MicroOpCode == 9'h02c) || (MicroOpCode == 9'h03a) || (MicroOpCode == 9'h03c) || (MicroOpCode == 9'h03d) || (MicroOpCode == 9'h04e) || (MicroOpCode == 9'h04f) || 0;
+	assign Signals[35] = (MicroOpCode == 9'h027) || (MicroOpCode == 9'h028) || 0;
+	assign Signals[36] = (MicroOpCode == 9'h01d) || 0;
+	assign Signals[37] = (MicroOpCode == 9'h018) || (MicroOpCode == 9'h019) || 0;
+	assign Signals[38] = (MicroOpCode == 9'h00d) || (MicroOpCode == 9'h00e) || (MicroOpCode == 9'h010) || 0;
+	assign Signals[39] = 0;
+	assign Signals[40] = (MicroOpCode == 9'h005) || 0;
+	assign Signals[41] = 0;
+	assign Signals[42] = 0;
+	assign Signals[43] = 0;
+	assign Signals[44] = (MicroOpCode == 9'h01c) || 0;
+	assign Signals[45] = 0;
+
+endmodule
+
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/SMEMemoryMux.v b/BENCHMARK/ULPSH_fabric/rtl/src/SMEMemoryMux.v
new file mode 100644
index 0000000..0709dcd
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/SMEMemoryMux.v
@@ -0,0 +1,70 @@
+// -----------------------------------------------------------------------------
+// title          : Sensor Manager Memory Module
+// project        : ULP Sensor Hub
+// -----------------------------------------------------------------------------
+// file           : SMEMemoryMux.v
+// author         : OCTO
+// company        : QuickLogic Corp
+// created        : 2012/??/??	
+// last update    : 2014/05/20
+// platform       : PolarPro III
+// standard       : Verilog 2001
+// -----------------------------------------------------------------------------
+// description: The Sensor Manger Memory Mux selects between several sources
+//              for passing both read and write information. 
+// -----------------------------------------------------------------------------
+// copyright (c) 2013
+// -----------------------------------------------------------------------------
+// revisions  :
+// date            version    author         description
+// 2014/05/20      1.0        Glen Gomes     Updated -> Added support for a second 
+//                                                      memory block by adding
+//                                                      address bits.
+// -----------------------------------------------------------------------------
+// Comments: This solution is specifically for use with the QuickLogic
+//           PolarPro III S2 device. 
+// -----------------------------------------------------------------------------
+
+`timescale 1ns / 10ps
+
+module SMEMemoryMux (
+	input		Select,
+	
+	input [9:0]		ReadAddressIn0,    // Expanded for Rel 0 on 6/18
+	input [9:0]		ReadAddressIn1,    // Expanded for Rel 0 on 6/18
+	output[9:0]		ReadAddressOut,    // Expanded for Rel 0 on 6/18
+	
+	input [9:0]		WriteAddressIn0,
+	input [9:0]		WriteAddressIn1,
+	output[9:0]		WriteAddressOut,
+	
+	input [8:0]		DataToMemoryIn0,
+	input [8:0]		DataToMemoryIn1,
+	output[8:0]		DataToMemoryOut,
+	
+	input [17:0]	DataFromMemoryIn0,
+	input [17:0]	DataFromMemoryIn1,
+	output[17:0]	DataFromMemoryOut,
+	
+	input			ReadEnableIn0,
+	input			ReadEnableIn1,
+	output			ReadEnableOut,
+	
+	input			WriteEnableIn0,
+	input			WriteEnableIn1,
+	output			WriteEnableOut,
+	
+	input			ReadClockIn0,
+	input			ReadClockIn1,
+	output			ReadClockOut	
+	);
+	
+	assign ReadAddressOut = (Select) ? ReadAddressIn1 : ReadAddressIn0;
+	assign WriteAddressOut = (Select) ? WriteAddressIn1 : WriteAddressIn0;
+	assign DataToMemoryOut = (Select) ? DataToMemoryIn1 : DataToMemoryIn0;
+	assign DataFromMemoryOut = (Select) ? DataFromMemoryIn1 : DataFromMemoryIn0;
+	assign ReadEnableOut = (Select) ? ReadEnableIn1 : ReadEnableIn0;
+	assign WriteEnableOut = (Select) ? WriteEnableIn1 : WriteEnableIn0;
+	assign ReadClockOut = (Select) ? ReadClockIn1 : ReadClockIn0;
+
+endmodule
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/SMMemory.v b/BENCHMARK/ULPSH_fabric/rtl/src/SMMemory.v
new file mode 100644
index 0000000..1ea5921
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/SMMemory.v
@@ -0,0 +1,112 @@
+// -----------------------------------------------------------------------------
+// title          : Sensor Manager Memory Module
+// project        : ULP Sensor Hub
+// -----------------------------------------------------------------------------
+// file           : SMMemory.v
+// author         : OCTO
+// company        : QuickLogic Corp
+// created        : 2012/??/??	
+// last update    : 2014/05/20
+// platform       : PolarPro III
+// standard       : Verilog 2001
+// -----------------------------------------------------------------------------
+// description: The Sensor Manger Memory performs several tasks. These include
+//              storing Sensor Manager Instructions, Sensor Data, and FFE mail
+//              box data. This memory consists of several physical memory
+//              blocks.
+// -----------------------------------------------------------------------------
+// copyright (c) 2013
+// -----------------------------------------------------------------------------
+// revisions  :
+// date            version    author         description
+// 2014/05/20      1.0        Glen Gomes     Updated -> Added a second memory block
+// -----------------------------------------------------------------------------
+// Comments: This solution is specifically for use with the QuickLogic
+//           PolarPro III S2 device. 
+// -----------------------------------------------------------------------------
+
+`timescale 1ns / 10ps
+
+module SMMemory (
+    // General Interface
+    input         ResetIn,
+	input		  SMBusyIn,
+    
+    //Read Interface
+    input   [9:0] ReadAddressIn,
+    output [17:0] ReadDataOut,
+    input         ReadSelectIn,
+    input         ReadClockIn,
+    
+    //Write Interface
+    input   [9:0] WriteAddressIn,
+    input   [8:0] WriteDataIn,
+    input         WriteSelectIn,
+
+    input   [9:0] WriteAddressIn_TLC,
+    input   [8:0] WriteDataIn_TLC,
+    input         WriteSelectIn_TLC,
+
+    input         WriteClockIn,
+	
+	output 	[9:0]	SMMemory_WriteAddressIn_TLC_o,
+	output 	[8:0]	SMMemory_ReadAddressIn_o,
+	output 			SMMemory_WriteSelectIn_TLC_o,
+	output 			SMMemory_ReadSelect_RAM0_o,
+	output 			SMMemory_WriteClockIn_o,
+	output 			SMMemory_ReadClockIn_o,
+	output  [8:0]	SMMemory_WriteDataIn_TLC_o,
+	input  	[17:0]	SMMemory_ReadDataOut_SRAM_i,
+	output 	[9:0]	SMMemory_WriteAddressIn_o,
+	output 		    SMMemory_WriteSelectIn_o,
+	output 			SMMemory_ReadSelect_RAM1_o,
+	output 			SMMemory_WriteDataIn_o,
+	input  	[17:0]	SMMemory_ReadDataOut_SRAM1_i
+	
+	
+
+	
+    );
+
+	// Define local variables
+	//
+	wire   [17:0] ReadDataOut_SRAM;
+	wire   [17:0] ReadDataOut_SRAM_1;
+
+	reg				ReadDataSel;
+	wire			ReadSelect_RAM0;
+	wire			ReadSelect_RAM1;
+	wire			SMMemoryBankSelect;
+
+
+	// generate individual read enables
+	assign ReadSelect_RAM0 = ReadSelectIn && !ReadAddressIn[9];
+	assign ReadSelect_RAM1 = ReadSelectIn && ReadAddressIn[9];
+
+
+	// Mux the read data
+	always @(posedge ReadClockIn)
+		ReadDataSel <= ReadAddressIn[9];
+
+	assign SMMemoryBankSelect = SMBusyIn ? ReadAddressIn[9] : ReadDataSel;
+	assign ReadDataOut = SMMemoryBankSelect ? ReadDataOut_SRAM_1: ReadDataOut_SRAM;
+
+
+	// Instantiate the Memory Blocks
+	//
+	assign SMMemory_WriteAddressIn_TLC_o = WriteAddressIn_TLC;
+	assign SMMemory_ReadAddressIn_o[8:0] = ReadAddressIn[8:0];
+	assign SMMemory_WriteSelectIn_TLC_o  = WriteSelectIn_TLC;
+	assign SMMemory_ReadSelect_RAM0_o    = ReadSelect_RAM0;
+	assign SMMemory_WriteClockIn_o       = WriteClockIn;
+	assign SMMemory_ReadClockIn_o        = ReadClockIn;
+	assign SMMemory_WriteDataIn_TLC_o    = WriteDataIn_TLC;
+	assign ReadDataOut_SRAM   		     = SMMemory_ReadDataOut_SRAM_i;
+	
+	assign SMMemory_WriteAddressIn_o     = WriteAddressIn;
+	assign SMMemory_WriteSelectIn_o      = WriteSelectIn;
+	assign SMMemory_ReadSelect_RAM1_o    = ReadSelect_RAM1;
+	assign SMMemory_WriteDataIn_o         = WriteDataIn;
+	assign ReadDataOut_SRAM1   		     = SMMemory_ReadDataOut_SRAM1_i;
+
+endmodule 
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/SPI_slave.v b/BENCHMARK/ULPSH_fabric/rtl/src/SPI_slave.v
new file mode 100644
index 0000000..4972d91
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/SPI_slave.v
@@ -0,0 +1,292 @@
+
+/*------------------------------------------------------------------------------
+SPI_slave
+	SPI slave interface, designed for the ULP Sensor Hub.
+	This module is designed to be as small and simple as possible, while
+	supporting the ULP Sensor Hub. Only supports SPI Mode 0 (CPOL=CPHA=0)...
+	which means that input data is latched on the positive edge of SPI_SCLK,
+	and driven out on the negative edge of SPI_SCLK, with the base value of
+	SPI_SCLK being 0.
+
+
+	SPI Protocol:
+		Writes:		MOSI: A0 + D0 + D1 + ... + Dn
+					MISO: xx + xx + xx + ... + xx
+
+		Reads:		MOSI: A0 + xx + xx + ... + xx
+					MISO: xx + xx + D0 + ... + Dn
+
+		A0 = [1-bit R/W: 1=write, 0=read] + [7-bit address]
+		Dn = valid data byte
+		xx = don't-care data byte
+
+		It is assumed that the MSb is transmitted first, and the LSb last.
+
+		The address is latched, and auto-incremented to support burst reads/writes.
+		The address, when 0d11, jumps back to 0d07, to support repeated (burst)
+		reads to/from the memory data port. The logic to re-map addresses above
+		0d11, that previously was in TLC.v, can now be removed. New registers
+		above 0d11 may now be added if needed.
+
+		This SPI slave requires extra edges on SPI_SCLK to complete any write
+		operation. This may be accomplished in any one of several ways:
+			1. A (non-destructive) read should be performed following the last
+			   write operation.
+			2. SPI_SCLK should be toggled after SPI_SS goes inactive
+			   (a free-running SPI_SCLK would accomplish this).
+			3. A few extra bits (totaling less than a full byte) should be
+			   transmitted by the master. These extra bits will be ignored by
+			   this core, but will provide the clocks needed to generated the
+			   wr_data_valid pulse.
+			4. A "null" transaction should be performed following the last
+			   write transaction, during which the address byte is transmitted
+			   by the SPI master followed by 0 bytes of read/write data.
+
+------------------------------------------------------------------------------*/
+
+
+
+
+`timescale 1ns / 1ns
+
+`include "SensorHubDefines.v"
+
+
+module SPI_slave (
+	input			rst,			// system/global reset (active-high)
+
+	// SPI interface
+	input			SPI_SCLK,		// base value 0 (mode 0)
+	input			SPI_MOSI,		// master out, slave in
+	output			SPI_MISO,		// master in, slave out
+	input			SPI_SS,			// slave select (active-low)
+
+	// internal interface
+	output	[6:0]	addr,
+	output	[7:0]	wr_data,
+	output			wr_data_valid,	// active high
+	input	[7:0]	rd_data,
+	output			rd_data_ack
+);
+
+
+parameter		WR = 1'b1;
+parameter		RD = 1'b0;
+
+
+wire			rst_int;
+
+reg		[7:0]	shift_in;
+reg		[7:0]	shift_out;
+
+reg		[2:0]	bit_cnt, bit_cnt_neg;
+
+reg				rcv_byte_valid;
+reg				addr_has_been_latched;
+reg				first_data_has_been_latched;
+reg		[6:0]	addr_reg;
+reg				write_readn;
+reg		[7:0]	write_data_reg;
+reg				wr_data_valid_reg;
+reg				write_pending;
+reg				rd_data_ack_reg;
+
+
+
+// rst_int is active when the global rst occurs or when the SPI interface is idle.
+//    Some logic needs to remain active after a SPI transaction occurs, so rst will be used in those cases.
+assign rst_int = rst || SPI_SS;
+
+// input shift register
+always @(posedge rst_int or posedge SPI_SCLK)
+	if (rst_int)
+		shift_in <= 8'b0;
+	else
+		if (!SPI_SS)
+			shift_in <= {shift_in[6:0], SPI_MOSI};
+		else
+			shift_in <= shift_in;
+
+
+// bit counter
+always @(posedge rst_int or posedge SPI_SCLK)
+	if (rst_int)
+		bit_cnt <= 3'b0;
+	else
+		if (!SPI_SS)
+			bit_cnt <= bit_cnt + 1;
+		else
+			bit_cnt <= 3'b0;
+
+
+// byte valid, active for 1 clk every time a full byte has been received from the master
+always @(posedge rst_int or posedge SPI_SCLK)
+	if (rst_int)
+		rcv_byte_valid <= 1'b0;
+	else
+		if (rcv_byte_valid)				// added to guarantee that rcv_byte_valid is only active for 1 clock
+			rcv_byte_valid <= 1'b0;
+		else
+			if (!SPI_SS && (bit_cnt == 3'b111))
+				rcv_byte_valid <= 1'b1;
+			else
+				rcv_byte_valid <= 1'b0;
+
+
+// flags for keeping track of the address byte and 1st data byte
+always @(posedge rst_int or posedge SPI_SCLK)
+	if (rst_int) begin
+		addr_has_been_latched		<= 1'b0;	// flag that gets set after the addr has been received (and latched)
+		first_data_has_been_latched	<= 1'b0;	// flag that gets set after the 1st data byte has been received (and latched)
+	end
+	else begin
+
+//		if (SPI_SS)		// if SPI interface is idle
+//			addr_has_been_latched <= 1'b0;
+//		else
+// the above is not necessary since the async rst includes SPI_SS
+			if (rcv_byte_valid)
+				addr_has_been_latched <= 1'b1;		// set flag after first byte (the address) is received, keep at 1 until transaction is over
+			else
+				addr_has_been_latched <= addr_has_been_latched;
+
+//		if (SPI_SS)		// if SPI interface is idle
+//			first_data_has_been_latched <= 1'b0;
+//		else
+// the above is not necessary since the async rst includes SPI_SS
+			if (addr_has_been_latched && rcv_byte_valid)
+				first_data_has_been_latched <= 1'b1;
+			else
+				first_data_has_been_latched <= first_data_has_been_latched;
+
+	end
+
+
+// address register, direction control flag
+always @(posedge rst or posedge SPI_SCLK)		// don't use rst_int so these signals will remain active even after SPI_SS has gone inactive
+	if (rst) begin
+		addr_reg		<= 7'b0;
+		write_readn		<= 1'b0;	// flag that signifies a write vs. read transaction
+	end
+	else begin
+
+		if (!addr_has_been_latched && rcv_byte_valid)
+			write_readn <= shift_in[7];				// the direction (r/w) flag is in the MSb of the address byte.
+		else
+			write_readn <= write_readn;
+
+		if (!addr_has_been_latched)
+			if (rcv_byte_valid)
+				addr_reg <= shift_in[6:0];				// latch the new address, located in the lowest 7 bits of the address byte.
+			else
+				addr_reg <= addr_reg;
+		else // addr_has_been_latched
+
+//			if (((write_readn == WR) && wr_data_valid_reg) || ((write_readn == RD) && rcv_byte_valid))
+//				addr_reg <= addr_reg + 1;
+//			else
+//				addr_reg <= addr_reg;
+
+			// during writes, make addr_reg	wrap back to MemDataByte0 after MemDataByte4
+			if ((write_readn == WR) && wr_data_valid_reg)
+				if (addr_reg == `MemDataByte4)
+					addr_reg <= `MemDataByte0;
+				else
+					addr_reg <= addr_reg + 1;
+			else
+				// during reads, do not increment addr_reg when accessing CM_FIFO_Data
+				//if ((write_readn == RD) && rcv_byte_valid)
+				if ((write_readn == RD) && rd_data_ack_reg)
+					if (addr_reg == `CM_FIFO_Data)
+						addr_reg <= addr_reg;
+					else
+						addr_reg <= addr_reg + 1;
+				else
+					addr_reg <= addr_reg;
+
+	end
+
+
+// write_pending flag, so writes eventually get sent to the internal interface when more SPI_SCLK edges occur
+always @(posedge rst or posedge SPI_SCLK)		// don't use rst_int since this may need to stay active after SPI_SS goes inactive
+	if (rst)
+		write_pending <= 1'b0;
+	else
+		if (wr_data_valid_reg)
+			write_pending <= 1'b0;
+		else
+			if ((write_readn == WR) && !SPI_SS && addr_has_been_latched && (bit_cnt == 3'b111))		// can't use rcv_byte_valid since there may not be extra clocks after this byte is being written
+				write_pending <= 1'b1;
+			else
+				write_pending <= write_pending;
+
+
+// write data valid signal
+always @(posedge rst or posedge SPI_SCLK)		// don't use rst_int since this may need to be set after SPI_SS goes inactive
+	if (rst)
+		wr_data_valid_reg <= 1'b0;
+	else
+		if (wr_data_valid_reg)
+			wr_data_valid_reg <= 1'b0;
+		else
+			if (write_pending)
+				wr_data_valid_reg <= 1'b1;
+			else
+				wr_data_valid_reg <= wr_data_valid_reg;
+
+
+always @(posedge rst or posedge SPI_SCLK)		// don't use rst_int since this needs to stay valid after SPI_SS goes inactive
+	if (rst)
+		write_data_reg <= 8'b0;
+	else
+		if (!SPI_SS && (bit_cnt == 3'b111))
+			write_data_reg <= {shift_in[6:0], SPI_MOSI};
+		else
+			write_data_reg <= write_data_reg;
+
+
+// output shift register
+always @(posedge rst_int or negedge SPI_SCLK)
+	if (rst_int) begin
+		bit_cnt_neg <= 3'b0;
+		shift_out <= 8'b0;
+	end
+	else begin
+		if (!SPI_SS) begin
+			bit_cnt_neg <= bit_cnt_neg + 1;
+
+			if (addr_has_been_latched && (bit_cnt_neg == 7))
+				shift_out <= rd_data;
+			else
+				shift_out <= {shift_out[6:0], 1'b0};
+		end
+		else begin
+			bit_cnt_neg <= 3'b0;
+			shift_out <= shift_out;
+		end
+	end
+
+
+// read data acknowledge. this is required to pop data from the CM FIFO
+always @(posedge rst_int or posedge SPI_SCLK)
+	if (rst_int)
+		rd_data_ack_reg <= 1'b0;
+	else
+		//if ( addr_has_been_latched && (write_readn == RD) && (bit_cnt == 3'b111) )
+		if ( addr_has_been_latched && (write_readn == RD) && rcv_byte_valid)
+			rd_data_ack_reg <= 1'b1;
+		else
+			rd_data_ack_reg <= 1'b0;
+
+
+
+// assignments to the outputs
+//assign SPI_MISO			= SPI_SS ? 1'bz : shift_out[7];
+assign SPI_MISO			= shift_out[7];//AP2 doesn't support tristate
+assign addr				= addr_reg;
+assign wr_data			= write_data_reg;
+assign wr_data_valid	= wr_data_valid_reg;
+assign rd_data_ack		= rd_data_ack_reg;
+
+endmodule
+
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/SensorHubDefines.v b/BENCHMARK/ULPSH_fabric/rtl/src/SensorHubDefines.v
new file mode 100644
index 0000000..bd2d0dc
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/SensorHubDefines.v
@@ -0,0 +1,65 @@
+
+`ifndef SensorHub_Definitions
+
+	`define SensorHub_Definitions
+
+	// Communication Manager register offsets
+	`define CommandReg				7'h00
+	`define StatusReg				7'h01
+	`define milSecSample			7'h02
+	`define InterruptCtrl			7'h03
+	`define InterruptStat			7'h04
+	`define CalValueLow				7'h05
+	`define CalValueHi				7'h06
+	`define Reserved_10				7'h07
+	`define Reserved_11				7'h08
+	`define Reserved_12				7'h09
+	`define Reserved_13				7'h0A
+	`define Reserved_14				7'h0B
+	`define CM_FIFO_Data			7'h0C
+	`define CM_Control				7'h0D
+	`define CM_Status				7'h0E
+	`define CM_FIFO_Flags_0			7'h0F
+	`define Reserved_1				7'h10	/* reserved for CM_FIFO_Flags_23 */
+	`define MailboxToFFE_0			7'h11
+	`define MailboxToFFE_1			7'h12
+	`define MailboxToFFE_2			7'h13
+	`define MailboxToFFE_3			7'h14
+	`define InterruptFFEMsg			7'h15
+	`define Reserved_5				7'h16
+	`define Reserved_6				7'h17
+	`define Reserved_7				7'h18
+	`define RunTimeAdrReg           7'h19
+	`define DemoLedCtrlReg          7'h1A   /* Register to control demo LEDs */
+	`define ClocksControl           7'h1B
+	`define	SleepControl			7'h1C
+	`define RunTimeAdrReg_Upr       7'h1D   /* New for Rel 0 on 6/18 */
+	`define MemAddrLow				7'h20
+	`define MemAddrHigh				7'h21
+	`define MemSelect				7'h22
+	`define MemDataByte0			7'h28
+	`define MemDataByte1			7'h29
+	`define MemDataByte2			7'h2A
+	`define MemDataByte3			7'h2B
+	`define MemDataByte4			7'h2C
+	
+
+	`define	CtrlSensorManager		8'h00
+	`define CtrlReceiveAddress		8'h01
+	`define CtrlRunTimeAddress		8'h02
+	`define	MasterPreLo				8'h08
+	`define	MasterPreHi				8'h09
+	`define MasterCTR				8'h0A
+	`define MasterTXR				8'h0B
+	`define MasterCR				8'h0C
+
+
+	`define CR_START		8'b1000_0000
+	`define CR_STOP			8'b0100_0000
+	`define CR_READ			8'b0010_0000
+	`define CR_WRITE		8'b0001_0000
+	`define CR_NAK			8'b0000_1000
+	// `define CR_POLL			8'b0000_0100
+	`define CR_IACK			8'b0000_0001
+
+`endif
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/SensorManager.v b/BENCHMARK/ULPSH_fabric/rtl/src/SensorManager.v
new file mode 100644
index 0000000..21f02a6
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/SensorManager.v
@@ -0,0 +1,960 @@
+// -----------------------------------------------------------------------------
+// title          : Sensor Manager Main Routine
+// project        : ULP Sensor Hub
+// -----------------------------------------------------------------------------
+// file           : SensorManager.v
+// author         : OCTO
+// company        : QuickLogic Corp
+// created        : 2012/??/??	
+// last update    : 2013/12/06
+// platform       : PolarPro III
+// standard       : Verilog 2001
+// -----------------------------------------------------------------------------
+// description: The Sensor Manger is responsible for controlling various
+//              external sensors and storing the resulting data in Sensor
+//              Manager Memory. These include performing transfers between 
+//              Sensor Memory and various registers.
+// -----------------------------------------------------------------------------
+// copyright (c) 2013
+// -----------------------------------------------------------------------------
+// revisions  :
+// date            version    author         description
+// 2013/12/06      1.0        Glen Gomes     Updated -> Mostly re-written
+// -----------------------------------------------------------------------------
+// Comments: This solution is specifically for use with the QuickLogic
+//           PolarPro III device. 
+// -----------------------------------------------------------------------------
+
+`timescale 1ns / 10ps
+
+module SensorManager (
+
+	                // General interface
+	                ClockIn,
+	                ResetIn,
+                    StartFromFFE,
+                    StartFromTLC,
+	                BusyOut,
+                    TimeStamp_Delta_i,
+                    TimeStamp_Delta_Tog_i,
+                    SensorInterrupt_0_i,
+                    SensorInterrupt_1_i,
+                    SensorInterrupt_2_i,
+                    SensorInterrupt_3_i,
+                    SensorInterrupt_0_o,
+                    SensorInterrupt_1_o,
+                    SensorInterrupt_2_o,
+                    SensorInterrupt_3_o,
+                    CtrlRunTimeAddressSM,
+                    CtrlRunTimeAddressOut,
+                    CtrlRunTimeAddressReg,
+	                MemReadAddressOut,
+	                MemReadEnableOut,
+	                MemReadDataIn,
+	                MemWriteAddressOut,
+	                MemWriteEnableOut,
+	                MemWriteDataOut,
+	                MemClockOut,
+	                I2C_wb_adr_o,
+	                I2C_wb_dat_o,
+	                I2C_wb_dat_i,
+	                I2C_wb_we_o,
+	                I2C_wb_stb_o,
+	                I2C_wb_cyc_o,
+	                I2C_wb_ack_i,
+	                I2C_tip_i,
+	                TP1,
+	                TP2,
+	                TP3,
+					SmClockSelect_o
+);	
+	
+//-----Port Signals--------------------
+//
+
+input               ClockIn;
+input               ResetIn;
+input           	StartFromFFE;
+input               StartFromTLC;
+output              BusyOut;
+input       [15:0]  TimeStamp_Delta_i;
+input               TimeStamp_Delta_Tog_i;
+input               SensorInterrupt_0_i;
+input               SensorInterrupt_1_i;
+input               SensorInterrupt_2_i;
+input               SensorInterrupt_3_i;
+output              SensorInterrupt_0_o;
+output              SensorInterrupt_1_o;
+output              SensorInterrupt_2_o;
+output              SensorInterrupt_3_o;
+input               CtrlRunTimeAddressSM;
+input        [9:0]  CtrlRunTimeAddressOut;
+output       [9:0]  CtrlRunTimeAddressReg;
+output       [9:0]  MemReadAddressOut;  // Expanded for Rel 0 on 6/18
+output              MemReadEnableOut;
+input       [17:0]  MemReadDataIn;
+output       [9:0]  MemWriteAddressOut;
+output              MemWriteEnableOut;
+output       [8:0]  MemWriteDataOut;
+output              MemClockOut;
+output       [2:0]  I2C_wb_adr_o;
+output       [7:0]  I2C_wb_dat_o;
+input        [7:0]  I2C_wb_dat_i;
+output              I2C_wb_we_o;
+output              I2C_wb_stb_o;
+output              I2C_wb_cyc_o;
+input               I2C_wb_ack_i;
+input               I2C_tip_i;
+output              TP1;
+output              TP2;
+output              TP3;
+output				SmClockSelect_o;
+
+
+wire                ClockIn;
+wire                ResetIn;
+wire                StartFromFFE;
+wire            	StartFromTLC;
+wire                BusyOut;
+wire        [15:0]  TimeStamp_Delta_i;
+wire                TimeStamp_Delta_Tog_i;
+wire                SensorInterrupt_0_i;
+wire                SensorInterrupt_1_i;
+wire                SensorInterrupt_2_i;
+wire                SensorInterrupt_3_i;
+reg                 SensorInterrupt_0_o;
+reg                 SensorInterrupt_1_o;
+reg                 SensorInterrupt_2_o;
+reg                 SensorInterrupt_3_o;
+wire                CtrlRunTimeAddressSM;
+wire         [9:0]  CtrlRunTimeAddressOut;
+reg          [9:0]  CtrlRunTimeAddressReg;
+wire  		 [9:0]  MemReadAddressOut;  // Expanded for Rel 0 on 6/18
+wire                MemReadEnableOut;
+wire        [17:0]  MemReadDataIn;
+wire         [9:0]  MemWriteAddressOut;
+wire                MemWriteEnableOut;
+reg          [8:0]  MemWriteDataOut;
+wire         [2:0]  I2C_wb_adr_o;
+wire         [7:0]  I2C_wb_dat_o;
+wire         [7:0]  I2C_wb_dat_i;
+wire                I2C_wb_we_o;
+wire                I2C_wb_stb_o;
+wire                I2C_wb_cyc_o;
+wire                I2C_wb_ack_i;
+wire                I2C_tip_i;
+wire                MemClockOut;
+wire                TP1;
+wire                TP2;
+wire                TP3;
+reg					SmClockSelect_o;
+
+
+//-----Internal Signals--------------------
+//
+
+wire		    	wb_cyc;
+
+wire			    wb_we;
+wire			    wb_stb;
+
+wire                wb_ack;
+reg                 wb_ack_sm;
+
+wire                wb_busy_poll;
+
+reg          [9:0]  CtrlReceiveAddressReg;
+
+reg          [5:0]  CtrlMailBoxSegmentCtr;
+reg                 CtrlMailBoxSegmentCtr_ce;
+
+reg          [9:2]  CtrlMailBoxTablePtr;
+
+reg          [9:0]  CtrlMailBoxJumpInstPtr;
+
+reg                 CtrlMailBoxJumpInstCycle;
+reg                 CtrlMailBoxJumpInstCycle_ce;
+	
+wire         [9:0]  StateMachineCtrlMemAddr;
+wire         [7:0]  i2c_masterDataToMem;
+
+wire                save_reg_2_mem;
+
+wire                control_sensor_manager_reg_dcd;
+wire                control_receive_reg_dcd;
+wire                control_runtime_reg_dcd;
+wire                control_jump_reg_dcd;
+wire                control_mailbox_tbl_ptr_dcd;
+wire                control_mailbox_jump_inst_ptr_dcd;
+
+reg                 RunSM;
+wire                BusySM;
+
+wire                StartIn_stb;
+
+reg                 StartFromFFE_1ff;
+reg                 StartFromFFE_2ff;
+reg                 StartFromFFE_3ff;
+reg                 StartFromFFE_4ff;
+reg                 StartFromFFE_5ff;
+reg                 StartFromFFE_6ff;
+
+reg                 StartFromTLC_1ff;
+reg                 StartFromTLC_2ff;
+
+reg                 CtrlRunTimeAddressSM_1ff;
+reg                 CtrlRunTimeAddressSM_2ff;
+
+reg					s1_BusyOut, s2_BusyOut;
+
+// Define write enable controls for each TimeStamp register
+//
+wire                SensorInterrupt_event_reg_we_dcd;
+
+wire                SensorInterrupt_event_mask_we_dcd;
+
+reg                 SensorInterrupt_event_mask_0;
+reg                 SensorInterrupt_event_mask_1;
+reg                 SensorInterrupt_event_mask_2;
+reg                 SensorInterrupt_event_mask_3;
+
+
+// Delta Time Stamp registers for each sensor
+//
+reg          [7:0]  TimeStamp_Delta_sensor_0;
+reg          [7:0]  TimeStamp_Delta_sensor_1;
+reg          [7:0]  TimeStamp_Delta_sensor_2;
+reg          [7:0]  TimeStamp_Delta_sensor_3;
+
+reg         [15:0]  TimeStamp_Delta_capt;
+reg         [15:0]  TimeStamp_Delta_readback;
+
+reg                 TimeStamp_Delta_Tog_1ff;
+reg                 TimeStamp_Delta_Tog_2ff;
+reg                 TimeStamp_Delta_Tog_3ff;
+
+// Meta-state registers for each sensor interrupt
+//
+reg                 SensorInterrupt_0_1ff;
+reg                 SensorInterrupt_0_2ff;
+reg                 SensorInterrupt_0_3ff;
+
+reg                 SensorInterrupt_1_1ff;
+reg                 SensorInterrupt_1_2ff;
+reg                 SensorInterrupt_1_3ff;
+
+reg                 SensorInterrupt_2_1ff;
+reg                 SensorInterrupt_2_2ff;
+reg                 SensorInterrupt_2_3ff;
+
+reg                 SensorInterrupt_3_1ff;
+reg                 SensorInterrupt_3_2ff;
+reg                 SensorInterrupt_3_3ff;
+
+
+//  Wait Instruction Registers
+//
+wire                control_wait_instr_reg_dcd;
+
+reg         [12:0]  control_wait_instr_cntr;
+reg         [12:0]  control_wait_instr_cntr_nxt;
+
+reg                 control_wait_instr_cntr_tc;
+reg                 control_wait_instr_cntr_tc_nxt;
+
+reg                 control_wait_instr_busy;
+wire                control_wait_instr_busy_nxt;
+
+
+
+//------Define Parameters---------
+//
+
+//
+// Define the various address spaces
+//
+// Note: These correspond to bits [7:3] of the register address field.
+//
+parameter SENSOR_MANAGER_ADR      = 5'h0;
+parameter I2C_MASTER_ADR          = 5'h1;
+parameter TIMESTAMP_DELTA_ADR     = 5'h2;
+
+
+
+//
+// Define the available registers in the Sensor Manager
+//
+// Note: These correspond to bits [2:0] of the register address field.
+//
+parameter CONTROL_SENSOR_MANAGER_ADDRESS  = 3'h0;
+parameter CONTROL_RECEIVE_ADDRESS         = 3'h1;
+parameter CONTROL_RUNTIME_ADDRESS         = 3'h2;
+parameter CONTROL_WAIT_INSTR_ADDRESS      = 3'h4;
+parameter CONTROL_MAILBOX_TABLE_PTR       = 3'h5;
+parameter CONTROL_MAILBOX_JUMP_INST_PTR   = 3'h6;
+parameter CONTROL_JUMP_ADDRESS            = 3'h7;
+
+
+//
+// Define the key registers in the I2C Master IP
+//
+// Note: These correspond to bits [2:0] of the register address field.
+//
+parameter I2C_MASTER_PRELO		  = 3'h0;
+parameter I2C_MASTER_PREHI        = 3'h1;
+parameter I2C_MASTER_CTR          = 3'h2;
+parameter I2C_MASTER_TXR          = 3'h3;
+parameter I2C_MASTER_CR           = 3'h4;
+
+
+// Define the available registers in the TimeStamp Logic
+//
+// Note: These correspond to bits [2:0] of the register address field.
+//
+parameter TIMESTAMP_DELTA_SENSOR_0    = 3'h0;
+parameter TIMESTAMP_DELTA_SENSOR_1    = 3'h1;
+parameter TIMESTAMP_DELTA_SENSOR_2    = 3'h2;
+parameter TIMESTAMP_DELTA_SENSOR_3    = 3'h3;
+parameter TIMESTAMP_DELTA_GENERIC_LSB = 3'h4;
+parameter TIMESTAMP_DELTA_GENERIC_MSB = 3'h5;
+parameter TIMESTAMP_DELTA_INT_EVENT   = 3'h6;
+
+
+//
+// Define the default location of the Mail Box structure in SM Memory
+//
+parameter MAILBOX_SM_ADDRESS      = 8'hFF; // Note: This is "3FC" shifted by two to the right
+
+//------Logic Operations----------
+//
+
+// I2C Interface to the Right Bank ASSP
+//
+assign  I2C_wb_dat_o                     = MemReadDataIn[15:8];
+assign  i2c_masterDataToMem              = I2C_wb_dat_i;
+assign  I2C_wb_we_o                      = wb_we;
+assign  I2C_wb_stb_o                     = wb_stb;
+
+// Decode the Wishbone bus address space(s)
+//
+assign I2C_wb_cyc_o                      = (MemReadDataIn[7:3] == I2C_MASTER_ADR) & wb_cyc & ~CtrlMailBoxJumpInstCycle;
+
+
+// Define the write enables controls for each register
+//
+assign control_sensor_manager_reg_dcd  = (MemReadDataIn[7:0] == {SENSOR_MANAGER_ADR, CONTROL_SENSOR_MANAGER_ADDRESS}) & wb_cyc & wb_stb & wb_we & ~wb_ack_sm & ~CtrlMailBoxJumpInstCycle;
+assign control_runtime_reg_dcd         = (MemReadDataIn[7:0] == {SENSOR_MANAGER_ADR, CONTROL_RUNTIME_ADDRESS})        & wb_cyc & wb_stb & wb_we & ~wb_ack_sm & ~CtrlMailBoxJumpInstCycle;
+
+assign control_wait_instr_reg_dcd      = (MemReadDataIn[7:0] == {SENSOR_MANAGER_ADR, CONTROL_WAIT_INSTR_ADDRESS})     & wb_cyc & wb_stb & wb_we & ~wb_ack_sm & ~CtrlMailBoxJumpInstCycle;
+
+assign control_receive_reg_dcd         = ((MemReadDataIn[7:0] == { SENSOR_MANAGER_ADR, CONTROL_RECEIVE_ADDRESS})
+		                               |  (MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_SENSOR_0})
+                                       |  (MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_SENSOR_1})
+                                       |  (MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_SENSOR_2})
+                                       |  (MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_SENSOR_3})
+                                       |  (MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_GENERIC_MSB})
+                                       |  (MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_GENERIC_LSB})) & wb_cyc & wb_stb & wb_we & ~wb_ack_sm & ~CtrlMailBoxJumpInstCycle;
+
+
+
+// Define the write enable for the Interrupt event of the Time Stamp Logic
+//
+// Note: This write occurs after the write of interrupt data to SM Memory
+//
+assign SensorInterrupt_event_reg_we_dcd  = (MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_INT_EVENT})   & wb_cyc & wb_stb & ~wb_we &  wb_ack_sm & ~CtrlMailBoxJumpInstCycle;
+assign SensorInterrupt_event_mask_we_dcd = (MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_INT_EVENT})   & wb_cyc & wb_stb &  wb_we & ~wb_ack_sm & ~CtrlMailBoxJumpInstCycle;
+assign TimeStamp_Delta_lsb_reg_we_dcd    = (MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_GENERIC_LSB}) & wb_cyc & wb_stb &  wb_we & ~wb_ack_sm & ~CtrlMailBoxJumpInstCycle;
+
+
+// Deterimine if the current cycle is a write to the instruction pointer.
+//
+// Note: This only happens during the "jump" instruction
+//
+//       This signals the Sensor Manager Statemachine that the current cycle
+//       is a "jump" and to load the register data value into the instruction
+//       pointer at the end of the current "register write" instruction.
+//
+assign control_jump_reg_dcd              = (MemReadDataIn[7:0] == {SENSOR_MANAGER_ADR, CONTROL_JUMP_ADDRESS})                                                 & ~CtrlMailBoxJumpInstCycle;
+
+
+// Determine if the current cycle is the start of a Mail Box based Jump
+// sequence.
+//
+// Note: The value of the bits in the Mail Box region of SM Memory determine
+//       if the current jump address should be loaded into the instruction
+//       pointer or if it should be ignored.
+//
+assign control_mailbox_tbl_ptr_dcd       = (MemReadDataIn[7:0] == {SENSOR_MANAGER_ADR, CONTROL_MAILBOX_TABLE_PTR})     & wb_cyc & wb_stb & wb_we & ~wb_ack_sm & ~CtrlMailBoxJumpInstCycle;
+assign control_mailbox_jump_inst_ptr_dcd = (MemReadDataIn[7:0] == {SENSOR_MANAGER_ADR, CONTROL_MAILBOX_JUMP_INST_PTR}) & wb_cyc & wb_stb & wb_we &  wb_ack_sm & ~CtrlMailBoxJumpInstCycle;
+
+
+// Determine if the current address should include a write to the Sensor Manager's Memory
+//
+// Note: There is currently only one address but this may expand with, for
+//       example, a TimeStamp function.
+//
+assign save_reg_2_mem                  = ((MemReadDataIn[7:0] == {     I2C_MASTER_ADR, I2C_MASTER_CR}) &  MemReadDataIn[13] & ~CtrlMailBoxJumpInstCycle)
+                                       | ((MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_SENSOR_0})           & ~CtrlMailBoxJumpInstCycle)
+                                       | ((MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_SENSOR_1})           & ~CtrlMailBoxJumpInstCycle)
+                                       | ((MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_SENSOR_2})           & ~CtrlMailBoxJumpInstCycle)
+                                       | ((MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_SENSOR_3})           & ~CtrlMailBoxJumpInstCycle)
+                                       | ((MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_GENERIC_LSB})        & ~CtrlMailBoxJumpInstCycle)
+                                       | ((MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_GENERIC_MSB})        & ~CtrlMailBoxJumpInstCycle)
+                                       | ((MemReadDataIn[7:0] == {TIMESTAMP_DELTA_ADR, TIMESTAMP_DELTA_INT_EVENT})          & ~CtrlMailBoxJumpInstCycle);
+
+
+// Determine if the Wishbone device requires monitoring its busy signal
+//
+// Note: The only device currently supported is the I2C Master IP. This IP
+//       will generate a I2C bus cycle when the "read" or "write"
+//       bits are set in the control register.
+//
+assign wb_busy_poll                    = ((MemReadDataIn[7:0] == {I2C_MASTER_ADR,     I2C_MASTER_CR             }) & (MemReadDataIn[12] | MemReadDataIn[13]) & ~CtrlMailBoxJumpInstCycle)
+                                       | ((MemReadDataIn[7:0] == {SENSOR_MANAGER_ADR, CONTROL_WAIT_INSTR_ADDRESS})                                           & ~CtrlMailBoxJumpInstCycle);
+
+
+// Determine when to start the Sensor Manager Statemachine
+//
+// Note: Use double-rank synchronization to resolve meta-stability issues.
+//
+//       Simulation shows these signals toggle from TLC.v clock domain to
+//       the Sensor Manager's.
+//
+assign StartIn_stb = (StartFromFFE_5ff ^ StartFromFFE_6ff)
+                   | (StartFromTLC_1ff ^ StartFromTLC_2ff);
+
+
+// Define the Sensor Manager Control Registers
+//
+always @(posedge ClockIn or posedge ResetIn) 
+begin
+    if (ResetIn)
+    begin
+		wb_ack_sm             <= 1'b0;
+
+        StartFromFFE_1ff      <= 1'b0;
+        StartFromFFE_2ff      <= 1'b0;
+		StartFromFFE_3ff      <= 1'b0;
+        StartFromFFE_4ff      <= 1'b0;
+		StartFromFFE_5ff      <= 1'b0;
+        StartFromFFE_6ff      <= 1'b0;
+
+        StartFromTLC_1ff      <= 1'b0;
+        StartFromTLC_2ff      <= 1'b0;
+
+		RunSM                 <= 1'b0;
+
+		CtrlReceiveAddressReg <= 10'h0;
+		CtrlRunTimeAddressReg <= 10'h0;
+
+        CtrlRunTimeAddressSM_1ff <=  1'b0;
+        CtrlRunTimeAddressSM_2ff <=  1'b0;
+
+        TimeStamp_Delta_sensor_0 <=  8'h0;
+        TimeStamp_Delta_sensor_1 <=  8'h0;
+        TimeStamp_Delta_sensor_2 <=  8'h0;
+        TimeStamp_Delta_sensor_3 <=  8'h0;
+
+        SensorInterrupt_0_1ff    <=  4'h0;
+        SensorInterrupt_0_2ff    <=  4'h0;
+        SensorInterrupt_0_3ff    <=  4'h0;
+
+        SensorInterrupt_1_1ff    <=  4'h0;
+        SensorInterrupt_1_2ff    <=  4'h0;
+        SensorInterrupt_1_3ff    <=  4'h0;
+
+        SensorInterrupt_2_1ff    <=  4'h0;
+        SensorInterrupt_2_2ff    <=  4'h0;
+        SensorInterrupt_2_3ff    <=  4'h0;
+
+        SensorInterrupt_3_1ff    <=  4'h0;
+        SensorInterrupt_3_2ff    <=  4'h0;
+        SensorInterrupt_3_3ff    <=  4'h0;
+
+        SensorInterrupt_0_o      <=  1'b0;
+        SensorInterrupt_1_o      <=  1'b0;
+        SensorInterrupt_2_o      <=  1'b0;
+        SensorInterrupt_3_o      <=  1'b0;
+
+        SensorInterrupt_event_mask_0 <= 1'b0;
+        SensorInterrupt_event_mask_1 <= 1'b0;
+        SensorInterrupt_event_mask_2 <= 1'b0;
+        SensorInterrupt_event_mask_3 <= 1'b0;
+
+        TimeStamp_Delta_capt     <= 16'h0;
+        TimeStamp_Delta_readback <= 16'h0;
+
+        TimeStamp_Delta_Tog_1ff  <=  1'b0;
+        TimeStamp_Delta_Tog_2ff  <=  1'b0;
+        TimeStamp_Delta_Tog_3ff  <=  1'b0;
+
+        CtrlMailBoxSegmentCtr       <=  6'h0;
+        CtrlMailBoxSegmentCtr_ce    <=  1'b0;
+
+        CtrlMailBoxTablePtr         <= MAILBOX_SM_ADDRESS;
+        CtrlMailBoxJumpInstPtr      <= 10'h0;
+
+        CtrlMailBoxJumpInstCycle    <=  1'b0;
+        CtrlMailBoxJumpInstCycle_ce <=  1'b0;
+
+        control_wait_instr_cntr     <= 13'h0;
+        control_wait_instr_cntr_tc  <=  1'b0;
+        control_wait_instr_busy     <=  1'b0;
+    end
+    else 
+    begin  
+		wb_ack_sm             <= ((MemReadDataIn[7:3] == SENSOR_MANAGER_ADR )
+		                       |  (MemReadDataIn[7:3] == TIMESTAMP_DELTA_ADR)
+		                       |  (CtrlMailBoxJumpInstCycle))                 & wb_cyc & wb_stb & ~wb_ack_sm;
+
+		// Double-rank synchronization between clock domains to avoid meta-state issues
+		//
+
+        StartFromFFE_1ff      <= StartFromFFE;
+        StartFromFFE_2ff      <= StartFromFFE_1ff;
+		StartFromFFE_3ff      <= StartFromFFE_2ff;
+        StartFromFFE_4ff      <= StartFromFFE_3ff;
+		StartFromFFE_5ff      <= StartFromFFE_4ff;
+        StartFromFFE_6ff      <= StartFromFFE_5ff;
+
+        StartFromTLC_1ff      <= StartFromTLC;
+        StartFromTLC_2ff      <= StartFromTLC_1ff;
+
+        CtrlRunTimeAddressSM_1ff <= CtrlRunTimeAddressSM;
+        CtrlRunTimeAddressSM_2ff <= CtrlRunTimeAddressSM_1ff;
+
+		// Define the Sensor Manager Control Register
+        //
+		// Note: A write of "0" to bit "0" of Sensor Manager Register "0" stops execution.
+		//
+		//       The remaining bits of the "control" register can be used for other purposes.
+		//
+		if (StartIn_stb)
+            RunSM             <= 1'b1;
+        else if (control_sensor_manager_reg_dcd)
+            RunSM             <= MemReadDataIn[8];
+
+        // Define the Sensor Manager Receive Address Register
+        //
+        if (control_receive_reg_dcd)
+			CtrlReceiveAddressReg <= MemReadDataIn[17:8];
+
+        // Define the Sensor Manager Run-time Address Register
+        //
+        if (control_runtime_reg_dcd)
+		    CtrlRunTimeAddressReg <= MemReadDataIn[17:8];
+	    else if ( CtrlRunTimeAddressSM_1ff ^ CtrlRunTimeAddressSM_2ff)
+		    CtrlRunTimeAddressReg <= CtrlRunTimeAddressOut;
+
+
+		// Synchronize the interrupt inputs to avoid meta-state issues
+		//
+        SensorInterrupt_0_1ff    <=  SensorInterrupt_0_i;
+        SensorInterrupt_0_2ff    <=  SensorInterrupt_0_1ff;
+        SensorInterrupt_0_3ff    <=  SensorInterrupt_0_2ff;
+
+        SensorInterrupt_1_1ff    <=  SensorInterrupt_1_i;
+        SensorInterrupt_1_2ff    <=  SensorInterrupt_1_1ff;
+        SensorInterrupt_1_3ff    <=  SensorInterrupt_1_2ff;
+
+        SensorInterrupt_2_1ff    <=  SensorInterrupt_2_i;
+        SensorInterrupt_2_2ff    <=  SensorInterrupt_2_1ff;
+        SensorInterrupt_2_3ff    <=  SensorInterrupt_2_2ff;
+
+        SensorInterrupt_3_1ff    <=  SensorInterrupt_3_i;
+        SensorInterrupt_3_2ff    <=  SensorInterrupt_3_1ff;
+        SensorInterrupt_3_3ff    <=  SensorInterrupt_3_2ff;
+
+        TimeStamp_Delta_Tog_1ff  <=  TimeStamp_Delta_Tog_i;
+        TimeStamp_Delta_Tog_2ff  <=  TimeStamp_Delta_Tog_1ff;
+        TimeStamp_Delta_Tog_3ff  <=  TimeStamp_Delta_Tog_2ff;
+
+
+		// Capture the external TimeStamp from the Communication Manager.
+		//
+		// Note: The Communication Manager uses the 32KHz clock for the
+		//       TimeStamp function. In the current application, this is not
+		//       the same clock used for the Sensor Manager. However, the
+		//       Sensor Manager's clock is currently significantly faster than
+		//       the 32KHz clock and can capture the TimeStamp value reliably
+		//       when is receives the TimeStamp toggle signal from the
+		//       Communication Manager.
+		//
+		//       This scheme may need to be revisted if the clock assignments
+		//       change on future designs.
+		//
+		if (TimeStamp_Delta_Tog_2ff ^ TimeStamp_Delta_Tog_3ff)
+            TimeStamp_Delta_capt     <= TimeStamp_Delta_i;
+
+	    // Capture the TimeStamp Value for a "generic" TimeStamp write to SM
+		// Memory.
+		//
+		// Note: The entire TimeStamp value is captured when a write of the
+		//       LSB value to SM Memory is triggered. This allows for the
+		//       writting of the MSB bits without the danger of the TimeStamp
+		//       value changing between writes of each TimeStamp byte to 
+		//       SM Memory.
+		//
+        if (TimeStamp_Delta_lsb_reg_we_dcd)
+            TimeStamp_Delta_readback <= TimeStamp_Delta_capt;
+
+
+		// Capture the time stamp delta when an interrupt is detected.
+		//
+		// Note: See below for the definition of the bit operations.
+		//
+        if (SensorInterrupt_0_2ff && (!SensorInterrupt_0_3ff))
+            TimeStamp_Delta_sensor_0 <=  TimeStamp_Delta_capt;
+
+
+        if (SensorInterrupt_1_2ff && (!SensorInterrupt_1_3ff))
+            TimeStamp_Delta_sensor_1 <=  TimeStamp_Delta_capt;
+
+
+        if (SensorInterrupt_2_2ff && (!SensorInterrupt_2_3ff))
+            TimeStamp_Delta_sensor_2 <=  TimeStamp_Delta_capt;
+
+
+        if (SensorInterrupt_3_2ff && (!SensorInterrupt_3_3ff))
+            TimeStamp_Delta_sensor_3 <=  TimeStamp_Delta_capt;
+
+	    // Set the Interrupt Status Mask bits
+		//
+		// Note: These bits are used "ANDed" with the write signal to clear
+		//       individual status bits. 
+		//
+		//       The alternate way is to write the interrupt status once
+		//       at the end of a series of SM code segments. However, there
+		//       may be a significant amount of time between TimeStamp value
+		//       capture and a single status being written to memory. This 
+		//       can allow the interrupt status to change after the TimeStamp 
+		//       is written to memory. This could result in the assumption 
+		//       of a good TimeStamp when, in fact, the TimeStamp is not 
+		//       valid.
+		//
+        if (SensorInterrupt_event_mask_we_dcd)
+		begin
+            SensorInterrupt_event_mask_0 <= MemReadDataIn[8];
+            SensorInterrupt_event_mask_1 <= MemReadDataIn[9];
+            SensorInterrupt_event_mask_2 <= MemReadDataIn[10];
+            SensorInterrupt_event_mask_3 <= MemReadDataIn[11];
+		end
+
+	    // Set the interrupt event bit for each sensor when an interrupt is
+		// detected.
+		//
+		// Note: Without this "interrupt event bit" is may not be possible to
+		//       know for certain if an interrupt happened. For example,
+		//       a value of "0" may be correct given the right
+		//       sampling period.
+		//
+		//       These status bits assume a positive (i.e. low-to-high)
+		//       interrupt assertion.
+		//
+		//       All interrupts are cleared when this register is read.
+		//
+        if (SensorInterrupt_event_reg_we_dcd && SensorInterrupt_event_mask_0)
+            SensorInterrupt_0_o       <=  1'h0;
+        else if (SensorInterrupt_0_2ff && (!SensorInterrupt_0_3ff))
+            SensorInterrupt_0_o       <=  1'h1;
+
+
+        if (SensorInterrupt_event_reg_we_dcd && SensorInterrupt_event_mask_1)
+            SensorInterrupt_1_o       <=  1'h0;
+        else if (SensorInterrupt_1_2ff && (!SensorInterrupt_1_3ff))
+            SensorInterrupt_1_o       <=  1'h1;
+
+
+        if (SensorInterrupt_event_reg_we_dcd && SensorInterrupt_event_mask_2)
+            SensorInterrupt_2_o       <=  1'h0;
+        else if (SensorInterrupt_2_2ff && (!SensorInterrupt_2_3ff))
+            SensorInterrupt_2_o       <=  1'h1;
+
+
+        if (SensorInterrupt_event_reg_we_dcd && SensorInterrupt_event_mask_3)
+            SensorInterrupt_3_o       <=  1'h0;
+        else if (SensorInterrupt_3_2ff && (!SensorInterrupt_3_3ff))
+            SensorInterrupt_3_o       <=  1'h1;
+
+
+		//  Mail Box Bit Counter
+		//
+		//  Note: Reset Bit Counter between SM Sessions.
+		//
+		//        This counter selects the Mail Box bits corresponding to each
+		//        SM code segment.
+		//
+        if (!BusySM)
+            CtrlMailBoxSegmentCtr    <=  6'h0;
+        else if (CtrlMailBoxSegmentCtr_ce)
+            CtrlMailBoxSegmentCtr    <=  CtrlMailBoxSegmentCtr + 1'b1;
+
+        CtrlMailBoxSegmentCtr_ce     <=  wb_cyc & wb_stb & wb_we & ~wb_ack_sm & CtrlMailBoxJumpInstCycle;
+
+		// Mail Box Table Address Pointer 
+		//
+		// Note: This is the location in SM Memory where the Mail Box is
+		//       located. Typically, the mail box will be in the last four
+		//       18-bit words in SM Memory.
+		//
+		//       This value can be dynamically changed by instructions in SM
+		//       memory.
+		//
+        if (control_mailbox_tbl_ptr_dcd)
+            CtrlMailBoxTablePtr      <=  MemReadDataIn[17:10];
+
+	    // Mail Box Jump Address
+		//
+		// Note: This address must be temporarily storged while the Mail Box
+		//       bits are being read from SM Memory.
+		//
+		//       Based on the Mail Box bit for the current code segment, this
+		//       jump address may or may not be used for a jump.
+		//
+        if (control_mailbox_jump_inst_ptr_dcd)
+            CtrlMailBoxJumpInstPtr   <=  MemReadDataIn[17:8];
+
+	    // Mail Box Jump Decode Cycle Flag
+		//
+		// Note: This flags that the current SM write cycle is a Mail Box Jump
+		//       decode operation. 
+		//
+		//       The data from SM Memory consist of Mail Box bits and should
+		//       not be decoded as a SM "write" instruction would.
+		//
+		//       The decode consists of selecting the correct bit from the 
+		//       Mail Box for the current SM code segment. Based on the state 
+		//       of this bit (i.e. 0 - No Jump; 1 - Jump), the SM instruction 
+		//       pointer will either proceed with the next instruction address 
+		//       or jump to a new code segment.
+		//
+        if (control_mailbox_jump_inst_ptr_dcd)
+            CtrlMailBoxJumpInstCycle <= 1'b1;
+        else if (CtrlMailBoxJumpInstCycle_ce)
+            CtrlMailBoxJumpInstCycle <= 1'b0;
+
+        CtrlMailBoxJumpInstCycle_ce  <= wb_cyc & wb_stb & wb_we &  wb_ack_sm & ~control_mailbox_jump_inst_ptr_dcd;
+
+
+		// Wait Instruction Register
+		//
+        if (control_wait_instr_reg_dcd || control_wait_instr_busy)
+		begin
+            control_wait_instr_cntr      <= control_wait_instr_cntr_nxt;
+            control_wait_instr_cntr_tc   <= control_wait_instr_cntr_tc_nxt;
+		end
+
+        control_wait_instr_busy          <= control_wait_instr_busy_nxt;
+    end
+end   
+
+
+// Define the Wait Instruction Busy signal
+//
+// Note: This busy starts with the first write and ends when the counter is done.
+//
+//       This is an N-1 counter. Therefore, a value of "0" means an "N" of "1".
+//       Therefore, there should be one cycle of busy even with a value of "0".
+//
+assign control_wait_instr_busy_nxt = (~control_wait_instr_busy &  control_wait_instr_reg_dcd)
+                                   | ( control_wait_instr_busy & ~control_wait_instr_cntr_tc);
+	
+
+// Define the operation of the Wait Instruction Counter
+//
+always @(MemReadDataIn           or
+         control_wait_instr_busy or
+         control_wait_instr_cntr
+        )
+begin
+
+    case({control_wait_instr_busy, MemReadDataIn[17]})
+	2'b00:  // MSB == 0 then count  1-to-1
+	begin
+        control_wait_instr_cntr_nxt      <= {4'h0, MemReadDataIn[16:8]        };
+        control_wait_instr_cntr_tc_nxt   <= (      MemReadDataIn[16:8] == 9'h0);
+	end
+	2'b01:  // MSB == 1 then count 16-to-1
+	begin
+        control_wait_instr_cntr_nxt      <= {      MemReadDataIn[16:8],   4'hF}; // Remember: N-1 means that "0" should be one wait period
+        control_wait_instr_cntr_tc_nxt   <= 1'b0;
+	end
+	2'b10:  // Normal Count
+	begin
+        control_wait_instr_cntr_nxt      <=  control_wait_instr_cntr -  13'h1;
+        control_wait_instr_cntr_tc_nxt   <= (control_wait_instr_cntr == 13'h1); 
+	end
+	2'b11:  // Normal Count - The value was shift << 4 so it is already 16x larger at loading time
+	begin
+        control_wait_instr_cntr_nxt      <=  control_wait_instr_cntr -  13'h1;
+        control_wait_instr_cntr_tc_nxt   <= (control_wait_instr_cntr == 13'h1); 
+	end
+	endcase
+end
+
+
+// Use the "run" bit to signal when the statemachine is "busy" in addition to
+// the statemachine busy bit.
+//
+assign BusyOut            = RunSM | BusySM;
+	
+
+// Define the Sensor Manager Memory's read address
+//
+// Note: StateMachine is allowed to read all of SensorManager Memory
+//
+//       The Sensor Manager Memory's "read" port is 10-bits (i.e. [9:0])
+//
+//       Select the Mail Box Address pointer during Mail Box Jump operations.
+//       The location pointed to contains Mail Box Jump enable bits AND NOT 
+//       SM instructions.
+//
+assign MemReadAddressOut  = CtrlMailBoxJumpInstCycle ? {CtrlMailBoxTablePtr, CtrlMailBoxSegmentCtr[5:4]} 
+                                                     :  StateMachineCtrlMemAddr ;
+
+
+// Limit the register write function to the upper half of the Sensor Manager's Memory space
+//
+// Note: The Sensor Manager Memory's "write" port address is 10-bits (i.e. [9:0])
+//
+assign MemWriteAddressOut = CtrlReceiveAddressReg;
+
+
+// Define the Data to be written to Sensor Memory
+//
+// Note: The I2C Master IP only outputs byte wide values
+//
+//       For the current design, the following are read back:
+//           - I2C Master IP is read back
+//           - TimeStamp registers for four sensors
+//           - TimeSTamp related interrupt event register
+//
+//      Only the I2C Master IP was supported in previous designs
+//
+always @(MemReadDataIn            or
+		 MemWriteDataOut          or
+         i2c_masterDataToMem      or
+         TimeStamp_Delta_sensor_0 or
+         TimeStamp_Delta_sensor_1 or
+         TimeStamp_Delta_sensor_2 or
+         TimeStamp_Delta_sensor_3 or
+		 TimeStamp_Delta_readback or
+         SensorInterrupt_0_o      or
+         SensorInterrupt_1_o      or
+         SensorInterrupt_2_o      or
+         SensorInterrupt_3_o    
+        )
+begin
+	case(MemReadDataIn[7:3])
+    I2C_MASTER_ADR:                    MemWriteDataOut <= {1'b0, i2c_masterDataToMem};
+	TIMESTAMP_DELTA_ADR:
+	begin
+		case(MemReadDataIn[2:0])
+        TIMESTAMP_DELTA_SENSOR_0     : MemWriteDataOut <= {1'b0, TimeStamp_Delta_sensor_0};
+        TIMESTAMP_DELTA_SENSOR_1     : MemWriteDataOut <= {1'b0, TimeStamp_Delta_sensor_1};
+        TIMESTAMP_DELTA_SENSOR_2     : MemWriteDataOut <= {1'b0, TimeStamp_Delta_sensor_2};
+        TIMESTAMP_DELTA_SENSOR_3     : MemWriteDataOut <= {1'b0, TimeStamp_Delta_sensor_3};
+        TIMESTAMP_DELTA_GENERIC_LSB  : MemWriteDataOut <= {1'b0, TimeStamp_Delta_readback[7:0]};
+        TIMESTAMP_DELTA_GENERIC_MSB  : MemWriteDataOut <= {1'b0, TimeStamp_Delta_readback[15:8]};
+        TIMESTAMP_DELTA_INT_EVENT    : MemWriteDataOut <= {4'h0, SensorInterrupt_3_o,
+				                                                 SensorInterrupt_2_o,
+															     SensorInterrupt_1_o,
+															     SensorInterrupt_0_o};
+		default:                       MemWriteDataOut <= {1'b0, i2c_masterDataToMem};
+        endcase
+	end
+	default:                           MemWriteDataOut <= {1'b0, i2c_masterDataToMem};
+	endcase
+end
+
+
+// Define the Sensor Manager Memory's clock
+//
+// Note: This is currently a flow through but this may change in future designs.
+//
+assign MemClockOut        = ClockIn;
+
+
+// Combine all Wishbone bus acknowledges
+//
+// Note: Only one acknowledge should happen at a time.
+//
+assign wb_ack             = wb_ack_sm | I2C_wb_ack_i;
+
+
+// Multiplex the address to the I2C Master IP when performing an I2C read
+//
+// Note: The address must be switched from the I2C "Control" Register to the I2C "Transmit/Receive" data address.
+//
+//       This only affects the I2C Master IP and does not affect any other device on the Wishbone bus.
+//
+assign I2C_wb_adr_o       = ((MemReadDataIn[7:0] == {I2C_MASTER_ADR, I2C_MASTER_CR}) &  MemReadDataIn[13] & (~wb_we))   
+                                                                   ? I2C_MASTER_TXR  :  MemReadDataIn[2:0];
+
+
+//------Instantiate Modules----------------
+//
+
+// Instantiate the Sensor Manager Statemachine
+//
+StateMachine StateMachine_inst      (
+
+        .CLK_IN                     ( ClockIn                               ),
+        .RESET_IN                   ( ResetIn                               ),
+
+		.RUNTIME_ADDRESS            ( CtrlRunTimeAddressReg                 ),
+        .CONTROL_JUMP_REG_DCD       ( control_jump_reg_dcd                  ),
+        .SAVE_REG_2_MEM             ( save_reg_2_mem                        ),
+
+        .MAILBOX_JUMP_INST_CYCLE    (CtrlMailBoxJumpInstCycle               ),
+        .MAILBOX_JUMP_INST_PTR      (CtrlMailBoxJumpInstPtr                 ),
+        .MAILBOX_SEGMENT_CTR        (CtrlMailBoxSegmentCtr[3:0]             ),
+
+        .WB_ACK_I                   ( wb_ack                                ),
+        .WB_BUSY_I                  ( I2C_tip_i | control_wait_instr_busy   ),
+		.WB_BUSY_POLL_I             ( wb_busy_poll                          ),
+
+        .WB_WE_O                    ( wb_we                                 ),
+        .WB_STB_O                   ( wb_stb                                ),
+        .WB_CYC_O                   ( wb_cyc                                ),
+
+        .SM_CNTL_REG_RUN            ( RunSM                                 ),
+        .SM_READ_DATA               ( MemReadDataIn                         ), // Data    "Byte" is MemReadDataIn[17:8]
+
+        .SM_INSTR_PTR               ( StateMachineCtrlMemAddr               ),
+        .SM_READ_SELECT             ( MemReadEnableOut                      ),
+
+        .SM_WRITE_SELECT            ( MemWriteEnableOut                     ),
+        .SM_BUSY                    ( BusySM                                )
+
+         );
+
+
+// test points
+//
+assign TP1 = I2C_tip_i;
+assign TP2 = BusyOut;
+assign TP3 = 0;
+
+// Logic to generate SmClockSelect_o
+wire	d_SmClockSelect;
+
+always @(posedge ClockIn or posedge ResetIn) 
+begin
+    if (ResetIn)
+    begin
+		s1_BusyOut  <= 1'b0;
+		s2_BusyOut	<= 1'b0;
+		SmClockSelect_o <= 1'b0;
+	end
+	else
+	begin
+		s1_BusyOut  <= BusyOut;
+		s2_BusyOut	<= s1_BusyOut;
+		SmClockSelect_o <= d_SmClockSelect;
+	end
+end
+
+assign d_SmClockSelect = SmClockSelect_o ? ((!s1_BusyOut && s2_BusyOut) ? 1'b0 : 1'b1) : ((StartFromFFE_1ff ^ StartFromFFE_2ff) ? 1'b1: 1'b0);	
+	
+endmodule
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/StateMachine.v b/BENCHMARK/ULPSH_fabric/rtl/src/StateMachine.v
new file mode 100644
index 0000000..7b5693e
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/StateMachine.v
@@ -0,0 +1,608 @@
+// -----------------------------------------------------------------------------
+// title          : Sensor Manager Statemachine
+// project        : ULP Sensor Hub
+// -----------------------------------------------------------------------------
+// file           : StateMachine.v
+// author         : Glen Gomes
+// company        : QuickLogic Corp
+// created        : 2013/12/06	
+// last update    : 2013/12/06
+// platform       : PolarPro III
+// standard       : Verilog 2001
+// -----------------------------------------------------------------------------
+// description: The Sensor Manger Statemachine is responsible for controlling the
+//              operations of the Sensor Manager. These include performing
+//              transfers between Sensor Memory and various registers.
+// -----------------------------------------------------------------------------
+// copyright (c) 2013
+// -----------------------------------------------------------------------------
+// revisions  :
+// date            version    author         description
+// 2013/12/06      1.0        Glen Gomes     created
+// 2014/05/27      1.1        Glen Gomes     Updated for Tay
+// -----------------------------------------------------------------------------
+// Comments: This solution is specifically for use with the QuickLogic
+//           PolarPro III device. 
+// -----------------------------------------------------------------------------
+
+`timescale 1ns/10ps
+
+module StateMachine (
+
+               CLK_IN,
+               RESET_IN,
+
+			   RUNTIME_ADDRESS,
+               CONTROL_JUMP_REG_DCD,
+               SAVE_REG_2_MEM,
+
+               MAILBOX_JUMP_INST_CYCLE,
+			   MAILBOX_JUMP_INST_PTR,
+			   MAILBOX_SEGMENT_CTR,
+
+               WB_ACK_I,
+               WB_BUSY_I,
+			   WB_BUSY_POLL_I,
+
+               WB_WE_O,
+               WB_STB_O,
+               WB_CYC_O,
+
+               SM_CNTL_REG_RUN,
+               SM_READ_DATA,
+
+               SM_INSTR_PTR,
+               SM_READ_SELECT,
+
+               SM_WRITE_SELECT,
+
+               SM_BUSY
+
+               );
+  
+
+//-----Port Signals--------------------
+//
+
+input          CLK_IN;
+input          RESET_IN;
+
+input    [9:0] RUNTIME_ADDRESS;
+input          CONTROL_JUMP_REG_DCD;
+input          SAVE_REG_2_MEM;
+
+input          MAILBOX_JUMP_INST_CYCLE;
+input    [9:0] MAILBOX_JUMP_INST_PTR;
+input    [3:0] MAILBOX_SEGMENT_CTR;
+
+input          WB_ACK_I;
+input          WB_BUSY_I;
+input          WB_BUSY_POLL_I;
+
+output         WB_WE_O;
+output         WB_STB_O;
+output         WB_CYC_O;
+
+input          SM_CNTL_REG_RUN;
+input   [17:0] SM_READ_DATA;
+
+output   [9:0] SM_INSTR_PTR;
+output         SM_READ_SELECT;
+
+output         SM_WRITE_SELECT;
+
+output         SM_BUSY;
+
+
+wire           CLK_IN;
+wire           RESET_IN;
+
+wire     [9:0] RUNTIME_ADDRESS;
+wire           CONTROL_JUMP_REG_DCD;
+wire           SAVE_REG_2_MEM;
+
+wire           MAILBOX_JUMP_INST_CYCLE;
+wire     [9:0] MAILBOX_JUMP_INST_PTR;
+wire     [3:0] MAILBOX_SEGMENT_CTR;
+
+wire           WB_ACK_I;
+wire           WB_BUSY_I;
+wire           WB_BUSY_POLL_I;
+
+reg            WB_WE_O;
+reg            wb_we_o_nxt;
+
+reg            WB_STB_O;
+reg            wb_stb_o_nxt;
+
+reg            WB_CYC_O;
+reg            wb_cyc_o_nxt;
+
+wire           SM_CNTL_REG_RUN;
+wire    [17:0] SM_READ_DATA;
+
+reg      [9:0] SM_INSTR_PTR;
+reg      [9:0] sm_instr_ptr_nxt;
+
+reg            SM_READ_SELECT;
+reg            sm_read_select_nxt;
+
+reg            SM_WRITE_SELECT;
+reg            sm_write_select_nxt;
+
+reg            SM_BUSY;
+reg            sm_busy_nxt;
+
+//-----Internal Signals--------------------
+//
+
+
+//
+// Define the Statemachine registers
+//
+reg      [3:0] sensor_manager_sm;
+reg      [3:0] sensor_manager_sm_nxt;
+
+
+//
+// Define the Instruction Pointer variables
+//
+
+reg            sm_instr_ptr_ce;
+reg            sm_instr_ptr_ce_nxt;
+
+reg            sm_instr_ptr_ld;
+reg            sm_instr_ptr_ld_nxt;
+
+//reg            sm_instr_ptr_sel;
+//reg            sm_instr_ptr_sel_nxt;
+
+reg            mailbox_jump_inst_ptr_ld;
+
+
+//------Define Parameters---------
+//
+
+//
+// Define the Sensor Manager Statemachine States
+//
+// Note: These states are chosen to allow for overlap of various signals
+//       during operation. This overlap should help reduce timing
+//       dependancies.
+//
+parameter SM_IDLE           = 4'h0;
+parameter SM_INC_PTR        = 4'h1;
+parameter SM_INST_RD        = 4'h2;
+//parameter SM_INST_DCD       = 4'h3; // Note: Will be used for TimeStamp Support in a future design
+parameter SM_REG_WR         = 4'h4;
+parameter SM_REG_RD         = 4'h5;
+parameter SM_WAIT_BUSY_ON   = 4'h6;
+parameter SM_WAIT_BUSY_OFF  = 4'h7;
+
+
+//
+// Sensor Manager Initialization Start Address
+//
+// Note: The previous IP used the reset of the "RuntimeAddress" register to
+//       select the sensor initialization code. This value explicity selects
+//       the value for the start (or re-start) of initialization.
+//
+parameter SM_INIT_INSTR_ADR = 10'h0; // Address for the start in initialization instructions
+
+
+//------Logic Operations----------
+//
+
+//
+// Define the Instruction Pointer
+//
+// Note: This pointer can start at either the sensor initialization code start
+//       address or the run-time code start address. 
+//
+always @( SM_INSTR_PTR            or
+		  sm_instr_ptr_ld         or
+		  sm_instr_ptr_ce         or
+		  SM_READ_DATA            or
+          CONTROL_JUMP_REG_DCD    or
+		  RUNTIME_ADDRESS         or
+          MAILBOX_JUMP_INST_CYCLE or
+          MAILBOX_JUMP_INST_PTR
+		 )
+begin
+	case({sm_instr_ptr_ld, sm_instr_ptr_ce})
+	2'b00: sm_instr_ptr_nxt    <= SM_INSTR_PTR;        // Hold Current Value
+	2'b01: sm_instr_ptr_nxt    <= SM_INSTR_PTR + 1'b1; // Increment to the next address
+	2'b10:
+	begin
+        case({MAILBOX_JUMP_INST_CYCLE, CONTROL_JUMP_REG_DCD})
+        2'b00:   sm_instr_ptr_nxt <= RUNTIME_ADDRESS;        //       Run-time Code Address
+        2'b01:   sm_instr_ptr_nxt <= SM_READ_DATA[17:8];     //           Jump      Address
+        default: sm_instr_ptr_nxt <= MAILBOX_JUMP_INST_PTR;  //  Mail Box Jump      Address
+        endcase
+	end
+	2'b11: sm_instr_ptr_nxt    <= SM_INSTR_PTR;        // Hold Current Value
+	endcase
+end
+
+
+// Select the Mail Box Jump Enable Bit
+//
+// Note: Mail Box Jump enable bits are spread over 16-bits of the 18-bits from 
+//       SM Memory.
+//
+always @( MAILBOX_SEGMENT_CTR      or
+          SM_READ_DATA             or
+	      mailbox_jump_inst_ptr_ld
+        )
+begin
+    case(MAILBOX_SEGMENT_CTR)
+	4'h0: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[0];
+	4'h1: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[1];
+	4'h2: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[2];
+	4'h3: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[3];
+	4'h4: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[4];
+	4'h5: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[5];
+	4'h6: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[6];
+	4'h7: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[7];
+	4'h8: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[9];
+	4'h9: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[10];
+	4'hA: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[11];
+	4'hB: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[12];
+	4'hC: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[13];
+	4'hD: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[14];
+	4'hE: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[15];
+	4'hF: mailbox_jump_inst_ptr_ld <= SM_READ_DATA[16];
+	endcase
+end
+
+
+// Define the registers associated with the Sensor Manager Statemachine
+//
+always @(posedge CLK_IN or posedge RESET_IN) 
+begin
+    if (RESET_IN)
+    begin
+        sensor_manager_sm  <= SM_IDLE;
+
+        SM_INSTR_PTR       <= 10'h0;
+        sm_instr_ptr_ce    <=  1'b0;
+        sm_instr_ptr_ld    <=  1'b0;
+
+        WB_WE_O            <=  1'b0;
+        WB_STB_O           <=  1'b0;
+		WB_CYC_O           <=  1'b0;
+
+        SM_READ_SELECT     <=  1'b0;
+        SM_WRITE_SELECT    <=  1'b0;
+
+        SM_BUSY            <=  1'b0;
+    end
+    else 
+    begin  
+        sensor_manager_sm  <= sensor_manager_sm_nxt;    
+
+        SM_INSTR_PTR       <= sm_instr_ptr_nxt;
+        sm_instr_ptr_ce    <= sm_instr_ptr_ce_nxt;
+        sm_instr_ptr_ld    <= sm_instr_ptr_ld_nxt;
+
+        WB_WE_O            <=  wb_we_o_nxt;
+        WB_STB_O           <=  wb_stb_o_nxt;
+		WB_CYC_O           <=  wb_cyc_o_nxt;
+
+        SM_READ_SELECT     <= sm_read_select_nxt;
+        SM_WRITE_SELECT    <= sm_write_select_nxt;
+
+        SM_BUSY            <= sm_busy_nxt;
+ 	end
+end   
+
+
+// Define the Sensor Manager Statemachine
+//
+always @( sensor_manager_sm        or
+          SM_CNTL_REG_RUN          or
+          CONTROL_JUMP_REG_DCD     or
+          SAVE_REG_2_MEM           or
+          WB_BUSY_I                or
+		  WB_BUSY_POLL_I           or
+		  WB_ACK_I                 or
+          MAILBOX_JUMP_INST_CYCLE  or
+	      mailbox_jump_inst_ptr_ld 
+         )
+begin
+    case(sensor_manager_sm)
+    SM_IDLE:
+	begin
+
+		case(SM_CNTL_REG_RUN)
+		1'b0:    // No Activity
+		begin
+            sensor_manager_sm_nxt <= SM_IDLE;
+
+		    sm_busy_nxt           <= 1'b0;
+            sm_instr_ptr_ld_nxt   <= 1'b0;
+        end
+		1'b1:    // Start at the Sensor Run-Time Code
+		begin
+            sensor_manager_sm_nxt <= SM_INC_PTR;
+
+		    sm_busy_nxt           <= 1'b1;
+            sm_instr_ptr_ld_nxt   <= 1'b1;
+        end
+        endcase
+
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+		wb_stb_o_nxt          <= 1'b0;
+		wb_cyc_o_nxt          <= 1'b0;
+	end
+    SM_INC_PTR:
+	begin
+        sensor_manager_sm_nxt <= SM_INST_RD;
+
+		sm_busy_nxt           <= 1'b1;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b1;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+		wb_stb_o_nxt          <= 1'b0;
+		wb_cyc_o_nxt          <= 1'b0;
+	end
+    SM_INST_RD:
+	begin
+        sensor_manager_sm_nxt <= SM_REG_WR;
+
+		sm_busy_nxt           <= 1'b1;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b1;
+		wb_stb_o_nxt          <= 1'b1;
+		wb_cyc_o_nxt          <= 1'b1;
+	end
+    SM_REG_WR:
+	begin
+
+        sm_read_select_nxt    <= 1'b0;
+
+		case(SM_CNTL_REG_RUN)
+		1'b0:  // A write of "0" to bit "0" of the Command register at address "0" turns off 
+			   // the Sensor Manager's Statemachine
+		begin
+		    sensor_manager_sm_nxt <= SM_IDLE;
+
+		    sm_busy_nxt           <= 1'b0;
+
+            sm_instr_ptr_ld_nxt   <= 1'b0;
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_we_o_nxt           <= 1'b0;
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+		end
+		1'b1: // Sensor Manager Statemachine is not stopped; continue processing
+		begin
+		    sm_busy_nxt           <= 1'b1;
+
+		    case({WB_BUSY_POLL_I, WB_ACK_I})
+            2'b00:    // Wait for Wish Bone Acknowledge and no need to wait for transfer complete
+	        begin
+		    	sensor_manager_sm_nxt <= SM_REG_WR;
+
+                sm_instr_ptr_ld_nxt   <= 1'b0;
+                sm_instr_ptr_ce_nxt   <= 1'b0;
+
+                sm_write_select_nxt   <= 1'b0;
+
+		        wb_we_o_nxt           <= 1'b1;
+		        wb_stb_o_nxt          <= 1'b1;
+		        wb_cyc_o_nxt          <= 1'b1;
+		    end
+            2'b01:    // Wish Bone Acknowledge Received and no need to wait for transfer complete
+	        begin
+                case(SAVE_REG_2_MEM)
+				1'b0: 
+				begin
+			        sensor_manager_sm_nxt <= SM_INC_PTR;
+
+					sm_instr_ptr_ld_nxt   <=   CONTROL_JUMP_REG_DCD
+                                          |   (MAILBOX_JUMP_INST_CYCLE & mailbox_jump_inst_ptr_ld);
+
+                    sm_instr_ptr_ce_nxt   <= ~ CONTROL_JUMP_REG_DCD
+                                          &  ~ MAILBOX_JUMP_INST_CYCLE;
+
+                    sm_write_select_nxt   <= 1'b0;
+
+		            wb_we_o_nxt           <= 1'b0;
+		            wb_stb_o_nxt          <= 1'b0;
+		            wb_cyc_o_nxt          <= 1'b0;
+				end
+				1'b1: 
+				begin
+			        sensor_manager_sm_nxt <= SM_REG_RD;
+
+                    sm_instr_ptr_ld_nxt   <= 1'b0;
+                    sm_instr_ptr_ce_nxt   <= 1'b0;
+
+                    sm_write_select_nxt   <= 1'b1;
+
+		            wb_we_o_nxt           <= 1'b0;
+		            wb_stb_o_nxt          <= 1'b1;
+		            wb_cyc_o_nxt          <= 1'b1;
+				end
+		        endcase
+		    end
+            2'b10:    // Wait for Wish Bone Acknowledge and will need to wait for transfer complete
+	        begin
+			    sensor_manager_sm_nxt <= SM_REG_WR;
+
+                sm_instr_ptr_ld_nxt   <= 1'b0;
+                sm_instr_ptr_ce_nxt   <= 1'b0;
+
+                sm_write_select_nxt   <= 1'b0;
+
+		        wb_we_o_nxt           <= 1'b1;
+		        wb_stb_o_nxt          <= 1'b1;
+		        wb_cyc_o_nxt          <= 1'b1;
+		    end
+            2'b11:     // Acknowledge received but need to wait for transfer complete
+	        begin
+			    sensor_manager_sm_nxt <= SM_WAIT_BUSY_ON;
+
+                sm_instr_ptr_ld_nxt   <= 1'b0;
+                sm_instr_ptr_ce_nxt   <= 1'b0;
+
+                sm_write_select_nxt   <= 1'b0;
+
+		        wb_we_o_nxt           <= 1'b0;
+		        wb_stb_o_nxt          <= 1'b0;
+		        wb_cyc_o_nxt          <= 1'b0;
+		    end
+            endcase
+		end
+        endcase
+	end
+    SM_REG_RD:
+	begin
+		sm_busy_nxt           <= 1'b1;
+
+        sm_read_select_nxt    <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+
+		case(WB_ACK_I)
+        1'b0:    // Waiting for Wish Bone Acknowledge
+		begin
+            sensor_manager_sm_nxt <= SM_REG_RD;
+
+            sm_instr_ptr_ld_nxt   <= 1'b0;
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+
+            sm_write_select_nxt   <= 1'b1;
+
+		    wb_stb_o_nxt          <= 1'b1;
+		    wb_cyc_o_nxt          <= 1'b1;
+        end
+        1'b1:    // Got Wish Bone Acknowledge
+        begin
+            sensor_manager_sm_nxt <= SM_INC_PTR;
+
+            sm_instr_ptr_ld_nxt   <=  CONTROL_JUMP_REG_DCD;
+            sm_instr_ptr_ce_nxt   <= ~CONTROL_JUMP_REG_DCD;
+
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+        end
+        endcase
+	end
+    SM_WAIT_BUSY_ON:
+	begin
+		sm_busy_nxt           <= 1'b1;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+		wb_stb_o_nxt          <= 1'b0;
+		wb_cyc_o_nxt          <= 1'b0;
+
+        case(WB_BUSY_I)
+        1'b0: sensor_manager_sm_nxt <= SM_WAIT_BUSY_ON;    // Wait for Busy from I/F
+        1'b1: sensor_manager_sm_nxt <= SM_WAIT_BUSY_OFF;   // Got      Busy from I/F
+        endcase
+	end
+    SM_WAIT_BUSY_OFF:
+	begin
+		sm_busy_nxt           <= 1'b1;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+
+	    wb_we_o_nxt           <= 1'b0;
+
+        case({SAVE_REG_2_MEM, WB_BUSY_I})
+        2'b00:    // Wishbone transfer complete; no need to write anything to Sensor Manager Memory
+				  // 
+				  // Note: Writes to the command register do not enter this state. 
+				  //       Therefore, there is no need to check for the end of processing.
+		begin
+			sensor_manager_sm_nxt <= SM_INC_PTR;
+
+            sm_instr_ptr_ce_nxt   <= 1'b1;
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+		end
+        2'b01:    // Wait for Wishbone transfer to complete
+		begin
+			sensor_manager_sm_nxt <= SM_WAIT_BUSY_OFF;
+
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+		end
+        2'b10:    // Wishbone transfer complete; Write resulting register value to Sensor Manager Memory
+		begin
+			sensor_manager_sm_nxt <= SM_REG_RD;
+
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+            sm_write_select_nxt   <= 1'b1;
+
+		    wb_stb_o_nxt          <= 1'b1;
+		    wb_cyc_o_nxt          <= 1'b1;
+		end
+        2'b11:    // Wait for Wishbone transfer to complete
+		begin
+			sensor_manager_sm_nxt <= SM_WAIT_BUSY_OFF;
+
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+		end
+        endcase
+	end
+	default:
+	begin
+        sensor_manager_sm_nxt <= SM_IDLE;
+
+		sm_busy_nxt           <= 1'b0;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+		wb_stb_o_nxt          <= 1'b0;
+		wb_cyc_o_nxt          <= 1'b0;
+	end
+	endcase
+end	
+
+endmodule
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/SystemClockControl.v b/BENCHMARK/ULPSH_fabric/rtl/src/SystemClockControl.v
new file mode 100644
index 0000000..448ec80
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/SystemClockControl.v
@@ -0,0 +1,128 @@
+
+`timescale 1ns / 10ps
+
+module SystemClockControl (
+	OperatingClockRef_i,
+	Clock32KIn_i,
+	SPIClock_i,
+	ResetIn_i,
+	
+	FfeClkSelect_i,
+	SmClkSelect_i,
+	SmSpeedSelect_i,
+	SpiClkSelect_i,
+	ClkSourceSelect_i,
+	Clk32KhzEnable_i,
+	MainClkEnable_i,
+	FfeClkEnable_i,
+	CM_AutoDrain_Busy,
+	
+	SmClock_o,
+	FfeClock_o,
+	FfeClock_x2_o,
+	clock_32KHz_o,
+	multiplierClk_o,
+	ClockGen_State_o,
+	CM_FIFO_ReadClk,
+	
+	clk_ringosc_i,
+	clk_ringosc_x2_i,
+	enable_i,
+	clk_cal_value_o,
+	assp_ringosc_en_o
+);
+
+// IO Declaration
+input			OperatingClockRef_i;
+input			Clock32KIn_i;
+input			SPIClock_i;
+input			ResetIn_i;
+	
+input	[2:0]	FfeClkSelect_i;
+input	[2:0]	SmClkSelect_i;
+input			SmSpeedSelect_i;
+input			SpiClkSelect_i;
+input			ClkSourceSelect_i;
+input			Clk32KhzEnable_i;
+input			MainClkEnable_i;
+input			FfeClkEnable_i;
+input			CM_AutoDrain_Busy;
+
+output			SmClock_o;
+output			FfeClock_o;
+output			FfeClock_x2_o;
+output			clock_32KHz_o;
+output			multiplierClk_o;
+output	[3:0]	ClockGen_State_o;
+output			CM_FIFO_ReadClk;
+
+input			clk_ringosc_i;
+input			clk_ringosc_x2_i;
+input			enable_i;
+output	[15:0]	clk_cal_value_o;
+output			assp_ringosc_en_o;
+
+reg				multiplierClk_o;
+wire	[3:0]	ClockGen_State_o;
+wire			CM_FIFO_ReadClk;
+wire			assp_ringosc_en_o;
+
+
+
+// Internal Signals Declaration
+wire			highSpeedClock, highSpeedClock_buff, highSpeedClock_x2_buff;
+reg		[6:0]	ClockDiv;
+wire			FfeClock;
+reg				SmClock;
+wire			RingOscEnable;
+wire			ring_osc_clk;
+wire			OperatingClockRef;
+
+	
+// Operations
+
+// Gating the enternal osc
+// assign	OperatingClockRef = OperatingClockRef_i && MainClkEnable_i;
+assign	OperatingClockRef = OperatingClockRef_i;
+
+// CM FIFO AutoDrain Read Clock
+// assign CM_FIFO_ReadClk = CM_AutoDrain_Busy ? (FfeClock && FfeClkEnable_i): SPIClock_i;
+assign CM_FIFO_ReadClk = CM_AutoDrain_Busy ? highSpeedClock_buff : SPIClock_i;
+
+// Ring Osclilator enable when the when weither FFE or SM is busy
+// assign RingOscEnable = !ResetIn_i && MainClkEnable_i && ClkSourceSelect_i;
+
+// Logic to gate 32KHz clock when the ULPSH goes to sleep
+// Only static power consumption
+assign	clock_32KHz_o = Clock32KIn_i && Clk32KhzEnable_i;
+
+// Logic to select between the external high speed clock and the internal ring oscillation
+// and main clock division
+// assign	highSpeedClock = ClkSourceSelect_i ?  ring_osc_clk : OperatingClockRef;
+buff buff_highSpeedClock (.A(clk_ringosc_i), .Q(highSpeedClock_buff));	// don't use a clock network for this
+//pragma attribute buff_highSpeedClock dont_touch true
+
+buff buff_highSpeedClock_x2 (.A(clk_ringosc_x2_i), .Q(highSpeedClock_x2_buff));	// don't use a clock network for this
+//pragma attribute buff_highSpeedClock_x2 dont_touch true
+
+
+
+// FFE CLK and SM CLK select and masking
+// assign FfeClock_o = SpiClkSelect_i ? SPIClock_i : FfeClock && FfeClkEnable_i;
+// assign SmClock_o = SmSpeedSelect_i ? SmClock : (SpiClkSelect_i ? SPIClock_i : FfeClock);
+assign FfeClock_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_buff;
+assign FfeClock_x2_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_x2_buff;
+assign SmClock_o = SpiClkSelect_i ? SPIClock_i : highSpeedClock_buff;
+
+
+ring_osc_adjust ring_osc_adjust_1 (
+		.reset_i			( ResetIn_i				),
+		.clk_ringosc_i		( clk_ringosc_i			),
+		.clk_32khz_i		( Clock32KIn_i			),
+		.enable_i			( enable_i				),
+		.cal_val_o			( clk_cal_value_o		)
+	);
+
+assign assp_ringosc_en_o = ClkSourceSelect_i || MainClkEnable_i;
+	
+endmodule
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/TLC.v b/BENCHMARK/ULPSH_fabric/rtl/src/TLC.v
new file mode 100644
index 0000000..36c0476
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/TLC.v
@@ -0,0 +1,731 @@
+
+/*------------------------------------------------------------------------------------------
+Title:			TLC.v
+Description:
+
+--------------------------------------------------------------------------------------------
+Revision History:
+
+--------------------------------------------------------------------------------------------
+To Do:
+
+
+------------------------------------------------------------------------------------------*/
+
+`timescale 1ns / 10ps
+
+`include "SensorHubDefines.v"
+`include "ulpsh_rtl_defines.v"
+
+module TLC (
+	// General interface
+	input				SPI_SCLK,
+	input				FFE_Clock,
+	input				Clock32KIn,
+	input				ResetIn,
+	output				SW_Reset,
+
+	output	reg			RingOsc_cal_en,
+	output	reg	[2:0]	RingOsc_select,
+	input		[15:0]	RingOsc_cal_value,
+
+	input				I2C_Master_Error,
+	input				FFEBusyIn,
+	input				SMBusyIn,
+	input				SMOverrunIn,
+	output				StartFFEOut,
+//	output 				InitSMOut,              // Removed for Rel 0 on 6/18
+	output				StartSMOut,
+	output reg	[15:0]	TimeStampOut,
+	output reg	      	TimeStampOut_Tog,
+	output				UseFastClockOut,
+
+	input		[7:0]	InterruptMsgFromFFEIn,
+	output				InterruptPinOut,
+	input				SensorInterruptIn,
+
+	output		[31:0]	FFE_Mailbox_Out,
+
+	input		[9:0]	CtrlRunTimeAddressReg,  // Expanded for Rel 0 on 6/18
+	output reg	[9:0]	CtrlRunTimeAddressOut,  // Expanded for Rel 0 on 6/18
+	output reg			CtrlRunTimeAddressSM,
+
+	// Interface to SPI Slave
+	input 		[6:0]	RegAddrIn,
+	input 		[7:0]	RegDataIn,
+	output reg	[7:0] 	RegDataOut,
+	input 				RegWriteEnableIn,
+	input 				RegReadDataAckIn,
+
+	// Interface to memories
+	output				TLCDrivingFFEControlMem,
+	output				TLCDrivingFFEDataMem1,
+	output				TLCDrivingFFEDataMem2,
+	output				TLCDrivingSMMem,
+	output				TLCDrivingCMMem,
+	output				MemorySelect_en,
+	output		[2:0]	MemorySelect,
+	output		[11:0]	MemoryAddressOut,
+	output		[35:0]	MemoryDataOut,
+	input 		[35:0]	MemoryDataIn,
+	output reg			MemoryReadEnableOut,
+	output reg			MemoryWriteEnableOut,
+	output				MemoryClockOut,
+
+	// Interface to Communication Manager FIFO
+	output	reg			CM_FIFO_ReadEnable,
+	input		[8:0]	CM_FIFO_ReadData,
+	input		[3:0]	CM_FIFO_PopFlags,
+	input		[3:0]	CM_FIFO_PushFlags,
+	input				CM_FIFO_Overflow,
+	output				CM_RingBufferMode,
+	input				CM_AutoDrain_Busy,
+	
+	// test points
+	output				TP1,
+	output				TP2,
+	
+	// LEDs ON/OFF Control
+	output reg	[2:0]	leds_off_o,
+	
+	// FFE CLock ENable
+	output	reg			FFE_CLK_Enable_o,
+	output	reg			ClockEnable_o,
+	output	reg			clock_32KHz_Enable_o,
+	output	reg	[2:0]	FFE_Clock_Control_o,
+	output	reg	[2:0]	SM_Clock_Control_o,
+	output	reg			ClkSourceSelect_o
+);
+
+	parameter		CYCLES_PER_MSEC = 33;		// number of 32.768KHz clock cycles per millisecond
+
+	reg		[7:0]	CommandReg;
+	reg		[7:0]	msecs_per_sample_reg;
+	reg		[7:0]	MemSelect_reg;
+	reg		[7:0]	MemAddrLow;
+	reg		[7:0]	MemAddrHigh;
+	reg		[7:0]	MemDataByte0;
+	reg		[7:0]	MemDataByte1;
+	reg		[7:0]	MemDataByte2;
+	reg		[7:0]	MemDataByte3;
+	reg		[3:0]	MemDataByte4;
+	reg		[7:0]	CM_Control_reg;
+	reg				WaitForMemRead;
+	reg				WaitForMemWrite;
+	reg				IncrementMemAddr;
+	reg				StartFFE_32K, StartFFE_Clkin;
+//	reg				InitSM_Clkin;              // Removed for Rel 0 on 6/18
+	reg				StartSM_Clkin;
+
+	reg		[7:0]	clock32K_count;		// this needs to be wide enough to accomodate the CYCLES_PER_MSEC constant
+	reg		[7:0]	count_msecs;
+	wire			pulse_1ms;
+	wire			pulse_sample_period;
+	reg				pulse_sample_period_reg;
+	wire			FFE_Holdoff;		// Used to ensure a full count on the First FFE run
+	reg				FFE_Holdoff_reset;
+	reg				FFE_Holdoff_preset;
+
+	wire			RunFFEContinuously;
+	//wire			RunFFEOnce;
+	//wire			RunSMOnce;
+	//wire			RunSensorInit;
+
+	wire			CM_FIFO_Overflow_reg;
+	reg		[3:0]	CM_FIFO_PopFlags_r1;
+	reg		[3:0]	CM_FIFO_PopFlags_r2;
+	reg		[3:0]	CM_FIFO_PopFlags_sync;
+	
+	wire			I2C_Master_Error_reg;
+	
+	reg		[7:0]	InterruptCtrl_reg;
+	reg		[7:0] 	InterruptFFEMsg_clear;
+	wire			Interrupt_En_0;
+	wire	[7:0]	InterruptFFEMsg_latched;
+	wire			InterruptFFEMsg_ORed;
+
+	reg				SW_Reset_Start;
+	reg				SW_Reset_r1;
+	reg				SW_Reset_r2;
+
+	reg				RunFFEContinuously_r1;
+	reg				RunFFEContinuously_r2;
+
+	reg				FFEOverrun;
+	reg		[31:0]	FFE_Mailbox_reg;
+	
+	wire			i_StartFFEOut;
+	reg				s1_StartFFEOut, s2_StartFFEOut;
+	reg				s3_FFEBusyIn, s2_FFEBusyIn, s1_FFEBusyIn;
+	reg				d_FFE_CLK_Enable;
+	reg				s1_SMBusyIn, s2_SMBusyIn, s3_SMBusyIn;
+	wire			d_ClockEnable;
+	wire 			smInit_enable;
+//	reg				s1_InitSM_Clkin, s2_InitSM_Clkin, s3_InitSM_Clkin, s4_InitSM_Clkin, s5_InitSM_Clkin, s6_InitSM_Clkin;   // Removed for Rel 0 on 6/18
+	reg				s1_StartSM_Clkin, s2_StartSM_Clkin, s3_StartSM_Clkin, s4_StartSM_Clkin, s5_StartSM_Clkin, s6_StartSM_Clkin;
+	wire	[2:0]	FFE_SET, SM_SET;
+	wire			clkSourceSelect;
+	reg				SleepMode, IntInputLevel;
+	reg				sensorInterrupt_s1, sensorInterrupt_s2, sensorInterrupt_s3;
+	wire			sleepModeSet, sleepReset;
+
+
+
+	assign FFE_Mailbox_Out			= {FFE_Mailbox_reg[15:0], FFE_Mailbox_reg[31:16]};
+	assign MemoryClockOut			= SPI_SCLK;
+
+	assign RunFFEContinuously		= CommandReg[0];
+	//assign RunFFEOnce				= CommandReg[1];
+	//assign RunSMOnce				= CommandReg[2];
+	//assign RunSensorInit			= CommandReg[3];
+	//assign SW_Reset				= CommandReg[6];
+	assign UseFastClockOut			= CommandReg[7];
+
+	assign Interrupt_En_0			= InterruptCtrl_reg[0];
+	assign Interrupt_En_1			= InterruptCtrl_reg[1];
+
+	assign TLCDrivingFFEControlMem	= MemSelect_reg[7] ? (MemSelect_reg[2:0] == 3'b000) : 1'b0;
+	assign TLCDrivingFFEDataMem1	= MemSelect_reg[7] ? (MemSelect_reg[2:0] == 3'b001) : 1'b0;
+	assign TLCDrivingFFEDataMem2	= MemSelect_reg[7] ? (MemSelect_reg[2:0] == 3'b010) : 1'b0;
+	assign TLCDrivingSMMem			= MemSelect_reg[7] ? (MemSelect_reg[2:0] == 3'b011) : 1'b0;
+	assign TLCDrivingCMMem			= 1'b0;		// should be removed, since the CMMem is now the CM FIFO
+	assign MemorySelect_en			= MemSelect_reg[7];
+	assign MemorySelect				= MemSelect_reg[2:0];
+
+	assign MemoryAddressOut			= {MemAddrHigh[3:0],MemAddrLow};
+	assign MemoryDataOut			= {MemDataByte4[3:0],MemDataByte3,MemDataByte2,MemDataByte1,MemDataByte0};
+
+	assign CM_RingBufferMode		= CM_Control_reg[0];
+	
+
+
+	// requests to run FFE and Sensor Manager
+
+	assign pulse_1ms			= (clock32K_count == (CYCLES_PER_MSEC - 1));		// 1-clock pulse each time 1ms has elapsed
+	assign pulse_sample_period	= (pulse_1ms && (count_msecs == 1));	// 1-clock pulse @ each sample period
+
+	assign StartFFEOut = s2_StartFFEOut;
+	// Delay starting FFE
+	always @(posedge Clock32KIn or posedge ResetIn)
+	begin
+		if (ResetIn)
+		begin
+			s1_StartFFEOut <= 1'b0;
+			s2_StartFFEOut <= 1'b0;
+		end
+		else
+		begin
+			s1_StartFFEOut <= i_StartFFEOut;
+			s2_StartFFEOut <= s1_StartFFEOut;
+		end
+	end
+	
+	// Synchronized FFE Busy input
+	// & logic to generate FFE_CLK_Enable (active when timer starts and off when busy end)
+	always @(posedge Clock32KIn or posedge ResetIn) 
+	begin
+		if (ResetIn) 
+		begin
+			s1_FFEBusyIn <= 0;
+			s2_FFEBusyIn <= 0;
+			s3_FFEBusyIn <= 0;
+		end
+		else 
+		begin
+			s1_FFEBusyIn <= FFEBusyIn;
+			s2_FFEBusyIn <= s1_FFEBusyIn;
+			s3_FFEBusyIn <= s2_FFEBusyIn;
+		end	
+	end
+
+always @*
+begin
+	if (!FFE_CLK_Enable_o)
+		d_FFE_CLK_Enable = s1_StartFFEOut ^ i_StartFFEOut;
+	else
+		if (s3_FFEBusyIn && !s2_FFEBusyIn)
+			d_FFE_CLK_Enable = 1'b0;
+		else
+			d_FFE_CLK_Enable = FFE_CLK_Enable_o;
+end
+
+always @(posedge Clock32KIn or posedge ResetIn) 
+	begin
+		if (ResetIn) 
+		begin
+			FFE_CLK_Enable_o <= 0;
+		end
+		else 
+		begin
+			FFE_CLK_Enable_o <= d_FFE_CLK_Enable;
+		end
+	end	
+	
+
+	always @(posedge Clock32KIn or posedge ResetIn) begin
+		if (ResetIn) begin
+			clock32K_count			<= 0;
+			count_msecs				<= 1;		// reset to 1 (sample period = 0 does not make sense, and should be invalid)
+			pulse_sample_period_reg	<= 0;
+			TimeStampOut			<= 0;
+			TimeStampOut_Tog		<= 0;
+			StartFFE_32K			<= 0;
+			FFEOverrun				<= 0;
+		end else begin
+
+			pulse_sample_period_reg	<= pulse_sample_period;		// de-glitch the pulse_sample_period signal, since it's used to asynchronously reset FFE_Holdoff
+
+			if (pulse_1ms) begin
+				clock32K_count   <= 0;
+				TimeStampOut     <= TimeStampOut + 1;				// the timestamp increments @ 1ms
+				TimeStampOut_Tog <= ~TimeStampOut_Tog;				// the timestamp increments @ 1ms
+			end else begin
+				clock32K_count   <= clock32K_count + 1;
+				TimeStampOut     <= TimeStampOut;
+				TimeStampOut_Tog <= TimeStampOut_Tog;
+			end
+
+			if (pulse_sample_period)							// sample period boundary
+				count_msecs <= msecs_per_sample_reg;				// reset the msec counter back to the register value
+			else
+				if (pulse_1ms)
+					count_msecs <= count_msecs - 1;					// decrement by 1 @ the 1ms boundary
+				else
+					count_msecs <= count_msecs;
+
+
+			//if ((clock32K_count == (CYCLES_PER_MSEC - 1)) && (count_msecs == 1)) begin		// msec counter about to be reset back to the register value
+			if (pulse_sample_period && !SleepMode) begin								// msec counter about to be reset back to the register value
+				if (RunFFEContinuously && !FFE_Holdoff) begin			// trigger a run only if FFE_Holdoff has been deactivated
+					if (FFEBusyIn) begin
+						FFEOverrun <= 1'b1;
+					end else begin
+						StartFFE_32K <= ~StartFFE_32K;
+						//CMBufferBeingWrittenOut <= CMBufferBeingWrittenOut + 1;
+						//if (!AlternateI2CIsActiveIn) begin // If Alternate I2C is active, then we are reading the buffer
+						//	CMBufferBeingRead <= CMBufferBeingWrittenOut;
+						//end
+					end
+				end
+			end
+
+		end
+	end
+
+
+
+	// software-controlled reset, 1-2 clock pulses wide @ the 32K clock
+
+	// generate a one-clock pulse @ the SPI_SCLK, to be used to preset a flop running in the 32K clock domain
+	always @(posedge SPI_SCLK)
+		if (RegWriteEnableIn && (RegAddrIn == `CommandReg) && RegDataIn[6])		// SW Reset control bit is being written
+			SW_Reset_Start <= 1;
+		else
+			SW_Reset_Start <= 0;
+
+	// 32K clock domain, the r1 flop gets preset by the SPI clock pulse above, and only gets deactivated after another 32K clock period (using the r2 flop)
+	always @(posedge Clock32KIn or posedge SW_Reset_Start)
+		if (SW_Reset_Start)
+			SW_Reset_r1 <= 1;
+		else
+			if (SW_Reset_r1 && !SW_Reset_r2)
+				SW_Reset_r1 <= 1;
+			else
+				SW_Reset_r1 <= 0;
+
+	// r2 flop, used to stretch the generated reset pulse
+	always @(posedge Clock32KIn)
+		SW_Reset_r2 <= SW_Reset_r1;
+
+
+	assign SW_Reset = SW_Reset_r2;
+
+
+	// When running the FFE continuously, this logic prevents the FFE from running until the start of a sample period
+
+	always @(posedge SPI_SCLK or posedge ResetIn)
+		if (ResetIn)
+			FFE_Holdoff_preset <= 0;
+		else
+			if (RegWriteEnableIn && (RegAddrIn == `CommandReg) && RegDataIn[0])		// Run FFE Continuously control bit is being written...
+				FFE_Holdoff_preset <= 1;											// ... assert FFE_Holdoff
+			else
+				FFE_Holdoff_preset <= 0;
+
+	always @(posedge Clock32KIn or posedge ResetIn)
+		if (ResetIn)
+			FFE_Holdoff_reset <= 0;
+		else
+			if (pulse_sample_period_reg && RunFFEContinuously && FFE_Holdoff)		// reset FFE_Holdoff when the first timer expiration occurs, to ensure a full first run
+				FFE_Holdoff_reset <= 1;
+			else
+				FFE_Holdoff_reset <= 0;
+
+	dff_pre_clr dff_pre_clr_FFE_Holdoff ( .CLK(1'b0) , .CLR(FFE_Holdoff_reset), .D(1'b0), .PRE(FFE_Holdoff_preset), .Q(FFE_Holdoff) );
+
+
+	
+	// latch the I2C Master Error signal
+	dff_pre_clr dff_pre_clr_I2C_Master_Error ( .CLK(1'b0) , .CLR(ResetIn), .D(1'b0), .PRE(I2C_Master_Error), .Q(I2C_Master_Error_reg) );
+
+
+
+	// interrupt logic
+
+	// note: InterruptMsgFromFFEIn should be de-glitched externally (currently de-glitched in FFE_Control.v)
+
+	// logic to clear the FFE msg interrupts
+	always @(posedge SPI_SCLK)
+		if (RegWriteEnableIn && (RegAddrIn == `InterruptFFEMsg))
+			InterruptFFEMsg_clear <= RegDataIn[7:0];
+		else
+			InterruptFFEMsg_clear <= 8'b0;
+
+	// latch the interrupt msg from the FFE, clear when the InterruptFFEMsg register is being written
+	dff_pre_clr dff_pre_clr_InterruptFFEMsg_0 ( .CLK(1'b0) , .CLR(InterruptFFEMsg_clear[0]), .D(1'b0), .PRE(InterruptMsgFromFFEIn[0]), .Q(InterruptFFEMsg_latched[0]) );
+	dff_pre_clr dff_pre_clr_InterruptFFEMsg_1 ( .CLK(1'b0) , .CLR(InterruptFFEMsg_clear[1]), .D(1'b0), .PRE(InterruptMsgFromFFEIn[1]), .Q(InterruptFFEMsg_latched[1]) );
+	dff_pre_clr dff_pre_clr_InterruptFFEMsg_2 ( .CLK(1'b0) , .CLR(InterruptFFEMsg_clear[2]), .D(1'b0), .PRE(InterruptMsgFromFFEIn[2]), .Q(InterruptFFEMsg_latched[2]) );
+	dff_pre_clr dff_pre_clr_InterruptFFEMsg_3 ( .CLK(1'b0) , .CLR(InterruptFFEMsg_clear[3]), .D(1'b0), .PRE(InterruptMsgFromFFEIn[3]), .Q(InterruptFFEMsg_latched[3]) );
+	dff_pre_clr dff_pre_clr_InterruptFFEMsg_4 ( .CLK(1'b0) , .CLR(InterruptFFEMsg_clear[4]), .D(1'b0), .PRE(InterruptMsgFromFFEIn[4]), .Q(InterruptFFEMsg_latched[4]) );
+	dff_pre_clr dff_pre_clr_InterruptFFEMsg_5 ( .CLK(1'b0) , .CLR(InterruptFFEMsg_clear[5]), .D(1'b0), .PRE(InterruptMsgFromFFEIn[5]), .Q(InterruptFFEMsg_latched[5]) );
+	dff_pre_clr dff_pre_clr_InterruptFFEMsg_6 ( .CLK(1'b0) , .CLR(InterruptFFEMsg_clear[6]), .D(1'b0), .PRE(InterruptMsgFromFFEIn[6]), .Q(InterruptFFEMsg_latched[6]) );
+	dff_pre_clr dff_pre_clr_InterruptFFEMsg_7 ( .CLK(1'b0) , .CLR(InterruptFFEMsg_clear[7]), .D(1'b0), .PRE(InterruptMsgFromFFEIn[7]), .Q(InterruptFFEMsg_latched[7]) );
+	
+
+
+	assign InterruptFFEMsg_ORed = |InterruptFFEMsg_latched[7:0];
+
+	// drive the interrupt output pin: active-high, level sensitive
+	assign InterruptPinOut = (Interrupt_En_0 && InterruptFFEMsg_ORed) ||
+	                         (Interrupt_En_1 && (I2C_Master_Error_reg || SMOverrunIn || FFEOverrun));
+
+	
+	
+	// overflow detection bit
+	
+	dff_pre_clr dff_pre_clr_overflow ( .CLK(1'b0) , .CLR(ResetIn), .D(1'b0), .PRE(CM_FIFO_Overflow), .Q(CM_FIFO_Overflow_reg) );
+
+	
+	// sync the FIFO flags to the SPI clock domain
+	always @(posedge SPI_SCLK) begin
+		CM_FIFO_PopFlags_r1 <= CM_FIFO_PopFlags;
+		CM_FIFO_PopFlags_r2 <= CM_FIFO_PopFlags_r1;
+		if (CM_FIFO_PopFlags_r1 == CM_FIFO_PopFlags_r2)
+			CM_FIFO_PopFlags_sync <= CM_FIFO_PopFlags_r2;
+		else
+			CM_FIFO_PopFlags_sync <= CM_FIFO_PopFlags_sync;
+	end
+
+
+	//Registers for controlling the FFE and memories
+	always @(posedge SPI_SCLK or posedge ResetIn) begin
+		if (ResetIn) begin
+			RegDataOut				<= 0;
+			MemoryReadEnableOut		<= 0;
+			MemoryWriteEnableOut	<= 0;
+			WaitForMemRead			<= 0;
+			WaitForMemWrite			<= 0;
+			IncrementMemAddr		<= 0;
+			CommandReg				<= 0;
+			msecs_per_sample_reg	<= 1;		// default value is 1 (sample period = 0 should be invalid)
+			InterruptCtrl_reg		<= 0;
+            MemSelect_reg			<= 0;
+			MemAddrLow				<= 0;
+			MemAddrHigh				<= 0;
+			MemDataByte0			<= 0;
+			MemDataByte1			<= 0;
+			MemDataByte2			<= 0;
+			MemDataByte3			<= 0;
+			MemDataByte4			<= 0;
+			StartFFE_Clkin			<= 0;
+//			InitSM_Clkin			<= 0;       // Removed for Rel 0 on 6/18
+			StartSM_Clkin			<= 0;
+			CM_FIFO_ReadEnable		<= 0;
+			CM_Control_reg			<= 0;
+			FFE_Mailbox_reg			<= 0;
+	        CtrlRunTimeAddressOut   <= 0;
+			CtrlRunTimeAddressSM 	<= 0;
+			leds_off_o				<= 3'b111;
+			ClkSourceSelect_o		<= 1'b0;
+			clock_32KHz_Enable_o	<= 1'b1;
+			FFE_Clock_Control_o		<= FFE_SET;
+			SM_Clock_Control_o		<= SM_SET;
+			RingOsc_cal_en			<= 0;
+			RingOsc_select			<= 3'h7;
+		end else begin
+			if (MemoryWriteEnableOut) begin
+				if(WaitForMemWrite == 0) begin
+					WaitForMemWrite <= 1;
+				end else begin
+					MemoryWriteEnableOut <= 0;
+					WaitForMemWrite <= 0;
+					IncrementMemAddr <= 1;
+				end
+			end // if (MemoryWriteEnableOut)
+
+			if (IncrementMemAddr) begin
+				IncrementMemAddr <= 0;
+				{MemAddrHigh[3:0],MemAddrLow} <= {MemAddrHigh[3:0],MemAddrLow} + 1;
+			end
+
+			if (MemoryReadEnableOut) begin
+				if (WaitForMemRead == 0) begin
+					WaitForMemRead <= 1;
+				end else begin
+					MemoryReadEnableOut <= 0;
+					WaitForMemRead <= 0;
+					MemDataByte4 <= MemoryDataIn[35:32];
+					MemDataByte3 <= MemoryDataIn[31:24];
+					MemDataByte2 <= MemoryDataIn[23:16];
+					MemDataByte1 <= MemoryDataIn[15:8];
+					MemDataByte0 <= MemoryDataIn[7:0];
+				end
+			end
+
+			// CM FIFO read control
+			///// Old Code
+			/*
+			if (CM_FIFO_ReadEnable)
+				CM_FIFO_ReadEnable <= 0;
+			else
+				if (RegAddrIn == `CM_FIFO_Data && RegReadDataAckIn)
+					CM_FIFO_ReadEnable <= 1;
+				else
+					CM_FIFO_ReadEnable <= 0;
+			*/
+			//// New Code
+			if (RegAddrIn == `CM_FIFO_Data && RegReadDataAckIn)
+				CM_FIFO_ReadEnable <= !CM_FIFO_ReadEnable;
+			else
+				CM_FIFO_ReadEnable <= CM_FIFO_ReadEnable;
+
+			if (RegWriteEnableIn) begin
+				case (RegAddrIn)
+					`CommandReg:			begin
+												CommandReg 				<= RegDataIn;
+												//FFE_Holdoff					<= 1;
+											end
+					`milSecSample:			msecs_per_sample_reg		<= RegDataIn;
+					`InterruptCtrl:			InterruptCtrl_reg			<= RegDataIn;
+					//`InterruptStat:														// currently writes to this register does nothing, adding more interrupts may change this.
+					`MemSelect:				MemSelect_reg				<= RegDataIn;
+					`MemAddrLow:			MemAddrLow					<= RegDataIn;
+					`MemAddrHigh:			begin
+												MemAddrHigh				<= RegDataIn;
+												WaitForMemRead			<= 0;				// this is assigned in separate 'if' statements, the logic should be combined into 1.
+												MemoryReadEnableOut		<= 1;
+											end
+					`MemDataByte0:			MemDataByte0				<= RegDataIn;
+					`MemDataByte1:			MemDataByte1				<= RegDataIn;
+					`MemDataByte2:			MemDataByte2				<= RegDataIn;
+					`MemDataByte3:			MemDataByte3				<= RegDataIn;
+					`MemDataByte4:			begin
+												MemDataByte4			<= RegDataIn[3:0];
+												MemoryWriteEnableOut	<= 1;
+												WaitForMemWrite			<= 0;				// this is assigned in separate 'if' statements, the logic should be combined into 1.
+											end
+					`CM_Control:			CM_Control_reg				<= RegDataIn;
+					`MailboxToFFE_0:		FFE_Mailbox_reg[7:0]		<= RegDataIn;
+					`MailboxToFFE_1:		FFE_Mailbox_reg[15:8]		<= RegDataIn;
+					`MailboxToFFE_2:		FFE_Mailbox_reg[23:16]		<= RegDataIn;
+					`MailboxToFFE_3:		FFE_Mailbox_reg[31:24]		<= RegDataIn;
+					`RunTimeAdrReg: 		begin
+	                                            CtrlRunTimeAddressOut[7:0]   <= RegDataIn;      // Expanded for Rel 0 on 6/18
+	                                            CtrlRunTimeAddressSM    <= ~CtrlRunTimeAddressSM;
+	                                        end
+					`DemoLedCtrlReg: 		begin
+	                                            leds_off_o				<= RegDataIn[2:0];
+	                                        end
+					`ClocksControl: 		begin
+	                                            FFE_Clock_Control_o		<= RegDataIn[2:0];
+												SM_Clock_Control_o		<= RegDataIn[5:3];
+												ClkSourceSelect_o		<= RegDataIn[6];
+												clock_32KHz_Enable_o	<= RegDataIn[7];
+	                                        end
+					`RunTimeAdrReg_Upr: 	begin
+	                                            CtrlRunTimeAddressOut[9:8]   <= RegDataIn[1:0]; // New for Rel 0 on 6/18
+	                                        end
+					`SleepControl:			begin
+												RingOsc_cal_en			<= RegDataIn[7];
+												RingOsc_select			<= RegDataIn[6:4];
+											end
+				endcase
+
+				if ((RegAddrIn == `CommandReg) && RegDataIn[1])		// run FFE once
+					StartFFE_Clkin <= ~StartFFE_Clkin;
+
+				//the SM control signals come as a pair because only one should be toggled at a time if both bits are written to in CommandReg
+				//Initialization takes precedense over Start
+//				if ((RegAddrIn == `CommandReg) && RegDataIn[3])       // Removed for Rel 0 on 6/18
+//					InitSM_Clkin <= ~InitSM_Clkin;                    // Removed for Rel 0 on 6/18
+//				else if ((RegAddrIn == `CommandReg) && RegDataIn[2])  // Updated for Rel 0 on 6/18
+				if ((RegAddrIn == `CommandReg) && RegDataIn[2])
+					StartSM_Clkin <= ~StartSM_Clkin;
+
+			end else begin
+				case (RegAddrIn)
+
+					`CommandReg:			RegDataOut <=	{	CommandReg[7],		// UseFastClk
+																1'b0,				// SW_Reset, self-clearing
+																1'b0,				// reserved
+																1'b0,				// reserved
+																1'b0,				// RunSensorInit, self-clearing
+																1'b0,				// RunSMOnce, self-clearing
+																1'b0,				// RunFFEOnce, self-clearing
+																CommandReg[0]		// RunFFEContinuously
+															};
+
+					`StatusReg:				RegDataOut <=	{	3'b0,
+																I2C_Master_Error_reg,
+																SMOverrunIn,
+																FFEOverrun,
+																SMBusyIn,
+																FFEBusyIn
+															};	// Status Reg
+
+					`milSecSample:			RegDataOut <= msecs_per_sample_reg;
+					`InterruptCtrl:			RegDataOut <= {6'b0, Interrupt_En_1, Interrupt_En_0};
+					`InterruptStat:			RegDataOut <= {7'b0, InterruptFFEMsg_ORed};
+					`MemSelect:				RegDataOut <= {MemSelect_reg[7], 4'b0, MemSelect_reg[2:0]};
+					`MemAddrLow:			RegDataOut <= MemAddrLow;
+					`MemAddrHigh:			RegDataOut <= MemAddrHigh;
+					`MemDataByte0:			RegDataOut <= MemoryDataIn[7:0];	// MemDataByte0;
+					`MemDataByte1:			RegDataOut <= MemoryDataIn[15:8];	// MemDataByte1;
+					`MemDataByte2:			RegDataOut <= MemoryDataIn[23:16];	// MemDataByte2;
+					`MemDataByte3:			RegDataOut <= MemoryDataIn[31:24];	// MemDataByte3;
+					`MemDataByte4:			RegDataOut <= MemoryDataIn[35:32];	// MemDataByte4;
+					`CM_FIFO_Data:			RegDataOut <= CM_FIFO_ReadData[7:0];
+					`CM_Control:			RegDataOut <= {7'b0, CM_RingBufferMode};
+					`CM_Status:				RegDataOut <= {6'b0, CM_FIFO_Overflow_reg, CM_AutoDrain_Busy};
+					`CM_FIFO_Flags_0:		RegDataOut <= {4'b0, CM_FIFO_PopFlags_sync};
+					`MailboxToFFE_0:		RegDataOut <= FFE_Mailbox_reg[7:0];
+					`MailboxToFFE_1:		RegDataOut <= FFE_Mailbox_reg[15:8];
+					`MailboxToFFE_2:		RegDataOut <= FFE_Mailbox_reg[23:16];
+					`MailboxToFFE_3:		RegDataOut <= FFE_Mailbox_reg[31:24];
+					`InterruptFFEMsg:		RegDataOut <= InterruptFFEMsg_latched;
+					`RunTimeAdrReg: 		RegDataOut <= CtrlRunTimeAddressReg[7:0];         // Expanded for Rel 0 on 6/18
+					`DemoLedCtrlReg: 		RegDataOut <= {5'b0, leds_off_o};
+					`ClocksControl: 		RegDataOut <= {clock_32KHz_Enable_o, ClkSourceSelect_o, SM_Clock_Control_o[2:0], FFE_Clock_Control_o[2:0]};
+					`SleepControl:			RegDataOut <= {RingOsc_cal_en, RingOsc_select[2:0], 1'b0, sleepModeSet, IntInputLevel, SleepMode};
+					`RunTimeAdrReg_Upr:		RegDataOut <= {6'h0, CtrlRunTimeAddressReg[9:8]}; // New for Rel 0 on 6/18
+					`CalValueLow:			RegDataOut <= RingOsc_cal_value[7:0];
+					`CalValueHi:			RegDataOut <= RingOsc_cal_value[15:8];
+					default: 				RegDataOut <= 8'h21;
+				endcase
+			end
+		end // if (ResetIn)
+	end // Always
+
+
+assign i_StartFFEOut	= StartFFE_32K ^ StartFFE_Clkin;
+//assign InitSMOut	= s6_InitSM_Clkin;  // Removed for Rel 0 on 6/18
+assign StartSMOut	= s6_StartSM_Clkin;
+
+// test points
+assign TP1 = FFE_Mailbox_reg[0];
+assign TP2 = RegWriteEnableIn;
+
+// Logic to drive RIng Osc Clock Enable / Disable
+
+//assign smInit_enable = (s2_InitSM_Clkin ^ s3_InitSM_Clkin) || (s2_StartSM_Clkin ^ s3_StartSM_Clkin);  // Removed for Rel 0 on 6/18
+assign smInit_enable = (s2_StartSM_Clkin ^ s3_StartSM_Clkin);                                           // Updated for Rel 0 on 6/18
+
+assign d_ClockEnable = ClockEnable_o ? ((!s2_SMBusyIn && s3_SMBusyIn) ? 1'b0 : 1'b1) : (( d_FFE_CLK_Enable || smInit_enable ) ? 1'b1 : 1'b0);
+always @(posedge Clock32KIn or posedge ResetIn) 
+	begin
+		if (ResetIn) 
+		begin
+			s1_SMBusyIn <= 0;
+			s2_SMBusyIn <= 0;
+			s3_SMBusyIn <= 0;
+			ClockEnable_o <= 0;
+//			s1_InitSM_Clkin <= 0;
+//			s2_InitSM_Clkin <= 0;
+//			s3_InitSM_Clkin <= 0;
+//			s4_InitSM_Clkin <= 0;
+//			s5_InitSM_Clkin <= 0;
+//			s6_InitSM_Clkin <= 0;
+			s1_StartSM_Clkin <= 0;
+			s2_StartSM_Clkin <= 0;
+			s3_StartSM_Clkin <= 0;
+			s4_StartSM_Clkin <= 0;
+			s5_StartSM_Clkin <= 0;
+			s6_StartSM_Clkin <= 0;
+		end
+		else 
+		begin
+			s1_SMBusyIn <= (SMBusyIn || FFEBusyIn);
+			s2_SMBusyIn <= s1_SMBusyIn;
+			s3_SMBusyIn <= s2_SMBusyIn;
+			ClockEnable_o <= d_ClockEnable;
+//			s1_InitSM_Clkin <= InitSM_Clkin;
+//			s2_InitSM_Clkin <= s1_InitSM_Clkin;
+//			s3_InitSM_Clkin <= s2_InitSM_Clkin;
+//			s4_InitSM_Clkin <= s3_InitSM_Clkin;
+//			s5_InitSM_Clkin <= s4_InitSM_Clkin;
+//			s6_InitSM_Clkin <= s5_InitSM_Clkin;
+			s1_StartSM_Clkin <= StartSM_Clkin;
+			s2_StartSM_Clkin <= s1_StartSM_Clkin;
+			s3_StartSM_Clkin <= s2_StartSM_Clkin;
+			s4_StartSM_Clkin <= s3_StartSM_Clkin;
+			s5_StartSM_Clkin <= s4_StartSM_Clkin;
+			s6_StartSM_Clkin <= s5_StartSM_Clkin;
+		end
+	end	
+	
+// Logic to select default reset values for the SM and FFE CLK selection
+assign	FFE_SET[0] = (`FFE1CLK_FREQ_SLT == 8'b00000001) || (`FFE1CLK_FREQ_SLT == 8'b00000010) || (`FFE1CLK_FREQ_SLT == 8'b00000100) || (`FFE1CLK_FREQ_SLT == 8'b00001000) ||
+                     (`FFE1CLK_FREQ_SLT == 8'b00010000) || (`FFE1CLK_FREQ_SLT == 8'b01000000);
+assign	FFE_SET[1] = (`FFE1CLK_FREQ_SLT == 8'b00000001) || (`FFE1CLK_FREQ_SLT == 8'b00000010) || (`FFE1CLK_FREQ_SLT == 8'b00000100) || (`FFE1CLK_FREQ_SLT == 8'b00001000) ||
+					 (`FFE1CLK_FREQ_SLT == 8'b00100000) || (`FFE1CLK_FREQ_SLT == 8'b01000000);
+assign	FFE_SET[2] = (`FFE1CLK_FREQ_SLT == 8'b10000000);
+
+assign	SM_SET[0] = (`SM1CLK_FREQ_SLT == 8'b00000010) || (`SM1CLK_FREQ_SLT == 8'b00001000) || (`SM1CLK_FREQ_SLT == 8'b00100000) || (`SM1CLK_FREQ_SLT == 8'b10000000);
+assign	SM_SET[1] = (`SM1CLK_FREQ_SLT == 8'b00000100) || (`SM1CLK_FREQ_SLT == 8'b00001000) || (`SM1CLK_FREQ_SLT == 8'b01000000) || (`SM1CLK_FREQ_SLT == 8'b10000000);
+assign	SM_SET[2] = (`SM1CLK_FREQ_SLT == 8'b00010000) || (`SM1CLK_FREQ_SLT == 8'b00100000) || (`SM1CLK_FREQ_SLT == 8'b01000000) || (`SM1CLK_FREQ_SLT == 8'b10000000);
+
+// Logic for Sleep Mode
+// Sensor interrupt input is double ring to check for transtion from low to high
+// Once detected, the design will enable the sampling period
+assign	sleepModeSet = sensorInterrupt_s2 && !sensorInterrupt_s3;
+always @(posedge Clock32KIn or posedge ResetIn) 
+	begin
+		if (ResetIn) 
+		begin
+			sensorInterrupt_s1 <= 0;
+			sensorInterrupt_s2 <= 0;
+			sensorInterrupt_s3 <= 0;
+		end
+		else
+		begin
+			sensorInterrupt_s1 <= (SensorInterruptIn ~^ IntInputLevel) && SleepMode;
+			sensorInterrupt_s2 <= sensorInterrupt_s1;
+			sensorInterrupt_s3 <= sensorInterrupt_s2;
+		end
+	end
+
+assign sleepReset = ResetIn || sleepModeSet;
+always @(posedge SPI_SCLK or posedge sleepReset) begin
+	if (sleepReset) 
+	begin
+		SleepMode <= 1'b0;
+	end
+	else if ((RegAddrIn == `SleepControl) && RegWriteEnableIn)
+	begin
+	    SleepMode <= RegDataIn[0];
+	end
+end
+	
+
+always @(posedge SPI_SCLK or posedge ResetIn) begin
+	if (ResetIn) 
+	begin
+		IntInputLevel <= 1'b1;
+	end
+	else if ((RegAddrIn == `SleepControl) && RegWriteEnableIn)
+	begin
+		IntInputLevel <= RegDataIn[1];
+	end
+end
+
+endmodule 
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/ULPSH_fabric.v b/BENCHMARK/ULPSH_fabric/rtl/src/ULPSH_fabric.v
new file mode 100644
index 0000000..686e3e5
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/ULPSH_fabric.v
@@ -0,0 +1,1089 @@
+
+`timescale 1ns / 10ps
+
+`include "ulpsh_rtl_defines.v"
+
+
+module ULPSH_fabric (
+	input			OperatingClockRef,
+	input			Clock32KIn,
+	input			ResetInN,
+	
+	input			SPI_SCLK,
+	input			SPI_SS,
+	input			SPI_MOSI,
+	output			SPI_MISO,
+	
+	output			Interrupt,
+	input	[4:0] 	SensorInterrupt,
+
+	// ASSP ring oscillator interface
+	output			ASSP_ringosc_en_o,
+	output	[2:0]	ASSP_ringosc_sel_o,
+	input			ASSP_ringosc_sysclk_i,			// divided ring osc clock (use this for system clock)
+	input			ASSP_ringosc_sysclk_x2_i,		// divided ring osc clock times 2
+	input			ASSP_ringosc_clk_i,				// raw ring osc clock div 2
+
+	// FFE Ctrl Mem, RAM0 --> ASSP RAM interface - left bank
+	output			FCM0_CLK_o,
+	output	[8:0]	FCM0_ADDR_o,
+	output	[35:0]	FCM0_WR_DATA_o,
+	input	[35:0]	FCM0_RD_DATA_i,
+	output			FCM0_WR_EN_o,
+	output			FCM0_RD_EN_o,
+	output	[3:0]	FCM0_WR_BE_o,
+
+	// FFE Ctrl Mem, RAM1 --> ASSP RAM interface - right bank
+	output			FCM1_CLK_o,
+	output	[8:0]	FCM1_ADDR_o,
+	output	[35:0]	FCM1_WR_DATA_o,
+	input	[35:0]	FCM1_RD_DATA_i,
+	output			FCM1_WR_EN_o,
+	output			FCM1_RD_EN_o,
+	output	[3:0]	FCM1_WR_BE_o,
+
+`ifdef ENABLE_FFE_F0_CM_SIZE_4K
+	// ASSP RAM interface - 8k - left bank
+	output			FCM8K_CLK_o,
+    output	[11:0]	FCM8K_ADDR_o,
+    output	[16:0]	FCM8K_WR_DATA_o,
+    input	[16:0]	FCM8K_RD_DATA_i,
+    output			FCM8K_WR_EN_o,
+    output			FCM8K_RD_EN_o,
+    output	[1:0]	FCM8K_WR_BE_o,
+`endif
+
+	// FFE Data Mem1 --> ASSP RAM interface - right bank
+	output			DMM1_WR_CLK_o,
+	output	[9:0]	DMM1_WR_ADDR_o,
+	output	[31:0]	DMM1_WR_DATA_o,
+	output			DMM1_WR_EN_o,
+	output	[3:0]	DMM1_WR_BE_o,
+	output			DMM1_RD_CLK_o,
+	output	[9:0]	DMM1_RD_ADDR_o,
+	input	[31:0]	DMM1_RD_DATA_i,
+	output			DMM1_RD_EN_o,
+
+	// FFE Data Mem2 --> ASSP RAM interface - right bank
+	output			DMM2_WR_CLK_o,
+	output	[9:0]	DMM2_WR_ADDR_o,
+	output	[31:0]	DMM2_WR_DATA_o,
+	output			DMM2_WR_EN_o,
+	output	[3:0]	DMM2_WR_BE_o,
+	output			DMM2_RD_CLK_o,
+	output	[9:0]	DMM2_RD_ADDR_o,
+	input	[31:0]	DMM2_RD_DATA_i,
+	output			DMM2_RD_EN_o,
+
+	// ASSP multiplier interface
+	output	[31:0]	Amult_o,
+	output	[31:0]	Bmult_o,
+	output			Valid_mult_o,
+	input	[63:0]	Cmult_i,
+	// ASSP RIGHT BANK: I2C Wishbone interface
+	output          I2C_wb_clk_o,
+	output          I2C_arst_o,
+	output  [2:0]   I2C_wb_adr_o,
+	output  [7:0]   I2C_wb_dat_o,
+	input   [7:0]   I2C_wb_dat_i,
+	output          I2C_wb_we_o,
+	output          I2C_wb_stb_o,
+	output          I2C_wb_cyc_o,
+	input           I2C_wb_ack_i,
+	input           I2C_tip_i,
+	input           I2C_Master_Error_i,
+
+    //inout           SensorScl_io,
+    output          SensorScl_io,
+    input           SensorScl_oen_i,
+	input           SensorScl_i,
+
+    //inout           SensorSda_io,
+    output          SensorSda_io,
+    input           SensorSda_oen_i,
+	input           SensorSda_i,
+
+
+	output	LED1,
+
+	output	TP1,
+	output	TP2,
+	output	TP3,
+	
+	//AP2
+	output 	[17:0]	CM_FIFO_1x_din_o			,
+	output 			CM_FIFO_1x_push_int_o		,
+	output 			CM_FIFO_1x_pop_int_o		,
+	output 			CM_FIFO_1x_push_clk_o		,
+	output 			CM_FIFO_1x_pop_clk_o		,
+	output 			CM_FIFO_1x_rst_o			,
+	                                            
+	input 			CM_FIFO_1x_almost_full_i	,
+	input 			CM_FIFO_1x_almost_empty_i	,
+	input 	[3:0]	CM_FIFO_1x_push_flag_i		,
+	input 	[3:0]	CM_FIFO_1x_pop_flag_i		,
+	input 	[8:0]	CM_FIFO_1x_dout_i			,
+	
+    output 	[9:0]	SMMemory_WriteAddressIn_TLC_o,
+	output 	[8:0]	SMMemory_ReadAddressIn_o,
+	output 			SMMemory_WriteSelectIn_TLC_o,
+	output 			SMMemory_ReadSelect_RAM0_o,
+	output 			SMMemory_WriteClockIn_o,
+	output 			SMMemory_ReadClockIn_o,
+	output  [8:0]	SMMemory_WriteDataIn_TLC_o,
+	input  	[17:0]	SMMemory_ReadDataOut_SRAM_i,
+	output 	[9:0]	SMMemory_WriteAddressIn_o,
+	output 		    SMMemory_WriteSelectIn_o,
+	output 			SMMemory_ReadSelect_RAM1_o,
+	output 			SMMemory_WriteDataIn_o,
+	input  	[17:0]	SMMemory_ReadDataOut_SRAM1_i,
+
+	
+	output  [8:0]   FFEControlMemory_4k_Address_TLC_o      ,		
+	output  [8:0]  	FFEControlMemory_4k_ReadAddress_muxed_o ,
+	output    		FFEControlMemory_4k_ram5_wr_en_o,  			
+	output    		FFEControlMemory_4k_ram5_rd_en_o,			
+	output    		FFEControlMemory_4k_SPI_clk_o, 				
+	output    		FFEControlMemory_4k_TLC_FFE_clk2x_muxed_o, 	
+	output  [35:0]  FFEControlMemory_4k_WriteData_TLC_o ,
+	input   [35:0]  FFEControlMemory_4k_ram5_rd_data_i	,
+	output    		FFEControlMemory_4k_ram4_wr_en_o	,	
+	output    		FFEControlMemory_4k_ram4_rd_en_o,
+	input  [35:0]  FFEControlMemory_4k_ram4_rd_data_i,
+	output [9:0]    FFEControlMemory_4k_fabric_ram1Kx9_addr_o,
+	output 			FFEControlMemory_4k_ram1_wr_en_o  ,		
+	output 			FFEControlMemory_4k_ram1_rd_en_o ,		
+	input  [8:0]    FFEControlMemory_4k_ram1_rd_data_i
+	
+
+);
+
+wire			SPI_SCLK_gclk;
+
+wire	[6:0]	RegAddr;
+wire	[7:0]	RegDataToTLC;
+wire	[7:0]	RegDataFromTLC;
+wire			RegWriteEnableToTLC;
+wire			RegReadDataAck;
+
+wire			TlcFfeCMMuxSelect;
+wire			TlcFfeDM1MuxSelect;
+wire			TlcFfeDM2MuxSelect;
+wire			TLC_SMMuxSelect;
+wire			TLC_CMMuxSelect;
+wire			TLC_MemorySelect_en;
+wire	[2:0]	TLC_MemorySelect;
+wire	[11:0]	TLC_MemoryAddress;
+wire	[35:0]	TLC_MemoryDataToMemory;
+wire	[35:0]	TlcMemoryDataFromMemory;
+wire			TLC_WriteEnable;
+wire			TLC_ReadEnable;
+wire			TLC_MemoryClock;
+
+wire			StartFFE;
+wire	[15:0]	TimeStamp;
+wire			UseFastClock;
+wire	[31:0]	MailboxToFFE;
+
+// Signals associated with Communication Manager function of TLC
+wire			CM_ReadEnableFromTLC;
+wire	[9:0]	CM_ReadAddressFromTLC;
+wire			CM_ReadClockFromTLC;
+wire	[3:0]	CMBufferBeingWritten;
+
+// Signals associated with FFE Control Memory
+wire	[11:0]	FFECM_WriteAddress;
+wire	[11:0]	FFECM_ReadAddress;
+wire			FFECM_WriteSelect;
+wire			FFECM_ReadSelect;
+wire	[35:0]	FFECM_WriteData;
+wire	[35:0]	FFECM_ReadData;
+wire	[35:0]	MemoryDataFromDM1Mux;
+
+// Signals associated with FFE Data Memory 1
+wire	[9:0]	FFEDM1_WriteAddress;
+wire	[9:0]	FFEDM1_ReadAddress;
+wire			FFEDM1_WriteSelect;
+wire			FFEDM1_ReadSelect;
+wire	[35:0]	FFEDM1_WriteData;
+wire	[35:0]	FFEDM1_ReadData;
+wire	[35:0]	MemoryDataFromDM2Mux;
+
+// Signals associated with FFE Data Memory 2
+wire	[9:0]	FFEDM2_WriteAddress;
+wire	[9:0]	FFEDM2_ReadAddress;
+wire			FFEDM2_WriteSelect;
+wire			FFEDM2_ReadSelect;
+wire	[35:0]	FFEDM2_WriteData;
+wire	[35:0]	FFEDM2_ReadData;
+wire	[17:0]	MemoryDataFromSMMux;
+
+// Signals associated with Sensor Manager Memory
+wire	[9:0]	SM_WriteAddress;
+wire	[9:0]	SM_ReadAddress;                        // Expanded for Rel 0 on 6/18
+wire			SM_WriteSelect;
+wire			SM_ReadSelect;
+wire	[8:0]	SM_WriteData;
+wire	[17:0]	SM_ReadData;
+wire	[8:0]	MemoryDataFromCMMux;
+
+// Signals associated with Communication Manager Memory
+wire			ASSP_CMFIFO_wr_clk;
+wire	[16:0]	ASSP_CMFIFO_wr_data;
+wire			ASSP_CMFIFO_wr_en;
+wire			ASSP_CMFIFO_rd_clk;
+wire	[16:0]	ASSP_CMFIFO_rd_data;
+wire			ASSP_CMFIFO_rd_en;
+wire			ASSP_CMFIFO_empty;
+wire			ASSP_CMFIFO_full;
+wire	[3:0]	ASSP_CMFIFO_rd_flags;
+wire	[3:0]	ASSP_CMFIFO_wr_flags;
+wire	[8:0]	CM_WriteAddress;
+wire	[9:0]	CM_ReadAddress;
+wire			CM_WriteSelect;
+wire			CM_ReadSelect;
+wire	[17:0]	CM_WriteData;
+wire	[8:0]	CM_ReadData;
+
+// Signals associated with FFE
+wire	[11:0]	FFECM_ReadAddressFromFFE;
+wire			FFECM_ReadEnableFromFFE;
+wire	[9:0]	FFEDM1_ReadAddressFromFFE;
+wire	[9:0]	FFEDM1_WriteAddressFromFFE;
+wire	[35:0]	FFEDM1_WriteDataFromFFE;
+wire	[9:0]	FFEDM2_ReadAddressFromFFE;
+wire	[9:0]	FFEDM2_WriteAddressFromFFE;
+wire	[35:0]	FFEDM2_WriteDataFromFFE;
+wire	[9:0]	SMSM_ReadAddressFromFFE;                // Expanded for Rel 0 on 6/18
+wire			SMSM_ReadEnableFromFFE;
+wire	[17:0]	CM_WriteDataFromFFE;
+wire			CM_WriteEnableFromFFE;
+wire			SMOverrun;								// Error bit when SM still running and FFE trying to start
+
+wire    [9:0]   SMSM_WriteAddressFromFFE;               // New      for Rel 0 on 6/18
+wire            SMSM_WriteEnableFromFFE;                // New      for Rel 0 on 6/18
+wire	[8:0]	SMSM_WriteDataFromFFE;                  // New      for Rel 0 on 6/18
+
+// Signals associated with Sensor Manager
+wire	[9:0]	SMSM_WriteAddressFromSensorManager; 
+wire			SMSM_WriteEnableFromSensorManager;
+wire	[8:0]	SMSM_WriteDataFromSensorManager;
+wire	[9:0]	SMSM_ReadAddressFromSensorManager;      // Expanded for Rel 0 on 6/18
+wire			SMSM_ReadEnableFromSensorManager;
+wire			SMSM_ReadClockFromSensorManager;
+//	wire			InitSMFromTLC;                          // Removed  for Rel 0 on 6/18
+wire			StartSMFromTLC;
+wire			StartSMFromFFE;
+
+wire			CM_FIFO_ReadEnable;
+wire	[8:0]	CM_FIFO_ReadData;
+wire	[3:0]	CM_FIFO_Pop_Flags;
+wire	[3:0]	CM_FIFO_Push_Flags;
+
+//wire			CM_FIFO_WriteEnable;
+//wire	[17:0]	CM_FIFO_WriteData;
+wire			CM_FIFO_full;
+wire			CM_FIFO_empty;
+wire			CM_FIFO_Overflow;
+wire			CM_RingBufferMode;
+wire			CM_AutoDrain_Busy;
+wire			CM_FIFO_ReadClk;
+wire			CM_FIFO_PopFromTLC;
+
+wire			FFE_Control_Clock_gclk;
+wire			FFE_Control_Clock_x2_gclk;
+wire			OperatingClock;
+
+wire			ResetIn;
+wire			SW_Reset;
+
+// FFE&SM Clock
+wire			FFE_Control_Clock;
+wire			FFE_Control_Clock_x2;
+wire			FFEandSM_Clock;
+wire			FFEBusy;
+wire			SMBusy;
+
+wire			FFEandSM_Clock_p;
+wire	[9:0]	ReadAddressFromSMorFFE;                  // Expanded for Rel 0 on 6/18
+wire			ReadEnableFromSMorFFE;
+	
+wire    [9:0]   WriteAddressFromSMorFFE;                 // New      for Rel 0 on 6/18
+wire            WriteEnableFromSMorFFE;                  // New      for Rel 0 on 6/18
+wire	[8:0]	WriteDataFromSMorFFE;                    // New      for Rel 0 on 6/18
+
+wire			FFE_Control_TP_1;
+wire			FFE_Control_TP_2;
+wire			FFE_Control_TP_3;
+
+wire			SM_ReadClock;
+wire			SM_ReadClock_gclk;
+
+wire			TP_SM_1, TP_SM_2, TP_SM_3;
+wire			TP_TLC_1, TP_TLC_2;
+
+wire	[7:0]	InterruptMsgFromFFE;
+
+wire			FFE_clock_halfperiod;
+
+reg		[11:0]	TLC_pop_cnt;
+reg				TLC_pop_stretched;
+
+wire			SM_Clock;
+wire			SM_Clock_gclk;
+
+wire 	[9:0]	CtrlRunTimeAddressReg;                   // Expanded for Rel 0 on 6/18
+wire 	[9:0]	CtrlRunTimeAddressOut;                   // Expanded for Rel 0 on 6/18
+wire 			CtrlRunTimeAddressSM;
+
+// Sensor On/OFF Control
+wire	[2:0]	LEDS_CTRL;
+
+wire			ring_osc_clk;
+wire			FFE_CLK_ENABLE;
+wire			SmClockSelect;
+wire			Main_Clock_Enable;
+wire			clock_32KHz_Enable;
+wire			Clock_32KHz;
+wire			external_Clock;
+wire	[2:0]	ffe_clock_select, sm_clock_select;
+reg				smClock;
+wire			clk_source_select;
+wire			OperatingClockRef_buff;
+wire 	[3:0] 	ClockGen_State;
+
+wire 	        TimeStamp_Tog;
+wire 	        SensorInterrupt_0_FFE;
+wire 	        SensorInterrupt_1_FFE;
+wire 	        SensorInterrupt_2_FFE;
+wire 	        SensorInterrupt_3_FFE;
+wire	[3:0]	SMInterruptToFFE;
+
+wire			assp_lb_ram0_clk;
+wire	[8:0]	assp_lb_ram0_addr;
+wire	[35:0]	assp_lb_ram0_wr_data;
+wire	[35:0]	assp_lb_ram0_rd_data;
+wire			assp_lb_ram0_wr_en;
+wire			assp_lb_ram0_rd_en;
+wire	[3:0]	assp_lb_ram0_wr_be;
+
+wire			assp_rb_ram1_clk;
+wire	[8:0]	assp_rb_ram1_addr;
+wire	[35:0]	assp_rb_ram1_wr_data;
+wire	[35:0]	assp_rb_ram1_rd_data;
+wire			assp_rb_ram1_wr_en;
+wire			assp_rb_ram1_rd_en;
+wire	[3:0]	assp_rb_ram1_wr_be;
+
+wire			assp_lb_ram8k_clk;
+wire	[11:0]	assp_lb_ram8k_addr;
+wire	[16:0]	assp_lb_ram8k_wr_data;
+wire	[16:0]	assp_lb_ram8k_rd_data;
+wire			assp_lb_ram8k_wr_en;
+wire			assp_lb_ram8k_rd_en;
+wire	[1:0]	assp_lb_ram8k_wr_be;
+
+wire			RingOsc_cal_en;
+wire	[2:0]	RingOsc_select;
+wire	[15:0]	clk_cal_value;
+
+wire			FFEDM1_ReadClock;
+wire			FFEDM1_WriteClock;
+wire			FFEDM2_ReadClock;
+wire			FFEDM2_WriteClock;
+
+wire			FFE_Control_Clock_dly1;
+wire			FFE_Control_Clock_dly2;
+wire			FFE_Control_Clock_dly3;
+
+
+`ifdef ENABLE_FFE_F0_EXTENDED_DM
+	wire		extended_DM1_select;
+	wire		extended_DM2_select;
+`endif
+
+
+//  Assign interrupt
+assign	SensorInterrupt_0 = SensorInterrupt[0];
+assign	SensorInterrupt_1 = SensorInterrupt[1];
+assign	SensorInterrupt_2 = SensorInterrupt[2];
+assign	SensorInterrupt_3 = SensorInterrupt[3];
+
+
+
+
+// compiler options, from rtl_defines.v
+// ENABLE_FFE_F0_EXTENDED_DM
+// ENABLE_FFE_F0_PROGRAMMABLE_SEG0_OFFSET
+// FFE_F0_SEG0_OFFSET  [value]
+// ENABLE_FFE_F0_SINGLE_DM
+
+
+
+assign ResetIn = ~ResetInN || SW_Reset;
+
+/*
+//// To be Remove
+	ring_osc_adjust ring_osc_adjust_1 (
+		.reset_i				( ResetIn					),
+		.clk_ringosc_div2_i		( ASSP_ringosc_clk_i	),
+		.clk_32khz_i			( Clock32KIn				),
+		.enable_i				( RingOsc_cal_en			),
+		.div_sel_o				( ASSP_ringosc_sel_o		)
+	);
+	assign ASSP_ringosc_en_o = 1'b1;
+*/
+
+	
+SystemClockControl clockcontrol_1	(
+	.OperatingClockRef_i		( OperatingClockRef			),
+	.Clock32KIn_i				( Clock32KIn				),
+	.SPIClock_i					( SPI_SCLK					),
+	.ResetIn_i					( ResetIn					),
+	
+	.FfeClkSelect_i				( ffe_clock_select			),
+	.SmClkSelect_i				( sm_clock_select			),
+	.SmSpeedSelect_i			( SmClockSelect				),
+	.SpiClkSelect_i				( UseFastClock				),
+	.ClkSourceSelect_i			( clk_source_select			),
+	.Clk32KhzEnable_i			( clock_32KHz_Enable		),
+	.MainClkEnable_i			( Main_Clock_Enable			),
+	.FfeClkEnable_i				( FFE_CLK_ENABLE			),
+	.CM_AutoDrain_Busy			( CM_AutoDrain_Busy			),
+	
+	.SmClock_o					( SM_Clock					),
+	.FfeClock_o					( FFE_Control_Clock			),
+	.FfeClock_x2_o				( FFE_Control_Clock_x2		),
+	.clock_32KHz_o				( Clock_32KHz				),
+	.multiplierClk_o			( OperatingClock			),
+	.ClockGen_State_o			( ClockGen_State			),
+	.CM_FIFO_ReadClk			( CM_FIFO_ReadClk			),
+	
+	.clk_ringosc_i				( ASSP_ringosc_sysclk_i		),
+	.clk_ringosc_x2_i			( ASSP_ringosc_sysclk_x2_i	),
+	.enable_i					( RingOsc_cal_en			),
+	.clk_cal_value_o			( clk_cal_value				),
+	.assp_ringosc_en_o			( ASSP_ringosc_en_o			)
+);
+
+// The Dragon SPI version requires a gclkbuff instantiation b/c the SPI CLK is on a GPIO pin
+
+GCLKBUFF clock_buffer_SPI_SCLK (.A(SPI_SCLK), .Z(SPI_SCLK_gclk));
+
+GCLKBUFF clock_buffer_OperatingClock (.A(OperatingClock), .Z(OperatingClock_gclk));
+
+// delay the 1x clock
+buff buff_ffe_control_clock1 (.A(FFE_Control_Clock), .Q(FFE_Control_Clock_dly1));
+buff buff_ffe_control_clock2 (.A(FFE_Control_Clock_dly1), .Q(FFE_Control_Clock_dly2));
+buff buff_ffe_control_clock3 (.A(FFE_Control_Clock_dly2), .Q(FFE_Control_Clock_dly3));
+//pragma attribute buff_ffe_control_clock1 dont_touch true
+//pragma attribute buff_ffe_control_clock2 dont_touch true
+//pragma attribute buff_ffe_control_clock3 dont_touch true
+
+//clock_buffer clock_buffer_FFE_Control_Clock (.A(FFE_Control_Clock), .Z(FFE_Control_Clock_gclk));
+GCLKBUFF clock_buffer_FFE_Control_Clock (.A(FFE_Control_Clock_dly3), .Z(FFE_Control_Clock_gclk));
+
+GCLKBUFF clock_buffer_FFE_Control_Clock_x2 (.A(FFE_Control_Clock_x2), .Z(FFE_Control_Clock_x2_gclk));
+
+GCLKBUFF clock_buffer_SM_Clock (.A(SM_Clock), .Z(SM_Clock_gclk));
+
+GCLKBUFF clock_buffer_CM_FIFO_ReadClk (.A(CM_FIFO_ReadClk), .Z(CM_FIFO_ReadClk_gclk));
+
+
+SPI_slave SPI_slave_1 (
+	.rst			( ResetIn				),		// system/global reset (active-high)
+
+	// SPI interface
+	.SPI_SCLK		( SPI_SCLK_gclk			),		// base value 0 (mode 0)
+	.SPI_MOSI		( SPI_MOSI				),		// master out, slave in
+	.SPI_MISO		( SPI_MISO				),		// master in, slave out
+	.SPI_SS			( SPI_SS				),		// slave select (active-low)
+
+	// internal interface
+	.addr			( RegAddr				),
+	.wr_data		( RegDataToTLC			),
+	.wr_data_valid	( RegWriteEnableToTLC	),	// active high
+	.rd_data		( RegDataFromTLC		),
+	.rd_data_ack	( RegReadDataAck		)
+);
+
+
+assign ASSP_ringosc_sel_o = RingOsc_select;
+TLC u_TLC (
+	// General interface
+	.SPI_SCLK					( SPI_SCLK_gclk				),
+	.Clock32KIn					( Clock_32KHz				),
+	.FFE_Clock					( FFE_Control_Clock_gclk	),
+	.ResetIn					( ResetIn					),
+	.SW_Reset					( SW_Reset					),
+
+	.RingOsc_cal_en				( RingOsc_cal_en			),
+	.RingOsc_select				( RingOsc_select			),
+	.RingOsc_cal_value			( clk_cal_value				),
+
+	.I2C_Master_Error			( I2C_Master_Error_i		),
+	.FFEBusyIn					( FFEBusy					),
+	.SMBusyIn					( SMBusy					),
+	.SMOverrunIn				( SMOverrun					),
+	.StartFFEOut				( StartFFE					),
+//		.InitSMOut					( InitSMFromTLC				),  // Removed  for Rel 0 on 6/18
+	.StartSMOut					( StartSMFromTLC			),
+	.TimeStampOut				( TimeStamp					),
+	.TimeStampOut_Tog			( TimeStamp_Tog				),
+	.UseFastClockOut			( UseFastClock				),
+
+	.InterruptMsgFromFFEIn		( InterruptMsgFromFFE		),
+	.InterruptPinOut			( Interrupt					),
+	.SensorInterruptIn			( SensorInterrupt[4]		),
+	
+	.FFE_Mailbox_Out			( MailboxToFFE				),
+	
+	.CtrlRunTimeAddressReg		( CtrlRunTimeAddressReg		),
+	.CtrlRunTimeAddressOut		( CtrlRunTimeAddressOut		),
+	.CtrlRunTimeAddressSM 		( CtrlRunTimeAddressSM		),
+
+
+	// Interface to SPI Slave
+	.RegAddrIn					( RegAddr					),
+	.RegDataIn					( RegDataToTLC				),
+	.RegDataOut					( RegDataFromTLC			),
+	.RegWriteEnableIn			( RegWriteEnableToTLC		),
+	.RegReadDataAckIn			( RegReadDataAck			),
+
+	// Interface to memories
+	.TLCDrivingFFEControlMem	( TlcFfeCMMuxSelect			),
+	.TLCDrivingFFEDataMem1		( TlcFfeDM1MuxSelect		),
+	.TLCDrivingFFEDataMem2		( TlcFfeDM2MuxSelect		),
+	.TLCDrivingSMMem			( TLC_SMMuxSelect			),
+	.TLCDrivingCMMem			( TLC_CMMuxSelect			),
+	.MemorySelect_en			( TLC_MemorySelect_en		),
+	.MemorySelect				( TLC_MemorySelect			),
+	.MemoryAddressOut			( TLC_MemoryAddress			),
+	.MemoryDataOut				( TLC_MemoryDataToMemory	),
+	.MemoryDataIn				( TlcMemoryDataFromMemory	),
+	.MemoryReadEnableOut		( TLC_ReadEnable			),
+	.MemoryWriteEnableOut		( TLC_WriteEnable			),
+	.MemoryClockOut				( TLC_MemoryClock			),
+	
+	// Interface to Communication Manager FIFO
+	.CM_FIFO_ReadEnable			( CM_FIFO_PopFromTLC		),
+	.CM_FIFO_ReadData			( CM_FIFO_ReadData			),
+	.CM_FIFO_PopFlags			( CM_FIFO_Pop_Flags			),
+	.CM_FIFO_PushFlags			( CM_FIFO_Push_Flags		),
+	.CM_FIFO_Overflow			( CM_FIFO_Overflow			),
+	.CM_RingBufferMode			( CM_RingBufferMode			),
+	.CM_AutoDrain_Busy			( CM_AutoDrain_Busy			),
+	.TP1						( TP_TLC_1					),
+	.TP2						( TP_TLC_2					),
+	.leds_off_o					( LEDS_CTRL					),
+	.FFE_CLK_Enable_o			( FFE_CLK_ENABLE			),
+	.ClockEnable_o				( Main_Clock_Enable			),
+	.clock_32KHz_Enable_o		( clock_32KHz_Enable		),
+	.FFE_Clock_Control_o		( ffe_clock_select			),
+	.SM_Clock_Control_o			( sm_clock_select			),
+	.ClkSourceSelect_o			( clk_source_select			)
+);
+
+
+assign SMInterruptToFFE = {SensorInterrupt_3_FFE, SensorInterrupt_2_FFE, SensorInterrupt_1_FFE, SensorInterrupt_0_FFE};
+
+FFE_Control u_FFE_Control ( // named RunFlexFusionEngine in C source
+	// General interface
+	.ClockIn					( FFE_Control_Clock_gclk		),
+	.Clock_x2In					( FFE_Control_Clock_x2_gclk		),
+	.ResetIn					( ResetIn						),
+	.MultClockIn				( OperatingClock_gclk			),
+	.MultStateIn				( ClockGen_State				),
+	.StartIn					( StartFFE						), //Start from TLC
+	.StartSMOut					( StartSMFromFFE				),
+	.BusyOut					( FFEBusy						),
+	.TimeStampIn				( TimeStamp						),
+	.MailboxIn					( MailboxToFFE					),
+	.SM_InterruptIn				( SMInterruptToFFE				),
+	.InterruptMsgOut			( InterruptMsgFromFFE			),
+
+	// FFE Memories
+	.ControlMemAddressOut		( FFECM_ReadAddressFromFFE		),
+	.ControlMemReadEnableOut	( FFECM_ReadEnableFromFFE		),
+	.SensorMemReadAddressOut	( SMSM_ReadAddressFromFFE		),
+	.SensorMemReadEnableOut		( SMSM_ReadEnableFromFFE		),
+	.SensorMemWriteAddressOut	( SMSM_WriteAddressFromFFE		), // New for Rel 0 on 6/18 **** Place holder *****
+	.SensorMemWriteEnableOut	( SMSM_WriteEnableFromFFE		), // New for Rel 0 on 6/18 **** Place holder *****
+	.ControlMemDataIn			( FFECM_ReadData				),
+	.Mem1ReadData				( FFEDM1_ReadData				),
+	.Mem2ReadData				( FFEDM2_ReadData				),
+	.SensorMemReadDataIn		( SM_ReadData					),
+	.SensorMemBusyIn			( SMBusy						),
+
+
+	.SensorMemWriteDataOut		( SMSM_WriteDataFromFFE			), // New for Rel 0 on 6/18 **** Place holder *****
+	.DataMem1ReadEnable			( FFEToDM1Mux_ReadEnable		),
+	.DataMem2ReadEnable			( FFEToDM2Mux_ReadEnable		),
+	.DataMem1WriteEnable		( FFEToDM1Mux_WriteEnable		),
+	.DataMem2WriteEnable		( FFEDM2_WriteEnable			),
+	.DataMem1ReadAddressOut		( FFEDM1_ReadAddressFromFFE		),
+	.DataMem1WriteAddressOut	( FFEDM1_WriteAddressFromFFE	),
+	.DataMem1WriteDataOut		( FFEDM1_WriteDataFromFFE		),
+	.DataMem2ReadAddressOut		( FFEDM2_ReadAddressFromFFE		),
+	.DataMem2WriteAddressOut	( FFEDM2_WriteAddressFromFFE	),
+	.DataMem2WriteDataOut		( FFEDM2_WriteDataFromFFE		),
+
+	.FFE_clock_halfperiod		( FFE_clock_halfperiod			),
+
+	.SMBusyIn					( SMBusy						),
+	.SMOverrunOut				( SMOverrun						),
+	
+	.CMWriteDataOut				( CM_WriteDataFromFFE			),
+	.CMWriteEnableOut			( CM_WriteEnableFromFFE			),
+
+	.mult_in1					( Amult_o						),
+	.mult_in2					( Bmult_o						),
+	.mult_enable				( Valid_mult_o					),
+	.mult_out					( Cmult_i						),
+	
+	.TP1						( FFE_Control_TP_1				),
+	.TP2						( FFE_Control_TP_2				),
+	.TP3						( FFE_Control_TP_3				)
+);
+
+
+assign I2C_wb_clk_o = SM_Clock_gclk;
+assign I2C_arst_o   = ResetIn;
+
+// Define the I2C bus control signals
+//
+/* assign SensorScl_io       = SensorScl_oen_i ? 1'bz : SensorScl_i;
+assign SensorSclPUOut     = SensorScl_oen_i ? 1 : 1'bz;
+
+assign SensorSda_io       = SensorSda_oen_i ? 1'bz : SensorSda_i;
+assign SensorSdaPUOut     = SensorSda_oen_i ? 1 : 1'bz; */
+
+
+assign SensorScl_io       = SensorScl_i;
+assign SensorSclPUOut     = 1 ;
+
+assign SensorSda_io       = SensorSda_i;
+assign SensorSdaPUOut     = 1;
+	
+
+SensorManager u_SensorManager (
+	.ClockIn			( SM_Clock_gclk							),
+	.ResetIn			( ResetIn								),
+//		.InitIn				( InitSMFromTLC							), // Removed  for Rel 0 on 6/18
+	.StartFromFFE		( StartSMFromFFE						),
+	.StartFromTLC		( StartSMFromTLC						),
+	.BusyOut			( SMBusy								),
+	.TimeStamp_Delta_i      ( TimeStamp[15:0]                   ), // Added    for Rel 0 on 6/18
+	.TimeStamp_Delta_Tog_i  ( TimeStamp_Tog                     ), // Added    for Rel 0 on 6/18
+	.SensorInterrupt_0_i    ( SensorInterrupt_0                 ), // Added    for Rel 0 on 6/18
+	.SensorInterrupt_1_i    ( SensorInterrupt_1                 ), // Added    for Rel 0 on 6/18
+	.SensorInterrupt_2_i    ( SensorInterrupt_2                 ), // Added    for Rel 0 on 6/18
+	.SensorInterrupt_3_i    ( SensorInterrupt_3                 ), // Added    for Rel 0 on 6/18
+	.SensorInterrupt_0_o    ( SensorInterrupt_0_FFE             ), // Added    for Rel 0 on 6/18; needs updated FFE
+	.SensorInterrupt_1_o    ( SensorInterrupt_1_FFE             ), // Added    for Rel 0 on 6/18; needs updated FFE
+	.SensorInterrupt_2_o    ( SensorInterrupt_2_FFE             ), // Added    for Rel 0 on 6/18; needs updated FFE
+	.SensorInterrupt_3_o    ( SensorInterrupt_3_FFE             ), // Added    for Rel 0 on 6/18; needs updated FFE
+	.CtrlRunTimeAddressReg	( CtrlRunTimeAddressReg				),
+	.CtrlRunTimeAddressOut	( CtrlRunTimeAddressOut				),
+	.CtrlRunTimeAddressSM 	( CtrlRunTimeAddressSM				),
+	.MemReadAddressOut	( SMSM_ReadAddressFromSensorManager		),
+	.MemReadEnableOut	( SMSM_ReadEnableFromSensorManager		),
+	.MemReadDataIn		( SM_ReadData							),
+	.MemWriteAddressOut	( SMSM_WriteAddressFromSensorManager	),
+	.MemWriteEnableOut	( SMSM_WriteEnableFromSensorManager		),
+	.MemWriteDataOut	( SMSM_WriteDataFromSensorManager		),
+	.MemClockOut		( SMSM_ReadClockFromSensorManager		),
+	.I2C_wb_adr_o       ( I2C_wb_adr_o                          ),
+	.I2C_wb_dat_o       ( I2C_wb_dat_o                          ),
+	.I2C_wb_dat_i       ( I2C_wb_dat_i                          ),
+	.I2C_wb_we_o        ( I2C_wb_we_o                           ),
+	.I2C_wb_stb_o       ( I2C_wb_stb_o                          ),
+	.I2C_wb_cyc_o       ( I2C_wb_cyc_o                          ),
+	.I2C_wb_ack_i       ( I2C_wb_ack_i                          ),
+	.I2C_tip_i          ( I2C_tip_i                             ),
+	.TP1				( TP_SM_1								),
+	.TP2				( TP_SM_2								),
+	.TP3				( TP_SM_3								),
+	.SmClockSelect_o	( SmClockSelect							)
+);
+
+
+
+	// 4k CM
+	FFEControlMemory_4k u_FFEControlMemory (
+		// General Interface
+		.ResetIn				( ResetIn					),
+		.SPI_clk				( SPI_SCLK_gclk				),
+		.TLC_FFE_clk2x_muxed	( FFE_Control_Clock_x2_gclk	),
+
+		.MemSelect_en			( TLC_MemorySelect_en		),
+		.MemSelect				( TLC_MemorySelect			),
+
+		.FFE_clock_halfperiod	( FFE_clock_halfperiod		),
+
+		.Address_TLC			( TLC_MemoryAddress			),
+
+		.MemoryMux_in			( MemoryDataFromDM1Mux		),
+		.MemoryMux_out			( TlcMemoryDataFromMemory	),
+
+		//Read Interface
+		.ReadAddress_FFE		( FFECM_ReadAddressFromFFE	),
+		.ReadData				( FFECM_ReadData			),
+		.ReadEnable_TLC			( TLC_ReadEnable			),
+		.ReadEnable_FFE			( FFECM_ReadEnableFromFFE	),
+
+		//Write Interface
+		.WriteData_TLC			( TLC_MemoryDataToMemory	),
+		.WriteEnable_TLC		( TLC_WriteEnable			),
+
+		// ASSP RAM interface - left bank
+		.assp_lb_ram0_clk		( assp_lb_ram0_clk			),
+		.assp_lb_ram0_addr		( assp_lb_ram0_addr			),
+		.assp_lb_ram0_wr_data	( assp_lb_ram0_wr_data		),
+		.assp_lb_ram0_rd_data	( assp_lb_ram0_rd_data		),
+		.assp_lb_ram0_wr_en		( assp_lb_ram0_wr_en		),
+		.assp_lb_ram0_rd_en		( assp_lb_ram0_rd_en		),
+		.assp_lb_ram0_wr_be		( assp_lb_ram0_wr_be		),
+
+		// ASSP RAM interface - right bank
+		.assp_rb_ram1_clk		( assp_rb_ram1_clk			),
+		.assp_rb_ram1_addr		( assp_rb_ram1_addr			),
+		.assp_rb_ram1_wr_data	( assp_rb_ram1_wr_data		),
+		.assp_rb_ram1_rd_data	( assp_rb_ram1_rd_data		),
+		.assp_rb_ram1_wr_en		( assp_rb_ram1_wr_en		),
+		.assp_rb_ram1_rd_en		( assp_rb_ram1_rd_en		),
+		.assp_rb_ram1_wr_be		( assp_rb_ram1_wr_be		),
+
+		// ASSP RAM interface - 8k - left bank
+		.assp_lb_ram8k_clk		( assp_lb_ram8k_clk			),
+		.assp_lb_ram8k_addr		( assp_lb_ram8k_addr		),
+		.assp_lb_ram8k_wr_data	( assp_lb_ram8k_wr_data		),
+		.assp_lb_ram8k_rd_data	( assp_lb_ram8k_rd_data		),
+		.assp_lb_ram8k_wr_en	( assp_lb_ram8k_wr_en		),
+		.assp_lb_ram8k_rd_en	( assp_lb_ram8k_rd_en		),
+		.assp_lb_ram8k_wr_be	( assp_lb_ram8k_wr_be		),
+		
+		.FFEControlMemory_4k_Address_TLC_o 				(   FFEControlMemory_4k_Address_TLC_o 			),	
+		.FFEControlMemory_4k_ReadAddress_muxed_o        (   FFEControlMemory_4k_ReadAddress_muxed_o     ),
+		.FFEControlMemory_4k_ram5_wr_en_o  			    (   FFEControlMemory_4k_ram5_wr_en_o  			), 
+		.FFEControlMemory_4k_ram5_rd_en_o 			    (   FFEControlMemory_4k_ram5_rd_en_o 			), 
+		.FFEControlMemory_4k_SPI_clk_o 				    (   FFEControlMemory_4k_SPI_clk_o 				), 
+		.FFEControlMemory_4k_TLC_FFE_clk2x_muxed_o 	    (   FFEControlMemory_4k_TLC_FFE_clk2x_muxed_o 	), 
+		.FFEControlMemory_4k_WriteData_TLC_o            (   FFEControlMemory_4k_WriteData_TLC_o         ),
+		.FFEControlMemory_4k_ram5_rd_data_i 			(   FFEControlMemory_4k_ram5_rd_data_i 		    ),
+		.FFEControlMemory_4k_ram4_wr_en_o               (   FFEControlMemory_4k_ram4_wr_en_o            ),
+		.FFEControlMemory_4k_ram4_rd_en_o               (   FFEControlMemory_4k_ram4_rd_en_o            ),
+		.FFEControlMemory_4k_ram4_rd_data_i             (   FFEControlMemory_4k_ram4_rd_data_i          ),
+		.FFEControlMemory_4k_fabric_ram1Kx9_addr_o      (   FFEControlMemory_4k_fabric_ram1Kx9_addr_o   ),
+		.FFEControlMemory_4k_ram1_wr_en_o               (   FFEControlMemory_4k_ram1_wr_en_o            ),
+		.FFEControlMemory_4k_ram1_rd_en_o               (   FFEControlMemory_4k_ram1_rd_en_o            ),
+		.FFEControlMemory_4k_ram1_rd_data_i             (   FFEControlMemory_4k_ram1_rd_data_i          )
+		
+	
+		
+	);
+
+
+
+
+// connections to the ASSP RAM blocks
+assign FCM0_CLK_o			= assp_lb_ram0_clk;
+assign #2 FCM0_ADDR_o		= assp_lb_ram0_addr;
+assign #2 FCM0_WR_DATA_o	= assp_lb_ram0_wr_data;
+assign assp_lb_ram0_rd_data = FCM0_RD_DATA_i;
+assign #2 FCM0_WR_EN_o		= assp_lb_ram0_wr_en;
+assign #2 FCM0_RD_EN_o		= assp_lb_ram0_rd_en;
+assign #2 FCM0_WR_BE_o		= assp_lb_ram0_wr_be;
+
+assign FCM1_CLK_o			= assp_rb_ram1_clk;
+assign #2 FCM1_ADDR_o		= assp_rb_ram1_addr;
+assign #2 FCM1_WR_DATA_o	= assp_rb_ram1_wr_data;
+assign assp_rb_ram1_rd_data	= FCM1_RD_DATA_i;
+assign #2 FCM1_WR_EN_o		= assp_rb_ram1_wr_en;
+assign #2 FCM1_RD_EN_o		= assp_rb_ram1_rd_en;
+assign #2 FCM1_WR_BE_o		= assp_rb_ram1_wr_be;
+
+	assign FCM8K_CLK_o				= assp_lb_ram8k_clk;
+	assign #2 FCM8K_ADDR_o			= assp_lb_ram8k_addr;
+	assign #2 FCM8K_WR_DATA_o		= assp_lb_ram8k_wr_data;
+	assign assp_lb_ram8k_rd_data	= FCM8K_RD_DATA_i;
+	assign #2 FCM8K_WR_EN_o			= assp_lb_ram8k_wr_en;
+	assign #2 FCM8K_RD_EN_o			= assp_lb_ram8k_rd_en;
+	assign #2 FCM8K_WR_BE_o			= assp_lb_ram8k_wr_be;
+
+
+	// extended-length DM
+
+	// If an extended-length DM is used, physical DM1 is the lower half of logical DM1.
+	// Therefore, the TLC select for DM1 must be combined with the most-significant address bit.
+
+	assign extended_DM1_select = TlcFfeDM1MuxSelect && !TLC_MemoryAddress[9];
+
+	FFEDataMemoryMux u_FFEDataMemory1Mux (
+		.Select				( extended_DM1_select			),
+
+		.ReadAddressIn0		( FFEDM1_ReadAddressFromFFE		),
+		.ReadAddressIn1		( TLC_MemoryAddress[9:0]		),
+		.ReadAddressOut		( FFEDM1_ReadAddress			),
+
+		.WriteAddressIn0	( FFEDM1_WriteAddressFromFFE	),
+		.WriteAddressIn1	( TLC_MemoryAddress[9:0]		),
+		.WriteAddressOut	( FFEDM1_WriteAddress			),
+
+		.DataToMemoryIn0	( FFEDM1_WriteDataFromFFE		),
+		.DataToMemoryIn1	( TLC_MemoryDataToMemory		),
+		.DataToMemoryOut	( FFEDM1_WriteData				),
+
+		.DataFromMemoryIn0	( MemoryDataFromDM2Mux			),
+		.DataFromMemoryIn1	( FFEDM1_ReadData				),
+		.DataFromMemoryOut	( MemoryDataFromDM1Mux			),
+
+		.ReadEnable0		( FFEToDM1Mux_ReadEnable		),
+		.ReadEnable1		( TLC_ReadEnable				),
+		.ReadEnable			( FFEDM1_ReadSelect				),
+
+		.WriteEnable0		( FFEToDM1Mux_WriteEnable		),
+		.WriteEnable1		( TLC_WriteEnable				),
+		.WriteEnable		( FFEDM1_WriteSelect			)
+	);
+
+
+
+
+// DM1 clock
+	// single-DM: use 2x FFE clock
+	assign FFEDM1_ReadClock	= FFE_Control_Clock_x2_gclk;
+	assign FFEDM1_WriteClock = FFE_Control_Clock_x2_gclk;
+
+
+
+assign DMM1_WR_CLK_o		= FFEDM1_WriteClock;
+assign #2 DMM1_WR_ADDR_o	= FFEDM1_WriteAddress;
+assign #2 DMM1_WR_DATA_o	= FFEDM1_WriteData[31:0];
+assign #2 DMM1_WR_EN_o 		= FFEDM1_WriteSelect;
+assign #2 DMM1_WR_BE_o 		= 4'b1111;
+assign DMM1_RD_CLK_o		= FFEDM1_ReadClock;
+assign #2 DMM1_RD_ADDR_o	= FFEDM1_ReadAddress;
+assign FFEDM1_ReadData		= {4'b0, DMM1_RD_DATA_i};
+assign #2 DMM1_RD_EN_o 		= FFEDM1_ReadSelect;
+
+
+// extended-length DM
+
+	// If an extended-length DM is used, physical DM2 is the upper half of logical DM1, according to s/w.
+	// Therefore, the TLC select for DM1 must be combined with the most-significant address bit.
+
+	assign extended_DM2_select = TlcFfeDM1MuxSelect && TLC_MemoryAddress[9];
+
+	FFEDataMemoryMux u_FFEDataMemory2Mux (
+
+		.Select				( extended_DM2_select				),
+
+		.ReadAddressIn0		( FFEDM2_ReadAddressFromFFE			),
+		.ReadAddressIn1		( TLC_MemoryAddress[9:0]			),
+		.ReadAddressOut		( FFEDM2_ReadAddress				),
+
+		.WriteAddressIn0	( FFEDM2_WriteAddressFromFFE		),
+		.WriteAddressIn1	( TLC_MemoryAddress[9:0]			),
+		.WriteAddressOut	( FFEDM2_WriteAddress				),
+
+		.DataToMemoryIn0	( FFEDM2_WriteDataFromFFE			),
+		.DataToMemoryIn1	( TLC_MemoryDataToMemory			),
+		.DataToMemoryOut	( FFEDM2_WriteData					),
+
+		.DataFromMemoryIn0	( {18'h00000,MemoryDataFromSMMux}	),
+		.DataFromMemoryIn1	( FFEDM2_ReadData					),
+		.DataFromMemoryOut	( MemoryDataFromDM2Mux				),
+
+		.ReadEnable0		( FFEToDM2Mux_ReadEnable			),
+		.ReadEnable1		( TLC_ReadEnable					),
+		.ReadEnable			( FFEDM2_ReadSelect					),
+
+		.WriteEnable0		( FFEDM2_WriteEnable				),
+		.WriteEnable1		( TLC_WriteEnable					),
+		.WriteEnable		( FFEDM2_WriteSelect				)
+	);
+
+
+// extended-length single-DM: DM2 driven by the 2x FFE clock
+		assign FFEDM2_ReadClock = FFE_Control_Clock_x2_gclk;
+		assign FFEDM2_WriteClock = FFE_Control_Clock_x2_gclk;
+
+
+
+// DM2 signal connections
+	// single-DM
+
+		// extended-length single-DM
+
+		// connect to DM2 as usual (note that the FFE_control module should drive these signals correctly,
+		//		accounting for the double-clock rate and the extended length).
+		assign DMM2_WR_CLK_o		= FFEDM2_WriteClock;
+		assign #2 DMM2_WR_ADDR_o	= FFEDM2_WriteAddress;
+		assign #2 DMM2_WR_DATA_o	= FFEDM2_WriteData[31:0];
+		assign #2 DMM2_WR_EN_o		= FFEDM2_WriteSelect;
+		assign #2 DMM2_WR_BE_o		= 4'b1111;
+		assign DMM2_RD_CLK_o		= FFEDM2_ReadClock;
+		assign #2 DMM2_RD_ADDR_o	= FFEDM2_ReadAddress;
+		assign #2 FFEDM2_ReadData	= {4'b0, DMM2_RD_DATA_i};
+		assign #2 DMM2_RD_EN_o		= FFEDM2_ReadSelect;
+
+
+
+assign ReadAddressFromSMorFFE  = SMBusy ? SMSM_ReadAddressFromSensorManager  :        SMSM_ReadAddressFromFFE;   // Expanded for Rel 0 on 6/18
+assign ReadEnableFromSMorFFE   = SMBusy ? SMSM_ReadEnableFromSensorManager   :        SMSM_ReadEnableFromFFE;
+
+assign WriteAddressFromSMorFFE = SMBusy ? SMSM_WriteAddressFromSensorManager :        SMSM_WriteAddressFromFFE;  // New      for Rel 0 on 6/18
+assign WriteEnableFromSMorFFE  = SMBusy ? SMSM_WriteEnableFromSensorManager  :        SMSM_WriteEnableFromFFE;   // New      for Rel 0 on 6/18
+assign WriteDataFromSMorFFE    = SMBusy ? SMSM_WriteDataFromSensorManager    :        SMSM_WriteDataFromFFE;     // New      for Rel 0 on 6/18
+
+SMEMemoryMux u_SMEMemoryMux (
+	.Select				( TLC_SMMuxSelect									),
+
+	.ReadAddressIn0		( ReadAddressFromSMorFFE							),
+	.ReadAddressIn1		( TLC_MemoryAddress[9:0]	 						),      // Expanded for Rel 0 on 6/18
+	.ReadAddressOut		( SM_ReadAddress									),
+
+	.WriteAddressIn0	( WriteAddressFromSMorFFE							),      // Expanded for Rel 0 on 6/18
+	.WriteAddressIn1	( TLC_MemoryAddress[9:0]							),
+	.WriteAddressOut	( SM_WriteAddress									),
+
+	.DataToMemoryIn0	( WriteDataFromSMorFFE								),      // New      for Rel 0 on 6/18
+	.DataToMemoryIn1	( TLC_MemoryDataToMemory[8:0]						),
+	.DataToMemoryOut	( SM_WriteData										),
+
+	.DataFromMemoryIn0	( {9'h000, 9'h123}									),
+	.DataFromMemoryIn1	( SM_ReadData										),
+	.DataFromMemoryOut	( MemoryDataFromSMMux								),
+
+	.ReadEnableIn0		( ReadEnableFromSMorFFE								),
+	.ReadEnableIn1		( TLC_ReadEnable									),
+	.ReadEnableOut		( SM_ReadSelect										),
+
+	.WriteEnableIn0		( WriteEnableFromSMorFFE							),      // New      for Rel 0 on 6/18
+	.WriteEnableIn1		( TLC_WriteEnable & ( TLC_MemoryAddress[10])		),      // Expanded for Rel 0 on 6/18
+	.WriteEnableOut		( SM_WriteSelect									),
+
+	.ReadClockIn0		( FFE_Control_Clock_gclk							),		// = ClockIn or Clock32K
+	.ReadClockIn1		( TLC_MemoryClock									),		// = ClockIn
+	.ReadClockOut		( 													)		// use external SM_ReadClock logic instead of this mux
+);
+
+
+SMMemory u_SMMemory (
+	.ResetIn			( ResetIn			),
+	.SMBusyIn			( SMBusy			),
+
+	//Read Interface  - Both   512 x 18 Memory Blocks
+	.ReadAddressIn		( SM_ReadAddress	),
+	.ReadDataOut		( SM_ReadData		),
+	.ReadSelectIn		( SM_ReadSelect		),
+	.ReadClockIn		( SM_Clock_gclk		),
+
+	//Write Interface - Lower 1024 x  9 Memory Block
+	.WriteAddressIn_TLC	( TLC_MemoryAddress[9:0]				),                  // New      for Rel 0 on 6/18
+	.WriteDataIn_TLC	( TLC_MemoryDataToMemory[8:0]			),                  // New      for Rel 0 on 6/18
+	.WriteSelectIn_TLC	( TLC_WriteEnable & (~TLC_MemoryAddress[10])),              // New      for Rel 0 on 6/18
+
+	//Write Interface - Upper 1024 x  9 Memory Block
+	.WriteAddressIn		( SM_WriteAddress	),
+	.WriteDataIn		( SM_WriteData		),
+	.WriteSelectIn		( SM_WriteSelect	),
+	.WriteClockIn		( SM_Clock_gclk		),
+	
+    .SMMemory_WriteAddressIn_TLC_o  ( SMMemory_WriteAddressIn_TLC_o ),
+	.SMMemory_ReadAddressIn_o         ( SMMemory_ReadAddressIn_o        ),
+	.SMMemory_WriteSelectIn_TLC_o   ( SMMemory_WriteSelectIn_TLC_o  ),
+	.SMMemory_ReadSelect_RAM0_o     ( SMMemory_ReadSelect_RAM0_o    ),
+	.SMMemory_WriteClockIn_o        ( SMMemory_WriteClockIn_o       ),
+	.SMMemory_ReadClockIn_o         ( SMMemory_ReadClockIn_o        ),
+	.SMMemory_WriteDataIn_TLC_o     ( SMMemory_WriteDataIn_TLC_o    ),
+	.SMMemory_ReadDataOut_SRAM_i    ( SMMemory_ReadDataOut_SRAM_i   ),
+	.SMMemory_WriteAddressIn_o	    (	SMMemory_WriteAddressIn_o	),
+	.SMMemory_WriteSelectIn_o       (	SMMemory_WriteSelectIn_o 	),
+	.SMMemory_ReadSelect_RAM1_o      (	SMMemory_ReadSelect_RAM1_o   	),
+	.SMMemory_WriteDataIn_o         (	SMMemory_WriteDataIn_o   	),
+	.SMMemory_ReadDataOut_SRAM1_i    (	SMMemory_ReadDataOut_SRAM1_i 	)
+	
+);
+
+
+	// 4k CM
+	CM_FIFO_1x CM_FIFO_1x_1 (
+		.rst		( ResetIn					),
+
+		.push_clk	( FFE_Control_Clock_gclk	),
+		.push		( CM_WriteEnableFromFFE		),
+		.din		( CM_WriteDataFromFFE		),
+		.full		( CM_FIFO_full				),
+		.push_flag	( CM_FIFO_Push_Flags		),
+		.overflow	( CM_FIFO_Overflow			),
+
+		.pop_clk	( CM_FIFO_ReadClk_gclk		),
+		.pop		( CM_FIFO_ReadEnable		),
+		.dout		( CM_FIFO_ReadData			),
+		.empty		( CM_FIFO_empty				),
+		.pop_flag	( CM_FIFO_Pop_Flags			),
+		
+		.CM_FIFO_1x_din_o				(	CM_FIFO_1x_din_o			),			
+		.CM_FIFO_1x_push_int_o		    (	CM_FIFO_1x_push_int_o		),
+		.CM_FIFO_1x_pop_int_o		    (	CM_FIFO_1x_pop_int_o		),
+		.CM_FIFO_1x_push_clk_o		    (	CM_FIFO_1x_push_clk_o		),
+		.CM_FIFO_1x_pop_clk_o		    (	CM_FIFO_1x_pop_clk_o		),
+		.CM_FIFO_1x_rst_o			    (	CM_FIFO_1x_rst_o			),
+		                                
+		.CM_FIFO_1x_almost_full_i	    (	CM_FIFO_1x_almost_full_i	),
+		.CM_FIFO_1x_almost_empty_i	    (	CM_FIFO_1x_almost_empty_i	),
+		.CM_FIFO_1x_push_flag_i		    (	CM_FIFO_1x_push_flag_i		),
+		.CM_FIFO_1x_pop_flag_i		    (	CM_FIFO_1x_pop_flag_i		),
+		.CM_FIFO_1x_dout_i			    (	CM_FIFO_1x_dout_i			)
+		
+		
+		
+		
+	);
+
+
+
+
+// auto drain module, to support Ring Buffer Mode
+CM_FIFO_autodrain CM_FIFO_autodrain_1 (
+	.rst					( ResetIn					),
+	.FFE_CLK_gclk			( CM_FIFO_ReadClk_gclk	),
+	//.FFE_CLK_gclk			( FFE_Control_Clock_gclk	),
+
+	.RingBufferMode			( CM_RingBufferMode			),
+	.CM_FIFO_PushFlags		( CM_FIFO_Push_Flags		),
+	.CM_FIFO_Empty			( CM_FIFO_empty				),
+	.CM_FIFO_PopFromTLC		( CM_FIFO_PopFromTLC		),
+	.CM_FIFO_ReadData		( CM_FIFO_ReadData			),
+
+	.CM_FIFO_Pop			( CM_FIFO_ReadEnable		),
+	.busy					( CM_AutoDrain_Busy			),
+	.TP1					( CM_ad_TP1					),
+	.TP2					( )
+);
+
+
+// LED
+assign LED1	= !CM_RingBufferMode;
+
+// Standard
+/*
+assign TP1 = 0;
+assign TP2 = 0;
+assign TP3 = 0;
+*/
+
+
+// For LEDs Demo Control
+
+assign TP1 = LEDS_CTRL[0];
+assign TP2 = LEDS_CTRL[1];
+assign TP3 = LEDS_CTRL[2];
+
+	
+	
+
+	
+endmodule
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/Aurora/primitive_macros.v b/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/Aurora/primitive_macros.v
new file mode 100644
index 0000000..5e212c6
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/Aurora/primitive_macros.v
@@ -0,0 +1,126 @@
+/***************************************************
+ Vendor          : QuickLogic Corp.
+ Aurora Version  : AU 1.0.0 			
+ File Name       : primtive_macros.v			
+ Author          : Kishor Kumar 
+ Description     : Verilog Netlist File (For Synthesis/Pre-Layout Simulation)									
+*****************************************************/
+
+/*-------------------------------------------------------------------------------
+ MODULE NAME : ck_buff 
+ DESCRIPTION : Clock tree buffer						
+--------------------------------------------------------------------------------*/
+`ifdef ck_buff
+`else
+`define ck_buff
+module ck_buff ( A , Q )/* synthesis black_box black_box_pad_pin = "A" */;
+input A/* synthesis syn_isclock=1 */;
+output Q;
+//pragma synthesis_off
+//pragma synthesis_on
+endmodule /* ck buff */
+`endif
+
+/*-------------------------------------------------------------------------------
+ MODULE NAME : gclkbuff 
+ DESCRIPTION : Global clock buffer						
+--------------------------------------------------------------------------------*/
+`ifdef GCLKBUFF
+`else
+`define GCLKBUFF
+module GCLKBUFF ( A , Z )/* synthesis black_box */;
+input A;
+output Z;
+//pragma synthesis_off
+//pragma synthesis_on
+endmodule /* gclk buff */
+`endif
+
+/*-------------------------------------------------------------------------------
+ MODULE NAME : in_buff 
+ DESCRIPTION : Input buffer					
+--------------------------------------------------------------------------------*/
+`ifdef in_buff
+`else
+`define in_buff
+module in_buff ( A , Q )/* synthesis black_box */;
+input A;
+output Q;
+//pragma synthesis_off
+//pragma synthesis_on
+endmodule /* in buff */
+`endif
+
+/*-------------------------------------------------------------------------------
+ MODULE NAME : out_buff 
+ DESCRIPTION : Output buffer					
+--------------------------------------------------------------------------------*/
+`ifdef out_buff
+`else
+`define out_buff
+module out_buff ( A , Q )/* synthesis black_box */;
+input A;
+output Q;
+//pragma synthesis_off
+//pragma synthesis_on
+endmodule /* out buff */
+`endif
+
+/*-------------------------------------------------------------------------------
+ MODULE NAME : inv 
+ DESCRIPTION : Inverter						
+--------------------------------------------------------------------------------*/
+`ifdef inv
+`else
+`define inv
+module inv ( A , Q )/* synthesis black_box */;
+input A;
+output Q;
+//pragma synthesis_off
+//pragma synthesis_on
+endmodule /*inverter*/
+`endif
+
+/*-------------------------------------------------------------------------------
+ MODULE NAME : buff 
+ DESCRIPTION : Buffer 					
+--------------------------------------------------------------------------------*/
+`ifdef buff
+`else
+`define buff
+module buff ( A , Q )/* synthesis black_box */;
+input A;
+output Q;
+//pragma synthesis_off
+//pragma synthesis_on
+endmodule /*buffer*/
+`endif
+
+/*-------------------------------------------------------------------------------
+ MODULE NAME : mux2x0 
+ DESCRIPTION : Basic Mux 2:1					
+--------------------------------------------------------------------------------*/
+`ifdef mux2x0
+`else
+`define mux2x0
+module mux2x0 ( A , B, S, Q )/* synthesis black_box */;
+input A, B, S;
+output Q;
+//pragma synthesis_off
+//pragma synthesis_on
+endmodule /*mux2x0*/
+`endif
+
+`ifdef LOGIC_Cell
+`else
+`define LOGIC_Cell
+module LOGIC_Cell (T0I0, T0I1, T0I2, T0I3, B0I0, B0I1, B0I2, B0I3, 
+            TB0S, Q0DI, CD0S, Q0EN, QST, QRT, QCK, QCKS, C0Z, Q0Z, B0Z)/* synthesis black_box */;
+input T0I0, T0I1, T0I2, T0I3, B0I0, B0I1, B0I2, B0I3;
+input TB0S, Q0DI, CD0S, Q0EN;				  
+input QST, QRT, QCK, QCKS;
+output C0Z, B0Z, Q0Z;
+//pragma synthesis_off
+//pragma synthesis_on
+endmodule /*LOGIC_Cell*/
+`endif
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/Aurora/qlprim.v b/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/Aurora/qlprim.v
new file mode 100644
index 0000000..38d205c
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/Aurora/qlprim.v
@@ -0,0 +1,1853 @@
+/***************************************************
+ Vendor        : QuickLogic Corp.
+ File Name     : qlprim.v
+ Description   : Behavioral model of Logic cell
+ Revisions     : Added specify blocks for Logic cell, GPIO and RAM
+ Author        : Kishor
+*****************************************************/
+
+// logic cell ------------------------------------------------------------------
+`timescale 1ns/10ps
+
+////////////////   Implementation of the LUT   //////////////////////
+module LUT (fragBitInfo, 
+            I0, 
+            I1, 
+            I2, 
+            I3, 
+            LUTOutput,
+			CarryOut 
+			);
+
+input [15:0] fragBitInfo; 
+input I0, I1, I2, I3;
+output LUTOutput; 
+output CarryOut;
+
+wire stage0_op0, stage0_op1, stage0_op2, stage0_op3, stage0_op4, stage0_op5, stage0_op6, stage0_op7; 
+wire stage1_op0, stage1_op1, stage1_op2, stage1_op3;
+wire stage2_op0, stage2_op1;
+
+//wire carry_mux_op;
+
+//assign carry_mux_op = CIS ? I2 : Cin;
+
+assign stage0_op0 = I0 ? fragBitInfo[1] : fragBitInfo[0];
+assign stage0_op1 = I0 ? fragBitInfo[3] : fragBitInfo[2];
+assign stage0_op2 = I0 ? fragBitInfo[5] : fragBitInfo[4];
+assign stage0_op3 = I0 ? fragBitInfo[7] : fragBitInfo[6];
+assign stage0_op4 = I0 ? fragBitInfo[9] : fragBitInfo[8];
+assign stage0_op5 = I0 ? fragBitInfo[11] : fragBitInfo[10];
+assign stage0_op6 = I0 ? fragBitInfo[13] : fragBitInfo[12];
+assign stage0_op7 = I0 ? fragBitInfo[15] : fragBitInfo[14];
+
+
+assign stage1_op0 = I1 ? stage0_op1 : stage0_op0; 
+assign stage1_op1 = I1 ? stage0_op3 : stage0_op2;
+assign stage1_op2 = I1 ? stage0_op5 : stage0_op4;
+assign stage1_op3 = I1 ? stage0_op7 : stage0_op6;
+
+
+assign stage2_op0 = I2 ? stage1_op1 : stage1_op0;
+assign stage2_op1 = I2 ? stage1_op3 : stage1_op2;
+
+
+assign LUTOutput = I3 ? stage2_op1 : stage2_op0;
+assign CarryOut = stage2_op1;
+
+endmodule
+
+
+module ONE_LOGIC_CELL (
+		tFragBitInfo,
+		bFragBitInfo,
+        TI0,
+        TI1,
+        TI2, 
+        TI3,
+        BI0, 
+        BI1,
+        BI2,
+        BI3,
+        TBS, 
+        QDI,
+        CDS,
+        QEN,
+        QST,
+        QRT,
+        QCK,
+        QCKS,
+        CZ,
+        QZ,
+        BZ,
+        BCO,
+		TCO);
+
+input [15:0] tFragBitInfo;
+input [15:0] bFragBitInfo;
+input TI0, TI1, TI2, TI3, BI0, BI1, BI2, BI3, TBS, QDI, CDS, QEN, QST, QRT, QCK, QCKS;
+
+output  CZ, QZ, BZ, BCO, TCO;
+
+
+wire tFragLUTOutput, bFragLUTOutput;
+
+wire mux_tbs_op, mux_cds_op, mux_bqs_op; 
+
+reg QZ_reg;
+
+
+LUT tLUT (.fragBitInfo(tFragBitInfo), .I0(TI0), .I1(TI1), .I2(TI2), .I3(TI3), .LUTOutput(tFragLUTOutput), .CarryOut(TCO));
+LUT bLUT (.fragBitInfo(bFragBitInfo), .I0(BI0), .I1(BI1), .I2(BI2), .I3(BI3), .LUTOutput(bFragLUTOutput), .CarryOut(BCO));
+
+
+assign mux_tbs_op = TBS ? bFragLUTOutput : tFragLUTOutput;
+assign mux_cds_op = CDS ? QDI : mux_tbs_op;
+
+
+/* synopsys translate off */
+always @ (posedge QCK)   
+begin
+	if(~QRT && ~QST )
+		if(QEN)
+        	QZ_reg = mux_cds_op;
+end
+	
+always @(QRT or QST)
+begin
+	if(QRT)
+		 QZ_reg = 1'b0;
+	else if (QST)
+		 QZ_reg = 1'b1;
+end
+
+
+assign CZ = mux_tbs_op; 
+assign BZ = bFragLUTOutput;
+
+assign QZ = QZ_reg;
+//assign BQZ = mux_bqs_op;
+
+endmodule 
+
+
+module LOGIC (
+		tFragBitInfo, 
+		bFragBitInfo,
+        T0I0, 
+        T0I1,
+        T0I2,
+        T0I3,
+        B0I0, 
+        B0I1,
+        B0I2,
+        B0I3,
+        TB0S, 
+        Q0DI,
+        CD0S,
+        Q0EN,
+        T1I0,
+        T1I1,
+        T1I2,
+        T1I3,
+        B1I0, 
+        B1I1,
+        B1I2,
+        B1I3,
+        TB1S, 
+        Q1DI,
+        CD1S,
+        Q1EN,
+        T2I0,
+        T2I1,
+        T2I2,
+        T2I3,
+        B2I0, 
+        B2I1,
+        B2I2,
+        B2I3,
+        TB2S, 
+        Q2DI,
+        CD2S,
+        Q2EN,
+        T3I0,
+        T3I1,
+        T3I2,
+        T3I3,
+        B3I0, 
+        B3I1,
+        B3I2,
+        B3I3,
+        TB3S, 
+        Q3DI,
+        CD3S,
+        Q3EN,
+        QST, 
+        QRT,
+        QCK,
+        QCKS,
+        C0Z,
+        Q0Z,
+        B0Z,
+        C1Z,
+        Q1Z,
+        B1Z,
+        C2Z,
+        Q2Z,
+        B2Z,
+        C3Z,
+        Q3Z,
+        B3Z,
+		T0CO, 
+		B0CO, 
+        T3CO, 
+        B3CO, 
+		T1CO, 
+		B1CO, 
+		T2CO, 
+		B2CO);
+
+input [63:0] tFragBitInfo;
+input [63:0] bFragBitInfo;
+input  T0I0; 
+input  T0I1;
+input  T0I2;
+input  T0I3;
+input  B0I0; 
+input  B0I1;
+input  B0I2;
+input  B0I3;
+input  TB0S; 
+input  Q0DI;
+input  CD0S;
+input  Q0EN;
+input  T1I0;
+input  T1I1;
+input  T1I2;
+input  T1I3;
+input  B1I0; 
+input  B1I1;
+input  B1I2;
+input  B1I3;
+input  TB1S; 
+input  Q1DI;
+input  CD1S;
+input  Q1EN;
+input  T2I0;
+input  T2I1;
+input  T2I2;
+input  T2I3;
+input  B2I0; 
+input  B2I1;
+input  B2I2;
+input  B2I3;
+input  TB2S; 
+input  Q2DI;
+input  CD2S;
+input  Q2EN;
+input  T3I0;
+input  T3I1;
+input  T3I2;
+input  T3I3;
+input  B3I0; 
+input  B3I1;
+input  B3I2;
+input  B3I3;
+input  TB3S; 
+input  Q3DI;
+input  CD3S;
+input  Q3EN;
+input  QST;
+input  QRT;
+input  QCK;
+input  QCKS;
+output  C0Z;
+output  Q0Z;
+output  B0Z;
+output  C1Z;
+output  Q1Z;
+output  B1Z;
+output  C2Z;
+output  Q2Z;
+output  B2Z;
+output  C3Z;
+output  Q3Z;
+output  B3Z;
+output  T3CO; 
+output  B3CO;
+output  T0CO; 
+output  B0CO; 
+output  T1CO; 
+output  B1CO; 
+output  T2CO; 	
+output  B2CO;
+
+
+ONE_LOGIC_CELL logic0(
+		.tFragBitInfo (tFragBitInfo[15:0]),
+		.bFragBitInfo (bFragBitInfo[15:0]),
+        .TI0 (T0I0),
+        .TI1 (T0I1),
+        .TI2 (T0I2), 
+        .TI3 (T0I3),
+        .BI0 (B0I0), 
+        .BI1 (B0I1),
+        .BI2 (B0I2),
+        .BI3 (B0I3),
+        .TBS (TB0S), 
+        .QDI (Q0DI),
+        .CDS (CD0S),
+        .QEN (Q0EN),
+        .QST (QST),
+        .QRT (QRT),
+        .QCK (QCK),
+        .QCKS (QCKS),
+        .CZ (C0Z),
+        .QZ (Q0Z),
+        .BZ (B0Z),
+        .TCO (T0CO), 
+        .BCO (B0CO)); 
+
+ONE_LOGIC_CELL logic1(
+		.tFragBitInfo (tFragBitInfo[31:16]),
+		.bFragBitInfo (bFragBitInfo[31:16]),
+        .TI0 (T1I0),
+        .TI1 (T1I1),
+        .TI2 (T1I2), 
+        .TI3 (T1I3),
+        .BI0 (B1I0), 
+        .BI1 (B1I1),
+        .BI2 (B1I2),
+        .BI3 (B1I3),
+        .TBS (TB1S), 
+        .QDI (Q1DI),
+        .CDS (CD1S),
+        .QEN (Q1EN),
+        .QST (QST),
+        .QRT (QRT),
+        .QCK (QCK),
+        .QCKS (QCKS),
+        .CZ (C1Z),
+        .QZ (Q1Z),
+        .BZ (B1Z),
+        .TCO (T1CO), 
+        .BCO (B1CO)); 
+
+ONE_LOGIC_CELL logic2(
+		.tFragBitInfo (tFragBitInfo[47:32]),
+		.bFragBitInfo (bFragBitInfo[47:32]),
+        .TI0 (T2I0),
+        .TI1 (T2I1),
+        .TI2 (T2I2), 
+        .TI3 (T2I3),
+        .BI0 (B2I0), 
+        .BI1 (B2I1),
+        .BI2 (B2I2),
+        .BI3 (B2I3),
+        .TBS (TB2S), 
+        .QDI (Q2DI),
+        .CDS (CD2S),
+        .QEN (Q2EN),
+        .QST (QST),
+        .QRT (QRT),
+        .QCK (QCK),
+        .QCKS (QCKS),
+        .CZ (C2Z),
+        .QZ (Q2Z),
+        .BZ (B2Z),
+        .TCO (T2CO),
+        .BCO (B2CO));
+
+ONE_LOGIC_CELL logic3(
+		.tFragBitInfo (tFragBitInfo[63:48]),
+		.bFragBitInfo (bFragBitInfo[63:48]),
+        .TI0 (T3I0),
+        .TI1 (T3I1),
+        .TI2 (T3I2), 
+        .TI3 (T3I3),
+        .BI0 (B3I0), 
+        .BI1 (B3I1),
+        .BI2 (B3I2),
+        .BI3 (B3I3),
+        .TBS (TB3S), 
+        .QDI (Q3DI),
+        .CDS (CD3S),
+        .QEN (Q3EN),
+        .QST (QST),
+        .QRT (QRT),
+        .QCK (QCK),
+        .QCKS (QCKS),
+        .CZ (C3Z),
+        .QZ (Q3Z),
+        .BZ (B3Z),
+        .TCO (T3CO),
+        .BCO (B3CO)); 
+specify
+
+	(QCK => Q0Z)  = (0,0);
+	(QCK => Q1Z)  = (0,0);
+	(QCK => Q2Z)  = (0,0);
+	(QCK => Q3Z)  = (0,0);
+
+/*
+	if ((B0CIS == 1'b0) && (T0CIS == 1'b0))
+		(T0CI => B0Z)  = (0,0);
+	if (B0CIS == 1'b0)
+		(T0I0 => B0Z)  = (0,0);
+	if (B0CIS == 1'b0)
+		(T0I1 => B0Z)  = (0,0);
+	if ((B0CIS == 1'b1) && (T0CIS == 1'b0))
+		(T0I2 => B0Z)  = (0,0);
+	if (B0CIS == 1'b0)
+		(T0I3 => B0Z)  = (0,0);
+
+	if ((B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(B0I0 => B1Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(B0I1 => B1Z)  = (0,0);
+	if ((B0CIS == 1'b1) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(B0I2 => B1Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(B0I3 => B1Z)  = (0,0);
+
+	if ((T0CIS == 1'b0) && (B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0CI => B1Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0I0 => B1Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0I1 => B1Z)  = (0,0);
+	if ((T0CIS == 1'b1) && (B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0I2 => B1Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0I3 => B1Z)  = (0,0);
+
+	if ((B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(B0I0 => B2Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(B0I1 => B2Z)  = (0,0);
+	if ((B0CIS == 1'b1) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(B0I2 => B2Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(B0I3 => B2Z)  = (0,0);
+
+
+	if ((T0CIS == 1'b0) && (B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(T0CI => B2Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(T0I0 => B2Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(T0I1 => B2Z)  = (0,0);
+	if ((T0CIS == 1'b1) && (B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(T0I2 => B2Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(T0I3 => B2Z)  = (0,0);
+
+	if ((B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(B0I0 => B3Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(B0I1 => B3Z)  = (0,0);
+	if ((B1CIS == 1'b1) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(B0I2 => B3Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(B0I3 => B3Z)  = (0,0);
+
+	if ((T0CIS == 1'b0) && (B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(T0CI => B3Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(T0I0 => B3Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(T0I1 => B3Z)  = (0,0);
+	if ((T0CIS == 1'b1) && (B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(T0I2 => B3Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(T0I3 => B3Z)  = (0,0);
+
+	if ((B1CIS == 1'b0)) 
+		(T1I0 => B1Z)  = (0,0);
+	if ((B1CIS == 1'b0)) 
+		(T1I1 => B1Z)  = (0,0);
+	if ( (T1CIS == 1'b1) && (B1CIS == 1'b0)) 
+		(T1I2 => B1Z)  = (0,0);
+	if ((B1CIS == 1'b0)) 
+		(T1I3 => B1Z)  = (0,0);
+
+	if ((B1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0)) 
+		(T1I0 => B2Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0)) 
+		(T1I1 => B2Z)  = (0,0);
+	if ((T1CIS == 1'b1) && (B1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0)) 
+		(T1I2 => B2Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0)) 
+		(T1I3 => B2Z)  = (0,0);
+
+	if (B2CIS == 1'b0)
+		(T2I0 => B2Z)  = (0,0);
+	if (B2CIS == 1'b0)
+		(T2I1 => B2Z)  = (0,0);
+	if ((T2CIS == 1'b1) && (B2CIS == 1'b0))
+		(T2I2 => B2Z)  = (0,0);
+	if (B2CIS == 1'b0)
+		(T2I3 => B2Z)  = (0,0);
+
+
+	if ((B1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0)) 
+		(T1I0 => B3Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0)) 
+		(T1I1 => B3Z)  = (0,0);
+	if ((T1CIS == 1'b1) && (B1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0)) 
+		(T1I2 => B3Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0)) 
+		(T1I3 => B3Z)  = (0,0);
+
+	if (B2CIS == 1'b0) 
+		(T2I0 => B3Z)  = (0,0);
+	if (B2CIS == 1'b0) 
+		(T2I1 => B3Z)  = (0,0);
+	if ((T2CIS == 1'b1) && (B2CIS == 1'b0))
+		(T2I2 => B3Z)  = (0,0);
+	if (B2CIS == 1'b0) 
+		(T2I3 => B3Z)  = (0,0);
+
+	if (B3CIS == 1'b0) 
+		(T3I0 => B3Z)  = (0,0);
+	if (B3CIS == 1'b0) 
+		(T3I1 => B3Z)  = (0,0);
+	if  ((T3CIS == 1'b1)&& (B3CIS == 1'b0))
+		(T3I2 => B3Z)  = (0,0);
+	if (B3CIS == 1'b0) 
+		(T3I3 => B3Z)  = (0,0);
+
+
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0))
+		(B1I0 => B2Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0))
+		(B1I1 => B2Z)  = (0,0);
+	if ( (B1CIS == 1'b1) && (T2CIS == 1'b0) && (B2CIS == 1'b0))
+		(B1I2 => B2Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0))
+		(B1I3 => B2Z)  = (0,0);
+
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0))
+		(B1I0 => B3Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0))
+		(B1I1 => B3Z)  = (0,0);
+	if ( (B1CIS == 1'b1) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0))
+		(B1I2 => B3Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0))
+		(B1I3 => B3Z)  = (0,0);
+
+	if ((T3CIS == 1'b0) && (B3CIS == 1'b0))
+		(B2I0 => B3Z)  = (0,0);
+	if ((T3CIS == 1'b0) && (B3CIS == 1'b0))
+		(B2I1 => B3Z)  = (0,0);
+	if ((B2CIS == 1'b1) && (T3CIS == 1'b0) && (B3CIS == 1'b0))
+		(B2I2 => B3Z)  = (0,0);
+	if ((T3CIS == 1'b0) && (B3CIS == 1'b0))
+		(B2I3 => B3Z)  = (0,0);
+
+
+	if ((T0CIS == 1'b0) && (B0CIS == 1'b0) && (TB1S == 1'b0))
+		(T0CI => C1Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (TB1S == 1'b0))
+		(T0I0 => C1Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (TB1S == 1'b0))
+		(T0I1 => C1Z)  = (0,0);
+	if ((T0CIS == 1'b1) && (B0CIS == 1'b0) && (TB1S == 1'b0))
+		(T0I2 => C1Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (TB1S == 1'b0))
+		(T0I3 => C1Z)  = (0,0);
+
+	if ((T0CIS == 1'b0) && (B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(T0CI => C2Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(T0I0 => C2Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(T0I1 => C2Z)  = (0,0);
+	if ((T0CIS == 1'b1) && (B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(T0I2 => C2Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(T0I3 => C2Z)  = (0,0);
+
+	if ((B1CIS == 1'b0) &&  (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(T1I0 => C2Z)  = (0,0);
+	if ((B1CIS == 1'b0) &&  (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(T1I1 => C2Z)  = (0,0);
+	if ((T1CIS == 1'b1) && (B1CIS == 1'b0) &&  (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(T1I2 => C2Z)  = (0,0);
+	if ((B1CIS == 1'b0) &&  (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(T1I3 => C2Z)  = (0,0);
+
+	if ((T0CIS == 1'b0) && (B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T0CI => C3Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T0I0 => C3Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T0I1 => C3Z)  = (0,0);
+	if ((T0CIS == 1'b1) && (B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T0I2 => C3Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T0I3 => C3Z)  = (0,0);
+
+	if ((B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T1I0 => C3Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T1I1 => C3Z)  = (0,0);
+	if ((T1CIS == 1'b1) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T1I2 => C3Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T1I3 => C3Z)  = (0,0);
+
+	if ((B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T2I0 => C3Z)  = (0,0);
+	if ((B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T2I1 => C3Z)  = (0,0);
+	if ((T2CIS == 1'b1) && (B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T2I2 => C3Z)  = (0,0);
+	if ((B2CIS == 1'b0) && (T3CIS == 1'b0)  && (TB2S == 1'b0))
+		(T2I3 => C3Z)  = (0,0);
+
+	if ((T1CIS == 1'b0) && (TB1S == 1'b0))
+		(B0I0 => C1Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (TB1S == 1'b0))
+		(B0I1 => C1Z)  = (0,0);
+	if ( (B0CIS == 1'b0) && (T1CIS == 1'b0) && (TB1S == 1'b0))
+		(B0I2 => C1Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (TB1S == 1'b0))
+		(B0I3 => C1Z)  = (0,0);
+
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (TB1S == 1'b1))
+		(B0I0 => C1Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (TB1S == 1'b1))
+		(B0I1 => C1Z)  = (0,0);
+	if ((B0CIS == 1'b1) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (TB1S == 1'b1))
+		(B0I2 => C1Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (TB1S == 1'b1))
+		(B0I3 => C1Z)  = (0,0);
+
+
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(B0I0 => C2Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(B0I1 => C2Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(B0I2 => C2Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(B0I3 => C2Z)  = (0,0);
+
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (TB2S == 1'b1))
+		(B0I0 => C2Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (TB2S == 1'b1))
+		(B0I1 => C2Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (TB2S == 1'b1))
+		(B0I2 => C2Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (TB2S == 1'b1))
+		(B0I3 => C2Z)  = (0,0);
+
+
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B0I0 => C3Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B0I1 => C3Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B0I2 => C3Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B0I3 => C3Z)  = (0,0);
+
+
+
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B0I0 => C3Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B0I1 => C3Z)  = (0,0);
+	if ((B0CIS == 1'b0) && (T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B0I2 => C3Z)  = (0,0);
+	if ((T1CIS == 1'b0) && (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B0I3 => C3Z)  = (0,0);
+
+
+	if ((T2CIS == 1'b0) && (TB2S == 1'b0))
+		(B1I0 => C2Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (TB2S == 1'b0))
+		(B1I1 => C2Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T2CIS == 1'b0) && (TB2S == 1'b0))
+		(B1I2 => C2Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (TB2S == 1'b0))
+		(B1I3 => C2Z)  = (0,0);
+
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (TB2S == 1'b1))
+		(B1I0 => C2Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (TB2S == 1'b1))
+		(B1I1 => C2Z)  = (0,0);
+	if ((B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (TB2S == 1'b1))
+		(B1I2 => C2Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (TB2S == 1'b1))
+		(B1I3 => C2Z)  = (0,0);
+
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B1I0 => C3Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B1I1 => C3Z)  = (0,0);
+	if ( (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B1I2 => C3Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B1I3 => C3Z)  = (0,0);
+
+
+
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B1I0 => C3Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B1I1 => C3Z)  = (0,0);
+	if ( (B1CIS == 1'b0) && (T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B1I2 => C3Z)  = (0,0);
+	if ((T2CIS == 1'b0) && (B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B1I3 => C3Z)  = (0,0);
+
+	if ((T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B2I0 => C3Z)  = (0,0);
+	if ((T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B2I1 => C3Z)  = (0,0);
+	if ((B2CIS == 1'b0) && (T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B2I2 => C3Z)  = (0,0);
+	if ((T3CIS == 1'b0) && (TB3S == 1'b0))
+		(B2I3 => C3Z)  = (0,0);
+
+
+	if ((T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B2I0 => C3Z)  = (0,0);
+	if ((T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B2I1 => C3Z)  = (0,0);
+	if ((B2CIS == 1'b0) && (T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B2I2 => C3Z)  = (0,0);
+	if ((T3CIS == 1'b0) && (B3CIS == 1'b0) && (TB3S == 1'b1))
+		(B2I3 => C3Z)  = (0,0);
+
+*/
+
+	(B3I0 => B3CO) = (0,0);
+	(B3I1 => B3CO) = (0,0);
+	(B3I3 => B3CO) = (0,0);
+	(B3I2 => B3CO) = (0,0);
+
+	(T3I0 => T3CO) = (0,0);
+	(T3I1 => T3CO) = (0,0);
+	(T3I3 => T3CO) = (0,0);
+	(T3I2 => T3CO) = (0,0);
+
+/*
+	if (B3CIS == 1'b0)
+		(T3I0 => B3CO) = (0,0);
+	if (B3CIS == 1'b0)
+		(T3I1 => B3CO) = (0,0);
+	if (B3CIS == 1'b0)
+		(T3I3 => B3CO) = (0,0);
+	if ((T3CIS == 1'b1) && (B3CIS == 1'b0))
+		(T3I2 => B3CO) = (0,0);
+
+
+	if ((B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(B2I0 => B3CO) = (0,0);
+	if ((B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(B2I1 => B3CO) = (0,0);
+	if ((B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(B2I3 => B3CO) = (0,0);
+	if ((B2CIS == 1'b1) && (B3CIS == 1'b0) && (T3CIS == 1'b0) )
+		(B2I2 => B3CO) = (0,0);
+
+	if ((B2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(T2I0 => B3CO) = (0,0);
+	if ((B2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(T2I1 => B3CO) = (0,0);
+	if ((B2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(T2I3 => B3CO) = (0,0);
+	if ((T3CIS == 1'b1) && (B2CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0))
+		(T2I2 => B3CO) = (0,0);
+
+	if ((B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(B1I0 => B3CO) = (0,0);
+	if ((B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(B1I1 => B3CO) = (0,0);
+	if ((B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(B1I3 => B3CO) = (0,0);
+	if ((B1CIS == 1'b1) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) )
+		(B1I2 => B3CO) = (0,0);
+
+	if ((B1CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(T1I0 => B3CO) = (0,0);
+	if ((B1CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(T1I1 => B3CO) = (0,0);
+	if ((B1CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(T1I3 => B3CO) = (0,0);
+	if ((T1CIS == 1'b1) && (B3CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0))
+		(T1I2 => B3CO) = (0,0);
+
+
+	if ((B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(B0I0 => B3CO) = (0,0);
+	if ((B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) )
+		(B0I1 => B3CO) = (0,0);
+	if ((B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(B0I3 => B3CO) = (0,0);
+	if ((B0CIS == 1'b1) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0) )
+		(B0I2 => B3CO) = (0,0);
+
+	if ((B0CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0I0 => B3CO) = (0,0);
+	if ((B0CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0I1 => B3CO) = (0,0);
+	if ((B0CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0I3 => B3CO) = (0,0);
+	if ((T0CIS == 1'b1) &&  (B0CIS == 1'b0) && (B3CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0I2 => B3CO) = (0,0);
+
+	if ((T0CIS == 1'b0) &&  (B0CIS == 1'b0) && (B3CIS == 1'b0) && (B3CIS == 1'b0) && (T3CIS == 1'b0) && (B2CIS == 1'b0) && (T2CIS == 1'b0) && (B1CIS == 1'b0) && (T1CIS == 1'b0))
+		(T0CI => B3CO) = (0,0);
+*/
+
+	(B0I0 => B0Z) = (0,0);
+	(B0I1 => B0Z) = (0,0);
+	(B0I3 => B0Z) = (0,0);
+	(B0I2 => B0Z) = (0,0);
+	//if (B0CIS == 1'b1)
+	//	(B0I2 => B0Z) = (0,0);
+
+	if (TB0S == 1'b1)
+		(B0I0 => C0Z) = (0,0);
+	if (TB0S == 1'b1)
+		(B0I1 => C0Z) = (0,0);
+	if (TB0S == 1'b1)
+		(B0I3 => C0Z) = (0,0);
+	//if ((B0CIS == 1'b1) && (TB0S == 1'b1)) 
+	if (TB0S == 1'b1)
+		(B0I2 => C0Z) = (0,0);
+
+	if (TB0S == 1'b0)
+		(T0I0 => C0Z) = (0,0);
+	if (TB0S == 1'b0)
+		(T0I1 => C0Z) = (0,0);
+	if (TB0S == 1'b0)
+		(T0I3 => C0Z) = (0,0);
+	//if ((T0CIS == 1'b1) && (TB0S == 1'b0))
+	if (TB0S == 1'b0)
+		(T0I2 => C0Z) = (0,0);
+
+	(B1I0 => B1Z) = (0,0);
+	(B1I1 => B1Z) = (0,0);
+	(B1I3 => B1Z) = (0,0);
+	(B1I2 => B1Z) = (0,0);
+	//if (B1CIS == 1'b1)
+	//	(B1I2 => B1Z) = (0,0);
+
+	if (TB1S == 1'b1)
+		(B1I0 => C1Z) = (0,0);
+	if (TB1S == 1'b1)
+		(B1I1 => C1Z) = (0,0);
+	if (TB1S == 1'b1)
+		(B1I3 => C1Z) = (0,0);
+	//if ((B1CIS == 1'b1) && (TB1S == 1'b1)) 
+	if (TB1S == 1'b1) 
+		(B1I2 => C1Z) = (0,0);
+
+	if (TB1S == 1'b0)
+		(T1I0 => C1Z) = (0,0);
+	if (TB1S == 1'b0)
+		(T1I1 => C1Z) = (0,0);
+	if (TB1S == 1'b0)
+		(T1I3 => C1Z) = (0,0);
+	if (TB1S == 1'b0)
+		(T1I2 => C1Z) = (0,0);
+
+	(B2I0 => B2Z) = (0,0);
+	(B2I1 => B2Z) = (0,0);
+	(B2I3 => B2Z) = (0,0);
+	(B2I2 => B2Z) = (0,0);
+	//if (B2CIS == 1'b1)
+	//	(B2I2 => B2Z) = (0,0);
+
+	if (TB2S == 1'b1)
+		(B2I0 => C2Z) = (0,0);
+	if (TB2S == 1'b1)
+		(B2I1 => C2Z) = (0,0);
+	if (TB2S == 1'b1)
+		(B2I3 => C2Z) = (0,0);
+	//if ((B2CIS == 1'b1) && (TB2S == 1'b1)) 
+	if (TB2S == 1'b1)
+		(B2I2 => C2Z) = (0,0);
+
+	if (TB2S == 1'b0)
+		(T2I0 => C2Z) = (0,0);
+	if (TB2S == 1'b0)
+		(T2I1 => C2Z) = (0,0);
+	if (TB2S == 1'b0)
+		(T2I3 => C2Z) = (0,0);
+	//if (T2CIS == 1'b1)
+	if (TB2S == 1'b0)
+		(T2I2 => C2Z) = (0,0);
+
+	(B3I0 => B3Z) = (0,0);
+	(B3I1 => B3Z) = (0,0);
+	(B3I3 => B3Z) = (0,0);
+	(B3I2 => B3Z) = (0,0);
+	//if (B3CIS == 1'b1)
+	//	(B3I2 => B3Z) = (0,0);
+
+	if (TB3S == 1'b1)
+		(B3I0 => C3Z) = (0,0);
+	if (TB3S == 1'b1)
+		(B3I1 => C3Z) = (0,0);
+	if (TB3S == 1'b1)
+		(B3I3 => C3Z) = (0,0);
+	//if ((B3CIS == 1'b1) && (TB3S == 1'b1)) 
+	if (TB3S == 1'b1) 
+		(B3I2 => C3Z) = (0,0);
+
+	if (TB3S == 1'b0)
+		(T3I0 => C3Z) = (0,0);
+	if (TB3S == 1'b0)
+		(T3I1 => C3Z) = (0,0);
+	if (TB3S == 1'b0)
+		(T3I3 => C3Z) = (0,0);
+	//if ((T3CIS == 1'b1) && (TB3S == 1'b0))
+	if (TB3S == 1'b0)
+		(T3I2 => C3Z) = (0,0);
+
+
+$removal (posedge QRT,negedge QST, 0);
+$removal (negedge QRT,negedge QST, 0);
+$recovery (posedge QRT,negedge QST, 0);
+$recovery (negedge QRT,negedge QST, 0);
+$setup( posedge Q1EN, negedge QCK, 0);
+$setup( negedge Q1EN, negedge QCK, 0);
+$hold( negedge QCK, posedge Q1EN, 0);
+$hold( negedge QCK, negedge Q1EN, 0);
+$setup( posedge Q2EN, negedge QCK, 0);
+$setup( negedge Q2EN, negedge QCK, 0);
+$hold( negedge QCK, posedge Q2EN, 0);
+$hold( negedge QCK, negedge Q2EN, 0);
+$setup( posedge Q2EN, negedge QCK, 0);
+$setup( negedge Q2EN, negedge QCK, 0);
+$hold( negedge QCK, posedge Q2EN, 0);
+$hold( negedge QCK, negedge Q2EN, 0);
+$setup( posedge Q3EN, negedge QCK, 0);
+$setup( negedge Q3EN, negedge QCK, 0);
+$hold( negedge QCK, posedge Q3EN, 0);
+$hold( negedge QCK, negedge Q3EN, 0);
+endspecify
+
+
+endmodule    
+
+
+`timescale 1ns/10ps
+
+module BIDIR (	
+		ESEL,
+		IE,
+		OSEL,
+		OQI,
+		OQE,	
+		FIXHOLD,
+		IZ,
+		IQZ,
+		IQE,
+		IQC,
+		IQR,
+		IN_EN,
+		IP,
+		CLK_EN,
+		DS_0_,
+		DS_1_,
+		SR,
+		ST,
+		WP_0_,
+		WP_1_
+		);
+				
+input ESEL;
+input IE;
+input OSEL;
+input OQI;
+input OQE;
+input FIXHOLD;
+output IZ;
+output IQZ;
+input IQE;
+input IQC;
+input IN_EN;
+input IQR;
+inout IP;
+
+input	CLK_EN;
+input	DS_0_;
+input	DS_1_;
+input	SR;
+input	ST;
+input	WP_0_;
+input	WP_1_;
+
+reg EN_reg, OQ_reg, IQZ;
+wire rstn, EN, OQ, AND_OUT, IQCP;
+
+wire FIXHOLD_int;	
+wire ESEL_int;
+wire IE_int;
+wire OSEL_int;
+wire OQI_int;
+wire IN_EN_int;
+wire OQE_int;
+wire IQE_int;
+wire IQC_int;
+wire IQR_int;
+
+parameter IOwithOUTDriver = 0;        //  has to be set for IO with out Driver
+
+buf FIXHOLD_buf (FIXHOLD_int,FIXHOLD);	
+buf IN_EN_buf (INEN_int,INEN);
+buf IQC_buf (IQC_int,IQC);
+buf IQR_buf (IQR_int,IQR);
+buf ESEL_buf (ESEL_int,ESEL);
+buf IE_buf (IE_int,IE);
+buf OSEL_buf (OSEL_int,OSEL);
+buf OQI_buf (OQI_int,OQI);
+buf OQE_buf (OQE_int,OQE);
+buf IQE_buf (IQE_int,IQE);
+
+assign rstn = ~IQR_int;
+assign IQCP = IQC_int;
+ if (IOwithOUTDriver)
+ begin
+	assign IZ = IP;
+ end
+ else
+  begin
+	//assign AND_OUT = IN_EN_int ? IP : 1'b0;
+	// Changing IN_EN_int, as its functionality is changed now
+	assign AND_OUT = ~IN_EN ? IP : 1'b0;
+
+	assign IZ = AND_OUT;
+ end
+assign EN = ESEL_int ? IE_int : EN_reg ;
+
+assign OQ = OSEL_int ? OQI_int : OQ_reg ;
+
+assign IP = EN ? OQ : 1'bz;
+
+initial
+	begin		
+		//Power on reset
+		EN_reg	= 1'b0;
+		OQ_reg= 1'b0;
+		IQZ=1'b0;
+	end
+always @(posedge IQCP or negedge rstn)
+	if (~rstn)
+		EN_reg <= 1'b0;
+	else
+		EN_reg <= IE_int;
+
+always @(posedge IQCP or negedge rstn)
+	if (~rstn)
+		OQ_reg <= 1'b0;
+	else
+		if (OQE_int)
+			OQ_reg <= OQI_int;
+			
+			
+always @(posedge IQCP or negedge rstn)		
+	if (~rstn)
+		IQZ <= 1'b0;
+	else
+		if (IQE_int)
+			IQZ <= AND_OUT;
+		
+// orig value
+//wire gpio_c18 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b1 && DS == 1'b1 && IQCS == 1'b1);
+//wire gpio_c16 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b1 && DS == 1'b0 && IQCS == 1'b1);
+//wire gpio_c14 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b0 && DS == 1'b1 && IQCS == 1'b1);
+//wire gpio_c12 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b0 && DS == 1'b0 && IQCS == 1'b1);
+//wire gpio_c10 = (OSEL == 1'b0  && OQE == 1'b1 && IQCS == 1'b1);
+//wire gpio_c8 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b1 && DS == 1'b1 && IQCS == 1'b0);
+//wire gpio_c6 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b1 && DS == 1'b0 && IQCS == 1'b0);
+//wire gpio_c4 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b0 && DS == 1'b1 && IQCS == 1'b0);
+//wire gpio_c2 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b0 && DS == 1'b0 && IQCS == 1'b0);
+//wire gpio_c0 = (OSEL == 1'b0  && OQE == 1'b1 && IQCS == 1'b0);
+//wire gpio_c30 = (IQE == 1'b1  && FIXHOLD == 1'b1 && IN_EN == 1'b1 && IQCS == 1'b1);
+//wire gpio_c28 = (IQE == 1'b1  && FIXHOLD == 1'b0 && IN_EN == 1'b1 && IQCS == 1'b1);
+//wire gpio_c22 = (IQE == 1'b1  && FIXHOLD == 1'b1 && IN_EN == 1'b1 && IQCS == 1'b0);
+//wire gpio_c20 = (IQE == 1'b1  && FIXHOLD == 1'b0 && IN_EN == 1'b1 && IQCS == 1'b0);
+
+// changed one
+wire gpio_c18 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 );
+wire gpio_c16 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 );
+wire gpio_c14 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 );
+wire gpio_c12 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 );
+wire gpio_c10 = (OSEL == 1'b0  && OQE == 1'b1 );
+wire gpio_c8 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c6 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 );
+wire gpio_c4 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c2 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c0 = (OSEL == 1'b0  && OQE == 1'b1);
+wire gpio_c30 = (IQE == 1'b1  && IN_EN == 1'b0);
+wire gpio_c28 = (IQE == 1'b1  && IN_EN == 1'b0);
+wire gpio_c22 = (IQE == 1'b1  && IN_EN == 1'b0);
+wire gpio_c20 = (IQE == 1'b1  && IN_EN == 1'b0);
+specify
+if ( IQE == 1'b1  )
+(IQC => IQZ) = (0,0,0,0,0,0);
+(IQR => IQZ) = (0,0);
+if ( IE == 1'b1 && OQE == 1'b1  )
+(IQC => IZ) = (0,0,0,0,0,0);
+if ( IE == 1'b0 )
+(IP => IZ) = (0,0);
+if ( IE == 1'b0 && IN_EN == 1'b1  )
+(IP => IZ) = (0,0);
+$setup (posedge IE,negedge IQC, 0);
+$setup (negedge IE,negedge IQC, 0);
+$hold (negedge IQC,posedge IE, 0);
+$hold (negedge IQC,negedge IE, 0);
+$setup (posedge IE,posedge IQC, 0);
+$setup (negedge IE,posedge IQC, 0);
+$hold (posedge IQC,posedge IE, 0);
+$hold (posedge IQC,negedge IE, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c18, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c18, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c18, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c18, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c16, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c16, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c16, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c16, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c14, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c14, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c14, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c14, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c12, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c12, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c12, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c12, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c10, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c10, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c10, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c10, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c8, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c8, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c8, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c8, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c6, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c6, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c6, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c6, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c4, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c4, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c4, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c4, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c2, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c2, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c2, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c2, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c0, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c0, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c0, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c0, 0);
+$setup (posedge OQE,negedge IQC, 0);
+$setup (negedge OQE,negedge IQC, 0);
+$hold (negedge IQC,posedge OQE, 0);
+$hold (negedge IQC,negedge OQE, 0);
+$setup (posedge OQE,posedge IQC, 0);
+$setup (negedge OQE,posedge IQC, 0);
+$hold (posedge IQC,posedge OQE, 0);
+$hold (posedge IQC,negedge OQE, 0);
+$setup (posedge IQE,negedge IQC, 0);
+$setup (negedge IQE,negedge IQC, 0);
+$hold (negedge IQC,posedge IQE, 0);
+$hold (negedge IQC,negedge IQE, 0);
+$setup (posedge IQE,posedge IQC, 0);
+$setup (negedge IQE,posedge IQC, 0);
+$hold (posedge IQC,posedge IQE, 0);
+$hold (posedge IQC,negedge IQE, 0);
+$recovery (posedge IQR,negedge IQC, 0);
+$recovery (negedge IQR,negedge IQC, 0);
+$removal (posedge IQR,negedge IQC, 0);
+$removal (negedge IQR,negedge IQC, 0);
+$recovery (posedge IQR,posedge IQC, 0);
+$recovery (negedge IQR,posedge IQC, 0);
+$removal (posedge IQR,posedge IQC, 0);
+$removal (negedge IQR,posedge IQC, 0);
+$setup( posedge IP, negedge IQC &&& gpio_c30, 0);
+$setup( negedge IP, negedge IQC &&& gpio_c30, 0);
+$hold( negedge IQC, posedge IP &&& gpio_c30, 0);
+$hold( negedge IQC, negedge IP &&& gpio_c30, 0);
+$setup( posedge IP, negedge IQC &&& gpio_c28, 0);
+$setup( negedge IP, negedge IQC &&& gpio_c28, 0);
+$hold( negedge IQC, posedge IP &&& gpio_c28, 0);
+$hold( negedge IQC, negedge IP &&& gpio_c28, 0);
+$setup( posedge IP, posedge IQC &&& gpio_c22, 0);
+$setup( negedge IP, posedge IQC &&& gpio_c22, 0);
+$hold( posedge IQC, posedge IP &&& gpio_c22, 0);
+$hold( posedge IQC, negedge IP &&& gpio_c22, 0);
+$setup( posedge IP, posedge IQC &&& gpio_c20, 0);
+$setup( negedge IP, posedge IQC &&& gpio_c20, 0);
+$hold( posedge IQC, posedge IP &&& gpio_c20, 0);
+$hold( posedge IQC, negedge IP &&& gpio_c20, 0);
+(IE => IP) = (0,0,0,0,0,0);
+if ( IE == 1'b1 )
+(OQI => IP) = (0,0);
+(IQC => IP) = (0,0,0,0,0,0);
+if ( IE == 1'b1 && OQE == 1'b1  )
+(IQC => IP) = (0,0,0,0,0,0);
+if ( IE == 1'b0 )
+(IQR => IP) = (0,0);
+endspecify
+endmodule
+
+//pragma synthesis_off
+module sw_mux (
+	port_out,
+	default_port,
+	alt_port,
+	switch
+	);
+	
+	output port_out;
+	input default_port;
+	input alt_port;
+	input switch;
+	
+	assign port_out = switch ? alt_port : default_port;
+	
+endmodule
+//pragma synthesis_on
+
+`timescale 1ns/10ps
+module QMUX (GMUXIN, QHSCK, IS, IZ);
+input GMUXIN, QHSCK, IS;
+output IZ;
+
+wire GMUXIN_int,  QHSCK_int, IS_int;
+buf GMUXIN_buf (GMUXIN_int, GMUXIN) ;
+buf QHSCK_buf (QHSCK_int, QHSCK) ;
+buf IS_buf (IS_int, IS) ;
+
+assign IZ = IS ? QHSCK_int : GMUXIN_int; 
+
+specify
+   (GMUXIN => IZ) = (0,0);
+   (QHSCK => IZ) = (0,0);
+   (IS => IZ) = (0,0);
+endspecify
+
+endmodule 
+
+module QPMUX (QCLKIN, QHSCK, GMUXIN, IS0, IS1, IZ);
+input QCLKIN, QHSCK, GMUXIN, IS0, IS1;
+output IZ;
+
+wire GMUXIN_int, QCLKIN_int, QHSCK_int, IS_int;
+buf GMUXIN_buf (GMUXIN_int, GMUXIN) ;
+buf QHSCK_buf (QHSCK_int, QHSCK) ;
+buf QCLKIN_buf (QCLKIN_int, QCLKIN) ;
+buf IS0_buf (IS0_int, IS0);
+buf IS1_buf (IS1_int, IS1);
+
+//assign IZ = IS0 ? (IS1 ? QHSCK_int : QCLKIN_int) : (IS1 ? QHSCK_int : GMUXIN_int); 
+assign IZ = IS0_int ? (IS1_int ? QHSCK_int : GMUXIN_int) : (IS1_int ? QHSCK_int : QCLKIN_int); 
+
+specify
+   (QCLKIN => IZ) = (0,0);
+   (QHSCK => IZ) = (0,0);
+   (GMUXIN => IZ) = (0,0);
+   (IS0 => IZ) = (0,0);
+   (IS1 => IZ) = (0,0);
+endspecify
+
+endmodule 
+
+module GMUX(GCLKIN, GHSCK, SSEL, BL_DEN, BL_DYNEN, BL_SEN, BL_VLP, BR_DEN, 
+            BR_DYNEN, BR_SEN, 
+            BR_VLP, TL_DEN, TL_DYNEN, TL_SEN, TL_VLP, TR_DEN, TR_DYNEN, TR_SEN, TR_VLP, IZ);
+input GCLKIN, GHSCK, SSEL, BL_DYNEN, BL_VLP, BR_DEN, BR_DYNEN, BR_SEN, BL_DEN, BL_SEN, 
+		 BR_VLP, TL_DEN, TL_DYNEN, TL_SEN, TL_VLP, TR_DEN, TR_DYNEN, TR_SEN, TR_VLP; 
+output IZ; 
+wire GCLKIN_int, GHSCK_int, SSEL_int;
+wire wire_mux_op_0;
+
+
+buf GCLKIN_buf (GCLKIN_int, GCLKIN) ;
+buf GHSCK_buf (GHSCK_int, GHSCK) ;
+buf SSEL_buf (SSEL_int, SSEL) ;
+//buf SEN_buf (SEN_int, SEN) ;
+//buf DYNEN_buf (DYNEN_int, DYNEN) ;
+//buf DEN_buf (DEN_int, DEN) ;
+//buf VLP_buf (VLP_int, VLP) ;
+
+assign wire_mux_op_0 = SSEL_int ? GHSCK_int : GCLKIN_int;
+//assign wire_mux_op_1 = SEN_int ? 1'b1 : 1'b0;
+//assign wire_mux_op_2 = DEN_int ? DYNEN_int : wire_mux_op_1;
+//assign wire_mux_op_3 = VLP_int ? 1'b0 : wire_mux_op_2;
+
+assign IZ  = wire_mux_op_0;
+
+specify
+   (GCLKIN => IZ) = (0,0);
+   (GHSCK => IZ) = (0,0);
+   (BL_DEN => IZ) = (0,0);
+   (BL_DYNEN => IZ) = (0,0);
+	(BL_SEN => IZ) = (0,0);   
+	(BL_VLP => IZ) = (0,0); 
+	(BR_DEN => IZ) = (0,0);
+	(BR_SEN => IZ) = (0,0); 
+	(BL_DEN => IZ) = (0,0); 
+	(BL_SEN => IZ) = (0,0); 
+	(BL_VLP => IZ) = (0,0); 
+	(BR_DEN => IZ) = (0,0); 
+	(BR_SEN => IZ) = (0,0);
+    (BR_VLP => IZ) = (0,0); 
+	(TL_DEN => IZ) = (0,0); 
+	(TL_SEN => IZ) = (0,0); 
+	(TL_VLP => IZ) = (0,0); 
+	(TR_DEN => IZ) = (0,0); 
+	(TR_SEN => IZ) = (0,0); 
+	(TR_VLP => IZ) = (0,0);
+	(BL_DYNEN => IZ) = (0,0); 
+    (BR_DYNEN => IZ) = (0,0); 
+	(TR_DYNEN => IZ) = (0,0); 
+	(TL_DYNEN => IZ) = (0,0); 
+endspecify
+
+endmodule 
+
+module SQMUX(QMUXIN, SQHSCK, SELECT, IZ);
+input QMUXIN, SQHSCK,SELECT;
+output IZ;
+
+wire QMUXIN_int, SQHSCK_int, SELECT_int;
+
+buf QMUXIN_buf (QMUXIN_int, QMUXIN) ;
+buf SQHSCK_buf (SQHSCK_int, SQHSCK) ;
+buf SELECT_buf (SELECT_int, SELECT) ;
+
+assign IZ = SELECT_int ?  SQHSCK_int : QMUXIN_int;
+specify
+   (QMUXIN => IZ) = (0,0);
+   (SQHSCK => IZ) = (0,0);
+   (SELECT => IZ) = (0,0);
+endspecify
+
+endmodule
+
+
+`timescale 1ns/10ps
+module SQEMUX(QMUXIN, SQHSCK, DYNEN, SEN, DEN, SELECT, IZ);
+input QMUXIN, SQHSCK, DYNEN, SEN, DEN, SELECT;
+output IZ;
+
+wire QMUXIN_int, SQHSCK_int, DYNEN_int, SEN_int, DEN_int, SELECT_int;
+buf QMUXIN_buf (QMUXIN_int, QMUXIN) ;
+buf SQHSCK_buf (SQHSCK_int, SQHSCK) ;
+buf DYNEN_buf (DYNEN_int, DYNEN) ;
+buf SEN_buf (SEN_int, SEN) ;
+buf DEN_buf (DEN_int, DEN) ;
+buf SELECT_buf (SELECT_int, SELECT) ;
+
+
+assign IZ = SELECT_int ?  SQHSCK_int : QMUXIN_int;
+	
+specify
+   (QMUXIN => IZ) = (0,0);
+   (SQHSCK => IZ) = (0,0);
+   (DYNEN => IZ) = (0,0);
+   (SEN => IZ) = (0,0);
+   (DEN => IZ) = (0,0);
+   (SELECT => IZ) = (0,0);
+endspecify
+endmodule
+
+
+
+`timescale 1ns/10ps
+module CAND(SEN, CLKIN, IZ);
+input SEN, CLKIN;
+output IZ;
+wire SEN_int, CLKIN_int;
+buf SEN_buf (SEN_int, SEN) ;
+buf CLKIN_buf (CLKIN_int, CLKIN) ;
+assign IZ = CLKIN_int & SEN_int; 
+
+specify
+   (CLKIN => IZ) = (0,0);
+   (SEN => IZ) = (0,0);
+endspecify
+endmodule 
+
+module CANDEN(CLKIN, DYNEN, SEN, DEN, IZ);
+input CLKIN, DYNEN, SEN, DEN;
+output IZ;
+wire CLKIN_int, DYNEN_int, SEN_int, DEN_int; 
+wire mux_op0, mux_op1;
+
+buf SEN_buf (SEN_int, SEN) ;
+buf CLKIN_buf (CLKIN_int, CLKIN) ;
+buf DYNEN_buf (DYNEN_int, DYNEN) ;
+buf DEN_buf (DEN_int, DEN) ;
+
+assign mux_op0 = SEN_int ? 1'b1 : 1'b0;
+assign mux_op1 = DEN_int ? DYNEN_int : mux_op0;
+
+assign IZ = CLKIN_int & SEN_int; 
+
+specify
+   (CLKIN => IZ) = (0,0);
+   (DYNEN => IZ) = (0,0);
+   (SEN => IZ) = (0,0);
+   (DEN => IZ) = (0,0);
+endspecify
+
+endmodule
+
+`timescale 1ns/10ps
+module CLOCK(IP, CEN, IC, OP);
+input IP, CEN;
+output IC, OP;
+buf IP_buf (IP_int, IP) ;
+buf CEN_buf (CEN_int, CEN) ;
+
+buf (IC, IP_int);
+
+specify
+   (IP => IC) = (0,0);
+endspecify
+
+
+endmodule
+
+// P_MUX3 cell -----------------------------------------------------------------
+//
+
+module P_MUX3( A, B, C, D, S, T, E, Z );
+input A, B, C, D, S, E, T;
+output Z;
+
+udpmux3 QL2 ( Z, A, B, C, D, E, S, T );
+
+specify
+   (A => Z) = 0;
+   (B => Z) = 0;
+   (C => Z) = 0;
+   (D => Z) = 0;
+   (E => Z) = 0;
+   (S => Z) = 0;
+   (T => Z) = 0;
+endspecify
+
+endmodule
+
+primitive udpmux3(Z, A, B, C, D, E, S, T);
+   output Z;
+   input A, B, C, D, E, S, T;
+   table
+   // A  B  C  D  E     S  T   :    Z
+      1  ?  ?  ?  ?     0  0   :    1  ;
+      0  ?  ?  ?  ?     0  0   :    0  ;
+      ?  0  ?  ?  ?     0  1   :    0  ;
+      ?  1  ?  ?  ?     0  1   :    1  ;
+      ?  ?  0  ?  ?     1  0   :    0  ;
+      ?  ?  1  ?  ?     1  0   :    1  ;
+      ?  ?  ?  0  ?     1  1   :    0  ;
+      ?  ?  ?  1  ?     1  1   :    1  ;
+   endtable
+endprimitive // udpmux3
+
+// P_MUX2 cell -----------------------------------------------------------------
+
+
+module P_MUX2( A, B, C, D, S, Z);
+input A, B, C, D, S;
+output Z;
+
+udpmux2 QL1 ( Z, A, B, C, D, S );
+
+specify
+   (A => Z) = 0;
+   (B => Z) = 0;
+   (C => Z) = 0;
+   (D => Z) = 0;
+   (S => Z) = 0;
+endspecify
+
+endmodule // P_MUX2
+
+// P_BUF cell -----------------------------------------------------------------
+
+module P_BUF( A, Z);
+input A;
+output Z;
+
+buf QL1 (Z, A);
+
+specify
+   (A => Z) = 0;
+endspecify
+
+endmodule
+
+primitive udpmux2(Z, A, B, C, D, S);
+   output Z;
+   input A, B, C, D, S;
+   table
+      // A  B  C  D  S   :    Z
+         1  0  ?  ?  0   :    1  ;
+         0  ?  ?  ?  0   :    0  ;
+         ?  1  ?  ?  0   :    0  ;
+         ?  ?  1  0  1   :    1  ;
+         ?  ?  0  ?  1   :    0  ;
+         ?  ?  ?  1  1   :    0  ;
+// Reduce pessimism
+         1  0  1  0  ?   :    1  ;
+         0  ?  0  ?  ?   :    0  ;
+         0  ?  ?  1  ?   :    0  ; // new
+         ?  1  ?  1  ?   :    0  ;
+         ?  1  0  ?  ?   :    0  ; // new
+   endtable
+endprimitive // udpmux2
+
+primitive udpand6(Z, A, B, C, D, E, F);
+   output Z;
+   input A, B, C, D, E, F;
+   table
+      // A  B  C  D  E  F  :  Z
+         1  0  1  0  1  0  :  1  ;
+         0  ?  ?  ?  ?  ?  :  0  ;
+         ?  1  ?  ?  ?  ?  :  0  ;
+         ?  ?  0  ?  ?  ?  :  0  ;
+         ?  ?  ?  1  ?  ?  :  0  ;
+         ?  ?  ?  ?  0  ?  :  0  ;
+         ?  ?  ?  ?  ?  1  :  0  ;
+   endtable
+endprimitive // udpand6
+
+module P_AND6( A, B, C, D, E, F, Z );
+input A, B, C, D, E, F;
+output Z;
+
+udpand6 QL1 ( Z, A, B, C, D, E, F );
+
+specify
+   (A => Z) = 0;
+   (B => Z) = 0;
+   (C => Z) = 0;
+   (D => Z) = 0;
+   (E => Z) = 0;
+   (F => Z) = 0;
+endspecify
+
+endmodule // P_AND6
+
+`timescale 1ns/10ps
+module SDIOMUX (SD_IP, SD_IZ, SD_OQI, SD_OE);
+
+input  SD_OE, SD_OQI;
+output SD_IZ;
+inout SD_IP;
+
+assign SD_IP = SD_OE ? SD_OQI : 1'bz;
+assign SD_IZ = ~SD_OE ? SD_IP : 1'bz;
+
+specify
+
+if ( SD_OE == 1'b0 ) (SD_IP => SD_IZ) = (0,0);
+if ( SD_OE == 1'b1 ) (SD_OQI => SD_IP) = (0,0);
+
+(SD_IP => SD_IZ) = (0,0,0,0,0,0);
+(SD_OE => SD_IP) = (0,0,0,0,0,0);
+
+endspecify
+
+endmodule
+
+`timescale 1ns/10ps
+module OBUF( IN_OBUF, OUT_OBUF);
+input IN_OBUF;
+output OUT_OBUF;
+
+buf QL1 (OUT_OBUF, IN_OBUF);
+
+specify
+   (IN_OBUF => OUT_OBUF) = 0;
+endspecify
+
+endmodule
+
+`timescale 1ns/10ps
+module IBUF(IN_IBUF, OUT_IBUF);
+input IN_IBUF;
+output OUT_IBUF;
+
+buf QL1 (OUT_IBUF, IN_IBUF);
+
+specify
+   (IN_IBUF => OUT_IBUF) = 0;
+endspecify
+
+endmodule
+
+`timescale 1ns/10ps
+module IO_REG (	
+		ESEL,
+		IE,
+		OSEL,
+		OQI,
+		OQE,	
+		FIXHOLD,
+		IZ,
+		IQZ,
+		IQE,
+		IQC,
+		IQR,
+		INEN,
+                A2F_reg, 
+                F2A_reg_0_, 
+                F2A_reg_1_
+		);
+				
+input ESEL;
+input IE;
+input OSEL;
+input OQI;
+input OQE;
+input FIXHOLD;
+output IZ;
+output IQZ;
+input IQE;
+input IQC;
+input INEN;
+input IQR;
+input A2F_reg;
+output F2A_reg_0_;
+output F2A_reg_1_;
+//inout IP;
+
+reg EN_reg, OQ_reg, IQZ;
+wire rstn, EN, OQ, AND_OUT;
+
+wire FIXHOLD_int;	
+wire ESEL_int;
+wire IE_int;
+wire OSEL_int;
+wire OQI_int;
+wire INEN_int;
+wire OQE_int;
+wire IQE_int;
+wire IQC_int;
+wire IQR_int;
+wire A2F_reg_int;
+
+parameter IOwithOUTDriver = 0;        //  has to be set for IO with out Driver
+
+buf FIXHOLD_buf (FIXHOLD_int,FIXHOLD);	
+buf INEN_buf (INEN_int,INEN);
+buf IQC_buf (IQC_int,IQC);
+buf IQR_buf (IQR_int,IQR);
+buf ESEL_buf (ESEL_int,ESEL);
+buf IE_buf (IE_int,IE);
+buf OSEL_buf (OSEL_int,OSEL);
+buf OQI_buf (OQI_int,OQI);
+buf OQE_buf (OQE_int,OQE);
+buf IQE_buf (IQE_int,IQE);
+buf A2F_reg_buf (A2F_reg_int, A2F_reg);
+
+assign rstn = ~IQR_int;
+ if (IOwithOUTDriver)
+ begin
+	//assign AND_OUT = IQIN_int;
+
+	//assign IZ = IP;
+	assign IZ = A2F_reg_int;
+ end
+ else
+  begin
+	//assign AND_OUT = INEN_int ? IP : 1'b0;
+	// Changing INEN_int, as its functionality is changed now
+	//assign AND_OUT = ~INEN_int ? IP : 1'b0;
+	assign AND_OUT = ~INEN_int ? A2F_reg_int : 1'b0;
+
+	assign IZ = AND_OUT;
+ end
+assign EN = ESEL_int ? IE_int : EN_reg ;
+
+assign OQ = OSEL_int ? OQI_int : OQ_reg ;
+
+assign F2A_reg_0_ = EN; 
+assign F2A_reg_1_ = OQ; 
+//output F2A_reg_0_;
+//output F2A_reg_1_;
+//assign IP = EN ? OQ : 1'bz;
+
+//assign (highz1,pull0) IP = WPD ? 1'b0 : 1'b1;
+initial
+	begin		
+		//Power on reset
+		EN_reg	= 1'b0;
+		OQ_reg= 1'b0;
+		IQZ=1'b0;
+	end
+always @(posedge IQC_int or negedge rstn)
+	if (~rstn)
+		EN_reg <= 1'b0;
+	else
+		EN_reg <= IE_int;
+
+always @(posedge IQC_int or negedge rstn)
+	if (~rstn)
+		OQ_reg <= 1'b0;
+	else
+		if (OQE_int)
+			OQ_reg <= OQI_int;
+			
+			
+always @(posedge IQC_int or negedge rstn)		
+	if (~rstn)
+		IQZ <= 1'b0;
+	else
+		if (IQE_int)
+			IQZ <= AND_OUT;
+		
+// orig value
+//wire gpio_c18 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b1 && DS == 1'b1 && IQCS == 1'b1);
+//wire gpio_c16 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b1 && DS == 1'b0 && IQCS == 1'b1);
+//wire gpio_c14 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b0 && DS == 1'b1 && IQCS == 1'b1);
+//wire gpio_c12 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b0 && DS == 1'b0 && IQCS == 1'b1);
+//wire gpio_c10 = (OSEL == 1'b0  && OQE == 1'b1 && IQCS == 1'b1);
+//wire gpio_c8 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b1 && DS == 1'b1 && IQCS == 1'b0);
+//wire gpio_c6 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b1 && DS == 1'b0 && IQCS == 1'b0);
+//wire gpio_c4 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b0 && DS == 1'b1 && IQCS == 1'b0);
+//wire gpio_c2 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1 && FIXHOLD == 1'b0 && DS == 1'b0 && IQCS == 1'b0);
+//wire gpio_c0 = (OSEL == 1'b0  && OQE == 1'b1 && IQCS == 1'b0);
+//wire gpio_c30 = (IQE == 1'b1  && FIXHOLD == 1'b1 && INEN == 1'b1 && IQCS == 1'b1);
+//wire gpio_c28 = (IQE == 1'b1  && FIXHOLD == 1'b0 && INEN == 1'b1 && IQCS == 1'b1);
+//wire gpio_c22 = (IQE == 1'b1  && FIXHOLD == 1'b1 && INEN == 1'b1 && IQCS == 1'b0);
+//wire gpio_c20 = (IQE == 1'b1  && FIXHOLD == 1'b0 && INEN == 1'b1 && IQCS == 1'b0);
+
+// changed one
+wire gpio_c18 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c16 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c14 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c12 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c10 = (OSEL == 1'b0  && OQE == 1'b1);
+wire gpio_c8 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c6 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c4 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c2 = (OSEL == 1'b1  && IE == 1'b1 && IQE == 1'b1);
+wire gpio_c0 = (OSEL == 1'b0  && OQE == 1'b1);
+wire gpio_c30 = (IQE == 1'b1  && INEN == 1'b0);
+wire gpio_c28 = (IQE == 1'b1  && INEN == 1'b0);
+wire gpio_c22 = (IQE == 1'b1  && INEN == 1'b0);
+wire gpio_c20 = (IQE == 1'b1  && INEN == 1'b0);
+specify
+if ( IQE == 1'b1  )
+(IQC => IQZ) = (0,0,0,0,0,0);
+(IQR => IQZ) = (0,0);
+if ( IE == 1'b1 && OQE == 1'b1  )
+(IQC => IZ) = (0,0,0,0,0,0);
+if ( IE == 1'b0 )
+(A2F_reg => IZ) = (0,0);
+if ( IE == 1'b0 && INEN == 1'b1  )
+(A2F_reg => IZ) = (0,0);
+$setup (posedge IE,negedge IQC, 0);
+$setup (negedge IE,negedge IQC, 0);
+$hold (negedge IQC,posedge IE, 0);
+$hold (negedge IQC,negedge IE, 0);
+$setup (posedge IE,posedge IQC, 0);
+$setup (negedge IE,posedge IQC, 0);
+$hold (posedge IQC,posedge IE, 0);
+$hold (posedge IQC,negedge IE, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c18, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c18, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c18, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c18, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c16, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c16, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c16, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c16, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c14, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c14, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c14, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c14, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c12, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c12, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c12, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c12, 0);
+$setup( posedge OQI, negedge IQC &&& gpio_c10, 0);
+$setup( negedge OQI, negedge IQC &&& gpio_c10, 0);
+$hold( negedge IQC, posedge OQI &&& gpio_c10, 0);
+$hold( negedge IQC, negedge OQI &&& gpio_c10, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c8, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c8, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c8, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c8, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c6, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c6, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c6, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c6, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c4, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c4, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c4, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c4, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c2, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c2, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c2, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c2, 0);
+$setup( posedge OQI, posedge IQC &&& gpio_c0, 0);
+$setup( negedge OQI, posedge IQC &&& gpio_c0, 0);
+$hold( posedge IQC, posedge OQI &&& gpio_c0, 0);
+$hold( posedge IQC, negedge OQI &&& gpio_c0, 0);
+$setup (posedge OQE,negedge IQC, 0);
+$setup (negedge OQE,negedge IQC, 0);
+$hold (negedge IQC,posedge OQE, 0);
+$hold (negedge IQC,negedge OQE, 0);
+$setup (posedge OQE,posedge IQC, 0);
+$setup (negedge OQE,posedge IQC, 0);
+$hold (posedge IQC,posedge OQE, 0);
+$hold (posedge IQC,negedge OQE, 0);
+$setup (posedge IQE,negedge IQC, 0);
+$setup (negedge IQE,negedge IQC, 0);
+$hold (negedge IQC,posedge IQE, 0);
+$hold (negedge IQC,negedge IQE, 0);
+$setup (posedge IQE,posedge IQC, 0);
+$setup (negedge IQE,posedge IQC, 0);
+$hold (posedge IQC,posedge IQE, 0);
+$hold (posedge IQC,negedge IQE, 0);
+$recovery (posedge IQR,negedge IQC, 0);
+$recovery (negedge IQR,negedge IQC, 0);
+$removal (posedge IQR,negedge IQC, 0);
+$removal (negedge IQR,negedge IQC, 0);
+$recovery (posedge IQR,posedge IQC, 0);
+$recovery (negedge IQR,posedge IQC, 0);
+$removal (posedge IQR,posedge IQC, 0);
+$removal (negedge IQR,posedge IQC, 0);
+$setup( posedge A2F_reg, negedge IQC &&& gpio_c30, 0);
+$setup( negedge A2F_reg, negedge IQC &&& gpio_c30, 0);
+$hold( negedge IQC, posedge A2F_reg &&& gpio_c30, 0);
+$hold( negedge IQC, negedge A2F_reg &&& gpio_c30, 0);
+$setup( posedge A2F_reg, negedge IQC &&& gpio_c28, 0);
+$setup( negedge A2F_reg, negedge IQC &&& gpio_c28, 0);
+$hold( negedge IQC, posedge A2F_reg &&& gpio_c28, 0);
+$hold( negedge IQC, negedge A2F_reg &&& gpio_c28, 0);
+$setup( posedge A2F_reg, posedge IQC &&& gpio_c22, 0);
+$setup( negedge A2F_reg, posedge IQC &&& gpio_c22, 0);
+$hold( posedge IQC, posedge A2F_reg &&& gpio_c22, 0);
+$hold( posedge IQC, negedge A2F_reg &&& gpio_c22, 0);
+$setup( posedge A2F_reg, posedge IQC &&& gpio_c20, 0);
+$setup( negedge A2F_reg, posedge IQC &&& gpio_c20, 0);
+$hold( posedge IQC, posedge A2F_reg &&& gpio_c20, 0);
+$hold( posedge IQC, negedge A2F_reg &&& gpio_c20, 0);
+(IE => F2A_reg_0_) = (0,0,0,0,0,0);
+if ( IE == 1'b1 )
+(IQC => F2A_reg_0_) = (0,0,0,0,0,0);
+if ( IE == 1'b1 && OQE == 1'b1  )
+(OQI => F2A_reg_1_) = (0,0);
+(IQC => F2A_reg_1_) = (0,0,0,0,0,0);
+if ( IE == 1'b0 )
+(IQR => F2A_reg_0_) = (0,0);
+(IQR => F2A_reg_1_) = (0,0);
+endspecify
+endmodule
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/clock_buffer_ql.v b/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/clock_buffer_ql.v
new file mode 100644
index 0000000..6a493b8
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/clock_buffer_ql.v
@@ -0,0 +1,17 @@
+
+`timescale 1ns / 1ns
+
+module clock_buffer (
+	input	A,
+	output	Z
+);
+
+
+
+GCLKBUFF gclkbuff_0 (.A(A), .Z(Z));
+//pragma attribute gclkbuff_0 ql_pack 1
+//pragma attribute gclkbuff_0 hierarchy preserve
+
+endmodule
+
+
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/dff_pre_clr_ql.v b/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/dff_pre_clr_ql.v
new file mode 100644
index 0000000..8780f42
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/hard_macros_ql/dff_pre_clr_ql.v
@@ -0,0 +1,18 @@
+
+`timescale 1ns / 1ns
+
+
+module dff_pre_clr (
+	input	CLK,
+	input	CLR,
+	input	D,
+	input	PRE,
+	output	Q
+);
+
+dffpc dffpc_0 ( .CLK(CLK) , .CLR(CLR), .D(D), .PRE(PRE), .Q(Q) )/* synthesis black_box */;
+//pragma attribute dffpc_0 dont_touch true
+
+endmodule
+
+
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/ring_osc_adjust.v b/BENCHMARK/ULPSH_fabric/rtl/src/ring_osc_adjust.v
new file mode 100644
index 0000000..e1b4fba
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/ring_osc_adjust.v
@@ -0,0 +1,301 @@
+
+/* ------------------------------------------------------------------
+ring_osc_adjust.v
+
+Control logic to keep the ring oscillator's frequency within the
+desired range.
+
+	divider values from ClockDivider_rev2.pdf:
+
+		SEL		sysclk_x2	sysclk
+		--------------------------------
+		000		?			?
+		001		2			4
+		010		3			6
+		011		4			8
+		100		5			10
+		101		6			12
+		110		7			14
+		111		8			16
+
+------------------------------------------------------------------ */
+
+`timescale 1ps/1ps
+
+/*
+module ring_osc_adjust (
+	input			reset_i,				// async reset
+	input			clk_ringosc_i,		// the ring oscillator output divided by 2 (this is not clk_main)
+	input			clk_32khz_i,			// 32.768KHz reference clock
+	input			enable_i,				// enable, can be tied off externally or driven occasionally to force re-calibration
+	output	[2:0]	div_sel_o				// divider selection control for the ring oscillator divider circuit (in ASSP)
+);
+
+reg				clk32k_r1, clk32k_r2;
+reg				clk32k_cycle_start;
+reg				enable_32k_sync, enable_32k_sync_r1;
+reg				enable_main_sync, enable_main_sync_r1, enable_main;
+reg		[10:0]	clk_ringosc_div2_cnt;
+reg		[2:0]	ring_osc_div, ring_osc_div_reg;
+
+// divider SEL values
+localparam	[2:0]	DIV2_SEL = 3'b001;
+localparam	[2:0]	DIV3_SEL = 3'b010;
+localparam	[2:0]	DIV4_SEL = 3'b011;
+localparam	[2:0]	DIV5_SEL = 3'b100;
+localparam	[2:0]	DIV6_SEL = 3'b101;
+localparam	[2:0]	DIV7_SEL = 3'b110;
+localparam	[2:0]	DIV8_SEL = 3'b111;
+
+// threshold values for each divider value.
+//		These are the count values where each divider value will be applied.
+//		Example: if there are 395 counts on clk_ringosc_div2 within a 32KHz clock period, the ring osc is divided by 5.
+//					A divider of 5 means that sysclk_x2 = ring_osc/5, and sysclk = ring_osc/10.
+//		Nomenclature:
+//			ring_osc		= ring oscillator raw clock (not accessible outside of ASSP)
+//			ring_osc_div2	= ring oscillator divided by 2 (used for calibration)
+//			sysclk_x2		= ring oscillator divided by SEL
+//			sysclk			= ring oscillator divided by SEL*2 (used as system clock A.K.A. FFE clock)
+//		Assumptions:
+//			Ring osc range: 25.2MHz - 53.2MHz (39.7ns to 18.8ns period)
+//			I2C master will divide clk_main by 9 to produce SCL.
+//			SCL freq cannot exceed 400KHz.
+//			Guardband of 10% is added to allow for temperature/voltage variation, in case calibration is only done once at startup.
+//				A smaller guardband can be used if calibration is performed periodically.
+localparam	[10:0]	DIV4_THRESHOLD = 11'd32;	// (the threshold of 32 is arbitrary... just needs to be somewhat larger than 0)
+localparam	[10:0]	DIV5_THRESHOLD = 11'd395;
+localparam	[10:0]	DIV6_THRESHOLD = 11'd494;
+localparam	[10:0]	DIV7_THRESHOLD = 11'd595;
+localparam	[10:0]	DIV8_THRESHOLD = 11'd693;
+
+
+// synchronize the enable to clk32k (set this FF on the rising edge of enable_i,
+//		clear it after one full 32KHz period has elapsed)
+always @(posedge enable_i or posedge clk_32khz_i)
+	if (enable_i)
+		enable_32k_sync <= 1'b1;
+	else
+		if (enable_32k_sync_r1)
+			enable_32k_sync <= 1'b0;
+		else
+			enable_32k_sync <= enable_32k_sync;
+
+always @(posedge clk_32khz_i)
+	enable_32k_sync_r1 <= enable_32k_sync;
+
+assign enable_32k = enable_32k_sync_r1;
+
+
+// detect rising edge on clk32khz
+always @(posedge clk_ringosc_i) begin
+	if (!enable_i) begin
+		clk32k_r1 <= 1'b0;
+		clk32k_r2 <= 1'b0;
+		clk32k_cycle_start <= 1'b0;
+	end
+	else begin
+		clk32k_r1 <= clk_32khz_i;
+		clk32k_r2 <= clk32k_r1;
+		clk32k_cycle_start <= clk32k_r1 && !clk32k_r2;
+	end
+end
+
+
+// synchronize the stretched enable to the main clk domain,
+//		turn this enable off when clk32k_cycle_start is active
+always @(posedge clk_ringosc_i or posedge reset_i) begin
+	if (reset_i) begin
+		enable_main_sync <= 1'b0;
+		enable_main_sync_r1 <= 1'b0;
+		enable_main <= 1'b0;
+	end
+	else begin
+		enable_main_sync <= enable_32k;
+		enable_main_sync_r1 <= enable_main_sync;
+		case (enable_main)
+			1'b0:	if (clk32k_cycle_start && enable_main_sync_r1)
+						enable_main <= 1'b1;
+					else
+						enable_main <= 1'b0;
+			1'b1:	if (clk32k_cycle_start && !enable_32k)
+						enable_main <= 1'b0;
+					else
+						enable_main <= 1'b1;
+		endcase
+	end
+end
+
+
+// count # of clk_ringosc_div2 cycles per 32khz clock period
+always @(posedge clk_ringosc_i or posedge reset_i)
+	if (reset_i)
+		clk_ringosc_div2_cnt <= 0;
+	else
+		if (enable_main)
+			if (clk32k_cycle_start)
+				clk_ringosc_div2_cnt <= 0;
+			else
+				clk_ringosc_div2_cnt <= clk_ringosc_div2_cnt + 1;
+		else
+			clk_ringosc_div2_cnt <= 0;
+
+
+// set the ring_osc clock divider value
+//		_div holds the temporary divider SEL valud
+//		_div_reg gets assigned after a full 32KHz clock period
+always @(posedge clk_ringosc_i or posedge reset_i)
+	if (reset_i) begin
+		ring_osc_div <= 3'b111;		// use the largest divide value by default
+		ring_osc_div_reg <= 3'b111;
+	end
+	else begin
+		if (enable_main)
+			case (clk_ringosc_div2_cnt)
+				DIV4_THRESHOLD:		ring_osc_div <= DIV4_SEL;
+				DIV5_THRESHOLD:		ring_osc_div <= DIV5_SEL;
+				DIV6_THRESHOLD:		ring_osc_div <= DIV6_SEL;
+				DIV7_THRESHOLD:		ring_osc_div <= DIV7_SEL;
+				DIV8_THRESHOLD:		ring_osc_div <= DIV8_SEL;
+				default:	ring_osc_div <= ring_osc_div;	// hold for all other values
+			endcase
+		else
+			ring_osc_div <= ring_osc_div;	// need to retain the old value when enable is off
+
+		if (clk32k_cycle_start)
+			ring_osc_div_reg <= ring_osc_div;
+		else
+			ring_osc_div_reg <= ring_osc_div_reg;
+	end
+
+assign div_sel_o = ring_osc_div_reg;
+
+
+//// New Logic to produce CNT to system
+//// Detect transition of Calibration aneble from Low to Hi
+always @(posedge clk_32khz_i or posedge reset_i)
+begin
+	if (reset_i) begin
+		enable_r1 <= 1'b0;
+		enable_r2 <= 1'b0;
+		enable_r3 <= 1'b0;
+	end
+	else begin
+		enable_r1 <= enable_i;
+		enable_r2 <= enable_r1;
+		enable_r3 <= enable_r2;
+	end
+end
+
+// Generating enable for Clock Cnt circuit
+// Default is is 2 32KHz CLK period
+always @(posedge clk_32khz_i or posedge reset_i)
+begin
+	if (reset_i)
+		downCnt <= 2'b0;
+	else
+		if (enable_r2 && !enable_r3)
+			downCnt <= 2'b11;
+		else if (downCnt[1] || downCnt[0])
+			downCnt <= downCnt - 1'b1;
+		else
+			downCnt <= downCnt;
+end
+
+// Sync to ring osc clk
+always @(posedge clk_ringosc_i or posedge reset_i)
+	if (reset_i)
+		downCnt1_r1 <= 1'b0;
+		downCnt1_r2 <= 1'b0;
+	else
+		downCnt1_r1 <= downCnt[1];
+		downCnt1_r2 <= downCnt1_r1;
+
+assign ringosccnt_reset = reset_i && !enable_i;
+// Counting # of ringosc cyces in two 32KHz clock
+always @(posedge clk_ringosc_i or posedge ringosccnt_reset)
+begin
+	if (ringosccnt_reset)
+		ringosc_2_cnt <= 16'b0;
+	else if (downCnt1_r2)
+		ringosc_2_cnt <= ringosc_2_cnt + 1'b0;
+	else
+		ringosc_2_cnt <= ringosc_2_cnt;
+end
+
+
+endmodule
+*/
+
+module ring_osc_adjust (
+	input			reset_i,				// async reset
+	input			clk_ringosc_i,		// the ring oscillator output divided by 2 (this is not clk_main)
+	input			clk_32khz_i,			// 32.768KHz reference clock
+	input			enable_i,				// enable, can be tied off externally or driven occasionally to force re-calibration
+	output	[15:0]	cal_val_o				// divider selection control for the ring oscillator divider circuit (in ASSP)
+);
+
+reg			enable_r1, enable_r2, enable_r3;
+reg	[2:0]	downCnt;
+reg			downCnt1_r1, downCnt1_r2;
+reg	[15:0]	ringosc_2_cnt;
+wire		ringosccnt_reset;
+
+//// New Logic to produce CNT to system
+//// Detect transition of Calibration aneble from Low to Hi
+always @(posedge clk_32khz_i or posedge reset_i)
+begin
+	if (reset_i) begin
+		enable_r1 <= 1'b0;
+		enable_r2 <= 1'b0;
+		enable_r3 <= 1'b0;
+	end
+	else begin
+		enable_r1 <= enable_i;
+		enable_r2 <= enable_r1;
+		enable_r3 <= enable_r2;
+	end
+end
+
+// Generating enable for Clock Cnt circuit
+// Default is is 2 32KHz CLK period
+always @(posedge clk_32khz_i or posedge reset_i)
+begin
+	if (reset_i)
+		downCnt <= 3'b0;
+	else
+		if (enable_r2 && !enable_r3)
+			downCnt <= 3'b111;
+		else if (downCnt != 3'b000)
+			downCnt <= downCnt - 1'b1;
+		else
+			downCnt <= downCnt;
+end
+
+// Sync to ring osc clk
+always @(posedge clk_ringosc_i or posedge reset_i)
+	if (reset_i)
+	begin
+		downCnt1_r1 <= 1'b0;
+		downCnt1_r2 <= 1'b0;
+	end
+	else
+	begin
+		downCnt1_r1 <= downCnt[2];
+		downCnt1_r2 <= downCnt1_r1;
+	end
+
+assign ringosccnt_reset = reset_i || !enable_i;
+// Counting # of ringosc cyces in two 32KHz clock
+always @(posedge clk_ringosc_i or posedge ringosccnt_reset)
+begin
+	if (ringosccnt_reset)
+		ringosc_2_cnt <= 16'b0;
+	else if (downCnt1_r2)
+		ringosc_2_cnt <= ringosc_2_cnt + 1'b1;
+	else
+		ringosc_2_cnt <= ringosc_2_cnt;
+end
+
+assign	cal_val_o = ringosc_2_cnt;
+
+endmodule
\ No newline at end of file
diff --git a/BENCHMARK/ULPSH_fabric/rtl/src/ulpsh_rtl_defines.v b/BENCHMARK/ULPSH_fabric/rtl/src/ulpsh_rtl_defines.v
new file mode 100644
index 0000000..c754860
--- /dev/null
+++ b/BENCHMARK/ULPSH_fabric/rtl/src/ulpsh_rtl_defines.v
@@ -0,0 +1,26 @@
+// -----------------------------------------------------------------------------
+// title          : ulpsh_rtl_defines.v
+// project        : ULP Sensor Hub
+// description    : RTL defines
+// -----------------------------------------------------------------------------
+// copyright (c) 2014, QuickLogic Corporation
+// -----------------------------------------------------------------------------
+
+// Clock Circuit control defines
+`define 	OP_CLK_DIV		8'b01000000
+`define 	FFE1CLK_FREQ_SLT	8'b01000000
+`define 	SM1CLK_FREQ_SLT		8'b00100000
+
+`ifdef SIMULATION
+	`define 	OSC_SELECTION		1'b0
+`else
+	`define 	OSC_SELECTION		1'b1
+`endif
+
+`define 	ENABLE_FFE_F0_SINGLE_DM
+
+`define 	ENABLE_FFE_F0_EXTENDED_DM
+
+`define 	FFE_F0_SEG0_OFFSET  			9'h095
+
+`define 	ENABLE_FFE_F0_CM_SIZE_4K
diff --git a/BENCHMARK/cavlc_top/cavlc_top_yosys.blif b/BENCHMARK/cavlc_top/cavlc_top_yosys.blif
new file mode 100644
index 0000000..c4d330d
--- /dev/null
+++ b/BENCHMARK/cavlc_top/cavlc_top_yosys.blif
@@ -0,0 +1,8620 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model cavlc_top
+.inputs clk rst_n ena start rbsp(15) rbsp(14) rbsp(13) rbsp(12) rbsp(11) rbsp(10) rbsp(9) rbsp(8) rbsp(7) rbsp(6) rbsp(5) rbsp(4) rbsp(3) rbsp(2) rbsp(1) rbsp(0) nC(0) nC(1) nC(2) nC(3) nC(4) nC(5) max_coeff_num(0) max_coeff_num(1) max_coeff_num(2) max_coeff_num(3) max_coeff_num(4)
+.outputs coeff_0(0) coeff_0(1) coeff_0(2) coeff_0(3) coeff_0(4) coeff_0(5) coeff_0(6) coeff_0(7) coeff_0(8) coeff_1(0) coeff_1(1) coeff_1(2) coeff_1(3) coeff_1(4) coeff_1(5) coeff_1(6) coeff_1(7) coeff_1(8) coeff_2(0) coeff_2(1) coeff_2(2) coeff_2(3) coeff_2(4) coeff_2(5) coeff_2(6) coeff_2(7) coeff_2(8) coeff_3(0) coeff_3(1) coeff_3(2) coeff_3(3) coeff_3(4) coeff_3(5) coeff_3(6) coeff_3(7) coeff_3(8) coeff_4(0) coeff_4(1) coeff_4(2) coeff_4(3) coeff_4(4) coeff_4(5) coeff_4(6) coeff_4(7) coeff_4(8) coeff_5(0) coeff_5(1) coeff_5(2) coeff_5(3) coeff_5(4) coeff_5(5) coeff_5(6) coeff_5(7) coeff_5(8) coeff_6(0) coeff_6(1) coeff_6(2) coeff_6(3) coeff_6(4) coeff_6(5) coeff_6(6) coeff_6(7) coeff_6(8) coeff_7(0) coeff_7(1) coeff_7(2) coeff_7(3) coeff_7(4) coeff_7(5) coeff_7(6) coeff_7(7) coeff_7(8) coeff_8(0) coeff_8(1) coeff_8(2) coeff_8(3) coeff_8(4) coeff_8(5) coeff_8(6) coeff_8(7) coeff_8(8) coeff_9(0) coeff_9(1) coeff_9(2) coeff_9(3) coeff_9(4) coeff_9(5) coeff_9(6) coeff_9(7) coeff_9(8) coeff_10(0) coeff_10(1) coeff_10(2) coeff_10(3) coeff_10(4) coeff_10(5) coeff_10(6) coeff_10(7) coeff_10(8) coeff_11(0) coeff_11(1) coeff_11(2) coeff_11(3) coeff_11(4) coeff_11(5) coeff_11(6) coeff_11(7) coeff_11(8) coeff_12(0) coeff_12(1) coeff_12(2) coeff_12(3) coeff_12(4) coeff_12(5) coeff_12(6) coeff_12(7) coeff_12(8) coeff_13(0) coeff_13(1) coeff_13(2) coeff_13(3) coeff_13(4) coeff_13(5) coeff_13(6) coeff_13(7) coeff_13(8) coeff_14(0) coeff_14(1) coeff_14(2) coeff_14(3) coeff_14(4) coeff_14(5) coeff_14(6) coeff_14(7) coeff_14(8) coeff_15(0) coeff_15(1) coeff_15(2) coeff_15(3) coeff_15(4) coeff_15(5) coeff_15(6) coeff_15(7) coeff_15(8) TotalCoeff(0) TotalCoeff(1) TotalCoeff(2) TotalCoeff(3) TotalCoeff(4) len_comb(0) len_comb(1) len_comb(2) len_comb(3) len_comb(4) idle valid
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_0 a=TotalZeros_comb(0)
+.subckt out_buff A=cavlc_fsm.TotalCoeff(0) Q=TotalCoeff(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_fsm.TotalCoeff(1) Q=TotalCoeff(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_fsm.TotalCoeff(2) Q=TotalCoeff(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_fsm.TotalCoeff(3) Q=TotalCoeff(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_fsm.TotalCoeff(4) Q=TotalCoeff(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=clk Q=cavlc_fsm.clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=cavlc_read_run_befores.coeff_0(0) Q=coeff_0(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_0(1) Q=coeff_0(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_0(2) Q=coeff_0(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_0(3) Q=coeff_0(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_0(4) Q=coeff_0(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_0(5) Q=coeff_0(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_0(6) Q=coeff_0(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_0(7) Q=coeff_0(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_0(8) Q=coeff_0(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_1(0) Q=coeff_1(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_10(0) Q=coeff_10(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_10(1) Q=coeff_10(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_10(2) Q=coeff_10(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_10(3) Q=coeff_10(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_10(4) Q=coeff_10(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_10(5) Q=coeff_10(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_10(6) Q=coeff_10(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_10(7) Q=coeff_10(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_10(8) Q=coeff_10(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_11(0) Q=coeff_11(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_11(1) Q=coeff_11(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_11(2) Q=coeff_11(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_11(3) Q=coeff_11(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_11(4) Q=coeff_11(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_11(5) Q=coeff_11(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_11(6) Q=coeff_11(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_11(7) Q=coeff_11(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_11(8) Q=coeff_11(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_12(0) Q=coeff_12(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_12(1) Q=coeff_12(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_12(2) Q=coeff_12(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_12(3) Q=coeff_12(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_12(4) Q=coeff_12(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_12(5) Q=coeff_12(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_12(6) Q=coeff_12(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_12(7) Q=coeff_12(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_12(8) Q=coeff_12(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_13(0) Q=coeff_13(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_13(1) Q=coeff_13(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_13(2) Q=coeff_13(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_13(3) Q=coeff_13(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_13(4) Q=coeff_13(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_13(5) Q=coeff_13(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_13(6) Q=coeff_13(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_13(7) Q=coeff_13(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_13(8) Q=coeff_13(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_14(0) Q=coeff_14(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_14(1) Q=coeff_14(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_14(2) Q=coeff_14(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_14(3) Q=coeff_14(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_14(4) Q=coeff_14(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_14(5) Q=coeff_14(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_14(6) Q=coeff_14(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_14(7) Q=coeff_14(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_14(8) Q=coeff_14(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_15(0) Q=coeff_15(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_15(1) Q=coeff_15(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_15(2) Q=coeff_15(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_15(3) Q=coeff_15(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_15(4) Q=coeff_15(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_15(5) Q=coeff_15(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_15(6) Q=coeff_15(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_read_run_befores.coeff_15(7) Q=coeff_15(7)
+.attr module_not_derived 00000000000000000000000000000001
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+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_len_gen.len_comb(1) Q=len_comb(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_len_gen.len_comb(2) Q=len_comb(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_len_gen.len_comb(3) Q=len_comb(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cavlc_len_gen.len_comb(4) Q=len_comb(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=max_coeff_num(0) Q=cavlc_fsm.max_coeff_num(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=max_coeff_num(1) Q=cavlc_fsm.max_coeff_num(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=max_coeff_num(2) Q=cavlc_fsm.max_coeff_num(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=max_coeff_num(3) Q=cavlc_fsm.max_coeff_num(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=max_coeff_num(4) Q=cavlc_fsm.max_coeff_num(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=nC(0) Q=cavlc_read_total_coeffs.nC(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=nC(1) Q=cavlc_read_total_coeffs.nC(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=nC(2) Q=cavlc_read_total_coeffs.nC(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=nC(3) Q=cavlc_read_total_coeffs.nC(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=nC(4) Q=cavlc_read_total_coeffs.nC(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=nC(5) Q=cavlc_read_total_zeros.chroma_DC_sel
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(15) Q=cavlc_read_levels.rbsp(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(14) Q=cavlc_read_levels.rbsp(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(5) Q=cavlc_read_levels.rbsp(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(4) Q=cavlc_read_levels.rbsp(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(3) Q=cavlc_read_levels.rbsp(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(2) Q=cavlc_read_levels.rbsp(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(1) Q=cavlc_read_levels.rbsp(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(0) Q=cavlc_read_levels.rbsp(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(13) Q=cavlc_read_levels.rbsp(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(12) Q=cavlc_read_levels.rbsp(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(11) Q=cavlc_read_levels.rbsp(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(10) Q=cavlc_read_levels.rbsp(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(9) Q=cavlc_read_levels.rbsp(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(8) Q=cavlc_read_levels.rbsp(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(7) Q=cavlc_read_levels.rbsp(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rbsp(6) Q=cavlc_read_levels.rbsp(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rst_n Q=cavlc_fsm.rst_n
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=start Q=cavlc_fsm.start
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=cavlc_fsm.valid Q=valid
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt LUT4 I0=cavlc_read_total_coeffs.nC(2) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I3 O=TotalCoeff_comb(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0 I1=len_comb_LUT4_O_1_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 O=TotalCoeff_comb(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1 I2=len_comb_LUT4_O_1_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(8) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_1(7) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(11) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(8) I2=cavlc_read_total_coeffs.rbsp_1(9) I3=cavlc_read_total_coeffs.rbsp_1(10) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(12) I1=cavlc_read_total_coeffs.rbsp_1(10) I2=cavlc_read_total_coeffs.rbsp_1(8) I3=cavlc_read_total_coeffs.rbsp_1(9) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_1(7) I2=cavlc_read_total_coeffs.rbsp_1(6) I3=cavlc_read_total_coeffs.rbsp_1(5) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_1(8) I3=cavlc_read_total_coeffs.rbsp_1(9) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_2(4) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(6) I1=cavlc_read_total_coeffs.rbsp_2(4) I2=cavlc_read_total_coeffs.rbsp_2(5) I3=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=start_LUT4_I1_O_LUT4_I2_2_I3 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_4(0) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_3(1) I3=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_3(4) I3=cavlc_read_total_coeffs.rbsp_3(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I3 O=TotalCoeff_comb(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100001110
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_4(3) I1=cavlc_read_total_coeffs.rbsp_4(2) I2=start_LUT4_I1_O_LUT4_I2_2_I3 I3=cavlc_read_total_coeffs.rbsp_4(1) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(6) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I0 I3=cavlc_read_total_coeffs.rbsp_1(7) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(6) I1=cavlc_read_total_coeffs.rbsp_1(7) I2=cavlc_read_total_coeffs.rbsp_1(8) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_1(5) I3=cavlc_read_total_coeffs.rbsp_1(4) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(5) I2=cavlc_read_total_coeffs.rbsp_1(4) I3=cavlc_read_total_coeffs.rbsp_1(6) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(3) I3=cavlc_read_total_coeffs.rbsp_1(2) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_total_coeffs.nC(2) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000111110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=cavlc_read_total_coeffs.rbsp_2(1) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(1) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_total_coeffs.nC(2) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(3) I1=cavlc_read_total_coeffs.rbsp_2(4) I2=cavlc_read_total_coeffs.rbsp_2(5) I3=cavlc_read_total_coeffs.rbsp_2(2) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110011010101
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(4) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_2(5) I2=cavlc_read_total_coeffs.rbsp_2(6) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_2(7) I3=cavlc_read_total_coeffs.rbsp_2(8) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(4) I1=cavlc_read_total_coeffs.rbsp_2(6) I2=cavlc_read_total_coeffs.rbsp_2(5) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_1_I2_LUT4_O_I1 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(7) I1=cavlc_read_total_coeffs.rbsp_3(3) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_total_coeffs.rbsp_3(4) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(2) I2=cavlc_read_total_coeffs.rbsp_3(4) I3=cavlc_read_total_coeffs.rbsp_3(5) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(0) I1=cavlc_read_total_coeffs.rbsp_3(2) I2=cavlc_read_total_coeffs.rbsp_3(1) I3=start_LUT4_I1_O_LUT4_I2_2_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0 I2=cavlc_read_total_coeffs.rbsp_5(3) I3=cavlc_read_total_coeffs.rbsp_5(5) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I3 O=TotalCoeff_comb(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1 I2=cavlc_read_total_coeffs.nC(2) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I1 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I0 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_1(10) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(14) I1=cavlc_read_total_coeffs.rbsp_1(13) I2=cavlc_read_total_coeffs.rbsp_1(12) I3=cavlc_read_total_coeffs.rbsp_1(11) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111011111111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_total_coeffs.rbsp_1(11) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_I2 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(8) I1=cavlc_read_total_coeffs.rbsp_1(10) I2=cavlc_read_total_coeffs.rbsp_1(9) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(11) I1=cavlc_read_total_coeffs.rbsp_1(12) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=cavlc_read_total_coeffs.rbsp_1(7) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(8) I1=cavlc_read_total_coeffs.rbsp_1(9) I2=cavlc_read_total_coeffs.rbsp_1(7) I3=cavlc_read_total_coeffs.rbsp_1(6) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(6) I1=cavlc_read_total_coeffs.rbsp_1(8) I2=cavlc_read_total_coeffs.rbsp_1(7) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I1 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(5) I2=cavlc_read_total_coeffs.rbsp_1(7) I3=cavlc_read_total_coeffs.rbsp_1(6) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(5) I3=cavlc_read_total_coeffs.rbsp_1(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_2(1) I3=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_2(5) I2=cavlc_read_total_coeffs.rbsp_2(4) I3=cavlc_read_total_coeffs.rbsp_2(6) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(6) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_2(7) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111101110
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(9) I1=cavlc_read_total_coeffs.rbsp_2(8) I2=cavlc_read_total_coeffs.rbsp_2(10) I3=cavlc_read_total_coeffs.rbsp_2(11) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110011010101
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(10) I1=cavlc_read_total_coeffs.rbsp_2(8) I2=cavlc_read_total_coeffs.rbsp_2(12) I3=cavlc_read_total_coeffs.rbsp_2(11) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_2(9) I2=cavlc_read_total_coeffs.rbsp_2(10) I3=cavlc_read_total_coeffs.rbsp_2(8) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(5) I1=cavlc_read_total_coeffs.rbsp_2(6) I2=cavlc_read_total_coeffs.rbsp_2(7) I3=cavlc_read_total_coeffs.rbsp_2(4) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111101
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(5) I1=cavlc_read_total_coeffs.rbsp_2(2) I2=cavlc_read_total_coeffs.rbsp_2(3) I3=cavlc_read_total_coeffs.rbsp_2(4) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001101111100011
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_total_coeffs.nC(2) I3=start_LUT4_I1_O_LUT4_I2_2_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_3(1) I2=cavlc_read_total_coeffs.rbsp_3(0) I3=cavlc_read_total_coeffs.rbsp_3(2) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(7) I1=cavlc_read_total_coeffs.rbsp_3(5) I2=cavlc_read_total_coeffs.rbsp_3(6) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(4) I1=cavlc_read_total_coeffs.rbsp_3(6) I2=cavlc_read_total_coeffs.rbsp_3(5) I3=cavlc_read_total_coeffs.rbsp_3(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_3(1) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(1) I1=cavlc_read_total_coeffs.rbsp_3(5) I2=cavlc_read_total_coeffs.rbsp_3(4) I3=cavlc_read_total_coeffs.rbsp_3(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_3(2) I3=cavlc_read_total_coeffs.rbsp_3(0) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=start_LUT4_I1_O_LUT4_I2_2_I3 I1=cavlc_read_total_coeffs.rbsp_4(3) I2=cavlc_read_total_coeffs.rbsp_4(2) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(4) I1=cavlc_read_total_coeffs.rbsp_5(2) I2=cavlc_read_total_coeffs.rbsp_5(5) I3=cavlc_read_total_coeffs.rbsp_5(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*I3)"
+.param INIT 0010000000000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I3_LUT4_O_I3 I3=cavlc_read_total_coeffs.rbsp_5(1) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I3 O=TotalCoeff_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1 I2=cavlc_read_total_coeffs.nC(2) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_2(4) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_2(5) I2=cavlc_read_total_coeffs.rbsp_2(7) I3=cavlc_read_total_coeffs.rbsp_2(6) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_2(6) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=cavlc_read_total_coeffs.rbsp_2(8) I3=cavlc_read_total_coeffs.rbsp_2(7) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_2(9) I2=cavlc_read_total_coeffs.rbsp_2(11) I3=cavlc_read_total_coeffs.rbsp_2(10) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_2(12) I2=cavlc_read_total_coeffs.rbsp_2(10) I3=cavlc_read_total_coeffs.rbsp_2(13) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_2(11) I3=cavlc_read_total_coeffs.rbsp_2(9) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(12) I1=cavlc_read_total_coeffs.rbsp_2(11) I2=cavlc_read_total_coeffs.rbsp_2(10) I3=cavlc_read_total_coeffs.rbsp_2(9) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(6) I1=cavlc_read_total_coeffs.rbsp_2(7) I2=cavlc_read_total_coeffs.rbsp_2(8) I3=cavlc_read_total_coeffs.rbsp_2(5) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I2=cavlc_read_total_coeffs.rbsp_2(7) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I3 O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(9) I1=cavlc_read_total_coeffs.rbsp_2(8) I2=cavlc_read_total_coeffs.rbsp_2(10) I3=cavlc_read_total_coeffs.rbsp_2(11) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_2(5) I3=cavlc_read_total_coeffs.rbsp_2(6) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_2(2) I3=cavlc_read_total_coeffs.rbsp_2(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=cavlc_read_total_coeffs.rbsp_2(3) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(3) I1=cavlc_read_total_coeffs.rbsp_2(5) I2=cavlc_read_total_coeffs.rbsp_2(4) I3=cavlc_read_total_coeffs.rbsp_2(2) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_2(1) I3=cavlc_read_total_coeffs.rbsp_2(0) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.nC(1) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(2) I1=cavlc_read_total_coeffs.rbsp_2(0) I2=cavlc_read_total_coeffs.rbsp_2(3) I3=cavlc_read_total_coeffs.rbsp_2(1) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(2) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(1) I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I1 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I0 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(12) I2=cavlc_read_total_coeffs.rbsp_1(14) I3=cavlc_read_total_coeffs.rbsp_1(13) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_1(11) I3=cavlc_read_total_coeffs.rbsp_1(10) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(12) I1=cavlc_read_total_coeffs.rbsp_1(13) I2=cavlc_read_total_coeffs.rbsp_1(11) I3=cavlc_read_total_coeffs.rbsp_1(10) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(10) I3=cavlc_read_total_coeffs.rbsp_1(11) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(12) I1=cavlc_read_total_coeffs.rbsp_1(15) I2=cavlc_read_total_coeffs.rbsp_1(13) I3=cavlc_read_total_coeffs.rbsp_1(14) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011100011010010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(8) I2=cavlc_read_total_coeffs.rbsp_1(9) I3=cavlc_read_total_coeffs.rbsp_1(10) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(10) I2=cavlc_read_total_coeffs.rbsp_1(12) I3=cavlc_read_total_coeffs.rbsp_1(11) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(9) I1=cavlc_read_total_coeffs.rbsp_1(8) I2=cavlc_read_total_coeffs.rbsp_1(7) I3=cavlc_read_total_coeffs.rbsp_1(6) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(8) I1=cavlc_read_total_coeffs.rbsp_1(7) I2=cavlc_read_total_coeffs.rbsp_1(6) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_1(3) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(4) I1=cavlc_read_total_coeffs.rbsp_1(7) I2=cavlc_read_total_coeffs.rbsp_1(6) I3=cavlc_read_total_coeffs.rbsp_1(5) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_1(3) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2 I3=start_LUT4_I1_O_LUT4_I2_2_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(2) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(5) I2=cavlc_read_total_coeffs.rbsp_3(6) I3=cavlc_read_total_coeffs.rbsp_3(8) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(8) I1=cavlc_read_total_coeffs.rbsp_3(9) I2=cavlc_read_total_coeffs.rbsp_3(7) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(5) I2=cavlc_read_total_coeffs.rbsp_3(6) I3=cavlc_read_total_coeffs.rbsp_3(7) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_3(7) I2=cavlc_read_total_coeffs.rbsp_3(5) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(5) I1=cavlc_read_total_coeffs.rbsp_3(6) I2=cavlc_read_total_coeffs.rbsp_3(4) I3=cavlc_read_total_coeffs.rbsp_3(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_3(1) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(5) I1=cavlc_read_total_coeffs.rbsp_3(3) I2=cavlc_read_total_coeffs.rbsp_3(4) I3=cavlc_read_total_coeffs.rbsp_3(2) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(1) I2=cavlc_read_total_coeffs.rbsp_3(3) I3=cavlc_read_total_coeffs.rbsp_3(2) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(4) I1=cavlc_read_total_coeffs.rbsp_3(1) I2=cavlc_read_total_coeffs.rbsp_3(2) I3=cavlc_read_total_coeffs.rbsp_3(0) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.nC(2) I2=cavlc_read_total_coeffs.rbsp_3(0) I3=cavlc_read_total_coeffs.rbsp_3(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=start_LUT4_I1_O_LUT4_I2_2_I3 I2=cavlc_read_total_coeffs.rbsp_4(3) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_4(2) I3=cavlc_read_total_coeffs.rbsp_4(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_4(4) I2=cavlc_read_total_coeffs.rbsp_4(0) I3=cavlc_read_total_coeffs.rbsp_4(1) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.nC(0) I2=cavlc_read_total_coeffs.nC(3) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.nC(4) I1=cavlc_read_total_coeffs.nC(1) I2=cavlc_read_total_coeffs.nC(2) I3=cavlc_read_total_zeros.chroma_DC_sel O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(2) I1=cavlc_read_total_coeffs.rbsp_5(1) I2=cavlc_read_total_coeffs.rbsp_5(5) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I3_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 I3=cavlc_read_total_coeffs.rbsp_5(0) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I1_O I1=len_comb_LUT4_O_1_I2_LUT4_O_I2 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_1(11) I2=cavlc_read_total_coeffs.rbsp_1(10) I3=cavlc_read_total_coeffs.rbsp_1(9) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_1(11) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I0 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(13) I1=cavlc_read_total_coeffs.rbsp_1(11) I2=cavlc_read_total_coeffs.rbsp_1(12) I3=cavlc_read_total_coeffs.rbsp_1(10) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_I0 I1=cavlc_read_total_coeffs.rbsp_1(11) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(15) I1=cavlc_read_total_coeffs.rbsp_1(14) I2=cavlc_read_total_coeffs.rbsp_1(13) I3=cavlc_read_total_coeffs.rbsp_1(12) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_I2 I1=cavlc_read_total_coeffs.rbsp_1(11) I2=cavlc_read_total_coeffs.rbsp_1(10) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I0 O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_1(12) I3=cavlc_read_total_coeffs.rbsp_1(13) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(15) I1=cavlc_read_total_coeffs.rbsp_1(14) I2=cavlc_read_total_coeffs.rbsp_1(13) I3=cavlc_read_total_coeffs.rbsp_1(12) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=cavlc_read_total_coeffs.rbsp_2(4) I2=cavlc_read_total_coeffs.rbsp_2(1) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 O=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_2(7) I3=cavlc_read_total_coeffs.rbsp_2(6) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_2(5) I3=cavlc_read_total_coeffs.rbsp_2(4) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_2(6) I2=cavlc_read_total_coeffs.rbsp_2(8) I3=cavlc_read_total_coeffs.rbsp_2(7) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111110
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_2(6) I2=cavlc_read_total_coeffs.rbsp_2(7) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*I3)"
+.param INIT 0010000000000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_2(10) I3=cavlc_read_total_coeffs.rbsp_2(9) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(9) I1=cavlc_read_total_coeffs.rbsp_2(10) I2=cavlc_read_total_coeffs.rbsp_2(11) I3=cavlc_read_total_coeffs.rbsp_2(8) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110100010000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(2) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2 I3=start_LUT4_I1_O_LUT4_I2_2_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.nC(2) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_3(0) I3=cavlc_read_total_coeffs.rbsp_3(1) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(3) I2=cavlc_read_total_coeffs.rbsp_3(2) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_3(3) I3=cavlc_read_total_coeffs.rbsp_3(2) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_3(4) I3=cavlc_read_total_coeffs.rbsp_3(5) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_3(6) I3=cavlc_read_total_coeffs.rbsp_3(5) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_3(4) I3=cavlc_read_total_coeffs.rbsp_3(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(8) I1=cavlc_read_total_coeffs.rbsp_3(6) I2=cavlc_read_total_coeffs.rbsp_3(5) I3=cavlc_read_total_coeffs.rbsp_3(7) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(5) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=cavlc_read_total_coeffs.rbsp_3(6) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I2 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(7) I2=cavlc_read_total_coeffs.rbsp_3(9) I3=cavlc_read_total_coeffs.rbsp_3(8) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_4(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I3_LUT4_O_I1 I2=start_LUT4_I1_O_LUT4_I2_2_I3 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_4(1) I2=cavlc_read_total_coeffs.rbsp_4(2) I3=cavlc_read_total_coeffs.rbsp_4(3) O=cavlc_fsm.TotalCoeff_comb_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_I3 O=TrailingOnes_comb(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110110000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I3 O=TrailingOnes_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.nC(2) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_1(1) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_1(4) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_1(10) I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(9) I3=cavlc_read_total_coeffs.rbsp_1(8) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(14) I1=cavlc_read_total_coeffs.rbsp_1(12) I2=cavlc_read_total_coeffs.rbsp_1(11) I3=cavlc_read_total_coeffs.rbsp_1(15) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(12) I1=cavlc_read_total_coeffs.rbsp_1(13) I2=cavlc_read_total_coeffs.rbsp_1(14) I3=cavlc_read_total_coeffs.rbsp_1(11) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(10) I3=cavlc_read_total_coeffs.rbsp_1(11) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(9) I2=cavlc_read_total_coeffs.rbsp_1(8) I3=cavlc_read_total_coeffs.rbsp_1(12) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(13) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I0 I2=cavlc_read_total_coeffs.rbsp_1(10) I3=cavlc_read_total_coeffs.rbsp_1(7) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(9) I1=cavlc_read_total_coeffs.rbsp_1(7) I2=cavlc_read_total_coeffs.rbsp_1(6) I3=cavlc_read_total_coeffs.rbsp_1(5) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(8) I1=cavlc_read_total_coeffs.rbsp_1(6) I2=cavlc_read_total_coeffs.rbsp_1(7) I3=cavlc_read_total_coeffs.rbsp_1(5) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(5) I1=cavlc_read_total_coeffs.rbsp_1(6) I2=cavlc_read_total_coeffs.rbsp_1(4) I3=cavlc_read_total_coeffs.rbsp_1(3) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(2) I2=cavlc_read_total_coeffs.rbsp_1(5) I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_1(0) I3=cavlc_read_total_coeffs.nC(1) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(9) I1=cavlc_read_total_coeffs.rbsp_2(11) I2=cavlc_read_total_coeffs.rbsp_2(13) I3=cavlc_read_total_coeffs.rbsp_2(12) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000010101011
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(13) I1=cavlc_read_total_coeffs.rbsp_2(11) I2=cavlc_read_total_coeffs.rbsp_2(10) I3=cavlc_read_total_coeffs.rbsp_2(9) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_2(10) I2=cavlc_read_total_coeffs.rbsp_2(6) I3=cavlc_read_total_coeffs.rbsp_2(7) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000101
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(9) I1=cavlc_read_total_coeffs.rbsp_2(10) I2=cavlc_read_total_coeffs.rbsp_2(11) I3=cavlc_read_total_coeffs.rbsp_2(8) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_2(8) I3=cavlc_read_total_coeffs.rbsp_2(6) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(7) I1=cavlc_read_total_coeffs.rbsp_2(5) I2=cavlc_read_total_coeffs.rbsp_2(4) I3=cavlc_read_total_coeffs.rbsp_2(6) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101100001111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(3) I1=cavlc_read_total_coeffs.rbsp_2(2) I2=cavlc_read_total_coeffs.rbsp_2(5) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(2) I1=cavlc_read_total_coeffs.rbsp_2(0) I2=cavlc_read_total_coeffs.rbsp_2(1) I3=cavlc_read_total_coeffs.nC(1) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.nC(2) I3=start_LUT4_I1_O_LUT4_I2_2_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=cavlc_read_total_coeffs.rbsp_3(9) I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(8) I1=cavlc_read_total_coeffs.rbsp_3(6) I2=cavlc_read_total_coeffs.rbsp_3(7) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(4) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_3(5) I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(8) I2=cavlc_read_total_coeffs.rbsp_3(6) I3=cavlc_read_total_coeffs.rbsp_3(7) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(3) I2=cavlc_read_total_coeffs.rbsp_3(4) I3=cavlc_read_total_coeffs.rbsp_3(7) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(6) I1=cavlc_read_total_coeffs.rbsp_3(4) I2=cavlc_read_total_coeffs.rbsp_3(3) I3=cavlc_read_total_coeffs.rbsp_3(2) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(2) I2=cavlc_read_total_coeffs.rbsp_3(5) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_3(3) I2=cavlc_read_total_coeffs.rbsp_3(1) I3=cavlc_read_total_coeffs.rbsp_3(0) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111101010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(2) I2=cavlc_read_total_coeffs.rbsp_3(4) I3=cavlc_read_total_coeffs.rbsp_3(3) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101100
+.subckt LUT4 I0=start_LUT4_I1_O_LUT4_I2_2_I3 I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I1_LUT4_O_I3 I2=cavlc_read_total_coeffs.rbsp_4(5) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(1) I1=cavlc_read_total_coeffs.rbsp_5(2) I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I3_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I3_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_5(4) I3=cavlc_read_total_coeffs.rbsp_5(3) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(7) I1=cavlc_read_total_coeffs.rbsp_5(3) I2=cavlc_read_total_coeffs.rbsp_5(6) I3=cavlc_read_total_coeffs.rbsp_5(5) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001111011100
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.nC(2) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_1(2) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(5) I3=cavlc_read_total_coeffs.rbsp_1(7) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010111111100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=cavlc_read_total_coeffs.rbsp_1(5) I3=cavlc_read_total_coeffs.rbsp_1(7) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_1(6) I3=cavlc_read_total_coeffs.rbsp_1(8) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(8) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(9) I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(12) I3=cavlc_read_total_coeffs.rbsp_1(10) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(13) I2=cavlc_read_total_coeffs.rbsp_1(12) I3=cavlc_read_total_coeffs.rbsp_1(15) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(12) I1=cavlc_read_total_coeffs.rbsp_1(13) I2=cavlc_read_total_coeffs.rbsp_1(14) I3=cavlc_read_total_coeffs.rbsp_1(11) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011001100001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(6) I2=cavlc_read_total_coeffs.rbsp_1(11) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(4) I2=cavlc_read_total_coeffs.rbsp_1(5) I3=cavlc_read_total_coeffs.rbsp_1(6) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_1(3) I3=cavlc_read_total_coeffs.rbsp_1(4) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I1 I3=cavlc_read_total_coeffs.rbsp_1(1) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(7) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_2(6) I3=cavlc_read_total_coeffs.rbsp_2(8) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101011111100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_2(10) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(12) I1=cavlc_read_total_coeffs.rbsp_2(11) I2=cavlc_read_total_coeffs.rbsp_2(9) I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000000110111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(13) I1=cavlc_read_total_coeffs.rbsp_2(12) I2=cavlc_read_total_coeffs.rbsp_2(11) I3=cavlc_read_total_coeffs.rbsp_2(10) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(9) I1=cavlc_read_total_coeffs.rbsp_2(6) I2=cavlc_read_total_coeffs.rbsp_2(7) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(6) I1=cavlc_read_total_coeffs.rbsp_2(4) I2=cavlc_read_total_coeffs.rbsp_2(7) I3=cavlc_read_total_coeffs.rbsp_2(5) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_2(1) I2=cavlc_read_total_coeffs.rbsp_2(4) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.nC(2) I3=start_LUT4_I1_O_LUT4_I2_2_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_3(0) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(6) I1=cavlc_read_total_coeffs.rbsp_3(4) I2=cavlc_read_total_coeffs.rbsp_3(5) I3=cavlc_read_total_coeffs.rbsp_3(3) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001110000000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(8) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.rbsp_3(6) I3=cavlc_read_total_coeffs.rbsp_3(5) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_total_coeffs.rbsp_3(7) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_3(6) I2=cavlc_read_total_coeffs.rbsp_3(2) I3=cavlc_read_total_coeffs.rbsp_3(1) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(1) I2=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_3(1) I2=cavlc_read_total_coeffs.rbsp_3(0) I3=cavlc_read_total_coeffs.rbsp_3(2) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(4) I2=cavlc_read_total_coeffs.rbsp_3(3) I3=cavlc_read_total_coeffs.rbsp_3(5) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I1_LUT4_O_I3 I1=cavlc_read_total_coeffs.rbsp_4(4) I2=start_LUT4_I1_O_LUT4_I2_2_I3 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(4) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_5(2) I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_3_I3 O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(7) I1=cavlc_read_total_coeffs.rbsp_5(5) I2=cavlc_read_total_coeffs.rbsp_5(6) I3=cavlc_read_total_coeffs.rbsp_5(3) O=cavlc_fsm.TrailingOnes_comb_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011001111100000
+.subckt ff CQZ=cavlc_fsm.i(3) D=cavlc_fsm.i_ff_CQZ_D QCK=cavlc_fsm.clk QEN=idle_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_fsm.i(2) D=cavlc_fsm.i_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=idle_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I0 I1=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I1 I2=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2 I3=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cavlc_fsm.i_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O I2=cavlc_fsm.i(2) I3=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_fsm.i(0) I2=TrailingOnes(1) I3=TrailingOnes(0) O=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=TotalCoeff_comb(0) I1=TotalCoeff_comb(1) I2=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O I3=TotalCoeff_comb(2) O=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I0 I1=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.i(2) I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101011000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff(2) I3=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 I3=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 O=idle_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(0) I3=cavlc_fsm.i(1) O=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=cavlc_fsm.i(1) D=cavlc_fsm.i_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=idle_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_2_D_LUT4_O_I0 I1=cavlc_fsm.i_ff_CQZ_2_D_LUT4_O_I1 I2=cavlc_fsm.i_ff_CQZ_2_D_LUT4_O_I2 I3=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cavlc_fsm.i_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111100010001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i(0) I2=cavlc_fsm.i(1) I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=cavlc_fsm.i_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=cavlc_fsm.TotalCoeff(0) I3=cavlc_fsm.TotalCoeff(1) O=cavlc_fsm.i_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0 I1=TotalCoeff_comb(0) I2=TotalCoeff_comb(1) I3=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O O=cavlc_fsm.i_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt LUT4 I0=cavlc_fsm.i(0) I1=TrailingOnes(0) I2=cavlc_fsm.i(1) I3=TrailingOnes(1) O=cavlc_fsm.i_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt ff CQZ=cavlc_fsm.i(0) D=cavlc_fsm.i_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=idle_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O I2=cavlc_fsm.i_ff_CQZ_3_D_LUT4_O_I2 I3=cavlc_fsm.i_ff_CQZ_3_D_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=cavlc_fsm.i(0) I3=cavlc_fsm.TotalCoeff(0) O=cavlc_fsm.i_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=TotalCoeff_comb(0) I1=cavlc_fsm.i(0) I2=TrailingOnes(0) I3=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O O=cavlc_fsm.i_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I1 I2=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I2 I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111100000
+.subckt LUT4 I0=TotalCoeff_comb(0) I1=TotalCoeff_comb(1) I2=TotalCoeff_comb(2) I3=TotalCoeff_comb(3) O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 I1=cavlc_fsm.i(2) I2=cavlc_fsm.i(3) I3=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff(3) I2=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=cavlc_fsm.TotalCoeff(2) O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3_LUT4_I1_O I1=idle_LUT4_I1_I0 I2=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3_LUT4_I1_O I2=idle_LUT4_I1_I0 I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=cavlc_read_run_befores.sel I1=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3 I2=cavlc_read_run_befores.ZeroLeft_init I3=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I2=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=cavlc_read_run_befores.clr_LUT4_I3_O O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I2=cavlc_fsm.i(2) I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I1=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O I2=cavlc_read_run_befores.clr_LUT4_I3_O I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I2=idle_LUT4_I1_I0 I3=cavlc_read_run_befores.clr_LUT4_I3_O O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=ZeroLeft(1) I2=cavlc_fsm.i(0) I3=ZeroLeft(0) O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100110010000
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_fsm.i(0) I2=ZeroLeft(0) I3=ZeroLeft(1) O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111010111101
+.subckt LUT4 I0=cavlc_fsm.i(2) I1=cavlc_fsm.i(1) I2=cavlc_read_run_befores.clr_LUT4_I3_O I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_fsm.i(0) I2=ZeroLeft(0) I3=ZeroLeft(1) O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000101000
+.subckt LUT4 I0=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_O I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_fsm.i(0) I2=ZeroLeft(0) I3=ZeroLeft(1) O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110101111110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I2=cavlc_fsm.i(3) I3=cavlc_read_run_befores.clr_LUT4_I3_O O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0 I1=cavlc_fsm.i(3) I2=ZeroLeft(3) I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0 I1=cavlc_fsm.i(3) I2=ZeroLeft(3) I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=ZeroLeft(2) I2=cavlc_fsm.i(2) I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0 I2=cavlc_fsm.i(3) I3=ZeroLeft(3) O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0 I2=cavlc_fsm.i(3) I3=ZeroLeft(3) O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=ZeroLeft(2) I2=cavlc_fsm.i(2) I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=ZeroLeft(1) I2=cavlc_fsm.i(0) I3=ZeroLeft(0) O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i(3) I2=cavlc_fsm.i(2) I3=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 O=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt ff CQZ=cavlc_fsm.valid D=cavlc_fsm.valid_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.valid_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=idle_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3_LUT4_I1_O O=cavlc_fsm.valid_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=cavlc_fsm.valid_ff_CQZ_D I1=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1 I2=idle_ff_CQZ_D_LUT4_O_I3 I3=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_fsm.valid_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_I3_O I2=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_I2 I3=cavlc_fsm.ena O=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O I3=idle_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.ena I2=cavlc_fsm.start I3=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1 O=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_run_befores.clr I1=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I1 I2=cavlc_fsm.idle I3=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O O=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.prefix_sel I3=cavlc_read_levels.t1s_sel O=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=idle_LUT4_I1_I0 I1=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I2=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3_LUT4_I1_O I3=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt ff CQZ=cavlc_read_levels.calc_sel D=cavlc_read_levels.calc_sel_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O I2=cavlc_read_levels.suffix_sel_ff_CQZ_D I3=cavlc_read_levels.calc_sel_ff_CQZ_D O=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_levels.calc_sel I1=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.suffix_sel I3=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O O=cavlc_read_levels.calc_sel_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cavlc_read_levels.suffix_sel I1=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O I3=cavlc_read_levels.calc_sel O=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3 O=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_init I1=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3 I2=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O I3=cavlc_read_run_befores.sel O=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.calc_sel I3=cavlc_read_levels.suffix_sel O=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_fsm.idle I1=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O I3=cavlc_read_run_befores.clr O=idle_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_run_befores.sel I3=cavlc_read_run_befores.ZeroLeft_init O=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=cavlc_read_levels.level_0(8) D=cavlc_read_levels.level_0_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_0(7) D=cavlc_read_levels.level_0_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_0(6) D=cavlc_read_levels.level_0_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_0(5) D=cavlc_read_levels.level_0_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_0(4) D=cavlc_read_levels.level_0_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_0(3) D=cavlc_read_levels.level_0_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_0_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_0(2) D=cavlc_read_levels.level_0_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_0_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_0(1) D=cavlc_read_levels.level_0_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_0_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_0(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I1=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I1=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=idle_LUT4_I1_I0 I3=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_I3_1_I1 I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 O=cavlc_read_levels.level_14_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I2=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 I3=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_abs_refresh I3=cavlc_read_levels.t1s_sel O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I2 I1=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1 I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011101110
+.subckt LUT4 I0=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1 I1=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_I2 I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=TrailingOnes(1) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.i(0) O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111001100000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1 I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O I1=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I2=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O I3=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=TrailingOnes(1) I1=cavlc_fsm.i(1) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I3=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 I3=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I1=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt ff CQZ=cavlc_read_levels.level_10(8) D=cavlc_read_levels.level_10_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_10(7) D=cavlc_read_levels.level_10_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=cavlc_read_levels.level_10(6) D=cavlc_read_levels.level_10_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt ff CQZ=cavlc_read_levels.level_10(5) D=cavlc_read_levels.level_10_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=cavlc_read_levels.level_10(4) D=cavlc_read_levels.level_10_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=cavlc_read_levels.level_10(3) D=cavlc_read_levels.level_10_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_10_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=cavlc_read_levels.level_10(2) D=cavlc_read_levels.level_10_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_10_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=cavlc_read_levels.level_10(1) D=cavlc_read_levels.level_10_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_10_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=cavlc_read_levels.level_10(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_10(5) I3=cavlc_read_levels.level_11(5) O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I0 I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O I2=cavlc_read_levels.level_8(5) I3=cavlc_read_levels.level_9(5) O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_I0 I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I3_O I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_2(5) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1 I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_I0_LUT4_O_I2 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I2=cavlc_read_levels.level_0(5) I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_3(5) I2=cavlc_read_levels.level_1(5) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cavlc_read_levels.level_11(8) I1=cavlc_read_levels.level_10(8) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_8(8) I2=cavlc_read_levels.level_9(8) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(0) I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I3=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cavlc_read_levels.level_11(8) D=cavlc_read_levels.level_11_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_11_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_11(7) D=cavlc_read_levels.level_11_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_11_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_11_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_11(6) D=cavlc_read_levels.level_11_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_11_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_11_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_11(5) D=cavlc_read_levels.level_11_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_11_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_11_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_11(4) D=cavlc_read_levels.level_11_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_11_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_11_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_11(3) D=cavlc_read_levels.level_11_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_11_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_11_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_11(2) D=cavlc_read_levels.level_11_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_11_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_11_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_11(1) D=cavlc_read_levels.level_11_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_11_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_11_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_11(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_11_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_11_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=cavlc_read_levels.level_13(8) I1=cavlc_read_levels.level_12(8) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I1 I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I2 I3=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=cavlc_read_levels.level_5(2) I1=cavlc_read_levels.level_4(2) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i(0) I2=cavlc_read_levels.level_12(2) I3=cavlc_read_levels.level_13(2) O=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I1=cavlc_read_levels.level_7(2) I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I3_I2 I3=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=cavlc_read_levels.level_15(2) I1=cavlc_read_levels.level_14(2) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O I1=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_I3_O O=cavlc_read_levels.level_11_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt ff CQZ=cavlc_read_levels.level_12(8) D=cavlc_read_levels.level_12_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_12(7) D=cavlc_read_levels.level_12_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_12_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_12(6) D=cavlc_read_levels.level_12_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_12_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_12(5) D=cavlc_read_levels.level_12_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_12_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_12(4) D=cavlc_read_levels.level_12_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_12_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_12(3) D=cavlc_read_levels.level_12_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_12_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_12(2) D=cavlc_read_levels.level_12_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_12_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_12(1) D=cavlc_read_levels.level_12_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_12_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_12(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_12_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I2 I3=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=TrailingOnes(1) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.i(0) O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111001100000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 I2=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I3=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I2=cavlc_fsm.i(0) I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I1=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=cavlc_read_levels.level_14(1) I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2 I3=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000011111111
+.subckt LUT4 I0=cavlc_read_levels.level_14(0) I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_I2 I3=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000011111111
+.subckt LUT4 I0=cavlc_fsm.i(0) I1=cavlc_fsm.i(1) I2=cavlc_read_levels.level_12(0) I3=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_I2_LUT4_O_I3 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O I1=cavlc_read_levels.level_13(0) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_15(0) O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_I0 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_O I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_I0_LUT4_O_I0 I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_I0_LUT4_O_I1 I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O I2=cavlc_read_levels.level_8(0) I3=cavlc_read_levels.level_9(0) O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i(0) I2=cavlc_read_levels.level_10(0) I3=cavlc_read_levels.level_11(0) O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=cavlc_fsm.i(0) I1=cavlc_fsm.i(1) I2=cavlc_read_levels.level_12(1) I3=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O I1=cavlc_read_levels.level_13(1) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_15(1) O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1 I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I0 I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I1 I2=cavlc_fsm.i(2) I3=cavlc_fsm.i(3) O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110011111010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.level_2(1) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I2=cavlc_read_levels.level_0(1) I3=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_3(1) I2=cavlc_read_levels.level_1(1) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cavlc_read_levels.level_9(1) I1=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_8(1) I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_11(1) I1=cavlc_read_levels.level_10(1) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.i(0) O=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_levels.level_13(8) D=cavlc_read_levels.level_13_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_13_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_13(7) D=cavlc_read_levels.level_13_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_13_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_13_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_13(6) D=cavlc_read_levels.level_13_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_13_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_13_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_13(5) D=cavlc_read_levels.level_13_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_13_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_13_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_13(4) D=cavlc_read_levels.level_13_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_13_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_13_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_13(3) D=cavlc_read_levels.level_13_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_13_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_13_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_13(2) D=cavlc_read_levels.level_13_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_13_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_13_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_13(1) D=cavlc_read_levels.level_13_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_13_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_13_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_13(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_13_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_13_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(1) I3=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.level_13_ff_CQZ_QEN_LUT4_O_I0 I1=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_levels.level_13_ff_CQZ_QEN_LUT4_O_I2 I3=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_levels.level_13_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i(0) I2=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 O=cavlc_read_levels.level_13_ff_CQZ_QEN_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_13_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt ff CQZ=cavlc_read_levels.level_14(8) D=cavlc_read_levels.level_14_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_14(7) D=cavlc_read_levels.level_14_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_14_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_14(6) D=cavlc_read_levels.level_14_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_14_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_14(5) D=cavlc_read_levels.level_14_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_14_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_14(4) D=cavlc_read_levels.level_14_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_14_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_14(3) D=cavlc_read_levels.level_14_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_14_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_14(2) D=cavlc_read_levels.level_14_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_14_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_14(1) D=cavlc_read_levels.level_14_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_14_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_14(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_14_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffix_sel_LUT4_I0_O I3=cavlc_read_levels.rbsp(1) O=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cavlc_read_levels.level_15(8) D=cavlc_read_levels.level_15_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_15(7) D=cavlc_read_levels.level_15_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 O=cavlc_read_levels.level_15_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_15(6) D=cavlc_read_levels.level_15_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_15_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111010
+.subckt ff CQZ=cavlc_read_levels.level_15(5) D=cavlc_read_levels.level_15_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O O=cavlc_read_levels.level_15_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111010
+.subckt ff CQZ=cavlc_read_levels.level_15(4) D=cavlc_read_levels.level_15_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O O=cavlc_read_levels.level_15_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt ff CQZ=cavlc_read_levels.level_15(3) D=cavlc_read_levels.level_15_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_15_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt ff CQZ=cavlc_read_levels.level_15(2) D=cavlc_read_levels.level_15_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3 O=cavlc_read_levels.level_15_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp(3) I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp(2) I1=cavlc_read_levels.level_code_tmp(1) I2=cavlc_read_levels.level_LUT4_O_I3 I3=cavlc_read_levels.level_code_tmp(0) O=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110101000
+.subckt ff CQZ=cavlc_read_levels.level_15(1) D=cavlc_read_levels.level_15_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 O=cavlc_read_levels.level_15_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_15(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O O=cavlc_read_levels.level_15_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_levels.level_15_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_levels.level_1(8) D=cavlc_read_levels.level_1_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_1_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_1(7) D=cavlc_read_levels.level_1_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_1_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_1(6) D=cavlc_read_levels.level_1_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_1_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_1(5) D=cavlc_read_levels.level_1_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_1_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_1(4) D=cavlc_read_levels.level_1_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_1_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_1(3) D=cavlc_read_levels.level_1_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_1_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_1_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_1(2) D=cavlc_read_levels.level_1_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_1_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_1_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_1(1) D=cavlc_read_levels.level_1_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_1_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_1_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_1(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_1_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i(0) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I3=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.i(0) O=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_levels.level_1_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I1=cavlc_fsm.i(0) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=TrailingOnes(1) O=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i(0) I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(2) I3=cavlc_fsm.i(3) O=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_abs_refresh I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt ff CQZ=cavlc_read_levels.level_2(8) D=cavlc_read_levels.level_2_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_2(7) D=cavlc_read_levels.level_2_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_2(6) D=cavlc_read_levels.level_2_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_2(5) D=cavlc_read_levels.level_2_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_2(4) D=cavlc_read_levels.level_2_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_2(3) D=cavlc_read_levels.level_2_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_2_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_2(2) D=cavlc_read_levels.level_2_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_2_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_2(1) D=cavlc_read_levels.level_2_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_2_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_2(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I1=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I2 I3=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3 O=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I1 I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 O=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 O=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 O=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 I2=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 O=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 O=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt ff CQZ=cavlc_read_levels.level_3(8) D=cavlc_read_levels.level_3_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_3(7) D=cavlc_read_levels.level_3_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_3(6) D=cavlc_read_levels.level_3_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_3(5) D=cavlc_read_levels.level_3_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_3(4) D=cavlc_read_levels.level_3_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_3(3) D=cavlc_read_levels.level_3_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_3_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_3(2) D=cavlc_read_levels.level_3_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_3_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_3(1) D=cavlc_read_levels.level_3_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_3_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_3(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_levels.level_4(8) D=cavlc_read_levels.level_4_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_4(7) D=cavlc_read_levels.level_4_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_4(6) D=cavlc_read_levels.level_4_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_4(5) D=cavlc_read_levels.level_4_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_4(4) D=cavlc_read_levels.level_4_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_4(3) D=cavlc_read_levels.level_4_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_4_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_4(2) D=cavlc_read_levels.level_4_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_4_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_4(1) D=cavlc_read_levels.level_4_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_4_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_4(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I2=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 I3=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I1 I2=cavlc_read_levels.level_6(6) I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I1 I2=cavlc_read_levels.level_6(5) I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I1_LUT4_O_I1 I2=cavlc_read_levels.level_7(5) I3=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=cavlc_read_levels.level_5(5) I1=cavlc_read_levels.level_4(5) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I3_I0 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I3_I1 I2=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_15(5) I1=cavlc_read_levels.level_14(5) I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_12(5) I2=cavlc_read_levels.level_13(5) I3=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_I1 I2=cavlc_read_levels.level_6(2) I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I0 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I1 I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_2(2) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1 I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I0_LUT4_O_I2 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I2=cavlc_read_levels.level_0(2) I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_3(2) I2=cavlc_read_levels.level_1(2) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I0 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I1 I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O I2=cavlc_read_levels.level_8(2) I3=cavlc_read_levels.level_9(2) O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i(0) I2=cavlc_read_levels.level_10(2) I3=cavlc_read_levels.level_11(2) O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1 I2=cavlc_read_levels.level_7(6) I3=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=cavlc_read_levels.level_5(6) I1=cavlc_read_levels.level_4(6) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I0 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1 I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I0 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1 I2=cavlc_fsm.i(1) I3=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O I2=cavlc_read_levels.level_12(6) I3=cavlc_read_levels.level_13(6) O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_levels.level_14(6) I3=cavlc_read_levels.level_15(6) O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1 I2=cavlc_fsm.i(2) I3=cavlc_fsm.i(3) O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110011111010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.level_2(6) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I2=cavlc_read_levels.level_0(6) I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_3(6) I2=cavlc_read_levels.level_1(6) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cavlc_read_levels.level_9(6) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_8(6) I3=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_11(6) I1=cavlc_read_levels.level_10(6) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.i(0) O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I2 I3=cavlc_read_levels.level_2_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=cavlc_read_levels.level_3_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_4(1) I2=cavlc_read_levels.level_5(1) I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_4(0) I2=cavlc_read_levels.level_5(0) I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_I0 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_read_levels.level_7(0) I1=cavlc_read_levels.level_6(0) I2=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_2(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1 I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_I3_LUT4_O_I2 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I2=cavlc_read_levels.level_0(0) I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_3(0) I2=cavlc_read_levels.level_1(0) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_1_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I2 I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_levels.level_7(1) I1=cavlc_read_levels.level_6(1) I2=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I3=cavlc_read_levels.level_4_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_levels.level_4_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I1=cavlc_fsm.i(0) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_4_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011011100000011
+.subckt ff CQZ=cavlc_read_levels.level_5(8) D=cavlc_read_levels.level_5_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_5(7) D=cavlc_read_levels.level_5_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_5(6) D=cavlc_read_levels.level_5_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_5(5) D=cavlc_read_levels.level_5_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_5(4) D=cavlc_read_levels.level_5_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_5(3) D=cavlc_read_levels.level_5_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_5_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_5(2) D=cavlc_read_levels.level_5_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_5_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_5(1) D=cavlc_read_levels.level_5_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_5_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_5(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=cavlc_read_levels.level_13_ff_CQZ_QEN_LUT4_O_I0 I1=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 I3=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O O=cavlc_read_levels.level_5_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=cavlc_read_levels.level_7(8) I1=cavlc_read_levels.level_6(8) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_7(7) I1=cavlc_read_levels.level_6(7) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_I0 I1=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_I2 I3=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cavlc_read_levels.level_15(8) I1=cavlc_read_levels.level_14(8) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_5(8) I1=cavlc_read_levels.level_4(8) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I1=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_I1 I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I2 I3=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I3 O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_0(8) I2=cavlc_read_levels.level_1(8) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=cavlc_read_levels.level_3(8) I1=cavlc_read_levels.level_2(8) I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(2) I3=cavlc_fsm.i(3) O=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_levels.level_6(8) D=cavlc_read_levels.level_6_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_6(7) D=cavlc_read_levels.level_6_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_6(6) D=cavlc_read_levels.level_6_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_6(5) D=cavlc_read_levels.level_6_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_6(4) D=cavlc_read_levels.level_6_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_6(3) D=cavlc_read_levels.level_6_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_6_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_6(2) D=cavlc_read_levels.level_6_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_6_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_6(1) D=cavlc_read_levels.level_6_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_6_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_6(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I1=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I3=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I3 O=cavlc_read_levels.level_6_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I3=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3 I2=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 O=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt ff CQZ=cavlc_read_levels.level_7(8) D=cavlc_read_levels.level_7_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_7(7) D=cavlc_read_levels.level_7_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_7(6) D=cavlc_read_levels.level_7_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_7(5) D=cavlc_read_levels.level_7_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_7(4) D=cavlc_read_levels.level_7_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_7(3) D=cavlc_read_levels.level_7_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_7(2) D=cavlc_read_levels.level_7_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_7_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_7(1) D=cavlc_read_levels.level_7_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_7_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_7(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I1=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=cavlc_fsm.i(0) I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000111110011
+.subckt LUT4 I0=cavlc_read_levels.level_9(7) I1=cavlc_read_levels.level_8(7) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_9(3) I1=cavlc_read_levels.level_8(3) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I0 I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=cavlc_read_levels.level_13(3) I1=cavlc_read_levels.level_12(3) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I1 I2=cavlc_read_levels.level_14(3) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I2=cavlc_read_levels.level_15(3) I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3 I1=cavlc_read_levels.level_14(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I2 I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=cavlc_read_levels.level_13(4) I1=cavlc_read_levels.level_12(4) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I2=cavlc_read_levels.level_15(4) I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I0 I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=cavlc_read_levels.level_7(4) I1=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I3=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I1=cavlc_read_levels.level_6(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101111110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i(0) I2=cavlc_read_levels.level_4(4) I3=cavlc_read_levels.level_5(4) O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0 I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I1 I2=cavlc_fsm.i(2) I3=cavlc_fsm.i(3) O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.level_2(4) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I2=cavlc_read_levels.level_0(4) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_3(4) I2=cavlc_read_levels.level_1(4) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O I1=cavlc_read_levels.level_9(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_8(4) I2=cavlc_fsm.i_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_levels.level_11(4) I1=cavlc_read_levels.level_10(4) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_11(3) I1=cavlc_read_levels.level_10(3) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I0 I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I1 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I2 I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=cavlc_read_levels.level_5(3) I1=cavlc_read_levels.level_4(3) I2=cavlc_fsm.i(1) I3=cavlc_fsm.i(0) O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010111110011
+.subckt LUT4 I0=cavlc_read_levels.level_7(3) I1=cavlc_read_levels.level_6(3) I2=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_2(3) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I2=cavlc_read_levels.level_0(3) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_3(3) I2=cavlc_read_levels.level_1(3) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I1 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I2 I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cavlc_read_levels.level_11(7) I1=cavlc_read_levels.level_10(7) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_5(7) I1=cavlc_read_levels.level_4(7) I2=cavlc_fsm.i(0) I3=cavlc_read_levels.level_3_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0 I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_2(7) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I2 I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_fsm.i(1) I1=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I2=cavlc_read_levels.level_0(7) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_3(7) I2=cavlc_read_levels.level_1(7) I3=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3 I1=cavlc_read_levels.level_14(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I2 I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=cavlc_read_levels.level_13(7) I1=cavlc_read_levels.level_12(7) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_11_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I2=cavlc_read_levels.level_15(7) I3=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.i(1) O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(3) I3=cavlc_fsm.i(2) O=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O I1=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O I3=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=cavlc_read_levels.level_7_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=TrailingOnes(0) I3=TrailingOnes(1) O=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt ff CQZ=cavlc_read_levels.level_8(8) D=cavlc_read_levels.level_8_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_8(7) D=cavlc_read_levels.level_8_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_8(6) D=cavlc_read_levels.level_8_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_8(5) D=cavlc_read_levels.level_8_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_8(4) D=cavlc_read_levels.level_8_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_8(3) D=cavlc_read_levels.level_8_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_8_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_8(2) D=cavlc_read_levels.level_8_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_8_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_8(1) D=cavlc_read_levels.level_8_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_8_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_8(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_3_O I2=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 O=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffix_sel_LUT4_I0_O I3=cavlc_read_levels.rbsp(2) O=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_7_ff_CQZ_QEN_LUT4_O_I1 I1=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I1 I2=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100001100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=TrailingOnes(1) I3=cavlc_fsm.i(0) O=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel_LUT4_I3_O I2=cavlc_read_levels.level_abs_refresh I3=cavlc_read_levels.level_6_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_fsm.i(0) O=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_levels.level_9(8) D=cavlc_read_levels.level_9_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_9(7) D=cavlc_read_levels.level_9_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O O=cavlc_read_levels.level_9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_9(6) D=cavlc_read_levels.level_9_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt ff CQZ=cavlc_read_levels.level_9(5) D=cavlc_read_levels.level_9_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O O=cavlc_read_levels.level_9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_9(4) D=cavlc_read_levels.level_9_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_9(3) D=cavlc_read_levels.level_9_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_9_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_9(2) D=cavlc_read_levels.level_9_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_9_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_9(1) D=cavlc_read_levels.level_9_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_9_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cavlc_read_levels.level_9(0) D=cavlc_read_levels.level_LUT4_I3_1_O QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:252.1-384.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=cavlc_read_levels.level_1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(1) I3=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_levels.level_9_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp(3) I2=cavlc_read_levels.level_code_tmp(2) I3=cavlc_read_levels.level(0) O=cavlc_read_levels.level_abs_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level(0) O=cavlc_read_levels.level_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp(1) I3=cavlc_read_levels.level_LUT4_O_I3 O=cavlc_read_levels.level(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3 I2=TrailingOnes(0) I3=TrailingOnes(1) O=cavlc_read_levels.level_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt ff CQZ=cavlc_read_levels.level_abs(8) D=cavlc_read_levels.level_abs_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_abs_refresh QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:241.1-247.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_abs(7) D=cavlc_read_levels.level_abs_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_abs_refresh QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:241.1-247.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2 O=cavlc_read_levels.level_abs_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111110110000
+.subckt ff CQZ=cavlc_read_levels.level_abs(6) D=cavlc_read_levels.level_abs_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_abs_refresh QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:241.1-247.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I1 O=cavlc_read_levels.level_abs_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt ff CQZ=cavlc_read_levels.level_abs(5) D=cavlc_read_levels.level_abs_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_abs_refresh QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:241.1-247.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.level_abs_ff_CQZ_3_D_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs_ff_CQZ_5_D_LUT4_O_I3 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_abs_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cavlc_read_levels.level_abs(4) D=cavlc_read_levels.level_abs_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_abs_refresh QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:241.1-247.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O I1=cavlc_read_levels.level_abs_ff_CQZ_5_D_LUT4_O_I3 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O O=cavlc_read_levels.level_abs_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt ff CQZ=cavlc_read_levels.level_abs(3) D=cavlc_read_levels.level_abs_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_abs_refresh QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:241.1-247.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.level_abs_ff_CQZ_5_D_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt ff CQZ=cavlc_read_levels.level_abs(2) D=cavlc_read_levels.level_abs_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_abs_refresh QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:241.1-247.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_levels.level(0) I1=cavlc_read_levels.level_code_tmp(2) I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=cavlc_read_levels.level_15_ff_CQZ_6_D_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111110110000
+.subckt ff CQZ=cavlc_read_levels.level_abs(1) D=cavlc_read_levels.level_abs_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_abs_refresh QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:241.1-247.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_levels.level(0) I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I2=cavlc_read_levels.level_code_tmp(2) I3=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100111100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp(2) I2=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3 I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp(1) I2=cavlc_read_levels.level_code_tmp(0) I3=cavlc_read_levels.level_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111110
+.subckt ff CQZ=cavlc_read_levels.level_abs(0) D=cavlc_read_levels.level(0) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_abs_refresh QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:241.1-247.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_abs_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O I3=cavlc_read_levels.level_abs_ff_CQZ_5_D_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp(8) I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp(6) I1=cavlc_read_levels.level_code_tmp(7) I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp(0) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=cavlc_read_levels.level_code_tmp(6) I3=cavlc_read_levels.level_code_tmp(0) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101111111000000
+.subckt LUT4 I0=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=cavlc_read_levels.level_code_tmp(0) I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=cavlc_read_levels.level_code_tmp(6) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O I3=cavlc_read_levels.t1s_sel_LUT4_I3_O O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp(7) I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cavlc_read_levels.level_LUT4_O_I3 I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_levels.level_code_tmp(1) I3=cavlc_read_levels.level_code_tmp(5) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp(1) I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_levels.level_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I1=cavlc_read_levels.level_code_tmp(0) I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=cavlc_read_levels.level_code_tmp(5) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000001011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp(4) I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=cavlc_read_levels.level_LUT4_O_I3 I2=cavlc_read_levels.level_code_tmp(1) I3=cavlc_read_levels.level_code_tmp(0) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110101000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp(4) I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp(3) I3=cavlc_read_levels.level_code_tmp(2) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_levels.level_code_tmp(8) I3=cavlc_read_levels.level_code_tmp(0) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111110100000
+.subckt LUT4 I0=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_code_tmp(8) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp(7) I2=cavlc_read_levels.level_code_tmp(6) I3=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cavlc_read_levels.level_LUT4_O_I3 I1=cavlc_read_levels.level_code_tmp(1) I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp(5) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=cavlc_read_levels.level_code_tmp(1) I3=cavlc_read_levels.level_LUT4_O_I3 O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp(4) I2=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=cavlc_read_levels.level_code_tmp(0) O=cavlc_read_levels.level_abs_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.t1s_sel_LUT4_I3_O I3=cavlc_read_levels.level_abs_refresh O=cavlc_read_levels.level_15_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.ena I3=cavlc_read_levels.calc_sel O=cavlc_read_levels.level_abs_refresh
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cavlc_read_levels.level_code_tmp(8) D=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(8) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:208.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_code_tmp(7) D=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(7) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:208.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_code_tmp(6) D=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(6) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:208.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_code_tmp(5) D=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(5) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:208.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_code_tmp(4) D=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(4) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:208.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_code_tmp(3) D=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(3) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:208.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_code_tmp(2) D=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(2) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:208.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_code_tmp(1) D=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D(1) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:208.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(0) I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I0 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_levels.level_abs(3) I3=cavlc_read_levels.level_abs(2) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I0 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_levels.level_abs(2) I3=cavlc_read_levels.level_abs(3) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110000010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(2) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(0) O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(2) O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I3 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2_LUT4_O_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=cavlc_read_levels.suffix_sel_LUT4_I0_O I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=cavlc_read_levels.rbsp(2) I1=cavlc_read_levels.suffixLength(1) I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.suffix_sel_LUT4_I0_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I1 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I3 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I2_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I0 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1 I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2_LUT4_I3_I2 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=cavlc_read_levels.level_prefix(0) I1=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1 I3=cavlc_read_levels.suffixLength(2) O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I3 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_2_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001001001101
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_4_I3 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_4_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_3_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_4_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_4_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_4_I1 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I2 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I1 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=cavlc_read_levels.rbsp(6) I1=cavlc_read_levels.suffix_sel_LUT4_I0_O I2=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I2 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I3 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.rbsp(2) I3=cavlc_read_levels.suffix_sel_LUT4_I0_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I2 I3=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=cavlc_read_levels.rbsp(8) I3=cavlc_read_levels.suffix_sel_LUT4_I0_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I0 I1=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I2_LUT4_O_I2 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000001011
+.subckt LUT4 I0=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=cavlc_read_levels.rbsp(9) I3=cavlc_read_levels.suffix_sel_LUT4_I0_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I3 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2_LUT4_O_I1 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=cavlc_read_levels.level_prefix(0) I1=cavlc_read_levels.level_prefix(2) I2=cavlc_read_levels.level_prefix(3) I3=cavlc_read_levels.level_prefix(1) O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=cavlc_read_levels.rbsp(10) I3=cavlc_read_levels.suffix_sel_LUT4_I0_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I3 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2_LUT4_I1_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=cavlc_read_levels.suffixLength(2) I3=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=cavlc_read_levels.level_prefix(0) I1=cavlc_read_levels.level_prefix(1) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(0) O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=cavlc_read_levels.suffixLength(2) O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cavlc_read_levels.level_code_tmp(0) D=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D(0) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:208.1-215.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I1 I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(0) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=cavlc_read_levels.rbsp(3) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.suffix_sel_LUT4_I0_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1 O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001110010101111
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(2) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001000100010
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(0) I1=cavlc_read_levels.level_prefix(3) I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2_LUT4_O_I2 I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1 I2=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1 O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I0 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1 I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(2) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I0 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1 I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(2) O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.level_prefix(1) I3=cavlc_read_levels.level_prefix(0) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.level_prefix(2) I3=cavlc_read_levels.level_prefix(3) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffix_sel_LUT4_I0_O I3=cavlc_read_levels.rbsp(4) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.rbsp(3) I1=cavlc_read_levels.suffix_sel_LUT4_I0_O I2=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_read_levels.suffix_sel_LUT4_I0_O I1=cavlc_read_levels.rbsp(5) I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(11) I1=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=cavlc_read_levels.suffix_sel_LUT4_I0_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101111110000
+.subckt LUT4 I0=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(7) I1=cavlc_read_levels.suffix_sel_LUT4_I0_O I2=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffix_sel_LUT4_I0_O I3=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.rbsp(3) I1=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.rbsp(0) I3=cavlc_read_levels.rbsp(1) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(1) I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.suffixLength(2) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cavlc_read_levels.rbsp(3) I1=cavlc_read_levels.suffix_sel_LUT4_I0_O I2=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=cavlc_read_levels.level_prefix(0) O=cavlc_read_levels.level_code_tmp_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.ena I3=cavlc_read_levels.suffix_sel O=cavlc_read_levels.level_code_tmp_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffix_sel_LUT4_I0_O I2=cavlc_read_levels.level_prefix_comb_LUT4_O_I2 I3=cavlc_read_levels.level_prefix_comb_LUT4_O_I3 O=cavlc_read_levels.level_prefix_comb(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffix_sel_LUT4_I0_O I2=cavlc_read_levels.level_prefix_comb_LUT4_O_I2 I3=cavlc_read_levels.level_prefix_comb_LUT4_O_1_I3 O=cavlc_read_levels.level_prefix_comb(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(9) I1=cavlc_read_levels.rbsp(8) I2=cavlc_read_levels.level_prefix_comb_LUT4_O_1_I3_LUT4_O_I2 I3=cavlc_read_levels.level_prefix_comb_LUT4_O_I3 O=cavlc_read_levels.level_prefix_comb_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffix_sel_LUT4_I0_O I2=cavlc_read_levels.rbsp(10) I3=cavlc_read_levels.rbsp(11) O=cavlc_read_levels.level_prefix_comb_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffix_sel_LUT4_I0_O I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=cavlc_read_levels.level_prefix_comb_LUT4_O_2_I3 O=cavlc_read_levels.level_prefix_comb(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_read_levels.level_prefix_comb_LUT4_O_2_I3_LUT4_O_I0 I1=cavlc_read_levels.level_prefix_comb_LUT4_O_2_I3_LUT4_O_I1 I2=cavlc_read_levels.rbsp(3) I3=cavlc_read_levels.level_8_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=cavlc_read_levels.level_prefix_comb_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(13) I1=cavlc_read_levels.rbsp(12) I2=cavlc_read_levels.level_prefix_comb_LUT4_O_1_I3_LUT4_O_I2 I3=cavlc_read_levels.level_prefix_comb_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_levels.level_prefix_comb_LUT4_O_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(3) I1=cavlc_read_levels.level_prefix_comb_LUT4_O_2_I3_LUT4_O_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_1_I0 I3=len_comb_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 O=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=cavlc_read_levels.rbsp(9) I1=cavlc_read_levels.rbsp(8) I2=cavlc_read_levels.level_prefix_comb_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_2_I3_LUT4_O_I2 O=cavlc_read_levels.level_prefix_comb_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I2=cavlc_read_levels.rbsp(1) I3=cavlc_read_levels.level_prefix_comb_LUT4_O_3_I3 O=cavlc_read_levels.level_prefix_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cavlc_read_levels.level_prefix_comb_LUT4_O_3_I3_LUT4_O_I0 I1=cavlc_read_levels.level_prefix_comb_LUT4_O_3_I3_LUT4_O_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=cavlc_read_levels.rbsp(2) O=cavlc_read_levels.level_prefix_comb_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=cavlc_read_levels.rbsp(13) I1=cavlc_read_levels.rbsp(14) I2=cavlc_read_levels.rbsp(12) I3=cavlc_read_levels.rbsp(11) O=cavlc_read_levels.level_prefix_comb_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_read_levels.rbsp(4) I1=cavlc_read_levels.rbsp(6) I2=cavlc_read_levels.rbsp(8) I3=cavlc_read_levels.rbsp(10) O=cavlc_read_levels.level_prefix_comb_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=cavlc_read_levels.rbsp(3) I3=cavlc_read_levels.rbsp(2) O=cavlc_read_levels.level_prefix_comb_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_levels.level_prefix_comb_LUT4_O_I3 I1=cavlc_read_levels.rbsp(1) I2=cavlc_read_levels.rbsp(2) I3=cavlc_read_levels.rbsp(3) O=cavlc_read_levels.level_prefix_comb_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_levels.level_prefix_comb_LUT4_O_I3_LUT4_I0_O I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=cavlc_read_levels.rbsp(0) O=cavlc_read_levels.level_prefix_comb_LUT4_O_I3_LUT4_I0_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_prefix_comb_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_2_I3_LUT4_O_I2 O=cavlc_read_levels.level_prefix_comb_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.rbsp(7) I3=cavlc_read_levels.rbsp(6) O=cavlc_read_levels.level_prefix_comb_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=cavlc_read_levels.level_prefix(3) D=cavlc_read_levels.level_prefix_comb(3) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_prefix_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:163.1-167.39|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_prefix(2) D=cavlc_read_levels.level_prefix_comb(2) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_prefix_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:163.1-167.39|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_prefix(1) D=cavlc_read_levels.level_prefix_comb(1) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_prefix_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:163.1-167.39|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.level_prefix(0) D=cavlc_read_levels.level_prefix_comb(0) QCK=cavlc_fsm.clk QEN=cavlc_read_levels.level_prefix_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:163.1-167.39|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.ena I3=cavlc_read_levels.prefix_sel O=cavlc_read_levels.level_prefix_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cavlc_read_levels.prefix_sel D=cavlc_read_levels.prefix_sel_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.prefix_sel_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.t1s_sel_ff_CQZ_D_LUT4_O_I3 I3=idle_ff_CQZ_D_LUT4_O_I3 O=cavlc_read_levels.prefix_sel_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt LUT4 I0=idle_LUT4_I1_I0 I1=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O I2=cavlc_read_levels.prefix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O O=cavlc_read_levels.prefix_sel_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=cavlc_fsm.TotalCoeff(4) O=cavlc_read_levels.prefix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cavlc_read_levels.suffixLength(2) D=cavlc_read_levels.suffixLength_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.suffixLength_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:175.1-189.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_levels.suffixLength(1) D=cavlc_read_levels.suffixLength_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.suffixLength_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:175.1-189.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I1 I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt ff CQZ=cavlc_read_levels.suffixLength(0) D=cavlc_read_levels.suffixLength_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_levels.suffixLength_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:156.19-186.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_levels.v:175.1-189.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(0) I1=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I1 I2=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=cavlc_read_levels.suffixLength(2) I3=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_levels.level_abs(6) I1=cavlc_read_levels.level_abs(7) I2=cavlc_read_levels.level_abs(8) I3=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=cavlc_read_levels.level_abs(2) I1=cavlc_read_levels.level_abs(3) I2=cavlc_read_levels.level_abs(4) I3=cavlc_read_levels.level_abs(5) O=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff(4) I2=TrailingOnes(1) I3=TrailingOnes(0) O=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011101110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff(3) I2=cavlc_fsm.TotalCoeff(2) I3=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 I1=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1 I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I0 I1=cavlc_read_levels.suffix_sel_LUT4_I0_O I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000001011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffix_sel_LUT4_I0_O I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I0 O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2 I1=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I0_LUT4_I3_O I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110011001010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.rbsp(2) I3=cavlc_read_levels.rbsp(1) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=cavlc_read_levels.suffix_sel_LUT4_I0_O I1=cavlc_read_levels.rbsp(4) I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=cavlc_read_levels.suffix_sel_LUT4_I0_O I1=cavlc_read_levels.rbsp(3) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(0) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffixLength(2) I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cavlc_read_levels.level_prefix(3) I1=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2 I3=cavlc_read_levels.suffixLength(2) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001110111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2_LUT4_I3_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(2) I2=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(0) I1=cavlc_read_levels.level_prefix(0) I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2_LUT4_O_I2 I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101100001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.level_prefix(1) I3=cavlc_read_levels.level_prefix(2) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=cavlc_read_levels.suffix_sel_LUT4_I0_O I1=cavlc_read_levels.rbsp(5) I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=cavlc_read_levels.level_code_tmp_ff_CQZ_7_D_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=cavlc_read_levels.suffix_sel_LUT4_I0_O I1=cavlc_read_levels.rbsp(5) I2=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(2) I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(0) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=cavlc_fsm.TotalCoeff(2) I2=cavlc_fsm.i(3) I3=cavlc_fsm.TotalCoeff(3) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff(2) I3=cavlc_fsm.i(2) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff(4) I2=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(1) I1=TrailingOnes(1) I2=TrailingOnes(0) I3=cavlc_fsm.TotalCoeff(0) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100100010
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cavlc_fsm.TotalCoeff(1) I2=cavlc_fsm.i(1) I3=TrailingOnes(1) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff(0) I3=TrailingOnes(0) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(4) I1=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TrailingOnes(0) I2=cavlc_fsm.TotalCoeff(0) I3=cavlc_fsm.i(0) O=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_prefix_ff_CQZ_QEN I2=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength_ff_CQZ_D_LUT4_O_I3 I2=cavlc_read_levels.suffixLength(2) I3=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_levels.level_abs(8) I2=cavlc_read_levels.suffixLength(2) I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011101110
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100110011
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(2) I1=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_read_levels.level_abs(0) I1=cavlc_read_levels.level_abs(1) I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001101110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_abs(4) I3=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=cavlc_read_levels.level_abs(7) I1=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs(6) I2=cavlc_read_levels.suffixLength(2) I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(1) I1=cavlc_read_levels.suffixLength(2) I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.level_abs(0) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011101111
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(2) I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.level_abs(1) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_levels.level_abs(4) I2=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffixLength(2) I3=cavlc_read_levels.suffixLength(1) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(1) I1=cavlc_read_levels.suffixLength(2) I2=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_levels.level_abs(6) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=cavlc_read_levels.level_abs(5) I1=cavlc_read_levels.suffixLength(0) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(2) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_abs(7) I2=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffixLength(2) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(0) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111110
+.subckt LUT4 I0=cavlc_read_levels.suffixLength(2) I1=cavlc_read_levels.suffixLength(1) I2=cavlc_read_levels.suffixLength(0) I3=cavlc_read_levels.level_abs(5) O=cavlc_read_levels.suffixLength_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=cavlc_read_levels.suffix_sel I1=cavlc_read_levels.t1s_sel I2=cavlc_read_levels.prefix_sel I3=cavlc_fsm.ena O=cavlc_read_levels.suffix_sel_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffix_sel_LUT4_I0_O I3=cavlc_read_levels.rbsp(0) O=cavlc_read_levels.level_15_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_levels.suffix_sel D=cavlc_read_levels.suffix_sel_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_levels.t1s_sel I1=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O I3=cavlc_read_levels.prefix_sel O=cavlc_read_levels.suffix_sel_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cavlc_read_levels.prefix_sel I1=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_levels.t1s_sel I3=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O O=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1 I3=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I1 O=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_run_befores.clr I3=cavlc_fsm.idle O=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.ena I3=cavlc_read_levels.t1s_sel O=cavlc_read_levels.t1s_sel_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cavlc_read_levels.t1s_sel D=cavlc_read_levels.t1s_sel_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=idle_ff_CQZ_D_LUT4_O_I3 I3=cavlc_read_levels.t1s_sel_ff_CQZ_D_LUT4_O_I3 O=cavlc_read_levels.t1s_sel_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=TrailingOnes_comb(1) I3=TrailingOnes_comb(0) O=cavlc_read_levels.t1s_sel_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=ZeroLeft(3) D=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.ZeroLeft_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:279.1-287.32|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=ZeroLeft(2) D=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.ZeroLeft_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:279.1-287.32|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I2 I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0 I1=len_comb_LUT4_O_3_I1_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100001010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(4) I1=cavlc_read_levels.rbsp(2) I2=cavlc_read_total_zeros.chroma_DC_sel I3=cavlc_read_levels.rbsp(3) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff(1) I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I3_LUT4_O_I2 I2=cavlc_read_levels.rbsp(7) I3=cavlc_read_levels.rbsp(6) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I2 I2=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(4) I1=cavlc_read_levels.rbsp(5) I2=cavlc_read_levels.rbsp(2) I3=cavlc_read_levels.rbsp(3) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O I3=cavlc_read_total_zeros.chroma_DC_sel O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=ZeroLeft(2) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt ff CQZ=ZeroLeft(1) D=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.ZeroLeft_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:279.1-287.32|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I2 I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111111111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_3_I1_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(1) I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I2 I1=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I0 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=cavlc_read_levels.rbsp(2) I1=cavlc_read_levels.rbsp(4) I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110000000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(3) I1=cavlc_fsm.TotalCoeff(1) I2=cavlc_fsm.TotalCoeff(2) I3=cavlc_fsm.TotalCoeff(0) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=len_comb_LUT4_O_3_I1_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011111111
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111101101010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(0) I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I2=cavlc_fsm.TotalCoeff(1) I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I2 I2=cavlc_fsm.TotalCoeff(1) I3=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(0) I1=len_comb_LUT4_O_2_I3_LUT4_O_I0 I2=cavlc_read_levels.rbsp(1) I3=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I2=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1 I3=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I0 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I2 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(4) I1=cavlc_read_levels.rbsp(5) I2=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I1 I3=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(0) I1=cavlc_read_levels.rbsp(2) I2=cavlc_read_levels.rbsp(1) I3=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt ff CQZ=ZeroLeft(0) D=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.ZeroLeft_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:279.1-287.32|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_zeros.chroma_DC_sel O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=len_comb_LUT4_O_3_I1_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110011111111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=cavlc_read_levels.rbsp(2) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I2=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.rbsp(1) I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=cavlc_read_levels.rbsp(4) I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff(1) I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I0 I1=cavlc_read_levels.rbsp(0) I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff(0) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=cavlc_fsm.TotalCoeff(0) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011101000000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(2) I1=cavlc_read_levels.rbsp(4) I2=cavlc_read_total_zeros.chroma_DC_sel I3=cavlc_read_levels.rbsp(3) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011110001
+.subckt LUT4 I0=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I2 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(1) I1=cavlc_read_levels.rbsp(2) I2=cavlc_fsm.TotalCoeff(1) I3=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I2=len_comb_LUT4_O_3_I1_LUT4_O_I1 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111111010
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I1=cavlc_read_levels.rbsp(2) I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=cavlc_read_levels.rbsp(4) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=cavlc_read_levels.rbsp(5) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I0 I3=cavlc_read_levels.rbsp(5) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001110111
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I2=cavlc_read_levels.rbsp(0) I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=cavlc_read_levels.rbsp(4) I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011001100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000011
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=len_comb_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.rbsp(2) I2=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=cavlc_read_levels.rbsp(1) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1 I2=ZeroLeft(0) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1 I3=ZeroLeft(0) O=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=ZeroLeft(2) I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001001001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=ZeroLeft(1) I2=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O I3=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.level_prefix_comb_LUT4_O_I3_LUT4_I0_O_LUT4_I1_O I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(2) I1=cavlc_read_levels.rbsp(0) I2=cavlc_read_levels.rbsp(1) I3=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001110000000011
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_levels.level_prefix_comb_LUT4_O_I2 I2=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3 I3=ZeroLeft(3) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000010111111
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=len_comb_LUT4_O_3_I1_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000011101110
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=cavlc_read_levels.rbsp(1) I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=cavlc_read_levels.rbsp(5) I3=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I0 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011001100001011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_zeros.chroma_DC_sel I2=cavlc_read_levels.rbsp(3) I3=cavlc_read_levels.rbsp(4) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.rbsp(2) I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff(1) I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I3_LUT4_O_I0 I2=cavlc_read_levels.rbsp(5) I3=cavlc_read_levels.rbsp(4) O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I2 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I3=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(3) I1=cavlc_fsm.TotalCoeff(2) I2=cavlc_read_run_befores.ZeroLeft_init I3=cavlc_fsm.ena O=len_comb_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_3_I2 I3=cavlc_read_run_befores.ZeroLeft_init O=len_comb_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.ena I3=cavlc_read_run_befores.ZeroLeft_init O=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cavlc_read_run_befores.ZeroLeft_init D=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2 I3=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O O=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(4) I1=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O O=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(1) I1=TrailingOnes(1) I2=cavlc_fsm.TotalCoeff(0) I3=TrailingOnes(0) O=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(4) I1=cavlc_fsm.max_coeff_num(4) I2=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=idle_LUT4_I1_I0 O=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=cavlc_fsm.max_coeff_num(3) I2=cavlc_fsm.TotalCoeff(3) I3=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff(2) I2=cavlc_fsm.max_coeff_num(2) I3=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(1) I1=cavlc_fsm.TotalCoeff(0) I2=cavlc_fsm.max_coeff_num(1) I3=cavlc_fsm.max_coeff_num(0) O=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.max_coeff_num(4) I3=cavlc_fsm.TotalCoeff(4) O=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=cavlc_read_run_befores.clr O=cavlc_read_run_befores.clr_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=cavlc_read_run_befores.clr O=cavlc_read_run_befores.clr_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.ena I3=cavlc_read_run_befores.clr O=cavlc_read_run_befores.clr_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cavlc_read_run_befores.clr D=cavlc_read_run_befores.clr_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.start I2=idle_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I3=idle_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cavlc_read_run_befores.clr_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cavlc_read_run_befores.coeff_0(8) D=cavlc_read_run_befores.coeff_0_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_0(7) D=cavlc_read_run_befores.coeff_0_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0(7) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_0(6) D=cavlc_read_run_befores.coeff_0_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0(6) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_0(5) D=cavlc_read_run_befores.coeff_0_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0(5) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_0(4) D=cavlc_read_run_befores.coeff_0_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0(4) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_0(3) D=cavlc_read_run_befores.coeff_0_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0(3) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_0(2) D=cavlc_read_run_befores.coeff_0_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0(2) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_0(1) D=cavlc_read_run_befores.coeff_0_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0(1) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_0(0) D=cavlc_read_run_befores.coeff_0_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0(0) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_0(8) I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_1_O O=cavlc_read_run_befores.coeff_0_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=cavlc_read_run_befores.coeff_10(8) D=cavlc_read_run_befores.coeff_10_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_10(7) D=cavlc_read_run_befores.coeff_10_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_10(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_10(6) D=cavlc_read_run_befores.coeff_10_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_10(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_10(5) D=cavlc_read_run_befores.coeff_10_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_10(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_10(4) D=cavlc_read_run_befores.coeff_10_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_10(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_10(3) D=cavlc_read_run_befores.coeff_10_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_10(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_10_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_10(2) D=cavlc_read_run_befores.coeff_10_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_10(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_10_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_10(1) D=cavlc_read_run_befores.coeff_10_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_10(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_10_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_10(0) D=cavlc_read_run_befores.coeff_10_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_10(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_10_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_10(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_11(8) D=cavlc_read_run_befores.coeff_11_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_11(7) D=cavlc_read_run_befores.coeff_11_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_11(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_11_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_11(6) D=cavlc_read_run_befores.coeff_11_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_11(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_11_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_11(5) D=cavlc_read_run_befores.coeff_11_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_11(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_11_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_11(4) D=cavlc_read_run_befores.coeff_11_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_11(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_11_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_11(3) D=cavlc_read_run_befores.coeff_11_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_11(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_11_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_11(2) D=cavlc_read_run_befores.coeff_11_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_11(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_11_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_11(1) D=cavlc_read_run_befores.coeff_11_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_11(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_11_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_11(0) D=cavlc_read_run_befores.coeff_11_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_11(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_11_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_11(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_11_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_12(8) D=cavlc_read_run_befores.coeff_12_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_12(7) D=cavlc_read_run_befores.coeff_12_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_12(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_12(6) D=cavlc_read_run_befores.coeff_12_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_12(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_12(5) D=cavlc_read_run_befores.coeff_12_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_12(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_12(4) D=cavlc_read_run_befores.coeff_12_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_12(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_12(3) D=cavlc_read_run_befores.coeff_12_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_12(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_12(2) D=cavlc_read_run_befores.coeff_12_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_12(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_12(1) D=cavlc_read_run_befores.coeff_12_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_12(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_12(0) D=cavlc_read_run_befores.coeff_12_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_12(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_12(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I2=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=cavlc_read_run_befores.clr_LUT4_I3_O O=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i(2) I3=cavlc_fsm.i(3) O=cavlc_read_run_befores.coeff_12_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cavlc_read_run_befores.coeff_13(8) D=cavlc_read_run_befores.coeff_13_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_13(7) D=cavlc_read_run_befores.coeff_13_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_13(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_13_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_13(6) D=cavlc_read_run_befores.coeff_13_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_13(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_13_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_13(5) D=cavlc_read_run_befores.coeff_13_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_13(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_13_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_13(4) D=cavlc_read_run_befores.coeff_13_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_13(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_13_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_13(3) D=cavlc_read_run_befores.coeff_13_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_13(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_13_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_13(2) D=cavlc_read_run_befores.coeff_13_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_13(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_13_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_13(1) D=cavlc_read_run_befores.coeff_13_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_13(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_13_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_13(0) D=cavlc_read_run_befores.coeff_13_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_13(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_13_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_13(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_13_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_14(8) D=cavlc_read_run_befores.coeff_14_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_14(7) D=cavlc_read_run_befores.coeff_14_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_14(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_14(6) D=cavlc_read_run_befores.coeff_14_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_14(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_14(5) D=cavlc_read_run_befores.coeff_14_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_14(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_14(4) D=cavlc_read_run_befores.coeff_14_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_14(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_14(3) D=cavlc_read_run_befores.coeff_14_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_14(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_14(2) D=cavlc_read_run_befores.coeff_14_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_14(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_14(1) D=cavlc_read_run_befores.coeff_14_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_14(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_14(0) D=cavlc_read_run_befores.coeff_14_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_14(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_14(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I2=cavlc_read_levels.level_13_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_run_befores.clr_LUT4_I3_O O=cavlc_read_run_befores.coeff_14_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt ff CQZ=cavlc_read_run_befores.coeff_15(8) D=cavlc_read_run_befores.coeff_15_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_15(7) D=cavlc_read_run_befores.coeff_15_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_15(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_15(6) D=cavlc_read_run_befores.coeff_15_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_15(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_15(5) D=cavlc_read_run_befores.coeff_15_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_15(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_15(4) D=cavlc_read_run_befores.coeff_15_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_15(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_15(3) D=cavlc_read_run_befores.coeff_15_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_15(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_15(2) D=cavlc_read_run_befores.coeff_15_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_15(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_15(1) D=cavlc_read_run_befores.coeff_15_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_15(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_15(0) D=cavlc_read_run_befores.coeff_15_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_15(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_15(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_2_I1 I2=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN_LUT4_O_I2 I3=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.clr_LUT4_I3_1_O I2=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I0 I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_I1 O=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I2=cavlc_read_levels.level_14_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_run_befores.clr_LUT4_I3_O O=cavlc_read_run_befores.coeff_15_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt ff CQZ=cavlc_read_run_befores.coeff_1(8) D=cavlc_read_run_befores.coeff_1_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_1(7) D=cavlc_read_run_befores.coeff_1_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_1(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_1(6) D=cavlc_read_run_befores.coeff_1_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_1(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_1(5) D=cavlc_read_run_befores.coeff_1_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_1(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_1(4) D=cavlc_read_run_befores.coeff_1_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_1(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_1(3) D=cavlc_read_run_befores.coeff_1_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_1(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_1_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_1(2) D=cavlc_read_run_befores.coeff_1_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_1(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_1_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_1(1) D=cavlc_read_run_befores.coeff_1_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_1(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_1_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_1(0) D=cavlc_read_run_befores.coeff_1_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_1(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_1_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_1(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_2(8) D=cavlc_read_run_befores.coeff_2_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_2(7) D=cavlc_read_run_befores.coeff_2_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_2(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_2(6) D=cavlc_read_run_befores.coeff_2_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_2(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_2(5) D=cavlc_read_run_befores.coeff_2_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_2(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_2(4) D=cavlc_read_run_befores.coeff_2_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_2(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_2(3) D=cavlc_read_run_befores.coeff_2_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_2(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_2(2) D=cavlc_read_run_befores.coeff_2_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_2(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_2(1) D=cavlc_read_run_befores.coeff_2_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_2(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_2(0) D=cavlc_read_run_befores.coeff_2_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_2(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_2(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN_LUT4_O_I3 I2=cavlc_fsm.i(1) I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O O=cavlc_read_run_befores.coeff_2_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt ff CQZ=cavlc_read_run_befores.coeff_3(8) D=cavlc_read_run_befores.coeff_3_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_3(7) D=cavlc_read_run_befores.coeff_3_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_3(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_3(6) D=cavlc_read_run_befores.coeff_3_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_3(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_3(5) D=cavlc_read_run_befores.coeff_3_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_3(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_3(4) D=cavlc_read_run_befores.coeff_3_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_3(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_3(3) D=cavlc_read_run_befores.coeff_3_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_3(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_3(2) D=cavlc_read_run_befores.coeff_3_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_3(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_3(1) D=cavlc_read_run_befores.coeff_3_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_3(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_3(0) D=cavlc_read_run_befores.coeff_3_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_3(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_3(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN_LUT4_O_I3 I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O O=cavlc_read_run_befores.coeff_3_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt ff CQZ=cavlc_read_run_befores.coeff_4(8) D=cavlc_read_run_befores.coeff_4_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_4(7) D=cavlc_read_run_befores.coeff_4_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_4(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_4(6) D=cavlc_read_run_befores.coeff_4_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_4(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_4(5) D=cavlc_read_run_befores.coeff_4_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_4(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_4(4) D=cavlc_read_run_befores.coeff_4_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_4(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_4(3) D=cavlc_read_run_befores.coeff_4_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_4(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_4(2) D=cavlc_read_run_befores.coeff_4_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_4(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_4(1) D=cavlc_read_run_befores.coeff_4_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_4(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_4(0) D=cavlc_read_run_befores.coeff_4_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_4(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_4(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I2=cavlc_read_levels.level_1_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 I3=cavlc_read_run_befores.clr_LUT4_I3_O O=cavlc_read_run_befores.coeff_4_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt ff CQZ=cavlc_read_run_befores.coeff_5(8) D=cavlc_read_run_befores.coeff_5_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_5(7) D=cavlc_read_run_befores.coeff_5_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_5(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_5(6) D=cavlc_read_run_befores.coeff_5_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_5(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_5(5) D=cavlc_read_run_befores.coeff_5_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_5(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_5(4) D=cavlc_read_run_befores.coeff_5_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_5(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_5(3) D=cavlc_read_run_befores.coeff_5_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_5(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_5_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_5(2) D=cavlc_read_run_befores.coeff_5_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_5(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_5_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_5(1) D=cavlc_read_run_befores.coeff_5_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_5(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_5_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_5(0) D=cavlc_read_run_befores.coeff_5_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_5(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_5_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_5(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_6(8) D=cavlc_read_run_befores.coeff_6_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_6(7) D=cavlc_read_run_befores.coeff_6_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_6(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_6(6) D=cavlc_read_run_befores.coeff_6_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_6(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_6(5) D=cavlc_read_run_befores.coeff_6_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_6(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_6(4) D=cavlc_read_run_befores.coeff_6_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_6(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_6(3) D=cavlc_read_run_befores.coeff_6_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_6(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_6_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_6(2) D=cavlc_read_run_befores.coeff_6_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_6(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_6_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_6(1) D=cavlc_read_run_befores.coeff_6_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_6(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_6_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_6(0) D=cavlc_read_run_befores.coeff_6_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_6(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_6_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_6(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_1_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O I1=cavlc_fsm.i(2) I2=cavlc_fsm.i(1) I3=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I3 O=cavlc_read_run_befores.coeff_6_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt ff CQZ=cavlc_read_run_befores.coeff_7(8) D=cavlc_read_run_befores.coeff_7_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_7(7) D=cavlc_read_run_befores.coeff_7_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_7(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_7(6) D=cavlc_read_run_befores.coeff_7_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_7(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_7(5) D=cavlc_read_run_befores.coeff_7_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_7(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_7(4) D=cavlc_read_run_befores.coeff_7_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_7(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_7(3) D=cavlc_read_run_befores.coeff_7_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_7(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_7(2) D=cavlc_read_run_befores.coeff_7_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_7(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_7(1) D=cavlc_read_run_befores.coeff_7_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_7(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_7(0) D=cavlc_read_run_befores.coeff_7_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_7(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_7(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_2_I0 I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I0_LUT4_I0_1_I1 I2=cavlc_read_run_befores.clr_LUT4_I3_1_O I3=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3 O=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_I3 I2=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O O=cavlc_read_run_befores.coeff_7_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt ff CQZ=cavlc_read_run_befores.coeff_8(8) D=cavlc_read_run_befores.coeff_8_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_8(7) D=cavlc_read_run_befores.coeff_8_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_8(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_8(6) D=cavlc_read_run_befores.coeff_8_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_8(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_8(5) D=cavlc_read_run_befores.coeff_8_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_8(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_8(4) D=cavlc_read_run_befores.coeff_8_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_8(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_8(3) D=cavlc_read_run_befores.coeff_8_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_8(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_8_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_8(2) D=cavlc_read_run_befores.coeff_8_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_8(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_8_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_8(1) D=cavlc_read_run_befores.coeff_8_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_8(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_8_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_8(0) D=cavlc_read_run_befores.coeff_8_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_I1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_8(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_8_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_8(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_9(8) D=cavlc_read_run_befores.coeff_9_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_run_befores.coeff_9(7) D=cavlc_read_run_befores.coeff_9_ff_CQZ_1_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_9(7) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_9(6) D=cavlc_read_run_befores.coeff_9_ff_CQZ_2_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_9(6) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_9(5) D=cavlc_read_run_befores.coeff_9_ff_CQZ_3_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_9(5) I2=cavlc_read_levels.level_10_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_9(4) D=cavlc_read_run_befores.coeff_9_ff_CQZ_4_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_9(4) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_9(3) D=cavlc_read_run_befores.coeff_9_ff_CQZ_5_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_9(3) I2=cavlc_read_levels.level_7_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O_LUT4_I2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_9_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_9(2) D=cavlc_read_run_befores.coeff_9_ff_CQZ_6_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_9(2) I2=cavlc_read_levels.level_4_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_2_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_9_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_9(1) D=cavlc_read_run_befores.coeff_9_ff_CQZ_7_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_9(1) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_9_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=cavlc_read_run_befores.coeff_9(0) D=cavlc_read_run_befores.coeff_9_ff_CQZ_8_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:210.24-257.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_run_befores.v:318.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_9(0) I2=cavlc_read_levels.level_12_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_9_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=cavlc_read_levels.level_9(8) I2=cavlc_read_levels.level_5_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I2_O I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=cavlc_read_run_befores.coeff_9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.ena I3=cavlc_read_run_befores.sel O=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cavlc_read_run_befores.sel D=cavlc_read_run_befores.sel_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I0 I1=idle_LUT4_I1_I0 I2=idle_ff_CQZ_D_LUT4_O_I1 I3=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3 O=cavlc_read_run_befores.sel_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100010001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O I3=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I2 O=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3 I3=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O O=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.i_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3_LUT4_I1_O O=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=cavlc_fsm.TotalCoeff(4) D=TotalCoeff_comb(4) QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.clr_LUT4_I3_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:1186.1-1194.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_fsm.TotalCoeff(3) D=TotalCoeff_comb(3) QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.clr_LUT4_I3_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:1186.1-1194.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_fsm.TotalCoeff(2) D=TotalCoeff_comb(2) QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.clr_LUT4_I3_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:1186.1-1194.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_fsm.TotalCoeff(1) D=TotalCoeff_comb(1) QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.clr_LUT4_I3_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:1186.1-1194.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_fsm.TotalCoeff(0) D=TotalCoeff_comb(0) QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.clr_LUT4_I3_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:1186.1-1194.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=TrailingOnes(1) D=TrailingOnes_comb(1) QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.clr_LUT4_I3_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:1186.1-1194.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=TrailingOnes(0) D=TrailingOnes_comb(0) QCK=cavlc_fsm.clk QEN=cavlc_read_run_befores.clr_LUT4_I3_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:1186.1-1194.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(0) D=cavlc_read_levels.rbsp(0) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(1) D=cavlc_read_levels.rbsp(1) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(10) D=cavlc_read_levels.rbsp(10) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(11) D=cavlc_read_levels.rbsp(11) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(12) D=cavlc_read_levels.rbsp(12) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(13) D=cavlc_read_levels.rbsp(13) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(14) D=cavlc_read_levels.rbsp(14) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(15) D=cavlc_read_levels.rbsp(15) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(2) D=cavlc_read_levels.rbsp(2) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(3) D=cavlc_read_levels.rbsp(3) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(4) D=cavlc_read_levels.rbsp(4) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(5) D=cavlc_read_levels.rbsp(5) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(6) D=cavlc_read_levels.rbsp(6) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(7) D=cavlc_read_levels.rbsp(7) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(8) D=cavlc_read_levels.rbsp(8) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_1(9) D=cavlc_read_levels.rbsp(9) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(0) D=cavlc_read_levels.rbsp(0) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(1) D=cavlc_read_levels.rbsp(1) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(10) D=cavlc_read_levels.rbsp(10) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(11) D=cavlc_read_levels.rbsp(11) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(12) D=cavlc_read_levels.rbsp(12) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(13) D=cavlc_read_levels.rbsp(13) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(2) D=cavlc_read_levels.rbsp(2) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(3) D=cavlc_read_levels.rbsp(3) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(4) D=cavlc_read_levels.rbsp(4) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(5) D=cavlc_read_levels.rbsp(5) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(6) D=cavlc_read_levels.rbsp(6) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(7) D=cavlc_read_levels.rbsp(7) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(8) D=cavlc_read_levels.rbsp(8) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_2(9) D=cavlc_read_levels.rbsp(9) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_1_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(0) D=cavlc_read_levels.rbsp(0) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(1) D=cavlc_read_levels.rbsp(1) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(2) D=cavlc_read_levels.rbsp(2) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(3) D=cavlc_read_levels.rbsp(3) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(4) D=cavlc_read_levels.rbsp(4) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(5) D=cavlc_read_levels.rbsp(5) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(6) D=cavlc_read_levels.rbsp(6) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(7) D=cavlc_read_levels.rbsp(7) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(8) D=cavlc_read_levels.rbsp(8) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_3(9) D=cavlc_read_levels.rbsp(9) QCK=cavlc_fsm.clk QEN=start_LUT4_I1_O_LUT4_I2_2_O QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_4(0) D=cavlc_read_levels.rbsp(0) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_4(1) D=cavlc_read_levels.rbsp(1) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_4(2) D=cavlc_read_levels.rbsp(2) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_4(3) D=cavlc_read_levels.rbsp(3) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_4(4) D=cavlc_read_levels.rbsp(4) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_4(5) D=cavlc_read_levels.rbsp(5) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_4_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=start_LUT4_I1_O I3=start_LUT4_I1_O_LUT4_I2_2_I3 O=cavlc_read_total_coeffs.rbsp_4_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_5(0) D=cavlc_read_levels.rbsp(0) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_5(1) D=cavlc_read_levels.rbsp(1) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_5(2) D=cavlc_read_levels.rbsp(2) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_5(3) D=cavlc_read_levels.rbsp(3) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_5(4) D=cavlc_read_levels.rbsp(4) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_5(5) D=cavlc_read_levels.rbsp(5) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_5(6) D=cavlc_read_levels.rbsp(6) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=cavlc_read_total_coeffs.rbsp_5(7) D=cavlc_read_levels.rbsp(7) QCK=cavlc_fsm.clk QEN=cavlc_read_total_coeffs.rbsp_5_ff_CQZ_QEN QRT=rst_n_LUT4_I3_O QST=TotalZeros_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:114.25-131.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_read_total_coeffs.v:128.1-150.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=idle_LUT4_I1_I0 I1=cavlc_fsm.idle I2=cavlc_read_levels.calc_sel I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3 O=len_comb_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.calc_sel I2=cavlc_read_run_befores.sel I3=cavlc_fsm.idle O=len_comb_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt ff CQZ=cavlc_fsm.idle D=idle_ff_CQZ_D QCK=cavlc_fsm.clk QEN=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_O QRT=TotalZeros_comb(0) QST=rst_n_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_top.v:276.11-292.2|/home/tpagarani/git/yosys-testing/Designs/cavlc_top/rtl/cavlc_fsm.v:89.1-157.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:136.8-136.82"
+.subckt LUT4 I0=TotalZeros_comb(0) I1=idle_ff_CQZ_D_LUT4_O_I1 I2=idle_ff_CQZ_D_LUT4_O_I2 I3=idle_ff_CQZ_D_LUT4_O_I3 O=idle_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=idle_ff_CQZ_D_LUT4_O_I1 I2=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I3 I3=cavlc_read_run_befores.sel_ff_CQZ_D_LUT4_O_I0 O=idle_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_init_ff_CQZ_D_LUT4_O_I1 I1=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_I0_I2 I2=idle_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O I3=cavlc_fsm.ena O=idle_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I2_I3_LUT4_I1_O I2=idle_LUT4_I1_I0 I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=idle_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3 I3=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I2=ZeroLeft(0) I3=ZeroLeft(1) O=idle_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=idle_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.start I3=idle_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=idle_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.calc_sel_ff_CQZ_D_LUT4_I3_O I3=cavlc_read_levels.suffix_sel_ff_CQZ_D_LUT4_O_I1_LUT4_I1_O O=idle_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalCoeff_comb(0) I1=TotalCoeff_comb(1) I2=idle_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=idle_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=idle_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalCoeff_comb(4) I2=TotalCoeff_comb(3) I3=TotalCoeff_comb(2) O=idle_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=len_comb_LUT4_O_I0 I1=len_comb_LUT4_O_I1 I2=len_comb_LUT4_O_I2 I3=len_comb_LUT4_O_I3 O=cavlc_len_gen.len_comb(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I1 I2=len_comb_LUT4_O_1_I2 I3=len_comb_LUT4_O_1_I3 O=cavlc_len_gen.len_comb(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=len_comb_LUT4_O_1_I2_LUT4_O_I0 I1=len_comb_LUT4_O_1_I2_LUT4_O_I1 I2=len_comb_LUT4_O_1_I2_LUT4_O_I2 I3=len_comb_LUT4_O_2_I0_LUT4_O_I3 O=len_comb_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I1_O I2=len_comb_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_1(9) O=len_comb_LUT4_O_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(13) I1=cavlc_read_total_coeffs.rbsp_1(12) I2=cavlc_read_total_coeffs.rbsp_1(11) I3=cavlc_read_total_coeffs.rbsp_1(10) O=len_comb_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=start_LUT4_I1_O_LUT4_I2_2_I3 I3=cavlc_read_total_coeffs.nC(2) O=len_comb_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I1 O=len_comb_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(1) I1=cavlc_read_total_coeffs.rbsp_1(2) I2=cavlc_read_total_coeffs.rbsp_1(3) I3=cavlc_read_total_coeffs.rbsp_1(4) O=len_comb_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cavlc_read_levels.t1s_sel I1=cavlc_read_levels.level_prefix_comb(3) I2=len_comb_LUT4_O_1_I3_LUT4_O_I2 I3=cavlc_read_levels.prefix_sel O=len_comb_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cavlc_read_levels.level_prefix_comb_LUT4_O_1_I3 I1=cavlc_read_levels.rbsp(3) I2=cavlc_read_levels.level_prefix_comb(1) I3=cavlc_read_levels.level_prefix_comb(0) O=len_comb_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=len_comb_LUT4_O_2_I0 I1=len_comb_LUT4_O_2_I1 I2=len_comb_LUT4_O_2_I2 I3=len_comb_LUT4_O_2_I3 O=cavlc_len_gen.len_comb(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111110100
+.subckt LUT4 I0=len_comb_LUT4_O_2_I0_LUT4_O_I0 I1=cavlc_read_levels.t1s_sel I2=len_comb_LUT4_O_2_I0_LUT4_O_I2 I3=len_comb_LUT4_O_2_I0_LUT4_O_I3 O=len_comb_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000011101110
+.subckt LUT4 I0=cavlc_read_levels.prefix_sel I1=cavlc_read_levels.level_prefix_comb(3) I2=len_comb_LUT4_O_1_I3_LUT4_O_I2 I3=len_comb_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.suffix_sel I2=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=cavlc_read_levels.prefix_sel O=len_comb_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(0) I1=len_comb_LUT4_O_2_I0_LUT4_O_I2 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 I3=len_comb_LUT4_O_2_I0_LUT4_O_I3 O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0 I1=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I3_LUT4_O_I3 I2=cavlc_read_total_coeffs.rbsp_5(2) I3=cavlc_read_total_coeffs.rbsp_5(1) O=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(4) I1=cavlc_read_total_coeffs.rbsp_5(5) I2=cavlc_read_total_coeffs.rbsp_5(3) I3=cavlc_read_total_coeffs.rbsp_5(6) O=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(2) I1=cavlc_read_total_coeffs.rbsp_3(3) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I1 I3=start_LUT4_I1_O_LUT4_I2_2_I3 O=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(4) I1=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_1_I2_LUT4_O_I1 O=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I2=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=cavlc_read_total_coeffs.rbsp_2(1) O=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(9) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I1_O I2=len_comb_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_1_I2_LUT4_O_I2 O=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.valid_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I1 I3=cavlc_read_levels.suffix_sel O=len_comb_LUT4_O_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I0 I1=len_comb_LUT4_O_3_I3_LUT4_O_I3 I2=len_comb_LUT4_O_I3_LUT4_O_I3 I3=len_comb_LUT4_O_3_I3_LUT4_O_I1 O=len_comb_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=len_comb_LUT4_O_2_I3_LUT4_O_I0 I1=len_comb_LUT4_O_2_I3_LUT4_O_I1 I2=len_comb_LUT4_O_2_I3_LUT4_O_I2 I3=len_comb_LUT4_O_3_I2 O=len_comb_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.rbsp(3) I3=cavlc_read_levels.rbsp(2) O=len_comb_LUT4_O_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I0 I1=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1 I2=len_comb_LUT4_O_2_I3_LUT4_O_I1 I3=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I3 O=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 I3=cavlc_read_levels.rbsp(2) O=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I2=cavlc_read_levels.rbsp(6) I3=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3 O=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3 I1=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I1 I2=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I2 I3=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I0 I2=cavlc_read_levels.rbsp(4) I3=cavlc_read_levels.rbsp(3) O=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(2) I1=cavlc_read_levels.rbsp(3) I2=cavlc_read_levels.rbsp(1) I3=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 O=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(3) I1=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_1_I0 I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 O=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I1_I0 I1=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3 I2=cavlc_read_levels.rbsp(4) I3=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I0_I1 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011111111
+.subckt LUT4 I0=cavlc_read_levels.rbsp(8) I1=cavlc_read_levels.rbsp(5) I2=cavlc_read_levels.rbsp(7) I3=cavlc_read_levels.rbsp(6) O=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001111011100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=cavlc_read_levels.rbsp(5) O=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O O=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=cavlc_fsm.TotalCoeff(1) O=len_comb_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.rbsp(5) I3=cavlc_read_levels.rbsp(4) O=len_comb_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=len_comb_LUT4_O_3_I0 I1=len_comb_LUT4_O_3_I1 I2=len_comb_LUT4_O_3_I2 I3=len_comb_LUT4_O_3_I3 O=cavlc_len_gen.len_comb(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110110000
+.subckt LUT4 I0=cavlc_read_levels.t1s_sel I1=len_comb_LUT4_O_3_I0_LUT4_O_I1 I2=len_comb_LUT4_O_3_I0_LUT4_O_I2 I3=cavlc_read_run_befores.ZeroLeft_init O=len_comb_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=cavlc_read_levels.prefix_sel I1=cavlc_read_levels.level_prefix_comb(2) I2=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.level_prefix_comb(0) I3=cavlc_read_levels.level_prefix_comb(1) O=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_levels.suffixLength(2) I2=cavlc_read_levels.prefix_sel I3=cavlc_read_levels.suffix_sel O=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.level_prefix(0) I3=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.level_prefix(1) I2=cavlc_read_levels.level_prefix(2) I3=cavlc_read_levels.level_prefix(3) O=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.suffixLength(1) I3=cavlc_read_levels.suffixLength(0) O=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1 I1=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0 I2=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_2_I0_LUT4_O_I3 O=len_comb_LUT4_O_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 O=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(2) I3=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(4) I2=cavlc_read_total_coeffs.rbsp_1(3) I3=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TrailingOnes_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I1_O I2=cavlc_read_total_coeffs.rbsp_1(9) I3=len_comb_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 O=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_1_I2_LUT4_O_I1 I2=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(2) I1=cavlc_read_total_coeffs.rbsp_2(1) I2=cavlc_read_total_coeffs.rbsp_2(0) I3=cavlc_read_total_coeffs.nC(1) O=len_comb_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=len_comb_LUT4_O_3_I1_LUT4_O_I0 I1=len_comb_LUT4_O_3_I1_LUT4_O_I1 I2=len_comb_LUT4_O_3_I1_LUT4_O_I2 I3=len_comb_LUT4_O_3_I1_LUT4_O_I3 O=len_comb_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I1 I2=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I0 I1=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I2 I2=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3 I3=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I1 O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=cavlc_read_levels.rbsp(4) O=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I2=cavlc_read_levels.rbsp(2) I3=cavlc_read_levels.rbsp(1) O=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=cavlc_read_run_befores.ZeroLeft_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff(3) I2=cavlc_fsm.TotalCoeff(1) I3=cavlc_fsm.TotalCoeff(2) O=len_comb_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I3_LUT4_O_I1 I2=len_comb_LUT4_O_2_I3_LUT4_O_I2 I3=len_comb_LUT4_O_2_I3_LUT4_O_I0 O=len_comb_LUT4_O_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I2 I1=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1 I2=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff(1) O=len_comb_LUT4_O_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1 I3=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I1=cavlc_read_levels.rbsp(2) I2=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I2 I3=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011100001111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_3_I1_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff(2) I3=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff(0) I3=cavlc_fsm.TotalCoeff(1) O=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_read_levels.rbsp(1) I1=cavlc_read_levels.rbsp(2) I2=cavlc_read_levels.rbsp(0) I3=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 O=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I0 I1=len_comb_LUT4_O_3_I3_LUT4_O_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I3 I3=len_comb_LUT4_O_3_I3_LUT4_O_I3 O=len_comb_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(3) I1=cavlc_read_levels.rbsp(4) I2=cavlc_read_levels.rbsp(5) I3=cavlc_read_levels.rbsp(6) O=len_comb_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=cavlc_read_levels.rbsp(2) O=len_comb_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=len_comb_LUT4_O_4_I0 I1=len_comb_LUT4_O_2_I1 I2=len_comb_LUT4_O_4_I2 I3=len_comb_LUT4_O_4_I3 O=cavlc_len_gen.len_comb(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111110100
+.subckt LUT4 I0=len_comb_LUT4_O_4_I0_LUT4_O_I0 I1=TrailingOnes(1) I2=len_comb_LUT4_O_4_I0_LUT4_O_I2 I3=cavlc_read_levels.t1s_sel O=len_comb_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100001010
+.subckt LUT4 I0=cavlc_read_levels.prefix_sel I1=cavlc_read_levels.level_prefix_comb(0) I2=cavlc_read_levels.level_prefix_comb(1) I3=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_levels.prefix_sel I2=cavlc_read_levels.suffix_sel I3=cavlc_read_levels.suffixLength(1) O=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cavlc_read_levels.level_prefix(3) I1=cavlc_read_levels.level_prefix(2) I2=cavlc_read_levels.level_prefix(0) I3=cavlc_read_levels.level_prefix(1) O=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I0 I1=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1 I2=start_LUT4_I1_O_LUT4_I2_2_I3 I3=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_3(2) I1=cavlc_read_total_coeffs.rbsp_3(3) I2=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I1 O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=cavlc_read_total_coeffs.rbsp_3(5) I3=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_3(6) I2=cavlc_read_total_coeffs.rbsp_3(8) I3=cavlc_read_total_coeffs.rbsp_3(7) O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=cavlc_read_total_coeffs.nC(1) I2=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cavlc_read_total_coeffs.nC(2) O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(2) I1=cavlc_read_total_coeffs.rbsp_2(1) I2=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_total_coeffs.rbsp_2(0) O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(4) I1=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I3=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_2(1) I2=cavlc_read_total_coeffs.rbsp_2(2) I3=cavlc_read_total_coeffs.rbsp_2(3) O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_1(1) I1=cavlc_read_total_coeffs.rbsp_1(2) I2=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TrailingOnes_comb_LUT4_O_1_I0_LUT4_O_I1 O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(4) I2=cavlc_read_total_coeffs.rbsp_1(3) I3=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(5) I2=cavlc_read_total_coeffs.rbsp_1(6) I3=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=len_comb_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 I1=cavlc_read_total_coeffs.rbsp_1(9) I2=cavlc_read_total_coeffs.rbsp_1(8) I3=cavlc_read_total_coeffs.rbsp_1(7) O=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=len_comb_LUT4_O_4_I2_LUT4_O_I0 I1=len_comb_LUT4_O_4_I2_LUT4_O_I1 I2=len_comb_LUT4_O_4_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I3_LUT4_O_I3 O=len_comb_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_I0 I1=len_comb_LUT4_O_4_I2_LUT4_O_I0 I2=len_comb_LUT4_O_4_I2_LUT4_O_I1 I3=cavlc_read_levels.rbsp(1) O=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I0 I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I1 I2=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3 O=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_1_I0 I1=cavlc_read_levels.rbsp(1) I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3 I3=cavlc_read_run_befores.clr_LUT4_I3_2_O O=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=ZeroLeft(1) I2=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I3=cavlc_read_levels.rbsp(0) O=len_comb_LUT4_O_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=ZeroLeft(2) I3=ZeroLeft(3) O=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=ZeroLeft(1) I1=ZeroLeft(0) I2=ZeroLeft(3) I3=ZeroLeft(2) O=len_comb_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_3_I3_LUT4_O_I3 O=len_comb_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I2=ZeroLeft(0) I3=ZeroLeft(1) O=len_comb_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.rbsp(4) I2=cavlc_read_levels.rbsp(3) I3=len_comb_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=cavlc_read_levels.rbsp(7) I1=cavlc_read_levels.rbsp(8) I2=cavlc_read_levels.rbsp(5) I3=cavlc_read_levels.rbsp(6) O=len_comb_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=len_comb_LUT4_O_4_I3_LUT4_O_I0 I1=len_comb_LUT4_O_4_I3_LUT4_O_I1 I2=len_comb_LUT4_O_4_I3_LUT4_O_I2 I3=len_comb_LUT4_O_3_I2 O=len_comb_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_zeros.chroma_DC_sel I3=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O O=len_comb_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1 I2=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff(1) I2=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 I3=cavlc_read_levels.rbsp(0) O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.rbsp(1) I2=len_comb_LUT4_O_2_I3_LUT4_O_I2 I3=len_comb_LUT4_O_2_I3_LUT4_O_I0 O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=cavlc_read_levels.level_prefix_comb_LUT4_O_I2 I1=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I2 I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I3 O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=len_comb_LUT4_O_3_I1_LUT4_O_I1 I3=len_comb_LUT4_O_I1_LUT4_O_I2 O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I0_LUT4_O_I2 I2=len_comb_LUT4_O_I0_LUT4_O_I0 I3=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=len_comb_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=len_comb_LUT4_O_I0_LUT4_O_I0 I1=len_comb_LUT4_O_I0_LUT4_O_I1 I2=len_comb_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_3_I2 O=len_comb_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I0_LUT4_O_I0 I3=cavlc_read_levels.rbsp(1) O=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff(1) I3=cavlc_fsm.TotalCoeff(0) O=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=cavlc_read_total_zeros.chroma_DC_sel O=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff(2) I3=cavlc_fsm.TotalCoeff(3) O=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=len_comb_LUT4_O_I0_LUT4_O_I1 I1=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_I0_I1 I2=len_comb_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_I0_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=cavlc_read_run_befores.ZeroLeft_init_LUT4_I3_1_O I1=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I1 I2=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O I3=ZeroLeft(1) O=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_levels.rbsp(1) I3=len_comb_LUT4_O_4_I3_LUT4_O_I0 O=len_comb_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff(0) I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=cavlc_fsm.TotalCoeff(1) O=len_comb_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_4_I3_LUT4_O_I0 I3=cavlc_read_levels.rbsp(0) O=len_comb_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000011111111
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_3_I1_LUT4_O_I1 O=len_comb_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(0) I1=cavlc_fsm.TotalCoeff(3) I2=cavlc_fsm.TotalCoeff(1) I3=cavlc_fsm.TotalCoeff(2) O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101111111110011
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I2 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.rbsp(4) I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.rbsp(3) I3=cavlc_read_total_zeros.chroma_DC_sel O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(0) I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110010110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=cavlc_read_levels.rbsp(1) O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.TotalCoeff(2) I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff(3) O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.rbsp(1) I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=cavlc_fsm.TotalCoeff(3) I3=cavlc_fsm.TotalCoeff(2) O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.rbsp(0) I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(2) I1=cavlc_fsm.TotalCoeff(1) I2=cavlc_fsm.TotalCoeff(3) I3=cavlc_fsm.TotalCoeff(0) O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O O=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_3_I1_LUT4_O_I1 O=len_comb_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff(2) I3=cavlc_fsm.TotalCoeff(3) O=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I2=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001110111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I2=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111101110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=cavlc_read_levels.rbsp(3) I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O O=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=cavlc_fsm.TotalCoeff(3) I3=cavlc_fsm.TotalCoeff(2) O=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I1=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=len_comb_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=len_comb_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=cavlc_fsm.TotalCoeff(1) I1=cavlc_fsm.TotalCoeff(0) I2=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I1=cavlc_read_levels.rbsp(2) I2=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O O=len_comb_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_total_zeros.chroma_DC_sel I3=cavlc_read_levels.rbsp(1) O=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_total_zeros.chroma_DC_sel I3=cavlc_read_levels.rbsp(0) O=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I1_LUT4_O_I2 I2=cavlc_read_total_zeros.chroma_DC_sel I3=cavlc_read_levels.rbsp(2) O=len_comb_LUT4_O_I1_LUT4_O_I2_LUT4_I1_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_4_I3_LUT4_O_I0 O=len_comb_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cavlc_read_levels.rbsp(3) I2=len_comb_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I2 O=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 I2=cavlc_read_levels.rbsp(2) I3=cavlc_read_levels.rbsp(1) O=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=len_comb_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I0 I1=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1 I2=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=len_comb_LUT4_O_2_I3_LUT4_O_I1_LUT4_I2_I0 O=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(8) I1=cavlc_read_levels.rbsp(5) I2=cavlc_read_levels.rbsp(7) I3=cavlc_read_levels.rbsp(6) O=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000011011111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.rbsp(4) I2=cavlc_read_levels.rbsp(5) I3=cavlc_read_levels.rbsp(3) O=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.rbsp(4) I2=cavlc_read_levels.rbsp(3) I3=cavlc_read_total_zeros.chroma_DC_sel O=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_fsm.TotalCoeff(0) I3=cavlc_fsm.TotalCoeff(1) O=len_comb_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_2_I1 I2=len_comb_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=len_comb_LUT4_O_1_I2_LUT4_O_I1 I1=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_2_I0_LUT4_O_I3 O=len_comb_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000011111111
+.subckt LUT4 I0=cavlc_read_total_coeffs.nC(1) I1=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100010001
+.subckt LUT4 I0=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_1(1) I3=cavlc_read_total_coeffs.rbsp_1(0) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(5) I2=cavlc_read_total_coeffs.rbsp_1(3) I3=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_1(7) I2=cavlc_read_total_coeffs.rbsp_1(6) I3=cavlc_read_total_coeffs.rbsp_1(4) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.rbsp_1(2) I2=cavlc_read_total_coeffs.rbsp_1(4) I3=cavlc_read_total_coeffs.rbsp_1(3) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_2(3) I2=cavlc_read_total_coeffs.rbsp_2(2) I3=cavlc_read_total_coeffs.rbsp_2(1) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101010
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(4) I1=cavlc_read_total_coeffs.rbsp_2(5) I2=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=cavlc_read_total_coeffs.rbsp_2(6) I2=cavlc_read_total_coeffs.rbsp_2(4) I3=cavlc_read_total_coeffs.rbsp_2(7) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_2(9) I1=cavlc_read_total_coeffs.rbsp_2(10) I2=cavlc_read_total_coeffs.rbsp_2(11) I3=cavlc_read_total_coeffs.rbsp_2(8) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.nC(1) I3=cavlc_read_total_coeffs.rbsp_2(0) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cavlc_fsm.TotalCoeff_comb_LUT4_O_4_I2 O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=len_comb_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=cavlc_read_total_coeffs.rbsp_3(2) I2=cavlc_fsm.TotalCoeff_comb_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 I3=cavlc_read_total_coeffs.rbsp_3(1) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=TotalZeros_comb(0) I1=start_LUT4_I1_O_LUT4_I2_2_I3 I2=cavlc_read_total_coeffs.nC(2) I3=cavlc_read_total_coeffs.rbsp_3(0) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(2) I1=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_total_coeffs.rbsp_5(1) I3=cavlc_read_total_coeffs.rbsp_5(0) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=cavlc_read_total_coeffs.rbsp_5(5) I1=cavlc_read_total_coeffs.rbsp_5(6) I2=cavlc_read_total_coeffs.rbsp_5(3) I3=cavlc_read_total_coeffs.rbsp_5(4) O=len_comb_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=cavlc_read_levels.t1s_sel I1=cavlc_read_levels.level_prefix_comb(0) I2=cavlc_read_levels.prefix_sel I3=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=len_comb_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_levels.t1s_sel I2=TrailingOnes(0) I3=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=cavlc_read_levels.prefix_sel I1=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_levels.suffix_sel I3=cavlc_read_levels.suffixLength(0) O=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=cavlc_read_levels.suffixLength(2) I3=len_comb_LUT4_O_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=len_comb_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I0 I1=len_comb_LUT4_O_I3_LUT4_O_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I2 I3=len_comb_LUT4_O_I3_LUT4_O_I3 O=len_comb_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=ZeroLeft(1) I1=ZeroLeft(2) I2=ZeroLeft(0) I3=ZeroLeft(3) O=len_comb_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=len_comb_LUT4_O_3_I3_LUT4_O_I3 I3=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=len_comb_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=len_comb_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_levels.rbsp(2) O=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I1=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(1) I1=cavlc_read_levels.rbsp(0) I2=ZeroLeft(0) I3=ZeroLeft(1) O=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001000110000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(5) I1=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cavlc_read_levels.rbsp(4) I3=cavlc_read_levels.rbsp(3) O=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=cavlc_read_levels.rbsp(8) I1=cavlc_read_levels.rbsp(9) I2=cavlc_read_levels.rbsp(7) I3=cavlc_read_levels.rbsp(6) O=len_comb_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.rbsp(0) I3=cavlc_read_levels.rbsp(1) O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_levels.rbsp(2) I3=cavlc_read_levels.rbsp(1) O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_1_I0 I1=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_levels.rbsp(1) O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_levels.rbsp(2) I3=cavlc_read_levels.rbsp(0) O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_1_O_LUT4_I2_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_1_O I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I3 O=cavlc_read_run_befores.ZeroLeft_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=cavlc_read_levels.rbsp(0) I2=cavlc_read_levels.rbsp(1) I3=cavlc_read_levels.rbsp(2) O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110000010111
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_4_I2_LUT4_O_I1 I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(2) I1=cavlc_read_levels.rbsp(1) I2=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=cavlc_read_levels.rbsp(0) O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=ZeroLeft(1) I1=ZeroLeft(0) I2=ZeroLeft(3) I3=ZeroLeft(2) O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(1) I1=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cavlc_read_levels.rbsp(0) I3=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101111100001100
+.subckt LUT4 I0=ZeroLeft(3) I1=ZeroLeft(1) I2=ZeroLeft(0) I3=ZeroLeft(2) O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=ZeroLeft(0) I1=ZeroLeft(3) I2=ZeroLeft(1) I3=ZeroLeft(2) O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cavlc_read_levels.rbsp(0) I1=ZeroLeft(0) I2=ZeroLeft(1) I3=len_comb_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 O=len_comb_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110000000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=TotalZeros_comb(0) I3=cavlc_fsm.rst_n O=rst_n_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.start I2=cavlc_fsm.ena I3=cavlc_read_total_zeros.chroma_DC_sel O=start_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_fsm.start I2=cavlc_read_total_zeros.chroma_DC_sel I3=cavlc_fsm.ena O=cavlc_read_total_coeffs.rbsp_5_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=len_comb_LUT4_O_1_I2_LUT4_O_I1 I2=start_LUT4_I1_O I3=cavlc_read_total_coeffs.nC(1) O=start_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.nC(1) I2=start_LUT4_I1_O I3=len_comb_LUT4_O_1_I2_LUT4_O_I1 O=start_LUT4_I1_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=cavlc_read_total_coeffs.nC(2) I2=start_LUT4_I1_O I3=start_LUT4_I1_O_LUT4_I2_2_I3 O=start_LUT4_I1_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=TotalZeros_comb(0) I1=TotalZeros_comb(0) I2=cavlc_read_total_coeffs.nC(4) I3=cavlc_read_total_coeffs.nC(3) O=start_LUT4_I1_O_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.end
diff --git a/BENCHMARK/cavlc_top/rtl/cavlc_fsm.v b/BENCHMARK/cavlc_top/rtl/cavlc_fsm.v
new file mode 100644
index 0000000..c78bfd1
--- /dev/null
+++ b/BENCHMARK/cavlc_top/rtl/cavlc_fsm.v
@@ -0,0 +1,162 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  cavlc_fsm                                                   ////
+////                                                              ////
+////  Description                                                 ////
+////      controls the cavlc parsing process                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - bin qiu, qiubin@opencores.org                         ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//2011-8-7 18:57    initial revision
+
+`include "defines.v"
+
+module cavlc_fsm
+(
+    clk,
+    rst_n,
+    ena,
+    start,
+    max_coeff_num,
+    TotalCoeff,
+    TotalCoeff_comb,
+    TrailingOnes,
+    TrailingOnes_comb,
+    ZeroLeft,
+    state,
+    i,
+    idle,
+    valid
+);
+//------------------------
+//ports
+//------------------------
+input  clk;
+input  rst_n;
+input  ena;
+input  start;
+
+input  [4:0]  max_coeff_num;
+input  [4:0]  TotalCoeff;
+input  [4:0]  TotalCoeff_comb;
+input  [1:0]  TrailingOnes;
+input  [1:0]  TrailingOnes_comb;
+input  [3:0]  ZeroLeft;
+
+output [7:0]  state;
+output [3:0]  i;
+output idle;
+output valid;
+
+//------------------------
+//FFs
+//------------------------
+reg  [7:0]  state;
+reg  [3:0]  i;
+reg  valid;
+
+//------------------------
+//state & i & valid
+//------------------------
+always @(posedge clk or negedge rst_n)
+if (!rst_n) begin
+    state   <= `cavlc_idle_s;
+    i <= 0;
+    valid <= 0;
+end
+else if (ena)
+case(state)
+    `cavlc_idle_s : begin
+        if (start) begin
+            state <= `cavlc_read_total_coeffs_s;
+            valid <= 0;
+        end
+        else begin
+            state <= `cavlc_idle_s;
+        end     
+    end
+    `cavlc_read_total_coeffs_s : begin
+        i <= TotalCoeff_comb -1;
+        if (TrailingOnes_comb > 0 && TotalCoeff_comb > 0)
+            state <= `cavlc_read_t1s_flags_s;
+        else if (TotalCoeff_comb > 0)
+            state <= `cavlc_read_level_prefix_s;
+        else begin
+            state <= `cavlc_idle_s;     
+            valid <= 1;
+        end
+    end
+    `cavlc_read_t1s_flags_s : begin
+        if (TrailingOnes == TotalCoeff)
+            state <= `cavlc_read_total_zeros_s;         
+        else begin
+            state <= `cavlc_read_level_prefix_s;
+            i <= i - TrailingOnes;
+        end
+    end
+    `cavlc_read_level_prefix_s : begin
+        state <= `cavlc_read_level_suffix_s;        
+    end
+    `cavlc_read_level_suffix_s : begin
+        state <= `cavlc_calc_level_s;       
+    end
+    `cavlc_calc_level_s : begin
+        if ( i == 0  && TotalCoeff < max_coeff_num)
+            state <= `cavlc_read_total_zeros_s;
+        else if (i == 0) begin
+            state <= `cavlc_read_run_befores_s;
+            i <= TotalCoeff - 1;
+        end
+        else begin
+            state <= `cavlc_read_level_prefix_s;
+            i <= i - 1;
+        end
+    end 
+    `cavlc_read_total_zeros_s : begin
+        state <= `cavlc_read_run_befores_s;
+        i <= TotalCoeff - 1;
+    end
+    `cavlc_read_run_befores_s : begin
+        if (i == 0 || ZeroLeft == 0) begin
+            state <= `cavlc_idle_s;
+            valid <= 1;
+        end
+        else begin
+            state <= `cavlc_read_run_befores_s;
+            i <= i - 1;
+        end
+    end     
+endcase
+
+assign idle = state[`cavlc_idle_bit];
+
+endmodule
+
diff --git a/BENCHMARK/cavlc_top/rtl/cavlc_len_gen.v b/BENCHMARK/cavlc_top/rtl/cavlc_len_gen.v
new file mode 100644
index 0000000..5ce9f61
--- /dev/null
+++ b/BENCHMARK/cavlc_top/rtl/cavlc_len_gen.v
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  cavlc_len_gen                                               ////
+////                                                              ////
+////  Description                                                 ////
+////      generate the number of bits to forward                  ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - bin qiu, qiubin@opencores.org                         ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//2011-8-7 20:19    initial revision
+
+`include "defines.v"
+
+module cavlc_len_gen
+(
+    cavlc_state,
+    len_read_total_coeffs_comb,
+    len_read_levels_comb,
+    len_read_total_zeros_comb,
+    len_read_run_befores_comb,
+    len_comb
+);
+//------------------------
+// ports
+//------------------------
+input  [7:0] cavlc_state;
+input  [4:0] len_read_total_coeffs_comb;
+input  [4:0] len_read_levels_comb;
+input  [3:0] len_read_total_zeros_comb;
+input  [3:0] len_read_run_befores_comb;
+
+output [4:0] len_comb;
+
+//------------------------
+// regs
+//------------------------
+reg [4:0] len_comb;         //number of bits comsumed by cavlc in a cycle
+
+//------------------------
+// len_comb
+//------------------------
+always @ (*)
+case (1'b1) //synthesis parallel_case
+    cavlc_state[`cavlc_read_total_coeffs_bit]  : len_comb <= len_read_total_coeffs_comb;
+    cavlc_state[`cavlc_read_t1s_flags_bit],  
+    cavlc_state[`cavlc_read_level_prefix_bit],
+    cavlc_state[`cavlc_read_level_suffix_bit]  : len_comb <= len_read_levels_comb;       
+    cavlc_state[`cavlc_read_total_zeros_bit]   : len_comb <= len_read_total_zeros_comb;
+    cavlc_state[`cavlc_read_run_befores_bit]   : len_comb <= len_read_run_befores_comb;
+    cavlc_state[`cavlc_calc_level_bit],
+    cavlc_state[`cavlc_idle_bit]               : len_comb <= 0;
+    default                                    : len_comb <= 'bx;
+endcase
+
+endmodule
+
diff --git a/BENCHMARK/cavlc_top/rtl/cavlc_read_levels.v b/BENCHMARK/cavlc_top/rtl/cavlc_read_levels.v
new file mode 100644
index 0000000..86470fd
--- /dev/null
+++ b/BENCHMARK/cavlc_top/rtl/cavlc_read_levels.v
@@ -0,0 +1,400 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  cavlc_read_levels                                           ////
+////                                                              ////
+////  Description                                                 ////
+////      decode levels for coeffs                                ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - bin qiu, qiubin@opencores.org                         ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+//2011-8-6  initiial revision
+//2011-8-19 reverse the order of level
+
+//  include TrailingOnes
+
+`include "defines.v"
+
+module cavlc_read_levels (
+    clk,
+    rst_n,
+    ena,
+    t1s_sel,
+    prefix_sel,
+    suffix_sel,
+    calc_sel,
+    TrailingOnes,
+    TotalCoeff,
+    rbsp,
+    i,
+    level_0,
+    level_1,
+    level_2,
+    level_3,
+    level_4,
+    level_5,
+    level_6,
+    level_7,
+    level_8,
+    level_9,
+    level_10,
+    level_11,
+    level_12,
+    level_13,
+    level_14,
+    level_15,
+    len_comb
+);
+//------------------------
+// ports
+//------------------------
+input   clk;
+input   rst_n;
+
+input   ena;
+input   t1s_sel;
+input   prefix_sel;
+input   suffix_sel;
+input   calc_sel;
+
+input   [1:0]   TrailingOnes;
+input   [4:0]   TotalCoeff;
+input   [0:15]  rbsp;
+input   [3:0]   i;
+
+output  [8:0]   level_0;
+output  [8:0]   level_1;
+output  [8:0]   level_2;
+output  [8:0]   level_3;
+output  [8:0]   level_4;
+output  [8:0]   level_5;
+output  [8:0]   level_6;
+output  [8:0]   level_7;
+output  [8:0]   level_8;
+output  [8:0]   level_9;
+output  [8:0]   level_10;
+output  [8:0]   level_11;
+output  [8:0]   level_12;
+output  [8:0]   level_13;
+output  [8:0]   level_14;
+output  [8:0]   level_15;
+
+output  [4:0]   len_comb;
+
+//------------------------
+//  regs
+//------------------------
+reg     [0:15]  rbsp_internal;        // reduce toggle rate
+reg     [3:0]   level_prefix_comb;
+reg     [8:0]   level_suffix;
+reg     [4:0]   len_comb;
+
+//------------------------
+// FFs
+//------------------------
+reg     [3:0]   level_prefix;
+reg     [2:0]   suffixLength;   // range from 0 to 6
+reg     [8:0]   level;
+reg     [8:0]   level_abs;
+reg     [8:0]   level_code_tmp;
+reg     [8:0]   level_0, level_1, level_2, level_3, level_4, level_5, level_6, level_7;
+reg     [8:0]   level_8, level_9, level_10, level_11, level_12, level_13, level_14, level_15;
+
+//------------------------
+// level_prefix_comb
+//------------------------
+always @(*)
+if ((t1s_sel || prefix_sel || suffix_sel)&& ena)
+    rbsp_internal <= rbsp;
+else
+    rbsp_internal <= 'hffff;
+
+always @(*)
+if (rbsp_internal[0])         level_prefix_comb <= 0;
+else if (rbsp_internal[1])    level_prefix_comb <= 1;
+else if (rbsp_internal[2])    level_prefix_comb <= 2;
+else if (rbsp_internal[3])    level_prefix_comb <= 3;
+else if (rbsp_internal[4])    level_prefix_comb <= 4;
+else if (rbsp_internal[5])    level_prefix_comb <= 5;
+else if (rbsp_internal[6])    level_prefix_comb <= 6;
+else if (rbsp_internal[7])    level_prefix_comb <= 7;
+else if (rbsp_internal[8])    level_prefix_comb <= 8;
+else if (rbsp_internal[9])    level_prefix_comb <= 9;
+else if (rbsp_internal[10])   level_prefix_comb <= 10;
+else if (rbsp_internal[11])   level_prefix_comb <= 11;
+else if (rbsp_internal[12])   level_prefix_comb <= 12; 
+else if (rbsp_internal[13])   level_prefix_comb <= 13; 
+else if (rbsp_internal[14])   level_prefix_comb <= 14;
+else if (rbsp_internal[15])   level_prefix_comb <= 15;
+else                          level_prefix_comb <= 'bx;
+    
+
+//------------------------
+// level_prefix
+//------------------------
+always @(posedge clk or negedge rst_n)
+if (!rst_n)
+    level_prefix <= 0;
+else if (prefix_sel && ena)
+    level_prefix <= level_prefix_comb;
+
+//------------------------
+// suffixLength
+//------------------------
+wire first_level;
+assign first_level = (i == TotalCoeff - TrailingOnes - 1);
+
+always @(posedge clk or negedge rst_n)
+if (!rst_n)
+    suffixLength <= 0;
+else if (prefix_sel && ena) begin
+    if (TotalCoeff > 10 && TrailingOnes < 3 && first_level )  //initialize suffixLength before proceeding first level_suffix
+        suffixLength <= 1;
+    else if (first_level)
+        suffixLength <= 0;
+    else if (suffixLength == 0 && level_abs > 2'd3)
+        suffixLength <= 2;
+    else if (suffixLength == 0)
+        suffixLength <= 1;
+    else if (  level_abs > (2'd3 << (suffixLength - 1'b1) ) && suffixLength < 6)
+        suffixLength <= suffixLength + 1'b1;
+end
+
+
+//------------------------
+// level_suffix
+//------------------------
+always @(*)
+if (suffixLength > 0 && level_prefix <= 14) 
+    level_suffix <= {3'b0, rbsp_internal[0:5] >> (3'd6 - suffixLength)};
+else if (level_prefix == 14)   //level_prefix == 14 && suffixLength == 0
+    level_suffix <= {3'b0, rbsp_internal[0:3] };
+else if (level_prefix == 15) 
+    level_suffix <= rbsp_internal[3:11];     
+else 
+    level_suffix <= 0;      
+
+//------------------------
+// level_code_tmp
+//------------------------
+always @(posedge clk or negedge rst_n)
+if (!rst_n) begin
+    level_code_tmp <=  0;
+end
+else if (suffix_sel && ena) begin
+    level_code_tmp <= (level_prefix << suffixLength) + level_suffix + 
+    ((suffixLength == 0 && level_prefix == 15) ? 4'd15 : 0);
+end
+
+
+//------------------------
+// level
+//------------------------
+wire    [2:0]   tmp1;
+
+assign tmp1 = (first_level && TrailingOnes < 3)? 2'd2 : 2'd0;
+
+always @(*)
+begin
+    if (level_code_tmp % 2 == 0) begin
+        level <= ( level_code_tmp + tmp1 + 2 ) >> 1;
+    end
+    else begin
+        level <= (-level_code_tmp - tmp1 - 1 ) >> 1;
+    end
+end
+
+//------------------------
+// level_abs
+//------------------------
+wire level_abs_refresh;
+assign level_abs_refresh = calc_sel && ena;
+
+always @(posedge clk or negedge rst_n)
+if (!rst_n) begin
+    level_abs <= 0;
+end
+else if (level_abs_refresh) begin
+    level_abs <= level[8] ? -level : level;
+end
+
+//------------------------
+// level regfile
+//------------------------
+always @ (posedge clk or negedge rst_n)
+if (!rst_n) begin
+    level_0 <= 0;   level_1 <= 0;   level_2 <= 0;   level_3 <= 0;
+    level_4 <= 0;   level_5 <= 0;   level_6 <= 0;   level_7 <= 0;
+    level_8 <= 0;   level_9 <= 0;   level_10<= 0;   level_11<= 0;
+    level_12<= 0;   level_13<= 0;   level_14<= 0;   level_15<= 0;
+end
+else if (t1s_sel && ena)
+    case (i)
+    0 : level_0 <= rbsp_internal[0]? -1 : 1;
+    1 : begin
+            level_1 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_0 <= rbsp_internal[1]? -1 : 1;
+        end
+    2 : begin
+            level_2 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_1 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_0 <= rbsp_internal[2]? -1 : 1;
+        end         
+    3 : begin
+            level_3 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_2 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_1 <= rbsp_internal[2]? -1 : 1;
+        end 
+    4 : begin
+            level_4 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_3 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_2 <= rbsp_internal[2]? -1 : 1;
+        end 
+    5 : begin
+            level_5 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_4 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_3 <= rbsp_internal[2]? -1 : 1;
+        end 
+    6 : begin
+            level_6 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_5 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_4 <= rbsp_internal[2]? -1 : 1;
+        end 
+    7 : begin
+            level_7 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_6 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_5 <= rbsp_internal[2]? -1 : 1;
+        end 
+    8 : begin
+            level_8 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_7 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_6 <= rbsp_internal[2]? -1 : 1;
+        end 
+    9 : begin
+            level_9 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_8 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_7 <= rbsp_internal[2]? -1 : 1;
+        end 
+    10: begin
+            level_10 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_9 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_8 <= rbsp_internal[2]? -1 : 1;
+        end 
+    11: begin
+            level_11 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_10 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_9 <= rbsp_internal[2]? -1 : 1;
+        end 
+    12: begin
+            level_12 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_11 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_10 <= rbsp_internal[2]? -1 : 1;
+        end 
+    13: begin
+            level_13 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_12 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_11 <= rbsp_internal[2]? -1 : 1;
+        end 
+    14: begin
+            level_14 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_13 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_12 <= rbsp_internal[2]? -1 : 1;
+        end 
+    15: begin
+            level_15 <= rbsp_internal[0]? -1 : 1;
+            if (TrailingOnes[1])
+                level_14 <= rbsp_internal[1]? -1 : 1;
+            if (TrailingOnes == 3)
+                level_13 <= rbsp_internal[2]? -1 : 1;
+        end 
+endcase
+else if (calc_sel && ena)
+case (i)
+    0 :level_0 <= level;
+    1 :level_1 <= level;
+    2 :level_2 <= level;
+    3 :level_3 <= level;
+    4 :level_4 <= level;
+    5 :level_5 <= level;
+    6 :level_6 <= level;
+    7 :level_7 <= level;
+    8 :level_8 <= level;
+    9 :level_9 <= level;
+    10:level_10<= level;
+    11:level_11<= level;
+    12:level_12<= level;
+    13:level_13<= level;
+    14:level_14<= level;
+    15:level_15<= level;
+endcase
+
+always @(*)
+if(t1s_sel)
+    len_comb <= TrailingOnes;
+else if(prefix_sel)
+    len_comb <= level_prefix_comb + 1;
+else if(suffix_sel && suffixLength > 0 && level_prefix <= 14)
+    len_comb <= suffixLength;  
+else if(suffix_sel && level_prefix == 14)
+    len_comb <= 4;
+else if(suffix_sel && level_prefix == 15)
+    len_comb <= 12;
+else
+    len_comb <= 0;        
+
+endmodule
diff --git a/BENCHMARK/cavlc_top/rtl/cavlc_read_run_befores.v b/BENCHMARK/cavlc_top/rtl/cavlc_read_run_befores.v
new file mode 100644
index 0000000..a35f26a
--- /dev/null
+++ b/BENCHMARK/cavlc_top/rtl/cavlc_read_run_befores.v
@@ -0,0 +1,368 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  cavlc_read_run_befores                                      ////
+////                                                              ////
+////  Description                                                 ////
+////       decode runs and combine them with levels               ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - bin qiu, qiubin@opencores.org                         ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//2011-8-16 initiial revision
+
+`include "defines.v"
+
+module cavlc_read_run_befores
+(
+    clk,
+    rst_n,
+    ena,
+    sel,
+    clr,
+    ZeroLeft_init,
+    
+    rbsp,
+    i,
+    TotalZeros_comb,
+    
+    level_0,
+    level_1,
+    level_2,
+    level_3,
+    level_4,
+    level_5,
+    level_6,
+    level_7,
+    level_8,
+    level_9,
+    level_10,
+    level_11,
+    level_12,
+    level_13,
+    level_14,
+    level_15,
+        
+    coeff_0,
+    coeff_1,
+    coeff_2,
+    coeff_3,
+    coeff_4,
+    coeff_5,
+    coeff_6,
+    coeff_7,
+    coeff_8,
+    coeff_9,
+    coeff_10,
+    coeff_11,
+    coeff_12,
+    coeff_13,
+    coeff_14,
+    coeff_15,
+    ZeroLeft,
+    len_comb
+);  
+//----------------------
+//ports
+//----------------------
+input   clk;
+input   rst_n;
+input   ena;
+input   sel;
+input   clr;
+input   ZeroLeft_init;
+
+input   [0:10]  rbsp;
+input   [3:0]   i;          //range from TotalCoeff-1 to 0
+input   [3:0]   TotalZeros_comb;
+
+input   [8:0]   level_0;
+input   [8:0]   level_1;
+input   [8:0]   level_2;
+input   [8:0]   level_3;
+input   [8:0]   level_4;
+input   [8:0]   level_5;
+input   [8:0]   level_6;
+input   [8:0]   level_7;
+input   [8:0]   level_8;
+input   [8:0]   level_9;
+input   [8:0]   level_10;
+input   [8:0]   level_11;
+input   [8:0]   level_12;
+input   [8:0]   level_13;
+input   [8:0]   level_14;
+input   [8:0]   level_15;
+
+output  [8:0]   coeff_0;
+output  [8:0]   coeff_1;
+output  [8:0]   coeff_2;
+output  [8:0]   coeff_3;
+output  [8:0]   coeff_4;
+output  [8:0]   coeff_5;
+output  [8:0]   coeff_6;
+output  [8:0]   coeff_7;
+output  [8:0]   coeff_8;
+output  [8:0]   coeff_9;
+output  [8:0]   coeff_10;
+output  [8:0]   coeff_11;
+output  [8:0]   coeff_12;
+output  [8:0]   coeff_13;
+output  [8:0]   coeff_14;
+output  [8:0]   coeff_15;
+
+output  [3:0]   ZeroLeft;
+
+output  [3:0]   len_comb;
+
+//----------------------
+//regs
+//----------------------
+reg     [3:0]   run;
+reg     [3:0]   len;
+reg     [8:0]   coeff;
+
+
+reg     [3:0]   len_comb;
+
+//----------------------
+//FFs
+//----------------------
+reg     [3:0]   ZeroLeft;
+
+reg     [8:0]   coeff_0;
+reg     [8:0]   coeff_1;
+reg     [8:0]   coeff_2;
+reg     [8:0]   coeff_3;
+reg     [8:0]   coeff_4;
+reg     [8:0]   coeff_5;
+reg     [8:0]   coeff_6;
+reg     [8:0]   coeff_7;
+reg     [8:0]   coeff_8;
+reg     [8:0]   coeff_9;
+reg     [8:0]   coeff_10;
+reg     [8:0]   coeff_11;
+reg     [8:0]   coeff_12;
+reg     [8:0]   coeff_13;
+reg     [8:0]   coeff_14;
+reg     [8:0]   coeff_15;
+
+//----------------------
+//run & len
+//----------------------
+always @(rbsp or ZeroLeft or ena or sel)
+if (ena && sel)
+case(ZeroLeft)
+    0 : begin len <= 0; run <= 0; end
+    1 : begin len <= 1; run <= rbsp[0]? 0:1; end
+    2 : begin if (rbsp[0]) begin
+            run <= 0;
+            len <= 1;
+        end
+        else if (rbsp[1]) begin
+            run <= 1;
+            len <= 2;
+        end 
+        else begin
+            run <= 2;
+            len <= 2;
+        end
+    end
+    3 : begin
+        run <= 3 - rbsp[0:1];
+        len <= 2;
+    end
+    4 : begin
+        if (rbsp[0:1] != 0) begin
+            run <= 3 - rbsp[0:1];
+            len <= 2;
+        end
+        else begin
+            run <= rbsp[2]? 3:4;
+            len <= 3;
+        end
+    end
+    5 : begin
+        if (rbsp[0]) begin
+            run <= rbsp[1]? 0:1;
+            len <= 2;
+        end
+        else if (rbsp[1]) begin
+            run <= rbsp[2]? 2:3;
+            len <= 3;
+        end     
+        else begin
+            run <= rbsp[2]? 4:5;
+            len <= 3;       
+        end
+    end
+    6 : begin
+        if (rbsp[0:1] == 2'b11) begin
+            run <= 0;
+            len <= 2;
+        end
+        else begin
+            len <= 3;
+            case(rbsp[0:2])
+                3'b000 : run <= 1;
+                3'b001 : run <= 2;
+                3'b011 : run <= 3;
+                3'b010 : run <= 4;
+                3'b101 : run <= 5;
+                default: run <= 6;
+            endcase
+        end     
+    end
+    default : begin
+        if (rbsp[0:2] != 0) begin
+            run <= 7 - rbsp[0:2];
+            len <= 3;
+        end
+        else begin
+            case (1'b1)
+                rbsp[3] : begin run <= 7;   len <= 4; end
+                rbsp[4] : begin run <= 8;   len <= 5; end
+                rbsp[5] : begin run <= 9;   len <= 6; end
+                rbsp[6] : begin run <= 10;  len <= 7; end
+                rbsp[7] : begin run <= 11;  len <= 8; end
+                rbsp[8] : begin run <= 12;  len <= 9; end
+                rbsp[9] : begin run <= 13;  len <= 10;end
+                rbsp[10]: begin run <= 14;  len <= 11;end
+                default : begin run <= 'bx; len <='bx;end
+            endcase
+        end
+    end
+endcase
+else begin
+    len <= 0;
+    run <= 0;
+end
+
+//----------------------
+//len_comb
+//----------------------
+always @(*)
+if (i >  0)
+    len_comb <= len;
+else
+    len_comb <= 0;
+    
+    
+//----------------------
+//ZeroLeft
+//----------------------
+always @(posedge clk or negedge rst_n)
+if (!rst_n)
+    ZeroLeft <= 0;
+else if (ena && clr)    //in case TotalCoeff >= max_coeff_num
+    ZeroLeft <= 0;
+else if (ena && ZeroLeft_init)
+    ZeroLeft <= TotalZeros_comb;
+else if (ena && sel )//if ZeroLeft == 0, run will be 0
+    ZeroLeft <= ZeroLeft - run; 
+        
+//----------------------
+//coeff
+//----------------------
+always @(*)
+if (ena && sel)
+case (i)
+    0 :coeff <= level_0;
+    1 :coeff <= level_1;
+    2 :coeff <= level_2;
+    3 :coeff <= level_3;
+    4 :coeff <= level_4;
+    5 :coeff <= level_5;    
+    6 :coeff <= level_6;
+    7 :coeff <= level_7;
+    8 :coeff <= level_8;
+    9 :coeff <= level_9;
+    10:coeff <= level_10;
+    11:coeff <= level_11;       
+    12:coeff <= level_12;
+    13:coeff <= level_13;
+    14:coeff <= level_14;
+    15:coeff <= level_15;
+endcase
+else
+    coeff <= 0;
+
+//----------------------
+//coeff_0 to coeff_15
+//----------------------
+always @(posedge clk or negedge rst_n)
+if (!rst_n) begin
+    coeff_0 <= 0;   coeff_1 <= 0;   coeff_2 <= 0;   coeff_3 <= 0;
+    coeff_4 <= 0;   coeff_5 <= 0;   coeff_6 <= 0;   coeff_7 <= 0;
+    coeff_8 <= 0;   coeff_9 <= 0;   coeff_10<= 0;   coeff_11<= 0;
+    coeff_12<= 0;   coeff_13<= 0;   coeff_14<= 0;   coeff_15<= 0;
+end
+else if (ena && clr) begin
+    coeff_0 <= 0;   coeff_1 <= 0;   coeff_2 <= 0;   coeff_3 <= 0;
+    coeff_4 <= 0;   coeff_5 <= 0;   coeff_6 <= 0;   coeff_7 <= 0;
+    coeff_8 <= 0;   coeff_9 <= 0;   coeff_10<= 0;   coeff_11<= 0;
+    coeff_12<= 0;   coeff_13<= 0;   coeff_14<= 0;   coeff_15<= 0;
+end
+else if (ena && sel && ZeroLeft > 0)
+case (ZeroLeft+i)
+    1 :coeff_1  <= coeff;
+    2 :coeff_2  <= coeff;
+    3 :coeff_3  <= coeff;
+    4 :coeff_4  <= coeff;
+    5 :coeff_5  <= coeff;
+    6 :coeff_6  <= coeff;
+    7 :coeff_7  <= coeff;
+    8 :coeff_8  <= coeff;
+    9 :coeff_9  <= coeff;
+    10:coeff_10 <= coeff;
+    11:coeff_11 <= coeff;
+    12:coeff_12 <= coeff;
+    13:coeff_13 <= coeff;
+    14:coeff_14 <= coeff;
+    default:
+    coeff_15    <= coeff;
+endcase
+else if (ena && sel) begin
+    if (i >= 0) coeff_0  <= level_0;
+    if (i >= 1) coeff_1  <= level_1;
+    if (i >= 2) coeff_2  <= level_2;
+    if (i >= 3) coeff_3  <= level_3;
+    if (i >= 4) coeff_4  <= level_4;
+    if (i >= 5) coeff_5  <= level_5;
+    if (i >= 6) coeff_6  <= level_6;
+    if (i >= 7) coeff_7  <= level_7;
+    if (i >= 8) coeff_8  <= level_8;
+    if (i >= 9) coeff_9  <= level_9;
+    if (i >= 10)coeff_10 <= level_10;
+    if (i >= 11)coeff_11 <= level_11;
+    if (i >= 12)coeff_12 <= level_12;
+    if (i >= 13)coeff_13 <= level_13;
+    if (i >= 14)coeff_14 <= level_14;
+    if (i == 15)coeff_15 <= level_15;
+end
+endmodule
diff --git a/BENCHMARK/cavlc_top/rtl/cavlc_read_total_coeffs.v b/BENCHMARK/cavlc_top/rtl/cavlc_read_total_coeffs.v
new file mode 100644
index 0000000..9226f8a
--- /dev/null
+++ b/BENCHMARK/cavlc_top/rtl/cavlc_read_total_coeffs.v
@@ -0,0 +1,1197 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  cavlc_read_total_coeffs                                     ////
+////                                                              ////
+////  Description                                                 ////
+////      decode total_coeffs and trailing ones                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - bin qiu, qiubin@opencores.org                         ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//2011-8-7  initial creation
+//2011-8-9  optimize output mux
+
+
+`include "defines.v"
+
+module cavlc_read_total_coeffs
+(
+    clk,
+    rst_n,
+    ena,
+    start,
+    sel,
+    rbsp, nC,
+    TrailingOnes,
+    TotalCoeff,
+    TrailingOnes_comb,
+    TotalCoeff_comb,
+    len_comb
+);
+//------------------------
+//ports
+//------------------------
+input   clk;
+input   rst_n;
+input   ena;
+input   start;
+input   sel;
+
+input   [0:15]   rbsp;
+input   signed   [5:0]   nC;
+
+output  [4:0]  TotalCoeff;        //range from 0 to 16
+output  [1:0]  TrailingOnes;      //range from 0 to 3   
+output  [4:0]  TotalCoeff_comb;   //unsaved result of TotalCoeff_comb
+output  [1:0]  TrailingOnes_comb; //unsaved result of TrailingOnes_comb
+output  [4:0]  len_comb;          //indicate how many rbsp bit consumed, range from 0 to 16
+
+
+//------------------------
+//regs
+//------------------------
+reg     [4:0]   TotalCoeff_comb;
+reg     [1:0]   TrailingOnes_comb;
+reg     [4:0]   len_comb;
+
+//for nC >= 0 && nC < 2
+reg     [4:0]   TotalCoeff_1;
+reg     [1:0]   TrailingOnes_1;
+reg     [4:0]   len_1;
+
+//for nC >= 2 && nC < 4
+reg     [4:0]   TotalCoeff_2;
+reg     [1:0]   TrailingOnes_2;
+reg     [4:0]   len_2;
+
+//for nC >= 4 && nC < 8
+reg     [4:0]   TotalCoeff_3;
+reg     [1:0]   TrailingOnes_3;
+reg     [4:0]   len_3;
+
+//for nC >= 8
+reg     [4:0]   TotalCoeff_4;
+reg     [1:0]   TrailingOnes_4;
+reg     [4:0]   len_4;
+
+//for nC == -1
+reg     [4:0]   TotalCoeff_5;
+reg     [1:0]   TrailingOnes_5;
+reg     [4:0]   len_5;
+
+
+//------------------------
+//FFs
+//------------------------
+//len is not necessary to be saved
+//TotalCoeff & TrailingOnes should be valid when cavlc_state == `cavlc_read_total_coeffs_s
+//to do that,combinational result "TotalCoeff_comb & TrailingOnes_comb" are outputed
+reg     [0:15]  rbsp_1;         
+reg     [0:13]  rbsp_2;
+reg     [0:9]   rbsp_3;
+reg     [0:5]   rbsp_4;
+reg     [0:7]   rbsp_5;
+
+reg     [4:0]   TotalCoeff;
+reg     [1:0]   TrailingOnes;
+
+//------------------------
+//input mux
+//------------------------
+always @(posedge clk or negedge rst_n)
+if (!rst_n)
+begin
+        rbsp_1 <=  0;
+        rbsp_2 <=  0;
+        rbsp_3 <=  0;
+        rbsp_4 <=  0;
+        rbsp_5 <=  0;
+
+end
+else if (ena && start)
+begin
+    if (nC[5])
+        rbsp_5 <=  rbsp[0:7];
+    else if ( nC[4] || nC[3])
+        rbsp_4 <= rbsp[0:5];
+    else if (nC[2])
+        rbsp_3 <= rbsp[0:9];
+    else if (nC[1])
+        rbsp_2 <= rbsp[0:13];
+    else
+        rbsp_1 <= rbsp;
+end
+//------------------------
+//nC >= 0 && nC < 2                 
+//------------------------
+always @(rbsp_1)
+case (1'b1) 
+rbsp_1[0] : begin
+    TrailingOnes_1  <= 0;
+    TotalCoeff_1    <= 0;
+    len_1           <= 1;
+end
+rbsp_1[1] : begin
+    TrailingOnes_1  <= 1;
+    TotalCoeff_1    <= 1;
+    len_1           <= 2;
+end
+rbsp_1[2] : begin
+    TrailingOnes_1  <= 2;
+    TotalCoeff_1    <= 2;
+    len_1           <= 3;
+end
+rbsp_1[3] : begin
+    if (rbsp_1[4] == 'b1) begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 3;
+        len_1           <= 5;
+    end
+    else if (rbsp_1[5] == 'b1) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 1;
+        len_1           <= 6;
+    end
+    else begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 2;
+        len_1           <= 6;
+    end
+end
+rbsp_1[4] : begin
+    if (rbsp_1[5] == 'b1) begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 4;
+        len_1           <= 6;
+    end
+    else if (rbsp_1[6] == 'b1) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 3;
+        len_1           <= 7;
+    end
+    else begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 5;
+        len_1           <= 7;
+    end
+end
+rbsp_1[5] : begin
+    len_1           <= 8;
+    if (rbsp_1[6:7] == 'b11) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 2;
+    end
+    else if (rbsp_1[6:7] == 'b10) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 3;
+    end
+    else if (rbsp_1[6:7] == 'b01) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 4;
+    end
+    else begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 6;
+    end
+end
+rbsp_1[6] : begin
+    len_1           <= 9;
+    if (rbsp_1[7:8] == 2'b11) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 3;
+    end
+    else if (rbsp_1[7:8] == 2'b10) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 4;
+    end
+    else if (rbsp_1[7:8] == 2'b01) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 5;
+    end
+    else  begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 7;
+    end
+end
+rbsp_1[7] : begin
+    len_1           <= 10;
+    if (rbsp_1[8:9] == 2'b11) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 4;
+    end
+    else if (rbsp_1[8:9] == 2'b10) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 5;
+    end
+    else if (rbsp_1[8:9] == 2'b01) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 6;
+    end
+    else begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 8;
+    end
+end
+rbsp_1[8] : begin
+    len_1           <= 11;
+    if (rbsp_1[9:10] == 2'b11) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 5;
+    end
+    else if (rbsp_1[9:10] == 2'b10) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 6;
+    end
+    else if (rbsp_1[9:10] == 2'b01) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 7;
+    end
+    else begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 9;
+    end
+end
+rbsp_1[9] : begin
+    len_1           <= 13;
+    if (rbsp_1[10:12] == 3'b111) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 6;
+    end
+    else if (rbsp_1[10:12] == 3'b011) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 7;
+    end
+    else if (rbsp_1[10:12] == 3'b110) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 7;
+    end
+    else if (rbsp_1[10:12] == 3'b000) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 8;
+    end
+    else if (rbsp_1[10:12] == 3'b010) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 8;
+    end
+    else if (rbsp_1[10:12] == 3'b101) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 8;
+    end
+    else if (rbsp_1[10:12] == 3'b001) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 9;
+    end
+    else begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 10;
+    end
+end
+rbsp_1[10] : begin
+    len_1           <= 14;
+    if (rbsp_1[11:13] == 3'b111) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 9;
+    end
+    else if (rbsp_1[11:13] == 3'b110) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 9;
+    end
+    else if (rbsp_1[11:13] == 3'b011) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 10;
+    end
+    else if (rbsp_1[11:13] == 3'b010) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 10;
+    end
+    else if (rbsp_1[11:13] == 3'b101) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 10;
+    end
+    else if (rbsp_1[11:13] == 3'b001) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 11;
+    end
+    else if (rbsp_1[11:13] == 3'b100) begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 11;
+    end
+    else begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 12;
+    end
+end
+rbsp_1[11] : begin
+    len_1           <= 15;
+    if (rbsp_1[12:14] == 3'b111) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 11;
+    end
+    else if (rbsp_1[12:14] == 3'b110) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 11;
+    end
+    else if (rbsp_1[12:14] == 3'b011) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 12;
+    end
+    else if (rbsp_1[12:14] == 3'b010) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 12;
+    end
+    else if (rbsp_1[12:14] == 3'b101) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 12;
+    end
+    else if (rbsp_1[12:14] == 3'b001) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 13;
+    end
+    else if (rbsp_1[12:14] == 3'b100) begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 13;
+    end
+    else begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 14;
+    end
+end
+rbsp_1[12] : begin
+    len_1           <= 16;
+    if (rbsp_1[13:15] == 3'b111) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 13;
+    end
+    else if (rbsp_1[13:15] == 3'b011) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 14;
+    end
+    else if (rbsp_1[13:15] == 3'b110) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 14;
+    end
+    else if (rbsp_1[13:15] == 3'b101) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 14;
+    end
+    else if (rbsp_1[13:15] == 3'b010) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 15;
+    end
+    else if (rbsp_1[13:15] == 3'b001) begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 15;
+    end
+    else if (rbsp_1[13:15] == 3'b100) begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 15;
+    end
+    else begin
+        TrailingOnes_1  <= 3;
+        TotalCoeff_1    <= 16;
+    end
+end
+rbsp_1[13] : begin
+    len_1           <= 16;
+    if (rbsp_1[14:15] == 2'b11) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 15;
+    end
+    else if (rbsp_1[14:15] == 2'b00) begin
+        TrailingOnes_1  <= 0;
+        TotalCoeff_1    <= 16;
+    end
+    else if (rbsp_1[14:15] == 2'b10) begin
+        TrailingOnes_1  <= 1;
+        TotalCoeff_1    <= 16;
+    end
+    else begin
+        TrailingOnes_1  <= 2;
+        TotalCoeff_1    <= 16;
+    end
+end
+default : begin
+    len_1           <= 15;
+    TrailingOnes_1  <= 1;
+    TotalCoeff_1    <= 13;
+end
+endcase
+
+//------------------------
+//nC >= 2 && nC < 4
+//------------------------
+always @(rbsp_2)
+case (1'b1) 
+rbsp_2[0] : begin
+    len_2           <= 2;
+    if (rbsp_2[1] == 'b1) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 0;
+    end
+    else begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 1;
+    end
+end
+rbsp_2[1] : begin
+    if (rbsp_2[2] == 'b1) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 2;
+        len_2           <= 3;
+    end
+    else if (rbsp_2[3] == 'b1) begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 3;
+        len_2           <= 4;
+    end
+    else begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 4;
+        len_2           <= 4;
+    end
+end
+rbsp_2[2] : begin
+    if (rbsp_2[3:4] == 'b11) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 2;
+        len_2           <= 5;
+    end
+    else if (rbsp_2[3:4] == 'b10) begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 5;
+        len_2           <= 5;
+    end
+    else if (rbsp_2[4:5] == 'b11) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 1;
+        len_2           <= 6;
+    end
+    else if (rbsp_2[4:5] == 'b10) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 3;
+        len_2           <= 6;
+    end
+    else if (rbsp_2[4:5] == 'b01) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 3;
+        len_2           <= 6;
+    end
+    else begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 6;
+        len_2           <= 6;
+    end
+end
+rbsp_2[3] : begin
+    len_2           <= 6;
+    if (rbsp_2[4:5] == 'b11) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 2;
+    end
+    else if (rbsp_2[4:5] == 'b10) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 4;
+    end
+    else if (rbsp_2[4:5] == 'b01) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 4;
+    end
+    else begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 7;
+    end
+end
+rbsp_2[4] : begin
+    len_2           <= 7;
+    if (rbsp_2[5:6] == 'b11) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 3;
+    end
+    else if (rbsp_2[5:6] == 'b10) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 5;
+    end
+    else if (rbsp_2[5:6] == 'b01) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 5;
+    end
+    else begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 8;
+    end
+end
+rbsp_2[5] : begin
+    len_2           <= 8;
+    if (rbsp_2[6:7] == 'b11) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 4;
+    end
+    else if (rbsp_2[6:7] == 'b00) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 5;
+    end
+    else if (rbsp_2[6:7] == 'b10) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 6;
+    end
+    else begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 6;
+    end
+end
+rbsp_2[6] : begin
+    len_2           <= 9;
+    if (rbsp_2[7:8] == 'b11) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 6;
+    end
+    else if (rbsp_2[7:8] == 'b10) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 7;
+    end
+    else if (rbsp_2[7:8] == 'b01) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 7;
+    end
+    else begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 9;
+    end
+end
+rbsp_2[7] : begin
+    len_2           <= 11;
+    if (rbsp_2[8:10] == 'b111) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 7;
+    end
+    else if (rbsp_2[8:10] == 'b011) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 8;
+    end
+    else if (rbsp_2[8:10] == 'b110) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 8;
+    end
+    else if (rbsp_2[8:10] == 'b101) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 8;
+    end
+    else if (rbsp_2[8:10] == 'b010) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 9;
+    end
+    else if (rbsp_2[8:10] == 'b001) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 9;
+    end
+    else if (rbsp_2[8:10] == 'b100) begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 10;
+    end
+    else begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 11;
+    end
+end
+rbsp_2[8] : begin
+    len_2           <= 12;
+    if (rbsp_2[9:11] == 'b111) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 9;
+    end
+    else if (rbsp_2[9:11] == 'b011) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 10;
+    end
+    else if (rbsp_2[9:11] == 'b110) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 10;
+    end
+    else if (rbsp_2[9:11] == 'b101) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 10;
+    end
+    else if (rbsp_2[9:11] == 'b000) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 11;
+    end
+    else if (rbsp_2[9:11] == 'b010) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 11;
+    end
+    else if (rbsp_2[9:11] == 'b001) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 11;
+    end
+    else  begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 12;
+    end
+end
+rbsp_2[9] : begin
+    len_2           <= 13;
+    if (rbsp_2[10:12] == 'b111) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 12;
+    end
+    else if (rbsp_2[10:12] == 'b110) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 12;
+    end
+    else if (rbsp_2[10:12] == 'b101) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 12;
+    end
+    else if (rbsp_2[10:12] == 'b011) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 13;
+    end
+    else if (rbsp_2[10:12] == 'b010) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 13;
+    end
+    else if (rbsp_2[10:12] == 'b001) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 13;
+    end
+    else if (rbsp_2[10:12] == 'b100) begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 13;
+    end
+    else begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 14;
+    end
+end
+rbsp_2[10] : begin
+    if (rbsp_2[11:12] == 'b11) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 14;
+        len_2           <= 13;
+    end
+    else if (rbsp_2[11:12] == 'b10) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 14;
+        len_2           <= 13;
+    end
+    else if (rbsp_2[12:13] == 'b11) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 14;
+        len_2           <= 14;
+    end
+    else if (rbsp_2[12:13] == 'b01) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 15;
+        len_2           <= 14;
+    end
+    else if (rbsp_2[12:13] == 'b00) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 15;
+        len_2           <= 14;
+    end
+    else begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 15;
+        len_2           <= 14;
+    end
+end
+rbsp_2[11] : begin
+    len_2           <= 14;
+    if (rbsp_2[12:13] == 'b11) begin
+        TrailingOnes_2  <= 0;
+        TotalCoeff_2    <= 16;
+    end
+    else if (rbsp_2[12:13] == 'b10) begin
+        TrailingOnes_2  <= 1;
+        TotalCoeff_2    <= 16;
+    end
+    else if (rbsp_2[12:13] == 'b01) begin
+        TrailingOnes_2  <= 2;
+        TotalCoeff_2    <= 16;
+    end
+    else begin
+        TrailingOnes_2  <= 3;
+        TotalCoeff_2    <= 16;
+    end
+end
+default : begin
+    TrailingOnes_2  <= 3;
+    TotalCoeff_2    <= 15;
+    len_2           <= 13;
+end
+endcase
+
+//------------------------
+// nC >= 4 && nC < 8
+//------------------------
+always @(rbsp_3)
+case (1'b1) 
+rbsp_3[0] : begin
+    len_3           <= 4;
+    case (rbsp_3[1:3])
+        'b111 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 0;
+        end
+        'b110 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 1;
+        end
+        'b101 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 2;
+        end
+        'b100 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 3;
+        end
+        'b011 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 4;
+        end
+        'b010 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 5;
+        end
+        'b001 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 6;
+        end
+        'b000 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 7;
+        end
+    endcase
+end
+rbsp_3[1] : begin
+    len_3           <= 5;
+    case (rbsp_3[2:4])
+        'b111 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 2;
+        end
+        'b100 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 3;
+        end
+        'b110 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 3;
+        end
+        'b010 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 4;
+        end
+        'b011 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 4;
+        end
+        'b000 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 5;
+        end
+        'b001 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 5;
+        end
+        'b101 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 8;
+        end
+    endcase
+end
+rbsp_3[2] : begin
+    len_3           <= 6;
+    case (rbsp_3[3:5])
+        3'b111 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 1;
+        end
+        3'b011 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 2;
+        end
+        3'b000 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 3;
+        end
+        3'b110 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 6;
+        end
+        3'b101 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 6;
+        end
+        3'b010 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 7;
+        end
+        3'b001 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 7;
+        end
+        3'b100 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 9;
+        end
+    endcase
+end
+rbsp_3[3] : begin
+    len_3           <= 7;
+    case (rbsp_3[4:6])
+        'b111 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 4;
+        end
+        'b011 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 5;
+        end
+        'b001 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 6;
+        end
+        'b000 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 7;
+        end
+        'b110 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 8;
+        end
+        'b101 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 8;
+        end
+
+        'b010 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 9;
+        end
+        'b100 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 10;
+        end
+    endcase
+end
+rbsp_3[4] : begin
+    len_3           <= 8;
+    case (rbsp_3[5:7])
+        'b111 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 8;
+        end
+        'b011 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 9;
+        end
+        'b110 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 9;
+        end
+        'b010 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 10;
+        end
+        'b101 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 10;
+        end
+        'b001 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 11;
+        end
+        'b100 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 11;
+        end
+        'b000 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 12;
+        end
+    endcase
+end
+rbsp_3[5] : begin
+    len_3           <= 9;
+    case (rbsp_3[6:8])
+        'b111 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 10;
+        end
+        'b011 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 11;
+        end
+        'b110 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 11;
+        end
+        'b000 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 12;
+        end
+        'b010 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 12;
+        end
+        'b101 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 12;
+        end
+        'b001 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 13;
+        end
+        'b100 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 13;
+        end
+    endcase
+end
+rbsp_3[6] : begin
+    if (rbsp_3[7:8] == 'b11)begin
+        TrailingOnes_3  <= 1;
+        TotalCoeff_3    <= 13;
+        len_3           <= 9;
+    end
+    else if (rbsp_3[7:9] == 'b101)begin
+        TrailingOnes_3  <= 0;
+        TotalCoeff_3    <= 13;
+        len_3           <= 10;
+    end
+    else if (rbsp_3[7:9] == 'b001)begin
+        TrailingOnes_3  <= 0;
+        TotalCoeff_3    <= 14;
+        len_3           <= 10;
+    end
+    else if (rbsp_3[7:9] == 'b100)begin
+        TrailingOnes_3  <= 1;
+        TotalCoeff_3    <= 14;
+        len_3           <= 10;
+    end
+    else if (rbsp_3[7:9] == 'b011)begin
+        TrailingOnes_3  <= 2;
+        TotalCoeff_3    <= 14;
+        len_3           <= 10;
+    end
+    else if (rbsp_3[7:9] == 'b010)begin
+        TrailingOnes_3  <= 3;
+        TotalCoeff_3    <= 14;
+        len_3           <= 10;
+    end
+    else begin
+        TrailingOnes_3  <= 1;
+        TotalCoeff_3    <= 15;
+        len_3           <= 10;
+    end
+end
+rbsp_3[7] : begin
+    len_3           <= 10;
+    case (rbsp_3[8:9])
+        'b01 : begin
+            TrailingOnes_3  <= 0;
+            TotalCoeff_3    <= 15;
+        end
+        'b11 : begin
+            TrailingOnes_3  <= 2;
+            TotalCoeff_3    <= 15;
+        end
+        'b10 : begin
+            TrailingOnes_3  <= 3;
+            TotalCoeff_3    <= 15;
+        end
+        'b00 : begin
+            TrailingOnes_3  <= 1;
+            TotalCoeff_3    <= 16;
+        end
+    endcase
+end
+rbsp_3[8] : begin
+    len_3           <= 10;
+    if (rbsp_3[9] == 'b1)begin
+        TrailingOnes_3  <= 2;
+        TotalCoeff_3    <= 16;
+    end
+    else begin
+        TrailingOnes_3  <= 3;
+        TotalCoeff_3    <= 16;
+    end
+end
+default : begin
+    len_3           <= 10;
+    TrailingOnes_3  <= 0;
+    TotalCoeff_3    <= 16;
+end
+endcase
+
+//------------------------
+// nC > 8
+//------------------------
+always @(rbsp_4)
+begin
+    len_4 <= 6;
+    if (rbsp_4[0:4] == 5'b00001) begin
+        TrailingOnes_4  <= 0;
+        TotalCoeff_4    <= 0;
+    end
+    else begin
+        TrailingOnes_4  <= rbsp_4[4:5];
+        TotalCoeff_4    <= rbsp_4[0:3] + 1'b1;
+    end
+end
+
+//------------------------
+// nC == -1
+//------------------------
+always @(rbsp_5)
+case (1'b1)
+rbsp_5[0] : begin
+    TrailingOnes_5  <= 1;
+    TotalCoeff_5    <= 1;
+    len_5           <= 1;
+end
+rbsp_5[1] : begin
+    TrailingOnes_5  <= 0;
+    TotalCoeff_5    <= 0;
+    len_5           <= 2;
+end
+rbsp_5[2] : begin
+    TrailingOnes_5  <= 2;
+    TotalCoeff_5    <= 2;
+    len_5           <= 3;
+end
+rbsp_5[3] : begin
+    len_5           <= 6;
+    if (rbsp_5[4:5] == 'b11) begin
+        TrailingOnes_5  <= 0;
+        TotalCoeff_5    <= 1;
+    end
+    else if (rbsp_5[4:5] == 'b00) begin
+        TrailingOnes_5  <= 0;
+        TotalCoeff_5    <= 2;
+    end
+    else if (rbsp_5[4:5] == 'b10) begin
+        TrailingOnes_5  <= 1;
+        TotalCoeff_5    <= 2;
+    end
+    else begin
+        TrailingOnes_5  <= 3;
+        TotalCoeff_5    <= 3;
+    end
+end
+rbsp_5[4] : begin
+    len_5           <= 6;
+    if (rbsp_5[5] == 'b1) begin
+        TrailingOnes_5  <= 0;
+        TotalCoeff_5    <= 3;
+    end
+    else begin
+        TrailingOnes_5  <= 0;
+        TotalCoeff_5    <= 4;
+    end
+end
+rbsp_5[5] : begin
+    len_5           <= 7;
+    if (rbsp_5[6] == 'b1) begin
+        TrailingOnes_5  <= 1;
+        TotalCoeff_5    <= 3;
+    end
+    else begin
+        TrailingOnes_5  <= 2;
+        TotalCoeff_5    <= 3;
+    end
+end
+rbsp_5[6] : begin
+    len_5           <= 8;
+    if (rbsp_5[7] == 'b1) begin
+        TrailingOnes_5  <= 1;
+        TotalCoeff_5    <= 4;
+    end
+    else begin
+        TrailingOnes_5  <= 2;
+        TotalCoeff_5    <= 4;
+    end
+end
+default : begin
+    len_5           <= 7;
+    TrailingOnes_5  <= 3;
+    TotalCoeff_5    <= 4;
+end
+endcase
+
+//------------------------
+//output mux
+//------------------------
+//startect a colum according to nC
+always @(*)
+begin
+    if (nC == -1) begin
+        TrailingOnes_comb   <= TrailingOnes_5;
+        TotalCoeff_comb     <= TotalCoeff_5;
+        len_comb            <= len_5;
+    end
+    else if (nC[4] | nC[3]) begin
+        TrailingOnes_comb   <= TrailingOnes_4;
+        TotalCoeff_comb     <= TotalCoeff_4;
+        len_comb            <= len_4;
+    end
+    else if (nC[2]) begin
+        TrailingOnes_comb   <= TrailingOnes_3;
+        TotalCoeff_comb     <= TotalCoeff_3;
+        len_comb            <= len_3;
+    end
+    else if (nC[1]) begin
+        TrailingOnes_comb   <= TrailingOnes_2;
+        TotalCoeff_comb     <= TotalCoeff_2;
+        len_comb            <= len_2;
+    end
+    else begin
+        TrailingOnes_comb   <= TrailingOnes_1;
+        TotalCoeff_comb     <= TotalCoeff_1;
+        len_comb            <= len_1;
+    end
+end
+
+//------------------------
+//TrailingOnes & TotalCoeff
+//------------------------
+always @(posedge clk or negedge rst_n)
+if (!rst_n) begin
+    TrailingOnes    <= 0;
+    TotalCoeff      <= 0;
+end
+else if (ena && sel) begin
+    TrailingOnes    <= TrailingOnes_comb;
+    TotalCoeff      <= TotalCoeff_comb;
+end
+
+endmodule
+
diff --git a/BENCHMARK/cavlc_top/rtl/cavlc_read_total_zeros.v b/BENCHMARK/cavlc_top/rtl/cavlc_read_total_zeros.v
new file mode 100644
index 0000000..9df5866
--- /dev/null
+++ b/BENCHMARK/cavlc_top/rtl/cavlc_read_total_zeros.v
@@ -0,0 +1,716 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  cavlc_read_total_zeros                                      ////
+////                                                              ////
+////  Description                                                 ////
+////       decode total_zeros                                     ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - bin qiu, qiubin@opencores.org                         ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//2011-8-14 initial version
+
+`include "defines.v"
+
+module cavlc_read_total_zeros
+(
+    ena,
+    sel,
+    chroma_DC_sel,
+    rbsp,
+    TotalCoeff,
+    TotalZeros_comb,
+    len_comb
+);
+//------------------------
+//ports
+//------------------------
+input   ena;
+input   sel;
+input   chroma_DC_sel;
+input   [0:8]   rbsp;
+input   [3:0]   TotalCoeff;
+
+output  [3:0]   TotalZeros_comb;
+output  [3:0]   len_comb;
+
+//-------------------------
+//rregs
+//-------------------------
+reg     [3:0]   TotalZeros_comb;    //TotalZeros will be saved as ZeroLeft in module cavlc_read_run_befores 
+reg     [3:0]   len_comb;
+
+
+//for  chroma_DC
+reg     [0:2]   rbsp_chroma_DC;         
+reg     [1:0]   TotalZeros_chroma_DC;
+reg     [1:0]   len_chroma_DC;
+
+//for TotalCoeff <= 3
+reg     [0:8]   rbsp_LE3;       
+reg     [3:0]   TotalZeros_LE3;
+reg     [3:0]   len_LE3;
+
+//for TotalCoeff > 3
+reg     [0:5]   rbsp_G3;        
+reg     [3:0]   TotalZeros_G3;
+reg     [2:0]   len_G3;
+
+
+//----------------------------------------
+//input mux
+//----------------------------------------
+always @(*)
+if (ena && sel && chroma_DC_sel) begin
+    rbsp_chroma_DC  <= rbsp[0:2];
+    rbsp_LE3        <= 'hffff;
+    rbsp_G3         <= 'hffff;
+end
+else if (ena && sel && TotalCoeff[3:2] == 2'b00) begin
+    rbsp_chroma_DC  <= 'hffff;
+    rbsp_LE3        <= rbsp[0:8];
+    rbsp_G3         <= 'hffff;
+end
+else if (ena && sel)begin
+    rbsp_chroma_DC  <= 'hffff;
+    rbsp_LE3        <= 'hffff;
+    rbsp_G3         <= rbsp[0:5];
+end
+else begin
+    rbsp_chroma_DC  <= 'hffff;
+    rbsp_LE3        <= 'hffff;
+    rbsp_G3         <= 'hffff;
+end
+
+//----------------------------------------
+//TotalZeros_chroma_DC & len_chroma_DC
+//----------------------------------------
+always @(*)
+if ( TotalCoeff == 1 && rbsp_chroma_DC[0] ) begin
+    TotalZeros_chroma_DC    <= 0;
+    len_chroma_DC           <= 1;
+end
+else if ( TotalCoeff == 1 && rbsp_chroma_DC[1] ) begin
+    TotalZeros_chroma_DC    <= 1;
+    len_chroma_DC           <= 2;
+end
+else if ( TotalCoeff == 1 && rbsp_chroma_DC[2] ) begin
+    TotalZeros_chroma_DC    <= 2;
+    len_chroma_DC           <= 3;
+end
+else if ( TotalCoeff == 1 ) begin
+    TotalZeros_chroma_DC    <= 3;
+    len_chroma_DC           <= 3;
+end
+else if ( TotalCoeff == 2 && rbsp_chroma_DC[0] ) begin
+    TotalZeros_chroma_DC    <= 0;
+    len_chroma_DC           <= 1;
+end
+else if ( TotalCoeff == 2 && rbsp_chroma_DC[1] ) begin
+    TotalZeros_chroma_DC    <= 1;
+    len_chroma_DC           <= 2;
+end
+else if ( TotalCoeff == 2 ) begin
+    TotalZeros_chroma_DC    <= 2;
+    len_chroma_DC           <= 2;
+end
+else if ( rbsp_chroma_DC[0] ) begin
+    TotalZeros_chroma_DC    <= 0;
+    len_chroma_DC           <= 1;
+end
+else begin
+    TotalZeros_chroma_DC    <= 1;
+    len_chroma_DC           <= 1;
+end
+
+
+//---------------------------------
+//TotalZeros_LE3 & len_LE3
+//---------------------------------
+always @(rbsp_LE3 or TotalCoeff)
+case (TotalCoeff[1:0])
+1 :begin
+    case(1'b1)
+    rbsp_LE3[0] : begin
+        TotalZeros_LE3  <= 0;
+        len_LE3         <= 1;   
+    end
+    rbsp_LE3[1] : begin
+        len_LE3         <= 3;
+        if (rbsp_LE3[2])
+            TotalZeros_LE3  <= 1;
+        else
+            TotalZeros_LE3  <= 2;
+    end
+    rbsp_LE3[2] : begin
+        len_LE3         <= 4;
+        if (rbsp_LE3[3])
+            TotalZeros_LE3  <= 3;
+        else
+            TotalZeros_LE3  <= 4;
+    end
+    rbsp_LE3[3] : begin
+        len_LE3         <= 5;
+        if (rbsp_LE3[4])
+            TotalZeros_LE3  <= 5;
+        else
+            TotalZeros_LE3  <= 6;
+    end
+    rbsp_LE3[4] : begin
+        len_LE3         <= 6;
+        if (rbsp_LE3[5])
+            TotalZeros_LE3  <= 7;
+        else
+            TotalZeros_LE3  <= 8;
+    end
+    rbsp_LE3[5] : begin
+        len_LE3         <= 7;
+        if (rbsp_LE3[6])
+            TotalZeros_LE3  <= 9;
+        else
+            TotalZeros_LE3  <= 10;
+    end
+    rbsp_LE3[6] : begin
+        len_LE3         <= 8;
+        if (rbsp_LE3[7])
+            TotalZeros_LE3  <= 11;
+        else
+            TotalZeros_LE3  <= 12;
+    end
+    rbsp_LE3[7] : begin
+        len_LE3         <= 9;
+        if (rbsp_LE3[8])
+            TotalZeros_LE3  <= 13;
+        else
+            TotalZeros_LE3  <= 14;
+    end
+    default : begin
+        len_LE3         <= 9;
+        TotalZeros_LE3  <= 15;
+    end
+    endcase
+end
+2 : begin
+    case(1'b1)
+    rbsp_LE3[0] : begin
+        len_LE3 <= 3;
+        case(rbsp_LE3[1:2])
+        'b11 :  TotalZeros_LE3  <= 0;
+        'b10 :  TotalZeros_LE3  <= 1;
+        'b01 :  TotalZeros_LE3  <= 2;
+        'b00 :  TotalZeros_LE3  <= 3;
+        endcase
+    end
+    rbsp_LE3[1] : begin
+        if (rbsp_LE3[2]) begin
+            TotalZeros_LE3  <= 4;
+            len_LE3         <= 3;
+        end
+        else begin
+            len_LE3         <= 4;
+            if (rbsp_LE3[3])
+                TotalZeros_LE3  <= 5;
+            else
+                TotalZeros_LE3  <= 6;
+        end
+    end
+    rbsp_LE3[2] : begin
+        len_LE3         <= 4;
+        if (rbsp_LE3[3])
+            TotalZeros_LE3  <= 7;
+        else
+            TotalZeros_LE3  <= 8;
+    end
+    rbsp_LE3[3] : begin
+        len_LE3         <= 5;
+        if (rbsp_LE3[4])
+            TotalZeros_LE3  <= 9;
+        else
+            TotalZeros_LE3  <= 10;
+    end
+    default : begin
+        len_LE3 <= 6;
+        case(rbsp_LE3[4:5])
+        'b11 :  TotalZeros_LE3  <= 11;
+        'b10 :  TotalZeros_LE3  <= 12;
+        'b01 :  TotalZeros_LE3  <= 13;
+        'b00 :  TotalZeros_LE3  <= 14;
+        endcase
+    end
+    endcase
+end
+3 : begin
+    case(1'b1)
+    rbsp_LE3[0] : begin
+        len_LE3 <= 3;
+        case(rbsp_LE3[1:2])
+        'b11 :  TotalZeros_LE3  <= 1;
+        'b10 :  TotalZeros_LE3  <= 2;
+        'b01 :  TotalZeros_LE3  <= 3;
+        'b00 :  TotalZeros_LE3  <= 6;
+        endcase
+    end
+    rbsp_LE3[1] : begin
+        if (rbsp_LE3[2]) begin
+            TotalZeros_LE3  <= 7;
+            len_LE3         <= 3;
+        end
+        else begin
+            len_LE3         <= 4;
+            if (rbsp_LE3[3])
+                TotalZeros_LE3  <= 0;
+            else
+                TotalZeros_LE3  <= 4;
+        end
+    end
+    rbsp_LE3[2] : begin
+        len_LE3         <= 4;
+        if (rbsp_LE3[3])
+            TotalZeros_LE3  <= 5;
+        else
+            TotalZeros_LE3  <= 8;
+    end
+    rbsp_LE3[3] : begin
+        len_LE3         <= 5;
+        if (rbsp_LE3[4])
+            TotalZeros_LE3  <= 9;
+        else
+            TotalZeros_LE3  <= 10;
+    end
+    rbsp_LE3[4] : begin
+        len_LE3         <= 5;
+        TotalZeros_LE3  <= 12;
+    end
+    default : begin
+        len_LE3 <= 6;
+        if(rbsp_LE3[5])
+            TotalZeros_LE3  <= 11;
+        else
+            TotalZeros_LE3  <= 13;      
+    end
+    endcase
+end
+default : begin
+    len_LE3         <= 'bx;
+    TotalZeros_LE3  <= 'bx;
+end
+endcase
+
+//---------------------------------
+//TotalZeros_G3 & len_G3
+//---------------------------------
+always @(rbsp_G3 or TotalCoeff)
+case (TotalCoeff)
+4 : begin
+    case(1'b1)
+    rbsp_G3[0] : begin
+        len_G3  <= 3;
+        case(rbsp_G3[1:2])
+        'b11 :  TotalZeros_G3   <= 1;
+        'b10 :  TotalZeros_G3   <= 4;
+        'b01 :  TotalZeros_G3   <= 5;
+        'b00 :  TotalZeros_G3   <= 6;
+        endcase
+    end
+    rbsp_G3[1] : begin
+        if (rbsp_G3[2]) begin
+            TotalZeros_G3   <= 8;
+            len_G3          <= 3;
+        end
+        else begin
+            len_G3          <= 4;
+            if (rbsp_G3[3])
+                TotalZeros_G3   <= 2;
+            else
+                TotalZeros_G3   <= 3;
+        end
+    end
+    rbsp_G3[2] : begin
+        len_G3          <= 4;
+        if (rbsp_G3[3])
+            TotalZeros_G3   <= 7;
+        else
+            TotalZeros_G3   <= 9;
+    end
+    default : begin
+        len_G3  <= 5;
+        case(rbsp_G3[3:4])
+        'b11 :  TotalZeros_G3   <= 0;
+        'b10 :  TotalZeros_G3   <= 10;
+        'b01 :  TotalZeros_G3   <= 11;
+        'b00 :  TotalZeros_G3   <= 12;
+        endcase
+    end
+    endcase
+end
+5 :begin
+    case(1'b1)
+    rbsp_G3[0] : begin
+        len_G3  <= 3;
+        case(rbsp_G3[1:2])
+        'b11 :  TotalZeros_G3   <= 3;
+        'b10 :  TotalZeros_G3   <= 4;
+        'b01 :  TotalZeros_G3   <= 5;
+        'b00 :  TotalZeros_G3   <= 6;
+        endcase
+    end
+    rbsp_G3[1] : begin
+        if (rbsp_G3[2]) begin
+            TotalZeros_G3   <= 7;
+            len_G3          <= 3;
+        end
+        else begin
+            len_G3          <= 4;
+            if (rbsp_G3[3])
+                TotalZeros_G3   <= 0;
+            else
+                TotalZeros_G3   <= 1;
+        end
+    end
+    rbsp_G3[2] : begin
+        len_G3          <= 4;
+        if (rbsp_G3[3])
+            TotalZeros_G3   <= 2;
+        else
+            TotalZeros_G3   <= 8;
+    end
+    rbsp_G3[3] : begin
+        len_G3          <= 4;
+        TotalZeros_G3   <= 10;
+    end
+    default : begin
+        len_G3  <= 5;
+        if (rbsp_G3[4])
+            TotalZeros_G3   <= 9;
+        else
+            TotalZeros_G3   <= 11;
+    end
+    endcase
+end
+6 : begin
+    case(1'b1)
+    rbsp_G3[0] : begin
+        len_G3  <= 3;
+        case(rbsp_G3[1:2])
+        'b11 :  TotalZeros_G3   <= 2;
+        'b10 :  TotalZeros_G3   <= 3;
+        'b01 :  TotalZeros_G3   <= 4;
+        'b00 :  TotalZeros_G3   <= 5;
+        endcase
+    end
+    rbsp_G3[1] : begin
+        len_G3          <= 3;
+        if (rbsp_G3[2])
+            TotalZeros_G3   <= 6;
+        else
+            TotalZeros_G3   <= 7;
+    end
+    rbsp_G3[2] : begin
+        len_G3          <= 3;
+        TotalZeros_G3   <= 9;
+    end
+    rbsp_G3[3] : begin
+        len_G3          <= 4;
+        TotalZeros_G3   <= 8;
+    end
+    rbsp_G3[4] : begin
+        len_G3          <= 5;
+        TotalZeros_G3   <= 1;
+    end
+    default : begin
+        len_G3  <= 6;
+        if (rbsp_G3[5])
+            TotalZeros_G3   <= 0;
+        else
+            TotalZeros_G3   <= 10;
+    end
+    endcase
+end
+7 :begin
+    case(1'b1)
+    rbsp_G3[0] : begin
+        if (rbsp_G3[1]) begin
+            TotalZeros_G3   <= 5;
+            len_G3          <= 2;
+        end
+        else begin
+            len_G3          <= 3;
+            if (rbsp_G3[2])
+                TotalZeros_G3   <= 2;
+            else
+                TotalZeros_G3   <= 3;
+        end
+    end
+    rbsp_G3[1] : begin
+        len_G3  <= 3;
+        if (rbsp_G3[2])
+            TotalZeros_G3   <= 4;
+        else
+            TotalZeros_G3   <= 6;
+    end
+    rbsp_G3[2] : begin
+        len_G3          <= 3;
+        TotalZeros_G3   <= 8;
+    end
+    rbsp_G3[3] : begin
+        len_G3          <= 4;
+        TotalZeros_G3   <= 7;
+    end
+    rbsp_G3[4] : begin
+        len_G3          <= 5;
+        TotalZeros_G3   <= 1;
+    end
+    default : begin
+        len_G3          <= 6;
+        if (rbsp_G3[5])
+            TotalZeros_G3   <= 0;
+        else
+            TotalZeros_G3   <= 9;
+    end
+    endcase
+end
+8 :begin
+    case(1'b1)
+    rbsp_G3[0] : begin
+        len_G3          <= 2;
+        if (rbsp_G3[1]) 
+            TotalZeros_G3   <= 4;
+        else 
+            TotalZeros_G3   <= 5;
+    end
+    rbsp_G3[1] : begin
+        len_G3          <= 3;
+        if (rbsp_G3[2]) 
+            TotalZeros_G3   <= 3;
+        else 
+            TotalZeros_G3   <= 6;
+    end
+    rbsp_G3[2] : begin
+        len_G3          <= 3;
+        TotalZeros_G3   <= 7;
+    end
+    rbsp_G3[3] : begin
+        len_G3          <= 4;
+        TotalZeros_G3   <= 1;
+    end
+    rbsp_G3[4] : begin
+        len_G3          <= 5;
+        TotalZeros_G3   <= 2;
+    end
+    default : begin
+        len_G3          <= 6;
+        if (rbsp_G3[5])
+            TotalZeros_G3   <= 0;
+        else
+            TotalZeros_G3   <= 8;
+    end
+    endcase
+end
+9 : begin
+    case(1'b1)
+    rbsp_G3[0] : begin
+        len_G3          <= 2;
+        if (rbsp_G3[1]) 
+            TotalZeros_G3   <= 3;
+        else 
+            TotalZeros_G3   <= 4;
+    end
+    rbsp_G3[1] : begin
+        len_G3          <= 2;
+        TotalZeros_G3   <= 6;
+    end
+    rbsp_G3[2] : begin
+        len_G3          <= 3;
+        TotalZeros_G3   <= 5;
+    end
+    rbsp_G3[3] : begin
+        len_G3          <= 4;
+        TotalZeros_G3   <= 2;
+    end
+    rbsp_G3[4] : begin
+        len_G3          <= 5;
+        TotalZeros_G3   <= 7;
+    end
+    default : begin
+        len_G3          <= 6;
+        if (rbsp_G3[5])
+            TotalZeros_G3   <= 0;
+        else
+            TotalZeros_G3   <= 1;
+    end
+    endcase
+end
+10 : begin
+    case(1'b1)
+    rbsp_G3[0] : begin
+        len_G3          <= 2;
+        if (rbsp_G3[1]) 
+            TotalZeros_G3   <= 3;
+        else 
+            TotalZeros_G3   <= 4;
+    end
+    rbsp_G3[1] : begin
+        len_G3          <= 2;
+        TotalZeros_G3   <= 5;
+    end
+    rbsp_G3[2] : begin
+        len_G3          <= 3;
+        TotalZeros_G3   <= 2;
+    end
+    rbsp_G3[3] : begin
+        len_G3          <= 4;
+        TotalZeros_G3   <= 6;
+    end
+    default : begin
+        len_G3          <= 5;
+        if (rbsp_G3[4])
+            TotalZeros_G3   <= 0;
+        else
+            TotalZeros_G3   <= 1;
+    end
+    endcase
+end
+11 : begin
+    case(1'b1)
+    rbsp_G3[0] : begin
+        len_G3          <= 1;
+        TotalZeros_G3   <= 4;
+    end
+    rbsp_G3[1] : begin
+        len_G3          <= 3;
+        if (rbsp_G3[2]) 
+            TotalZeros_G3   <= 5;
+        else 
+            TotalZeros_G3   <= 3;
+    end
+    rbsp_G3[2] : begin
+        len_G3          <= 3;
+        TotalZeros_G3   <= 2;
+    end
+    default : begin
+        len_G3          <= 4;
+        if (rbsp_G3[3])
+            TotalZeros_G3   <= 1;
+        else
+            TotalZeros_G3   <= 0;
+    end
+    endcase
+end
+12 : begin
+    case(1'b1)
+    rbsp_G3[0] : begin
+        len_G3          <= 1;
+        TotalZeros_G3   <= 3;
+    end
+    rbsp_G3[1] : begin
+        len_G3          <= 2;
+        TotalZeros_G3   <= 2;
+    end
+    rbsp_G3[2] : begin
+        len_G3          <= 3;
+        TotalZeros_G3   <= 4;
+    end
+    default : begin
+        len_G3          <= 4;
+        if (rbsp_G3[3])
+            TotalZeros_G3   <= 1;
+        else
+            TotalZeros_G3   <= 0;
+    end
+    endcase
+end
+13  :begin
+    if (rbsp_G3[0]) begin
+        TotalZeros_G3   <= 2;
+        len_G3          <= 1;       
+    end
+    else if (rbsp_G3[1]) begin
+        TotalZeros_G3   <= 3;
+        len_G3          <= 2;   
+    end
+    else if (rbsp_G3[2]) begin
+        TotalZeros_G3   <= 1;
+        len_G3          <= 3;   
+    end
+    else begin
+        TotalZeros_G3   <= 0;
+        len_G3          <= 3;       
+    end
+end
+14  : begin
+    if (rbsp_G3[0]) begin
+        TotalZeros_G3   <= 2;
+        len_G3          <= 1;       
+    end
+    else if (rbsp_G3[1]) begin
+        TotalZeros_G3   <= 1;
+        len_G3          <= 2;   
+    end
+    else begin
+        TotalZeros_G3   <= 0;
+        len_G3          <= 2;       
+    end
+end
+15  : begin
+    len_G3  <= 1;
+    if (rbsp_G3[0])
+        TotalZeros_G3   <= 1;
+    else
+        TotalZeros_G3   <= 0;
+end
+default : begin
+    len_G3          <= 'bx;
+    TotalZeros_G3   <= 'bx;
+end
+endcase
+
+//---------------------------------
+//TotalZeros_comb & len_comb
+//---------------------------------
+always @(*)
+if (ena && sel && chroma_DC_sel) begin
+    TotalZeros_comb     <= TotalZeros_chroma_DC;
+    len_comb            <= len_chroma_DC;
+end
+else if (ena && sel && TotalCoeff[3:2] == 2'b00) begin
+    TotalZeros_comb     <= TotalZeros_LE3;
+    len_comb            <= len_LE3;
+end
+else if (ena && sel)begin
+    TotalZeros_comb     <= TotalZeros_G3;
+    len_comb            <= len_G3;
+end
+else begin
+    TotalZeros_comb     <= 0;
+    len_comb            <= 0;
+end
+
+
+endmodule
diff --git a/BENCHMARK/cavlc_top/rtl/cavlc_top.v b/BENCHMARK/cavlc_top/rtl/cavlc_top.v
new file mode 100644
index 0000000..0f22464
--- /dev/null
+++ b/BENCHMARK/cavlc_top/rtl/cavlc_top.v
@@ -0,0 +1,294 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  cavlc_top                                                   ////
+////                                                              ////
+////  Description                                                 ////
+////       top module of cavlc decoder                            ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - bin qiu, qiubin@opencores.org                         ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2011 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//2011-8-7 initial version
+
+`include "defines.v"
+
+module cavlc_top
+(
+    clk,
+    rst_n,
+    ena,
+    start,
+    rbsp,
+    nC,
+    max_coeff_num,
+
+    coeff_0,
+    coeff_1,
+    coeff_2,
+    coeff_3,
+    coeff_4,
+    coeff_5,
+    coeff_6,
+    coeff_7,
+    coeff_8,
+    coeff_9,
+    coeff_10,
+    coeff_11,
+    coeff_12,
+    coeff_13,
+    coeff_14,
+    coeff_15,
+    TotalCoeff,
+    len_comb,
+    idle,
+    valid
+);
+//------------------------
+// ports
+//------------------------
+input   clk, rst_n;
+input   ena;
+input   start;
+input   [0:15]  rbsp;
+input   signed [5:0]    nC;
+input   [4:0]   max_coeff_num;
+
+output  signed [8:0]    coeff_0;
+output  signed [8:0]    coeff_1;
+output  signed [8:0]    coeff_2;
+output  signed [8:0]    coeff_3;
+output  signed [8:0]    coeff_4;
+output  signed [8:0]    coeff_5;
+output  signed [8:0]    coeff_6;
+output  signed [8:0]    coeff_7;
+output  signed [8:0]    coeff_8;
+output  signed [8:0]    coeff_9;
+output  signed [8:0]    coeff_10;
+output  signed [8:0]    coeff_11;
+output  signed [8:0]    coeff_12;
+output  signed [8:0]    coeff_13;
+output  signed [8:0]    coeff_14;
+output  signed [8:0]    coeff_15;
+output  [4:0]   TotalCoeff;
+output  [4:0]   len_comb;
+output  idle;
+output  valid;
+
+//------------------------
+// cavlc_read_total_coeffs
+//------------------------
+wire [1:0] TrailingOnes;
+wire [4:0] TotalCoeff;
+wire [1:0] TrailingOnes_comb;
+wire [4:0] TotalCoeff_comb;
+wire [4:0] len_read_total_coeffs_comb;
+wire [7:0] cavlc_state;
+
+cavlc_read_total_coeffs cavlc_read_total_coeffs(
+    .clk(clk),
+    .rst_n(rst_n),
+    .ena(ena),
+    .start(start),
+    .sel(cavlc_state[`cavlc_read_total_coeffs_bit]),
+    
+    .rbsp(rbsp),
+    .nC(nC),
+    
+    .TrailingOnes(TrailingOnes), 
+    .TotalCoeff(TotalCoeff),
+
+    .TrailingOnes_comb(TrailingOnes_comb), 
+    .TotalCoeff_comb(TotalCoeff_comb),
+
+    .len_comb(len_read_total_coeffs_comb)
+);
+
+//------------------------
+// cavlc_read_levels
+//------------------------
+wire    [4:0]   len_read_levels_comb;
+wire    [3:0]   i;
+
+wire    [8:0]   level_0;
+wire    [8:0]   level_1;
+wire    [8:0]   level_2;
+wire    [8:0]   level_3;
+wire    [8:0]   level_4;
+wire    [8:0]   level_5;
+wire    [8:0]   level_6;
+wire    [8:0]   level_7;
+wire    [8:0]   level_8;
+wire    [8:0]   level_9;
+wire    [8:0]   level_10;
+wire    [8:0]   level_11;
+wire    [8:0]   level_12;
+wire    [8:0]   level_13;
+wire    [8:0]   level_14;
+wire    [8:0]   level_15;
+
+cavlc_read_levels cavlc_read_levels(
+    .clk(clk),
+    .rst_n(rst_n),
+    .ena(ena),  
+    .t1s_sel(cavlc_state[`cavlc_read_t1s_flags_bit]),
+    .prefix_sel(cavlc_state[`cavlc_read_level_prefix_bit]),
+    .suffix_sel(cavlc_state[`cavlc_read_level_suffix_bit]),
+    .calc_sel(cavlc_state[`cavlc_calc_level_bit]),
+    .TrailingOnes(TrailingOnes), 
+    .TotalCoeff(TotalCoeff),
+    .i(i),
+    .rbsp(rbsp),
+    
+    .level_0(level_0),
+    .level_1(level_1),
+    .level_2(level_2),
+    .level_3(level_3),
+    .level_4(level_4),
+    .level_5(level_5),
+    .level_6(level_6),
+    .level_7(level_7),
+    .level_8(level_8),
+    .level_9(level_9),
+    .level_10(level_10),
+    .level_11(level_11),
+    .level_12(level_12),
+    .level_13(level_13),
+    .level_14(level_14),
+    .level_15(level_15),
+    .len_comb(len_read_levels_comb)
+);
+
+//------------------------
+// cavlc_read_total_zeros
+//------------------------
+wire    [3:0]   TotalZeros_comb;
+wire    [3:0]   len_read_total_zeros_comb;
+
+cavlc_read_total_zeros cavlc_read_total_zeros(
+    .ena(ena),
+    .sel(cavlc_state[`cavlc_read_total_zeros_bit]),
+    .chroma_DC_sel(nC[5]),
+    .rbsp(rbsp[0:8]),
+    .TotalCoeff(TotalCoeff[3:0]),
+    .TotalZeros_comb(TotalZeros_comb),
+    .len_comb(len_read_total_zeros_comb)
+);
+
+//------------------------
+// read_run_before
+//------------------------
+wire    [3:0]   ZeroLeft;
+wire    [3:0]   len_read_run_befores_comb;
+
+cavlc_read_run_befores cavlc_read_run_befores(
+    .clk(clk),
+    .rst_n(rst_n),
+    .ena(ena),
+    .clr(cavlc_state[`cavlc_read_total_coeffs_bit]),
+    .sel(cavlc_state[`cavlc_read_run_befores_bit]),
+    .ZeroLeft_init(cavlc_state[`cavlc_read_total_zeros_bit]),
+    
+    .rbsp(rbsp[0:10]),
+    .i(i),
+    .TotalZeros_comb(TotalZeros_comb),
+    
+    .level_0(level_0),
+    .level_1(level_1),
+    .level_2(level_2),
+    .level_3(level_3),
+    .level_4(level_4),
+    .level_5(level_5),
+    .level_6(level_6),
+    .level_7(level_7),
+    .level_8(level_8),
+    .level_9(level_9),
+    .level_10(level_10),
+    .level_11(level_11),
+    .level_12(level_12),
+    .level_13(level_13),
+    .level_14(level_14),
+    .level_15(level_15),
+        
+    .coeff_0(coeff_0),
+    .coeff_1(coeff_1),
+    .coeff_2(coeff_2),
+    .coeff_3(coeff_3),
+    .coeff_4(coeff_4),
+    .coeff_5(coeff_5),
+    .coeff_6(coeff_6),
+    .coeff_7(coeff_7),
+    .coeff_8(coeff_8),
+    .coeff_9(coeff_9),
+    .coeff_10(coeff_10),
+    .coeff_11(coeff_11),
+    .coeff_12(coeff_12),
+    .coeff_13(coeff_13),
+    .coeff_14(coeff_14),
+    .coeff_15(coeff_15),
+    .ZeroLeft(ZeroLeft),
+    .len_comb(len_read_run_befores_comb)
+);
+
+//------------------------
+// cavlc_len_gen
+//------------------------
+wire [4:0] len_comb;
+
+cavlc_len_gen cavlc_len_gen(
+    .cavlc_state(cavlc_state),
+    .len_read_total_coeffs_comb(len_read_total_coeffs_comb),
+    .len_read_levels_comb(len_read_levels_comb),
+    .len_read_total_zeros_comb(len_read_total_zeros_comb),
+    .len_read_run_befores_comb(len_read_run_befores_comb),
+    .len_comb(len_comb)
+);
+
+//------------------------
+// fsm
+//------------------------
+cavlc_fsm cavlc_fsm(
+    .clk(clk),
+    .rst_n(rst_n),
+    .ena(ena),
+    .start(start),
+    
+    .max_coeff_num(max_coeff_num),
+    .TotalCoeff(TotalCoeff),
+    .TotalCoeff_comb(TotalCoeff_comb),
+    .TrailingOnes(TrailingOnes),
+    .TrailingOnes_comb(TrailingOnes_comb),
+    .ZeroLeft(ZeroLeft),
+    .state(cavlc_state),
+    .i(i),
+    .idle(idle),
+    .valid(valid) 
+);
+
+endmodule
diff --git a/BENCHMARK/cavlc_top/rtl/defines.v b/BENCHMARK/cavlc_top/rtl/defines.v
new file mode 100644
index 0000000..1d06a35
--- /dev/null
+++ b/BENCHMARK/cavlc_top/rtl/defines.v
@@ -0,0 +1,22 @@
+`timescale 1ns / 1ns // timescale time_unit/time_presicion
+
+`define cavlc_idle_bit     				0
+`define cavlc_read_total_coeffs_bit	1
+`define cavlc_read_t1s_flags_bit	2
+`define cavlc_read_level_prefix_bit     3
+`define cavlc_read_level_suffix_bit     4
+`define cavlc_calc_level_bit		5
+`define cavlc_read_total_zeros_bit  	6
+`define cavlc_read_run_befores_bit  	7
+
+`define cavlc_idle_s     		8'b00000001
+`define cavlc_read_total_coeffs_s     	8'b00000010
+`define cavlc_read_t1s_flags_s		8'b00000100
+`define cavlc_read_level_prefix_s     	8'b00001000
+`define cavlc_read_level_suffix_s     	8'b00010000
+`define cavlc_calc_level_s		8'b00100000
+`define cavlc_read_total_zeros_s    	8'b01000000
+`define cavlc_read_run_befores_s    	8'b10000000
+
+
+
diff --git a/BENCHMARK/cf_fft_256_8/cf_fft_256_8_yosys.blif b/BENCHMARK/cf_fft_256_8/cf_fft_256_8_yosys.blif
new file mode 100644
index 0000000..d7c4436
--- /dev/null
+++ b/BENCHMARK/cf_fft_256_8/cf_fft_256_8_yosys.blif
@@ -0,0 +1,43477 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model cf_fft_256_8
+.inputs clock_c enable_i reset_i sync_i data_0_i(0) data_0_i(1) data_0_i(2) data_0_i(3) data_0_i(4) data_0_i(5) data_0_i(6) data_0_i(7) data_0_i(8) data_0_i(9) data_0_i(10) data_0_i(11) data_0_i(12) data_0_i(13) data_0_i(14) data_0_i(15) data_1_i(0) data_1_i(1) data_1_i(2) data_1_i(3) data_1_i(4) data_1_i(5) data_1_i(6) data_1_i(7) data_1_i(8) data_1_i(9) data_1_i(10) data_1_i(11) data_1_i(12) data_1_i(13) data_1_i(14) data_1_i(15)
+.outputs sync_o data_0_o(0) data_0_o(1) data_0_o(2) data_0_o(3) data_0_o(4) data_0_o(5) data_0_o(6) data_0_o(7) data_0_o(8) data_0_o(9) data_0_o(10) data_0_o(11) data_0_o(12) data_0_o(13) data_0_o(14) data_0_o(15) data_1_o(0) data_1_o(1) data_1_o(2) data_1_o(3) data_1_o(4) data_1_o(5) data_1_o(6) data_1_o(7) data_1_o(8) data_1_o(9) data_1_o(10) data_1_o(11) data_1_o(12) data_1_o(13) data_1_o(14) data_1_o(15)
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_0 a=n1019
+.subckt in_buff A=clock_c Q=$iopadmap$clock_c
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(0) Q=n28(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(1) Q=n28(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(10) Q=n28(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(11) Q=n28(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(12) Q=n28(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(13) Q=n28(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(14) Q=n28(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(15) Q=n28(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(2) Q=n28(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(3) Q=n28(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(4) Q=n28(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(5) Q=n28(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(6) Q=n28(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(7) Q=n28(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(8) Q=n28(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_0_i(9) Q=n28(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=n2052(0) Q=data_0_o(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(1) Q=data_0_o(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(10) Q=data_0_o(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(11) Q=data_0_o(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(12) Q=data_0_o(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(13) Q=data_0_o(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(14) Q=data_0_o(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(15) Q=data_0_o(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(2) Q=data_0_o(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(3) Q=data_0_o(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(4) Q=data_0_o(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(5) Q=data_0_o(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(6) Q=data_0_o(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(7) Q=data_0_o(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(8) Q=data_0_o(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2052(9) Q=data_0_o(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=data_1_i(0) Q=n28(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(1) Q=n28(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(10) Q=n28(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(11) Q=n28(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(12) Q=n28(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(13) Q=n28(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(14) Q=n28(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(15) Q=n28(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(2) Q=n28(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(3) Q=n28(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(4) Q=n28(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(5) Q=n28(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(6) Q=n28(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(7) Q=n28(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(8) Q=n28(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=data_1_i(9) Q=n28(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=n2053(0) Q=data_1_o(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(1) Q=data_1_o(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(10) Q=data_1_o(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(11) Q=data_1_o(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(12) Q=data_1_o(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(13) Q=data_1_o(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(14) Q=data_1_o(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(15) Q=data_1_o(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(2) Q=data_1_o(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(3) Q=data_1_o(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(4) Q=data_1_o(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(5) Q=data_1_o(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(6) Q=data_1_o(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(7) Q=data_1_o(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(8) Q=data_1_o(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=n2053(9) Q=data_1_o(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=enable_i Q=n2059
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=reset_i Q=n2062
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=sync_i Q=n14(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=n1982 Q=sync_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_I2 I3=data_0_o_LUT4_O_I3 O=n2052(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_1_I2 I3=data_0_o_LUT4_O_1_I3 O=n2052(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_10_I2 I3=data_0_o_LUT4_O_10_I3 O=n2052(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(5) I1=n1993(5) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(21) I1=n1993(21) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_11_I2 I3=data_0_o_LUT4_O_11_I3 O=n2052(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(4) I1=n1993(4) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(20) I1=n1993(20) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_12_I2 I3=data_0_o_LUT4_O_12_I3 O=n2052(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(3) I1=n1993(3) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(19) I1=n1993(19) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_13_I2 I3=data_0_o_LUT4_O_13_I3 O=n2052(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(2) I1=n1993(2) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(18) I1=n1993(18) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_14_I2 I3=data_0_o_LUT4_O_14_I3 O=n2052(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(1) I1=n1993(1) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(17) I1=n1993(17) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_15_I2 I3=data_0_o_LUT4_O_15_I3 O=n2052(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(16) I1=n1993(16) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1993(0) I1=n1997(0) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1997(14) I1=n1993(14) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(30) I1=n1993(30) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_2_I2 I3=data_0_o_LUT4_O_2_I3 O=n2052(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(13) I1=n1993(13) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(29) I1=n1993(29) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_3_I2 I3=data_0_o_LUT4_O_3_I3 O=n2052(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(12) I1=n1993(12) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(28) I1=n1993(28) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_4_I2 I3=data_0_o_LUT4_O_4_I3 O=n2052(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(11) I1=n1993(11) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(27) I1=n1993(27) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_5_I2 I3=data_0_o_LUT4_O_5_I3 O=n2052(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(10) I1=n1993(10) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(26) I1=n1993(26) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_6_I2 I3=data_0_o_LUT4_O_6_I3 O=n2052(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(9) I1=n1993(9) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(25) I1=n1993(25) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_7_I2 I3=data_0_o_LUT4_O_7_I3 O=n2052(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(8) I1=n1993(8) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(24) I1=n1993(24) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_8_I2 I3=data_0_o_LUT4_O_8_I3 O=n2052(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(7) I1=n1993(7) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(23) I1=n1993(23) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_0_o_LUT4_O_9_I2 I3=data_0_o_LUT4_O_9_I3 O=n2052(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1997(6) I1=n1993(6) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(22) I1=n1993(22) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1997(15) I1=n1993(15) I2=n2001 I3=n2042(0) O=data_0_o_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1997(31) I1=n1993(31) I2=n2042(0) I3=n2001 O=data_0_o_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_I2 I3=data_1_o_LUT4_O_I3 O=n2053(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_1_I2 I3=data_1_o_LUT4_O_1_I3 O=n2053(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_10_I2 I3=data_1_o_LUT4_O_10_I3 O=n2053(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(5) I1=n2030(5) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(21) I1=n2030(21) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_11_I2 I3=data_1_o_LUT4_O_11_I3 O=n2053(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(4) I1=n2030(4) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(20) I1=n2030(20) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_12_I2 I3=data_1_o_LUT4_O_12_I3 O=n2053(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(3) I1=n2030(3) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(19) I1=n2030(19) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_13_I2 I3=data_1_o_LUT4_O_13_I3 O=n2053(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(2) I1=n2030(2) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(18) I1=n2030(18) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_14_I2 I3=data_1_o_LUT4_O_14_I3 O=n2053(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(1) I1=n2030(1) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(17) I1=n2030(17) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_15_I2 I3=data_1_o_LUT4_O_15_I3 O=n2053(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(16) I1=n2030(16) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n2030(0) I1=n2034(0) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n2034(14) I1=n2030(14) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(30) I1=n2030(30) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_2_I2 I3=data_1_o_LUT4_O_2_I3 O=n2053(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(13) I1=n2030(13) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(29) I1=n2030(29) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_3_I2 I3=data_1_o_LUT4_O_3_I3 O=n2053(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(12) I1=n2030(12) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(28) I1=n2030(28) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_4_I2 I3=data_1_o_LUT4_O_4_I3 O=n2053(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(11) I1=n2030(11) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(27) I1=n2030(27) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_5_I2 I3=data_1_o_LUT4_O_5_I3 O=n2053(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(10) I1=n2030(10) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(26) I1=n2030(26) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_6_I2 I3=data_1_o_LUT4_O_6_I3 O=n2053(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(9) I1=n2030(9) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(25) I1=n2030(25) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_7_I2 I3=data_1_o_LUT4_O_7_I3 O=n2053(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(8) I1=n2030(8) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(24) I1=n2030(24) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_8_I2 I3=data_1_o_LUT4_O_8_I3 O=n2053(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(7) I1=n2030(7) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(23) I1=n2030(23) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1019 I2=data_1_o_LUT4_O_9_I2 I3=data_1_o_LUT4_O_9_I3 O=n2053(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n2034(6) I1=n2030(6) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(22) I1=n2030(22) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n2034(15) I1=n2030(15) I2=n2038 I3=n2042(0) O=data_1_o_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n2034(31) I1=n2030(31) I2=n2042(0) I3=n2038 O=data_1_o_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1019 I1=n1000 I2=n2059 I3=n1045(0) O=n1000_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1000 I2=n2059 I3=n1045(0) O=n1000_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n1000 I3=n1008(0) O=n1000_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=n1000 D=n1000_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4557.1-4562.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1006(5) D=n966_LUT4_I3_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4563.1-4568.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1006(4) D=n966_LUT4_I3_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4563.1-4568.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1006(3) D=n966_LUT4_I3_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4563.1-4568.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1006(2) D=n966_LUT4_I3_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4563.1-4568.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1006(1) D=n966_LUT4_I3_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4563.1-4568.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1006(0) D=n966_LUT4_I3_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4563.1-4568.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1008(0) I2=n2059 I3=n1000 O=n1013_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n1008(0) D=n1013_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4569.1-4574.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1008(1) I2=n1008(0) I3=n2062 O=n1013_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1018 O=n1018_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1018_LUT4_I3_O I2=n1094(4) I3=n2085_LUT4_O_I0_LUT4_O_I0 O=n1225_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1018_LUT4_I3_O I3=n1018_LUT4_I3_O_LUT4_I2_I3 O=n1225_LUT4_I3_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1018_LUT4_I3_O I3=n1225_LUT4_I0_O O=n1225_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n2085_LUT4_O_I0_LUT4_O_I0 I1=n1094(5) I2=n1094(4) I3=n1094(6) O=n1018_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n2085_LUT4_O_I0_LUT4_O_I0 I1=n1094(4) I2=n1094(5) I3=n1018_LUT4_I3_O O=n1225_LUT4_I3_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n1018 D=n1018_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4575.1-4580.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1008(1) I3=n2062 O=n1018_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n101(31) D=n28(31) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(30) D=n28(30) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(21) D=n28(21) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(20) D=n28(20) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(19) D=n28(19) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(18) D=n28(18) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(17) D=n28(17) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(16) D=n28(16) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(15) D=n28(15) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(14) D=n28(14) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(13) D=n28(13) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(12) D=n28(12) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(29) D=n28(29) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(11) D=n28(11) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(10) D=n28(10) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(9) D=n28(9) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(8) D=n28(8) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(7) D=n28(7) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(6) D=n28(6) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(5) D=n28(5) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(4) D=n28(4) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(3) D=n28(3) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(2) D=n28(2) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(28) D=n28(28) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(1) D=n28(1) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(0) D=n28(0) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n101(27) D=n28(27) QCK=$iopadmap$clock_c QEN=n85_LUT4_I3_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3539.1-3543.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
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+.subckt ff CQZ=n1029(5) D=n949(5) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(4) D=n949(4) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(3) D=n949(3) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(2) D=n949(2) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(28) D=n942(12) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(1) D=n949(1) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(0) D=n949(0) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(27) D=n942(11) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(26) D=n942(10) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(25) D=n942(9) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(24) D=n942(8) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(23) D=n942(7) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1029(22) D=n942(6) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1033(31) D=n942(15) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1033(30) D=n942(14) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1033(21) D=n942(5) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1033(20) D=n942(4) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1033(19) D=n942(3) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(18) D=n942(2) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(17) D=n942(1) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(16) D=n942(0) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(15) D=n949(15) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(14) D=n949(14) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(13) D=n949(13) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(12) D=n949(12) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(29) D=n942(13) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(11) D=n949(11) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(10) D=n949(10) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(9) D=n949(9) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(8) D=n949(8) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(7) D=n949(7) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(6) D=n949(6) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(5) D=n949(5) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(4) D=n949(4) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(3) D=n949(3) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(2) D=n949(2) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(28) D=n942(12) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(1) D=n949(1) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(0) D=n949(0) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(27) D=n942(11) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(26) D=n942(10) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(25) D=n942(9) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(24) D=n942(8) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(23) D=n942(7) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1033(22) D=n942(6) QCK=$iopadmap$clock_c QEN=n1013_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4591.1-4595.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1033(15) I1=n1029(15) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(14) I1=n1029(14) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(5) I1=n1029(5) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(4) I1=n1029(4) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(3) I1=n1029(3) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(2) I1=n1029(2) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(1) I1=n1029(1) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1029(0) I1=n1033(0) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1033(13) I1=n1029(13) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(12) I1=n1029(12) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(11) I1=n1029(11) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(10) I1=n1029(10) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(9) I1=n1029(9) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(8) I1=n1029(8) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(7) I1=n1029(7) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(6) I1=n1029(6) I2=n1037 I3=n1078(0) O=n1037_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1033(31) I1=n1029(31) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(30) I1=n1029(30) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(21) I1=n1029(21) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(20) I1=n1029(20) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(19) I1=n1029(19) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(18) I1=n1029(18) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(17) I1=n1029(17) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(16) I1=n1029(16) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(29) I1=n1029(29) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(28) I1=n1029(28) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(27) I1=n1029(27) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(26) I1=n1029(26) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(25) I1=n1029(25) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(24) I1=n1029(24) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(23) I1=n1029(23) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1033(22) I1=n1029(22) I2=n1078(0) I3=n1037 O=n1037_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n1037 D=n1037_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4601.1-4606.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1008(0) O=n1037_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n1045(0) D=n1050_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4613.1-4618.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1045(0) I2=n1008(1) I3=n2062 O=n1050_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=n105(31) D=n28(31) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(30) D=n28(30) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(21) D=n28(21) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(20) D=n28(20) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(19) D=n28(19) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(18) D=n28(18) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(17) D=n28(17) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(16) D=n28(16) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(15) D=n28(15) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(14) D=n28(14) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(13) D=n28(13) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(12) D=n28(12) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(29) D=n28(29) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(11) D=n28(11) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(10) D=n28(10) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(9) D=n28(9) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(8) D=n28(8) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(7) D=n28(7) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(6) D=n28(6) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(5) D=n28(5) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(4) D=n28(4) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(3) D=n28(3) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(2) D=n28(2) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(28) D=n28(28) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(1) D=n28(1) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(0) D=n28(0) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(27) D=n28(27) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(26) D=n28(26) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(25) D=n28(25) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(24) D=n28(24) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(23) D=n28(23) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n105(22) D=n28(22) QCK=$iopadmap$clock_c QEN=n85_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3549.1-3553.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1066(31) D=n942(15) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4619.1-4623.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1066(30) D=n942(14) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4619.1-4623.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1066(21) D=n942(5) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4619.1-4623.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1066(20) D=n942(4) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1066(3) D=n949(3) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1066(26) D=n942(10) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1066(25) D=n942(9) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1070(17) D=n942(1) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1070(15) D=n949(15) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1070(14) D=n949(14) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1070(13) D=n949(13) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1070(12) D=n949(12) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1070(29) D=n942(13) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(11) D=n949(11) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1070(10) D=n949(10) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(9) D=n949(9) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(8) D=n949(8) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(7) D=n949(7) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(6) D=n949(6) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(5) D=n949(5) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(4) D=n949(4) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(3) D=n949(3) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(2) D=n949(2) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(28) D=n942(12) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(1) D=n949(1) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(0) D=n949(0) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(27) D=n942(11) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(26) D=n942(10) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(25) D=n942(9) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(24) D=n942(8) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(23) D=n942(7) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1070(22) D=n942(6) QCK=$iopadmap$clock_c QEN=n1000_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4629.1-4633.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1070(15) I1=n1066(15) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(14) I1=n1066(14) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(5) I1=n1066(5) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(4) I1=n1066(4) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(3) I1=n1066(3) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(2) I1=n1066(2) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(1) I1=n1066(1) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1066(0) I1=n1070(0) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1070(13) I1=n1066(13) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(12) I1=n1066(12) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(11) I1=n1066(11) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(10) I1=n1066(10) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(9) I1=n1066(9) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(8) I1=n1066(8) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(7) I1=n1066(7) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(6) I1=n1066(6) I2=n1074 I3=n1078(0) O=n1074_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1070(31) I1=n1066(31) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(30) I1=n1066(30) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(21) I1=n1066(21) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(20) I1=n1066(20) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(19) I1=n1066(19) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(18) I1=n1066(18) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(17) I1=n1066(17) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(16) I1=n1066(16) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(29) I1=n1066(29) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(28) I1=n1066(28) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(27) I1=n1066(27) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(26) I1=n1066(26) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(25) I1=n1066(25) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(24) I1=n1066(24) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(23) I1=n1066(23) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1070(22) I1=n1066(22) I2=n1078(0) I3=n1074 O=n1074_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n1074 D=n1074_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4639.1-4644.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1045(0) O=n1074_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n1078(0) D=n1083_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4645.1-4650.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1018_LUT4_I3_O I3=n1083_ff_CQZ_D_LUT4_O_I3 O=n1083_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1006(1) I1=n1006(0) I2=n1083_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1078(0) O=n1083_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n1006(2) I1=n1006(3) I2=n1006(4) I3=n1006(5) O=n1083_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=n1094(6) D=n1225_LUT4_I3_O(6) QCK=$iopadmap$clock_c QEN=n2085 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4651.1-4656.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1094(5) D=n1225_LUT4_I3_O(5) QCK=$iopadmap$clock_c QEN=n2085 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4651.1-4656.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1094(4) D=n1225_LUT4_I3_O(4) QCK=$iopadmap$clock_c QEN=n2085 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4651.1-4656.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1094(3) D=n1225_LUT4_I3_O(3) QCK=$iopadmap$clock_c QEN=n2085 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4651.1-4656.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1094(2) D=n1225_LUT4_I3_O(2) QCK=$iopadmap$clock_c QEN=n2085 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4651.1-4656.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1094(1) D=n1225_LUT4_I3_O(1) QCK=$iopadmap$clock_c QEN=n2085 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4651.1-4656.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n105(15) I1=n101(15) I2=n109 I3=n113(0) O=n109_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(14) I1=n101(14) I2=n109 I3=n113(0) O=n109_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(5) I1=n101(5) I2=n109 I3=n113(0) O=n109_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(4) I1=n101(4) I2=n109 I3=n113(0) O=n109_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(3) I1=n101(3) I2=n109 I3=n113(0) O=n109_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(2) I1=n101(2) I2=n109 I3=n113(0) O=n109_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(1) I1=n101(1) I2=n109 I3=n113(0) O=n109_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n101(0) I1=n105(0) I2=n109 I3=n113(0) O=n109_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n105(13) I1=n101(13) I2=n109 I3=n113(0) O=n109_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(12) I1=n101(12) I2=n109 I3=n113(0) O=n109_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(11) I1=n101(11) I2=n109 I3=n113(0) O=n109_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(10) I1=n101(10) I2=n109 I3=n113(0) O=n109_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(9) I1=n101(9) I2=n109 I3=n113(0) O=n109_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(8) I1=n101(8) I2=n109 I3=n113(0) O=n109_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(7) I1=n101(7) I2=n109 I3=n113(0) O=n109_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(6) I1=n101(6) I2=n109 I3=n113(0) O=n109_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n105(31) I1=n101(31) I2=n113(0) I3=n109 O=n109_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(30) I1=n101(30) I2=n113(0) I3=n109 O=n109_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(21) I1=n101(21) I2=n113(0) I3=n109 O=n109_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(20) I1=n101(20) I2=n113(0) I3=n109 O=n109_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(19) I1=n101(19) I2=n113(0) I3=n109 O=n109_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(18) I1=n101(18) I2=n113(0) I3=n109 O=n109_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(17) I1=n101(17) I2=n113(0) I3=n109 O=n109_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(16) I1=n101(16) I2=n113(0) I3=n109 O=n109_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(29) I1=n101(29) I2=n113(0) I3=n109 O=n109_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(28) I1=n101(28) I2=n113(0) I3=n109 O=n109_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(27) I1=n101(27) I2=n113(0) I3=n109 O=n109_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(26) I1=n101(26) I2=n113(0) I3=n109 O=n109_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(25) I1=n101(25) I2=n113(0) I3=n109 O=n109_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(24) I1=n101(24) I2=n113(0) I3=n109 O=n109_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(23) I1=n101(23) I2=n113(0) I3=n109 O=n109_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n105(22) I1=n101(22) I2=n113(0) I3=n109 O=n109_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n109 D=n109_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3559.1-3564.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n80(0) O=n109_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n2085_LUT4_O_I0 I1=n1098(0) I2=n1018 I3=n2062 O=n1107_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=n1098(0) D=n1107_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4657.1-4662.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1107 I2=n2085_LUT4_O_I0 I3=n2062 O=n1195_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n1107 D=n1107_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4663.1-4668.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(15) D=n1113_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(14) D=n1113_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(5) D=n1113_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(4) D=n1113_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(3) D=n1113_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(2) D=n1113_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(1) D=n1113_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(0) D=n1113_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(13) D=n1113_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(12) D=n1113_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(11) D=n1113_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(10) D=n1113_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(9) D=n1113_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(8) D=n1113_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(7) D=n1113_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1113(6) D=n1113_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4669.1-4674.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_O I3=n1037_LUT4_I2_O O=n1113_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_1_O I3=n1037_LUT4_I2_1_O O=n1113_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_10_O I3=n1037_LUT4_I2_10_O O=n1113_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_11_O I3=n1037_LUT4_I2_11_O O=n1113_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_12_O I3=n1037_LUT4_I2_12_O O=n1113_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_13_O I3=n1037_LUT4_I2_13_O O=n1113_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_14_O I3=n1037_LUT4_I2_14_O O=n1113_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_15_O I3=n1037_LUT4_I2_15_O O=n1113_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_2_O I3=n1037_LUT4_I2_2_O O=n1113_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_3_O I3=n1037_LUT4_I2_3_O O=n1113_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_4_O I3=n1037_LUT4_I2_4_O O=n1113_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_5_O I3=n1037_LUT4_I2_5_O O=n1113_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_6_O I3=n1037_LUT4_I2_6_O O=n1113_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_7_O I3=n1037_LUT4_I2_7_O O=n1113_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_8_O I3=n1037_LUT4_I2_8_O O=n1113_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1037_LUT4_I3_9_O I3=n1037_LUT4_I2_9_O O=n1113_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=n1119(15) D=n1119_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(14) D=n1119_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(5) D=n1119_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(4) D=n1119_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(3) D=n1119_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(2) D=n1119_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(1) D=n1119_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(0) D=n1119_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(13) D=n1119_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(12) D=n1119_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(11) D=n1119_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(10) D=n1119_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(9) D=n1119_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(8) D=n1119_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(7) D=n1119_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1119(6) D=n1119_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4675.1-4680.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_O I3=n1074_LUT4_I2_O O=n1119_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_1_O I3=n1074_LUT4_I2_1_O O=n1119_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_10_O I3=n1074_LUT4_I2_10_O O=n1119_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_11_O I3=n1074_LUT4_I2_11_O O=n1119_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_12_O I3=n1074_LUT4_I2_12_O O=n1119_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_13_O I3=n1074_LUT4_I2_13_O O=n1119_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_14_O I3=n1074_LUT4_I2_14_O O=n1119_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_15_O I3=n1074_LUT4_I2_15_O O=n1119_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_2_O I3=n1074_LUT4_I2_2_O O=n1119_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_3_O I3=n1074_LUT4_I2_3_O O=n1119_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_4_O I3=n1074_LUT4_I2_4_O O=n1119_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_5_O I3=n1074_LUT4_I2_5_O O=n1119_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_6_O I3=n1074_LUT4_I2_6_O O=n1119_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_7_O I3=n1074_LUT4_I2_7_O O=n1119_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_8_O I3=n1074_LUT4_I2_8_O O=n1119_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1074_LUT4_I3_9_O I3=n1074_LUT4_I2_9_O O=n1119_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1125(7) I3=n2062 O=n1129_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1125(6) I3=n2062 O=n1129_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1125(5) I3=n2062 O=n1129_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1125(4) I3=n2062 O=n1129_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1125(3) I3=n2062 O=n1129_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1125(2) I3=n2062 O=n1129_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1125(1) I3=n2062 O=n1129_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1125(0) I3=n2062 O=n1129_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1125(7) D=n1125_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4681.1-4686.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1125(6) D=n1125_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4681.1-4686.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1125(5) D=n1125_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4681.1-4686.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1125(4) D=n1125_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4681.1-4686.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1125(3) D=n1125_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4681.1-4686.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1125(2) D=n1125_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4681.1-4686.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1125(1) D=n1125_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4681.1-4686.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1125(0) D=n1125_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4681.1-4686.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(15) I3=n2062 O=n1125_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(14) I3=n2062 O=n1125_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(13) I3=n2062 O=n1125_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(12) I3=n2062 O=n1125_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(11) I3=n2062 O=n1125_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(10) I3=n2062 O=n1125_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(9) I3=n2062 O=n1125_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(8) I3=n2062 O=n1125_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1129(7) D=n1129_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4687.1-4692.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1129(6) D=n1129_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4687.1-4692.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1129(5) D=n1129_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4687.1-4692.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1129(4) D=n1129_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4687.1-4692.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1129(3) D=n1129_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4687.1-4692.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1129(2) D=n1129_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4687.1-4692.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1129(1) D=n1129_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4687.1-4692.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1129(0) D=n1129_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4687.1-4692.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1133(7) I3=n2062 O=n1137_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1133(6) I3=n2062 O=n1137_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1133(5) I3=n2062 O=n1137_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1133(4) I3=n2062 O=n1137_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1133(3) I3=n2062 O=n1137_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1133(2) I3=n2062 O=n1137_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1133(1) I3=n2062 O=n1137_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1133(0) I3=n2062 O=n1137_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1133(7) D=n1133_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4693.1-4698.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1133(6) D=n1133_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4693.1-4698.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1133(5) D=n1133_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4693.1-4698.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1133(4) D=n1133_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4693.1-4698.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1133(3) D=n1133_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4693.1-4698.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1133(2) D=n1133_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4693.1-4698.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1133(1) D=n1133_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4693.1-4698.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1133(0) D=n1133_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4693.1-4698.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(7) I3=n2062 O=n1133_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(6) I3=n2062 O=n1133_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(5) I3=n2062 O=n1133_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(4) I3=n2062 O=n1133_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(3) I3=n2062 O=n1133_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(2) I3=n2062 O=n1133_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(1) I3=n2062 O=n1133_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1113(0) I3=n2062 O=n1133_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1137(7) D=n1137_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4699.1-4704.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1137(6) D=n1137_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4699.1-4704.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1137(5) D=n1137_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4699.1-4704.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1137(4) D=n1137_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4699.1-4704.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1137(3) D=n1137_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4699.1-4704.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1137(2) D=n1137_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4699.1-4704.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1137(1) D=n1137_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4699.1-4704.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1137(0) D=n1137_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4699.1-4704.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(15) D=n1140_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(14) D=n1140_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(5) D=n1140_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(4) D=n1140_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(3) D=n1140_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(2) D=n1140_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(1) D=n1140_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(0) D=n1140_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(13) D=n1140_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(12) D=n1140_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(11) D=n1140_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(10) D=n1140_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(9) D=n1140_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(8) D=n1140_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(7) D=n1140_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1140(6) D=n1140_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4705.1-4724.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1094(3) I1=n1094(4) I2=n1094(5) I3=n1094(6) O=n1140_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=n1094(6) I1=n1094(3) I2=n1094(5) I3=n1094(4) O=n1140_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101011101
+.subckt LUT4 I0=n1094(4) I1=n1094(6) I2=n1094(5) I3=n1094(3) O=n1140_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010000
+.subckt LUT4 I0=n1019 I1=n1094(3) I2=n1094(4) I3=n1094(5) O=n1140_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1094(3) I1=n1094(5) I2=n1094(6) I3=n1094(4) O=n1140_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011110000000
+.subckt LUT4 I0=n1094(5) I1=n1094(6) I2=n1094(3) I3=n1094(4) O=n1140_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100100100111010
+.subckt LUT4 I0=n1094(6) I1=n1094(3) I2=n1094(5) I3=n1094(4) O=n1140_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100001100
+.subckt LUT4 I0=n1094(5) I1=n1094(6) I2=n1094(4) I3=n1094(3) O=n1140_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001111111010
+.subckt LUT4 I0=n1094(4) I1=n1094(3) I2=n1094(5) I3=n1094(6) O=n1140_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001110000101111
+.subckt LUT4 I0=n1094(3) I1=n1094(5) I2=n1094(4) I3=n1094(6) O=n1140_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=n1094(5) I1=n1094(6) I2=n1094(3) I3=n1094(4) O=n1140_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110000010011
+.subckt LUT4 I0=n1094(6) I1=n1094(3) I2=n1094(5) I3=n1094(4) O=n1140_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001111101101
+.subckt LUT4 I0=n1094(3) I1=n1094(5) I2=n1094(6) I3=n1094(4) O=n1140_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001001100101101
+.subckt LUT4 I0=n1094(3) I1=n1094(5) I2=n1094(6) I3=n1094(4) O=n1140_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101000011101011
+.subckt LUT4 I0=n1094(6) I1=n1094(5) I2=n1094(3) I3=n1094(4) O=n1140_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111110
+.subckt LUT4 I0=n1094(3) I1=n1094(5) I2=n1094(6) I3=n1094(4) O=n1140_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000100000010
+.subckt ff CQZ=n1148(7) D=n1148_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4725.1-4730.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1148(6) D=n1148_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4725.1-4730.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1148(5) D=n1148_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4725.1-4730.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1148(4) D=n1148_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4725.1-4730.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1148(3) D=n1148_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4725.1-4730.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1148(2) D=n1148_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4725.1-4730.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1148(1) D=n1148_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4725.1-4730.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1148(0) D=n1148_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4725.1-4730.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n1148_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_1_I0 I1=n1148_ff_CQZ_D_LUT4_O_1_I1 I2=n2062 I3=n1148_ff_CQZ_D_LUT4_O_1_I3 O=n1148_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_2_I1 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I3=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 I2=n1140(14) I3=n1119(15) O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(15) I3=n1119(14) O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(15) I1=n1140(14) I2=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I3=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0 I1=n1140(13) I2=n1119(15) I3=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(15) I1=n1140(13) I2=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1119(13) I1=n1140(15) I2=n1119(14) I3=n1140(14) O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1140(14) I2=n1119(13) I3=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n1119(15) I1=n1140(13) I2=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0 O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=n1140(13) I2=n1119(14) I3=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(12) I1=n1140(15) I2=n1119(13) I3=n1140(14) O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(12) I1=n1119(13) I2=n1140(14) I3=n1140(15) O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1119(14) I1=n1140(14) I2=n1119(15) I3=n1140(15) O=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_2_I1 I2=n1148_ff_CQZ_D_LUT4_O_2_I2 I3=n2062 O=n1148_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1148_ff_CQZ_D_LUT4_O_3_I3 O=n1148_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I2=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1148_ff_CQZ_D_LUT4_O_4_I3 O=n1148_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_5_I1 I1=n1148_ff_CQZ_D_LUT4_O_5_I3 I2=n1148_ff_CQZ_D_LUT4_O_5_I2 I3=n1148_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1148_ff_CQZ_D_LUT4_O_5_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I3 O=n1148_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_5_I1 I1=n1148_ff_CQZ_D_LUT4_O_5_I3 I2=n1148_ff_CQZ_D_LUT4_O_5_I2 I3=n1148_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n1148_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n1140(8) I3=n1119(15) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(10) I3=n1119(12) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(10) I1=n1140(12) I2=n1119(11) I3=n1140(11) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(8) I1=n1140(14) I2=n1119(9) I3=n1140(13) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(10) I1=n1140(13) I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1119(8) I1=n1119(9) I2=n1140(13) I3=n1140(14) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1119(8) I1=n1140(15) I2=n1119(9) I3=n1140(14) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1140(10) I3=n1119(13) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(11) I1=n1140(12) I2=n1119(12) I3=n1140(11) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1140(8) I1=n1119(15) I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(9) I3=n1119(14) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(11) I3=n1119(11) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n1140(10) I3=n1119(14) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1140(13) I3=n1119(11) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(9) I1=n1140(15) I2=n1119(10) I3=n1140(14) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n1140(13) I2=n1119(10) I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(8) I1=n1119(9) I2=n1140(14) I3=n1140(15) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n1140(13) I3=n1119(10) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 I2=n1140(9) I3=n1119(15) O=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1140(9) I2=n1119(15) I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n1140(10) I2=n1119(13) I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1140(12) I2=n1119(12) I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n1140(10) I2=n1119(14) I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(12) I1=n1140(12) I2=n1119(13) I3=n1140(11) O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(12) I1=n1119(13) I2=n1140(11) I3=n1140(12) O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n1140(10) I3=n1119(15) O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1140(13) I3=n1119(12) O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(10) I1=n1140(15) I2=n1119(11) I3=n1140(14) O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=n1140(13) I2=n1119(11) I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1140(15) I2=n1140(14) I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1148_ff_CQZ_D_LUT4_O_6_I3 O=n1148_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(9) I3=n1119(13) O=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1148_ff_CQZ_D_LUT4_O_7_I3 O=n1148_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=n1019 I1=n1140(8) I2=n1119(10) I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1119(8) I1=n1140(11) I2=n1119(9) I3=n1140(10) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(10) I1=n1140(9) I2=n1119(11) I3=n1140(8) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000111
+.subckt LUT4 I0=n1119(8) I1=n1119(9) I2=n1140(8) I3=n1140(9) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1140(10) I2=n1119(8) I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=n1119(9) I1=n1140(9) I2=n1140(8) I3=n1119(10) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1140(8) I1=n1140(9) I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1119(10) I3=n1119(9) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1119(13) I1=n1140(8) I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n1119(8) I1=n1140(13) I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1140(8) I1=n1119(13) I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(9) I3=n1119(12) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(10) I3=n1119(10) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(11) I3=n1119(9) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(8) I1=n1140(12) I2=n1119(9) I3=n1140(11) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1119(8) I3=n1140(13) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(10) I3=n1119(11) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(9) I1=n1140(12) I2=n1119(10) I3=n1140(11) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(12) I3=n1119(9) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(8) I3=n1119(14) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1119(12) I1=n1140(8) I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1119(12) I3=n1140(8) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1119(8) I1=n1119(9) I2=n1140(11) I3=n1140(10) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(9) I3=n1119(11) O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(13) I1=n1140(8) I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n1148_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n1148_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_2_I1 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n1140(10) I2=n1119(15) I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(13) I1=n1140(12) I2=n1119(14) I3=n1140(11) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(13) I1=n1119(14) I2=n1140(11) I3=n1140(12) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1119(14) I1=n1140(12) I2=n1119(15) I3=n1140(11) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1140(13) I3=n1119(13) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(11) I1=n1140(15) I2=n1119(12) I3=n1140(14) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=n1140(13) I2=n1119(12) I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(10) I1=n1119(11) I2=n1140(14) I3=n1140(15) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1119(14) I1=n1119(15) I2=n1140(11) I3=n1140(12) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1119(15) I1=n1140(12) I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1140(13) I2=n1119(13) I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(11) I1=n1119(12) I2=n1140(14) I3=n1140(15) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=n1140(13) I3=n1119(14) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1119(15) I3=n1140(12) O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1148_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1148_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n1154(7) D=n1154_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4731.1-4736.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1154(6) D=n1154_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4731.1-4736.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1154(5) D=n1154_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4731.1-4736.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1154(4) D=n1154_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4731.1-4736.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1154(3) D=n1154_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4731.1-4736.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1154(2) D=n1154_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4731.1-4736.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1154(1) D=n1154_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4731.1-4736.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1154(0) D=n1154_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4731.1-4736.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n1154_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_1_I1 I2=n1154_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n1154_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=n1154_ff_CQZ_D_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=n1154_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I3=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 O=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I2=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n2062 I1=n1154_ff_CQZ_D_LUT4_O_2_I1 I2=n1154_ff_CQZ_D_LUT4_O_2_I2 I3=n1154_ff_CQZ_D_LUT4_O_2_I3 O=n1154_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_1_I1 I1=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I2=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 I3=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101111110010
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1119(7) I1=n1140(6) I2=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1119(6) I3=n1140(7) O=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=n1140(7) I2=n1119(7) I3=n1154_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1140(7) I3=n1119(5) O=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I2=n1119(5) I3=n1140(7) O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(6) I3=n1119(6) O=n1154_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(7) I1=n1140(6) I2=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n2062 I1=n1154_ff_CQZ_D_LUT4_O_3_I1 I2=n1154_ff_CQZ_D_LUT4_O_3_I2 I3=n1154_ff_CQZ_D_LUT4_O_3_I3 O=n1154_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2 I2=n1154_ff_CQZ_D_LUT4_O_4_I3 I3=n1154_ff_CQZ_D_LUT4_O_4_I1 O=n1154_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1154_ff_CQZ_D_LUT4_O_3_I2 I3=n1154_ff_CQZ_D_LUT4_O_3_I3 O=n1154_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1154_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 I3=n1154_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 O=n1154_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1154_ff_CQZ_D_LUT4_O_4_I1 I2=n1154_ff_CQZ_D_LUT4_O_4_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I3 O=n1154_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_4_I1 I1=n1154_ff_CQZ_D_LUT4_O_4_I3 I2=n1154_ff_CQZ_D_LUT4_O_4_I2 I3=n1154_ff_CQZ_D_LUT4_O_3_I3 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I1=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I2=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1119(7) I2=n1140(1) I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I1=n1140(2) I2=n1119(5) I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(3) I1=n1119(4) I2=n1140(4) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n1140(2) I2=n1119(6) I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(4) I1=n1140(4) I2=n1119(5) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(4) I1=n1119(5) I2=n1140(4) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 I2=n1119(7) I3=n1140(1) O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n1140(2) I3=n1119(6) O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1140(5) I3=n1119(3) O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n1119(1) I3=n1140(6) O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(7) I3=n1119(0) O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I1=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1154_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1154_ff_CQZ_D_LUT4_O_5_I3 O=n1154_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I2=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I3=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I2=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I3=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 O=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1154_ff_CQZ_D_LUT4_O_6_I3 O=n1154_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I1 I1=n1154_ff_CQZ_D_LUT4_O_7_I3 I2=n1154_ff_CQZ_D_LUT4_O_7_I2 I3=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1140(0) I1=n1119(7) I2=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1119(6) I3=n1140(1) O=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n2062 I1=n1154_ff_CQZ_D_LUT4_O_7_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I3 O=n1154_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I1 I1=n1154_ff_CQZ_D_LUT4_O_7_I3 I2=n1154_ff_CQZ_D_LUT4_O_7_I2 I3=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1119(4) I3=n1140(0) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1119(3) I3=n1140(1) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(0) I1=n1119(1) I2=n1140(3) I3=n1140(2) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1119(5) I1=n1140(0) I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(2) I3=n1119(2) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1119(4) I1=n1140(0) I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011100010001
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011101110000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1119(1) I3=n1140(1) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(2) I3=n1119(0) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1140(1) I1=n1119(2) I2=n1119(3) I3=n1140(0) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(0) I1=n1140(3) I2=n1119(1) I3=n1140(2) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011111100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(0) I3=n1119(2) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1140(1) I1=n1119(0) I2=n1119(1) I3=n1140(0) O=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1140(0) I1=n1119(5) I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1119(4) I3=n1140(1) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1119(0) I1=n1140(6) I2=n1119(1) I3=n1140(5) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(2) I1=n1140(4) I2=n1119(3) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(2) I3=n1119(4) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1119(0) I3=n1140(5) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(4) I3=n1119(1) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(0) I3=n1119(6) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(5) I1=n1140(0) I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n1119(0) I1=n1140(5) I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(2) I3=n1119(3) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(1) I1=n1140(4) I2=n1119(2) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(4) I3=n1119(0) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(3) I3=n1119(1) O=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1140(2) I3=n1119(5) O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(3) I1=n1140(4) I2=n1119(4) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1119(0) I1=n1140(7) I2=n1119(1) I3=n1140(6) O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(5) I3=n1119(2) O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(0) I1=n1119(1) I2=n1140(6) I3=n1140(5) O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I1=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I2=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n1140(0) I3=n1119(7) O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(4) I3=n1119(2) O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I1=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 I2=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I3=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 I3=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1119(5) I3=n1140(1) O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1119(7) I3=n1140(4) O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=n1140(7) I3=n1119(3) O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(6) I3=n1119(4) O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(5) I3=n1119(5) O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1140(5) I3=n1119(6) O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1140(7) I1=n1119(4) I2=n1119(5) I3=n1140(6) O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(5) I3=n1119(7) O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n1140(5) I2=n1119(6) I3=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1119(5) I2=n1140(7) I3=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_3_I2 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110001110001
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1140(2) I2=n1119(7) I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(5) I1=n1140(4) I2=n1119(6) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(5) I1=n1119(6) I2=n1140(4) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1119(6) I1=n1140(4) I2=n1119(7) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1140(7) I1=n1119(3) I2=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1119(3) I3=n1140(6) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1140(2) I3=n1119(7) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(3) I1=n1140(6) I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1119(2) I3=n1140(7) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(5) I3=n1119(4) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1140(5) I2=n1119(3) I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1140(7) I1=n1119(1) I2=n1119(2) I3=n1140(6) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1140(7) I1=n1119(1) I2=n1119(2) I3=n1140(6) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1119(6) I1=n1119(7) I2=n1140(4) I3=n1140(3) O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1119(7) I1=n1140(4) I2=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=n1154_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1154_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt ff CQZ=n1159(7) D=n1159_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4737.1-4742.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1159(6) D=n1159_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4737.1-4742.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1159(5) D=n1159_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4737.1-4742.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1159(4) D=n1159_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4737.1-4742.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1159(3) D=n1159_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4737.1-4742.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1159(2) D=n1159_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4737.1-4742.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1159(1) D=n1159_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4737.1-4742.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1159(0) D=n1159_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4737.1-4742.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1159_ff_CQZ_D_LUT4_O_I1 I2=n1154(7) I3=n1148(7) O=n1159_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1159_ff_CQZ_D_LUT4_O_1_I1 I2=n1154(6) I3=n1148(6) O=n1159_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1148(5) I2=n1154(5) I3=n1159_ff_CQZ_D_LUT4_O_2_I1 O=n1159_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1159_ff_CQZ_D_LUT4_O_2_I1 I2=n1154(5) I3=n1148(5) O=n1159_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1148(4) I2=n1154(4) I3=n1159_ff_CQZ_D_LUT4_O_3_I1 O=n1159_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1159_ff_CQZ_D_LUT4_O_3_I1 I2=n1154(4) I3=n1148(4) O=n1159_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1148(3) I2=n1154(3) I3=n1159_ff_CQZ_D_LUT4_O_4_I1 O=n1159_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1159_ff_CQZ_D_LUT4_O_4_I1 I2=n1154(3) I3=n1148(3) O=n1159_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1148(2) I2=n1154(2) I3=n1159_ff_CQZ_D_LUT4_O_5_I1 O=n1159_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1159_ff_CQZ_D_LUT4_O_5_I1 I2=n1154(2) I3=n1148(2) O=n1159_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1154(1) I1=n1148(1) I2=n1148(0) I3=n1154(0) O=n1159_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1159_ff_CQZ_D_LUT4_O_6_I3 O=n1159_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1148(0) I1=n1154(0) I2=n1154(1) I3=n1148(1) O=n1159_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n1148(0) I2=n1154(0) I3=n2062 O=n1159_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1148(6) I2=n1154(6) I3=n1159_ff_CQZ_D_LUT4_O_1_I1 O=n1159_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=n1165(7) D=n1165_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4743.1-4748.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1165(6) D=n1165_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4743.1-4748.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1165(5) D=n1165_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4743.1-4748.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1165(4) D=n1165_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4743.1-4748.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1165(3) D=n1165_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4743.1-4748.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1165(2) D=n1165_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4743.1-4748.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1165(1) D=n1165_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4743.1-4748.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1165(0) D=n1165_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4743.1-4748.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n1165_ff_CQZ_D_LUT4_O_I3 O=n1165_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_1_I1 I2=n1165_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n1165_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_2_I2 I2=n1165_ff_CQZ_D_LUT4_O_2_I3 I3=n1165_ff_CQZ_D_LUT4_O_2_I1 O=n1165_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1165_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n1165_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1165_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1165_ff_CQZ_D_LUT4_O_2_I1 I2=n1165_ff_CQZ_D_LUT4_O_2_I2 I3=n1165_ff_CQZ_D_LUT4_O_2_I3 O=n1165_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 I2=n1119(12) I3=n1140(6) O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1140(5) I2=n1119(12) I3=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(13) I1=n1140(4) I2=n1119(14) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(13) I1=n1119(14) I2=n1140(4) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1119(14) I1=n1140(5) I2=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1119(13) I1=n1140(6) I2=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I3=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(4) I3=n1119(15) O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1119(15) I3=n1140(2) O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1119(15) I1=n1140(3) I2=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(4) I3=n1119(14) O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(5) I3=n1119(13) O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I2=n1140(6) I3=n1119(12) O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(7) I3=n1119(11) O=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1119(13) I3=n1140(6) O=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n1119(15) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(7) I3=n1119(12) O=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1140(5) I3=n1119(15) O=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(14) I1=n1140(5) I2=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1165_ff_CQZ_D_LUT4_O_3_I3 O=n1165_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1165_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1165_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=n1119(11) I3=n1140(6) O=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I2=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I3=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1165_ff_CQZ_D_LUT4_O_4_I3 O=n1165_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_5_I1 I1=n1165_ff_CQZ_D_LUT4_O_5_I3 I2=n1165_ff_CQZ_D_LUT4_O_5_I2 I3=n1165_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1165_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1165_ff_CQZ_D_LUT4_O_5_I1 I2=n1165_ff_CQZ_D_LUT4_O_5_I2 I3=n1165_ff_CQZ_D_LUT4_O_5_I3 O=n1165_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_5_I1 I1=n1165_ff_CQZ_D_LUT4_O_5_I3 I2=n1165_ff_CQZ_D_LUT4_O_5_I2 I3=n1165_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_6_I3 I2=n1165_ff_CQZ_D_LUT4_O_6_I2 I3=n1165_ff_CQZ_D_LUT4_O_6_I1 O=n1165_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1119(10) I3=n1140(6) O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1140(5) I2=n1119(10) I3=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(11) I1=n1140(4) I2=n1119(12) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(11) I1=n1119(12) I2=n1140(4) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(7) I3=n1119(9) O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1119(11) I1=n1140(6) I2=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1140(5) I2=n1119(11) I3=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(12) I1=n1119(13) I2=n1140(4) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(7) I3=n1119(10) O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1119(15) I2=n1140(2) I3=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1119(14) I3=n1140(1) O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1140(5) I3=n1119(12) O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n2062 I1=n1165_ff_CQZ_D_LUT4_O_6_I1 I2=n1165_ff_CQZ_D_LUT4_O_6_I2 I3=n1165_ff_CQZ_D_LUT4_O_6_I3 O=n1165_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1165_ff_CQZ_D_LUT4_O_7_I1 I3=n1165_ff_CQZ_D_LUT4_O_7_I2 O=n1165_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=n1119(9) I3=n1140(6) O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1140(5) I2=n1119(9) I3=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(10) I1=n1140(4) I2=n1119(11) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(10) I1=n1119(11) I2=n1140(4) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(7) I3=n1119(8) O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1119(10) I1=n1140(6) I2=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1140(1) I1=n1119(15) I2=n1119(14) I3=n1140(2) O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1140(5) I3=n1119(11) O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(12) I1=n1140(4) I2=n1119(13) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1119(15) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2 I3=n2062 O=n1165_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1119(8) I1=n1119(9) I2=n1140(4) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1119(8) I1=n1140(4) I2=n1119(9) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=n1140(2) I2=n1119(9) I3=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1140(1) I1=n1119(10) I2=n1119(11) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1140(2) I3=n1119(10) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1119(8) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=n1140(2) I3=n1119(9) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1119(10) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1119(9) I3=n1140(1) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1140(3) I3=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1119(10) I3=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n1119(8) I1=n1140(1) I2=n1119(9) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(2) I3=n1119(8) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1140(1) I1=n1119(10) I2=n1119(11) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1140(6) I2=n1119(8) I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1140(5) I2=n1119(8) I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(9) I1=n1140(4) I2=n1119(10) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(9) I1=n1119(10) I2=n1140(4) I3=n1140(3) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1140(2) I2=n1119(10) I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1140(1) I1=n1119(11) I2=n1119(12) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1140(1) I1=n1119(11) I2=n1119(12) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1140(5) I3=n1119(8) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1140(2) I3=n1119(11) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 I2=n1140(6) I3=n1119(8) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1119(9) I1=n1140(6) I2=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I3=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1140(5) I3=n1119(9) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1140(2) I2=n1119(11) I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1140(1) I1=n1119(12) I2=n1119(13) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1140(1) I1=n1119(12) I2=n1119(13) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1140(2) I3=n1119(12) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1140(5) I3=n1119(10) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(15) I1=n1140(0) I2=n1165_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(2) I3=n1119(13) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1140(2) I2=n1119(12) I3=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1140(1) I1=n1119(13) I2=n1119(14) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1140(1) I1=n1119(13) I2=n1119(14) I3=n1140(0) O=n1165_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_2_I1 I1=n1165_ff_CQZ_D_LUT4_O_2_I3 I2=n1165_ff_CQZ_D_LUT4_O_2_I2 I3=n1165_ff_CQZ_D_LUT4_O_1_I2 O=n1165_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1165_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n1165_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1140(5) I2=n1119(15) I3=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1119(14) I1=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1140(6) O=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1119(14) I1=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1140(6) O=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1140(5) I2=n1119(14) I3=n1165_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(7) I3=n1119(13) O=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(14) I1=n1140(7) I2=n1119(15) I3=n1140(6) O=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(14) I1=n1140(6) I2=n1140(7) I3=n1119(15) O=n1165_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt ff CQZ=n1171(7) D=n1171_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4749.1-4754.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1171(6) D=n1171_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4749.1-4754.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1171(5) D=n1171_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4749.1-4754.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1171(4) D=n1171_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4749.1-4754.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1171(3) D=n1171_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4749.1-4754.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1171(2) D=n1171_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4749.1-4754.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1171(1) D=n1171_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4749.1-4754.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1171(0) D=n1171_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4749.1-4754.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n1171_ff_CQZ_D_LUT4_O_I3 O=n1171_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_1_I1 I2=n1171_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n1171_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_2_I2 I2=n1171_ff_CQZ_D_LUT4_O_2_I3 I3=n1171_ff_CQZ_D_LUT4_O_2_I1 O=n1171_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1171_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n1171_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1171_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1171_ff_CQZ_D_LUT4_O_2_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I3 O=n1171_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1119(4) I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1119(4) I1=n1119(5) I2=n1140(12) I3=n1140(13) O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(15) I3=n1119(3) O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1119(6) I1=n1140(13) I2=n1119(7) I3=n1140(12) O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(5) I1=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2 I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1119(7) I3=n1140(11) O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1119(4) I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1119(7) I2=n1140(11) I3=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(10) I3=n1119(6) O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(5) I1=n1140(13) I2=n1119(6) I3=n1140(12) O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1119(5) I1=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2 I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1119(5) I1=n1119(6) I2=n1140(12) I3=n1140(13) O=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(15) I3=n1119(4) O=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1140(13) I3=n1119(7) O=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1171_ff_CQZ_D_LUT4_O_3_I3 O=n1171_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1171_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1171_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1119(3) I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1171_ff_CQZ_D_LUT4_O_4_I3 O=n1171_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_5_I1 I1=n1171_ff_CQZ_D_LUT4_O_5_I3 I2=n1171_ff_CQZ_D_LUT4_O_5_I2 I3=n1171_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1171_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1171_ff_CQZ_D_LUT4_O_5_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I3 O=n1171_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_5_I1 I1=n1171_ff_CQZ_D_LUT4_O_5_I3 I2=n1171_ff_CQZ_D_LUT4_O_5_I2 I3=n1171_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n1171_ff_CQZ_D_LUT4_O_7_I2 I2=n1171_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I3=n1171_ff_CQZ_D_LUT4_O_7_I1 O=n1171_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 I2=n1119(1) I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1119(6) I3=n1140(8) O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(12) I3=n1119(2) O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(13) I3=n1119(1) O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(15) I3=n1119(0) O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1119(2) I1=n1140(14) I2=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1119(3) I1=n1140(13) I2=n1119(4) I3=n1140(12) O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(7) I1=n1140(9) I2=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(11) I3=n1119(5) O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1140(9) I2=n1119(6) I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1140(10) I2=n1119(4) I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1119(2) I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1140(13) I2=n1119(2) I3=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(3) I1=n1140(12) I2=n1119(7) I3=n1140(8) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(3) I1=n1119(7) I2=n1140(8) I3=n1140(12) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(15) I3=n1119(1) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1119(3) I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1119(3) I1=n1119(4) I2=n1140(12) I3=n1140(13) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(15) I3=n1119(2) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1119(4) I1=n1140(13) I2=n1119(5) I3=n1140(12) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(6) I1=n1140(11) I2=n1119(7) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n1171_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=n1119(7) I3=n1140(9) O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1171_ff_CQZ_D_LUT4_O_6_I3 O=n1171_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I2 I1=n1171_ff_CQZ_D_LUT4_O_7_I1 I2=n1171_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I2 I3=n2062 O=n1171_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1119(0) I1=n1119(4) I2=n1140(8) I3=n1140(12) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1119(0) I1=n1140(12) I2=n1119(4) I3=n1140(8) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1140(9) I2=n1119(2) I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(0) I1=n1140(11) I2=n1119(1) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(0) I1=n1119(1) I2=n1140(11) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=n1140(9) I3=n1119(3) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n1140(9) I2=n1119(3) I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(1) I1=n1140(11) I2=n1119(2) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(1) I1=n1119(2) I2=n1140(11) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1140(13) I3=n1119(0) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1140(9) I3=n1119(4) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(2) I1=n1140(11) I2=n1119(3) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 I2=n1140(14) I3=n1119(0) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1140(9) I3=n1119(5) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(3) I1=n1140(11) I2=n1119(4) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=n1140(9) I2=n1119(4) I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(2) I1=n1119(3) I2=n1140(11) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1119(6) I1=n1140(8) I2=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n1140(8) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=n1019 I1=n1119(3) I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1119(2) I2=n1140(10) I3=n1119(0) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n1119(0) I1=n1140(10) I2=n1119(1) I3=n1140(9) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1119(3) I3=n1140(8) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001000100
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1140(9) I3=n1119(2) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(0) I1=n1119(1) I2=n1140(10) I3=n1140(9) O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1140(14) I2=n1119(0) I3=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1140(13) I2=n1119(0) I3=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(1) I1=n1140(12) I2=n1119(5) I3=n1140(8) O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(1) I1=n1119(5) I2=n1140(8) I3=n1140(12) O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1119(1) I1=n1140(14) I2=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0 I3=n1171_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1140(13) I3=n1119(2) O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1140(9) I3=n1119(6) O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1119(4) I1=n1140(11) I2=n1119(5) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=n1140(9) I2=n1119(5) I3=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1119(3) I1=n1119(4) I2=n1140(11) I3=n1140(10) O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_2_I1 I1=n1171_ff_CQZ_D_LUT4_O_2_I3 I2=n1171_ff_CQZ_D_LUT4_O_2_I2 I3=n1171_ff_CQZ_D_LUT4_O_1_I2 O=n1171_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1171_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n1171_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1140(13) I2=n1119(7) I3=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1119(6) I1=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1119(6) I1=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1119(6) I1=n1119(7) I2=n1140(12) I3=n1140(13) O=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1140(15) I3=n1119(5) O=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1119(6) I1=n1140(15) I2=n1119(7) I3=n1140(14) O=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1119(6) I1=n1140(14) I2=n1119(7) I3=n1140(15) O=n1171_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt ff CQZ=n1176(7) D=n1176_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4755.1-4760.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1176(6) D=n1176_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4755.1-4760.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1176(5) D=n1176_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4755.1-4760.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1176(4) D=n1176_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4755.1-4760.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1176(3) D=n1176_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4755.1-4760.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1176(2) D=n1176_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4755.1-4760.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1176(1) D=n1176_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4755.1-4760.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1176(0) D=n1176_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4755.1-4760.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1176_ff_CQZ_D_LUT4_O_I1 I2=n1171(7) I3=n1165(7) O=n1176_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1176_ff_CQZ_D_LUT4_O_1_I1 I2=n1171(6) I3=n1165(6) O=n1176_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1165(5) I2=n1171(5) I3=n1176_ff_CQZ_D_LUT4_O_2_I1 O=n1176_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1176_ff_CQZ_D_LUT4_O_2_I1 I2=n1171(5) I3=n1165(5) O=n1176_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1165(4) I2=n1171(4) I3=n1176_ff_CQZ_D_LUT4_O_3_I1 O=n1176_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1176_ff_CQZ_D_LUT4_O_3_I1 I2=n1171(4) I3=n1165(4) O=n1176_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1165(3) I2=n1171(3) I3=n1176_ff_CQZ_D_LUT4_O_4_I1 O=n1176_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1176_ff_CQZ_D_LUT4_O_4_I1 I2=n1171(3) I3=n1165(3) O=n1176_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1165(2) I2=n1171(2) I3=n1176_ff_CQZ_D_LUT4_O_5_I1 O=n1176_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1176_ff_CQZ_D_LUT4_O_5_I1 I2=n1171(2) I3=n1165(2) O=n1176_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1171(1) I1=n1165(1) I2=n1171(0) I3=n1165(0) O=n1176_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1176_ff_CQZ_D_LUT4_O_6_I3 O=n1176_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1171(0) I1=n1165(0) I2=n1171(1) I3=n1165(1) O=n1176_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1165(0) I2=n1171(0) I3=n2062 O=n1176_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1165(6) I2=n1171(6) I3=n1176_ff_CQZ_D_LUT4_O_1_I1 O=n1176_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n1183(15) D=n1183_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(14) D=n1183_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(5) D=n1183_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(4) D=n1183_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(3) D=n1183_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(2) D=n1183_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(1) D=n1183_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(0) D=n1183_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(13) D=n1183_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(12) D=n1183_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(11) D=n1183_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(10) D=n1183_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(9) D=n1183_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(8) D=n1183_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(7) D=n1183_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1183(6) D=n1183_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4761.1-4766.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_I1 I2=n1159(7) I3=n1129(7) O=n1183_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_1_I1 I2=n1159(6) I3=n1129(6) O=n1183_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_10_I1 I2=n1176(4) I3=n1137(4) O=n1183_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1137(3) I2=n1176(3) I3=n1183_ff_CQZ_D_LUT4_O_11_I1 O=n1183_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_11_I1 I2=n1176(3) I3=n1137(3) O=n1183_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1137(2) I2=n1176(2) I3=n1183_ff_CQZ_D_LUT4_O_12_I1 O=n1183_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_12_I1 I2=n1176(2) I3=n1137(2) O=n1183_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1176(1) I1=n1137(1) I2=n1137(0) I3=n1176(0) O=n1183_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1183_ff_CQZ_D_LUT4_O_13_I3 O=n1183_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1176(0) I1=n1137(0) I2=n1176(1) I3=n1137(1) O=n1183_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1129(0) I2=n1159(0) I3=n2062 O=n1183_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1137(0) I2=n1176(0) I3=n2062 O=n1183_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1129(5) I2=n1159(5) I3=n1183_ff_CQZ_D_LUT4_O_2_I1 O=n1183_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_2_I1 I2=n1159(5) I3=n1129(5) O=n1183_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1129(4) I2=n1159(4) I3=n1183_ff_CQZ_D_LUT4_O_3_I1 O=n1183_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_3_I1 I2=n1159(4) I3=n1129(4) O=n1183_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1129(3) I2=n1159(3) I3=n1183_ff_CQZ_D_LUT4_O_4_I1 O=n1183_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_4_I1 I2=n1159(3) I3=n1129(3) O=n1183_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1129(2) I2=n1159(2) I3=n1183_ff_CQZ_D_LUT4_O_5_I1 O=n1183_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_5_I1 I2=n1159(2) I3=n1129(2) O=n1183_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1159(1) I1=n1129(1) I2=n1129(0) I3=n1159(0) O=n1183_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1183_ff_CQZ_D_LUT4_O_6_I3 O=n1183_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1159(0) I1=n1129(0) I2=n1159(1) I3=n1129(1) O=n1183_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_7_I1 I2=n1176(7) I3=n1137(7) O=n1183_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1137(6) I2=n1176(6) I3=n1183_ff_CQZ_D_LUT4_O_8_I1 O=n1183_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_8_I1 I2=n1176(6) I3=n1137(6) O=n1183_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1137(5) I2=n1176(5) I3=n1183_ff_CQZ_D_LUT4_O_9_I1 O=n1183_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1183_ff_CQZ_D_LUT4_O_9_I1 I2=n1176(5) I3=n1137(5) O=n1183_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1137(4) I2=n1176(4) I3=n1183_ff_CQZ_D_LUT4_O_10_I1 O=n1183_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n1129(6) I2=n1159(6) I3=n1183_ff_CQZ_D_LUT4_O_1_I1 O=n1183_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n113(0) D=n118_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3565.1-3570.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n51_LUT4_I3_O I3=n118_ff_CQZ_D_LUT4_O_I3 O=n118_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n39(1) I1=n39(0) I2=n118_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n113(0) O=n118_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n39(2) I1=n39(3) I2=n39(4) I3=n39(5) O=n118_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=n1190(15) D=n1190_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(14) D=n1190_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(5) D=n1190_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(4) D=n1190_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(3) D=n1190_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(2) D=n1190_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(1) D=n1190_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(0) D=n1183_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(13) D=n1190_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(12) D=n1190_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(11) D=n1190_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(10) D=n1190_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(9) D=n1190_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(8) D=n1183_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(7) D=n1190_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1190(6) D=n1190_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4767.1-4772.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_I1 I2=n1159(7) I3=n1129(7) O=n1190_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_1_I1 I2=n1159(6) I3=n1129(6) O=n1190_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_10_I1 I2=n1176(4) I3=n1137(4) O=n1190_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1137(3) I2=n1176(3) I3=n1190_ff_CQZ_D_LUT4_O_11_I1 O=n1190_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_11_I1 I2=n1176(3) I3=n1137(3) O=n1190_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1137(2) I2=n1176(2) I3=n1190_ff_CQZ_D_LUT4_O_12_I1 O=n1190_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_12_I1 I2=n1176(2) I3=n1137(2) O=n1190_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1176(1) I1=n1137(1) I2=n1137(0) I3=n1176(0) O=n1190_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1190_ff_CQZ_D_LUT4_O_13_I3 O=n1190_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1137(0) I1=n1176(0) I2=n1176(1) I3=n1137(1) O=n1190_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n1129(5) I2=n1159(5) I3=n1190_ff_CQZ_D_LUT4_O_2_I1 O=n1190_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_2_I1 I2=n1159(5) I3=n1129(5) O=n1190_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1129(4) I2=n1159(4) I3=n1190_ff_CQZ_D_LUT4_O_3_I1 O=n1190_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_3_I1 I2=n1159(4) I3=n1129(4) O=n1190_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1129(3) I2=n1159(3) I3=n1190_ff_CQZ_D_LUT4_O_4_I1 O=n1190_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_4_I1 I2=n1159(3) I3=n1129(3) O=n1190_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1129(2) I2=n1159(2) I3=n1190_ff_CQZ_D_LUT4_O_5_I1 O=n1190_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_5_I1 I2=n1159(2) I3=n1129(2) O=n1190_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1159(1) I1=n1129(1) I2=n1129(0) I3=n1159(0) O=n1190_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1190_ff_CQZ_D_LUT4_O_6_I3 O=n1190_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1129(0) I1=n1159(0) I2=n1159(1) I3=n1129(1) O=n1190_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_7_I1 I2=n1176(7) I3=n1137(7) O=n1190_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1137(6) I2=n1176(6) I3=n1190_ff_CQZ_D_LUT4_O_8_I1 O=n1190_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_8_I1 I2=n1176(6) I3=n1137(6) O=n1190_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1137(5) I2=n1176(5) I3=n1190_ff_CQZ_D_LUT4_O_9_I1 O=n1190_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1190_ff_CQZ_D_LUT4_O_9_I1 I2=n1176(5) I3=n1137(5) O=n1190_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1137(4) I2=n1176(4) I3=n1190_ff_CQZ_D_LUT4_O_10_I1 O=n1190_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1129(6) I2=n1159(6) I3=n1190_ff_CQZ_D_LUT4_O_1_I1 O=n1190_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1195 I3=n2062 O=n1199_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1195 D=n1195_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4773.1-4778.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1199 I3=n2062 O=n1203_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1199 D=n1199_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4779.1-4784.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n11(5) D=sync_i_LUT4_I3_O_LUT4_I1_O(5) QCK=$iopadmap$clock_c QEN=n2115 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3465.1-3470.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n11(4) D=sync_i_LUT4_I3_O_LUT4_I1_O(4) QCK=$iopadmap$clock_c QEN=n2115 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3465.1-3470.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n11(3) D=sync_i_LUT4_I3_O_LUT4_I1_O(3) QCK=$iopadmap$clock_c QEN=n2115 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3465.1-3470.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n11(2) D=sync_i_LUT4_I3_O_LUT4_I1_O(2) QCK=$iopadmap$clock_c QEN=n2115 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3465.1-3470.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n11(1) D=sync_i_LUT4_I3_O_LUT4_I1_O(1) QCK=$iopadmap$clock_c QEN=n2115 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3465.1-3470.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n11(0) D=sync_i_LUT4_I3_O_LUT4_I1_O(0) QCK=$iopadmap$clock_c QEN=n2115 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3465.1-3470.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1203 I3=n2062 O=n1207_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1203 D=n1203_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4785.1-4790.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1207 O=n1207_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1207_LUT4_I3_O I2=n1247(4) I3=n1207_LUT4_I3_O_LUT4_I1_I3 O=n1207_LUT4_I3_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1207_LUT4_I3_O I2=n1247(1) I3=n1247(0) O=n1207_LUT4_I3_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1247(0) I1=n1247(1) I2=n1247(2) I3=n1247(3) O=n1207_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1207_LUT4_I3_O I3=n1207_LUT4_I3_O_LUT4_I2_I3 O=n1207_LUT4_I3_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1207_LUT4_I3_O I3=n1247(0) O=n1207_LUT4_I3_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1247(0) I1=n1247(1) I2=n1247(2) I3=n1247(3) O=n1207_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n1207_LUT4_I3_O_LUT4_I1_I3 I1=n1247(4) I2=n1247(5) I3=n1207_LUT4_I3_O O=n1207_LUT4_I3_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1247(0) I1=n1247(1) I2=n1247(2) I3=n1207_LUT4_I3_O O=n1207_LUT4_I3_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n1207 D=n1207_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4791.1-4796.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1094(0) I1=n1094(1) I2=n1094(2) I3=n1094(3) O=n1225_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n1094(0) I1=n1094(1) I2=n1094(2) I3=n1018_LUT4_I3_O O=n1225_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1094(0) I1=n1094(3) I2=n1094(1) I3=n1094(2) O=n2085_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1018_LUT4_I3_O I2=n1094(1) I3=n1094(0) O=n1225_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1018_LUT4_I3_O I3=n1094(0) O=n1225_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1094(0) D=n1225_LUT4_I3_O(0) QCK=$iopadmap$clock_c QEN=n2085 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4651.1-4656.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1229 I3=n2062 O=n1233_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1229 D=n1229_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4821.1-4826.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1094(0) I3=n2062 O=n1229_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1233 I3=n2062 O=n1237_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1233 D=n1233_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4827.1-4832.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1237 I3=n2062 O=n1241_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1237 D=n1237_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4833.1-4838.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1241 I2=n2059 I3=n1286(0) O=n1241_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1241 I2=n2059 I3=n1286(0) O=n1241_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n1241 I3=n1249(0) O=n1241_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=n1241 D=n1241_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4839.1-4844.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1247(5) D=n1207_LUT4_I3_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4845.1-4850.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1247(4) D=n1207_LUT4_I3_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4845.1-4850.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1247(3) D=n1207_LUT4_I3_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4845.1-4850.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1247(2) D=n1207_LUT4_I3_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4845.1-4850.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1247(1) D=n1207_LUT4_I3_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4845.1-4850.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1247(0) D=n1207_LUT4_I3_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4845.1-4850.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1249(0) I2=n2059 I3=n1241 O=n1254_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n1249(0) D=n1254_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4851.1-4856.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1207 I2=n1249(0) I3=n2062 O=n1254_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1259 I3=n2079_LUT4_O_I3 O=n1348_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1259 O=n1259_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1259_LUT4_I3_O I2=n1335(4) I3=n1348_LUT4_I3_I1 O=n1466_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1259_LUT4_I3_O I3=n1466_LUT4_I1_O O=n1466_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1348_LUT4_I3_I1 I1=n1348_LUT4_I3_I2_LUT4_O_I3 I2=n1335(6) I3=n1259_LUT4_I3_O O=n1466_LUT4_I3_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1348_LUT4_I3_I1 I1=n1335(4) I2=n1335(5) I3=n1259_LUT4_I3_O O=n1466_LUT4_I3_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n1259 D=n1259_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4857.1-4862.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1207 I3=n2062 O=n1259_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1270(31) D=n1183(15) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(30) D=n1183(14) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(21) D=n1183(5) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(20) D=n1183(4) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(19) D=n1183(3) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(18) D=n1183(2) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(17) D=n1183(1) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(16) D=n1183(0) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(15) D=n1190(15) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(14) D=n1190(14) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(13) D=n1190(13) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(12) D=n1190(12) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(29) D=n1183(13) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(11) D=n1190(11) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(10) D=n1190(10) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(9) D=n1190(9) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(8) D=n1190(8) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(7) D=n1190(7) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(6) D=n1190(6) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(5) D=n1190(5) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(4) D=n1190(4) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(3) D=n1190(3) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(2) D=n1190(2) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(28) D=n1183(12) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(1) D=n1190(1) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(0) D=n1190(0) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(27) D=n1183(11) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(26) D=n1183(10) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(25) D=n1183(9) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(24) D=n1183(8) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(23) D=n1183(7) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1270(22) D=n1183(6) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4863.1-4867.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(31) D=n1183(15) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(30) D=n1183(14) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(21) D=n1183(5) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(20) D=n1183(4) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(19) D=n1183(3) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(18) D=n1183(2) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(17) D=n1183(1) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(16) D=n1183(0) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(15) D=n1190(15) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(14) D=n1190(14) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(13) D=n1190(13) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(12) D=n1190(12) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(29) D=n1183(13) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(11) D=n1190(11) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(10) D=n1190(10) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(9) D=n1190(9) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(8) D=n1190(8) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(7) D=n1190(7) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(6) D=n1190(6) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(5) D=n1190(5) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(4) D=n1190(4) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(3) D=n1190(3) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(2) D=n1190(2) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(28) D=n1183(12) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(1) D=n1190(1) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(0) D=n1190(0) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(27) D=n1183(11) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(26) D=n1183(10) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(25) D=n1183(9) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(24) D=n1183(8) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(23) D=n1183(7) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1274(22) D=n1183(6) QCK=$iopadmap$clock_c QEN=n1254_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4873.1-4877.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1274(15) I1=n1270(15) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(14) I1=n1270(14) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(5) I1=n1270(5) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(4) I1=n1270(4) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(3) I1=n1270(3) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(2) I1=n1270(2) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(1) I1=n1270(1) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1270(0) I1=n1274(0) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1274(13) I1=n1270(13) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(12) I1=n1270(12) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(11) I1=n1270(11) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(10) I1=n1270(10) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(9) I1=n1270(9) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(8) I1=n1270(8) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(7) I1=n1270(7) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(6) I1=n1270(6) I2=n1278 I3=n1319(0) O=n1278_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1274(31) I1=n1270(31) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(30) I1=n1270(30) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(21) I1=n1270(21) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(20) I1=n1270(20) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(19) I1=n1270(19) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(18) I1=n1270(18) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(17) I1=n1270(17) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(16) I1=n1270(16) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(29) I1=n1270(29) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(28) I1=n1270(28) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(27) I1=n1270(27) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(26) I1=n1270(26) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(25) I1=n1270(25) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(24) I1=n1270(24) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(23) I1=n1270(23) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1274(22) I1=n1270(22) I2=n1319(0) I3=n1278 O=n1278_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n1278 D=n1278_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4883.1-4888.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1249(0) O=n1278_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n1286(0) D=n1291_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4895.1-4900.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1286(0) I2=n1207 I3=n2062 O=n1291_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=n129(6) D=n142_LUT4_I3_I2_LUT4_I3_O(6) QCK=$iopadmap$clock_c QEN=n2109 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3571.1-3576.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n129(5) D=n142_LUT4_I3_I2_LUT4_I3_O(5) QCK=$iopadmap$clock_c QEN=n2109 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3571.1-3576.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n129(4) D=n142_LUT4_I3_I2_LUT4_I3_O(4) QCK=$iopadmap$clock_c QEN=n2109 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3571.1-3576.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n129(3) D=n142_LUT4_I3_I2_LUT4_I3_O(3) QCK=$iopadmap$clock_c QEN=n2109 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3571.1-3576.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n129(2) D=n142_LUT4_I3_I2_LUT4_I3_O(2) QCK=$iopadmap$clock_c QEN=n2109 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3571.1-3576.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n129(1) D=n142_LUT4_I3_I2_LUT4_I3_O(1) QCK=$iopadmap$clock_c QEN=n2109 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3571.1-3576.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(31) D=n1183(15) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(30) D=n1183(14) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(21) D=n1183(5) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(20) D=n1183(4) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(19) D=n1183(3) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(18) D=n1183(2) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(17) D=n1183(1) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(16) D=n1183(0) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(15) D=n1190(15) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(14) D=n1190(14) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4901.1-4905.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1307(13) D=n1190(13) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1307(26) D=n1183(10) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1307(25) D=n1183(9) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1307(24) D=n1183(8) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1307(22) D=n1183(6) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1311(16) D=n1183(0) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.attr module_not_derived 00000000000000000000000000000001
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+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1311(11) D=n1190(11) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1311(10) D=n1190(10) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(9) D=n1190(9) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(8) D=n1190(8) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(7) D=n1190(7) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(6) D=n1190(6) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(5) D=n1190(5) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(4) D=n1190(4) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(3) D=n1190(3) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(2) D=n1190(2) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(28) D=n1183(12) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(1) D=n1190(1) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(0) D=n1190(0) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(27) D=n1183(11) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(26) D=n1183(10) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(25) D=n1183(9) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(24) D=n1183(8) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(23) D=n1183(7) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1311(22) D=n1183(6) QCK=$iopadmap$clock_c QEN=n1241_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4911.1-4915.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1311(15) I1=n1307(15) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(14) I1=n1307(14) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(5) I1=n1307(5) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(4) I1=n1307(4) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(3) I1=n1307(3) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(2) I1=n1307(2) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(1) I1=n1307(1) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1307(0) I1=n1311(0) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1311(13) I1=n1307(13) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(12) I1=n1307(12) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(11) I1=n1307(11) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(10) I1=n1307(10) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(9) I1=n1307(9) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(8) I1=n1307(8) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(7) I1=n1307(7) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(6) I1=n1307(6) I2=n1315 I3=n1319(0) O=n1315_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1311(31) I1=n1307(31) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(30) I1=n1307(30) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(21) I1=n1307(21) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(20) I1=n1307(20) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(19) I1=n1307(19) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(18) I1=n1307(18) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(17) I1=n1307(17) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(16) I1=n1307(16) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(29) I1=n1307(29) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(28) I1=n1307(28) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(27) I1=n1307(27) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(26) I1=n1307(26) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(25) I1=n1307(25) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(24) I1=n1307(24) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(23) I1=n1307(23) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1311(22) I1=n1307(22) I2=n1319(0) I3=n1315 O=n1315_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n1315 D=n1315_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4921.1-4926.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1286(0) O=n1315_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n1319(0) D=n1324_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4927.1-4932.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1259_LUT4_I3_O I3=n1324_ff_CQZ_D_LUT4_O_I3 O=n1324_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1247(1) I1=n1247(0) I2=n1324_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1319(0) O=n1324_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n1247(2) I1=n1247(3) I2=n1247(4) I3=n1247(5) O=n1324_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=n1335(6) D=n1466_LUT4_I3_O(6) QCK=$iopadmap$clock_c QEN=n2079 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4933.1-4938.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1335(5) D=n1466_LUT4_I3_O(5) QCK=$iopadmap$clock_c QEN=n2079 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4933.1-4938.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1335(4) D=n1466_LUT4_I3_O(4) QCK=$iopadmap$clock_c QEN=n2079 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4933.1-4938.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1335(3) D=n1466_LUT4_I3_O(3) QCK=$iopadmap$clock_c QEN=n2079 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4933.1-4938.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1335(2) D=n1466_LUT4_I3_O(2) QCK=$iopadmap$clock_c QEN=n2079 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4933.1-4938.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1335(1) D=n1466_LUT4_I3_O(1) QCK=$iopadmap$clock_c QEN=n2079 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4933.1-4938.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1339(0) I2=n1348_LUT4_I3_I1 I3=n1348_LUT4_I3_I2 O=n2079_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt ff CQZ=n1339(0) D=n1348_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4939.1-4944.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1348_LUT4_I3_I1 I2=n1348_LUT4_I3_I2 I3=n1348 O=n1436_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(6) I3=n1348_LUT4_I3_I2_LUT4_O_I3 O=n1348_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1335(6) I2=n1348_LUT4_I3_I2_LUT4_O_I3 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3 I3=n1466_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(3) I3=n1335(2) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I3 I3=n1335(4) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I1_I2 I3=n1335(3) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(4) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_I3 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=n1019 I1=n1335(6) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I0 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1019 I1=n1335(6) I2=n1335(4) I3=n1335(5) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1335(6) I1=n1335(4) I2=n1335(5) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110111111111
+.subckt LUT4 I0=n1019 I1=n1335(6) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_1_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_1_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_10_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_10_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_I3 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_10_I1 I2=n1335(4) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3 I3=n1335(6) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1335(6) I1=n1466_LUT4_I2_I3 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I2 I3=n1335(4) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 I1=n1335(6) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2 I3=n1335(5) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111111
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001011111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I1_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I2_LUT4_O_I1 I2=n1335(2) I3=n1348_LUT4_I3_I2 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I3 I2=n1335(3) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I3 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I1 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I3_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_12_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I2 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_12_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_12_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I3 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1335(3) I1=n1335(6) I2=n1335(4) I3=n1335(5) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001111010000
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I3 I1=n1335(2) I2=n1335(3) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=n1335(5) I1=n1335(6) I2=n1335(4) I3=n1466_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101011101100
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2 I2=n1335(3) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_2_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101111
+.subckt LUT4 I0=n1335(6) I1=n1335(3) I2=n1335(5) I3=n1335(4) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001100000000000
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I0 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_7_I0 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I0_LUT4_O_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1019 I1=n1335(2) I2=n1335(4) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(5) I3=n1335(6) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1335(2) I1=n1335(3) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3 I3=n1335(6) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001111111111111
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1335(3) I1=n1335(4) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I3 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_4_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_4_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_4_I1_LUT4_O_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I0 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I1 I2=n1335(3) I3=n1348_LUT4_I3_I2 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n1335(4) I1=n1335(3) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I0 I3=n1335(6) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_5_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I3 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_5_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_5_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010011111111
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_5_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_11_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(4) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I1_I2 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I2 I3=n1335(6) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I1 I2=n1335(2) I3=n1335(3) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I1_I2 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I1 I2=n1335(3) I3=n1335(2) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110110010101110
+.subckt LUT4 I0=n1348_LUT4_I3_I2 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I3 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I1_LUT4_O_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1019 I1=n1335(6) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_I3 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(6) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I1 I2=n1335(6) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1019 I1=n1335(6) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_I3 I3=n1466_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_7_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I1 I2=n1335(6) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_7_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_I3 I3=n1466_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1335(3) I1=n1335(4) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_1_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I3 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_3_I0_LUT4_O_I1 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=n1019 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_10_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1348_LUT4_I3_I2 I1=n1335(2) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_I3_LUT4_O_I1 I3=n1335(3) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1335(3) I1=n1335(2) I2=n1335(4) I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(5) I3=n1335(6) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(5) I3=n1335(4) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111101110
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_I3 I1=n1335(5) I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0 I3=n1335(6) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(5) I3=n1335(4) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(2) I3=n1335(3) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(5) I3=n1335(6) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I3 I1=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1 I2=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O I3=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3 O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(3) I3=n1335(2) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1335(6) I1=n1335(5) I2=n1335(3) I3=n1335(4) O=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(5) I3=n1335(4) O=n1348_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=n1348 D=n1348_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4945.1-4950.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(15) D=n1354_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(14) D=n1354_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(5) D=n1354_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(4) D=n1354_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(3) D=n1354_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(2) D=n1354_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(1) D=n1354_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(0) D=n1354_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(13) D=n1354_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(12) D=n1354_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(11) D=n1354_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(10) D=n1354_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(9) D=n1354_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(8) D=n1354_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(7) D=n1354_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1354(6) D=n1354_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4951.1-4956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_O I3=n1278_LUT4_I2_O O=n1354_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_1_O I3=n1278_LUT4_I2_1_O O=n1354_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_10_O I3=n1278_LUT4_I2_10_O O=n1354_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_11_O I3=n1278_LUT4_I2_11_O O=n1354_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_12_O I3=n1278_LUT4_I2_12_O O=n1354_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_13_O I3=n1278_LUT4_I2_13_O O=n1354_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_14_O I3=n1278_LUT4_I2_14_O O=n1354_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_15_O I3=n1278_LUT4_I2_15_O O=n1354_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_2_O I3=n1278_LUT4_I2_2_O O=n1354_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_3_O I3=n1278_LUT4_I2_3_O O=n1354_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_4_O I3=n1278_LUT4_I2_4_O O=n1354_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_5_O I3=n1278_LUT4_I2_5_O O=n1354_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_6_O I3=n1278_LUT4_I2_6_O O=n1354_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_7_O I3=n1278_LUT4_I2_7_O O=n1354_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_8_O I3=n1278_LUT4_I2_8_O O=n1354_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1278_LUT4_I3_9_O I3=n1278_LUT4_I2_9_O O=n1354_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=n1360(15) D=n1360_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(14) D=n1360_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(5) D=n1360_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(4) D=n1360_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(3) D=n1360_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(2) D=n1360_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(1) D=n1360_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(0) D=n1360_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(13) D=n1360_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(12) D=n1360_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(11) D=n1360_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(10) D=n1360_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(9) D=n1360_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(8) D=n1360_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(7) D=n1360_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1360(6) D=n1360_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4957.1-4962.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_O I3=n1315_LUT4_I2_O O=n1360_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_1_O I3=n1315_LUT4_I2_1_O O=n1360_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_10_O I3=n1315_LUT4_I2_10_O O=n1360_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_11_O I3=n1315_LUT4_I2_11_O O=n1360_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_12_O I3=n1315_LUT4_I2_12_O O=n1360_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_13_O I3=n1315_LUT4_I2_13_O O=n1360_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_14_O I3=n1315_LUT4_I2_14_O O=n1360_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_15_O I3=n1315_LUT4_I2_15_O O=n1360_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_2_O I3=n1315_LUT4_I2_2_O O=n1360_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_3_O I3=n1315_LUT4_I2_3_O O=n1360_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_4_O I3=n1315_LUT4_I2_4_O O=n1360_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_5_O I3=n1315_LUT4_I2_5_O O=n1360_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_6_O I3=n1315_LUT4_I2_6_O O=n1360_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_7_O I3=n1315_LUT4_I2_7_O O=n1360_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_8_O I3=n1315_LUT4_I2_8_O O=n1360_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1315_LUT4_I3_9_O I3=n1315_LUT4_I2_9_O O=n1360_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1366(7) I3=n2062 O=n1370_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1366(6) I3=n2062 O=n1370_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1366(5) I3=n2062 O=n1370_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1366(4) I3=n2062 O=n1370_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1366(3) I3=n2062 O=n1370_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1366(2) I3=n2062 O=n1370_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1366(1) I3=n2062 O=n1370_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1366(0) I3=n2062 O=n1370_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1366(7) D=n1366_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4963.1-4968.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1366(6) D=n1366_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4963.1-4968.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1366(5) D=n1366_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4963.1-4968.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1366(4) D=n1366_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4963.1-4968.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1366(3) D=n1366_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4963.1-4968.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1366(2) D=n1366_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4963.1-4968.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1366(1) D=n1366_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4963.1-4968.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1366(0) D=n1366_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4963.1-4968.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(15) I3=n2062 O=n1366_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(14) I3=n2062 O=n1366_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(13) I3=n2062 O=n1366_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(12) I3=n2062 O=n1366_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(11) I3=n2062 O=n1366_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(10) I3=n2062 O=n1366_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(9) I3=n2062 O=n1366_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(8) I3=n2062 O=n1366_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1370(7) D=n1370_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4969.1-4974.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1370(6) D=n1370_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4969.1-4974.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1370(5) D=n1370_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4969.1-4974.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1370(4) D=n1370_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4969.1-4974.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1370(3) D=n1370_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4969.1-4974.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1370(2) D=n1370_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4969.1-4974.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1370(1) D=n1370_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4969.1-4974.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1370(0) D=n1370_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4969.1-4974.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1374(7) I3=n2062 O=n1378_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1374(6) I3=n2062 O=n1378_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1374(5) I3=n2062 O=n1378_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1374(4) I3=n2062 O=n1378_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1374(3) I3=n2062 O=n1378_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1374(2) I3=n2062 O=n1378_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1374(1) I3=n2062 O=n1378_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1374(0) I3=n2062 O=n1378_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1374(7) D=n1374_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4975.1-4980.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1374(6) D=n1374_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4975.1-4980.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1374(5) D=n1374_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4975.1-4980.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1374(4) D=n1374_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4975.1-4980.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1374(3) D=n1374_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4975.1-4980.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1374(2) D=n1374_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4975.1-4980.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1374(1) D=n1374_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4975.1-4980.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1374(0) D=n1374_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4975.1-4980.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(7) I3=n2062 O=n1374_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(6) I3=n2062 O=n1374_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(5) I3=n2062 O=n1374_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(4) I3=n2062 O=n1374_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(3) I3=n2062 O=n1374_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(2) I3=n2062 O=n1374_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(1) I3=n2062 O=n1374_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1354(0) I3=n2062 O=n1374_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1378(7) D=n1378_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4981.1-4986.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1378(6) D=n1378_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4981.1-4986.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1378(5) D=n1378_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4981.1-4986.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1378(4) D=n1378_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4981.1-4986.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1378(3) D=n1378_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4981.1-4986.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1378(2) D=n1378_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4981.1-4986.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1378(1) D=n1378_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4981.1-4986.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1378(0) D=n1378_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4981.1-4986.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(15) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(14) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(5) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(4) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(3) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(2) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(1) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(0) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(13) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(12) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(11) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(10) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(9) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(8) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(7) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1381(6) D=n1348_LUT4_I3_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4987.1-5022.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1389(7) D=n1389_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5023.1-5028.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1389(6) D=n1389_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5023.1-5028.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1389(5) D=n1389_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5023.1-5028.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1389(4) D=n1389_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5023.1-5028.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1389(3) D=n1389_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5023.1-5028.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1389(2) D=n1389_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5023.1-5028.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1389(1) D=n1389_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5023.1-5028.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1389(0) D=n1389_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5023.1-5028.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n1389_ff_CQZ_D_LUT4_O_I3 O=n1389_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_1_I1 I2=n1389_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n1389_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_2_I2 I2=n1389_ff_CQZ_D_LUT4_O_2_I3 I3=n1389_ff_CQZ_D_LUT4_O_2_I1 O=n1389_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1389_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n1389_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1389_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1389_ff_CQZ_D_LUT4_O_2_I1 I2=n1389_ff_CQZ_D_LUT4_O_2_I2 I3=n1389_ff_CQZ_D_LUT4_O_2_I3 O=n1389_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 I2=n1360(12) I3=n1381(14) O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1381(13) I2=n1360(12) I3=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(13) I1=n1381(12) I2=n1360(14) I3=n1381(11) O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(13) I1=n1360(14) I2=n1381(11) I3=n1381(12) O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1360(14) I1=n1381(13) I2=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1360(13) I1=n1381(14) I2=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I3=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(12) I3=n1360(15) O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1360(15) I3=n1381(10) O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1360(15) I1=n1381(11) I2=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(12) I3=n1360(14) O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(13) I3=n1360(13) O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I2=n1381(14) I3=n1360(12) O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(11) O=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1360(13) I3=n1381(14) O=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n1360(15) I3=n1381(11) O=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(12) O=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1381(13) I3=n1360(15) O=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1360(14) I1=n1381(13) I2=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1389_ff_CQZ_D_LUT4_O_3_I3 O=n1389_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1389_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1389_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=n1360(11) I3=n1381(14) O=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I2=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I3=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1389_ff_CQZ_D_LUT4_O_4_I3 O=n1389_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_5_I1 I1=n1389_ff_CQZ_D_LUT4_O_5_I3 I2=n1389_ff_CQZ_D_LUT4_O_5_I2 I3=n1389_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1389_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1389_ff_CQZ_D_LUT4_O_5_I1 I2=n1389_ff_CQZ_D_LUT4_O_5_I2 I3=n1389_ff_CQZ_D_LUT4_O_5_I3 O=n1389_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_5_I1 I1=n1389_ff_CQZ_D_LUT4_O_5_I3 I2=n1389_ff_CQZ_D_LUT4_O_5_I2 I3=n1389_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I3 I2=n1389_ff_CQZ_D_LUT4_O_6_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I1 O=n1389_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1360(10) I3=n1381(14) O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1381(13) I2=n1360(10) I3=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(11) I1=n1381(12) I2=n1360(12) I3=n1381(11) O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(11) I1=n1360(12) I2=n1381(11) I3=n1381(12) O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(9) O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1360(11) I1=n1381(14) I2=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1381(13) I2=n1360(11) I3=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(12) I1=n1360(13) I2=n1381(11) I3=n1381(12) O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(10) O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1360(15) I2=n1381(10) I3=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(9) I3=n1360(14) O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1381(13) I3=n1360(12) O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n2062 I1=n1389_ff_CQZ_D_LUT4_O_6_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I3 O=n1389_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1381(14) I2=n1360(8) I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1381(13) I2=n1360(8) I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(9) I1=n1381(12) I2=n1360(10) I3=n1381(11) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(9) I1=n1360(10) I2=n1381(11) I3=n1381(12) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1381(10) I2=n1360(10) I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1381(8) I1=n1360(12) I2=n1360(11) I3=n1381(9) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1381(8) I1=n1360(11) I2=n1360(12) I3=n1381(9) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1381(13) I3=n1360(8) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1381(10) I3=n1360(11) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=n1381(14) I3=n1360(8) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1360(9) I1=n1381(14) I2=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I3=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1381(13) I3=n1360(9) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1381(10) I2=n1360(11) I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1381(8) I1=n1360(13) I2=n1360(12) I3=n1381(9) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1381(8) I1=n1360(12) I2=n1360(13) I3=n1381(9) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1381(10) I3=n1360(12) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1381(13) I3=n1360(10) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1381(8) I1=n1360(15) I2=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(10) I3=n1360(13) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1381(10) I2=n1360(12) I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1381(8) I1=n1360(14) I2=n1360(13) I3=n1381(9) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1381(8) I1=n1360(13) I2=n1360(14) I3=n1381(9) O=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=n1360(9) I3=n1381(14) O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1381(13) I2=n1360(9) I3=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(10) I1=n1381(12) I2=n1360(11) I3=n1381(11) O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(10) I1=n1360(11) I2=n1381(11) I3=n1381(12) O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(8) O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1360(10) I1=n1381(14) I2=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1360(14) I1=n1381(10) I2=n1360(15) I3=n1381(9) O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1381(13) I3=n1360(11) O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1360(12) I1=n1381(12) I2=n1360(13) I3=n1381(11) O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1381(8) I3=n1360(15) O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1389_ff_CQZ_D_LUT4_O_7_I3 O=n1389_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I0 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1360(8) I3=n1381(8) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(10) I3=n1360(8) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(9) I3=n1360(9) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1360(10) I3=n1381(8) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1360(8) I1=n1381(11) I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1381(10) I3=n1360(10) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1381(8) I1=n1360(10) I2=n1360(11) I3=n1381(9) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(10) I3=n1360(9) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1381(8) I1=n1360(11) I2=n1360(10) I3=n1381(9) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(9) I1=n1381(11) I2=n1360(8) I3=n1381(12) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n1360(8) I3=n1381(11) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1360(9) I1=n1360(8) I2=n1381(11) I3=n1381(12) O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_2_I1 I1=n1389_ff_CQZ_D_LUT4_O_2_I3 I2=n1389_ff_CQZ_D_LUT4_O_2_I2 I3=n1389_ff_CQZ_D_LUT4_O_1_I2 O=n1389_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1389_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n1389_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1381(13) I2=n1360(15) I3=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1360(14) I1=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1360(14) I1=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1381(13) I2=n1360(14) I3=n1389_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(13) O=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(14) I1=n1381(15) I2=n1360(15) I3=n1381(14) O=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(14) I1=n1381(14) I2=n1360(15) I3=n1381(15) O=n1389_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1019 I1=n133(0) I2=n129(6) I3=n142_LUT4_I3_I2 O=n2109_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt ff CQZ=n133(0) D=n142_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3577.1-3582.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1395(7) D=n1395_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5029.1-5034.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1395(6) D=n1395_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5029.1-5034.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1395(5) D=n1395_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5029.1-5034.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1395(4) D=n1395_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5029.1-5034.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1395(3) D=n1395_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5029.1-5034.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1395(2) D=n1395_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5029.1-5034.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1395(1) D=n1395_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5029.1-5034.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1395(0) D=n1395_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5029.1-5034.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n1395_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1395_ff_CQZ_D_LUT4_O_1_I3 O=n1395_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I1=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I3=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1395_ff_CQZ_D_LUT4_O_2_I3 O=n1395_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_3_I1 I1=n1395_ff_CQZ_D_LUT4_O_3_I3 I2=n1395_ff_CQZ_D_LUT4_O_3_I2 I3=n1395_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1395_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1395_ff_CQZ_D_LUT4_O_3_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I3 O=n1395_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_3_I1 I1=n1395_ff_CQZ_D_LUT4_O_3_I3 I2=n1395_ff_CQZ_D_LUT4_O_3_I2 I3=n1395_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I1=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 I2=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I3=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 O=n1395_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=n1360(3) I3=n1381(6) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0 I2=n1381(6) I3=n1360(3) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1381(5) I1=n1360(3) I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(3) I3=n1360(5) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(4) I1=n1381(4) I2=n1360(5) I3=n1381(3) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(2) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1381(5) I3=n1360(5) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1360(6) I1=n1381(4) I2=n1360(7) I3=n1381(3) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1360(7) I3=n1381(2) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(1) I3=n1360(6) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(4) I1=n1381(6) I2=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0 I3=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111010
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n1381(0) I3=n1360(7) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1360(6) I1=n1381(2) I2=n1360(7) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(4) I1=n1381(5) I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1360(6) I1=n1381(1) I2=n1360(7) I3=n1381(2) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1360(5) I1=n1381(4) I2=n1360(6) I3=n1381(3) O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 O=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=n1360(4) I3=n1381(6) O=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=n1381(5) I2=n1360(4) I3=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1381(4) I2=n1360(6) I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(3) O=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(6) I1=n1381(5) I2=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1360(5) I1=n1381(6) I2=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(4) I3=n1360(7) O=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1395_ff_CQZ_D_LUT4_O_4_I3 O=n1395_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1395_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 I3=n1395_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 O=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 I3=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1381(7) I1=n1360(1) I2=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(6) I3=n1360(2) O=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1395_ff_CQZ_D_LUT4_O_5_I3 O=n1395_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_I0_O I1=n1395_ff_CQZ_D_LUT4_O_6_I3 I2=n1395_ff_CQZ_D_LUT4_O_6_I2 I3=n1395_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1395_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 I3=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_I0_O I2=n1395_ff_CQZ_D_LUT4_O_6_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I3 O=n1395_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1381(6) I2=n1360(0) I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1381(5) I2=n1360(0) I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(1) I1=n1381(4) I2=n1360(2) I3=n1381(3) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(1) I1=n1360(2) I2=n1381(3) I3=n1381(4) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 I2=n1381(7) I3=n1360(0) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1360(3) I1=n1381(4) I2=n1360(4) I3=n1381(3) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(5) I3=n1360(2) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1381(0) I1=n1360(7) I2=n1360(6) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(2) I3=n1360(5) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=n1381(2) I2=n1360(4) I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1381(0) I1=n1360(5) I2=n1360(6) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1381(2) I2=n1360(2) I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1381(0) I1=n1360(4) I2=n1360(3) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1381(0) I1=n1360(3) I2=n1360(4) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1381(5) I3=n1360(0) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=n1381(2) I3=n1360(3) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=n1381(6) I3=n1360(0) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1381(2) I3=n1360(4) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1381(0) I1=n1360(6) I2=n1360(5) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1381(2) I2=n1360(3) I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1381(0) I1=n1360(5) I2=n1360(4) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1381(0) I1=n1360(4) I2=n1360(5) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_I0_O I1=n1395_ff_CQZ_D_LUT4_O_6_I3 I2=n1395_ff_CQZ_D_LUT4_O_6_I2 I3=n1395_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1381(7) I1=n1360(0) I2=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(6) I3=n1360(1) O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(5) I3=n1360(1) O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(4) I3=n1360(2) O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(2) I1=n1381(4) I2=n1360(3) I3=n1381(3) O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1381(7) I3=n1360(1) O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(4) I3=n1360(3) O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=n1381(5) I3=n1360(3) O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_I0_O I3=n1395_ff_CQZ_D_LUT4_O_7_I3 O=n1395_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100000000
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000000000001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1381(3) I2=n1360(0) I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1381(2) I3=n1360(1) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(2) I3=n1360(0) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(1) I3=n1360(1) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(1) I1=n1381(0) I2=n1360(0) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1360(2) I3=n1381(0) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1360(2) I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=n1381(3) I3=n1360(0) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1360(1) I1=n1360(0) I2=n1381(3) I3=n1381(4) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1360(1) I1=n1381(3) I2=n1360(0) I3=n1381(4) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1381(2) I2=n1360(1) I3=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1381(0) I1=n1360(3) I2=n1360(2) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1381(0) I1=n1360(2) I2=n1360(3) I3=n1381(1) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1381(2) I3=n1360(2) O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1381(5) I2=n1360(7) I3=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1360(6) I1=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1381(6) O=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1360(6) I1=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1381(6) O=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1381(5) I2=n1360(6) I3=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(5) O=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(6) I1=n1381(7) I2=n1360(7) I3=n1381(6) O=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(6) I1=n1381(6) I2=n1360(7) I3=n1381(7) O=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=n1381(5) I3=n1360(7) O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n1360(5) I3=n1381(6) O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1395_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=n1381(5) I2=n1360(5) I3=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1381(3) I2=n1360(6) I3=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(4) O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(6) I1=n1381(5) I2=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=n1395_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 O=n1395_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=n1400(7) D=n1400_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5035.1-5040.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1400(6) D=n1400_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5035.1-5040.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1400(5) D=n1400_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5035.1-5040.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1400(4) D=n1400_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5035.1-5040.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1400(3) D=n1400_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5035.1-5040.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1400(2) D=n1400_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5035.1-5040.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1400(1) D=n1400_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5035.1-5040.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1400(0) D=n1400_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5035.1-5040.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1400_ff_CQZ_D_LUT4_O_I1 I2=n1395(7) I3=n1389(7) O=n1400_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1400_ff_CQZ_D_LUT4_O_1_I1 I2=n1395(6) I3=n1389(6) O=n1400_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1389(5) I2=n1395(5) I3=n1400_ff_CQZ_D_LUT4_O_2_I1 O=n1400_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1400_ff_CQZ_D_LUT4_O_2_I1 I2=n1395(5) I3=n1389(5) O=n1400_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1389(4) I2=n1395(4) I3=n1400_ff_CQZ_D_LUT4_O_3_I1 O=n1400_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1400_ff_CQZ_D_LUT4_O_3_I1 I2=n1395(4) I3=n1389(4) O=n1400_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1389(3) I2=n1395(3) I3=n1400_ff_CQZ_D_LUT4_O_4_I1 O=n1400_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1400_ff_CQZ_D_LUT4_O_4_I1 I2=n1395(3) I3=n1389(3) O=n1400_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1389(2) I2=n1395(2) I3=n1400_ff_CQZ_D_LUT4_O_5_I1 O=n1400_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1400_ff_CQZ_D_LUT4_O_5_I1 I2=n1395(2) I3=n1389(2) O=n1400_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1395(1) I1=n1389(1) I2=n1389(0) I3=n1395(0) O=n1400_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1400_ff_CQZ_D_LUT4_O_6_I3 O=n1400_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1389(0) I1=n1395(0) I2=n1395(1) I3=n1389(1) O=n1400_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n1389(0) I2=n1395(0) I3=n2062 O=n1400_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1389(6) I2=n1395(6) I3=n1400_ff_CQZ_D_LUT4_O_1_I1 O=n1400_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=n1406(7) D=n1406_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5041.1-5046.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1406(6) D=n1406_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5041.1-5046.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1406(5) D=n1406_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5041.1-5046.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1406(4) D=n1406_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5041.1-5046.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1406(3) D=n1406_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5041.1-5046.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1406(2) D=n1406_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5041.1-5046.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1406(1) D=n1406_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5041.1-5046.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1406(0) D=n1406_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5041.1-5046.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n1406_ff_CQZ_D_LUT4_O_I3 O=n1406_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_1_I1 I2=n1406_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n1406_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_2_I2 I2=n1406_ff_CQZ_D_LUT4_O_2_I3 I3=n1406_ff_CQZ_D_LUT4_O_2_I1 O=n1406_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1406_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n1406_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1406_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1406_ff_CQZ_D_LUT4_O_2_I1 I2=n1406_ff_CQZ_D_LUT4_O_2_I2 I3=n1406_ff_CQZ_D_LUT4_O_2_I3 O=n1406_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 I2=n1360(12) I3=n1381(6) O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1381(5) I2=n1360(12) I3=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(13) I1=n1381(4) I2=n1360(14) I3=n1381(3) O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(13) I1=n1360(14) I2=n1381(3) I3=n1381(4) O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1360(14) I1=n1381(5) I2=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1360(13) I1=n1381(6) I2=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I3=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(4) I3=n1360(15) O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1360(15) I3=n1381(2) O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1360(15) I1=n1381(3) I2=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(4) I3=n1360(14) O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(5) I3=n1360(13) O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I2=n1381(6) I3=n1360(12) O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(11) O=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1360(13) I3=n1381(6) O=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n1360(15) I3=n1381(3) O=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(12) O=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1381(5) I3=n1360(15) O=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1360(14) I1=n1381(5) I2=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1406_ff_CQZ_D_LUT4_O_3_I3 O=n1406_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1406_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1406_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=n1360(11) I3=n1381(6) O=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I2=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I3=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1406_ff_CQZ_D_LUT4_O_4_I3 O=n1406_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_5_I1 I1=n1406_ff_CQZ_D_LUT4_O_5_I3 I2=n1406_ff_CQZ_D_LUT4_O_5_I2 I3=n1406_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1406_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1406_ff_CQZ_D_LUT4_O_5_I1 I2=n1406_ff_CQZ_D_LUT4_O_5_I2 I3=n1406_ff_CQZ_D_LUT4_O_5_I3 O=n1406_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_5_I1 I1=n1406_ff_CQZ_D_LUT4_O_5_I3 I2=n1406_ff_CQZ_D_LUT4_O_5_I2 I3=n1406_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I3 I2=n1406_ff_CQZ_D_LUT4_O_6_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I1 O=n1406_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1360(10) I3=n1381(6) O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1381(5) I2=n1360(10) I3=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(11) I1=n1381(4) I2=n1360(12) I3=n1381(3) O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(11) I1=n1360(12) I2=n1381(3) I3=n1381(4) O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(9) O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1360(11) I1=n1381(6) I2=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1381(5) I2=n1360(11) I3=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(12) I1=n1360(13) I2=n1381(3) I3=n1381(4) O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(10) O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1360(15) I2=n1381(2) I3=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(1) I3=n1360(14) O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1381(5) I3=n1360(12) O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n2062 I1=n1406_ff_CQZ_D_LUT4_O_6_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I3 O=n1406_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1381(6) I2=n1360(8) I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1381(5) I2=n1360(8) I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(9) I1=n1381(4) I2=n1360(10) I3=n1381(3) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(9) I1=n1360(10) I2=n1381(3) I3=n1381(4) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1381(2) I2=n1360(10) I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(11) I1=n1381(1) I2=n1360(12) I3=n1381(0) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(11) I1=n1360(12) I2=n1381(0) I3=n1381(1) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1381(5) I3=n1360(8) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1381(2) I3=n1360(11) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=n1381(6) I3=n1360(8) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1360(9) I1=n1381(6) I2=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I3=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1381(5) I3=n1360(9) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1381(2) I2=n1360(11) I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(12) I1=n1381(1) I2=n1360(13) I3=n1381(0) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(12) I1=n1360(13) I2=n1381(0) I3=n1381(1) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1381(2) I3=n1360(12) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1381(5) I3=n1360(10) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1360(15) I1=n1381(0) I2=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(2) I3=n1360(13) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1381(2) I2=n1360(12) I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(13) I1=n1381(1) I2=n1360(14) I3=n1381(0) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(13) I1=n1360(14) I2=n1381(0) I3=n1381(1) O=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=n1360(9) I3=n1381(6) O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1381(5) I2=n1360(9) I3=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(10) I1=n1381(4) I2=n1360(11) I3=n1381(3) O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(10) I1=n1360(11) I2=n1381(3) I3=n1381(4) O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(8) O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1360(10) I1=n1381(6) I2=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1360(14) I1=n1381(2) I2=n1360(15) I3=n1381(1) O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1381(5) I3=n1360(11) O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1360(12) I1=n1381(4) I2=n1360(13) I3=n1381(3) O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1360(15) I3=n1381(0) O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1406_ff_CQZ_D_LUT4_O_7_I3 O=n1406_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I0 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1360(8) I3=n1381(0) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(2) I3=n1360(8) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(0) I3=n1360(10) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(1) I3=n1360(9) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1360(8) I1=n1381(3) I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1381(2) I3=n1360(10) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1360(10) I1=n1360(11) I2=n1381(0) I3=n1381(1) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(2) I3=n1360(9) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(10) I1=n1381(1) I2=n1360(11) I3=n1381(0) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(9) I1=n1381(3) I2=n1360(8) I3=n1381(4) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n1360(8) I3=n1381(3) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1360(9) I1=n1360(8) I2=n1381(3) I3=n1381(4) O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_2_I1 I1=n1406_ff_CQZ_D_LUT4_O_2_I3 I2=n1406_ff_CQZ_D_LUT4_O_2_I2 I3=n1406_ff_CQZ_D_LUT4_O_1_I2 O=n1406_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1406_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n1406_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1381(5) I2=n1360(15) I3=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1360(14) I1=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1381(6) O=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1360(14) I1=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1381(6) O=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1381(5) I2=n1360(14) I3=n1406_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(7) I3=n1360(13) O=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(14) I1=n1381(7) I2=n1360(15) I3=n1381(6) O=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(14) I1=n1381(6) I2=n1360(15) I3=n1381(7) O=n1406_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt ff CQZ=n1412(7) D=n1412_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5047.1-5052.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1412(6) D=n1412_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5047.1-5052.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1412(5) D=n1412_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5047.1-5052.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1412(4) D=n1412_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5047.1-5052.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1412(3) D=n1412_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5047.1-5052.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1412(2) D=n1412_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5047.1-5052.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1412(1) D=n1412_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5047.1-5052.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1412(0) D=n1412_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5047.1-5052.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n1412_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1412_ff_CQZ_D_LUT4_O_1_I3 O=n1412_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I1=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I3=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1412_ff_CQZ_D_LUT4_O_2_I3 O=n1412_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_3_I1 I1=n1412_ff_CQZ_D_LUT4_O_3_I3 I2=n1412_ff_CQZ_D_LUT4_O_3_I2 I3=n1412_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1412_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1412_ff_CQZ_D_LUT4_O_3_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I3 O=n1412_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_3_I1 I1=n1412_ff_CQZ_D_LUT4_O_3_I3 I2=n1412_ff_CQZ_D_LUT4_O_3_I2 I3=n1412_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I1=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I3=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1360(3) I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1360(3) I1=n1360(4) I2=n1381(12) I3=n1381(13) O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(2) O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1360(4) I1=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1360(7) I2=n1381(11) I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(10) I3=n1360(6) O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(5) I1=n1381(13) I2=n1360(6) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1360(6) I1=n1381(11) I2=n1360(7) I3=n1381(10) O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1360(3) I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1360(4) I1=n1381(13) I2=n1360(5) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1360(4) I1=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1360(4) I1=n1360(5) I2=n1381(12) I3=n1381(13) O=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(3) O=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1360(6) I1=n1381(13) I2=n1360(7) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(5) I1=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n1360(7) I3=n1381(11) O=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1412_ff_CQZ_D_LUT4_O_4_I3 O=n1412_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1412_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 I3=n1412_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 O=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1381(15) I1=n1360(1) I2=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(14) I3=n1360(2) O=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1412_ff_CQZ_D_LUT4_O_5_I3 O=n1412_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_6_I1 I1=n1412_ff_CQZ_D_LUT4_O_6_I3 I2=n1412_ff_CQZ_D_LUT4_O_6_I2 I3=n1412_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1412_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1412_ff_CQZ_D_LUT4_O_6_I1 I2=n1412_ff_CQZ_D_LUT4_O_6_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3 O=n1412_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_6_I1 I1=n1412_ff_CQZ_D_LUT4_O_6_I3 I2=n1412_ff_CQZ_D_LUT4_O_6_I2 I3=n1412_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1412_ff_CQZ_D_LUT4_O_7_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1 O=n1412_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1360(0) I1=n1381(15) I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(14) I3=n1360(1) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1381(8) I1=n1360(6) I2=n1360(2) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1360(1) I2=n1381(14) I3=n1381(13) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n1360(1) I1=n1381(14) I2=n1360(2) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1381(15) I3=n1360(1) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n1360(2) I2=n1381(14) I3=n1381(13) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n1360(2) I1=n1381(14) I2=n1360(3) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1360(3) I1=n1381(13) I2=n1360(4) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(11) I3=n1360(5) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(9) I3=n1360(7) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1381(9) I2=n1360(6) I3=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(4) I1=n1360(5) I2=n1381(10) I3=n1381(11) O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2 I3=n2062 O=n1412_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1360(0) I2=n1381(14) I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1360(0) I2=n1381(13) I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1381(8) I1=n1360(5) I2=n1360(1) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1381(8) I1=n1360(1) I2=n1360(5) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 I2=n1360(0) I3=n1381(15) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1381(13) I3=n1360(2) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1381(8) I1=n1360(7) I2=n1360(3) I3=n1381(12) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1381(9) I3=n1360(6) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1360(4) I1=n1381(11) I2=n1360(5) I3=n1381(10) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=n1381(9) I2=n1360(5) I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(3) I1=n1360(4) I2=n1381(10) I3=n1381(11) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1381(9) I2=n1360(3) I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(1) I1=n1381(11) I2=n1360(2) I3=n1381(10) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(1) I1=n1360(2) I2=n1381(10) I3=n1381(11) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1360(0) I3=n1381(13) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=n1381(9) I3=n1360(4) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 I2=n1360(0) I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1381(9) I3=n1360(5) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1360(3) I1=n1381(11) I2=n1360(4) I3=n1381(10) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1381(9) I2=n1360(4) I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1360(2) I1=n1381(11) I2=n1360(3) I3=n1381(10) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(2) I1=n1360(3) I2=n1381(10) I3=n1381(11) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1381(13) I3=n1360(1) O=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100100010
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1381(8) I1=n1360(4) I2=n1381(12) I3=n1360(0) O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1381(8) I1=n1360(4) I2=n1381(12) I3=n1360(0) O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(0) I1=n1381(11) I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1381(9) I3=n1360(3) O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001100110010
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1360(3) I3=n1381(8) O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(1) I1=n1381(9) I2=n1381(10) I3=n1360(0) O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1381(10) I1=n1360(0) I2=n1360(2) I3=n1381(8) O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n1360(1) I1=n1381(9) I2=n1381(10) I3=n1360(0) O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1360(1) I1=n1381(10) I2=n1381(11) I3=n1360(0) O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(9) I3=n1360(2) O=n1412_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1381(13) I2=n1360(7) I3=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1360(6) I1=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1360(6) I1=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1360(6) I1=n1360(7) I2=n1381(12) I3=n1381(13) O=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(5) O=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1360(6) I1=n1381(15) I2=n1360(7) I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1360(6) I1=n1381(14) I2=n1360(7) I3=n1381(15) O=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1360(5) I1=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1381(14) O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1360(5) I1=n1360(6) I2=n1381(12) I3=n1381(13) O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1381(15) I3=n1360(4) O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=n1381(13) I3=n1360(7) O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=n1412_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 O=n1412_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=n1417(7) D=n1417_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5053.1-5058.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1417(6) D=n1417_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5053.1-5058.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1417(5) D=n1417_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5053.1-5058.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1417(4) D=n1417_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5053.1-5058.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1417(3) D=n1417_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5053.1-5058.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1417(2) D=n1417_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5053.1-5058.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1417(1) D=n1417_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5053.1-5058.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1417(0) D=n1417_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5053.1-5058.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1417_ff_CQZ_D_LUT4_O_I1 I2=n1406(7) I3=n1412(7) O=n1417_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1417_ff_CQZ_D_LUT4_O_1_I1 I2=n1406(6) I3=n1412(6) O=n1417_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1412(5) I2=n1406(5) I3=n1417_ff_CQZ_D_LUT4_O_2_I1 O=n1417_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1417_ff_CQZ_D_LUT4_O_2_I1 I2=n1406(5) I3=n1412(5) O=n1417_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1412(4) I2=n1406(4) I3=n1417_ff_CQZ_D_LUT4_O_3_I1 O=n1417_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1417_ff_CQZ_D_LUT4_O_3_I1 I2=n1406(4) I3=n1412(4) O=n1417_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1412(3) I2=n1406(3) I3=n1417_ff_CQZ_D_LUT4_O_4_I1 O=n1417_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1417_ff_CQZ_D_LUT4_O_4_I1 I2=n1406(3) I3=n1412(3) O=n1417_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1412(2) I2=n1406(2) I3=n1417_ff_CQZ_D_LUT4_O_5_I1 O=n1417_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1417_ff_CQZ_D_LUT4_O_5_I1 I2=n1406(2) I3=n1412(2) O=n1417_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1406(1) I1=n1412(1) I2=n1406(0) I3=n1412(0) O=n1417_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1417_ff_CQZ_D_LUT4_O_6_I3 O=n1417_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1406(0) I1=n1412(0) I2=n1406(1) I3=n1412(1) O=n1417_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1412(0) I2=n1406(0) I3=n2062 O=n1417_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1412(6) I2=n1406(6) I3=n1417_ff_CQZ_D_LUT4_O_1_I1 O=n1417_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n1424(15) D=n1424_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(14) D=n1424_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(5) D=n1424_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(4) D=n1424_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(3) D=n1424_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(2) D=n1424_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(1) D=n1424_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(0) D=n1424_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(13) D=n1424_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(12) D=n1424_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(11) D=n1424_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(10) D=n1424_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(9) D=n1424_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(8) D=n1424_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(7) D=n1424_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1424(6) D=n1424_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5059.1-5064.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_I1 I2=n1400(7) I3=n1370(7) O=n1424_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_1_I1 I2=n1400(6) I3=n1370(6) O=n1424_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_10_I1 I2=n1417(4) I3=n1378(4) O=n1424_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1378(3) I2=n1417(3) I3=n1424_ff_CQZ_D_LUT4_O_11_I1 O=n1424_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_11_I1 I2=n1417(3) I3=n1378(3) O=n1424_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1378(2) I2=n1417(2) I3=n1424_ff_CQZ_D_LUT4_O_12_I1 O=n1424_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_12_I1 I2=n1417(2) I3=n1378(2) O=n1424_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1417(1) I1=n1378(1) I2=n1378(0) I3=n1417(0) O=n1424_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1424_ff_CQZ_D_LUT4_O_13_I3 O=n1424_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1417(0) I1=n1378(0) I2=n1417(1) I3=n1378(1) O=n1424_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1370(0) I2=n1400(0) I3=n2062 O=n1424_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1378(0) I2=n1417(0) I3=n2062 O=n1424_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1370(5) I2=n1400(5) I3=n1424_ff_CQZ_D_LUT4_O_2_I1 O=n1424_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_2_I1 I2=n1400(5) I3=n1370(5) O=n1424_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1370(4) I2=n1400(4) I3=n1424_ff_CQZ_D_LUT4_O_3_I1 O=n1424_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_3_I1 I2=n1400(4) I3=n1370(4) O=n1424_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1370(3) I2=n1400(3) I3=n1424_ff_CQZ_D_LUT4_O_4_I1 O=n1424_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_4_I1 I2=n1400(3) I3=n1370(3) O=n1424_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1370(2) I2=n1400(2) I3=n1424_ff_CQZ_D_LUT4_O_5_I1 O=n1424_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_5_I1 I2=n1400(2) I3=n1370(2) O=n1424_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1400(1) I1=n1370(1) I2=n1370(0) I3=n1400(0) O=n1424_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1424_ff_CQZ_D_LUT4_O_6_I3 O=n1424_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1400(0) I1=n1370(0) I2=n1400(1) I3=n1370(1) O=n1424_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_7_I1 I2=n1417(7) I3=n1378(7) O=n1424_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1378(6) I2=n1417(6) I3=n1424_ff_CQZ_D_LUT4_O_8_I1 O=n1424_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_8_I1 I2=n1417(6) I3=n1378(6) O=n1424_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1378(5) I2=n1417(5) I3=n1424_ff_CQZ_D_LUT4_O_9_I1 O=n1424_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1424_ff_CQZ_D_LUT4_O_9_I1 I2=n1417(5) I3=n1378(5) O=n1424_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1378(4) I2=n1417(4) I3=n1424_ff_CQZ_D_LUT4_O_10_I1 O=n1424_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n1370(6) I2=n1400(6) I3=n1424_ff_CQZ_D_LUT4_O_1_I1 O=n1424_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n129(6) I2=n142_LUT4_I3_I2 I3=n142 O=n231_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=n1019 I1=n51_LUT4_I3_O I2=n129(6) I3=n142_LUT4_I3_I2 O=n142_LUT4_I3_I2_LUT4_I3_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n142_LUT4_I3_I2_LUT4_O_I3 I1=n129(4) I2=n129(5) I3=n51_LUT4_I3_O O=n142_LUT4_I3_I2_LUT4_I3_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1019 I1=n51_LUT4_I3_O I2=n129(4) I3=n142_LUT4_I3_I2_LUT4_O_I3 O=n142_LUT4_I3_I2_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n51_LUT4_I3_O I3=n142_LUT4_I3_I2_LUT4_I3_O_LUT4_O_2_I3 O=n142_LUT4_I3_I2_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n129(0) I1=n129(1) I2=n129(2) I3=n129(3) O=n142_LUT4_I3_I2_LUT4_I3_O_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n129(0) I1=n129(1) I2=n129(2) I3=n51_LUT4_I3_O O=n142_LUT4_I3_I2_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1019 I1=n51_LUT4_I3_O I2=n129(1) I3=n129(0) O=n142_LUT4_I3_I2_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n51_LUT4_I3_O I3=n129(0) O=n142_LUT4_I3_I2_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n129(5) I2=n129(4) I3=n142_LUT4_I3_I2_LUT4_O_I3 O=n142_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n129(0) I1=n129(1) I2=n129(2) I3=n129(3) O=n142_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=n142 D=n142_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3583.1-3588.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(15) D=n1431_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(14) D=n1431_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(5) D=n1431_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(4) D=n1431_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(3) D=n1431_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(2) D=n1431_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(1) D=n1431_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(0) D=n1424_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(13) D=n1431_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(12) D=n1431_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(11) D=n1431_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(10) D=n1431_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(9) D=n1431_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(8) D=n1424_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(7) D=n1431_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1431(6) D=n1431_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5065.1-5070.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_I1 I2=n1400(7) I3=n1370(7) O=n1431_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_1_I1 I2=n1400(6) I3=n1370(6) O=n1431_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_10_I1 I2=n1417(4) I3=n1378(4) O=n1431_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1378(3) I2=n1417(3) I3=n1431_ff_CQZ_D_LUT4_O_11_I1 O=n1431_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_11_I1 I2=n1417(3) I3=n1378(3) O=n1431_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1378(2) I2=n1417(2) I3=n1431_ff_CQZ_D_LUT4_O_12_I1 O=n1431_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_12_I1 I2=n1417(2) I3=n1378(2) O=n1431_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1417(1) I1=n1378(1) I2=n1378(0) I3=n1417(0) O=n1431_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1431_ff_CQZ_D_LUT4_O_13_I3 O=n1431_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1378(0) I1=n1417(0) I2=n1417(1) I3=n1378(1) O=n1431_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n1370(5) I2=n1400(5) I3=n1431_ff_CQZ_D_LUT4_O_2_I1 O=n1431_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_2_I1 I2=n1400(5) I3=n1370(5) O=n1431_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1370(4) I2=n1400(4) I3=n1431_ff_CQZ_D_LUT4_O_3_I1 O=n1431_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_3_I1 I2=n1400(4) I3=n1370(4) O=n1431_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1370(3) I2=n1400(3) I3=n1431_ff_CQZ_D_LUT4_O_4_I1 O=n1431_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_4_I1 I2=n1400(3) I3=n1370(3) O=n1431_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1370(2) I2=n1400(2) I3=n1431_ff_CQZ_D_LUT4_O_5_I1 O=n1431_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_5_I1 I2=n1400(2) I3=n1370(2) O=n1431_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1400(1) I1=n1370(1) I2=n1370(0) I3=n1400(0) O=n1431_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1431_ff_CQZ_D_LUT4_O_6_I3 O=n1431_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1370(0) I1=n1400(0) I2=n1400(1) I3=n1370(1) O=n1431_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_7_I1 I2=n1417(7) I3=n1378(7) O=n1431_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1378(6) I2=n1417(6) I3=n1431_ff_CQZ_D_LUT4_O_8_I1 O=n1431_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_8_I1 I2=n1417(6) I3=n1378(6) O=n1431_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1378(5) I2=n1417(5) I3=n1431_ff_CQZ_D_LUT4_O_9_I1 O=n1431_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1431_ff_CQZ_D_LUT4_O_9_I1 I2=n1417(5) I3=n1378(5) O=n1431_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1378(4) I2=n1417(4) I3=n1431_ff_CQZ_D_LUT4_O_10_I1 O=n1431_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1370(6) I2=n1400(6) I3=n1431_ff_CQZ_D_LUT4_O_1_I1 O=n1431_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1436 I3=n2062 O=n1440_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1436 D=n1436_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5071.1-5076.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1440 I3=n2062 O=n1444_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1440 D=n1440_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5077.1-5082.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1444 I3=n2062 O=n1448_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1444 D=n1444_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5083.1-5088.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1448 O=n1448_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1448_LUT4_I3_O I2=n1488(4) I3=n1448_LUT4_I3_O_LUT4_I1_I3 O=n1448_LUT4_I3_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1448_LUT4_I3_O I2=n1488(1) I3=n1488(0) O=n1448_LUT4_I3_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1488(0) I1=n1488(1) I2=n1488(2) I3=n1488(3) O=n1448_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1448_LUT4_I3_O I3=n1448_LUT4_I3_O_LUT4_I2_I3 O=n1448_LUT4_I3_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1448_LUT4_I3_O I3=n1488(0) O=n1448_LUT4_I3_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1488(0) I1=n1488(1) I2=n1488(2) I3=n1488(3) O=n1448_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n1448_LUT4_I3_O_LUT4_I1_I3 I1=n1488(4) I2=n1488(5) I3=n1448_LUT4_I3_O O=n1448_LUT4_I3_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1488(0) I1=n1488(1) I2=n1488(2) I3=n1448_LUT4_I3_O O=n1448_LUT4_I3_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n1448 D=n1448_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5089.1-5094.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1335(0) I1=n1335(1) I2=n1335(2) I3=n1259_LUT4_I3_O O=n1466_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1335(2) I1=n1335(0) I2=n1335(1) I3=n1335(3) O=n1466_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n1019 I1=n1335(1) I2=n1335(0) I3=n1466_LUT4_I2_I3 O=n1348_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(3) I3=n1335(2) O=n1466_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1259_LUT4_I3_O I2=n1335(1) I3=n1335(0) O=n1466_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1259_LUT4_I3_O I3=n1335(0) O=n1466_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1335(0) D=n1466_LUT4_I3_O(0) QCK=$iopadmap$clock_c QEN=n2079 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4933.1-4938.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1470 I3=n2062 O=n1474_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1470 D=n1470_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5119.1-5124.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1335(0) I3=n2062 O=n1470_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1474 I3=n2062 O=n1478_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1474 D=n1474_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5125.1-5130.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1478 I3=n2062 O=n1482_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1478 D=n1478_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5131.1-5136.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1482 I2=n2059 I3=n1527(0) O=n1482_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1482 I2=n2059 I3=n1527(0) O=n1482_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n1482 I3=n1490(0) O=n1482_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=n1482 D=n1482_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5137.1-5142.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1488(5) D=n1448_LUT4_I3_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5143.1-5148.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1488(4) D=n1448_LUT4_I3_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5143.1-5148.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1488(3) D=n1448_LUT4_I3_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5143.1-5148.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1488(2) D=n1448_LUT4_I3_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5143.1-5148.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1488(1) D=n1448_LUT4_I3_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5143.1-5148.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1488(0) D=n1448_LUT4_I3_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5143.1-5148.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(15) D=n148_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(14) D=n148_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(5) D=n148_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(4) D=n148_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(3) D=n148_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(2) D=n148_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(1) D=n148_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(0) D=n148_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(13) D=n148_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(12) D=n148_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(11) D=n148_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(10) D=n148_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(9) D=n148_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(8) D=n148_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(7) D=n148_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n148(6) D=n148_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3589.1-3594.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_O I3=n72_LUT4_I2_O O=n148_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_1_O I3=n72_LUT4_I2_1_O O=n148_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_10_O I3=n72_LUT4_I2_10_O O=n148_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_11_O I3=n72_LUT4_I2_11_O O=n148_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_12_O I3=n72_LUT4_I2_12_O O=n148_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_13_O I3=n72_LUT4_I2_13_O O=n148_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_14_O I3=n72_LUT4_I2_14_O O=n148_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_15_O I3=n72_LUT4_I2_15_O O=n148_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_2_O I3=n72_LUT4_I2_2_O O=n148_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_3_O I3=n72_LUT4_I2_3_O O=n148_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_4_O I3=n72_LUT4_I2_4_O O=n148_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_5_O I3=n72_LUT4_I2_5_O O=n148_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_6_O I3=n72_LUT4_I2_6_O O=n148_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_7_O I3=n72_LUT4_I2_7_O O=n148_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_8_O I3=n72_LUT4_I2_8_O O=n148_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n72_LUT4_I3_9_O I3=n72_LUT4_I2_9_O O=n148_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1490(0) I2=n2059 I3=n1482 O=n1495_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n1490(0) D=n1495_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5149.1-5154.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1448 I2=n1490(0) I3=n2062 O=n1495_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1500 I3=n2073_LUT4_O_I3 O=n1589_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1500 O=n1500_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1500_LUT4_I3_O I2=n1576(4) I3=n1589_LUT4_I3_I1 O=n1707_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1500_LUT4_I3_O I3=n1500_LUT4_I3_O_LUT4_I2_I3 O=n1707_LUT4_I3_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1589_LUT4_I3_I1 I1=n1576(5) I2=n1576(4) I3=n1576(6) O=n1500_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n1589_LUT4_I3_I1 I1=n1576(4) I2=n1576(5) I3=n1500_LUT4_I3_O O=n1707_LUT4_I3_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n1500 D=n1500_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5155.1-5160.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1448 I3=n2062 O=n1500_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1511(31) D=n1424(15) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(30) D=n1424(14) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(21) D=n1424(5) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(20) D=n1424(4) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(19) D=n1424(3) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(18) D=n1424(2) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(17) D=n1424(1) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1511(16) D=n1424(0) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(15) D=n1431(15) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(14) D=n1431(14) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(13) D=n1431(13) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(12) D=n1431(12) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(29) D=n1424(13) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(11) D=n1431(11) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(10) D=n1431(10) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(9) D=n1431(9) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(8) D=n1431(8) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(7) D=n1431(7) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(6) D=n1431(6) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1511(5) D=n1431(5) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1511(4) D=n1431(4) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1511(3) D=n1431(3) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1511(2) D=n1431(2) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1511(28) D=n1424(12) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(1) D=n1431(1) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(0) D=n1431(0) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(27) D=n1424(11) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(26) D=n1424(10) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(25) D=n1424(9) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(24) D=n1424(8) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(23) D=n1424(7) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1511(22) D=n1424(6) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5161.1-5165.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(31) D=n1424(15) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(30) D=n1424(14) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(21) D=n1424(5) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(20) D=n1424(4) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(19) D=n1424(3) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(18) D=n1424(2) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(17) D=n1424(1) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(16) D=n1424(0) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(15) D=n1431(15) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(14) D=n1431(14) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(13) D=n1431(13) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(12) D=n1431(12) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(29) D=n1424(13) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(11) D=n1431(11) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(10) D=n1431(10) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(9) D=n1431(9) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(8) D=n1431(8) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(7) D=n1431(7) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(6) D=n1431(6) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(5) D=n1431(5) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(4) D=n1431(4) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(3) D=n1431(3) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(2) D=n1431(2) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(28) D=n1424(12) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(1) D=n1431(1) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(0) D=n1431(0) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(27) D=n1424(11) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(26) D=n1424(10) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(25) D=n1424(9) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(24) D=n1424(8) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(23) D=n1424(7) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1515(22) D=n1424(6) QCK=$iopadmap$clock_c QEN=n1495_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5171.1-5175.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1515(15) I1=n1511(15) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(14) I1=n1511(14) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(5) I1=n1511(5) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(4) I1=n1511(4) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(3) I1=n1511(3) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(2) I1=n1511(2) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(1) I1=n1511(1) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1511(0) I1=n1515(0) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1515(13) I1=n1511(13) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(12) I1=n1511(12) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(11) I1=n1511(11) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(10) I1=n1511(10) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(9) I1=n1511(9) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(8) I1=n1511(8) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(7) I1=n1511(7) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(6) I1=n1511(6) I2=n1519 I3=n1560(0) O=n1519_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1515(31) I1=n1511(31) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(30) I1=n1511(30) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(21) I1=n1511(21) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(20) I1=n1511(20) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(19) I1=n1511(19) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(18) I1=n1511(18) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(17) I1=n1511(17) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(16) I1=n1511(16) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(29) I1=n1511(29) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(28) I1=n1511(28) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(27) I1=n1511(27) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(26) I1=n1511(26) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(25) I1=n1511(25) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(24) I1=n1511(24) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(23) I1=n1511(23) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1515(22) I1=n1511(22) I2=n1560(0) I3=n1519 O=n1519_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n1519 D=n1519_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5181.1-5186.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1490(0) O=n1519_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n1527(0) D=n1532_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5193.1-5198.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1527(0) I2=n1448 I3=n2062 O=n1532_ff_CQZ_D
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+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
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+.subckt ff CQZ=n1548(31) D=n1424(15) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(30) D=n1424(14) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(21) D=n1424(5) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(20) D=n1424(4) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(19) D=n1424(3) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1548(18) D=n1424(2) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(17) D=n1424(1) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1548(16) D=n1424(0) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(15) D=n1431(15) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(14) D=n1431(14) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(13) D=n1431(13) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(12) D=n1431(12) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(29) D=n1424(13) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(11) D=n1431(11) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(10) D=n1431(10) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(9) D=n1431(9) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(8) D=n1431(8) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(7) D=n1431(7) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(6) D=n1431(6) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(5) D=n1431(5) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(4) D=n1431(4) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(3) D=n1431(3) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(2) D=n1431(2) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(28) D=n1424(12) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(1) D=n1431(1) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(0) D=n1431(0) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(27) D=n1424(11) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(26) D=n1424(10) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(25) D=n1424(9) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(24) D=n1424(8) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(23) D=n1424(7) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1548(22) D=n1424(6) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5199.1-5203.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(15) D=n154_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(14) D=n154_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(5) D=n154_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(4) D=n154_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(3) D=n154_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(2) D=n154_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(1) D=n154_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(0) D=n154_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(13) D=n154_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(12) D=n154_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(11) D=n154_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(10) D=n154_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(9) D=n154_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(8) D=n154_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(7) D=n154_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n154(6) D=n154_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3595.1-3600.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_O I3=n109_LUT4_I2_O O=n154_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_1_O I3=n109_LUT4_I2_1_O O=n154_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_10_O I3=n109_LUT4_I2_10_O O=n154_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_11_O I3=n109_LUT4_I2_11_O O=n154_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_12_O I3=n109_LUT4_I2_12_O O=n154_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_13_O I3=n109_LUT4_I2_13_O O=n154_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_14_O I3=n109_LUT4_I2_14_O O=n154_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_15_O I3=n109_LUT4_I2_15_O O=n154_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_2_O I3=n109_LUT4_I2_2_O O=n154_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_3_O I3=n109_LUT4_I2_3_O O=n154_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_4_O I3=n109_LUT4_I2_4_O O=n154_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_5_O I3=n109_LUT4_I2_5_O O=n154_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_6_O I3=n109_LUT4_I2_6_O O=n154_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_7_O I3=n109_LUT4_I2_7_O O=n154_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_8_O I3=n109_LUT4_I2_8_O O=n154_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n109_LUT4_I3_9_O I3=n109_LUT4_I2_9_O O=n154_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=n1552(31) D=n1424(15) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(30) D=n1424(14) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(21) D=n1424(5) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(20) D=n1424(4) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(19) D=n1424(3) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(18) D=n1424(2) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(17) D=n1424(1) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(16) D=n1424(0) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(15) D=n1431(15) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(14) D=n1431(14) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(13) D=n1431(13) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(12) D=n1431(12) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(29) D=n1424(13) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(11) D=n1431(11) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(10) D=n1431(10) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(9) D=n1431(9) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(8) D=n1431(8) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(7) D=n1431(7) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(6) D=n1431(6) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(5) D=n1431(5) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(4) D=n1431(4) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(3) D=n1431(3) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(2) D=n1431(2) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(28) D=n1424(12) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(1) D=n1431(1) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(0) D=n1431(0) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(27) D=n1424(11) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(26) D=n1424(10) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(25) D=n1424(9) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(24) D=n1424(8) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(23) D=n1424(7) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1552(22) D=n1424(6) QCK=$iopadmap$clock_c QEN=n1482_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5209.1-5213.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1552(15) I1=n1548(15) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(14) I1=n1548(14) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(5) I1=n1548(5) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(4) I1=n1548(4) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(3) I1=n1548(3) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(2) I1=n1548(2) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(1) I1=n1548(1) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1548(0) I1=n1552(0) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1552(13) I1=n1548(13) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(12) I1=n1548(12) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(11) I1=n1548(11) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(10) I1=n1548(10) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(9) I1=n1548(9) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(8) I1=n1548(8) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(7) I1=n1548(7) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(6) I1=n1548(6) I2=n1556 I3=n1560(0) O=n1556_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1552(31) I1=n1548(31) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(30) I1=n1548(30) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(21) I1=n1548(21) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(20) I1=n1548(20) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(19) I1=n1548(19) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(18) I1=n1548(18) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(17) I1=n1548(17) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(16) I1=n1548(16) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(29) I1=n1548(29) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(28) I1=n1548(28) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(27) I1=n1548(27) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(26) I1=n1548(26) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(25) I1=n1548(25) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(24) I1=n1548(24) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(23) I1=n1548(23) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1552(22) I1=n1548(22) I2=n1560(0) I3=n1556 O=n1556_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n1556 D=n1556_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5219.1-5224.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1527(0) O=n1556_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n1560(0) D=n1565_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5225.1-5230.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1500_LUT4_I3_O I3=n1565_ff_CQZ_D_LUT4_O_I3 O=n1565_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1488(1) I1=n1488(0) I2=n1565_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1560(0) O=n1565_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n1488(2) I1=n1488(3) I2=n1488(4) I3=n1488(5) O=n1565_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=n1576(6) D=n1707_LUT4_I3_O(6) QCK=$iopadmap$clock_c QEN=n2073 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5231.1-5236.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1576(5) D=n1707_LUT4_I3_O(5) QCK=$iopadmap$clock_c QEN=n2073 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5231.1-5236.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1576(4) D=n1707_LUT4_I3_O(4) QCK=$iopadmap$clock_c QEN=n2073 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5231.1-5236.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1576(3) D=n1707_LUT4_I3_O(3) QCK=$iopadmap$clock_c QEN=n2073 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5231.1-5236.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1576(2) D=n1707_LUT4_I3_O(2) QCK=$iopadmap$clock_c QEN=n2073 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5231.1-5236.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1576(1) D=n1707_LUT4_I3_O(1) QCK=$iopadmap$clock_c QEN=n2073 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5231.1-5236.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1580(0) I2=n1589_LUT4_I3_I1 I3=n1589_LUT4_I3_I2 O=n2073_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt ff CQZ=n1580(0) D=n1589_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5237.1-5242.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1589_LUT4_I3_I1 I2=n1589_LUT4_I3_I2 I3=n1589 O=n1677_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2 I1=n1576(2) I2=n1589_LUT4_I3_I2_LUT4_I0_I2 I3=n1576(1) O=n1589_LUT4_I3_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111010
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=n1576(3) I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I2_I0 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(4) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(2) I3=n1576(1) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(2) I3=n1576(1) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1576(1) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I0 I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(1) I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I3 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 I2=n1576(4) I3=n1576(3) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I0 I1=n1576(2) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I0 I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=n1707_LUT4_I1_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(6) I3=n1576(5) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I0 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(5) I3=n1576(6) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I2=n1576(1) I3=n1576(2) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0 I1=n1576(6) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001011111111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(3) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_10_I1 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I0 I2=n1576(1) I3=n1576(2) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101000100010011
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I0 I1=n1589_LUT4_I3_I2_LUT4_O_I3 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010011111111
+.subckt LUT4 I0=n1019 I1=n1576(4) I2=n1707_LUT4_I1_2_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1576(3) I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 I3=n1576(2) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I3_LUT4_O_I1 I2=n1707_LUT4_I1_I0 I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I2 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I3 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 I3=n1589_LUT4_I3_I2_LUT4_I2_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I0 I1=n1589_LUT4_I3_I2_LUT4_I2_I0 I2=n1576(1) I3=n1576(2) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011000000
+.subckt LUT4 I0=n1576(6) I1=n1576(5) I2=n1576(4) I3=n1707_LUT4_I1_2_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000000100000000
+.subckt LUT4 I0=n1707_LUT4_I1_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_O_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(4) I3=n1576(3) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I1=n1576(2) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I1 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=n1576(2) I1=n1576(5) I2=n1576(4) I3=n1576(3) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I0 I1=n1576(1) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I0 I1=n1576(6) I2=n1576(5) I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_I2 I1=n1576(1) I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 I3=n1576(2) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010111001111
+.subckt LUT4 I0=n1576(2) I1=n1589_LUT4_I3_I2_LUT4_I2_I0 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I0 I3=n1576(1) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I3 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I0 I1=n1576(2) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I0 I3=n1576(1) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010111001111
+.subckt LUT4 I0=n1019 I1=n1576(4) I2=n1576(3) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1576(2) I1=n1576(4) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1576(3) I1=n1576(1) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I0 I1=n1576(1) I2=n1576(2) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111101
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 I2=n1576(1) I3=n1707_LUT4_I1_2_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_O_I3 I2=n1576(4) I3=n1707_LUT4_I1_2_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_O_I3 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=n1576(3) I1=n1576(2) I2=n1576(1) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I1 I3=n1707_LUT4_I1_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 I1=n1589_LUT4_I3_I2_LUT4_I2_I0 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 I1=n1589_LUT4_I3_I2_LUT4_I0_I2 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_I2 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_O_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_I3_O O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011111111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_I2 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_I3_O O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1576(4) I1=n1707_LUT4_I1_2_I3 I2=n1576(5) I3=n1576(6) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_I2 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1 I2=n1576(2) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011111111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I3 O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(2) I3=n1576(1) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(4) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I2 I3=n1576(3) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_O_I3 I3=n1576(4) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I3_LUT4_O_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(4) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 I1=n1707_LUT4_I1_2_I3 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I0 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_I3_O O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001011111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(5) I3=n1576(6) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1576(3) I1=n1576(1) I2=n1576(2) I3=n1576(4) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=n1576(3) I1=n1576(1) I2=n1576(2) I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000100000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I2 I2=n1576(3) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I3_LUT4_O_I0 I1=n1576(3) I2=n1576(1) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=n1576(1) I1=n1589_LUT4_I3_I2_LUT4_I0_I2 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I2 I3=n1576(2) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I2=n1589_LUT4_I3_I2_LUT4_O_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=n1019 I1=n1576(1) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=n1576(5) I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0_LUT4_O_I2 I3=n1576(6) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=n1576(2) I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I2=n1707_LUT4_I1_2_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I3_LUT4_O_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1576(2) I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 I2=n1576(1) I3=n1576(3) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111001100111111
+.subckt LUT4 I0=n1707_LUT4_I1_2_I3 I1=n1576(1) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_I2 I2=n1576(1) I3=n1576(2) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I2 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I2=n1589_LUT4_I3_I2_LUT4_O_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I0 I1=n1576(6) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010011111111
+.subckt LUT4 I0=n1576(5) I1=n1576(1) I2=n1576(4) I3=n1576(3) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111001111111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0 I1=n1576(1) I2=n1576(4) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1019 I1=n1576(2) I2=n1576(1) I3=n1576(3) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000011
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I1 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_O_I3 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 I2=n1576(3) I3=n1576(4) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I3 I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I0 I2=n1576(2) I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1576(2) I1=n1576(3) I2=n1576(1) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_I3_O I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=n1576(5) I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I0_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I0_LUT4_O_I2 I3=n1576(6) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=n1576(3) I1=n1576(4) I2=n1576(2) I3=n1576(1) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101011101100
+.subckt LUT4 I0=n1576(1) I1=n1576(3) I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_I1_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101001101
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I1=n1576(1) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I1=n1576(1) I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1576(1) I1=n1576(2) I2=n1576(3) I3=n1576(4) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_I2 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=n1019 I1=n1576(2) I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 I3=n1589_LUT4_I3_I2_LUT4_I2_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I0 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I2 I3=n1576(4) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000111110011
+.subckt LUT4 I0=n1576(3) I1=n1576(4) I2=n1707_LUT4_I1_I0 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0 I2=n1576(2) I3=n1576(5) O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(3) I3=n1707_LUT4_I1_I0 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1576(1) I1=n1589_LUT4_I3_I2_LUT4_I0_I2 I2=n1576(2) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_I3_O O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000011011111
+.subckt LUT4 I0=n1576(2) I1=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1 I2=n1576(3) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I3_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I2 I1=n1576(3) I2=n1576(2) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_I0 I1=n1576(3) I2=n1589_LUT4_I3_I2 I3=n1576(1) O=n1589_LUT4_I3_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010111001111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I0 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0 I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2 I3=n1589_LUT4_I3_I2_LUT4_I2_O O=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=n1576(1) I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 I2=n1576(2) I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=n1576(4) O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(3) I3=n1576(4) O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1576(3) I1=n1576(2) I2=n1576(1) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(4) I3=n1576(3) O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I0 I1=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I0_LUT4_O_I3 I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=n1019 I1=n1576(4) I2=n1576(3) I3=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I0 I3=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 O=n1589_LUT4_I3_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(4) I3=n1589_LUT4_I3_I2_LUT4_O_I3 O=n1589_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(5) I3=n1576(6) O=n1589_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=n1589 D=n1589_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5243.1-5248.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(15) D=n1595_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(14) D=n1595_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(5) D=n1595_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(4) D=n1595_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(3) D=n1595_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(2) D=n1595_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(1) D=n1595_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(0) D=n1595_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(13) D=n1595_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(12) D=n1595_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(11) D=n1595_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(10) D=n1595_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(9) D=n1595_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(8) D=n1595_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(7) D=n1595_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1595(6) D=n1595_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5249.1-5254.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_O I3=n1519_LUT4_I2_O O=n1595_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_1_O I3=n1519_LUT4_I2_1_O O=n1595_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_10_O I3=n1519_LUT4_I2_10_O O=n1595_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_11_O I3=n1519_LUT4_I2_11_O O=n1595_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_12_O I3=n1519_LUT4_I2_12_O O=n1595_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_13_O I3=n1519_LUT4_I2_13_O O=n1595_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_14_O I3=n1519_LUT4_I2_14_O O=n1595_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_15_O I3=n1519_LUT4_I2_15_O O=n1595_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_2_O I3=n1519_LUT4_I2_2_O O=n1595_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_3_O I3=n1519_LUT4_I2_3_O O=n1595_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_4_O I3=n1519_LUT4_I2_4_O O=n1595_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_5_O I3=n1519_LUT4_I2_5_O O=n1595_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_6_O I3=n1519_LUT4_I2_6_O O=n1595_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_7_O I3=n1519_LUT4_I2_7_O O=n1595_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_8_O I3=n1519_LUT4_I2_8_O O=n1595_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1519_LUT4_I3_9_O I3=n1519_LUT4_I2_9_O O=n1595_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=n1601(15) D=n1601_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(14) D=n1601_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(5) D=n1601_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(4) D=n1601_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(3) D=n1601_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(2) D=n1601_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(1) D=n1601_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(0) D=n1601_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(13) D=n1601_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(12) D=n1601_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(11) D=n1601_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(10) D=n1601_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(9) D=n1601_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(8) D=n1601_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(7) D=n1601_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1601(6) D=n1601_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5255.1-5260.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_O I3=n1556_LUT4_I2_O O=n1601_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_1_O I3=n1556_LUT4_I2_1_O O=n1601_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_10_O I3=n1556_LUT4_I2_10_O O=n1601_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_11_O I3=n1556_LUT4_I2_11_O O=n1601_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_12_O I3=n1556_LUT4_I2_12_O O=n1601_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_13_O I3=n1556_LUT4_I2_13_O O=n1601_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_14_O I3=n1556_LUT4_I2_14_O O=n1601_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_15_O I3=n1556_LUT4_I2_15_O O=n1601_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_2_O I3=n1556_LUT4_I2_2_O O=n1601_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_3_O I3=n1556_LUT4_I2_3_O O=n1601_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_4_O I3=n1556_LUT4_I2_4_O O=n1601_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_5_O I3=n1556_LUT4_I2_5_O O=n1601_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_6_O I3=n1556_LUT4_I2_6_O O=n1601_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_7_O I3=n1556_LUT4_I2_7_O O=n1601_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_8_O I3=n1556_LUT4_I2_8_O O=n1601_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1556_LUT4_I3_9_O I3=n1556_LUT4_I2_9_O O=n1601_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1607(7) I3=n2062 O=n1611_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1607(6) I3=n2062 O=n1611_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1607(5) I3=n2062 O=n1611_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1607(4) I3=n2062 O=n1611_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1607(3) I3=n2062 O=n1611_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1607(2) I3=n2062 O=n1611_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1607(1) I3=n2062 O=n1611_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1607(0) I3=n2062 O=n1611_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1607(7) D=n1607_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5261.1-5266.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1607(6) D=n1607_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5261.1-5266.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1607(5) D=n1607_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5261.1-5266.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1607(4) D=n1607_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5261.1-5266.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1607(3) D=n1607_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5261.1-5266.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1607(2) D=n1607_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5261.1-5266.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1607(1) D=n1607_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5261.1-5266.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1607(0) D=n1607_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5261.1-5266.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(15) I3=n2062 O=n1607_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(14) I3=n2062 O=n1607_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(13) I3=n2062 O=n1607_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(12) I3=n2062 O=n1607_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(11) I3=n2062 O=n1607_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(10) I3=n2062 O=n1607_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(9) I3=n2062 O=n1607_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(8) I3=n2062 O=n1607_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1611(7) D=n1611_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5267.1-5272.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1611(6) D=n1611_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5267.1-5272.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1611(5) D=n1611_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5267.1-5272.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1611(4) D=n1611_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5267.1-5272.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1611(3) D=n1611_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5267.1-5272.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1611(2) D=n1611_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5267.1-5272.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1611(1) D=n1611_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5267.1-5272.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1611(0) D=n1611_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5267.1-5272.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1615(7) I3=n2062 O=n1619_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1615(6) I3=n2062 O=n1619_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1615(5) I3=n2062 O=n1619_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1615(4) I3=n2062 O=n1619_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1615(3) I3=n2062 O=n1619_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1615(2) I3=n2062 O=n1619_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1615(1) I3=n2062 O=n1619_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1615(0) I3=n2062 O=n1619_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1615(7) D=n1615_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5273.1-5278.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1615(6) D=n1615_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5273.1-5278.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1615(5) D=n1615_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5273.1-5278.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1615(4) D=n1615_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5273.1-5278.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1615(3) D=n1615_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5273.1-5278.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1615(2) D=n1615_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5273.1-5278.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1615(1) D=n1615_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5273.1-5278.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1615(0) D=n1615_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5273.1-5278.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(7) I3=n2062 O=n1615_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(6) I3=n2062 O=n1615_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(5) I3=n2062 O=n1615_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(4) I3=n2062 O=n1615_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(3) I3=n2062 O=n1615_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(2) I3=n2062 O=n1615_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(1) I3=n2062 O=n1615_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1595(0) I3=n2062 O=n1615_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1619(7) D=n1619_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5279.1-5284.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1619(6) D=n1619_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5279.1-5284.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1619(5) D=n1619_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5279.1-5284.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1619(4) D=n1619_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5279.1-5284.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1619(3) D=n1619_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5279.1-5284.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1619(2) D=n1619_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5279.1-5284.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1619(1) D=n1619_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5279.1-5284.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1619(0) D=n1619_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5279.1-5284.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n161(7) I3=n2062 O=n165_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n161(6) I3=n2062 O=n165_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n161(5) I3=n2062 O=n165_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n161(4) I3=n2062 O=n165_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n161(3) I3=n2062 O=n165_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n161(2) I3=n2062 O=n165_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n161(1) I3=n2062 O=n165_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n161(0) I3=n2062 O=n165_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n161(7) D=n161_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3601.1-3606.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n161(6) D=n161_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3601.1-3606.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n161(5) D=n161_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3601.1-3606.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n161(4) D=n161_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3601.1-3606.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n161(3) D=n161_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3601.1-3606.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n161(2) D=n161_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3601.1-3606.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n161(1) D=n161_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3601.1-3606.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n161(0) D=n161_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3601.1-3606.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(15) I3=n2062 O=n161_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(14) I3=n2062 O=n161_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(13) I3=n2062 O=n161_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(12) I3=n2062 O=n161_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(11) I3=n2062 O=n161_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(10) I3=n2062 O=n161_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(9) I3=n2062 O=n161_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(8) I3=n2062 O=n161_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1622(15) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(14) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(5) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(4) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(3) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(2) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(1) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(0) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(13) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(12) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(11) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(10) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(9) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(8) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(7) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1622(6) D=n1589_LUT4_I3_I2_LUT4_I0_O_LUT4_I1_O(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5285.1-5352.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1630(7) D=n1630_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5353.1-5358.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1630(6) D=n1630_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5353.1-5358.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1630(5) D=n1630_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5353.1-5358.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1630(4) D=n1630_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5353.1-5358.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1630(3) D=n1630_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5353.1-5358.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1630(2) D=n1630_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5353.1-5358.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1630(1) D=n1630_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5353.1-5358.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1630(0) D=n1630_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5353.1-5358.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n1630_ff_CQZ_D_LUT4_O_I3 O=n1630_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_1_I1 I2=n1630_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n1630_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_2_I2 I2=n1630_ff_CQZ_D_LUT4_O_2_I3 I3=n1630_ff_CQZ_D_LUT4_O_2_I1 O=n1630_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1630_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n1630_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1630_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1630_ff_CQZ_D_LUT4_O_2_I1 I2=n1630_ff_CQZ_D_LUT4_O_2_I2 I3=n1630_ff_CQZ_D_LUT4_O_2_I3 O=n1630_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 I2=n1601(12) I3=n1622(14) O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1622(13) I2=n1601(12) I3=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(13) I1=n1622(12) I2=n1601(14) I3=n1622(11) O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(13) I1=n1601(14) I2=n1622(11) I3=n1622(12) O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1601(14) I1=n1622(13) I2=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1601(13) I1=n1622(14) I2=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I3=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(12) I3=n1601(15) O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1601(15) I3=n1622(10) O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1601(15) I1=n1622(11) I2=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(12) I3=n1601(14) O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(13) I3=n1601(13) O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I2=n1622(14) I3=n1601(12) O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(11) O=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1601(13) I3=n1622(14) O=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n1601(15) I3=n1622(11) O=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(12) O=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1622(13) I3=n1601(15) O=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(14) I1=n1622(13) I2=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1630_ff_CQZ_D_LUT4_O_3_I3 O=n1630_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1630_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1630_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=n1601(11) I3=n1622(14) O=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I2=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I3=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1630_ff_CQZ_D_LUT4_O_4_I3 O=n1630_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_5_I1 I1=n1630_ff_CQZ_D_LUT4_O_5_I3 I2=n1630_ff_CQZ_D_LUT4_O_5_I2 I3=n1630_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1630_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1630_ff_CQZ_D_LUT4_O_5_I1 I2=n1630_ff_CQZ_D_LUT4_O_5_I2 I3=n1630_ff_CQZ_D_LUT4_O_5_I3 O=n1630_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_5_I1 I1=n1630_ff_CQZ_D_LUT4_O_5_I3 I2=n1630_ff_CQZ_D_LUT4_O_5_I2 I3=n1630_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I3 I2=n1630_ff_CQZ_D_LUT4_O_6_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I1 O=n1630_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1601(10) I3=n1622(14) O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1622(13) I2=n1601(10) I3=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(11) I1=n1622(12) I2=n1601(12) I3=n1622(11) O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(11) I1=n1601(12) I2=n1622(11) I3=n1622(12) O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(9) O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(11) I1=n1622(14) I2=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1622(13) I2=n1601(11) I3=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(12) I1=n1601(13) I2=n1622(11) I3=n1622(12) O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(10) O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1601(15) I2=n1622(10) I3=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(9) I3=n1601(14) O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1622(13) I3=n1601(12) O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n2062 I1=n1630_ff_CQZ_D_LUT4_O_6_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I3 O=n1630_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1622(14) I2=n1601(8) I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1622(13) I2=n1601(8) I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(9) I1=n1622(12) I2=n1601(10) I3=n1622(11) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(9) I1=n1601(10) I2=n1622(11) I3=n1622(12) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1622(10) I2=n1601(10) I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1622(8) I1=n1601(12) I2=n1601(11) I3=n1622(9) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1622(8) I1=n1601(11) I2=n1601(12) I3=n1622(9) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1622(13) I3=n1601(8) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1622(10) I3=n1601(11) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=n1622(14) I3=n1601(8) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(9) I1=n1622(14) I2=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I3=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1622(13) I3=n1601(9) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1622(10) I2=n1601(11) I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1622(8) I1=n1601(13) I2=n1601(12) I3=n1622(9) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1622(8) I1=n1601(12) I2=n1601(13) I3=n1622(9) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1622(10) I3=n1601(12) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1622(13) I3=n1601(10) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1622(8) I1=n1601(15) I2=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(10) I3=n1601(13) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1622(10) I2=n1601(12) I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1622(8) I1=n1601(14) I2=n1601(13) I3=n1622(9) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1622(8) I1=n1601(13) I2=n1601(14) I3=n1622(9) O=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=n1601(9) I3=n1622(14) O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1622(13) I2=n1601(9) I3=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(10) I1=n1622(12) I2=n1601(11) I3=n1622(11) O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(10) I1=n1601(11) I2=n1622(11) I3=n1622(12) O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(8) O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(10) I1=n1622(14) I2=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1601(14) I1=n1622(10) I2=n1601(15) I3=n1622(9) O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1622(13) I3=n1601(11) O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(12) I1=n1622(12) I2=n1601(13) I3=n1622(11) O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1622(8) I3=n1601(15) O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1630_ff_CQZ_D_LUT4_O_7_I3 O=n1630_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I0 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1601(8) I3=n1622(8) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(10) I3=n1601(8) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(9) I3=n1601(9) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1601(10) I3=n1622(8) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1601(8) I1=n1622(11) I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1622(10) I3=n1601(10) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1622(8) I1=n1601(10) I2=n1601(11) I3=n1622(9) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(10) I3=n1601(9) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1622(8) I1=n1601(11) I2=n1601(10) I3=n1622(9) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(9) I1=n1622(11) I2=n1601(8) I3=n1622(12) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n1601(8) I3=n1622(11) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1601(9) I1=n1601(8) I2=n1622(11) I3=n1622(12) O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_2_I1 I1=n1630_ff_CQZ_D_LUT4_O_2_I3 I2=n1630_ff_CQZ_D_LUT4_O_2_I2 I3=n1630_ff_CQZ_D_LUT4_O_1_I2 O=n1630_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1630_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n1630_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1622(13) I2=n1601(15) I3=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1601(14) I1=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1601(14) I1=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1622(13) I2=n1601(14) I3=n1630_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(13) O=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(14) I1=n1622(15) I2=n1601(15) I3=n1622(14) O=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(14) I1=n1622(14) I2=n1601(15) I3=n1622(15) O=n1630_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt ff CQZ=n1636(7) D=n1636_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5359.1-5364.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1636(6) D=n1636_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5359.1-5364.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1636(5) D=n1636_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5359.1-5364.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1636(4) D=n1636_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5359.1-5364.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1636(3) D=n1636_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5359.1-5364.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1636(2) D=n1636_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5359.1-5364.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1636(1) D=n1636_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5359.1-5364.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1636(0) D=n1636_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5359.1-5364.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n1636_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_1_I0 I1=n1636_ff_CQZ_D_LUT4_O_1_I1 I2=n2062 I3=n1636_ff_CQZ_D_LUT4_O_1_I3 O=n1636_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_3_I1 I1=n1636_ff_CQZ_D_LUT4_O_3_I3 I2=n1636_ff_CQZ_D_LUT4_O_3_I2 I3=n1636_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_2_I3 I1=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I3=n1636_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I2=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I3=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I0 I1=n1601(7) I2=n1622(7) I3=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(6) I3=n1601(6) O=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(7) I1=n1622(6) I2=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n2062 I1=n1636_ff_CQZ_D_LUT4_O_2_I1 I2=n1636_ff_CQZ_D_LUT4_O_2_I2 I3=n1636_ff_CQZ_D_LUT4_O_2_I3 O=n1636_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2 I2=n1636_ff_CQZ_D_LUT4_O_3_I3 I3=n1636_ff_CQZ_D_LUT4_O_3_I1 O=n1636_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_2_I3 I3=n1636_ff_CQZ_D_LUT4_O_2_I2 O=n1636_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I2=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=n1636_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1601(7) I1=n1622(6) I2=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=n1601(5) I3=n1622(7) O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(7) I3=n1601(6) O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(5) I3=n1601(7) O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I0 I2=n1622(7) I3=n1601(5) O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1622(5) I2=n1601(6) I3=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(4) I1=n1622(7) I2=n1601(5) I3=n1622(6) O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(4) I1=n1601(5) I2=n1622(7) I3=n1622(6) O=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n2062 I1=n1636_ff_CQZ_D_LUT4_O_3_I1 I2=n1636_ff_CQZ_D_LUT4_O_3_I2 I3=n1636_ff_CQZ_D_LUT4_O_3_I3 O=n1636_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I1=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I3=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n1622(2) I2=n1601(7) I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(5) I1=n1622(4) I2=n1601(6) I3=n1622(3) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(5) I1=n1601(6) I2=n1622(4) I3=n1622(3) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1601(6) I1=n1622(4) I2=n1601(7) I3=n1622(3) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1622(5) I3=n1601(5) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(3) I1=n1622(7) I2=n1601(4) I3=n1622(6) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1622(5) I2=n1601(4) I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(2) I1=n1601(3) I2=n1622(7) I3=n1622(6) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1601(6) I1=n1601(7) I2=n1622(4) I3=n1622(3) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1601(7) I1=n1622(4) I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1601(7) I3=n1622(4) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1622(5) I2=n1601(5) I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(3) I1=n1601(4) I2=n1622(7) I3=n1622(6) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1622(5) I3=n1601(6) O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I2=n1636_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=n1636_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1636_ff_CQZ_D_LUT4_O_4_I3 O=n1636_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_5_I1 I1=n1636_ff_CQZ_D_LUT4_O_5_I3 I2=n1636_ff_CQZ_D_LUT4_O_5_I2 I3=n1636_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1636_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1636_ff_CQZ_D_LUT4_O_5_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I3 O=n1636_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_5_I1 I1=n1636_ff_CQZ_D_LUT4_O_5_I3 I2=n1636_ff_CQZ_D_LUT4_O_5_I2 I3=n1636_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n1636_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n1601(7) I3=n1622(0) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(2) I3=n1601(4) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(2) I1=n1622(4) I2=n1601(3) I3=n1622(3) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(1) I1=n1622(5) I2=n1601(0) I3=n1622(6) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(2) I1=n1622(5) I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1601(1) I1=n1601(0) I2=n1622(6) I3=n1622(5) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1601(1) I1=n1622(6) I2=n1601(0) I3=n1622(7) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1622(2) I3=n1601(5) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(3) I1=n1622(4) I2=n1601(4) I3=n1622(3) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(7) I1=n1622(0) I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(1) I3=n1601(6) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(3) I3=n1601(3) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1622(2) I3=n1601(6) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(2) I1=n1622(6) I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(7) I3=n1601(1) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(5) I3=n1601(3) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n1622(5) I2=n1601(2) I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(1) I1=n1601(0) I2=n1622(7) I3=n1622(6) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n1622(5) I3=n1601(2) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I2=n1622(1) I3=n1601(7) O=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1622(2) I2=n1601(6) I3=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(4) I1=n1622(4) I2=n1601(5) I3=n1622(3) O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(4) I1=n1601(5) I2=n1622(4) I3=n1622(3) O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n1622(2) I3=n1601(7) O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1622(5) I3=n1601(4) O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(2) I1=n1622(7) I2=n1601(3) I3=n1622(6) O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n1601(2) I3=n1622(6) O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1622(1) I2=n1601(7) I3=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n1622(2) I2=n1601(5) I3=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1622(4) I2=n1601(4) I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1636_ff_CQZ_D_LUT4_O_6_I3 O=n1636_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(1) I3=n1601(5) O=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1636_ff_CQZ_D_LUT4_O_7_I3 O=n1636_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1601(1) I1=n1622(2) I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1622(0) I1=n1601(3) I2=n1601(2) I3=n1622(1) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(3) I3=n1601(0) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000001110101
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=n1622(2) I2=n1601(0) I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(1) I1=n1622(1) I2=n1622(0) I3=n1601(2) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(1) I1=n1622(0) I2=n1601(2) I3=n1622(1) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1622(2) I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n1601(1) I1=n1622(0) I2=n1601(0) I3=n1622(1) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1601(1) I1=n1622(2) I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1622(0) I1=n1601(5) I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n1601(0) I1=n1622(5) I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1601(5) I1=n1622(0) I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(1) I3=n1601(4) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(2) I3=n1601(2) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(3) I3=n1601(1) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(1) I1=n1622(3) I2=n1601(0) I3=n1622(4) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1601(0) I3=n1622(5) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(2) I3=n1601(3) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(1) I1=n1622(4) I2=n1601(2) I3=n1622(3) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(4) I3=n1601(1) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1601(6) I3=n1622(0) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1622(0) I1=n1601(4) I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1622(0) I3=n1601(4) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1601(1) I1=n1601(0) I2=n1622(3) I3=n1622(2) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1601(2) I2=n1622(0) I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(1) I3=n1601(3) O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1622(0) I1=n1601(5) I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n1636_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n1636_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I3=n1636_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 O=n1636_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=n1641(7) D=n1641_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5365.1-5370.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1641(6) D=n1641_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5365.1-5370.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1641(5) D=n1641_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5365.1-5370.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1641(4) D=n1641_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5365.1-5370.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1641(3) D=n1641_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5365.1-5370.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1641(2) D=n1641_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5365.1-5370.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1641(1) D=n1641_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5365.1-5370.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1641(0) D=n1641_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5365.1-5370.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1641_ff_CQZ_D_LUT4_O_I1 I2=n1636(7) I3=n1630(7) O=n1641_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1641_ff_CQZ_D_LUT4_O_1_I1 I2=n1636(6) I3=n1630(6) O=n1641_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1630(5) I2=n1636(5) I3=n1641_ff_CQZ_D_LUT4_O_2_I1 O=n1641_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1641_ff_CQZ_D_LUT4_O_2_I1 I2=n1636(5) I3=n1630(5) O=n1641_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1630(4) I2=n1636(4) I3=n1641_ff_CQZ_D_LUT4_O_3_I1 O=n1641_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1641_ff_CQZ_D_LUT4_O_3_I1 I2=n1636(4) I3=n1630(4) O=n1641_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1630(3) I2=n1636(3) I3=n1641_ff_CQZ_D_LUT4_O_4_I1 O=n1641_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1641_ff_CQZ_D_LUT4_O_4_I1 I2=n1636(3) I3=n1630(3) O=n1641_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1630(2) I2=n1636(2) I3=n1641_ff_CQZ_D_LUT4_O_5_I1 O=n1641_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1641_ff_CQZ_D_LUT4_O_5_I1 I2=n1636(2) I3=n1630(2) O=n1641_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1636(1) I1=n1630(1) I2=n1630(0) I3=n1636(0) O=n1641_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1641_ff_CQZ_D_LUT4_O_6_I3 O=n1641_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1630(0) I1=n1636(0) I2=n1636(1) I3=n1630(1) O=n1641_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n1630(0) I2=n1636(0) I3=n2062 O=n1641_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1630(6) I2=n1636(6) I3=n1641_ff_CQZ_D_LUT4_O_1_I1 O=n1641_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=n1647(7) D=n1647_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5371.1-5376.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1647(6) D=n1647_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5371.1-5376.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1647(5) D=n1647_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5371.1-5376.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1647(4) D=n1647_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5371.1-5376.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1647(3) D=n1647_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5371.1-5376.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1647(2) D=n1647_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5371.1-5376.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1647(1) D=n1647_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5371.1-5376.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1647(0) D=n1647_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5371.1-5376.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n1647_ff_CQZ_D_LUT4_O_I3 O=n1647_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_1_I1 I2=n1647_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n1647_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_2_I2 I2=n1647_ff_CQZ_D_LUT4_O_2_I3 I3=n1647_ff_CQZ_D_LUT4_O_2_I1 O=n1647_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1647_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n1647_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1647_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1647_ff_CQZ_D_LUT4_O_2_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I3 O=n1647_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1601(12) I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1601(12) I1=n1601(13) I2=n1622(5) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(7) I3=n1601(11) O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(14) I1=n1622(5) I2=n1601(15) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(13) I1=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2 I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1601(15) I3=n1622(3) O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1601(12) I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1601(15) I2=n1622(3) I3=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(2) I3=n1601(14) O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(13) I1=n1622(5) I2=n1601(14) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(13) I1=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2 I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1601(13) I1=n1601(14) I2=n1622(5) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(7) I3=n1601(12) O=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1622(5) I3=n1601(15) O=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1647_ff_CQZ_D_LUT4_O_3_I3 O=n1647_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1647_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1647_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1601(11) I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1647_ff_CQZ_D_LUT4_O_4_I3 O=n1647_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_5_I1 I1=n1647_ff_CQZ_D_LUT4_O_5_I3 I2=n1647_ff_CQZ_D_LUT4_O_5_I2 I3=n1647_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1647_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1647_ff_CQZ_D_LUT4_O_5_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I3 O=n1647_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_5_I1 I1=n1647_ff_CQZ_D_LUT4_O_5_I3 I2=n1647_ff_CQZ_D_LUT4_O_5_I2 I3=n1647_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n1647_ff_CQZ_D_LUT4_O_7_I2 I2=n1647_ff_CQZ_D_LUT4_O_7_I1 I3=n1647_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 I2=n1601(9) I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1601(10) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1601(14) I3=n1622(0) O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(5) I3=n1601(9) O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1601(8) I3=n1622(7) O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(10) I1=n1622(6) I2=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1601(11) I1=n1622(5) I2=n1601(12) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(15) I1=n1622(1) I2=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(3) I3=n1601(13) O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1622(1) I2=n1601(14) I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1622(2) I2=n1601(12) I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1601(10) I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1622(5) I2=n1601(10) I3=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1622(0) I1=n1601(15) I2=n1601(11) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1622(0) I1=n1601(11) I2=n1601(15) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(7) I3=n1601(9) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(11) I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1601(11) I1=n1601(12) I2=n1622(5) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(7) I3=n1601(10) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1601(12) I1=n1622(5) I2=n1601(13) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(14) I1=n1622(3) I2=n1601(15) I3=n1622(2) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n1647_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=n1601(15) I3=n1622(1) O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1647_ff_CQZ_D_LUT4_O_6_I3 O=n1647_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_7_I2 I1=n1647_ff_CQZ_D_LUT4_O_7_I1 I2=n1647_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2 I3=n2062 O=n1647_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1601(8) I2=n1622(6) I3=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1601(9) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1601(13) I3=n1622(0) O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1601(8) I3=n1622(5) O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(9) I1=n1622(6) I2=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0 I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1622(5) I3=n1601(10) O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1622(1) I3=n1601(14) O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(12) I1=n1622(3) I2=n1601(13) I3=n1622(2) O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=n1622(1) I2=n1601(13) I3=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(11) I1=n1601(12) I2=n1622(3) I3=n1622(2) O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 I2=n1601(8) I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1622(1) I3=n1601(13) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(11) I1=n1622(3) I2=n1601(12) I3=n1622(2) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I1=n1622(1) I2=n1601(12) I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(10) I1=n1601(11) I2=n1622(3) I3=n1622(2) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1601(10) I1=n1622(4) I2=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=n1647_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n1622(1) I2=n1601(11) I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(9) I1=n1601(10) I2=n1622(3) I3=n1622(2) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1601(9) I1=n1622(4) I2=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=n1647_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n1622(1) I3=n1601(12) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(10) I1=n1622(3) I2=n1601(11) I3=n1622(2) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1622(0) I1=n1601(12) I2=n1622(4) I3=n1601(8) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=n1622(1) I2=n1601(10) I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(9) I1=n1622(2) I2=n1622(3) I3=n1601(8) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(9) I1=n1622(3) I2=n1622(2) I3=n1601(8) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1622(1) I3=n1601(11) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(9) I1=n1622(3) I2=n1601(10) I3=n1622(2) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1622(0) I1=n1601(12) I2=n1622(4) I3=n1601(8) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001100110010
+.subckt LUT4 I0=n1019 I1=n1601(11) I2=n1622(0) I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1601(11) I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n1019 I1=n1622(0) I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1601(9) I1=n1622(1) I2=n1622(2) I3=n1601(8) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1019 I1=n1601(10) I2=n1601(8) I3=n1622(2) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1601(10) I1=n1622(1) I2=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1601(10) I3=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n1601(9) I1=n1622(2) I2=n1622(1) I3=n1601(8) O=n1647_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_2_I1 I1=n1647_ff_CQZ_D_LUT4_O_2_I3 I2=n1647_ff_CQZ_D_LUT4_O_2_I2 I3=n1647_ff_CQZ_D_LUT4_O_1_I2 O=n1647_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1647_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n1647_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1622(5) I2=n1601(15) I3=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1601(14) I1=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1601(14) I1=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1601(14) I1=n1601(15) I2=n1622(5) I3=n1622(4) O=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(7) I3=n1601(13) O=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(14) I1=n1622(7) I2=n1601(15) I3=n1622(6) O=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(14) I1=n1622(6) I2=n1622(7) I3=n1601(15) O=n1647_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt ff CQZ=n1653(7) D=n1653_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5377.1-5382.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1653(6) D=n1653_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5377.1-5382.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1653(5) D=n1653_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5377.1-5382.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1653(4) D=n1653_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5377.1-5382.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1653(3) D=n1653_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5377.1-5382.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1653(2) D=n1653_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5377.1-5382.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1653(1) D=n1653_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5377.1-5382.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1653(0) D=n1653_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5377.1-5382.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n1653_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1653_ff_CQZ_D_LUT4_O_1_I3 O=n1653_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I1=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I3=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1653_ff_CQZ_D_LUT4_O_2_I3 O=n1653_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_3_I1 I1=n1653_ff_CQZ_D_LUT4_O_3_I3 I2=n1653_ff_CQZ_D_LUT4_O_3_I2 I3=n1653_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1653_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1653_ff_CQZ_D_LUT4_O_3_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I3 O=n1653_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_3_I1 I1=n1653_ff_CQZ_D_LUT4_O_3_I3 I2=n1653_ff_CQZ_D_LUT4_O_3_I2 I3=n1653_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I1=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I3=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1601(3) I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1601(3) I1=n1601(4) I2=n1622(12) I3=n1622(13) O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(2) O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(4) I1=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1601(7) I2=n1622(11) I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(10) I3=n1601(6) O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(5) I1=n1622(13) I2=n1601(6) I3=n1622(12) O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1601(6) I1=n1622(11) I2=n1601(7) I3=n1622(10) O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1601(3) I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1601(4) I1=n1622(13) I2=n1601(5) I3=n1622(12) O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1601(4) I1=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1601(4) I1=n1601(5) I2=n1622(12) I3=n1622(13) O=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(3) O=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1601(6) I1=n1622(13) I2=n1601(7) I3=n1622(12) O=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(5) I1=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n1601(7) I3=n1622(11) O=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1653_ff_CQZ_D_LUT4_O_4_I3 O=n1653_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1653_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 I3=n1653_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 O=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1622(15) I1=n1601(1) I2=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(14) I3=n1601(2) O=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1653_ff_CQZ_D_LUT4_O_5_I3 O=n1653_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_6_I1 I1=n1653_ff_CQZ_D_LUT4_O_6_I3 I2=n1653_ff_CQZ_D_LUT4_O_6_I2 I3=n1653_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1653_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1653_ff_CQZ_D_LUT4_O_6_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3 O=n1653_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_6_I1 I1=n1653_ff_CQZ_D_LUT4_O_6_I3 I2=n1653_ff_CQZ_D_LUT4_O_6_I2 I3=n1653_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1622(14) I2=n1601(0) I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1622(13) I2=n1601(0) I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(1) I1=n1622(12) I2=n1601(5) I3=n1622(8) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(1) I1=n1601(5) I2=n1622(8) I3=n1622(12) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 I2=n1622(15) I3=n1601(0) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1622(13) I3=n1601(2) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(3) I1=n1622(12) I2=n1601(7) I3=n1622(8) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1622(9) I3=n1601(6) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(4) I1=n1622(11) I2=n1601(5) I3=n1622(10) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=n1622(9) I2=n1601(5) I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(3) I1=n1601(4) I2=n1622(10) I3=n1622(11) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1622(9) I3=n1601(5) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(3) I1=n1622(11) I2=n1601(4) I3=n1622(10) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n1622(9) I2=n1601(4) I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(2) I1=n1601(3) I2=n1622(10) I3=n1622(11) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1622(13) I3=n1601(1) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=n1622(14) I3=n1601(0) O=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1622(15) I1=n1601(0) I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(14) I3=n1601(1) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1601(2) I1=n1622(12) I2=n1601(6) I3=n1622(8) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1601(1) I2=n1622(14) I3=n1622(13) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n1601(1) I1=n1622(14) I2=n1601(2) I3=n1622(12) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1622(15) I3=n1601(1) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n1601(2) I2=n1622(14) I3=n1622(13) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n1601(2) I1=n1622(14) I2=n1601(3) I3=n1622(12) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1601(3) I1=n1622(13) I2=n1601(4) I3=n1622(12) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(11) I3=n1601(5) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(9) I3=n1601(7) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1622(9) I2=n1601(6) I3=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(4) I1=n1601(5) I2=n1622(10) I3=n1622(11) O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1653_ff_CQZ_D_LUT4_O_7_I3 O=n1653_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010011111100
+.subckt LUT4 I0=n1601(1) I1=n1601(0) I2=n1622(10) I3=n1622(11) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=n1601(2) I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=n1019 I1=n1601(2) I2=n1601(0) I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1622(9) I1=n1601(1) I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1622(8) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=n1019 I1=n1622(10) I2=n1601(0) I3=n1601(2) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1601(2) I1=n1622(9) I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1601(1) I1=n1601(0) I2=n1622(9) I3=n1622(10) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(8) I3=n1601(3) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1622(9) I3=n1601(4) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(2) I1=n1622(11) I2=n1601(3) I3=n1622(10) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1622(9) I1=n1601(3) I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(10) I3=n1601(2) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(1) I1=n1622(11) I2=n1601(2) I3=n1622(10) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1622(13) I3=n1601(0) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1601(4) I1=n1622(8) I2=n1601(0) I3=n1622(12) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1622(9) I2=n1601(2) I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1601(1) I1=n1622(10) I2=n1601(0) I3=n1622(11) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n1622(9) I3=n1601(3) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1601(4) I1=n1622(8) I2=n1601(0) I3=n1622(12) O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I3=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1622(13) I2=n1601(7) I3=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1601(6) I1=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1601(6) I1=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1601(6) I1=n1601(7) I2=n1622(12) I3=n1622(13) O=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(5) O=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1601(6) I1=n1622(15) I2=n1601(7) I3=n1622(14) O=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1601(6) I1=n1622(14) I2=n1601(7) I3=n1622(15) O=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1601(5) I1=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1622(14) O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1601(5) I1=n1601(6) I2=n1622(12) I3=n1622(13) O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1622(15) I3=n1601(4) O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=n1622(13) I3=n1601(7) O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=n1653_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 O=n1653_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=n1658(7) D=n1658_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5383.1-5388.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1658(6) D=n1658_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5383.1-5388.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1658(5) D=n1658_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5383.1-5388.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1658(4) D=n1658_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5383.1-5388.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1658(3) D=n1658_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5383.1-5388.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1658(2) D=n1658_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5383.1-5388.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1658(1) D=n1658_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5383.1-5388.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1658(0) D=n1658_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5383.1-5388.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1658_ff_CQZ_D_LUT4_O_I1 I2=n1647(7) I3=n1653(7) O=n1658_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1658_ff_CQZ_D_LUT4_O_1_I1 I2=n1647(6) I3=n1653(6) O=n1658_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1653(5) I2=n1647(5) I3=n1658_ff_CQZ_D_LUT4_O_2_I1 O=n1658_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1658_ff_CQZ_D_LUT4_O_2_I1 I2=n1647(5) I3=n1653(5) O=n1658_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1653(4) I2=n1647(4) I3=n1658_ff_CQZ_D_LUT4_O_3_I1 O=n1658_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1658_ff_CQZ_D_LUT4_O_3_I1 I2=n1647(4) I3=n1653(4) O=n1658_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1653(3) I2=n1647(3) I3=n1658_ff_CQZ_D_LUT4_O_4_I1 O=n1658_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1658_ff_CQZ_D_LUT4_O_4_I1 I2=n1647(3) I3=n1653(3) O=n1658_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1653(2) I2=n1647(2) I3=n1658_ff_CQZ_D_LUT4_O_5_I1 O=n1658_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1658_ff_CQZ_D_LUT4_O_5_I1 I2=n1647(2) I3=n1653(2) O=n1658_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1647(1) I1=n1653(1) I2=n1647(0) I3=n1653(0) O=n1658_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1658_ff_CQZ_D_LUT4_O_6_I3 O=n1658_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1647(0) I1=n1653(0) I2=n1647(1) I3=n1653(1) O=n1658_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1653(0) I2=n1647(0) I3=n2062 O=n1658_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1653(6) I2=n1647(6) I3=n1658_ff_CQZ_D_LUT4_O_1_I1 O=n1658_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n165(7) D=n165_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3607.1-3612.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n165(6) D=n165_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3607.1-3612.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n165(5) D=n165_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3607.1-3612.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n165(4) D=n165_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3607.1-3612.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n165(3) D=n165_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3607.1-3612.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n165(2) D=n165_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3607.1-3612.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n165(1) D=n165_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3607.1-3612.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n165(0) D=n165_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3607.1-3612.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(15) D=n1665_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(14) D=n1665_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(5) D=n1665_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(4) D=n1665_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(3) D=n1665_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(2) D=n1665_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(1) D=n1665_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(0) D=n1665_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(13) D=n1665_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(12) D=n1665_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(11) D=n1665_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(10) D=n1665_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(9) D=n1665_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(8) D=n1665_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(7) D=n1665_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1665(6) D=n1665_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5389.1-5394.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_I1 I2=n1641(7) I3=n1611(7) O=n1665_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_1_I1 I2=n1641(6) I3=n1611(6) O=n1665_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_10_I1 I2=n1658(4) I3=n1619(4) O=n1665_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1619(3) I2=n1658(3) I3=n1665_ff_CQZ_D_LUT4_O_11_I1 O=n1665_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_11_I1 I2=n1658(3) I3=n1619(3) O=n1665_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1619(2) I2=n1658(2) I3=n1665_ff_CQZ_D_LUT4_O_12_I1 O=n1665_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_12_I1 I2=n1658(2) I3=n1619(2) O=n1665_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1658(1) I1=n1619(1) I2=n1619(0) I3=n1658(0) O=n1665_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1665_ff_CQZ_D_LUT4_O_13_I3 O=n1665_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1658(0) I1=n1619(0) I2=n1658(1) I3=n1619(1) O=n1665_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1611(0) I2=n1641(0) I3=n2062 O=n1665_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1619(0) I2=n1658(0) I3=n2062 O=n1665_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1611(5) I2=n1641(5) I3=n1665_ff_CQZ_D_LUT4_O_2_I1 O=n1665_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_2_I1 I2=n1641(5) I3=n1611(5) O=n1665_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1611(4) I2=n1641(4) I3=n1665_ff_CQZ_D_LUT4_O_3_I1 O=n1665_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_3_I1 I2=n1641(4) I3=n1611(4) O=n1665_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1611(3) I2=n1641(3) I3=n1665_ff_CQZ_D_LUT4_O_4_I1 O=n1665_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_4_I1 I2=n1641(3) I3=n1611(3) O=n1665_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1611(2) I2=n1641(2) I3=n1665_ff_CQZ_D_LUT4_O_5_I1 O=n1665_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_5_I1 I2=n1641(2) I3=n1611(2) O=n1665_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1641(1) I1=n1611(1) I2=n1611(0) I3=n1641(0) O=n1665_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1665_ff_CQZ_D_LUT4_O_6_I3 O=n1665_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1641(0) I1=n1611(0) I2=n1641(1) I3=n1611(1) O=n1665_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_7_I1 I2=n1658(7) I3=n1619(7) O=n1665_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1619(6) I2=n1658(6) I3=n1665_ff_CQZ_D_LUT4_O_8_I1 O=n1665_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_8_I1 I2=n1658(6) I3=n1619(6) O=n1665_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1619(5) I2=n1658(5) I3=n1665_ff_CQZ_D_LUT4_O_9_I1 O=n1665_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1665_ff_CQZ_D_LUT4_O_9_I1 I2=n1658(5) I3=n1619(5) O=n1665_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1619(4) I2=n1658(4) I3=n1665_ff_CQZ_D_LUT4_O_10_I1 O=n1665_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n1611(6) I2=n1641(6) I3=n1665_ff_CQZ_D_LUT4_O_1_I1 O=n1665_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n1672(15) D=n1672_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(14) D=n1672_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(5) D=n1672_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(4) D=n1672_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(3) D=n1672_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(2) D=n1672_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(1) D=n1672_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(0) D=n1665_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(13) D=n1672_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(12) D=n1672_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(11) D=n1672_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(10) D=n1672_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(9) D=n1672_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(8) D=n1665_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(7) D=n1672_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1672(6) D=n1672_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5395.1-5400.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_I1 I2=n1641(7) I3=n1611(7) O=n1672_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_1_I1 I2=n1641(6) I3=n1611(6) O=n1672_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_10_I1 I2=n1658(4) I3=n1619(4) O=n1672_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1619(3) I2=n1658(3) I3=n1672_ff_CQZ_D_LUT4_O_11_I1 O=n1672_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_11_I1 I2=n1658(3) I3=n1619(3) O=n1672_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1619(2) I2=n1658(2) I3=n1672_ff_CQZ_D_LUT4_O_12_I1 O=n1672_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_12_I1 I2=n1658(2) I3=n1619(2) O=n1672_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1658(1) I1=n1619(1) I2=n1619(0) I3=n1658(0) O=n1672_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1672_ff_CQZ_D_LUT4_O_13_I3 O=n1672_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1619(0) I1=n1658(0) I2=n1658(1) I3=n1619(1) O=n1672_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n1611(5) I2=n1641(5) I3=n1672_ff_CQZ_D_LUT4_O_2_I1 O=n1672_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_2_I1 I2=n1641(5) I3=n1611(5) O=n1672_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1611(4) I2=n1641(4) I3=n1672_ff_CQZ_D_LUT4_O_3_I1 O=n1672_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_3_I1 I2=n1641(4) I3=n1611(4) O=n1672_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1611(3) I2=n1641(3) I3=n1672_ff_CQZ_D_LUT4_O_4_I1 O=n1672_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_4_I1 I2=n1641(3) I3=n1611(3) O=n1672_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1611(2) I2=n1641(2) I3=n1672_ff_CQZ_D_LUT4_O_5_I1 O=n1672_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_5_I1 I2=n1641(2) I3=n1611(2) O=n1672_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1641(1) I1=n1611(1) I2=n1611(0) I3=n1641(0) O=n1672_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1672_ff_CQZ_D_LUT4_O_6_I3 O=n1672_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1611(0) I1=n1641(0) I2=n1641(1) I3=n1611(1) O=n1672_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_7_I1 I2=n1658(7) I3=n1619(7) O=n1672_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1619(6) I2=n1658(6) I3=n1672_ff_CQZ_D_LUT4_O_8_I1 O=n1672_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_8_I1 I2=n1658(6) I3=n1619(6) O=n1672_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1619(5) I2=n1658(5) I3=n1672_ff_CQZ_D_LUT4_O_9_I1 O=n1672_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1672_ff_CQZ_D_LUT4_O_9_I1 I2=n1658(5) I3=n1619(5) O=n1672_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1619(4) I2=n1658(4) I3=n1672_ff_CQZ_D_LUT4_O_10_I1 O=n1672_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1611(6) I2=n1641(6) I3=n1672_ff_CQZ_D_LUT4_O_1_I1 O=n1672_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1677 I3=n2062 O=n1681_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1677 D=n1677_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5401.1-5406.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1681 I3=n2062 O=n1685_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1681 D=n1681_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5407.1-5412.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1685 I3=n2062 O=n1689_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1685 D=n1685_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5413.1-5418.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1689 O=n1689_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1689_LUT4_I3_O I2=n1729(4) I3=n1689_LUT4_I3_O_LUT4_I1_I3 O=n1689_LUT4_I3_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1689_LUT4_I3_O I2=n1729(1) I3=n1729(0) O=n1689_LUT4_I3_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1729(0) I1=n1729(1) I2=n1729(2) I3=n1729(3) O=n1689_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1689_LUT4_I3_O I3=n1689_LUT4_I3_O_LUT4_I2_I3 O=n1689_LUT4_I3_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1689_LUT4_I3_O I3=n1729(0) O=n1689_LUT4_I3_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1729(0) I1=n1729(1) I2=n1729(2) I3=n1729(3) O=n1689_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n1689_LUT4_I3_O_LUT4_I1_I3 I1=n1729(4) I2=n1729(5) I3=n1689_LUT4_I3_O O=n1689_LUT4_I3_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1729(0) I1=n1729(1) I2=n1729(2) I3=n1689_LUT4_I3_O O=n1689_LUT4_I3_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n1689 D=n1689_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5419.1-5424.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n169(7) I3=n2062 O=n173_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n169(6) I3=n2062 O=n173_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n169(5) I3=n2062 O=n173_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n169(4) I3=n2062 O=n173_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n169(3) I3=n2062 O=n173_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n169(2) I3=n2062 O=n173_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n169(1) I3=n2062 O=n173_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n169(0) I3=n2062 O=n173_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n169(7) D=n169_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3613.1-3618.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n169(6) D=n169_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3613.1-3618.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n169(5) D=n169_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3613.1-3618.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n169(4) D=n169_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3613.1-3618.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n169(3) D=n169_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3613.1-3618.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n169(2) D=n169_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3613.1-3618.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n169(1) D=n169_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3613.1-3618.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n169(0) D=n169_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3613.1-3618.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(7) I3=n2062 O=n169_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(6) I3=n2062 O=n169_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(5) I3=n2062 O=n169_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(4) I3=n2062 O=n169_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(3) I3=n2062 O=n169_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(2) I3=n2062 O=n169_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(1) I3=n2062 O=n169_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n148(0) I3=n2062 O=n169_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1707_LUT4_I1_I0 I1=n1576(0) I2=n1576(3) I3=n1500_LUT4_I3_O O=n1707_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1576(1) I1=n1576(0) I2=n1576(2) I3=n1500_LUT4_I3_O O=n1707_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1019 I1=n1576(0) I2=n1576(1) I3=n1707_LUT4_I1_2_I3 O=n1589_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(2) I3=n1576(3) O=n1707_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(2) I3=n1576(1) O=n1707_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1500_LUT4_I3_O I2=n1576(0) I3=n1576(1) O=n1707_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1500_LUT4_I3_O I3=n1576(0) O=n1707_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1576(0) D=n1707_LUT4_I3_O(0) QCK=$iopadmap$clock_c QEN=n2073 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5231.1-5236.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1711 I3=n2062 O=n1715_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1711 D=n1711_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5449.1-5454.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1576(0) I3=n2062 O=n1711_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1715 I3=n2062 O=n1719_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1715 D=n1715_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5455.1-5460.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1719 I3=n2062 O=n1723_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1719 D=n1719_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5461.1-5466.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1723 I2=n2059 I3=n1768(0) O=n1723_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1723 I2=n2059 I3=n1768(0) O=n1723_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n1723 I3=n1731(0) O=n1723_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=n1723 D=n1723_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5467.1-5472.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1729(5) D=n1689_LUT4_I3_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5473.1-5478.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1729(4) D=n1689_LUT4_I3_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5473.1-5478.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1729(3) D=n1689_LUT4_I3_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5473.1-5478.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1729(2) D=n1689_LUT4_I3_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5473.1-5478.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1729(1) D=n1689_LUT4_I3_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5473.1-5478.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1729(0) D=n1689_LUT4_I3_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5473.1-5478.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1731(0) I2=n2059 I3=n1723 O=n1736_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n1731(0) D=n1736_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5479.1-5484.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1689 I2=n1731(0) I3=n2062 O=n1736_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=n173(7) D=n173_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3619.1-3624.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n173(6) D=n173_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3619.1-3624.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n173(5) D=n173_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3619.1-3624.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n173(4) D=n173_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3619.1-3624.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n173(3) D=n173_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3619.1-3624.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n173(2) D=n173_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3619.1-3624.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n173(1) D=n173_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3619.1-3624.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n173(0) D=n173_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3619.1-3624.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1741 I3=n2067_LUT4_O_I3 O=n1830_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1741 O=n1741_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O I2=n1817(4) I3=n1830_LUT4_I3_I2 O=n1741_LUT4_I3_O_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O I2=n1817(3) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3 O=n1741_LUT4_I3_O_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 I2=n1817(3) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(0) I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 I3=n1817(4) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0 I1=n1741_LUT4_I3_O_LUT4_I3_1_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(2) I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_I3_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I2 I2=n1830_LUT4_I3_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_2_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_O_I0 I1=n1817(2) I2=n1817(3) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(1) I3=n1817(0) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O I1=n1741_LUT4_I3_O_LUT4_I1_2_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=n1817(3) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1817(1) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_I3_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(3) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1817(5) I2=n1817(6) I3=n1817(4) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(4) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1817(1) I2=n1817(3) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1817(6) I2=n1817(4) I3=n1817(5) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1817(1) I1=n1817(3) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1817(5) I2=n1817(4) I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n1817(0) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=n1817(3) I1=n1817(0) I2=n1817(1) I3=n1830_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0 I1=n1817(0) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(3) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_2_I3 I2=n1817(3) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I3_1_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(3) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1817(6) I2=n1817(5) I3=n1817(4) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1817(0) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 I2=n1817(1) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 I1=n1817(2) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0 I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010100111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111111111
+.subckt LUT4 I0=n1019 I1=n1817(4) I2=n1817(5) I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1817(2) I1=n1817(3) I2=n1817(0) I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110110100
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1817(0) I1=n1817(2) I2=n1817(1) I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0_LUT4_O_I1_LUT4_O_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I0_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_I3 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I3_1_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(3) I3=n1830_LUT4_I3_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2 I1=n1817(3) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I3=n1830_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I2 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000001
+.subckt LUT4 I0=n1817(4) I1=n1817(3) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=n1817(3) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111111
+.subckt LUT4 I0=n1019 I1=n1817(3) I2=n1817(2) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 I2=n1830_LUT4_I3_I2_LUT4_O_I3 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I1=n1830_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=n1830_LUT4_I3_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 I2=n1817(3) I3=n1830_LUT4_I3_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I1_LUT4_O_I2 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 I2=n1830_LUT4_I3_I2_LUT4_O_I3 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I3 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=n1817(2) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=n1830_LUT4_I3_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111111111
+.subckt LUT4 I0=n1817(2) I1=n1817(0) I2=n1817(1) I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101111110100
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=n1817(1) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I1_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I2=n1830_LUT4_I3_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000011111111
+.subckt LUT4 I0=n1830_LUT4_I3_I2 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1817(1) I1=n1817(3) I2=n1817(2) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110000000000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I1_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(3) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_I3_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011111111
+.subckt LUT4 I0=n1817(0) I1=n1817(3) I2=n1817(1) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110011001101
+.subckt LUT4 I0=n1817(3) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000011111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_I3_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I2 I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I2 I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110011110101
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(3) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1 I2=n1817(0) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1019 I1=n1817(3) I2=n1817(0) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1817(1) I1=n1817(2) I2=n1817(0) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I3_1_I2 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=n1817(3) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 I2=n1817(2) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101111111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I1_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I1_LUT4_O_I1 I2=n1817(5) I3=n1817(4) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=n1817(3) I1=n1817(2) I2=n1741_LUT4_I3_O_LUT4_I3_1_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110100000000
+.subckt LUT4 I0=n1817(0) I1=n1817(1) I2=n1817(3) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101111010100
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_7_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n1817(3) I1=n1817(2) I2=n1817(1) I3=n1830_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100000000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_7_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=n1817(1) I1=n1817(3) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I0_LUT4_O_I2 I3=n1830_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010001000
+.subckt LUT4 I0=n1817(2) I1=n1817(1) I2=n1817(3) I3=n1817(0) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110011110110000
+.subckt LUT4 I0=n1817(5) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2 I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110110000
+.subckt LUT4 I0=n1817(3) I1=n1741_LUT4_I3_O_LUT4_I3_1_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2 I2=n1817(1) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=n1019 I1=n1817(0) I2=n1817(1) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=n1019 I1=n1817(0) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111010
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3 I2=n1817(4) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I3_1_I2 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1817(1) I1=n1817(2) I2=n1817(0) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110001100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=n1019 I1=n1817(1) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I0 I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1817(2) I1=n1817(1) I2=n1817(3) I3=n1817(0) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=n1817(2) I1=n1817(1) I2=n1817(0) I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(5) I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1830_LUT4_I3_I2_LUT4_O_I3 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I1_LUT4_O_I2 I3=n1817(4) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000111110000
+.subckt LUT4 I0=n1019 I1=n1817(3) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I3_1_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1817(2) I1=n1817(0) I2=n1817(3) I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=n1817(1) I1=n1817(0) I2=n1817(2) I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001000000000
+.subckt LUT4 I0=n1817(3) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 I2=n1817(2) I3=n1830_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_7_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1817(3) I2=n1817(0) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I0_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 I2=n1817(3) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1019 I1=n1817(1) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I3=n1817(0) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I1_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I3_1_I2 I1=n1817(2) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_2_I3 I1=n1817(2) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001111111111111
+.subckt LUT4 I0=n1817(0) I1=n1817(3) I2=n1817(2) I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110000100011
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_7_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I1_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0_LUT4_O_I1_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=n1817(0) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I1 I1=n1817(3) I2=n1817(0) I3=n1830_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=n1817(3) I1=n1741_LUT4_I3_O_LUT4_I3_1_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I1_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I3=n1817(0) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100000111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=n1817(4) I1=n1817(3) I2=n1817(1) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n1817(3) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I2=n1817(0) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I3_1_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1817(0) I1=n1817(2) I2=n1817(1) I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100010000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I1=n1817(1) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_3_I3_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000011111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001011111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=n1817(3) I1=n1817(0) I2=n1817(1) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I3_1_I2 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I2=n1817(4) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111111010
+.subckt LUT4 I0=n1019 I1=n1817(3) I2=n1817(1) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=n1817(1) I1=n1817(3) I2=n1817(0) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001110000101111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I3_1_I2 I1=n1817(2) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_I3_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I3_1_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110011111010
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=n1817(2) I1=n1817(3) I2=n1817(0) I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111100110001
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I3=n1741_LUT4_I3_O_LUT4_I1_2_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1817(3) I1=n1817(1) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I3_LUT4_O_I1 I3=n1830_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_7_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_7_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I3=n1830_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1817(3) I1=n1817(2) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2 I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_7_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(2) I3=n1741_LUT4_I3_O_LUT4_I1_2_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(3) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I1 I2=n1817(6) I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 I1=n1817(1) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I2 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_11_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_2_I3 I1=n1817(2) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_8_I2_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110110000
+.subckt LUT4 I0=n1817(2) I1=n1817(1) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_I0 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1830_LUT4_I3_I2 I1=n1817(4) I2=n1817(6) I3=n1817(5) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=n1817(4) I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_I3_I0 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_4_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011111111
+.subckt LUT4 I0=n1019 I1=n1817(3) I2=n1817(2) I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_O_I0 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_14_I1 I1=n1817(5) I2=n1817(4) I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_O_I3 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 I1=n1741_LUT4_I3_O_LUT4_I1_2_I3 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111110010
+.subckt LUT4 I0=n1830_LUT4_I3_I2_LUT4_O_I3 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_1_I1_LUT4_O_I2 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1817(3) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=n1019 I1=n1817(1) I2=n1817(0) I3=n1817(2) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I2_LUT4_I3_I0 I1=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=n1019 I1=n1817(1) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_I0_LUT4_I3_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1817(2) I1=n1817(3) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=n1830_LUT4_I3_I1 I1=n1817(0) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I3=n1817(1) O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111100010101
+.subckt LUT4 I0=n1817(0) I1=n1817(1) I2=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 O=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(2) I3=n1741_LUT4_I3_O_LUT4_I1_2_I3 O=n1741_LUT4_I3_O_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1741_LUT4_I3_O I2=n1817(2) I3=n1741_LUT4_I3_O_LUT4_I1_2_I3 O=n1741_LUT4_I3_O_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(1) I3=n1817(0) O=n1741_LUT4_I3_O_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O I3=n1741_LUT4_I3_O_LUT4_I2_I3 O=n1741_LUT4_I3_O_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O I3=n1817(0) O=n1741_LUT4_I3_O_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1830_LUT4_I3_I2 I1=n1817(4) I2=n1817(5) I3=n1817(6) O=n1741_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n1830_LUT4_I3_I2 I1=n1817(4) I2=n1817(5) I3=n1741_LUT4_I3_O O=n1741_LUT4_I3_O_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O_LUT4_I3_1_I2 I3=n1741_LUT4_I3_O O=n1741_LUT4_I3_O_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(1) I3=n1817(0) O=n1741_LUT4_I3_O_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=n1741 D=n1741_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5485.1-5490.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1689 I3=n2062 O=n1741_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1752(31) D=n1665(15) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(30) D=n1665(14) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(21) D=n1665(5) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(20) D=n1665(4) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(19) D=n1665(3) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(18) D=n1665(2) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(17) D=n1665(1) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(16) D=n1665(0) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(15) D=n1672(15) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(14) D=n1672(14) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(13) D=n1672(13) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(12) D=n1672(12) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(29) D=n1665(13) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(11) D=n1672(11) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(10) D=n1672(10) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(9) D=n1672(9) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(8) D=n1672(8) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(7) D=n1672(7) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(6) D=n1672(6) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n1752(5) D=n1672(5) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1752(4) D=n1672(4) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1752(3) D=n1672(3) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1752(2) D=n1672(2) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1752(28) D=n1665(12) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1752(1) D=n1672(1) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1752(0) D=n1672(0) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1752(27) D=n1665(11) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n1752(26) D=n1665(10) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(25) D=n1665(9) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(24) D=n1665(8) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(23) D=n1665(7) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1752(22) D=n1665(6) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5491.1-5495.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(31) D=n1665(15) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(30) D=n1665(14) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(21) D=n1665(5) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(20) D=n1665(4) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(19) D=n1665(3) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(18) D=n1665(2) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(17) D=n1665(1) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(16) D=n1665(0) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(15) D=n1672(15) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(14) D=n1672(14) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(13) D=n1672(13) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(12) D=n1672(12) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(29) D=n1665(13) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(11) D=n1672(11) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(10) D=n1672(10) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(9) D=n1672(9) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(8) D=n1672(8) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(7) D=n1672(7) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(6) D=n1672(6) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(5) D=n1672(5) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(4) D=n1672(4) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(3) D=n1672(3) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(2) D=n1672(2) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(28) D=n1665(12) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(1) D=n1672(1) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(0) D=n1672(0) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(27) D=n1665(11) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(26) D=n1665(10) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(25) D=n1665(9) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(24) D=n1665(8) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(23) D=n1665(7) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1756(22) D=n1665(6) QCK=$iopadmap$clock_c QEN=n1736_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5501.1-5505.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1756(15) I1=n1752(15) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(14) I1=n1752(14) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(5) I1=n1752(5) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(4) I1=n1752(4) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(3) I1=n1752(3) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(2) I1=n1752(2) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(1) I1=n1752(1) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1752(0) I1=n1756(0) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1756(13) I1=n1752(13) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(12) I1=n1752(12) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(11) I1=n1752(11) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(10) I1=n1752(10) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(9) I1=n1752(9) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(8) I1=n1752(8) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(7) I1=n1752(7) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(6) I1=n1752(6) I2=n1760 I3=n1801(0) O=n1760_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1756(31) I1=n1752(31) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(30) I1=n1752(30) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(21) I1=n1752(21) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(20) I1=n1752(20) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(19) I1=n1752(19) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(18) I1=n1752(18) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(17) I1=n1752(17) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(16) I1=n1752(16) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(29) I1=n1752(29) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(28) I1=n1752(28) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(27) I1=n1752(27) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(26) I1=n1752(26) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(25) I1=n1752(25) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(24) I1=n1752(24) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(23) I1=n1752(23) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1756(22) I1=n1752(22) I2=n1801(0) I3=n1760 O=n1760_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n1760 D=n1760_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5511.1-5516.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1731(0) O=n1760_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n1768(0) D=n1773_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5523.1-5528.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1768(0) I2=n1689 I3=n2062 O=n1773_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=n1789(31) D=n1665(15) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(30) D=n1665(14) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(21) D=n1665(5) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(20) D=n1665(4) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(19) D=n1665(3) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(18) D=n1665(2) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(17) D=n1665(1) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(16) D=n1665(0) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(15) D=n1672(15) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(14) D=n1672(14) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1789(13) D=n1672(13) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5529.1-5533.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
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+.subckt ff CQZ=n1793(0) D=n1672(0) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5539.1-5543.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1793(27) D=n1665(11) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5539.1-5543.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1793(26) D=n1665(10) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5539.1-5543.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1793(25) D=n1665(9) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5539.1-5543.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1793(24) D=n1665(8) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5539.1-5543.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1793(23) D=n1665(7) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5539.1-5543.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1793(22) D=n1665(6) QCK=$iopadmap$clock_c QEN=n1723_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5539.1-5543.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1793(15) I1=n1789(15) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(14) I1=n1789(14) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(5) I1=n1789(5) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(4) I1=n1789(4) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(3) I1=n1789(3) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(2) I1=n1789(2) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(1) I1=n1789(1) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1789(0) I1=n1793(0) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n1793(13) I1=n1789(13) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(12) I1=n1789(12) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(11) I1=n1789(11) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(10) I1=n1789(10) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(9) I1=n1789(9) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(8) I1=n1789(8) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(7) I1=n1789(7) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(6) I1=n1789(6) I2=n1797 I3=n1801(0) O=n1797_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n1793(31) I1=n1789(31) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(30) I1=n1789(30) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(21) I1=n1789(21) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(20) I1=n1789(20) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(19) I1=n1789(19) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(18) I1=n1789(18) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(17) I1=n1789(17) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(16) I1=n1789(16) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(29) I1=n1789(29) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(28) I1=n1789(28) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(27) I1=n1789(27) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(26) I1=n1789(26) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(25) I1=n1789(25) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(24) I1=n1789(24) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(23) I1=n1789(23) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n1793(22) I1=n1789(22) I2=n1801(0) I3=n1797 O=n1797_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n1797 D=n1797_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5549.1-5554.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1768(0) O=n1797_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n1801(0) D=n1806_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5555.1-5560.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1741_LUT4_I3_O I3=n1806_ff_CQZ_D_LUT4_O_I3 O=n1806_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1729(1) I1=n1729(0) I2=n1806_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1801(0) O=n1806_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n1729(2) I1=n1729(3) I2=n1729(4) I3=n1729(5) O=n1806_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=n1817(6) D=n1741_LUT4_I3_O_LUT4_I1_O(6) QCK=$iopadmap$clock_c QEN=n2067 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5561.1-5566.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1817(5) D=n1741_LUT4_I3_O_LUT4_I1_O(5) QCK=$iopadmap$clock_c QEN=n2067 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5561.1-5566.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1817(4) D=n1741_LUT4_I3_O_LUT4_I1_O(4) QCK=$iopadmap$clock_c QEN=n2067 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5561.1-5566.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1817(3) D=n1741_LUT4_I3_O_LUT4_I1_O(3) QCK=$iopadmap$clock_c QEN=n2067 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5561.1-5566.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1817(2) D=n1741_LUT4_I3_O_LUT4_I1_O(2) QCK=$iopadmap$clock_c QEN=n2067 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5561.1-5566.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1817(1) D=n1741_LUT4_I3_O_LUT4_I1_O(1) QCK=$iopadmap$clock_c QEN=n2067 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5561.1-5566.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1821(0) I2=n1830_LUT4_I3_I1 I3=n1830_LUT4_I3_I2 O=n2067_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt ff CQZ=n1821(0) D=n1830_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5567.1-5572.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1830_LUT4_I3_I1 I2=n1830_LUT4_I3_I2 I3=n1830 O=n1918_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=n1019 I1=n1817(5) I2=n1817(4) I3=n1817(6) O=n1830_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1817(3) I2=n1817(0) I3=n1830_LUT4_I3_I2_LUT4_O_I3 O=n1830_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(1) I3=n1817(2) O=n1830_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=n1830 D=n1830_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5573.1-5578.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(15) D=n1836_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(14) D=n1836_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(5) D=n1836_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(4) D=n1836_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(3) D=n1836_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(2) D=n1836_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(1) D=n1836_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(0) D=n1836_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(13) D=n1836_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(12) D=n1836_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(11) D=n1836_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(10) D=n1836_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(9) D=n1836_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(8) D=n1836_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(7) D=n1836_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1836(6) D=n1836_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5579.1-5584.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_O I3=n1760_LUT4_I2_O O=n1836_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_1_O I3=n1760_LUT4_I2_1_O O=n1836_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_10_O I3=n1760_LUT4_I2_10_O O=n1836_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_11_O I3=n1760_LUT4_I2_11_O O=n1836_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_12_O I3=n1760_LUT4_I2_12_O O=n1836_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_13_O I3=n1760_LUT4_I2_13_O O=n1836_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_14_O I3=n1760_LUT4_I2_14_O O=n1836_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_15_O I3=n1760_LUT4_I2_15_O O=n1836_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_2_O I3=n1760_LUT4_I2_2_O O=n1836_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_3_O I3=n1760_LUT4_I2_3_O O=n1836_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_4_O I3=n1760_LUT4_I2_4_O O=n1836_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_5_O I3=n1760_LUT4_I2_5_O O=n1836_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_6_O I3=n1760_LUT4_I2_6_O O=n1836_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_7_O I3=n1760_LUT4_I2_7_O O=n1836_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_8_O I3=n1760_LUT4_I2_8_O O=n1836_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1760_LUT4_I3_9_O I3=n1760_LUT4_I2_9_O O=n1836_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=n1842(15) D=n1842_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(14) D=n1842_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(5) D=n1842_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(4) D=n1842_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(3) D=n1842_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(2) D=n1842_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(1) D=n1842_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(0) D=n1842_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(13) D=n1842_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(12) D=n1842_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(11) D=n1842_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(10) D=n1842_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(9) D=n1842_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(8) D=n1842_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(7) D=n1842_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1842(6) D=n1842_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5585.1-5590.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_O I3=n1797_LUT4_I2_O O=n1842_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_1_O I3=n1797_LUT4_I2_1_O O=n1842_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_10_O I3=n1797_LUT4_I2_10_O O=n1842_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_11_O I3=n1797_LUT4_I2_11_O O=n1842_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_12_O I3=n1797_LUT4_I2_12_O O=n1842_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_13_O I3=n1797_LUT4_I2_13_O O=n1842_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_14_O I3=n1797_LUT4_I2_14_O O=n1842_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_15_O I3=n1797_LUT4_I2_15_O O=n1842_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_2_O I3=n1797_LUT4_I2_2_O O=n1842_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_3_O I3=n1797_LUT4_I2_3_O O=n1842_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_4_O I3=n1797_LUT4_I2_4_O O=n1842_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_5_O I3=n1797_LUT4_I2_5_O O=n1842_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_6_O I3=n1797_LUT4_I2_6_O O=n1842_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_7_O I3=n1797_LUT4_I2_7_O O=n1842_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_8_O I3=n1797_LUT4_I2_8_O O=n1842_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1797_LUT4_I3_9_O I3=n1797_LUT4_I2_9_O O=n1842_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1848(7) I3=n2062 O=n1852_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1848(6) I3=n2062 O=n1852_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1848(5) I3=n2062 O=n1852_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1848(4) I3=n2062 O=n1852_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1848(3) I3=n2062 O=n1852_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1848(2) I3=n2062 O=n1852_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1848(1) I3=n2062 O=n1852_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1848(0) I3=n2062 O=n1852_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1848(7) D=n1848_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5591.1-5596.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1848(6) D=n1848_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5591.1-5596.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1848(5) D=n1848_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5591.1-5596.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1848(4) D=n1848_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5591.1-5596.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1848(3) D=n1848_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5591.1-5596.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1848(2) D=n1848_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5591.1-5596.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1848(1) D=n1848_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5591.1-5596.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1848(0) D=n1848_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5591.1-5596.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(15) I3=n2062 O=n1848_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(14) I3=n2062 O=n1848_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(13) I3=n2062 O=n1848_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(12) I3=n2062 O=n1848_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(11) I3=n2062 O=n1848_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(10) I3=n2062 O=n1848_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(9) I3=n2062 O=n1848_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(8) I3=n2062 O=n1848_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184(7) I3=n2062 O=n195_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184(6) I3=n2062 O=n195_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184(5) I3=n2062 O=n195_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184(4) I3=n2062 O=n195_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184(3) I3=n2062 O=n195_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184(2) I3=n2062 O=n195_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184(1) I3=n2062 O=n195_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184(0) I3=n2062 O=n195_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n184(7) D=n184_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3631.1-3636.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n184(6) D=n184_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3631.1-3636.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n184(5) D=n184_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3631.1-3636.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n184(4) D=n184_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3631.1-3636.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n184(3) D=n184_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3631.1-3636.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n184(2) D=n184_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3631.1-3636.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n184(1) D=n184_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3631.1-3636.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n184(0) D=n184_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3631.1-3636.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n184_ff_CQZ_D_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_I3 O=n184_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n184_ff_CQZ_D_LUT4_O_1_I3 O=n184_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_2_I1 I1=n184_ff_CQZ_D_LUT4_O_2_I3 I2=n184_ff_CQZ_D_LUT4_O_2_I2 I3=n184_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n2062 I1=n184_ff_CQZ_D_LUT4_O_2_I1 I2=n184_ff_CQZ_D_LUT4_O_2_I2 I3=n184_ff_CQZ_D_LUT4_O_2_I3 O=n184_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n184_ff_CQZ_D_LUT4_O_3_I2 I2=n184_ff_CQZ_D_LUT4_O_3_I3 I3=n184_ff_CQZ_D_LUT4_O_3_I1 O=n184_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 I3=n184_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=n184_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n154(15) I1=n154(14) I2=n154(12) I3=n154(13) O=n184_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111101010001
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I2=n154(15) I3=n184_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=n2062 I1=n184_ff_CQZ_D_LUT4_O_3_I1 I2=n184_ff_CQZ_D_LUT4_O_3_I2 I3=n184_ff_CQZ_D_LUT4_O_3_I3 O=n184_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I1=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I3=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n154(14) I1=n154(15) I2=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I3=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 O=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I2=n154(14) I3=n154(15) O=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=n154(14) I2=n154(15) I3=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I2=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n154(13) I1=n154(14) I2=n154(15) I3=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 I1=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I2=n154(14) I3=n154(15) O=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=n154(15) I2=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I3=n184_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 I3=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 O=n184_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n154(14) I1=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I2=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 I3=n154(15) O=n184_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000110000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n184_ff_CQZ_D_LUT4_O_4_I3 O=n184_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I0 I1=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I2=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I3=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=n154(13) I1=n154(14) I2=n154(15) I3=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=n1019 I1=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n184_ff_CQZ_D_LUT4_O_5_I3 O=n184_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_6_I1 I1=n184_ff_CQZ_D_LUT4_O_6_I3 I2=n184_ff_CQZ_D_LUT4_O_6_I2 I3=n184_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n184_ff_CQZ_D_LUT4_O_6_I1 I2=n184_ff_CQZ_D_LUT4_O_6_I2 I3=n184_ff_CQZ_D_LUT4_O_6_I3 O=n184_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_6_I1 I1=n184_ff_CQZ_D_LUT4_O_6_I3 I2=n184_ff_CQZ_D_LUT4_O_6_I2 I3=n184_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n184_ff_CQZ_D_LUT4_O_7_I2 I2=n184_ff_CQZ_D_LUT4_O_7_I3 I3=n184_ff_CQZ_D_LUT4_O_7_I1 O=n184_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n154(15) I2=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I0 I1=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 O=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n154(14) I2=n154(13) I3=n154(12) O=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n154(15) I2=n154(14) I3=n154(13) O=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I3=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 O=n184_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I0 I1=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I2=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I3=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n2062 I1=n184_ff_CQZ_D_LUT4_O_7_I1 I2=n184_ff_CQZ_D_LUT4_O_7_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I3 O=n184_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 I1=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n154(14) I3=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 I1=n154(13) I2=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I3=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 O=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n154(13) I1=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0 I2=n154(8) I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 O=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=n1019 I1=n154(11) I2=n154(10) I3=n154(9) O=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n154(8) I1=n154(9) I2=n154(10) I3=n154(11) O=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011101111111
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0 I1=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n154(12) I3=n154(11) O=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101000110000
+.subckt LUT4 I0=n1019 I1=n154(10) I2=n154(9) I3=n154(8) O=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n154(10) I2=n154(9) I3=n154(8) O=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 I1=n154(14) I2=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0 I1=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 I2=n184_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n154(8) O=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=n1019 I1=n154(9) I2=n154(8) I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n154(12) I2=n154(11) I3=n154(10) O=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n154(11) I2=n154(10) I3=n154(9) O=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n154(12) I2=n154(11) I3=n154(10) O=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n154(8) I1=n154(9) I2=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n154(10) O=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n154(13) I2=n154(12) I3=n154(11) O=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n154(9) I2=n154(8) I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n154(15) I2=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I0 I1=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n154(8) I2=n154(9) I3=n154(10) O=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111010101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 O=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n154(10) I2=n154(9) I3=n154(8) O=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n154(13) I2=n154(12) I3=n154(11) O=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n154(14) I2=n154(13) I3=n154(12) O=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I2=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n154(14) I1=n154(13) I2=n154(15) I3=n184_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=n184_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 O=n184_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n184_ff_CQZ_D_LUT4_O_2_I1 I1=n184_ff_CQZ_D_LUT4_O_2_I3 I2=n184_ff_CQZ_D_LUT4_O_2_I2 I3=n184_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n184_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n184_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n184_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n154(12) I1=n154(13) I2=n154(15) I3=n154(14) O=n184_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000111001111
+.subckt ff CQZ=n1852(7) D=n1852_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5597.1-5602.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1852(6) D=n1852_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5597.1-5602.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1852(5) D=n1852_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5597.1-5602.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1852(4) D=n1852_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5597.1-5602.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1852(3) D=n1852_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5597.1-5602.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1852(2) D=n1852_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5597.1-5602.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1852(1) D=n1852_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5597.1-5602.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1852(0) D=n1852_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5597.1-5602.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1856(7) I3=n2062 O=n1860_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1856(6) I3=n2062 O=n1860_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1856(5) I3=n2062 O=n1860_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1856(4) I3=n2062 O=n1860_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1856(3) I3=n2062 O=n1860_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1856(2) I3=n2062 O=n1860_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1856(1) I3=n2062 O=n1860_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1856(0) I3=n2062 O=n1860_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1856(7) D=n1856_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5603.1-5608.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1856(6) D=n1856_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5603.1-5608.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1856(5) D=n1856_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5603.1-5608.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1856(4) D=n1856_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5603.1-5608.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1856(3) D=n1856_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5603.1-5608.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1856(2) D=n1856_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5603.1-5608.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1856(1) D=n1856_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5603.1-5608.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1856(0) D=n1856_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5603.1-5608.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(7) I3=n2062 O=n1856_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(6) I3=n2062 O=n1856_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(5) I3=n2062 O=n1856_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(4) I3=n2062 O=n1856_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(3) I3=n2062 O=n1856_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(2) I3=n2062 O=n1856_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(1) I3=n2062 O=n1856_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1836(0) I3=n2062 O=n1856_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1860(7) D=n1860_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5609.1-5614.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1860(6) D=n1860_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5609.1-5614.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1860(5) D=n1860_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5609.1-5614.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1860(4) D=n1860_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5609.1-5614.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1860(3) D=n1860_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5609.1-5614.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1860(2) D=n1860_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5609.1-5614.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1860(1) D=n1860_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5609.1-5614.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1860(0) D=n1860_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5609.1-5614.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(15) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(14) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(5) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(4) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(3) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(2) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(1) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(0) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(13) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(12) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(11) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(10) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(9) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(8) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(7) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1863(6) D=n1741_LUT4_I3_O_LUT4_I1_1_I3_LUT4_I0_O_LUT4_I2_O_LUT4_I3_O_LUT4_I2_O(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5615.1-5746.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1871(7) D=n1871_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5747.1-5752.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1871(6) D=n1871_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5747.1-5752.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1871(5) D=n1871_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5747.1-5752.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1871(4) D=n1871_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5747.1-5752.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1871(3) D=n1871_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5747.1-5752.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1871(2) D=n1871_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5747.1-5752.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1871(1) D=n1871_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5747.1-5752.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1871(0) D=n1871_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5747.1-5752.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n1871_ff_CQZ_D_LUT4_O_I3 O=n1871_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_1_I1 I2=n1871_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n1871_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_2_I2 I2=n1871_ff_CQZ_D_LUT4_O_2_I3 I3=n1871_ff_CQZ_D_LUT4_O_2_I1 O=n1871_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1871_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n1871_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1871_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1871_ff_CQZ_D_LUT4_O_2_I1 I2=n1871_ff_CQZ_D_LUT4_O_2_I2 I3=n1871_ff_CQZ_D_LUT4_O_2_I3 O=n1871_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 I2=n1842(12) I3=n1863(14) O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1863(13) I2=n1842(12) I3=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(13) I1=n1863(12) I2=n1842(14) I3=n1863(11) O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(13) I1=n1842(14) I2=n1863(11) I3=n1863(12) O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1842(14) I1=n1863(13) I2=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1842(13) I1=n1863(14) I2=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I3=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(12) I3=n1842(15) O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1842(15) I3=n1863(10) O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1842(15) I1=n1863(11) I2=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(12) I3=n1842(14) O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(13) I3=n1842(13) O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I2=n1863(14) I3=n1842(12) O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(11) O=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1842(13) I3=n1863(14) O=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n1842(15) I3=n1863(11) O=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(12) O=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1863(13) I3=n1842(15) O=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1842(14) I1=n1863(13) I2=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1871_ff_CQZ_D_LUT4_O_3_I3 O=n1871_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1871_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1871_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=n1842(11) I3=n1863(14) O=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I2=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I3=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1871_ff_CQZ_D_LUT4_O_4_I3 O=n1871_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_5_I1 I1=n1871_ff_CQZ_D_LUT4_O_5_I3 I2=n1871_ff_CQZ_D_LUT4_O_5_I2 I3=n1871_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1871_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1871_ff_CQZ_D_LUT4_O_5_I1 I2=n1871_ff_CQZ_D_LUT4_O_5_I2 I3=n1871_ff_CQZ_D_LUT4_O_5_I3 O=n1871_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_5_I1 I1=n1871_ff_CQZ_D_LUT4_O_5_I3 I2=n1871_ff_CQZ_D_LUT4_O_5_I2 I3=n1871_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I3 I2=n1871_ff_CQZ_D_LUT4_O_6_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I1 O=n1871_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1842(10) I3=n1863(14) O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1863(13) I2=n1842(10) I3=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(11) I1=n1863(12) I2=n1842(12) I3=n1863(11) O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(11) I1=n1842(12) I2=n1863(11) I3=n1863(12) O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(9) O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(11) I1=n1863(14) I2=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1863(13) I2=n1842(11) I3=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(12) I1=n1842(13) I2=n1863(11) I3=n1863(12) O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(10) O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1842(15) I2=n1863(10) I3=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(9) I3=n1842(14) O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1863(13) I3=n1842(12) O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n2062 I1=n1871_ff_CQZ_D_LUT4_O_6_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I3 O=n1871_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1863(14) I2=n1842(8) I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1863(13) I2=n1842(8) I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(9) I1=n1863(12) I2=n1842(10) I3=n1863(11) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(9) I1=n1842(10) I2=n1863(11) I3=n1863(12) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1863(10) I2=n1842(10) I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1863(8) I1=n1842(12) I2=n1842(11) I3=n1863(9) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1863(8) I1=n1842(11) I2=n1842(12) I3=n1863(9) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1863(13) I3=n1842(8) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1863(10) I3=n1842(11) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=n1863(14) I3=n1842(8) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(9) I1=n1863(14) I2=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I3=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1863(13) I3=n1842(9) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1863(10) I2=n1842(11) I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1863(8) I1=n1842(13) I2=n1842(12) I3=n1863(9) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1863(8) I1=n1842(12) I2=n1842(13) I3=n1863(9) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1863(10) I3=n1842(12) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1863(13) I3=n1842(10) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1863(8) I1=n1842(15) I2=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(10) I3=n1842(13) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1863(10) I2=n1842(12) I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1863(8) I1=n1842(14) I2=n1842(13) I3=n1863(9) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1863(8) I1=n1842(13) I2=n1842(14) I3=n1863(9) O=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=n1842(9) I3=n1863(14) O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1863(13) I2=n1842(9) I3=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(10) I1=n1863(12) I2=n1842(11) I3=n1863(11) O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(10) I1=n1842(11) I2=n1863(11) I3=n1863(12) O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(8) O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(10) I1=n1863(14) I2=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1842(14) I1=n1863(10) I2=n1842(15) I3=n1863(9) O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1863(13) I3=n1842(11) O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1842(12) I1=n1863(12) I2=n1842(13) I3=n1863(11) O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1863(8) I3=n1842(15) O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1871_ff_CQZ_D_LUT4_O_7_I3 O=n1871_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I0 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1842(8) I3=n1863(8) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(10) I3=n1842(8) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(9) I3=n1842(9) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1842(10) I3=n1863(8) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1842(8) I1=n1863(11) I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1863(10) I3=n1842(10) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1863(8) I1=n1842(10) I2=n1842(11) I3=n1863(9) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(10) I3=n1842(9) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1863(8) I1=n1842(11) I2=n1842(10) I3=n1863(9) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(9) I1=n1863(11) I2=n1842(8) I3=n1863(12) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n1842(8) I3=n1863(11) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1842(9) I1=n1842(8) I2=n1863(11) I3=n1863(12) O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_2_I1 I1=n1871_ff_CQZ_D_LUT4_O_2_I3 I2=n1871_ff_CQZ_D_LUT4_O_2_I2 I3=n1871_ff_CQZ_D_LUT4_O_1_I2 O=n1871_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1871_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n1871_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1863(13) I2=n1842(15) I3=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1842(14) I1=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1842(14) I1=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1863(13) I2=n1842(14) I3=n1871_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(13) O=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1842(14) I1=n1863(15) I2=n1842(15) I3=n1863(14) O=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(14) I1=n1863(14) I2=n1842(15) I3=n1863(15) O=n1871_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt ff CQZ=n1877(7) D=n1877_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5753.1-5758.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1877(6) D=n1877_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5753.1-5758.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1877(5) D=n1877_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5753.1-5758.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1877(4) D=n1877_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5753.1-5758.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1877(3) D=n1877_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5753.1-5758.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1877(2) D=n1877_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5753.1-5758.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1877(1) D=n1877_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5753.1-5758.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1877(0) D=n1877_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5753.1-5758.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n1877_ff_CQZ_D_LUT4_O_I3 O=n1877_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n2062 I1=n1877_ff_CQZ_D_LUT4_O_1_I1 I2=n1877_ff_CQZ_D_LUT4_O_1_I2 I3=n1877_ff_CQZ_D_LUT4_O_1_I3 O=n1877_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_2_I2 I2=n1877_ff_CQZ_D_LUT4_O_2_I3 I3=n1877_ff_CQZ_D_LUT4_O_2_I1 O=n1877_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1877_ff_CQZ_D_LUT4_O_1_I3 I3=n1877_ff_CQZ_D_LUT4_O_1_I2 O=n1877_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n1877_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1877_ff_CQZ_D_LUT4_O_2_I1 I2=n1877_ff_CQZ_D_LUT4_O_2_I2 I3=n1877_ff_CQZ_D_LUT4_O_2_I3 O=n1877_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 I2=n1842(4) I3=n1863(6) O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1863(5) I2=n1842(4) I3=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(5) I1=n1863(4) I2=n1842(6) I3=n1863(3) O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(5) I1=n1842(6) I2=n1863(3) I3=n1863(4) O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1842(6) I1=n1863(5) I2=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1842(5) I1=n1863(6) I2=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I3=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(4) I3=n1842(7) O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1842(7) I3=n1863(2) O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1842(7) I1=n1863(3) I2=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(4) I3=n1842(6) O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(5) I3=n1842(5) O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I2=n1863(6) I3=n1842(4) O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(3) O=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1842(5) I3=n1863(6) O=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n1842(7) I3=n1863(3) O=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(4) O=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1863(5) I3=n1842(7) O=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1842(6) I1=n1863(5) I2=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1877_ff_CQZ_D_LUT4_O_3_I3 O=n1877_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1877_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1877_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=n1842(3) I3=n1863(6) O=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I2=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I3=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1877_ff_CQZ_D_LUT4_O_4_I3 O=n1877_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I1 I1=n1877_ff_CQZ_D_LUT4_O_5_I3 I2=n1877_ff_CQZ_D_LUT4_O_5_I2 I3=n1877_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1877_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1877_ff_CQZ_D_LUT4_O_5_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I3 O=n1877_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I1 I1=n1877_ff_CQZ_D_LUT4_O_5_I3 I2=n1877_ff_CQZ_D_LUT4_O_5_I2 I3=n1877_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n1877_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n1877_ff_CQZ_D_LUT4_O_7_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I1 O=n1877_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n1842(1) I3=n1863(6) O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1863(5) I2=n1842(1) I3=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(2) I1=n1863(4) I2=n1842(3) I3=n1863(3) O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(2) I1=n1842(3) I2=n1863(3) I3=n1863(4) O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(0) O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(2) I1=n1863(6) I2=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1842(6) I1=n1863(2) I2=n1842(7) I3=n1863(1) O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1863(5) I3=n1842(3) O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1842(4) I1=n1863(4) I2=n1842(5) I3=n1863(3) O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1863(0) I3=n1842(7) O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1842(2) I3=n1863(6) O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1863(5) I2=n1842(2) I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(3) I1=n1863(4) I2=n1842(4) I3=n1863(3) O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(3) I1=n1842(4) I2=n1863(3) I3=n1863(4) O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(1) O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(3) I1=n1863(6) I2=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1863(5) I2=n1842(3) I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(4) I1=n1842(5) I2=n1863(3) I3=n1863(4) O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(2) O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1842(7) I2=n1863(2) I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(1) I3=n1842(6) O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1863(5) I3=n1842(4) O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1877_ff_CQZ_D_LUT4_O_6_I3 O=n1877_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I2 I1=n1877_ff_CQZ_D_LUT4_O_7_I1 I2=n1877_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2 I3=n2062 O=n1877_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1842(1) I1=n1842(0) I2=n1863(3) I3=n1863(4) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1863(0) I1=n1842(0) I2=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1863(2) I3=n1842(2) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n1863(2) I2=n1842(1) I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1863(0) I1=n1842(3) I2=n1842(2) I3=n1863(1) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1863(0) I1=n1842(2) I2=n1842(3) I3=n1863(1) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1842(1) I1=n1863(3) I2=n1842(0) I3=n1863(4) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1863(3) I2=n1842(0) I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I2=n1863(2) I3=n1842(1) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n1863(3) I3=n1842(0) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1863(0) I3=n1842(2) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1863(0) I3=n1842(2) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(2) I3=n1842(0) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(1) I3=n1842(1) O=n1877_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1863(6) I2=n1842(0) I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1863(5) I2=n1842(0) I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(1) I1=n1863(4) I2=n1842(2) I3=n1863(3) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(1) I1=n1842(2) I2=n1863(3) I3=n1863(4) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1863(2) I2=n1842(2) I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1863(0) I1=n1842(4) I2=n1842(3) I3=n1863(1) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1863(0) I1=n1842(3) I2=n1842(4) I3=n1863(1) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1863(5) I3=n1842(0) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1863(2) I3=n1842(3) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 I2=n1863(6) I3=n1842(0) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(1) I1=n1863(6) I2=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I3=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1863(5) I3=n1842(1) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1863(2) I2=n1842(3) I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1863(0) I1=n1842(5) I2=n1842(4) I3=n1863(1) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1863(0) I1=n1842(4) I2=n1842(5) I3=n1863(1) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1863(2) I3=n1842(4) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1863(5) I3=n1842(2) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1863(0) I1=n1842(7) I2=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(2) I3=n1842(5) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1863(2) I2=n1842(4) I3=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1863(0) I1=n1842(6) I2=n1842(5) I3=n1863(1) O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1842(5) I2=n1863(0) I3=n1877_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=n1877_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_2_I1 I1=n1877_ff_CQZ_D_LUT4_O_2_I3 I2=n1877_ff_CQZ_D_LUT4_O_2_I2 I3=n1877_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1877_ff_CQZ_D_LUT4_O_1_I2 I3=n1877_ff_CQZ_D_LUT4_O_1_I3 O=n1877_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1863(5) I2=n1842(7) I3=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1842(6) I1=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1863(6) O=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1842(6) I1=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1863(6) O=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1863(5) I2=n1842(6) I3=n1877_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(5) O=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1842(6) I1=n1863(7) I2=n1842(7) I3=n1863(6) O=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(6) I1=n1863(6) I2=n1842(7) I3=n1863(7) O=n1877_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt ff CQZ=n1882(7) D=n1882_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5759.1-5764.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1882(6) D=n1882_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5759.1-5764.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1882(5) D=n1882_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5759.1-5764.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1882(4) D=n1882_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5759.1-5764.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1882(3) D=n1882_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5759.1-5764.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1882(2) D=n1882_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5759.1-5764.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1882(1) D=n1882_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5759.1-5764.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1882(0) D=n1882_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5759.1-5764.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1882_ff_CQZ_D_LUT4_O_I1 I2=n1877(7) I3=n1871(7) O=n1882_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1882_ff_CQZ_D_LUT4_O_1_I1 I2=n1877(6) I3=n1871(6) O=n1882_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1871(5) I2=n1877(5) I3=n1882_ff_CQZ_D_LUT4_O_2_I1 O=n1882_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1882_ff_CQZ_D_LUT4_O_2_I1 I2=n1877(5) I3=n1871(5) O=n1882_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1871(4) I2=n1877(4) I3=n1882_ff_CQZ_D_LUT4_O_3_I1 O=n1882_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1882_ff_CQZ_D_LUT4_O_3_I1 I2=n1877(4) I3=n1871(4) O=n1882_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1871(3) I2=n1877(3) I3=n1882_ff_CQZ_D_LUT4_O_4_I1 O=n1882_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1882_ff_CQZ_D_LUT4_O_4_I1 I2=n1877(3) I3=n1871(3) O=n1882_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1871(2) I2=n1877(2) I3=n1882_ff_CQZ_D_LUT4_O_5_I1 O=n1882_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1882_ff_CQZ_D_LUT4_O_5_I1 I2=n1877(2) I3=n1871(2) O=n1882_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1877(1) I1=n1871(1) I2=n1871(0) I3=n1877(0) O=n1882_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1882_ff_CQZ_D_LUT4_O_6_I3 O=n1882_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1871(0) I1=n1877(0) I2=n1877(1) I3=n1871(1) O=n1882_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n1871(0) I2=n1877(0) I3=n2062 O=n1882_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1871(6) I2=n1877(6) I3=n1882_ff_CQZ_D_LUT4_O_1_I1 O=n1882_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=n1888(7) D=n1888_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5765.1-5770.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1888(6) D=n1888_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5765.1-5770.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1888(5) D=n1888_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5765.1-5770.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1888(4) D=n1888_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5765.1-5770.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1888(3) D=n1888_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5765.1-5770.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1888(2) D=n1888_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5765.1-5770.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1888(1) D=n1888_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5765.1-5770.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1888(0) D=n1888_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5765.1-5770.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n1888_ff_CQZ_D_LUT4_O_I3 O=n1888_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_1_I1 I2=n1888_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n1888_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_2_I2 I2=n1888_ff_CQZ_D_LUT4_O_2_I3 I3=n1888_ff_CQZ_D_LUT4_O_2_I1 O=n1888_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1888_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n1888_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n1888_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1888_ff_CQZ_D_LUT4_O_2_I1 I2=n1888_ff_CQZ_D_LUT4_O_2_I2 I3=n1888_ff_CQZ_D_LUT4_O_2_I3 O=n1888_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 I2=n1842(12) I3=n1863(6) O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1863(5) I2=n1842(12) I3=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(13) I1=n1863(4) I2=n1842(14) I3=n1863(3) O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(13) I1=n1842(14) I2=n1863(3) I3=n1863(4) O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1842(14) I1=n1863(5) I2=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1842(13) I1=n1863(6) I2=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I3=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(4) I3=n1842(15) O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1842(15) I3=n1863(2) O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n1842(15) I1=n1863(3) I2=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(4) I3=n1842(14) O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(5) I3=n1842(13) O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I2=n1863(6) I3=n1842(12) O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(11) O=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n1842(13) I3=n1863(6) O=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n1842(15) I3=n1863(3) O=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(12) O=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n1863(5) I3=n1842(15) O=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1842(14) I1=n1863(5) I2=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1888_ff_CQZ_D_LUT4_O_3_I3 O=n1888_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1888_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n1888_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=n1842(11) I3=n1863(6) O=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I2=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I3=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1888_ff_CQZ_D_LUT4_O_4_I3 O=n1888_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_5_I1 I1=n1888_ff_CQZ_D_LUT4_O_5_I3 I2=n1888_ff_CQZ_D_LUT4_O_5_I2 I3=n1888_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1888_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1888_ff_CQZ_D_LUT4_O_5_I1 I2=n1888_ff_CQZ_D_LUT4_O_5_I2 I3=n1888_ff_CQZ_D_LUT4_O_5_I3 O=n1888_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_5_I1 I1=n1888_ff_CQZ_D_LUT4_O_5_I3 I2=n1888_ff_CQZ_D_LUT4_O_5_I2 I3=n1888_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I3 I2=n1888_ff_CQZ_D_LUT4_O_6_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I1 O=n1888_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n1842(10) I3=n1863(6) O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1863(5) I2=n1842(10) I3=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(11) I1=n1863(4) I2=n1842(12) I3=n1863(3) O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(11) I1=n1842(12) I2=n1863(3) I3=n1863(4) O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(9) O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(11) I1=n1863(6) I2=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1863(5) I2=n1842(11) I3=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(12) I1=n1842(13) I2=n1863(3) I3=n1863(4) O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(10) O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1842(15) I2=n1863(2) I3=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(1) I3=n1842(14) O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1863(5) I3=n1842(12) O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n2062 I1=n1888_ff_CQZ_D_LUT4_O_6_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I3 O=n1888_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1863(6) I2=n1842(8) I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1863(5) I2=n1842(8) I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(9) I1=n1863(4) I2=n1842(10) I3=n1863(3) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(9) I1=n1842(10) I2=n1863(3) I3=n1863(4) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1863(2) I2=n1842(10) I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(11) I1=n1863(1) I2=n1842(12) I3=n1863(0) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(11) I1=n1842(12) I2=n1863(0) I3=n1863(1) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1863(5) I3=n1842(8) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1863(2) I3=n1842(11) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=n1863(6) I3=n1842(8) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(9) I1=n1863(6) I2=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I3=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1863(5) I3=n1842(9) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1863(2) I2=n1842(11) I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(12) I1=n1863(1) I2=n1842(13) I3=n1863(0) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(12) I1=n1842(13) I2=n1863(0) I3=n1863(1) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n1863(2) I3=n1842(12) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n1863(5) I3=n1842(10) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1842(15) I1=n1863(0) I2=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(2) I3=n1842(13) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n1863(2) I2=n1842(12) I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(13) I1=n1863(1) I2=n1842(14) I3=n1863(0) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(13) I1=n1842(14) I2=n1863(0) I3=n1863(1) O=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=n1842(9) I3=n1863(6) O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n1863(5) I2=n1842(9) I3=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(10) I1=n1863(4) I2=n1842(11) I3=n1863(3) O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(10) I1=n1842(11) I2=n1863(3) I3=n1863(4) O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(8) O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(10) I1=n1863(6) I2=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1842(14) I1=n1863(2) I2=n1842(15) I3=n1863(1) O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1863(5) I3=n1842(11) O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1842(12) I1=n1863(4) I2=n1842(13) I3=n1863(3) O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1842(15) I3=n1863(0) O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1888_ff_CQZ_D_LUT4_O_7_I3 O=n1888_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I0 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1842(8) I3=n1863(0) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(2) I3=n1842(8) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(0) I3=n1842(10) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(1) I3=n1842(9) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1842(8) I1=n1863(3) I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1863(2) I3=n1842(10) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1842(10) I1=n1842(11) I2=n1863(0) I3=n1863(1) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(2) I3=n1842(9) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1842(10) I1=n1863(1) I2=n1842(11) I3=n1863(0) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(9) I1=n1863(3) I2=n1842(8) I3=n1863(4) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n1842(8) I3=n1863(3) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1842(9) I1=n1842(8) I2=n1863(3) I3=n1863(4) O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_2_I1 I1=n1888_ff_CQZ_D_LUT4_O_2_I3 I2=n1888_ff_CQZ_D_LUT4_O_2_I2 I3=n1888_ff_CQZ_D_LUT4_O_1_I2 O=n1888_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1888_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n1888_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1863(5) I2=n1842(15) I3=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1842(14) I1=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1863(6) O=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1842(14) I1=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1863(6) O=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n1863(5) I2=n1842(14) I3=n1888_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(7) I3=n1842(13) O=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1842(14) I1=n1863(7) I2=n1842(15) I3=n1863(6) O=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(14) I1=n1863(6) I2=n1842(15) I3=n1863(7) O=n1888_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt ff CQZ=n1894(7) D=n1894_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5771.1-5776.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1894(6) D=n1894_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5771.1-5776.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1894(5) D=n1894_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5771.1-5776.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1894(4) D=n1894_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5771.1-5776.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1894(3) D=n1894_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5771.1-5776.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1894(2) D=n1894_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5771.1-5776.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1894(1) D=n1894_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5771.1-5776.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1894(0) D=n1894_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5771.1-5776.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n1894_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1894_ff_CQZ_D_LUT4_O_1_I3 O=n1894_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I1=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I3=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1894_ff_CQZ_D_LUT4_O_2_I3 O=n1894_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_3_I1 I1=n1894_ff_CQZ_D_LUT4_O_3_I3 I2=n1894_ff_CQZ_D_LUT4_O_3_I2 I3=n1894_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n1894_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n1894_ff_CQZ_D_LUT4_O_3_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I3 O=n1894_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_3_I1 I1=n1894_ff_CQZ_D_LUT4_O_3_I3 I2=n1894_ff_CQZ_D_LUT4_O_3_I2 I3=n1894_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I1=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I3=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1842(3) I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1842(3) I1=n1842(4) I2=n1863(12) I3=n1863(13) O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(2) O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(4) I1=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1842(7) I2=n1863(11) I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(10) I3=n1842(6) O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1842(5) I1=n1863(13) I2=n1842(6) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1842(6) I1=n1863(11) I2=n1842(7) I3=n1863(10) O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1842(3) I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1842(4) I1=n1863(13) I2=n1842(5) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1842(4) I1=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1842(4) I1=n1842(5) I2=n1863(12) I3=n1863(13) O=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(3) O=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1842(6) I1=n1863(13) I2=n1842(7) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(5) I1=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n1842(7) I3=n1863(11) O=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1894_ff_CQZ_D_LUT4_O_4_I3 O=n1894_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1894_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 I3=n1894_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 O=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1863(15) I1=n1842(1) I2=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(14) I3=n1842(2) O=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1894_ff_CQZ_D_LUT4_O_5_I3 O=n1894_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_6_I1 I1=n1894_ff_CQZ_D_LUT4_O_6_I3 I2=n1894_ff_CQZ_D_LUT4_O_6_I2 I3=n1894_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1894_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n1894_ff_CQZ_D_LUT4_O_6_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3 O=n1894_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_6_I1 I1=n1894_ff_CQZ_D_LUT4_O_6_I3 I2=n1894_ff_CQZ_D_LUT4_O_6_I2 I3=n1894_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I1=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1842(0) I2=n1863(14) I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n1842(0) I2=n1863(13) I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1863(8) I1=n1842(5) I2=n1842(1) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1863(8) I1=n1842(1) I2=n1842(5) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 I2=n1842(0) I3=n1863(15) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1863(13) I3=n1842(2) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1863(8) I1=n1842(7) I2=n1842(3) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1863(9) I3=n1842(6) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1842(4) I1=n1863(11) I2=n1842(5) I3=n1863(10) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=n1863(9) I2=n1842(5) I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(3) I1=n1842(4) I2=n1863(10) I3=n1863(11) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n1863(9) I2=n1842(3) I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(1) I1=n1863(11) I2=n1842(2) I3=n1863(10) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(1) I1=n1842(2) I2=n1863(10) I3=n1863(11) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n1842(0) I3=n1863(13) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=n1863(9) I3=n1842(4) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=n1842(0) I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1863(9) I3=n1842(5) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1842(3) I1=n1863(11) I2=n1842(4) I3=n1863(10) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n1863(9) I2=n1842(4) I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(2) I1=n1863(11) I2=n1842(3) I3=n1863(10) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(2) I1=n1842(3) I2=n1863(10) I3=n1863(11) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1863(13) I3=n1842(1) O=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1842(0) I1=n1863(15) I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(14) I3=n1842(1) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1863(8) I1=n1842(6) I2=n1842(2) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1842(1) I2=n1863(14) I3=n1863(13) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n1842(1) I1=n1863(14) I2=n1842(2) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1863(15) I3=n1842(1) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n1842(2) I2=n1863(14) I3=n1863(13) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n1842(2) I1=n1863(14) I2=n1842(3) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1842(3) I1=n1863(13) I2=n1842(4) I3=n1863(12) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(11) I3=n1842(5) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(9) I3=n1842(7) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n1863(9) I2=n1842(6) I3=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(4) I1=n1842(5) I2=n1863(10) I3=n1863(11) O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1894_ff_CQZ_D_LUT4_O_7_I3 O=n1894_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011110001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1842(3) I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=n1842(1) I1=n1863(9) I2=n1863(10) I3=n1842(0) O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n1842(2) I1=n1863(9) I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1863(10) I1=n1842(0) I2=n1842(2) I3=n1863(8) O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=n1842(3) I1=n1863(8) I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1842(1) I1=n1863(9) I2=n1863(10) I3=n1842(0) O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1863(8) I1=n1842(4) I2=n1863(12) I3=n1842(0) O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1863(8) I1=n1842(4) I2=n1863(12) I3=n1842(0) O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n1863(9) I3=n1842(3) O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n1863(9) I2=n1842(2) I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1842(1) I1=n1863(10) I2=n1863(11) I3=n1842(0) O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(1) I1=n1863(10) I2=n1863(11) I3=n1842(0) O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I1=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n1863(13) I2=n1842(7) I3=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1842(6) I1=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n1842(6) I1=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1842(6) I1=n1842(7) I2=n1863(12) I3=n1863(13) O=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(5) O=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1842(6) I1=n1863(15) I2=n1842(7) I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1842(6) I1=n1863(14) I2=n1842(7) I3=n1863(15) O=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1842(5) I1=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n1863(14) O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1842(5) I1=n1842(6) I2=n1863(12) I3=n1863(13) O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1863(15) I3=n1842(4) O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=n1863(13) I3=n1842(7) O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=n1894_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 O=n1894_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=n1899(7) D=n1899_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5777.1-5782.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1899(6) D=n1899_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5777.1-5782.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1899(5) D=n1899_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5777.1-5782.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1899(4) D=n1899_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5777.1-5782.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1899(3) D=n1899_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5777.1-5782.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1899(2) D=n1899_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5777.1-5782.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1899(1) D=n1899_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5777.1-5782.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1899(0) D=n1899_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5777.1-5782.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1899_ff_CQZ_D_LUT4_O_I1 I2=n1888(7) I3=n1894(7) O=n1899_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1899_ff_CQZ_D_LUT4_O_1_I1 I2=n1888(6) I3=n1894(6) O=n1899_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1894(5) I2=n1888(5) I3=n1899_ff_CQZ_D_LUT4_O_2_I1 O=n1899_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1899_ff_CQZ_D_LUT4_O_2_I1 I2=n1888(5) I3=n1894(5) O=n1899_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1894(4) I2=n1888(4) I3=n1899_ff_CQZ_D_LUT4_O_3_I1 O=n1899_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1899_ff_CQZ_D_LUT4_O_3_I1 I2=n1888(4) I3=n1894(4) O=n1899_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1894(3) I2=n1888(3) I3=n1899_ff_CQZ_D_LUT4_O_4_I1 O=n1899_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1899_ff_CQZ_D_LUT4_O_4_I1 I2=n1888(3) I3=n1894(3) O=n1899_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1894(2) I2=n1888(2) I3=n1899_ff_CQZ_D_LUT4_O_5_I1 O=n1899_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1899_ff_CQZ_D_LUT4_O_5_I1 I2=n1888(2) I3=n1894(2) O=n1899_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1888(1) I1=n1894(1) I2=n1888(0) I3=n1894(0) O=n1899_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1899_ff_CQZ_D_LUT4_O_6_I3 O=n1899_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1888(0) I1=n1894(0) I2=n1888(1) I3=n1894(1) O=n1899_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1894(0) I2=n1888(0) I3=n2062 O=n1899_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1894(6) I2=n1888(6) I3=n1899_ff_CQZ_D_LUT4_O_1_I1 O=n1899_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n1906(15) D=n1906_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(14) D=n1906_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(5) D=n1906_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(4) D=n1906_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(3) D=n1906_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(2) D=n1906_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(1) D=n1906_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(0) D=n1906_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(13) D=n1906_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(12) D=n1906_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(11) D=n1906_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(10) D=n1906_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(9) D=n1906_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(8) D=n1906_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(7) D=n1906_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1906(6) D=n1906_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5783.1-5788.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_I1 I2=n1882(7) I3=n1852(7) O=n1906_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_1_I1 I2=n1882(6) I3=n1852(6) O=n1906_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_10_I1 I2=n1899(4) I3=n1860(4) O=n1906_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1860(3) I2=n1899(3) I3=n1906_ff_CQZ_D_LUT4_O_11_I1 O=n1906_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_11_I1 I2=n1899(3) I3=n1860(3) O=n1906_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1860(2) I2=n1899(2) I3=n1906_ff_CQZ_D_LUT4_O_12_I1 O=n1906_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_12_I1 I2=n1899(2) I3=n1860(2) O=n1906_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1899(1) I1=n1860(1) I2=n1860(0) I3=n1899(0) O=n1906_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1906_ff_CQZ_D_LUT4_O_13_I3 O=n1906_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1899(0) I1=n1860(0) I2=n1899(1) I3=n1860(1) O=n1906_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1852(0) I2=n1882(0) I3=n2062 O=n1906_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1860(0) I2=n1899(0) I3=n2062 O=n1906_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1852(5) I2=n1882(5) I3=n1906_ff_CQZ_D_LUT4_O_2_I1 O=n1906_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_2_I1 I2=n1882(5) I3=n1852(5) O=n1906_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1852(4) I2=n1882(4) I3=n1906_ff_CQZ_D_LUT4_O_3_I1 O=n1906_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_3_I1 I2=n1882(4) I3=n1852(4) O=n1906_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1852(3) I2=n1882(3) I3=n1906_ff_CQZ_D_LUT4_O_4_I1 O=n1906_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_4_I1 I2=n1882(3) I3=n1852(3) O=n1906_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1852(2) I2=n1882(2) I3=n1906_ff_CQZ_D_LUT4_O_5_I1 O=n1906_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_5_I1 I2=n1882(2) I3=n1852(2) O=n1906_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1882(1) I1=n1852(1) I2=n1852(0) I3=n1882(0) O=n1906_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1906_ff_CQZ_D_LUT4_O_6_I3 O=n1906_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1882(0) I1=n1852(0) I2=n1882(1) I3=n1852(1) O=n1906_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_7_I1 I2=n1899(7) I3=n1860(7) O=n1906_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1860(6) I2=n1899(6) I3=n1906_ff_CQZ_D_LUT4_O_8_I1 O=n1906_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_8_I1 I2=n1899(6) I3=n1860(6) O=n1906_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1860(5) I2=n1899(5) I3=n1906_ff_CQZ_D_LUT4_O_9_I1 O=n1906_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n1906_ff_CQZ_D_LUT4_O_9_I1 I2=n1899(5) I3=n1860(5) O=n1906_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n1860(4) I2=n1899(4) I3=n1906_ff_CQZ_D_LUT4_O_10_I1 O=n1906_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n1852(6) I2=n1882(6) I3=n1906_ff_CQZ_D_LUT4_O_1_I1 O=n1906_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n1913(15) D=n1913_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(14) D=n1913_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(5) D=n1913_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(4) D=n1913_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(3) D=n1913_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(2) D=n1913_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(1) D=n1913_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(0) D=n1906_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(13) D=n1913_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(12) D=n1913_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(11) D=n1913_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(10) D=n1913_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(9) D=n1913_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(8) D=n1906_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(7) D=n1913_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1913(6) D=n1913_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5789.1-5794.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_I1 I2=n1882(7) I3=n1852(7) O=n1913_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_1_I1 I2=n1882(6) I3=n1852(6) O=n1913_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_10_I1 I2=n1899(4) I3=n1860(4) O=n1913_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1860(3) I2=n1899(3) I3=n1913_ff_CQZ_D_LUT4_O_11_I1 O=n1913_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_11_I1 I2=n1899(3) I3=n1860(3) O=n1913_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1860(2) I2=n1899(2) I3=n1913_ff_CQZ_D_LUT4_O_12_I1 O=n1913_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_12_I1 I2=n1899(2) I3=n1860(2) O=n1913_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1899(1) I1=n1860(1) I2=n1860(0) I3=n1899(0) O=n1913_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1913_ff_CQZ_D_LUT4_O_13_I3 O=n1913_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1860(0) I1=n1899(0) I2=n1899(1) I3=n1860(1) O=n1913_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n1852(5) I2=n1882(5) I3=n1913_ff_CQZ_D_LUT4_O_2_I1 O=n1913_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_2_I1 I2=n1882(5) I3=n1852(5) O=n1913_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1852(4) I2=n1882(4) I3=n1913_ff_CQZ_D_LUT4_O_3_I1 O=n1913_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_3_I1 I2=n1882(4) I3=n1852(4) O=n1913_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1852(3) I2=n1882(3) I3=n1913_ff_CQZ_D_LUT4_O_4_I1 O=n1913_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_4_I1 I2=n1882(3) I3=n1852(3) O=n1913_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1852(2) I2=n1882(2) I3=n1913_ff_CQZ_D_LUT4_O_5_I1 O=n1913_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_5_I1 I2=n1882(2) I3=n1852(2) O=n1913_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1882(1) I1=n1852(1) I2=n1852(0) I3=n1882(0) O=n1913_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1913_ff_CQZ_D_LUT4_O_6_I3 O=n1913_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1852(0) I1=n1882(0) I2=n1882(1) I3=n1852(1) O=n1913_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_7_I1 I2=n1899(7) I3=n1860(7) O=n1913_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1860(6) I2=n1899(6) I3=n1913_ff_CQZ_D_LUT4_O_8_I1 O=n1913_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_8_I1 I2=n1899(6) I3=n1860(6) O=n1913_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1860(5) I2=n1899(5) I3=n1913_ff_CQZ_D_LUT4_O_9_I1 O=n1913_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n1913_ff_CQZ_D_LUT4_O_9_I1 I2=n1899(5) I3=n1860(5) O=n1913_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n1860(4) I2=n1899(4) I3=n1913_ff_CQZ_D_LUT4_O_10_I1 O=n1913_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1852(6) I2=n1882(6) I3=n1913_ff_CQZ_D_LUT4_O_1_I1 O=n1913_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1918 I3=n2062 O=n1922_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1918 D=n1918_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5795.1-5800.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1922 I3=n2062 O=n1926_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1922 D=n1922_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5801.1-5806.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1926 I3=n2062 O=n1930_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1926 D=n1926_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5807.1-5812.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1930 O=n1930_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1930_LUT4_I3_O I2=n1970(4) I3=n1930_LUT4_I3_O_LUT4_I1_I3 O=n1930_LUT4_I3_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1930_LUT4_I3_O I2=n1970(1) I3=n1970(0) O=n1930_LUT4_I3_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1970(0) I1=n1970(1) I2=n1970(2) I3=n1970(3) O=n1930_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1930_LUT4_I3_O I3=n1930_LUT4_I3_O_LUT4_I2_I3 O=n1930_LUT4_I3_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1930_LUT4_I3_O I3=n1970(0) O=n1930_LUT4_I3_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1970(0) I1=n1970(1) I2=n1970(2) I3=n1970(3) O=n1930_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n1930_LUT4_I3_O_LUT4_I1_I3 I1=n1970(4) I2=n1970(5) I3=n1930_LUT4_I3_O O=n1930_LUT4_I3_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1970(0) I1=n1970(1) I2=n1970(2) I3=n1930_LUT4_I3_O O=n1930_LUT4_I3_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n1930 D=n1930_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5813.1-5818.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1817(0) D=n1741_LUT4_I3_O_LUT4_I1_O(0) QCK=$iopadmap$clock_c QEN=n2067 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5561.1-5566.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1952 I3=n2062 O=n1956_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1952 D=n1952_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5843.1-5848.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1817(0) I3=n2062 O=n1952_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1956 I3=n2062 O=n1960_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1956 D=n1956_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5849.1-5854.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n195(7) D=n195_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3643.1-3648.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n195(6) D=n195_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3643.1-3648.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n195(5) D=n195_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3643.1-3648.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n195(4) D=n195_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3643.1-3648.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n195(3) D=n195_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3643.1-3648.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n195(2) D=n195_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3643.1-3648.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n195(1) D=n195_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3643.1-3648.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n195(0) D=n195_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3643.1-3648.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1960 I3=n2062 O=n1964_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1960 D=n1960_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5855.1-5860.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1964 I2=n2059 I3=n2009(0) O=n1964_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1964 I2=n2059 I3=n2009(0) O=n1964_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n1964 I3=n1972(0) O=n1964_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=n1964 D=n1964_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5861.1-5866.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1970(5) D=n1930_LUT4_I3_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5867.1-5872.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1970(4) D=n1930_LUT4_I3_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5867.1-5872.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1970(3) D=n1930_LUT4_I3_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5867.1-5872.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1970(2) D=n1930_LUT4_I3_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5867.1-5872.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1970(1) D=n1930_LUT4_I3_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5867.1-5872.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1970(0) D=n1930_LUT4_I3_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5867.1-5872.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1972(0) I2=n2059 I3=n1964 O=n1977_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n1972(0) D=n1977_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5873.1-5878.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1930 I2=n1972(0) I3=n2062 O=n1977_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n2062 I2=n1982 I3=n1982_LUT4_I2_I3 O=n2047_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n1970(1) I1=n1970(0) I2=n1982_LUT4_I2_I3_LUT4_O_I2 I3=n2042(0) O=n1982_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n1970(2) I1=n1970(3) I2=n1970(4) I3=n1970(5) O=n1982_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=n1982 D=n1982_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5879.1-5886.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1930 I3=n2062 O=n1982_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n1993(31) D=n1906(15) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(30) D=n1906(14) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(21) D=n1906(5) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(20) D=n1906(4) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(19) D=n1906(3) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(18) D=n1906(2) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(17) D=n1906(1) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(16) D=n1906(0) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(15) D=n1913(15) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(14) D=n1913(14) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(13) D=n1913(13) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(12) D=n1913(12) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(29) D=n1906(13) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(11) D=n1913(11) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(10) D=n1913(10) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(9) D=n1913(9) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(8) D=n1913(8) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(7) D=n1913(7) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(6) D=n1913(6) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(5) D=n1913(5) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(4) D=n1913(4) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(3) D=n1913(3) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(2) D=n1913(2) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(28) D=n1906(12) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(1) D=n1913(1) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(0) D=n1913(0) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(27) D=n1906(11) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(26) D=n1906(10) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(25) D=n1906(9) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(24) D=n1906(8) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(23) D=n1906(7) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1993(22) D=n1906(6) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5887.1-5891.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(31) D=n1906(15) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(30) D=n1906(14) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(21) D=n1906(5) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(20) D=n1906(4) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(19) D=n1906(3) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(18) D=n1906(2) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(17) D=n1906(1) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(16) D=n1906(0) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(15) D=n1913(15) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(14) D=n1913(14) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(13) D=n1913(13) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(12) D=n1913(12) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(29) D=n1906(13) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(11) D=n1913(11) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(10) D=n1913(10) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(9) D=n1913(9) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(8) D=n1913(8) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(7) D=n1913(7) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(6) D=n1913(6) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(5) D=n1913(5) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(4) D=n1913(4) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(3) D=n1913(3) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(2) D=n1913(2) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(28) D=n1906(12) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(1) D=n1913(1) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(0) D=n1913(0) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(27) D=n1906(11) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(26) D=n1906(10) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(25) D=n1906(9) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(24) D=n1906(8) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(23) D=n1906(7) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n1997(22) D=n1906(6) QCK=$iopadmap$clock_c QEN=n1977_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5897.1-5901.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2001 D=n2001_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5907.1-5912.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1972(0) O=n2001_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n2009(0) D=n2014_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5919.1-5924.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2009(0) I2=n1930 I3=n2062 O=n2014_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=n2030(31) D=n1906(15) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(30) D=n1906(14) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(21) D=n1906(5) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(20) D=n1906(4) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(19) D=n1906(3) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(18) D=n1906(2) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(17) D=n1906(1) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(16) D=n1906(0) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(15) D=n1913(15) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(14) D=n1913(14) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(13) D=n1913(13) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(12) D=n1913(12) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(29) D=n1906(13) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(11) D=n1913(11) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(10) D=n1913(10) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5925.1-5929.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2030(9) D=n1913(9) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(30) D=n1906(14) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(21) D=n1906(5) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(20) D=n1906(4) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(19) D=n1906(3) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(18) D=n1906(2) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(17) D=n1906(1) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(16) D=n1906(0) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(15) D=n1913(15) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(14) D=n1913(14) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(13) D=n1913(13) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(12) D=n1913(12) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n2034(29) D=n1906(13) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(11) D=n1913(11) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(10) D=n1913(10) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(9) D=n1913(9) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(8) D=n1913(8) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(7) D=n1913(7) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(6) D=n1913(6) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(5) D=n1913(5) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(4) D=n1913(4) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(3) D=n1913(3) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(2) D=n1913(2) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(28) D=n1906(12) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(1) D=n1913(1) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(0) D=n1913(0) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(27) D=n1906(11) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(26) D=n1906(10) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(25) D=n1906(9) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(24) D=n1906(8) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(23) D=n1906(7) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2034(22) D=n1906(6) QCK=$iopadmap$clock_c QEN=n1964_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5935.1-5939.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n2038 D=n2038_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5945.1-5950.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n2009(0) O=n2038_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n2042(0) D=n2047_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:5951.1-5956.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2059 I2=n1741_LUT4_I3_O I3=n2067_LUT4_O_I3 O=n2067
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n1500_LUT4_I3_O I3=n2073_LUT4_O_I3 O=n2073
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n1259_LUT4_I3_O I3=n2079_LUT4_O_I3 O=n2079
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207(7) I3=n2062 O=n212_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207(6) I3=n2062 O=n212_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207(5) I3=n2062 O=n212_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207(4) I3=n2062 O=n212_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207(3) I3=n2062 O=n212_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207(2) I3=n2062 O=n212_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207(1) I3=n2062 O=n212_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207(0) I3=n2062 O=n212_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n207(7) D=n207_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3655.1-3660.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n207(6) D=n207_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3655.1-3660.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n207(5) D=n207_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3655.1-3660.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n207(4) D=n207_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3655.1-3660.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n207(3) D=n207_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3655.1-3660.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n207(2) D=n207_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3655.1-3660.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n207(1) D=n207_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3655.1-3660.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n207(0) D=n207_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3655.1-3660.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n207_ff_CQZ_D_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_I3 O=n207_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n207_ff_CQZ_D_LUT4_O_1_I3 O=n207_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_2_I1 I1=n207_ff_CQZ_D_LUT4_O_2_I3 I2=n207_ff_CQZ_D_LUT4_O_2_I2 I3=n207_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n2062 I1=n207_ff_CQZ_D_LUT4_O_2_I1 I2=n207_ff_CQZ_D_LUT4_O_2_I2 I3=n207_ff_CQZ_D_LUT4_O_2_I3 O=n207_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_3_I2 I2=n207_ff_CQZ_D_LUT4_O_3_I3 I3=n207_ff_CQZ_D_LUT4_O_3_I1 O=n207_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=n207_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n154(7) I1=n154(6) I2=n154(4) I3=n154(5) O=n207_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111101010001
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I2=n154(7) I3=n207_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=n2062 I1=n207_ff_CQZ_D_LUT4_O_3_I1 I2=n207_ff_CQZ_D_LUT4_O_3_I2 I3=n207_ff_CQZ_D_LUT4_O_3_I3 O=n207_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I1=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I3=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n154(6) I1=n154(7) I2=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 O=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I2=n154(6) I3=n154(7) O=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=n154(6) I2=n154(7) I3=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 I2=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n154(5) I1=n154(6) I2=n154(7) I3=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 I1=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I2=n154(6) I3=n154(7) O=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=n154(7) I2=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 O=n207_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n154(6) I1=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I2=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 I3=n154(7) O=n207_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000110000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n207_ff_CQZ_D_LUT4_O_4_I3 O=n207_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I0 I1=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I2=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I3=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=n154(5) I1=n154(6) I2=n154(7) I3=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n207_ff_CQZ_D_LUT4_O_5_I3 O=n207_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_6_I1 I1=n207_ff_CQZ_D_LUT4_O_6_I3 I2=n207_ff_CQZ_D_LUT4_O_6_I2 I3=n207_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n207_ff_CQZ_D_LUT4_O_6_I1 I2=n207_ff_CQZ_D_LUT4_O_6_I2 I3=n207_ff_CQZ_D_LUT4_O_6_I3 O=n207_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_6_I1 I1=n207_ff_CQZ_D_LUT4_O_6_I3 I2=n207_ff_CQZ_D_LUT4_O_6_I2 I3=n207_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_7_I2 I2=n207_ff_CQZ_D_LUT4_O_7_I3 I3=n207_ff_CQZ_D_LUT4_O_7_I1 O=n207_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n154(7) I2=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I0 I1=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 O=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n154(6) I2=n154(5) I3=n154(4) O=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n154(7) I2=n154(6) I3=n154(5) O=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 O=n207_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I0 I1=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I2=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I3=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n2062 I1=n207_ff_CQZ_D_LUT4_O_7_I1 I2=n207_ff_CQZ_D_LUT4_O_7_I2 I3=n207_ff_CQZ_D_LUT4_O_7_I3 O=n207_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 I1=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n154(6) O=n207_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I1=n154(5) I2=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 O=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=n154(5) I1=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0 I2=n154(0) I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 O=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n154(0) I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 O=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n1019 I1=n154(2) I2=n154(1) I3=n154(0) O=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n154(2) I2=n154(1) I3=n154(3) O=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1 I2=n154(4) I3=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n154(3) I1=n154(0) I2=n154(1) I3=n154(2) O=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n154(3) I1=n154(0) I2=n154(1) I3=n154(2) O=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 I1=n154(6) I2=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0 I1=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 I3=n154(0) O=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000101010000
+.subckt LUT4 I0=n1019 I1=n154(1) I2=n154(0) I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n154(2) I2=n154(4) I3=n154(3) O=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n154(2) I2=n154(1) I3=n154(3) O=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n154(2) I2=n154(4) I3=n154(3) O=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n154(0) I1=n154(1) I2=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n154(2) O=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n154(5) I2=n154(4) I3=n154(3) O=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n154(1) I2=n154(0) I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n154(7) I2=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I0 I1=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n154(0) I2=n154(1) I3=n154(2) O=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111010101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 O=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n154(5) I2=n154(4) I3=n154(3) O=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n154(6) I2=n154(5) I3=n154(4) O=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I2=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n154(6) I1=n154(5) I2=n154(7) I3=n207_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=n207_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 O=n207_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n207_ff_CQZ_D_LUT4_O_2_I1 I1=n207_ff_CQZ_D_LUT4_O_2_I3 I2=n207_ff_CQZ_D_LUT4_O_2_I2 I3=n207_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n207_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n207_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n207_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n154(4) I1=n154(5) I2=n154(7) I3=n154(6) O=n207_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000111001111
+.subckt LUT4 I0=n2085_LUT4_O_I0 I1=n1098(0) I2=n1018_LUT4_I3_O I3=n2059 O=n2085
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=n2085_LUT4_O_I0_LUT4_O_I0 I1=n1094(6) I2=n1094(5) I3=n1094(4) O=n2085_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n777_LUT4_I3_O I3=n2091_LUT4_O_I3 O=n2091
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n536_LUT4_I3_O I3=n2097_LUT4_O_I3 O=n2097
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n295_LUT4_I3_O I3=n2103_LUT4_O_I3 O=n2103
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n51_LUT4_I3_O I3=n2109_LUT4_O_I3 O=n2109
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=n26_LUT4_I2_I3 I1=n17(0) I2=sync_i_LUT4_I3_O I3=n2059 O=n2115
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt ff CQZ=n212(7) D=n212_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3661.1-3666.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n212(6) D=n212_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3661.1-3666.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n212(5) D=n212_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3661.1-3666.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n212(4) D=n212_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3661.1-3666.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n212(3) D=n212_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3661.1-3666.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n212(2) D=n212_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3661.1-3666.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n212(1) D=n212_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3661.1-3666.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n212(0) D=n212_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3661.1-3666.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(15) D=n219_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(14) D=n219_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(5) D=n219_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(4) D=n219_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(3) D=n219_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(2) D=n219_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(1) D=n219_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(0) D=n219_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(13) D=n219_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(12) D=n219_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(11) D=n219_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(10) D=n219_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(9) D=n219_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(8) D=n219_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(7) D=n219_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n219(6) D=n219_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3667.1-3672.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_I1 I2=n195(7) I3=n165(7) O=n219_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_1_I1 I2=n195(6) I3=n165(6) O=n219_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_10_I1 I2=n212(4) I3=n173(4) O=n219_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n173(3) I2=n212(3) I3=n219_ff_CQZ_D_LUT4_O_11_I1 O=n219_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_11_I1 I2=n212(3) I3=n173(3) O=n219_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n173(2) I2=n212(2) I3=n219_ff_CQZ_D_LUT4_O_12_I1 O=n219_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_12_I1 I2=n212(2) I3=n173(2) O=n219_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n212(1) I1=n173(1) I2=n173(0) I3=n212(0) O=n219_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n219_ff_CQZ_D_LUT4_O_13_I3 O=n219_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n212(0) I1=n173(0) I2=n212(1) I3=n173(1) O=n219_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n165(0) I2=n195(0) I3=n2062 O=n219_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n173(0) I2=n212(0) I3=n2062 O=n219_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n165(5) I2=n195(5) I3=n219_ff_CQZ_D_LUT4_O_2_I1 O=n219_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_2_I1 I2=n195(5) I3=n165(5) O=n219_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n165(4) I2=n195(4) I3=n219_ff_CQZ_D_LUT4_O_3_I1 O=n219_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_3_I1 I2=n195(4) I3=n165(4) O=n219_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n165(3) I2=n195(3) I3=n219_ff_CQZ_D_LUT4_O_4_I1 O=n219_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_4_I1 I2=n195(3) I3=n165(3) O=n219_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n165(2) I2=n195(2) I3=n219_ff_CQZ_D_LUT4_O_5_I1 O=n219_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_5_I1 I2=n195(2) I3=n165(2) O=n219_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n195(1) I1=n165(1) I2=n165(0) I3=n195(0) O=n219_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n219_ff_CQZ_D_LUT4_O_6_I3 O=n219_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n195(0) I1=n165(0) I2=n195(1) I3=n165(1) O=n219_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_7_I1 I2=n212(7) I3=n173(7) O=n219_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n173(6) I2=n212(6) I3=n219_ff_CQZ_D_LUT4_O_8_I1 O=n219_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_8_I1 I2=n212(6) I3=n173(6) O=n219_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n173(5) I2=n212(5) I3=n219_ff_CQZ_D_LUT4_O_9_I1 O=n219_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n219_ff_CQZ_D_LUT4_O_9_I1 I2=n212(5) I3=n173(5) O=n219_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n173(4) I2=n212(4) I3=n219_ff_CQZ_D_LUT4_O_10_I1 O=n219_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n165(6) I2=n195(6) I3=n219_ff_CQZ_D_LUT4_O_1_I1 O=n219_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n226(15) D=n226_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(14) D=n226_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(5) D=n226_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(4) D=n226_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(3) D=n226_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(2) D=n226_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(1) D=n226_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(0) D=n219_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(13) D=n226_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(12) D=n226_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(11) D=n226_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(10) D=n226_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(9) D=n226_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(8) D=n219_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(7) D=n226_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n226(6) D=n226_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3673.1-3678.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_I1 I2=n195(7) I3=n165(7) O=n226_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_1_I1 I2=n195(6) I3=n165(6) O=n226_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_10_I1 I2=n212(4) I3=n173(4) O=n226_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n173(3) I2=n212(3) I3=n226_ff_CQZ_D_LUT4_O_11_I1 O=n226_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_11_I1 I2=n212(3) I3=n173(3) O=n226_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n173(2) I2=n212(2) I3=n226_ff_CQZ_D_LUT4_O_12_I1 O=n226_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_12_I1 I2=n212(2) I3=n173(2) O=n226_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n212(1) I1=n173(1) I2=n173(0) I3=n212(0) O=n226_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n226_ff_CQZ_D_LUT4_O_13_I3 O=n226_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n173(0) I1=n212(0) I2=n212(1) I3=n173(1) O=n226_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n165(5) I2=n195(5) I3=n226_ff_CQZ_D_LUT4_O_2_I1 O=n226_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_2_I1 I2=n195(5) I3=n165(5) O=n226_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n165(4) I2=n195(4) I3=n226_ff_CQZ_D_LUT4_O_3_I1 O=n226_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_3_I1 I2=n195(4) I3=n165(4) O=n226_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n165(3) I2=n195(3) I3=n226_ff_CQZ_D_LUT4_O_4_I1 O=n226_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_4_I1 I2=n195(3) I3=n165(3) O=n226_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n165(2) I2=n195(2) I3=n226_ff_CQZ_D_LUT4_O_5_I1 O=n226_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_5_I1 I2=n195(2) I3=n165(2) O=n226_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n195(1) I1=n165(1) I2=n165(0) I3=n195(0) O=n226_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n226_ff_CQZ_D_LUT4_O_6_I3 O=n226_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n165(0) I1=n195(0) I2=n195(1) I3=n165(1) O=n226_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_7_I1 I2=n212(7) I3=n173(7) O=n226_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n173(6) I2=n212(6) I3=n226_ff_CQZ_D_LUT4_O_8_I1 O=n226_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_8_I1 I2=n212(6) I3=n173(6) O=n226_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n173(5) I2=n212(5) I3=n226_ff_CQZ_D_LUT4_O_9_I1 O=n226_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n226_ff_CQZ_D_LUT4_O_9_I1 I2=n212(5) I3=n173(5) O=n226_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n173(4) I2=n212(4) I3=n226_ff_CQZ_D_LUT4_O_10_I1 O=n226_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n165(6) I2=n195(6) I3=n226_ff_CQZ_D_LUT4_O_1_I1 O=n226_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=n17(0) D=n26_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3471.1-3476.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n231 I3=n2062 O=n235_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n231 D=n231_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3679.1-3684.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n235 I3=n2062 O=n239_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n235 D=n235_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3685.1-3690.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n239 I3=n2062 O=n243_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n239 D=n239_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3691.1-3696.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n243 O=n243_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n243_LUT4_I3_O I2=n283(4) I3=n243_LUT4_I3_O_LUT4_I1_I3 O=n243_LUT4_I3_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n243_LUT4_I3_O I2=n283(1) I3=n283(0) O=n243_LUT4_I3_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n283(0) I1=n283(1) I2=n283(2) I3=n283(3) O=n243_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n243_LUT4_I3_O I3=n243_LUT4_I3_O_LUT4_I2_I3 O=n243_LUT4_I3_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n243_LUT4_I3_O I3=n283(0) O=n243_LUT4_I3_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n283(0) I1=n283(1) I2=n283(2) I3=n283(3) O=n243_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n243_LUT4_I3_O_LUT4_I1_I3 I1=n283(4) I2=n283(5) I3=n243_LUT4_I3_O O=n243_LUT4_I3_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n283(0) I1=n283(1) I2=n283(2) I3=n243_LUT4_I3_O O=n243_LUT4_I3_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n243 D=n243_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3697.1-3702.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n129(0) D=n142_LUT4_I3_I2_LUT4_I3_O(0) QCK=$iopadmap$clock_c QEN=n2109 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3571.1-3576.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n265 I3=n2062 O=n269_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n265 D=n265_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3727.1-3732.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n129(0) I3=n2062 O=n265_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n269 I3=n2062 O=n273_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n269 D=n269_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3733.1-3738.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n26 I2=n26_LUT4_I2_I3 I3=n2062 O=n51_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n2062 I2=n26 I3=n26_LUT4_I2_I3 O=n26_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1019 I1=n26_LUT4_I2_O I2=n39(4) I3=n26_LUT4_I2_O_LUT4_I1_I3 O=n26_LUT4_I2_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n26_LUT4_I2_O I2=n39(1) I3=n39(0) O=n26_LUT4_I2_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n39(0) I1=n39(1) I2=n39(2) I3=n39(3) O=n26_LUT4_I2_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n26_LUT4_I2_O I3=n26_LUT4_I2_O_LUT4_I2_I3 O=n26_LUT4_I2_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n26_LUT4_I2_O I3=n39(0) O=n26_LUT4_I2_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n39(0) I1=n39(1) I2=n39(2) I3=n39(3) O=n26_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n26_LUT4_I2_O_LUT4_I1_I3 I1=n39(4) I2=n39(5) I3=n26_LUT4_I2_O O=n26_LUT4_I2_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n39(0) I1=n39(1) I2=n39(2) I3=n26_LUT4_I2_O O=n26_LUT4_I2_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n26 D=n26_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3477.1-3482.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n273 I3=n2062 O=n277_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n273 D=n273_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3739.1-3744.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n277 I2=n2059 I3=n322(0) O=n277_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n277 I2=n2059 I3=n322(0) O=n277_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n277 I3=n285(0) O=n277_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=n277 D=n277_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3745.1-3750.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n283(5) D=n243_LUT4_I3_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3751.1-3756.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n283(4) D=n243_LUT4_I3_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3751.1-3756.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n283(3) D=n243_LUT4_I3_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3751.1-3756.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n283(2) D=n243_LUT4_I3_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3751.1-3756.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n283(1) D=n243_LUT4_I3_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3751.1-3756.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n283(0) D=n243_LUT4_I3_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3751.1-3756.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n285(0) I2=n2059 I3=n277 O=n290_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n285(0) D=n290_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3757.1-3762.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n243 I2=n285(0) I3=n2062 O=n290_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n2062 I2=n295 I3=n2103_LUT4_O_I3 O=n384_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n295 O=n295_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n295 D=n295_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3763.1-3768.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n243 I3=n2062 O=n295_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n29_LUT4_I1_I0 I1=n11(6) I2=n11(4) I3=n11(5) O=n26_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n11(0) I1=n11(1) I2=n11(2) I3=n11(3) O=n29_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n29_LUT4_I1_I0 I1=n11(4) I2=n11(5) I3=n11(6) O=n29_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=n11(6) D=sync_i_LUT4_I3_O_LUT4_I1_O(6) QCK=$iopadmap$clock_c QEN=n2115 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3465.1-3470.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(31) D=n219(15) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(30) D=n219(14) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(21) D=n219(5) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(20) D=n219(4) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(19) D=n219(3) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(18) D=n219(2) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(17) D=n219(1) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(16) D=n219(0) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(15) D=n226(15) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(14) D=n226(14) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(13) D=n226(13) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(12) D=n226(12) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(29) D=n219(13) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(11) D=n226(11) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(10) D=n226(10) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(9) D=n226(9) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(8) D=n226(8) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(7) D=n226(7) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(6) D=n226(6) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n306(5) D=n226(5) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n306(4) D=n226(4) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n306(3) D=n226(3) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n306(2) D=n226(2) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n306(28) D=n219(12) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n306(1) D=n226(1) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n306(0) D=n226(0) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n306(27) D=n219(11) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n306(26) D=n219(10) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n306(25) D=n219(9) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n306(24) D=n219(8) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n306(23) D=n219(7) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n306(22) D=n219(6) QCK=$iopadmap$clock_c QEN=n277_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3769.1-3773.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(31) D=n219(15) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(30) D=n219(14) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(21) D=n219(5) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(20) D=n219(4) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(19) D=n219(3) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(18) D=n219(2) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(17) D=n219(1) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(16) D=n219(0) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(15) D=n226(15) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(14) D=n226(14) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(13) D=n226(13) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(12) D=n226(12) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(29) D=n219(13) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(11) D=n226(11) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(10) D=n226(10) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(9) D=n226(9) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(8) D=n226(8) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(7) D=n226(7) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(6) D=n226(6) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(5) D=n226(5) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(4) D=n226(4) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(3) D=n226(3) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(2) D=n226(2) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(28) D=n219(12) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(1) D=n226(1) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(0) D=n226(0) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(27) D=n219(11) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(26) D=n219(10) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(25) D=n219(9) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(24) D=n219(8) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(23) D=n219(7) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n310(22) D=n219(6) QCK=$iopadmap$clock_c QEN=n290_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3779.1-3783.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n310(15) I1=n306(15) I2=n314 I3=n355(0) O=n314_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(14) I1=n306(14) I2=n314 I3=n355(0) O=n314_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(5) I1=n306(5) I2=n314 I3=n355(0) O=n314_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(4) I1=n306(4) I2=n314 I3=n355(0) O=n314_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(3) I1=n306(3) I2=n314 I3=n355(0) O=n314_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(2) I1=n306(2) I2=n314 I3=n355(0) O=n314_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(1) I1=n306(1) I2=n314 I3=n355(0) O=n314_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n306(0) I1=n310(0) I2=n314 I3=n355(0) O=n314_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n310(13) I1=n306(13) I2=n314 I3=n355(0) O=n314_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(12) I1=n306(12) I2=n314 I3=n355(0) O=n314_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(11) I1=n306(11) I2=n314 I3=n355(0) O=n314_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(10) I1=n306(10) I2=n314 I3=n355(0) O=n314_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(9) I1=n306(9) I2=n314 I3=n355(0) O=n314_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(8) I1=n306(8) I2=n314 I3=n355(0) O=n314_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(7) I1=n306(7) I2=n314 I3=n355(0) O=n314_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(6) I1=n306(6) I2=n314 I3=n355(0) O=n314_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n310(31) I1=n306(31) I2=n355(0) I3=n314 O=n314_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(30) I1=n306(30) I2=n355(0) I3=n314 O=n314_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(21) I1=n306(21) I2=n355(0) I3=n314 O=n314_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(20) I1=n306(20) I2=n355(0) I3=n314 O=n314_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(19) I1=n306(19) I2=n355(0) I3=n314 O=n314_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(18) I1=n306(18) I2=n355(0) I3=n314 O=n314_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(17) I1=n306(17) I2=n355(0) I3=n314 O=n314_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(16) I1=n306(16) I2=n355(0) I3=n314 O=n314_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(29) I1=n306(29) I2=n355(0) I3=n314 O=n314_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(28) I1=n306(28) I2=n355(0) I3=n314 O=n314_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(27) I1=n306(27) I2=n355(0) I3=n314 O=n314_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(26) I1=n306(26) I2=n355(0) I3=n314 O=n314_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(25) I1=n306(25) I2=n355(0) I3=n314 O=n314_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(24) I1=n306(24) I2=n355(0) I3=n314 O=n314_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(23) I1=n306(23) I2=n355(0) I3=n314 O=n314_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n310(22) I1=n306(22) I2=n355(0) I3=n314 O=n314_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n314 D=n314_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3789.1-3794.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n285(0) O=n314_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n322(0) D=n327_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3801.1-3806.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n322(0) I2=n243 I3=n2062 O=n327_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=n343(31) D=n219(15) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(30) D=n219(14) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(21) D=n219(5) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(20) D=n219(4) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(19) D=n219(3) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(18) D=n219(2) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(17) D=n219(1) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(16) D=n219(0) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(15) D=n226(15) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(14) D=n226(14) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(13) D=n226(13) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(12) D=n226(12) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3807.1-3811.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n343(29) D=n219(13) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n347(14) D=n226(14) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(29) D=n219(13) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(10) D=n226(10) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(8) D=n226(8) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(7) D=n226(7) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(6) D=n226(6) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(5) D=n226(5) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(4) D=n226(4) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(3) D=n226(3) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(2) D=n226(2) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(28) D=n219(12) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(1) D=n226(1) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(0) D=n226(0) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n347(27) D=n219(11) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3817.1-3821.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n347(26) D=n219(10) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3817.1-3821.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n347(25) D=n219(9) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3817.1-3821.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n347(24) D=n219(8) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3817.1-3821.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n347(23) D=n219(7) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3817.1-3821.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n347(22) D=n219(6) QCK=$iopadmap$clock_c QEN=n277_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3817.1-3821.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n347(15) I1=n343(15) I2=n351 I3=n355(0) O=n351_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(14) I1=n343(14) I2=n351 I3=n355(0) O=n351_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(5) I1=n343(5) I2=n351 I3=n355(0) O=n351_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(4) I1=n343(4) I2=n351 I3=n355(0) O=n351_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(3) I1=n343(3) I2=n351 I3=n355(0) O=n351_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(2) I1=n343(2) I2=n351 I3=n355(0) O=n351_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(1) I1=n343(1) I2=n351 I3=n355(0) O=n351_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n343(0) I1=n347(0) I2=n351 I3=n355(0) O=n351_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n347(13) I1=n343(13) I2=n351 I3=n355(0) O=n351_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(12) I1=n343(12) I2=n351 I3=n355(0) O=n351_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(11) I1=n343(11) I2=n351 I3=n355(0) O=n351_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(10) I1=n343(10) I2=n351 I3=n355(0) O=n351_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(9) I1=n343(9) I2=n351 I3=n355(0) O=n351_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(8) I1=n343(8) I2=n351 I3=n355(0) O=n351_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(7) I1=n343(7) I2=n351 I3=n355(0) O=n351_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(6) I1=n343(6) I2=n351 I3=n355(0) O=n351_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n347(31) I1=n343(31) I2=n355(0) I3=n351 O=n351_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(30) I1=n343(30) I2=n355(0) I3=n351 O=n351_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(21) I1=n343(21) I2=n355(0) I3=n351 O=n351_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(20) I1=n343(20) I2=n355(0) I3=n351 O=n351_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(19) I1=n343(19) I2=n355(0) I3=n351 O=n351_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(18) I1=n343(18) I2=n355(0) I3=n351 O=n351_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(17) I1=n343(17) I2=n355(0) I3=n351 O=n351_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(16) I1=n343(16) I2=n355(0) I3=n351 O=n351_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(29) I1=n343(29) I2=n355(0) I3=n351 O=n351_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(28) I1=n343(28) I2=n355(0) I3=n351 O=n351_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(27) I1=n343(27) I2=n355(0) I3=n351 O=n351_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(26) I1=n343(26) I2=n355(0) I3=n351 O=n351_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(25) I1=n343(25) I2=n355(0) I3=n351 O=n351_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(24) I1=n343(24) I2=n355(0) I3=n351 O=n351_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(23) I1=n343(23) I2=n355(0) I3=n351 O=n351_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n347(22) I1=n343(22) I2=n355(0) I3=n351 O=n351_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n351 D=n351_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3827.1-3832.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n322(0) O=n351_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n355(0) D=n360_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3833.1-3838.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n295_LUT4_I3_O I3=n360_ff_CQZ_D_LUT4_O_I3 O=n360_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n283(1) I1=n283(0) I2=n360_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n355(0) O=n360_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n283(2) I1=n283(3) I2=n283(4) I3=n283(5) O=n360_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=n371(5) D=n384_LUT4_I3_I2_LUT4_I3_O(5) QCK=$iopadmap$clock_c QEN=n2103 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3839.1-3844.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n371(4) D=n384_LUT4_I3_I2_LUT4_I3_O(4) QCK=$iopadmap$clock_c QEN=n2103 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3839.1-3844.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n371(3) D=n384_LUT4_I3_I2_LUT4_I3_O(3) QCK=$iopadmap$clock_c QEN=n2103 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3839.1-3844.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n371(2) D=n384_LUT4_I3_I2_LUT4_I3_O(2) QCK=$iopadmap$clock_c QEN=n2103 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3839.1-3844.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n371(1) D=n384_LUT4_I3_I2_LUT4_I3_O(1) QCK=$iopadmap$clock_c QEN=n2103 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3839.1-3844.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n375(0) I2=n371(6) I3=n384_LUT4_I3_I2 O=n2103_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt ff CQZ=n375(0) D=n384_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3845.1-3850.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n371(6) I2=n384_LUT4_I3_I2 I3=n384 O=n472_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=n1019 I1=n295_LUT4_I3_O I2=n371(6) I3=n384_LUT4_I3_I2 O=n384_LUT4_I3_I2_LUT4_I3_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n384_LUT4_I3_I2_LUT4_O_I3 I1=n371(4) I2=n371(5) I3=n295_LUT4_I3_O O=n384_LUT4_I3_I2_LUT4_I3_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1019 I1=n295_LUT4_I3_O I2=n371(4) I3=n384_LUT4_I3_I2_LUT4_O_I3 O=n384_LUT4_I3_I2_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n295_LUT4_I3_O I3=n384_LUT4_I3_I2_LUT4_I3_O_LUT4_O_2_I3 O=n384_LUT4_I3_I2_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n371(0) I1=n371(1) I2=n371(2) I3=n371(3) O=n384_LUT4_I3_I2_LUT4_I3_O_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n371(0) I1=n371(1) I2=n371(2) I3=n295_LUT4_I3_O O=n384_LUT4_I3_I2_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1019 I1=n295_LUT4_I3_O I2=n371(1) I3=n371(0) O=n384_LUT4_I3_I2_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n295_LUT4_I3_O I3=n371(0) O=n384_LUT4_I3_I2_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n371(5) I2=n371(4) I3=n384_LUT4_I3_I2_LUT4_O_I3 O=n384_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n371(0) I1=n371(1) I2=n371(2) I3=n371(3) O=n384_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=n384 D=n384_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3851.1-3856.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1019 I3=n371(6) O=n417_ff_CQZ_7_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=n371(6) D=n384_LUT4_I3_I2_LUT4_I3_O(6) QCK=$iopadmap$clock_c QEN=n2103 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3839.1-3844.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(15) D=n390_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(14) D=n390_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(5) D=n390_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(4) D=n390_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(3) D=n390_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(2) D=n390_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(1) D=n390_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(0) D=n390_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(13) D=n390_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(12) D=n390_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(11) D=n390_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(10) D=n390_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(9) D=n390_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(8) D=n390_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(7) D=n390_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n390(6) D=n390_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3857.1-3862.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_O I3=n314_LUT4_I2_O O=n390_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_1_O I3=n314_LUT4_I2_1_O O=n390_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_10_O I3=n314_LUT4_I2_10_O O=n390_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_11_O I3=n314_LUT4_I2_11_O O=n390_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_12_O I3=n314_LUT4_I2_12_O O=n390_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_13_O I3=n314_LUT4_I2_13_O O=n390_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_14_O I3=n314_LUT4_I2_14_O O=n390_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_15_O I3=n314_LUT4_I2_15_O O=n390_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_2_O I3=n314_LUT4_I2_2_O O=n390_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_3_O I3=n314_LUT4_I2_3_O O=n390_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_4_O I3=n314_LUT4_I2_4_O O=n390_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_5_O I3=n314_LUT4_I2_5_O O=n390_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_6_O I3=n314_LUT4_I2_6_O O=n390_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_7_O I3=n314_LUT4_I2_7_O O=n390_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_8_O I3=n314_LUT4_I2_8_O O=n390_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n314_LUT4_I3_9_O I3=n314_LUT4_I2_9_O O=n390_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=n396(15) D=n396_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(14) D=n396_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(5) D=n396_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(4) D=n396_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(3) D=n396_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(2) D=n396_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(1) D=n396_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(0) D=n396_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(13) D=n396_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(12) D=n396_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(11) D=n396_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(10) D=n396_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(9) D=n396_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(8) D=n396_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(7) D=n396_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n396(6) D=n396_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3863.1-3868.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_O I3=n351_LUT4_I2_O O=n396_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_1_O I3=n351_LUT4_I2_1_O O=n396_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_10_O I3=n351_LUT4_I2_10_O O=n396_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_11_O I3=n351_LUT4_I2_11_O O=n396_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_12_O I3=n351_LUT4_I2_12_O O=n396_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_13_O I3=n351_LUT4_I2_13_O O=n396_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_14_O I3=n351_LUT4_I2_14_O O=n396_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_15_O I3=n351_LUT4_I2_15_O O=n396_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_2_O I3=n351_LUT4_I2_2_O O=n396_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_3_O I3=n351_LUT4_I2_3_O O=n396_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_4_O I3=n351_LUT4_I2_4_O O=n396_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_5_O I3=n351_LUT4_I2_5_O O=n396_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_6_O I3=n351_LUT4_I2_6_O O=n396_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_7_O I3=n351_LUT4_I2_7_O O=n396_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_8_O I3=n351_LUT4_I2_8_O O=n396_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n351_LUT4_I3_9_O I3=n351_LUT4_I2_9_O O=n396_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=n39(5) D=n26_LUT4_I2_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3483.1-3488.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n39(4) D=n26_LUT4_I2_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3483.1-3488.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n39(3) D=n26_LUT4_I2_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3483.1-3488.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n39(2) D=n26_LUT4_I2_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3483.1-3488.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n39(1) D=n26_LUT4_I2_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3483.1-3488.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n39(0) D=n26_LUT4_I2_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3483.1-3488.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n402(7) I3=n2062 O=n406_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n402(6) I3=n2062 O=n406_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n402(5) I3=n2062 O=n406_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n402(4) I3=n2062 O=n406_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n402(3) I3=n2062 O=n406_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n402(2) I3=n2062 O=n406_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n402(1) I3=n2062 O=n406_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n402(0) I3=n2062 O=n406_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n402(7) D=n402_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3869.1-3874.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n402(6) D=n402_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3869.1-3874.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n402(5) D=n402_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3869.1-3874.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n402(4) D=n402_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3869.1-3874.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n402(3) D=n402_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3869.1-3874.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n402(2) D=n402_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3869.1-3874.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n402(1) D=n402_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3869.1-3874.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n402(0) D=n402_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3869.1-3874.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(15) I3=n2062 O=n402_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(14) I3=n2062 O=n402_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(13) I3=n2062 O=n402_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(12) I3=n2062 O=n402_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(11) I3=n2062 O=n402_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(10) I3=n2062 O=n402_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(9) I3=n2062 O=n402_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(8) I3=n2062 O=n402_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n406(7) D=n406_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3875.1-3880.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n406(6) D=n406_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3875.1-3880.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n406(5) D=n406_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3875.1-3880.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n406(4) D=n406_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3875.1-3880.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n406(3) D=n406_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3875.1-3880.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n406(2) D=n406_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3875.1-3880.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n406(1) D=n406_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3875.1-3880.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n406(0) D=n406_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3875.1-3880.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n410(7) I3=n2062 O=n414_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n410(6) I3=n2062 O=n414_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n410(5) I3=n2062 O=n414_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n410(4) I3=n2062 O=n414_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n410(3) I3=n2062 O=n414_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n410(2) I3=n2062 O=n414_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n410(1) I3=n2062 O=n414_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n410(0) I3=n2062 O=n414_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n410(7) D=n410_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3881.1-3886.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n410(6) D=n410_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3881.1-3886.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n410(5) D=n410_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3881.1-3886.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n410(4) D=n410_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3881.1-3886.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n410(3) D=n410_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3881.1-3886.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n410(2) D=n410_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3881.1-3886.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n410(1) D=n410_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3881.1-3886.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n410(0) D=n410_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3881.1-3886.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(7) I3=n2062 O=n410_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(6) I3=n2062 O=n410_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(5) I3=n2062 O=n410_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(4) I3=n2062 O=n410_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(3) I3=n2062 O=n410_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(2) I3=n2062 O=n410_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(1) I3=n2062 O=n410_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n390(0) I3=n2062 O=n410_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n414(7) D=n414_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3887.1-3892.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n414(6) D=n414_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3887.1-3892.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n414(5) D=n414_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3887.1-3892.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n414(4) D=n414_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3887.1-3892.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n414(3) D=n414_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3887.1-3892.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n414(2) D=n414_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3887.1-3892.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n414(1) D=n414_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3887.1-3892.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n414(0) D=n414_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3887.1-3892.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(15) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(14) D=n417_ff_CQZ_7_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(5) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(4) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(3) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(2) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(1) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(0) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(13) D=n417_ff_CQZ_7_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(12) D=n417_ff_CQZ_7_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(11) D=n417_ff_CQZ_7_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(10) D=n417_ff_CQZ_7_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(9) D=n417_ff_CQZ_7_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(8) D=n417_ff_CQZ_7_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(7) D=n371(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n417(6) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3893.1-3898.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n425(7) D=n425_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3899.1-3904.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n425(6) D=n425_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3899.1-3904.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n425(5) D=n425_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3899.1-3904.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n425(4) D=n425_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3899.1-3904.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n425(3) D=n425_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3899.1-3904.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n425(2) D=n425_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3899.1-3904.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n425(1) D=n425_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3899.1-3904.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n425(0) D=n425_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3899.1-3904.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n425_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_1_I0 I1=n425_ff_CQZ_D_LUT4_O_1_I1 I2=n2062 I3=n425_ff_CQZ_D_LUT4_O_1_I3 O=n425_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_3_I1 I1=n425_ff_CQZ_D_LUT4_O_3_I3 I2=n425_ff_CQZ_D_LUT4_O_3_I2 I3=n425_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I2=n425_ff_CQZ_D_LUT4_O_2_I3 I3=n425_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 I2=n396(15) I3=n417(14) O=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(14) I3=n417(15) O=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n417(14) I1=n396(15) I2=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 I1=n396(15) I2=n417(13) I3=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n396(13) I2=n417(14) I3=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I2=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n417(14) I1=n396(14) I2=n417(15) I3=n396(15) O=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n2062 I1=n425_ff_CQZ_D_LUT4_O_2_I1 I2=n425_ff_CQZ_D_LUT4_O_2_I2 I3=n425_ff_CQZ_D_LUT4_O_2_I3 O=n425_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I2 I2=n425_ff_CQZ_D_LUT4_O_3_I3 I3=n425_ff_CQZ_D_LUT4_O_3_I1 O=n425_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_2_I3 I3=n425_ff_CQZ_D_LUT4_O_2_I2 O=n425_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 I2=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I3=n425_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100001
+.subckt LUT4 I0=n417(13) I1=n396(15) I2=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n2062 I1=n425_ff_CQZ_D_LUT4_O_3_I1 I2=n425_ff_CQZ_D_LUT4_O_3_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I3 O=n425_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I1=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I3=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n396(15) I2=n417(10) I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n417(12) I1=n396(13) I2=n417(11) I3=n396(14) O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(12) I1=n417(11) I2=n396(13) I3=n396(14) O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n417(12) I1=n396(14) I2=n417(11) I3=n396(15) O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=n396(13) I3=n417(13) O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n396(12) I2=n417(13) I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n417(15) I1=n417(14) I2=n396(10) I3=n396(11) O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n417(12) I1=n417(11) I2=n396(14) I3=n396(15) O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n417(12) I1=n396(15) I2=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I0 I3=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n417(13) I1=n396(15) I2=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=n396(14) I2=n417(13) I3=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n417(15) I1=n417(14) I2=n396(12) I3=n396(13) O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n417(15) I1=n396(13) I2=n417(14) I3=n396(14) O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n417(12) I3=n396(15) O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=n396(13) I2=n417(13) I3=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n417(15) I1=n396(11) I2=n417(14) I3=n396(12) O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(15) I1=n417(14) I2=n396(11) I3=n396(12) O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n396(14) I3=n417(13) O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n417(15) I1=n396(12) I2=n417(14) I3=n396(13) O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n425_ff_CQZ_D_LUT4_O_4_I3 O=n425_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_5_I1 I1=n425_ff_CQZ_D_LUT4_O_5_I3 I2=n425_ff_CQZ_D_LUT4_O_5_I2 I3=n425_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n425_ff_CQZ_D_LUT4_O_5_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I3 O=n425_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_5_I1 I1=n425_ff_CQZ_D_LUT4_O_5_I3 I2=n425_ff_CQZ_D_LUT4_O_5_I2 I3=n425_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n425_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n396(15) I3=n417(8) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(12) I3=n417(10) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n417(12) I1=n396(10) I2=n417(11) I3=n396(11) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(14) I1=n396(8) I2=n417(13) I3=n396(9) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(13) I1=n396(10) I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n417(14) I1=n417(13) I2=n396(9) I3=n396(8) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n417(15) I1=n396(8) I2=n417(14) I3=n396(9) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n396(13) I3=n417(10) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n417(12) I1=n396(11) I2=n417(11) I3=n396(12) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(15) I1=n417(8) I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(14) I3=n417(9) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(11) I3=n417(11) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n396(14) I3=n417(10) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n396(11) I3=n417(13) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n417(15) I1=n396(9) I2=n417(14) I3=n396(10) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n396(10) I2=n417(13) I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n417(15) I1=n417(14) I2=n396(9) I3=n396(8) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n396(10) I3=n417(13) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I2=n396(15) I3=n417(9) O=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n396(14) I2=n417(10) I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n417(12) I1=n396(12) I2=n417(11) I3=n396(13) O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(12) I1=n417(11) I2=n396(12) I3=n396(13) O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n396(15) I3=n417(10) O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n396(12) I3=n417(13) O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n417(15) I1=n396(10) I2=n417(14) I3=n396(11) O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=n396(11) I2=n417(13) I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n417(15) I1=n417(14) I2=n396(9) I3=n396(10) O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n396(15) I2=n417(9) I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n396(13) I2=n417(10) I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n396(12) I2=n417(12) I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n425_ff_CQZ_D_LUT4_O_6_I3 O=n425_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(9) I3=n417(12) O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(14) I3=n417(8) O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(13) I3=n417(9) O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n417(13) I3=n396(8) O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(11) I3=n417(10) O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n417(12) I1=n396(9) I2=n417(11) I3=n396(10) O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n425_ff_CQZ_D_LUT4_O_7_I3 O=n425_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000001011
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n417(8) I1=n396(12) I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n417(11) I1=n417(10) I2=n396(9) I3=n396(8) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(11) I3=n417(9) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n417(12) I1=n396(8) I2=n417(11) I3=n396(9) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(10) I3=n417(10) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n396(10) I2=n417(8) I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n396(8) I2=n417(10) I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n417(9) I1=n396(9) I2=n417(8) I3=n396(10) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(9) I1=n396(9) I2=n417(8) I3=n396(10) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n417(9) I1=n396(9) I2=n417(8) I3=n396(8) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n417(10) I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n417(9) I1=n396(10) I2=n417(8) I3=n396(11) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(8) I3=n417(11) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(9) I3=n417(10) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n396(13) I1=n417(8) I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(12) I3=n417(9) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n417(8) I1=n396(13) I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=n417(8) I3=n396(12) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n417(8) I1=n396(13) I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(9) I3=n417(11) O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n417(13) I1=n396(8) I2=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n425_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n425_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I3=n425_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 O=n425_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=n431(7) D=n431_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3905.1-3910.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n431(6) D=n431_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3905.1-3910.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n431(5) D=n431_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3905.1-3910.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n431(4) D=n431_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3905.1-3910.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n431(3) D=n431_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3905.1-3910.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n431(2) D=n431_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3905.1-3910.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n431(1) D=n431_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3905.1-3910.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n431(0) D=n431_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3905.1-3910.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n431_ff_CQZ_D_LUT4_O_I3 O=n431_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000001
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_1_I1 I2=n431_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n431_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_2_I2 I2=n431_ff_CQZ_D_LUT4_O_2_I3 I3=n431_ff_CQZ_D_LUT4_O_2_I1 O=n431_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n431_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n431_ff_CQZ_D_LUT4_O_2_I1 I2=n431_ff_CQZ_D_LUT4_O_2_I2 I3=n431_ff_CQZ_D_LUT4_O_2_I3 O=n431_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n396(4) I1=n396(5) I2=n417(5) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(5) I1=n417(5) I2=n396(6) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(7) I1=n417(3) I2=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n417(6) I2=n396(3) I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(5) I1=n396(6) I2=n417(5) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n431_ff_CQZ_D_LUT4_O_3_I3 O=n431_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n431_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n417(2) I2=n396(7) I3=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I3=n431_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n431_ff_CQZ_D_LUT4_O_4_I3 O=n431_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_5_I1 I1=n431_ff_CQZ_D_LUT4_O_5_I3 I2=n431_ff_CQZ_D_LUT4_O_5_I2 I3=n431_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n2062 I1=n431_ff_CQZ_D_LUT4_O_5_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I3 O=n431_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_5_I1 I1=n431_ff_CQZ_D_LUT4_O_5_I3 I2=n431_ff_CQZ_D_LUT4_O_5_I2 I3=n431_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n431_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n417(2) I3=n396(5) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(0) I3=n396(6) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(1) I1=n417(5) I2=n396(2) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(0) I1=n417(6) I2=n396(3) I3=n417(3) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(1) I1=n417(6) I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n396(0) I1=n396(3) I2=n417(6) I3=n417(3) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n396(0) I1=n417(7) I2=n396(4) I3=n417(3) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n417(0) I3=n396(7) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n396(2) I1=n417(5) I2=n396(3) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(2) I1=n396(5) I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(1) I3=n396(6) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(4) I3=n396(2) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n417(6) I3=n396(1) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n396(7) I1=n417(1) I2=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(3) I1=n417(5) I2=n396(4) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n417(6) I3=n396(2) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n396(1) I1=n417(7) I2=n396(5) I3=n417(3) O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n417(6) I2=n396(1) I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n417(7) I2=n396(4) I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n396(7) I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n417(0) I2=n396(7) I3=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n417(5) I2=n396(3) I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(2) I3=n396(6) O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n417(2) I3=n396(7) O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n396(3) I1=n396(4) I2=n417(5) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(4) I1=n417(5) I2=n396(5) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n417(6) I3=n396(3) O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n396(2) I1=n417(7) I2=n396(6) I3=n417(3) O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1019 I1=n417(6) I2=n396(2) I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n431_ff_CQZ_D_LUT4_O_6_I3 O=n431_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n417(1) I1=n396(5) I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n431_ff_CQZ_D_LUT4_O_7_I3 O=n431_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000000000001
+.subckt LUT4 I0=n396(3) I1=n417(0) I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(3) I3=n396(0) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=n396(0) I1=n396(1) I2=n417(2) I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n417(0) I2=n396(2) I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n396(0) I1=n417(2) I2=n396(1) I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(0) I1=n396(1) I2=n417(0) I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I2=n417(0) I3=n396(3) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n396(1) I1=n417(2) I2=n396(2) I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(1) I1=n396(2) I2=n417(2) I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n417(1) I2=n396(2) I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n396(4) I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n396(0) I1=n396(4) I2=n417(0) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(2) I3=n396(3) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n396(4) I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n396(2) I1=n417(3) I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n396(2) I3=n417(3) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(0) I3=n396(5) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(0) I1=n417(5) I2=n396(1) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n396(5) I2=n417(1) I3=n417(0) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n396(1) I1=n417(4) I2=n396(5) I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(2) I3=n396(4) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n396(0) I1=n396(3) I2=n417(0) I3=n417(3) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n396(2) I1=n417(2) I2=n396(3) I3=n417(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(3) I3=n396(1) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(0) I1=n417(4) I2=n396(4) I3=n417(0) O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n431_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n431_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I2=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I3=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_2_I1 I1=n431_ff_CQZ_D_LUT4_O_2_I3 I2=n431_ff_CQZ_D_LUT4_O_2_I2 I3=n431_ff_CQZ_D_LUT4_O_1_I2 O=n431_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n431_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=n431_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 O=n431_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n431_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001001001101
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n396(6) I1=n396(7) I2=n417(5) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=n417(5) I3=n396(7) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n396(6) I1=n417(5) I2=n396(7) I3=n417(4) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(4) I1=n417(7) I2=n396(5) I3=n417(6) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=n396(7) I3=n417(3) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(7) I3=n396(3) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n417(5) I2=n396(7) I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n396(4) I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=n396(6) I3=n417(6) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(7) I3=n396(5) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n396(6) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(6) I3=n396(4) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(5) I1=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n417(6) I3=n396(7) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110001001100
+.subckt LUT4 I0=n1019 I1=n417(3) I2=n396(2) I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(7) I3=n396(6) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(7) I3=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n396(5) I1=n396(6) I2=n417(6) I3=n396(7) O=n431_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000001111111
+.subckt ff CQZ=n436(7) D=n436_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3911.1-3916.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n436(6) D=n436_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3911.1-3916.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n436(5) D=n436_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3911.1-3916.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n436(4) D=n436_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3911.1-3916.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n436(3) D=n436_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3911.1-3916.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n436(2) D=n436_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3911.1-3916.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n436(1) D=n436_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3911.1-3916.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n436(0) D=n436_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3911.1-3916.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n436_ff_CQZ_D_LUT4_O_I1 I2=n431(7) I3=n425(7) O=n436_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n436_ff_CQZ_D_LUT4_O_1_I1 I2=n431(6) I3=n425(6) O=n436_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n425(5) I2=n431(5) I3=n436_ff_CQZ_D_LUT4_O_2_I1 O=n436_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n436_ff_CQZ_D_LUT4_O_2_I1 I2=n431(5) I3=n425(5) O=n436_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n425(4) I2=n431(4) I3=n436_ff_CQZ_D_LUT4_O_3_I1 O=n436_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n436_ff_CQZ_D_LUT4_O_3_I1 I2=n431(4) I3=n425(4) O=n436_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n425(3) I2=n431(3) I3=n436_ff_CQZ_D_LUT4_O_4_I1 O=n436_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n436_ff_CQZ_D_LUT4_O_4_I1 I2=n431(3) I3=n425(3) O=n436_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n425(2) I2=n431(2) I3=n436_ff_CQZ_D_LUT4_O_5_I1 O=n436_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n436_ff_CQZ_D_LUT4_O_5_I1 I2=n431(2) I3=n425(2) O=n436_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n431(1) I1=n425(1) I2=n425(0) I3=n431(0) O=n436_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n436_ff_CQZ_D_LUT4_O_6_I3 O=n436_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n425(0) I1=n431(0) I2=n431(1) I3=n425(1) O=n436_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n425(0) I2=n431(0) I3=n2062 O=n436_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n425(6) I2=n431(6) I3=n436_ff_CQZ_D_LUT4_O_1_I1 O=n436_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=n442(7) D=n442_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3917.1-3922.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n442(6) D=n442_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3917.1-3922.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n442(5) D=n442_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3917.1-3922.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n442(4) D=n442_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3917.1-3922.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n442(3) D=n442_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3917.1-3922.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n442(2) D=n442_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3917.1-3922.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n442(1) D=n442_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3917.1-3922.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n442(0) D=n442_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3917.1-3922.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n442_ff_CQZ_D_LUT4_O_I3 O=n442_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_1_I1 I2=n442_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n442_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I3=n442_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n442_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_2_I3 I2=n442_ff_CQZ_D_LUT4_O_2_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I1 O=n442_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n442_ff_CQZ_D_LUT4_O_2_I1 I2=n442_ff_CQZ_D_LUT4_O_2_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I3 O=n442_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n396(14) I3=n417(3) O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(4) I3=n396(13) O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(2) I3=n396(15) O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(14) I1=n417(4) I2=n396(15) I3=n417(3) O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(11) I1=n417(7) I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n396(11) I3=n417(6) O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(14) I1=n396(15) I2=n417(4) I3=n417(3) O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n396(15) I1=n417(4) I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n442_ff_CQZ_D_LUT4_O_3_I3 O=n442_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 O=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n442_ff_CQZ_D_LUT4_O_4_I3 O=n442_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_5_I1 I1=n442_ff_CQZ_D_LUT4_O_5_I3 I2=n442_ff_CQZ_D_LUT4_O_5_I2 I3=n442_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 O=n442_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n442_ff_CQZ_D_LUT4_O_5_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I3 O=n442_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_5_I1 I1=n442_ff_CQZ_D_LUT4_O_5_I3 I2=n442_ff_CQZ_D_LUT4_O_5_I2 I3=n442_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n442_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n417(0) I3=n396(15) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(2) I3=n396(12) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(10) I1=n417(4) I2=n396(11) I3=n417(3) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(9) I1=n417(5) I2=n396(8) I3=n417(6) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(10) I1=n417(5) I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n396(9) I1=n396(8) I2=n417(6) I3=n417(5) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n396(9) I1=n417(6) I2=n396(8) I3=n417(7) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n417(2) I3=n396(13) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n396(11) I1=n417(4) I2=n396(12) I3=n417(3) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(0) I1=n396(15) I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(1) I3=n396(14) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(13) I1=n417(3) I2=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n417(5) I3=n396(11) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n396(9) I1=n417(7) I2=n396(10) I3=n417(6) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n417(5) I2=n396(10) I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n396(9) I1=n396(8) I2=n417(7) I3=n417(6) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n417(5) I3=n396(10) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I2=n417(1) I3=n396(15) O=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n396(13) I3=n417(3) O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(2) I3=n396(14) O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(14) I1=n417(3) I2=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=n442_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n396(11) I1=n417(6) I2=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(7) I3=n396(10) O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(5) I3=n396(12) O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=n417(5) I2=n396(11) I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n396(9) I1=n396(10) I2=n417(7) I3=n417(6) O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n417(1) I2=n396(15) I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1019 I1=n417(2) I2=n396(13) I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(4) I3=n396(12) O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(3) I3=n396(11) O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n442_ff_CQZ_D_LUT4_O_6_I3 O=n442_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(1) I3=n396(13) O=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n442_ff_CQZ_D_LUT4_O_7_I3 O=n442_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110001110
+.subckt LUT4 I0=n396(9) I1=n417(2) I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n417(2) I2=n396(8) I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n396(9) I1=n396(10) I2=n417(0) I3=n417(1) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n417(2) I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n396(9) I1=n417(0) I2=n396(8) I3=n417(1) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n396(9) I1=n417(1) I2=n396(10) I3=n417(0) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=n1019 I1=n417(0) I2=n396(10) I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n396(9) I1=n417(2) I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n396(10) I1=n417(1) I2=n396(11) I3=n417(0) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(3) I3=n396(8) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n417(0) I1=n396(13) I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(1) I3=n396(12) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=n396(8) I3=n417(5) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(4) I3=n396(9) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(0) I3=n396(14) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(13) I1=n417(0) I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n396(12) I1=n417(0) I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n396(12) I3=n417(0) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n396(9) I1=n396(8) I2=n417(3) I3=n417(2) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(1) I3=n396(11) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(13) I1=n417(0) I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(2) I3=n396(10) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(3) I3=n396(9) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(9) I1=n417(3) I2=n396(8) I3=n417(4) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(8) I1=n417(5) I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(2) I3=n396(11) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(9) I1=n417(4) I2=n396(10) I3=n417(3) O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n442_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n442_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_2_I1 I1=n442_ff_CQZ_D_LUT4_O_2_I2 I2=n442_ff_CQZ_D_LUT4_O_2_I3 I3=n442_ff_CQZ_D_LUT4_O_1_I1 O=n442_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=n442_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n396(15) I3=n417(4) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n396(11) I3=n417(7) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(6) I3=n396(12) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(5) I3=n396(13) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n417(5) I3=n396(14) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(5) I3=n396(15) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n417(7) I3=n396(13) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n417(5) I2=n396(14) I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n396(12) I1=n417(7) I2=n396(13) I3=n417(6) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n417(7) I2=n396(13) I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n396(15) I1=n417(6) I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n396(13) I3=n417(7) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(7) I3=n396(14) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n396(15) I2=n417(7) I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(6) I3=n396(14) O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(15) I1=n417(6) I2=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n442_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=n448(7) D=n448_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3923.1-3928.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n448(6) D=n448_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3923.1-3928.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n448(5) D=n448_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3923.1-3928.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n448(4) D=n448_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3923.1-3928.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n448(3) D=n448_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3923.1-3928.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n448(2) D=n448_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3923.1-3928.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n448(1) D=n448_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3923.1-3928.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n448(0) D=n448_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3923.1-3928.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n448_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_1_I0 I1=n448_ff_CQZ_D_LUT4_O_1_I1 I2=n2062 I3=n448_ff_CQZ_D_LUT4_O_1_I3 O=n448_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_2_I1 I1=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n396(7) I3=n417(12) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n417(15) I3=n396(3) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(14) I3=n396(4) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(13) I3=n396(5) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n417(13) I3=n396(6) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(13) I3=n396(7) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I0 I2=n396(5) I3=n417(15) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n417(13) I2=n396(6) I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n417(15) I1=n396(4) I2=n396(5) I3=n417(14) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n396(5) I2=n417(15) I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n396(7) I1=n417(14) I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1 I2=n417(15) I3=n396(5) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(6) I3=n417(15) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I0 I1=n417(15) I2=n396(7) I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(14) I3=n396(6) O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(7) I1=n417(14) I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_2_I1 I2=n448_ff_CQZ_D_LUT4_O_2_I2 I3=n2062 O=n448_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n448_ff_CQZ_D_LUT4_O_3_I3 O=n448_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n448_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n448_ff_CQZ_D_LUT4_O_4_I3 O=n448_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I1 I1=n448_ff_CQZ_D_LUT4_O_5_I3 I2=n448_ff_CQZ_D_LUT4_O_5_I2 I3=n448_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I3=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n448_ff_CQZ_D_LUT4_O_5_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I3 O=n448_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I1 I1=n448_ff_CQZ_D_LUT4_O_5_I3 I2=n448_ff_CQZ_D_LUT4_O_5_I2 I3=n448_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n448_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n417(8) I3=n396(7) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(10) I3=n396(4) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(2) I1=n417(12) I2=n396(3) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(0) I1=n417(14) I2=n396(1) I3=n417(13) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(0) I1=n417(15) I2=n396(1) I3=n417(14) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(13) I3=n396(2) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(0) I1=n396(1) I2=n417(14) I3=n417(13) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n417(10) I3=n396(5) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n396(3) I1=n417(12) I2=n396(4) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(8) I1=n396(7) I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(9) I3=n396(6) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(11) I3=n396(3) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n417(10) I3=n396(6) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n396(2) I1=n417(14) I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(1) I3=n417(15) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(13) I3=n396(3) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n396(1) I3=n417(14) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(15) I3=n396(0) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I2=n417(9) I3=n396(7) O=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n417(10) I2=n396(6) I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n396(4) I1=n417(12) I2=n396(5) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(4) I1=n396(5) I2=n417(12) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n417(10) I3=n396(7) O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n396(3) I1=n417(14) I2=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n396(2) I3=n417(15) O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(13) I3=n396(4) O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n396(2) I3=n417(14) O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n417(9) I2=n396(7) I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n417(10) I2=n396(5) I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n417(12) I2=n396(4) I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n448_ff_CQZ_D_LUT4_O_6_I3 O=n448_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(12) I3=n396(1) O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(8) I3=n396(6) O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(9) I3=n396(5) O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n396(0) I3=n417(13) O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(10) I3=n396(3) O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(1) I1=n417(12) I2=n396(2) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n448_ff_CQZ_D_LUT4_O_7_I3 O=n448_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000001011
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n396(2) I1=n417(10) I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000000100000000
+.subckt LUT4 I0=n396(0) I1=n396(1) I2=n417(9) I3=n417(8) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n396(4) I1=n417(8) I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n396(0) I1=n396(1) I2=n417(11) I3=n417(10) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(9) I3=n396(3) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n396(0) I1=n417(12) I2=n396(1) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(10) I3=n396(2) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n417(8) I2=n396(2) I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n396(1) I1=n417(10) I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n396(2) I1=n417(9) I2=n396(3) I3=n417(8) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(11) I3=n396(0) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111101110
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=n417(10) I2=n396(0) I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n396(1) I1=n417(9) I2=n396(2) I3=n417(8) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(1) I1=n396(2) I2=n417(9) I3=n417(8) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n396(1) I1=n417(10) I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n417(8) I1=n396(5) I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(9) I3=n396(4) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n396(5) I1=n417(8) I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n396(4) I3=n417(8) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n396(5) I1=n417(8) I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n417(11) I3=n396(1) O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n396(0) I1=n417(13) I2=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n448_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n448_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_2_I1 I1=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n417(10) I2=n396(7) I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n396(5) I1=n417(12) I2=n396(6) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n396(5) I1=n396(6) I2=n417(12) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(6) I1=n417(12) I2=n396(7) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n417(15) I1=n396(3) I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n396(3) I3=n417(14) O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n396(6) I1=n396(7) I2=n417(12) I3=n417(11) O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n396(7) I1=n417(12) I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n448_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 I2=n448_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I3=n448_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 O=n448_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt ff CQZ=n453(7) D=n453_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3929.1-3934.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n453(6) D=n453_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3929.1-3934.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n453(5) D=n453_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3929.1-3934.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n453(4) D=n453_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3929.1-3934.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n453(3) D=n453_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3929.1-3934.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n453(2) D=n453_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3929.1-3934.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n453(1) D=n453_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3929.1-3934.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n453(0) D=n453_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3929.1-3934.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n453_ff_CQZ_D_LUT4_O_I1 I2=n442(7) I3=n448(7) O=n453_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n453_ff_CQZ_D_LUT4_O_1_I1 I2=n442(6) I3=n448(6) O=n453_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n448(5) I2=n442(5) I3=n453_ff_CQZ_D_LUT4_O_2_I1 O=n453_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n453_ff_CQZ_D_LUT4_O_2_I1 I2=n442(5) I3=n448(5) O=n453_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n448(4) I2=n442(4) I3=n453_ff_CQZ_D_LUT4_O_3_I1 O=n453_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n453_ff_CQZ_D_LUT4_O_3_I1 I2=n442(4) I3=n448(4) O=n453_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n448(3) I2=n442(3) I3=n453_ff_CQZ_D_LUT4_O_4_I1 O=n453_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n453_ff_CQZ_D_LUT4_O_4_I1 I2=n442(3) I3=n448(3) O=n453_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n448(2) I2=n442(2) I3=n453_ff_CQZ_D_LUT4_O_5_I1 O=n453_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n453_ff_CQZ_D_LUT4_O_5_I1 I2=n442(2) I3=n448(2) O=n453_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n442(1) I1=n448(1) I2=n442(0) I3=n448(0) O=n453_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n453_ff_CQZ_D_LUT4_O_6_I3 O=n453_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n442(0) I1=n448(0) I2=n442(1) I3=n448(1) O=n453_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n448(0) I2=n442(0) I3=n2062 O=n453_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n448(6) I2=n442(6) I3=n453_ff_CQZ_D_LUT4_O_1_I1 O=n453_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n460(15) D=n460_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(14) D=n460_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(5) D=n460_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(4) D=n460_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(3) D=n460_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(2) D=n460_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(1) D=n460_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(0) D=n460_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(13) D=n460_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(12) D=n460_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(11) D=n460_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(10) D=n460_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(9) D=n460_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(8) D=n460_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(7) D=n460_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n460(6) D=n460_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3935.1-3940.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_I1 I2=n436(7) I3=n406(7) O=n460_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_1_I1 I2=n436(6) I3=n406(6) O=n460_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_10_I1 I2=n453(4) I3=n414(4) O=n460_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n414(3) I2=n453(3) I3=n460_ff_CQZ_D_LUT4_O_11_I1 O=n460_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_11_I1 I2=n453(3) I3=n414(3) O=n460_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n414(2) I2=n453(2) I3=n460_ff_CQZ_D_LUT4_O_12_I1 O=n460_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_12_I1 I2=n453(2) I3=n414(2) O=n460_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n453(1) I1=n414(1) I2=n414(0) I3=n453(0) O=n460_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n460_ff_CQZ_D_LUT4_O_13_I3 O=n460_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n453(0) I1=n414(0) I2=n453(1) I3=n414(1) O=n460_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n406(0) I2=n436(0) I3=n2062 O=n460_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n414(0) I2=n453(0) I3=n2062 O=n460_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n406(5) I2=n436(5) I3=n460_ff_CQZ_D_LUT4_O_2_I1 O=n460_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_2_I1 I2=n436(5) I3=n406(5) O=n460_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n406(4) I2=n436(4) I3=n460_ff_CQZ_D_LUT4_O_3_I1 O=n460_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_3_I1 I2=n436(4) I3=n406(4) O=n460_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n406(3) I2=n436(3) I3=n460_ff_CQZ_D_LUT4_O_4_I1 O=n460_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_4_I1 I2=n436(3) I3=n406(3) O=n460_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n406(2) I2=n436(2) I3=n460_ff_CQZ_D_LUT4_O_5_I1 O=n460_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_5_I1 I2=n436(2) I3=n406(2) O=n460_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n436(1) I1=n406(1) I2=n406(0) I3=n436(0) O=n460_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n460_ff_CQZ_D_LUT4_O_6_I3 O=n460_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n436(0) I1=n406(0) I2=n436(1) I3=n406(1) O=n460_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_7_I1 I2=n453(7) I3=n414(7) O=n460_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n414(6) I2=n453(6) I3=n460_ff_CQZ_D_LUT4_O_8_I1 O=n460_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_8_I1 I2=n453(6) I3=n414(6) O=n460_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n414(5) I2=n453(5) I3=n460_ff_CQZ_D_LUT4_O_9_I1 O=n460_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n460_ff_CQZ_D_LUT4_O_9_I1 I2=n453(5) I3=n414(5) O=n460_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n414(4) I2=n453(4) I3=n460_ff_CQZ_D_LUT4_O_10_I1 O=n460_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n406(6) I2=n436(6) I3=n460_ff_CQZ_D_LUT4_O_1_I1 O=n460_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n467(15) D=n467_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(14) D=n467_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(5) D=n467_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(4) D=n467_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(3) D=n467_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(2) D=n467_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(1) D=n467_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(0) D=n460_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(13) D=n467_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(12) D=n467_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(11) D=n467_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(10) D=n467_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(9) D=n467_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(8) D=n460_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(7) D=n467_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n467(6) D=n467_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3941.1-3946.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_I1 I2=n436(7) I3=n406(7) O=n467_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_1_I1 I2=n436(6) I3=n406(6) O=n467_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_10_I1 I2=n453(4) I3=n414(4) O=n467_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n414(3) I2=n453(3) I3=n467_ff_CQZ_D_LUT4_O_11_I1 O=n467_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_11_I1 I2=n453(3) I3=n414(3) O=n467_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n414(2) I2=n453(2) I3=n467_ff_CQZ_D_LUT4_O_12_I1 O=n467_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_12_I1 I2=n453(2) I3=n414(2) O=n467_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n453(1) I1=n414(1) I2=n414(0) I3=n453(0) O=n467_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n467_ff_CQZ_D_LUT4_O_13_I3 O=n467_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n414(0) I1=n453(0) I2=n453(1) I3=n414(1) O=n467_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n406(5) I2=n436(5) I3=n467_ff_CQZ_D_LUT4_O_2_I1 O=n467_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_2_I1 I2=n436(5) I3=n406(5) O=n467_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n406(4) I2=n436(4) I3=n467_ff_CQZ_D_LUT4_O_3_I1 O=n467_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_3_I1 I2=n436(4) I3=n406(4) O=n467_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n406(3) I2=n436(3) I3=n467_ff_CQZ_D_LUT4_O_4_I1 O=n467_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_4_I1 I2=n436(3) I3=n406(3) O=n467_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n406(2) I2=n436(2) I3=n467_ff_CQZ_D_LUT4_O_5_I1 O=n467_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_5_I1 I2=n436(2) I3=n406(2) O=n467_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n436(1) I1=n406(1) I2=n406(0) I3=n436(0) O=n467_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n467_ff_CQZ_D_LUT4_O_6_I3 O=n467_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n406(0) I1=n436(0) I2=n436(1) I3=n406(1) O=n467_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_7_I1 I2=n453(7) I3=n414(7) O=n467_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n414(6) I2=n453(6) I3=n467_ff_CQZ_D_LUT4_O_8_I1 O=n467_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_8_I1 I2=n453(6) I3=n414(6) O=n467_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n414(5) I2=n453(5) I3=n467_ff_CQZ_D_LUT4_O_9_I1 O=n467_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n467_ff_CQZ_D_LUT4_O_9_I1 I2=n453(5) I3=n414(5) O=n467_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n414(4) I2=n453(4) I3=n467_ff_CQZ_D_LUT4_O_10_I1 O=n467_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n406(6) I2=n436(6) I3=n467_ff_CQZ_D_LUT4_O_1_I1 O=n467_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n2059 I2=n41(0) I3=n11(6) O=n46_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n41(0) I3=n11(6) O=n46_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n41(0) D=n46_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3489.1-3494.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n41(0) I2=n51_ff_CQZ_D I3=n26_LUT4_I2_O O=n46_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n472 I3=n2062 O=n476_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n472 D=n472_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3947.1-3952.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n476 I3=n2062 O=n480_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n476 D=n476_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3953.1-3958.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n480 I3=n2062 O=n484_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n480 D=n480_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3959.1-3964.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n484 O=n484_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n484_LUT4_I3_O I2=n524(4) I3=n484_LUT4_I3_O_LUT4_I1_I3 O=n484_LUT4_I3_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n484_LUT4_I3_O I2=n524(1) I3=n524(0) O=n484_LUT4_I3_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n524(0) I1=n524(1) I2=n524(2) I3=n524(3) O=n484_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n484_LUT4_I3_O I3=n484_LUT4_I3_O_LUT4_I2_I3 O=n484_LUT4_I3_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n484_LUT4_I3_O I3=n524(0) O=n484_LUT4_I3_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n524(0) I1=n524(1) I2=n524(2) I3=n524(3) O=n484_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n484_LUT4_I3_O_LUT4_I1_I3 I1=n524(4) I2=n524(5) I3=n484_LUT4_I3_O O=n484_LUT4_I3_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n524(0) I1=n524(1) I2=n524(2) I3=n484_LUT4_I3_O O=n484_LUT4_I3_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n484 D=n484_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3965.1-3970.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n371(0) D=n384_LUT4_I3_I2_LUT4_I3_O(0) QCK=$iopadmap$clock_c QEN=n2103 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3839.1-3844.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n506 I3=n2062 O=n510_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n506 D=n506_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3995.1-4000.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n371(0) I3=n2062 O=n506_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n510 I3=n2062 O=n514_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n510 D=n510_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4001.1-4006.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n514 I3=n2062 O=n518_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n514 D=n514_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4007.1-4012.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n518 I2=n2059 I3=n563(0) O=n518_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n518 I2=n2059 I3=n563(0) O=n518_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n518 I3=n526(0) O=n518_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=n518 D=n518_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4013.1-4018.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n111(0) I3=n2109_LUT4_O_I3 O=n142_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n111(0) O=n51_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n111(0) D=n51_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3495.1-3500.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n524(5) D=n484_LUT4_I3_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4019.1-4024.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n524(4) D=n484_LUT4_I3_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4019.1-4024.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n524(3) D=n484_LUT4_I3_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4019.1-4024.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n524(2) D=n484_LUT4_I3_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4019.1-4024.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n524(1) D=n484_LUT4_I3_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4019.1-4024.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n524(0) D=n484_LUT4_I3_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4019.1-4024.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n526(0) I2=n2059 I3=n518 O=n531_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n526(0) D=n531_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4025.1-4030.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n484 I2=n526(0) I3=n2062 O=n531_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n2062 I2=n536 I3=n2097_LUT4_O_I3 O=n625_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n536 O=n536_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n536_LUT4_I3_O I2=n612(5) I3=n625_LUT4_I3_I2 O=n743_LUT4_I3_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n536_LUT4_I3_O I2=n612(4) I3=n743_LUT4_I0_2_O O=n743_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n536_LUT4_I3_O I3=n743_LUT4_I0_O O=n743_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n625_LUT4_I3_I2 I1=n612(5) I2=n612(6) I3=n536_LUT4_I3_O O=n743_LUT4_I3_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n536 D=n536_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4031.1-4036.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n484 I3=n2062 O=n536_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n547(31) D=n460(15) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(30) D=n460(14) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(21) D=n460(5) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(20) D=n460(4) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(19) D=n460(3) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(18) D=n460(2) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(17) D=n460(1) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(16) D=n460(0) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(15) D=n467(15) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(14) D=n467(14) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(13) D=n467(13) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(12) D=n467(12) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(29) D=n460(13) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(11) D=n467(11) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(10) D=n467(10) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(9) D=n467(9) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4037.1-4041.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n547(8) D=n467(8) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n547(22) D=n460(6) QCK=$iopadmap$clock_c QEN=n518_LUT4_I2_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n551(31) D=n460(15) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n551(20) D=n460(4) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n551(19) D=n460(3) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n551(18) D=n460(2) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n551(17) D=n460(1) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n551(16) D=n460(0) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n551(15) D=n467(15) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n551(14) D=n467(14) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(13) D=n467(13) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(12) D=n467(12) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(29) D=n460(13) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(11) D=n467(11) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(10) D=n467(10) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(9) D=n467(9) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(8) D=n467(8) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(7) D=n467(7) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(6) D=n467(6) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(5) D=n467(5) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(4) D=n467(4) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(3) D=n467(3) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(2) D=n467(2) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(28) D=n460(12) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(1) D=n467(1) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(0) D=n467(0) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(27) D=n460(11) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(26) D=n460(10) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(25) D=n460(9) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(24) D=n460(8) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(23) D=n460(7) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n551(22) D=n460(6) QCK=$iopadmap$clock_c QEN=n531_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4047.1-4051.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n551(15) I1=n547(15) I2=n555 I3=n596(0) O=n555_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(14) I1=n547(14) I2=n555 I3=n596(0) O=n555_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(5) I1=n547(5) I2=n555 I3=n596(0) O=n555_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(4) I1=n547(4) I2=n555 I3=n596(0) O=n555_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(3) I1=n547(3) I2=n555 I3=n596(0) O=n555_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(2) I1=n547(2) I2=n555 I3=n596(0) O=n555_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(1) I1=n547(1) I2=n555 I3=n596(0) O=n555_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n547(0) I1=n551(0) I2=n555 I3=n596(0) O=n555_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n551(13) I1=n547(13) I2=n555 I3=n596(0) O=n555_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(12) I1=n547(12) I2=n555 I3=n596(0) O=n555_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(11) I1=n547(11) I2=n555 I3=n596(0) O=n555_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(10) I1=n547(10) I2=n555 I3=n596(0) O=n555_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(9) I1=n547(9) I2=n555 I3=n596(0) O=n555_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(8) I1=n547(8) I2=n555 I3=n596(0) O=n555_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(7) I1=n547(7) I2=n555 I3=n596(0) O=n555_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(6) I1=n547(6) I2=n555 I3=n596(0) O=n555_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n551(31) I1=n547(31) I2=n596(0) I3=n555 O=n555_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(30) I1=n547(30) I2=n596(0) I3=n555 O=n555_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(21) I1=n547(21) I2=n596(0) I3=n555 O=n555_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(20) I1=n547(20) I2=n596(0) I3=n555 O=n555_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(19) I1=n547(19) I2=n596(0) I3=n555 O=n555_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(18) I1=n547(18) I2=n596(0) I3=n555 O=n555_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(17) I1=n547(17) I2=n596(0) I3=n555 O=n555_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(16) I1=n547(16) I2=n596(0) I3=n555 O=n555_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(29) I1=n547(29) I2=n596(0) I3=n555 O=n555_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(28) I1=n547(28) I2=n596(0) I3=n555 O=n555_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(27) I1=n547(27) I2=n596(0) I3=n555 O=n555_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(26) I1=n547(26) I2=n596(0) I3=n555 O=n555_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(25) I1=n547(25) I2=n596(0) I3=n555 O=n555_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(24) I1=n547(24) I2=n596(0) I3=n555 O=n555_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(23) I1=n547(23) I2=n596(0) I3=n555 O=n555_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n551(22) I1=n547(22) I2=n596(0) I3=n555 O=n555_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n555 D=n555_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4057.1-4062.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n526(0) O=n555_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n563(0) D=n568_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4069.1-4074.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n563(0) I2=n484 I3=n2062 O=n568_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=n584(31) D=n460(15) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(30) D=n460(14) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(21) D=n460(5) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(20) D=n460(4) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(19) D=n460(3) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(18) D=n460(2) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(17) D=n460(1) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(16) D=n460(0) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(15) D=n467(15) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(14) D=n467(14) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4075.1-4079.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n584(13) D=n467(13) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n588(19) D=n460(3) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n588(18) D=n460(2) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n588(17) D=n460(1) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n588(16) D=n460(0) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n588(15) D=n467(15) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n588(14) D=n467(14) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n588(13) D=n467(13) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n588(12) D=n467(12) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n588(29) D=n460(13) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(11) D=n467(11) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
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+.subckt ff CQZ=n588(10) D=n467(10) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=n588(9) D=n467(9) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(8) D=n467(8) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(7) D=n467(7) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(6) D=n467(6) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(5) D=n467(5) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(4) D=n467(4) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(3) D=n467(3) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(2) D=n467(2) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(28) D=n460(12) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(1) D=n467(1) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(0) D=n467(0) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(27) D=n460(11) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(26) D=n460(10) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(25) D=n460(9) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(24) D=n460(8) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(23) D=n460(7) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n588(22) D=n460(6) QCK=$iopadmap$clock_c QEN=n518_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4085.1-4089.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n588(15) I1=n584(15) I2=n592 I3=n596(0) O=n592_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(14) I1=n584(14) I2=n592 I3=n596(0) O=n592_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(5) I1=n584(5) I2=n592 I3=n596(0) O=n592_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(4) I1=n584(4) I2=n592 I3=n596(0) O=n592_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(3) I1=n584(3) I2=n592 I3=n596(0) O=n592_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(2) I1=n584(2) I2=n592 I3=n596(0) O=n592_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(1) I1=n584(1) I2=n592 I3=n596(0) O=n592_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n584(0) I1=n588(0) I2=n592 I3=n596(0) O=n592_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n588(13) I1=n584(13) I2=n592 I3=n596(0) O=n592_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(12) I1=n584(12) I2=n592 I3=n596(0) O=n592_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(11) I1=n584(11) I2=n592 I3=n596(0) O=n592_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(10) I1=n584(10) I2=n592 I3=n596(0) O=n592_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(9) I1=n584(9) I2=n592 I3=n596(0) O=n592_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(8) I1=n584(8) I2=n592 I3=n596(0) O=n592_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(7) I1=n584(7) I2=n592 I3=n596(0) O=n592_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(6) I1=n584(6) I2=n592 I3=n596(0) O=n592_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n588(31) I1=n584(31) I2=n596(0) I3=n592 O=n592_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(30) I1=n584(30) I2=n596(0) I3=n592 O=n592_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(21) I1=n584(21) I2=n596(0) I3=n592 O=n592_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(20) I1=n584(20) I2=n596(0) I3=n592 O=n592_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(19) I1=n584(19) I2=n596(0) I3=n592 O=n592_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(18) I1=n584(18) I2=n596(0) I3=n592 O=n592_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(17) I1=n584(17) I2=n596(0) I3=n592 O=n592_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(16) I1=n584(16) I2=n596(0) I3=n592 O=n592_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(29) I1=n584(29) I2=n596(0) I3=n592 O=n592_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(28) I1=n584(28) I2=n596(0) I3=n592 O=n592_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(27) I1=n584(27) I2=n596(0) I3=n592 O=n592_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(26) I1=n584(26) I2=n596(0) I3=n592 O=n592_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(25) I1=n584(25) I2=n596(0) I3=n592 O=n592_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(24) I1=n584(24) I2=n596(0) I3=n592 O=n592_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(23) I1=n584(23) I2=n596(0) I3=n592 O=n592_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n588(22) I1=n584(22) I2=n596(0) I3=n592 O=n592_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n592 D=n592_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4095.1-4100.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n563(0) O=n592_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n596(0) D=n601_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4101.1-4106.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n536_LUT4_I3_O I3=n601_ff_CQZ_D_LUT4_O_I3 O=n601_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n524(1) I1=n524(0) I2=n601_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n596(0) O=n601_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n524(2) I1=n524(3) I2=n524(4) I3=n524(5) O=n601_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=n612(6) D=n743_LUT4_I3_O(6) QCK=$iopadmap$clock_c QEN=n2097 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4107.1-4112.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n612(5) D=n743_LUT4_I3_O(5) QCK=$iopadmap$clock_c QEN=n2097 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4107.1-4112.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n612(4) D=n743_LUT4_I3_O(4) QCK=$iopadmap$clock_c QEN=n2097 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4107.1-4112.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n612(3) D=n743_LUT4_I3_O(3) QCK=$iopadmap$clock_c QEN=n2097 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4107.1-4112.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n612(2) D=n743_LUT4_I3_O(2) QCK=$iopadmap$clock_c QEN=n2097 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4107.1-4112.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n612(1) D=n743_LUT4_I3_O(1) QCK=$iopadmap$clock_c QEN=n2097 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4107.1-4112.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n616(0) I2=n658_ff_CQZ_D(15) I3=n625_LUT4_I3_I2 O=n2097_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt ff CQZ=n616(0) D=n625_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4113.1-4118.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n658_ff_CQZ_D(15) I2=n625_LUT4_I3_I2 I3=n625 O=n713_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n612(4) I3=n743_LUT4_I0_2_O O=n625_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=n625 D=n625_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4119.1-4124.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(15) D=n631_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(14) D=n631_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(5) D=n631_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(4) D=n631_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(3) D=n631_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(2) D=n631_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(1) D=n631_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(0) D=n631_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(13) D=n631_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(12) D=n631_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(11) D=n631_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(10) D=n631_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(9) D=n631_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(8) D=n631_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(7) D=n631_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n631(6) D=n631_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4125.1-4130.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_O I3=n555_LUT4_I2_O O=n631_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_1_O I3=n555_LUT4_I2_1_O O=n631_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_10_O I3=n555_LUT4_I2_10_O O=n631_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_11_O I3=n555_LUT4_I2_11_O O=n631_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_12_O I3=n555_LUT4_I2_12_O O=n631_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_13_O I3=n555_LUT4_I2_13_O O=n631_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_14_O I3=n555_LUT4_I2_14_O O=n631_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_15_O I3=n555_LUT4_I2_15_O O=n631_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_2_O I3=n555_LUT4_I2_2_O O=n631_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_3_O I3=n555_LUT4_I2_3_O O=n631_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_4_O I3=n555_LUT4_I2_4_O O=n631_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_5_O I3=n555_LUT4_I2_5_O O=n631_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_6_O I3=n555_LUT4_I2_6_O O=n631_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_7_O I3=n555_LUT4_I2_7_O O=n631_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_8_O I3=n555_LUT4_I2_8_O O=n631_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n555_LUT4_I3_9_O I3=n555_LUT4_I2_9_O O=n631_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=n637(15) D=n637_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(14) D=n637_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(5) D=n637_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(4) D=n637_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(3) D=n637_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(2) D=n637_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(1) D=n637_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(0) D=n637_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(13) D=n637_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(12) D=n637_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(11) D=n637_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(10) D=n637_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(9) D=n637_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(8) D=n637_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(7) D=n637_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n637(6) D=n637_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4131.1-4136.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_O I3=n592_LUT4_I2_O O=n637_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_1_O I3=n592_LUT4_I2_1_O O=n637_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_10_O I3=n592_LUT4_I2_10_O O=n637_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_11_O I3=n592_LUT4_I2_11_O O=n637_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_12_O I3=n592_LUT4_I2_12_O O=n637_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_13_O I3=n592_LUT4_I2_13_O O=n637_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_14_O I3=n592_LUT4_I2_14_O O=n637_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_15_O I3=n592_LUT4_I2_15_O O=n637_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_2_O I3=n592_LUT4_I2_2_O O=n637_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_3_O I3=n592_LUT4_I2_3_O O=n637_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_4_O I3=n592_LUT4_I2_4_O O=n637_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_5_O I3=n592_LUT4_I2_5_O O=n637_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_6_O I3=n592_LUT4_I2_6_O O=n637_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_7_O I3=n592_LUT4_I2_7_O O=n637_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_8_O I3=n592_LUT4_I2_8_O O=n637_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n592_LUT4_I3_9_O I3=n592_LUT4_I2_9_O O=n637_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n643(7) I3=n2062 O=n647_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n643(6) I3=n2062 O=n647_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n643(5) I3=n2062 O=n647_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n643(4) I3=n2062 O=n647_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n643(3) I3=n2062 O=n647_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n643(2) I3=n2062 O=n647_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n643(1) I3=n2062 O=n647_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n643(0) I3=n2062 O=n647_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n643(7) D=n643_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4137.1-4142.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n643(6) D=n643_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4137.1-4142.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n643(5) D=n643_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4137.1-4142.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n643(4) D=n643_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4137.1-4142.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n643(3) D=n643_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4137.1-4142.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n643(2) D=n643_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4137.1-4142.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n643(1) D=n643_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4137.1-4142.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n643(0) D=n643_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4137.1-4142.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(15) I3=n2062 O=n643_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(14) I3=n2062 O=n643_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(13) I3=n2062 O=n643_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(12) I3=n2062 O=n643_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(11) I3=n2062 O=n643_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(10) I3=n2062 O=n643_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(9) I3=n2062 O=n643_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(8) I3=n2062 O=n643_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n647(7) D=n647_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4143.1-4148.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n647(6) D=n647_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4143.1-4148.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n647(5) D=n647_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4143.1-4148.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n647(4) D=n647_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4143.1-4148.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n647(3) D=n647_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4143.1-4148.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n647(2) D=n647_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4143.1-4148.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n647(1) D=n647_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4143.1-4148.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n647(0) D=n647_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4143.1-4148.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(31) D=n28(31) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(30) D=n28(30) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(21) D=n28(21) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(20) D=n28(20) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(19) D=n28(19) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(18) D=n28(18) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(17) D=n28(17) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(16) D=n28(16) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(15) D=n28(15) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(14) D=n28(14) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(13) D=n28(13) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(12) D=n28(12) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(29) D=n28(29) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(11) D=n28(11) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(10) D=n28(10) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(9) D=n28(9) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(8) D=n28(8) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(7) D=n28(7) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(6) D=n28(6) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(5) D=n28(5) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(4) D=n28(4) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(3) D=n28(3) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(2) D=n28(2) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(28) D=n28(28) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(1) D=n28(1) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(0) D=n28(0) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(27) D=n28(27) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(26) D=n28(26) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(25) D=n28(25) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(24) D=n28(24) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(23) D=n28(23) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n64(22) D=n28(22) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3501.1-3505.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n651(7) I3=n2062 O=n655_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n651(6) I3=n2062 O=n655_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n651(5) I3=n2062 O=n655_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n651(4) I3=n2062 O=n655_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n651(3) I3=n2062 O=n655_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n651(2) I3=n2062 O=n655_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n651(1) I3=n2062 O=n655_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n651(0) I3=n2062 O=n655_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n651(7) D=n651_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4149.1-4154.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n651(6) D=n651_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4149.1-4154.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n651(5) D=n651_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4149.1-4154.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n651(4) D=n651_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4149.1-4154.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n651(3) D=n651_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4149.1-4154.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n651(2) D=n651_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4149.1-4154.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n651(1) D=n651_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4149.1-4154.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n651(0) D=n651_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4149.1-4154.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(7) I3=n2062 O=n651_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(6) I3=n2062 O=n651_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(5) I3=n2062 O=n651_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(4) I3=n2062 O=n651_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(3) I3=n2062 O=n651_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(2) I3=n2062 O=n651_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(1) I3=n2062 O=n651_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n631(0) I3=n2062 O=n651_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n655(7) D=n655_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4155.1-4160.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n655(6) D=n655_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4155.1-4160.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n655(5) D=n655_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4155.1-4160.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n655(4) D=n655_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4155.1-4160.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n655(3) D=n655_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4155.1-4160.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n655(2) D=n655_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4155.1-4160.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n655(1) D=n655_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4155.1-4160.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n655(0) D=n655_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4155.1-4160.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(15) D=n658_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(14) D=n658_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(5) D=n612(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(4) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(3) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(2) D=n612(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(1) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(0) D=n612(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(13) D=n658_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(12) D=n658_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(11) D=n658_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(10) D=n658_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(9) D=n658_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(8) D=n658_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(7) D=n658_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n658(6) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4161.1-4168.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1019 I3=n612(6) O=n658_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt LUT4 I0=n1019 I1=n1019 I2=n612(5) I3=n612(6) O=n658_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n612(5) I3=n612(6) O=n658_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n612(5) I3=n612(6) O=n658_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=n666(7) D=n666_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4169.1-4174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n666(6) D=n666_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4169.1-4174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n666(5) D=n666_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4169.1-4174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n666(4) D=n666_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4169.1-4174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n666(3) D=n666_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4169.1-4174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n666(2) D=n666_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4169.1-4174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n666(1) D=n666_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4169.1-4174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n666(0) D=n666_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4169.1-4174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n666_ff_CQZ_D_LUT4_O_I3 O=n666_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n2062 I1=n666_ff_CQZ_D_LUT4_O_1_I1 I2=n666_ff_CQZ_D_LUT4_O_1_I2 I3=n666_ff_CQZ_D_LUT4_O_1_I3 O=n666_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_2_I2 I2=n666_ff_CQZ_D_LUT4_O_2_I3 I3=n666_ff_CQZ_D_LUT4_O_2_I1 O=n666_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_1_I3 I3=n666_ff_CQZ_D_LUT4_O_1_I2 O=n666_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I2=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n666_ff_CQZ_D_LUT4_O_2_I1 I2=n666_ff_CQZ_D_LUT4_O_2_I2 I3=n666_ff_CQZ_D_LUT4_O_2_I3 O=n666_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n658(10) I2=n637(15) I3=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(13) I1=n658(12) I2=n637(14) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(13) I1=n637(14) I2=n658(12) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I2=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n666_ff_CQZ_D_LUT4_O_3_I3 O=n666_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n666_ff_CQZ_D_LUT4_O_4_I3 O=n666_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_5_I1 I1=n666_ff_CQZ_D_LUT4_O_5_I3 I2=n666_ff_CQZ_D_LUT4_O_5_I2 I3=n666_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n666_ff_CQZ_D_LUT4_O_5_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I3 O=n666_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_5_I1 I1=n666_ff_CQZ_D_LUT4_O_5_I3 I2=n666_ff_CQZ_D_LUT4_O_5_I2 I3=n666_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n666_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n658(8) I3=n637(15) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(10) I3=n637(12) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(10) I1=n658(12) I2=n637(11) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(8) I1=n658(14) I2=n637(9) I3=n658(13) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(10) I1=n658(13) I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n637(8) I1=n637(9) I2=n658(14) I3=n658(13) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n637(8) I1=n658(15) I2=n637(9) I3=n658(14) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n658(10) I3=n637(13) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n637(11) I1=n658(12) I2=n637(12) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n658(8) I1=n637(15) I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(9) I3=n637(14) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(11) I3=n637(11) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n658(10) I3=n637(14) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n658(13) I3=n637(11) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n637(9) I1=n658(15) I2=n637(10) I3=n658(14) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n658(13) I2=n637(10) I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(8) I1=n637(9) I2=n658(15) I3=n658(14) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n658(13) I3=n637(10) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I2=n658(9) I3=n637(15) O=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n658(10) I2=n637(14) I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(12) I1=n658(12) I2=n637(13) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(12) I1=n637(13) I2=n658(12) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n658(10) I3=n637(15) O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n637(11) I1=n658(14) I2=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=n658(13) I2=n637(11) I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(9) I1=n637(10) I2=n658(15) I3=n658(14) O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n658(9) I2=n637(15) I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n658(10) I2=n637(13) I3=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n658(12) I2=n637(12) I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n666_ff_CQZ_D_LUT4_O_6_I3 O=n666_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(12) I3=n637(9) O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(8) I3=n637(14) O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(9) I3=n637(13) O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=n637(8) I3=n658(13) O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n666_ff_CQZ_D_LUT4_O_7_I3 O=n666_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000001011
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110001110
+.subckt LUT4 I0=n637(9) I1=n658(10) I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n637(10) I1=n658(9) I2=n637(11) I3=n658(8) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(11) I3=n637(8) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=n658(10) I2=n637(8) I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(9) I1=n637(10) I2=n658(9) I3=n658(8) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n658(10) I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n637(8) I1=n637(9) I2=n658(9) I3=n658(8) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n637(9) I1=n658(9) I2=n637(10) I3=n658(8) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n637(9) I1=n658(10) I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n637(13) I1=n658(8) I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(10) I3=n637(10) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(11) I3=n637(9) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(9) I3=n637(12) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(8) I1=n658(12) I2=n637(9) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(8) I1=n658(13) I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(10) I3=n637(11) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(9) I1=n658(12) I2=n637(10) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n637(12) I1=n658(8) I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n637(12) I3=n658(8) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n637(8) I1=n637(9) I2=n658(11) I3=n658(10) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n658(8) I2=n637(10) I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(9) I3=n637(11) O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n658(8) I1=n637(13) I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n637(13) I1=n658(8) I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n666_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n666_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_2_I1 I1=n666_ff_CQZ_D_LUT4_O_2_I3 I2=n666_ff_CQZ_D_LUT4_O_2_I2 I3=n666_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_1_I3 I1=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n637(14) I1=n637(15) I2=n658(12) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n637(15) I1=n658(12) I2=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n637(15) I3=n658(12) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n637(11) I3=n658(15) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n658(13) I3=n637(14) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n637(14) I1=n658(12) I2=n637(15) I3=n658(11) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(11) I1=n658(15) I2=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(14) I3=n637(12) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(13) I3=n637(13) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n637(11) I3=n658(14) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(15) I3=n637(10) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(13) I3=n637(12) O=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I3=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(13) I3=n637(15) O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n658(15) I3=n637(13) O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n658(13) I2=n637(14) I3=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(12) I1=n658(15) I2=n637(13) I3=n658(14) O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n658(15) I2=n637(13) I3=n666_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n637(15) I1=n658(14) I2=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n637(13) I3=n658(15) O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(15) I3=n637(14) O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n637(15) I2=n658(15) I3=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(14) I3=n637(14) O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(15) I1=n658(14) I2=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n666_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=n672(7) D=n672_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4175.1-4180.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n672(6) D=n672_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4175.1-4180.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n672(5) D=n672_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4175.1-4180.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n672(4) D=n672_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4175.1-4180.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n672(3) D=n672_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4175.1-4180.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n672(2) D=n672_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4175.1-4180.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n672(1) D=n672_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4175.1-4180.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n672(0) D=n672_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4175.1-4180.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n672_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_1_I1 I2=n672_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n672_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I1=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I2=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I3=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 O=n672_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I3=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 O=n672_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n672_ff_CQZ_D_LUT4_O_2_I3 O=n672_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 I3=n672_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 O=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I1=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 I2=n658(3) I3=n637(7) O=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n672_ff_CQZ_D_LUT4_O_3_I3 O=n672_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_4_I1 I1=n672_ff_CQZ_D_LUT4_O_4_I3 I2=n672_ff_CQZ_D_LUT4_O_4_I2 I3=n672_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n2062 I1=n672_ff_CQZ_D_LUT4_O_4_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I3 O=n672_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_4_I1 I1=n672_ff_CQZ_D_LUT4_O_4_I3 I2=n672_ff_CQZ_D_LUT4_O_4_I2 I3=n672_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I1=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I2=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n637(5) I1=n658(3) I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(6) I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n637(6) I2=n658(1) I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n658(2) I1=n637(6) I2=n637(7) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n637(7) I1=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n658(4) I1=n637(5) I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n637(3) I2=n658(5) I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n658(7) I1=n658(6) I2=n637(1) I3=n637(2) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n637(4) I3=n658(5) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n658(7) I1=n637(2) I2=n658(6) I3=n637(3) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 I2=n637(5) I3=n658(3) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n658(4) I1=n637(4) I2=n658(1) I3=n637(7) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n637(3) I3=n658(5) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n658(7) I1=n637(1) I2=n658(6) I3=n637(2) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=n658(7) I1=n658(6) I2=n637(0) I3=n637(1) O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I1=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n637(7) I1=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n637(7) I2=n658(4) I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(6) I3=n658(3) O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n658(3) I1=n637(7) I2=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n658(4) I3=n637(5) O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n658(4) I1=n637(6) I2=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=n637(4) I2=n658(5) I3=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n658(7) I1=n658(6) I2=n637(2) I3=n637(3) O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=n637(5) I3=n658(5) O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n672_ff_CQZ_D_LUT4_O_5_I3 O=n672_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I2=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I3=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I2=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I3=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 O=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n672_ff_CQZ_D_LUT4_O_6_I3 O=n672_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I1 I1=n672_ff_CQZ_D_LUT4_O_7_I3 I2=n672_ff_CQZ_D_LUT4_O_7_I2 I3=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I1=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 I2=n658(3) I3=n637(4) O=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n2062 I1=n672_ff_CQZ_D_LUT4_O_7_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I3 O=n672_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I1 I1=n672_ff_CQZ_D_LUT4_O_7_I3 I2=n672_ff_CQZ_D_LUT4_O_7_I2 I3=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100011101110
+.subckt LUT4 I0=n637(1) I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n658(1) I1=n637(2) I2=n637(3) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n658(2) I2=n658(0) I3=n637(2) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(0) I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n658(1) I1=n637(1) I2=n637(2) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n637(1) I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n658(1) I1=n637(1) I2=n637(2) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(0) I3=n658(3) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n658(4) I1=n637(0) I2=n637(4) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(3) I3=n658(1) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(2) I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n658(3) I1=n637(2) I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n637(2) I1=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n658(1) I1=n637(2) I2=n637(3) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(1) I3=n658(3) O=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n637(2) I1=n658(3) I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(3) I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n658(1) I1=n637(5) I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n658(4) I1=n637(2) I2=n637(6) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n658(6) I1=n637(0) I2=n658(5) I3=n637(1) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n658(5) I3=n637(0) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n637(4) I2=n658(1) I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n658(2) I1=n637(4) I2=n637(5) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(3) I3=n658(3) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n658(3) I1=n637(2) I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n658(5) I1=n637(0) I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(4) I3=n658(1) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n658(4) I1=n637(1) I2=n637(5) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(0) I3=n637(4) O=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n637(6) I3=n658(1) O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n658(4) I1=n637(3) I2=n637(7) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n658(7) I1=n637(0) I2=n658(6) I3=n637(1) O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(2) I3=n658(5) O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n658(6) I1=n658(5) I2=n637(0) I3=n637(1) O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n658(1) I1=n637(5) I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I1=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I2=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 O=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n658(3) I1=n637(4) I2=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=n637(5) I2=n658(1) I3=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n658(4) I1=n637(2) I2=n637(6) I3=n658(0) O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(5) I3=n658(2) O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I1=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 I2=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I3=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 O=n672_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n637(4) I1=n658(2) I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n658(4) I3=n637(7) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=n637(5) I2=n658(5) I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n658(7) I1=n637(3) I2=n658(6) I3=n637(4) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n658(7) I1=n658(6) I2=n637(3) I3=n637(4) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=n637(6) I3=n658(5) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n658(6) I1=n637(7) I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n658(7) I3=n637(5) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(6) I3=n658(7) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(7) I3=n658(5) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n637(5) I3=n658(7) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n637(6) I2=n658(5) I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n658(7) I1=n637(4) I2=n658(6) I3=n637(5) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n658(7) I1=n658(6) I2=n637(4) I3=n637(5) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n658(7) I2=n637(7) I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(6) I3=n658(6) O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n658(6) I1=n637(7) I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I2=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_1_I1 O=n672_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100001010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n658(4) I1=n637(7) I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=n672_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=n658(4) I3=n637(6) O=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=n672_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n672_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=n677(7) D=n677_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4181.1-4186.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n677(6) D=n677_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4181.1-4186.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n677(5) D=n677_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4181.1-4186.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n677(4) D=n677_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4181.1-4186.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n677(3) D=n677_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4181.1-4186.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n677(2) D=n677_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4181.1-4186.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n677(1) D=n677_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4181.1-4186.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n677(0) D=n677_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4181.1-4186.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n677_ff_CQZ_D_LUT4_O_I1 I2=n672(7) I3=n666(7) O=n677_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n677_ff_CQZ_D_LUT4_O_1_I1 I2=n672(6) I3=n666(6) O=n677_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n666(5) I2=n672(5) I3=n677_ff_CQZ_D_LUT4_O_2_I1 O=n677_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n677_ff_CQZ_D_LUT4_O_2_I1 I2=n672(5) I3=n666(5) O=n677_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n666(4) I2=n672(4) I3=n677_ff_CQZ_D_LUT4_O_3_I1 O=n677_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n677_ff_CQZ_D_LUT4_O_3_I1 I2=n672(4) I3=n666(4) O=n677_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n666(3) I2=n672(3) I3=n677_ff_CQZ_D_LUT4_O_4_I1 O=n677_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n677_ff_CQZ_D_LUT4_O_4_I1 I2=n672(3) I3=n666(3) O=n677_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n666(2) I2=n672(2) I3=n677_ff_CQZ_D_LUT4_O_5_I1 O=n677_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n677_ff_CQZ_D_LUT4_O_5_I1 I2=n672(2) I3=n666(2) O=n677_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n672(1) I1=n666(1) I2=n666(0) I3=n672(0) O=n677_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n677_ff_CQZ_D_LUT4_O_6_I3 O=n677_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n666(0) I1=n672(0) I2=n672(1) I3=n666(1) O=n677_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n666(0) I2=n672(0) I3=n2062 O=n677_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n666(6) I2=n672(6) I3=n677_ff_CQZ_D_LUT4_O_1_I1 O=n677_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=n683(7) D=n683_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4187.1-4192.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n683(6) D=n683_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4187.1-4192.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n683(5) D=n683_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4187.1-4192.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n683(4) D=n683_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4187.1-4192.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n683(3) D=n683_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4187.1-4192.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n683(2) D=n683_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4187.1-4192.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n683(1) D=n683_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4187.1-4192.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n683(0) D=n683_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4187.1-4192.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n683_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_1_I0 I1=n683_ff_CQZ_D_LUT4_O_1_I1 I2=n2062 I3=n683_ff_CQZ_D_LUT4_O_1_I3 O=n683_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_3_I1 I1=n683_ff_CQZ_D_LUT4_O_3_I3 I2=n683_ff_CQZ_D_LUT4_O_3_I2 I3=n683_ff_CQZ_D_LUT4_O_2_I2 O=n683_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n637(14) I1=n658(6) I2=n637(15) I3=n658(7) O=n683_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I2=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_2_I1 I2=n683_ff_CQZ_D_LUT4_O_2_I2 I3=n2062 O=n683_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_3_I2 I2=n683_ff_CQZ_D_LUT4_O_3_I3 I3=n683_ff_CQZ_D_LUT4_O_3_I1 O=n683_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I2=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=n658(5) I2=n637(15) I3=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n637(14) I2=n658(7) I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n658(7) I1=n637(14) I2=n637(15) I3=n658(6) O=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n2062 I1=n683_ff_CQZ_D_LUT4_O_3_I1 I2=n683_ff_CQZ_D_LUT4_O_3_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I3 O=n683_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I3=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n658(2) I2=n637(15) I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(13) I1=n658(4) I2=n637(14) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(13) I1=n637(14) I2=n658(4) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n637(14) I1=n658(4) I2=n637(15) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(12) I1=n658(6) I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(11) I3=n658(7) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(5) I3=n637(13) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n637(11) I3=n658(6) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n637(14) I1=n637(15) I2=n658(4) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n637(15) I1=n658(4) I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n637(12) I3=n658(6) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n658(7) I1=n637(12) I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(6) I3=n637(13) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(5) I3=n637(14) O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n637(15) I3=n658(4) O=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n637(15) I1=n658(5) I2=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n637(15) I1=n658(5) I2=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=n658(7) I3=n637(12) O=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n658(7) I1=n637(13) I2=n637(14) I3=n658(6) O=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n683_ff_CQZ_D_LUT4_O_4_I3 O=n683_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I1 I1=n683_ff_CQZ_D_LUT4_O_5_I3 I2=n683_ff_CQZ_D_LUT4_O_5_I2 I3=n683_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n683_ff_CQZ_D_LUT4_O_5_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I3 O=n683_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I1 I1=n683_ff_CQZ_D_LUT4_O_5_I3 I2=n683_ff_CQZ_D_LUT4_O_5_I2 I3=n683_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n683_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n658(0) I3=n637(15) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(2) I3=n637(12) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(10) I1=n658(4) I2=n637(11) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(8) I1=n658(6) I2=n637(9) I3=n658(5) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n637(8) I1=n658(7) I2=n637(9) I3=n658(6) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(5) I3=n637(10) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(8) I1=n637(9) I2=n658(6) I3=n658(5) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n658(2) I3=n637(13) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n637(11) I1=n658(4) I2=n637(12) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n658(0) I1=n637(15) I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(1) I3=n637(14) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(3) I3=n637(11) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n658(2) I3=n637(14) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n637(10) I1=n658(6) I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(9) I3=n658(7) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(5) I3=n637(11) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n637(9) I3=n658(6) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(7) I3=n637(8) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I2=n658(1) I3=n637(15) O=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n658(2) I2=n637(14) I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(12) I1=n658(4) I2=n637(13) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(12) I1=n637(13) I2=n658(4) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n658(2) I3=n637(15) O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n637(11) I1=n658(6) I2=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n637(10) I3=n658(7) O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(5) I3=n637(12) O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n637(10) I3=n658(6) O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n658(1) I2=n637(15) I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n658(2) I2=n637(13) I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n658(4) I2=n637(12) I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n683_ff_CQZ_D_LUT4_O_6_I3 O=n683_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(1) I3=n637(13) O=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n683_ff_CQZ_D_LUT4_O_7_I3 O=n683_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000000100000000
+.subckt LUT4 I0=n637(9) I1=n658(2) I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(3) I3=n637(8) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(10) I1=n658(1) I2=n637(11) I3=n658(0) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(0) I3=n637(10) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(2) I3=n637(8) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(8) I1=n637(9) I2=n658(1) I3=n658(0) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I2=n637(9) I3=n658(1) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n637(9) I1=n658(2) I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=n637(13) I1=n658(0) I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n637(12) I1=n658(0) I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n637(12) I3=n658(0) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n637(8) I1=n637(9) I2=n658(3) I3=n658(2) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(1) I3=n637(11) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n637(13) I1=n658(0) I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n637(8) I1=n658(5) I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n658(0) I1=n637(13) I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(1) I3=n637(12) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(2) I3=n637(10) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(3) I3=n637(9) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(8) I1=n658(4) I2=n637(9) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n637(8) I3=n658(5) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(2) I3=n637(11) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(9) I1=n658(4) I2=n637(10) I3=n658(3) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(4) I3=n637(9) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(0) I3=n637(14) O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n683_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n683_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I3=n683_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 O=n683_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=n689(7) D=n689_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4193.1-4198.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n689(6) D=n689_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4193.1-4198.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n689(5) D=n689_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4193.1-4198.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n689(4) D=n689_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4193.1-4198.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n689(3) D=n689_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4193.1-4198.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n689(2) D=n689_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4193.1-4198.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n689(1) D=n689_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4193.1-4198.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n689(0) D=n689_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4193.1-4198.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_I2 I3=n2062 O=n689_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_1_I0 I1=n689_ff_CQZ_D_LUT4_O_1_I1 I2=n2062 I3=n689_ff_CQZ_D_LUT4_O_1_I3 O=n689_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_3_I1 I1=n689_ff_CQZ_D_LUT4_O_3_I3 I2=n689_ff_CQZ_D_LUT4_O_3_I2 I3=n689_ff_CQZ_D_LUT4_O_2_I2 O=n689_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n637(6) I1=n658(14) I2=n658(15) I3=n637(7) O=n689_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I1=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I2=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_2_I1 I2=n689_ff_CQZ_D_LUT4_O_2_I2 I3=n2062 O=n689_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_3_I2 I2=n689_ff_CQZ_D_LUT4_O_3_I3 I3=n689_ff_CQZ_D_LUT4_O_3_I1 O=n689_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I2=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=n658(13) I2=n637(7) I3=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(5) I1=n637(6) I2=n658(15) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n637(6) I1=n658(15) I2=n637(7) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n2062 I1=n689_ff_CQZ_D_LUT4_O_3_I1 I2=n689_ff_CQZ_D_LUT4_O_3_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I3 O=n689_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I1=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I3=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n637(6) I3=n658(11) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(12) I3=n637(5) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(10) I3=n637(7) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n637(6) I1=n658(12) I2=n637(7) I3=n658(11) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(4) I1=n658(14) I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(15) I3=n637(3) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(13) I3=n637(5) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n637(3) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n637(6) I1=n637(7) I2=n658(12) I3=n658(11) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n637(7) I1=n658(12) I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=n637(4) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n658(13) I3=n637(6) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n637(4) I1=n658(15) I2=n637(5) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n637(7) I3=n658(12) O=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n637(7) I1=n658(13) I2=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n637(7) I1=n658(13) I2=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=n658(13) I2=n637(6) I3=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(4) I1=n637(5) I2=n658(15) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n637(5) I1=n658(15) I2=n637(6) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n689_ff_CQZ_D_LUT4_O_4_I3 O=n689_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_5_I1 I1=n689_ff_CQZ_D_LUT4_O_5_I3 I2=n689_ff_CQZ_D_LUT4_O_5_I2 I3=n689_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n689_ff_CQZ_D_LUT4_O_5_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I3 O=n689_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_5_I1 I1=n689_ff_CQZ_D_LUT4_O_5_I3 I2=n689_ff_CQZ_D_LUT4_O_5_I2 I3=n689_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n689_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n658(8) I3=n637(7) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(10) I3=n637(4) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(2) I1=n658(12) I2=n637(3) I3=n658(11) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(0) I1=n658(14) I2=n637(1) I3=n658(13) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(2) I1=n658(13) I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n637(0) I1=n637(1) I2=n658(14) I3=n658(13) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n637(0) I1=n658(15) I2=n637(1) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n658(10) I3=n637(5) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n637(3) I1=n658(12) I2=n637(4) I3=n658(11) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n658(8) I1=n637(7) I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(9) I3=n637(6) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(11) I3=n637(3) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n658(10) I3=n637(6) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n658(13) I3=n637(3) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n637(1) I1=n658(15) I2=n637(2) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n658(13) I2=n637(2) I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(0) I1=n637(1) I2=n658(15) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n658(13) I3=n637(2) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I2=n658(9) I3=n637(7) O=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n658(10) I2=n637(6) I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(4) I1=n658(12) I2=n637(5) I3=n658(11) O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n637(4) I1=n637(5) I2=n658(12) I3=n658(11) O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n637(6) I1=n658(11) I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n637(3) I1=n658(14) I2=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(15) I3=n637(2) O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(13) I3=n637(4) O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=n658(13) I2=n637(3) I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n637(1) I1=n637(2) I2=n658(15) I3=n658(14) O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n658(9) I2=n637(7) I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n658(10) I2=n637(5) I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n658(12) I2=n637(4) I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n689_ff_CQZ_D_LUT4_O_6_I3 O=n689_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(9) I3=n637(5) O=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n689_ff_CQZ_D_LUT4_O_7_I3 O=n689_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=n637(0) I1=n637(1) I2=n658(9) I3=n658(8) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n637(1) I1=n637(2) I2=n658(9) I3=n658(8) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n658(10) I2=n637(0) I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n637(1) I1=n658(9) I2=n637(2) I3=n658(8) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n658(10) I2=n637(2) I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n637(2) I1=n658(9) I2=n637(3) I3=n658(8) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(11) I3=n637(0) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(10) I3=n637(1) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n658(8) I2=n637(2) I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n637(5) I1=n658(8) I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n637(0) I1=n658(13) I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n658(8) I1=n637(5) I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(9) I3=n637(4) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(11) I3=n637(1) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(12) I3=n637(0) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n637(0) I3=n658(13) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(10) I3=n637(3) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(1) I1=n658(12) I2=n637(2) I3=n658(11) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(12) I3=n637(1) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(8) I3=n637(6) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(10) I3=n637(2) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n637(4) I1=n658(8) I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n637(4) I3=n658(8) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n637(0) I1=n637(1) I2=n658(11) I3=n658(10) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n658(9) I3=n637(3) O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n637(5) I1=n658(8) I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n689_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n689_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I3=n689_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 O=n689_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=n68(31) D=n28(31) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(30) D=n28(30) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(21) D=n28(21) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(20) D=n28(20) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(19) D=n28(19) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(18) D=n28(18) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(17) D=n28(17) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(16) D=n28(16) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(15) D=n28(15) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(14) D=n28(14) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(13) D=n28(13) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(12) D=n28(12) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(29) D=n28(29) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(11) D=n28(11) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(10) D=n28(10) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(9) D=n28(9) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(8) D=n28(8) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(7) D=n28(7) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(6) D=n28(6) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(5) D=n28(5) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(4) D=n28(4) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(3) D=n28(3) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(2) D=n28(2) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(28) D=n28(28) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(1) D=n28(1) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(0) D=n28(0) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(27) D=n28(27) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(26) D=n28(26) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(25) D=n28(25) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(24) D=n28(24) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(23) D=n28(23) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n68(22) D=n28(22) QCK=$iopadmap$clock_c QEN=n46_LUT4_I2_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3511.1-3515.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n694(7) D=n694_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4199.1-4204.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n694(6) D=n694_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4199.1-4204.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n694(5) D=n694_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4199.1-4204.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n694(4) D=n694_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4199.1-4204.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n694(3) D=n694_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4199.1-4204.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n694(2) D=n694_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4199.1-4204.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n694(1) D=n694_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4199.1-4204.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n694(0) D=n694_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4199.1-4204.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n694_ff_CQZ_D_LUT4_O_I1 I2=n683(7) I3=n689(7) O=n694_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n694_ff_CQZ_D_LUT4_O_1_I1 I2=n683(6) I3=n689(6) O=n694_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n689(5) I2=n683(5) I3=n694_ff_CQZ_D_LUT4_O_2_I1 O=n694_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n694_ff_CQZ_D_LUT4_O_2_I1 I2=n683(5) I3=n689(5) O=n694_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n689(4) I2=n683(4) I3=n694_ff_CQZ_D_LUT4_O_3_I1 O=n694_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n694_ff_CQZ_D_LUT4_O_3_I1 I2=n683(4) I3=n689(4) O=n694_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n689(3) I2=n683(3) I3=n694_ff_CQZ_D_LUT4_O_4_I1 O=n694_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n694_ff_CQZ_D_LUT4_O_4_I1 I2=n683(3) I3=n689(3) O=n694_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n689(2) I2=n683(2) I3=n694_ff_CQZ_D_LUT4_O_5_I1 O=n694_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n694_ff_CQZ_D_LUT4_O_5_I1 I2=n683(2) I3=n689(2) O=n694_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n683(1) I1=n689(1) I2=n683(0) I3=n689(0) O=n694_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n694_ff_CQZ_D_LUT4_O_6_I3 O=n694_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n683(0) I1=n689(0) I2=n683(1) I3=n689(1) O=n694_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n689(0) I2=n683(0) I3=n2062 O=n694_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n689(6) I2=n683(6) I3=n694_ff_CQZ_D_LUT4_O_1_I1 O=n694_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n701(15) D=n701_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(14) D=n701_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(5) D=n701_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(4) D=n701_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(3) D=n701_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(2) D=n701_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(1) D=n701_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(0) D=n701_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(13) D=n701_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(12) D=n701_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(11) D=n701_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(10) D=n701_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(9) D=n701_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(8) D=n701_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(7) D=n701_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n701(6) D=n701_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4205.1-4210.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_I1 I2=n677(7) I3=n647(7) O=n701_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_1_I1 I2=n677(6) I3=n647(6) O=n701_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_10_I1 I2=n694(4) I3=n655(4) O=n701_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n655(3) I2=n694(3) I3=n701_ff_CQZ_D_LUT4_O_11_I1 O=n701_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_11_I1 I2=n694(3) I3=n655(3) O=n701_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n655(2) I2=n694(2) I3=n701_ff_CQZ_D_LUT4_O_12_I1 O=n701_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_12_I1 I2=n694(2) I3=n655(2) O=n701_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n694(1) I1=n655(1) I2=n655(0) I3=n694(0) O=n701_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n701_ff_CQZ_D_LUT4_O_13_I3 O=n701_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n694(0) I1=n655(0) I2=n694(1) I3=n655(1) O=n701_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n647(0) I2=n677(0) I3=n2062 O=n701_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n655(0) I2=n694(0) I3=n2062 O=n701_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n647(5) I2=n677(5) I3=n701_ff_CQZ_D_LUT4_O_2_I1 O=n701_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_2_I1 I2=n677(5) I3=n647(5) O=n701_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n647(4) I2=n677(4) I3=n701_ff_CQZ_D_LUT4_O_3_I1 O=n701_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_3_I1 I2=n677(4) I3=n647(4) O=n701_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n647(3) I2=n677(3) I3=n701_ff_CQZ_D_LUT4_O_4_I1 O=n701_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_4_I1 I2=n677(3) I3=n647(3) O=n701_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n647(2) I2=n677(2) I3=n701_ff_CQZ_D_LUT4_O_5_I1 O=n701_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_5_I1 I2=n677(2) I3=n647(2) O=n701_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n677(1) I1=n647(1) I2=n647(0) I3=n677(0) O=n701_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n701_ff_CQZ_D_LUT4_O_6_I3 O=n701_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n677(0) I1=n647(0) I2=n677(1) I3=n647(1) O=n701_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_7_I1 I2=n694(7) I3=n655(7) O=n701_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n655(6) I2=n694(6) I3=n701_ff_CQZ_D_LUT4_O_8_I1 O=n701_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_8_I1 I2=n694(6) I3=n655(6) O=n701_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n655(5) I2=n694(5) I3=n701_ff_CQZ_D_LUT4_O_9_I1 O=n701_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n701_ff_CQZ_D_LUT4_O_9_I1 I2=n694(5) I3=n655(5) O=n701_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n655(4) I2=n694(4) I3=n701_ff_CQZ_D_LUT4_O_10_I1 O=n701_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n647(6) I2=n677(6) I3=n701_ff_CQZ_D_LUT4_O_1_I1 O=n701_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n708(15) D=n708_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(14) D=n708_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(5) D=n708_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(4) D=n708_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(3) D=n708_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(2) D=n708_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(1) D=n708_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(0) D=n701_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(13) D=n708_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(12) D=n708_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(11) D=n708_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(10) D=n708_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(9) D=n708_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(8) D=n701_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(7) D=n708_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n708(6) D=n708_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4211.1-4216.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_I1 I2=n677(7) I3=n647(7) O=n708_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_1_I1 I2=n677(6) I3=n647(6) O=n708_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_10_I1 I2=n694(4) I3=n655(4) O=n708_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n655(3) I2=n694(3) I3=n708_ff_CQZ_D_LUT4_O_11_I1 O=n708_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_11_I1 I2=n694(3) I3=n655(3) O=n708_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n655(2) I2=n694(2) I3=n708_ff_CQZ_D_LUT4_O_12_I1 O=n708_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_12_I1 I2=n694(2) I3=n655(2) O=n708_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n694(1) I1=n655(1) I2=n655(0) I3=n694(0) O=n708_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n708_ff_CQZ_D_LUT4_O_13_I3 O=n708_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n655(0) I1=n694(0) I2=n694(1) I3=n655(1) O=n708_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n647(5) I2=n677(5) I3=n708_ff_CQZ_D_LUT4_O_2_I1 O=n708_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_2_I1 I2=n677(5) I3=n647(5) O=n708_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n647(4) I2=n677(4) I3=n708_ff_CQZ_D_LUT4_O_3_I1 O=n708_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_3_I1 I2=n677(4) I3=n647(4) O=n708_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n647(3) I2=n677(3) I3=n708_ff_CQZ_D_LUT4_O_4_I1 O=n708_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_4_I1 I2=n677(3) I3=n647(3) O=n708_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n647(2) I2=n677(2) I3=n708_ff_CQZ_D_LUT4_O_5_I1 O=n708_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_5_I1 I2=n677(2) I3=n647(2) O=n708_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n677(1) I1=n647(1) I2=n647(0) I3=n677(0) O=n708_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n708_ff_CQZ_D_LUT4_O_6_I3 O=n708_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n647(0) I1=n677(0) I2=n677(1) I3=n647(1) O=n708_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_7_I1 I2=n694(7) I3=n655(7) O=n708_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n655(6) I2=n694(6) I3=n708_ff_CQZ_D_LUT4_O_8_I1 O=n708_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_8_I1 I2=n694(6) I3=n655(6) O=n708_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n655(5) I2=n694(5) I3=n708_ff_CQZ_D_LUT4_O_9_I1 O=n708_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n708_ff_CQZ_D_LUT4_O_9_I1 I2=n694(5) I3=n655(5) O=n708_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n655(4) I2=n694(4) I3=n708_ff_CQZ_D_LUT4_O_10_I1 O=n708_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n647(6) I2=n677(6) I3=n708_ff_CQZ_D_LUT4_O_1_I1 O=n708_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n713 I3=n2062 O=n717_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n713 D=n713_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4217.1-4222.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n717 I3=n2062 O=n721_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n717 D=n717_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4223.1-4228.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n721 I3=n2062 O=n725_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n721 D=n721_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4229.1-4234.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n725 O=n725_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n725_LUT4_I3_O I2=n765(4) I3=n725_LUT4_I3_O_LUT4_I1_I3 O=n725_LUT4_I3_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n725_LUT4_I3_O I2=n765(1) I3=n765(0) O=n725_LUT4_I3_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n765(0) I1=n765(1) I2=n765(2) I3=n765(3) O=n725_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n725_LUT4_I3_O I3=n725_LUT4_I3_O_LUT4_I2_I3 O=n725_LUT4_I3_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n725_LUT4_I3_O I3=n765(0) O=n725_LUT4_I3_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n765(0) I1=n765(1) I2=n765(2) I3=n765(3) O=n725_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n725_LUT4_I3_O_LUT4_I1_I3 I1=n765(4) I2=n765(5) I3=n725_LUT4_I3_O O=n725_LUT4_I3_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n765(0) I1=n765(1) I2=n765(2) I3=n725_LUT4_I3_O O=n725_LUT4_I3_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n725 D=n725_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4235.1-4240.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n68(15) I1=n64(15) I2=n72 I3=n113(0) O=n72_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(14) I1=n64(14) I2=n72 I3=n113(0) O=n72_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(5) I1=n64(5) I2=n72 I3=n113(0) O=n72_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(4) I1=n64(4) I2=n72 I3=n113(0) O=n72_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(3) I1=n64(3) I2=n72 I3=n113(0) O=n72_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(2) I1=n64(2) I2=n72 I3=n113(0) O=n72_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(1) I1=n64(1) I2=n72 I3=n113(0) O=n72_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n64(0) I1=n68(0) I2=n72 I3=n113(0) O=n72_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n68(13) I1=n64(13) I2=n72 I3=n113(0) O=n72_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(12) I1=n64(12) I2=n72 I3=n113(0) O=n72_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(11) I1=n64(11) I2=n72 I3=n113(0) O=n72_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(10) I1=n64(10) I2=n72 I3=n113(0) O=n72_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(9) I1=n64(9) I2=n72 I3=n113(0) O=n72_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(8) I1=n64(8) I2=n72 I3=n113(0) O=n72_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(7) I1=n64(7) I2=n72 I3=n113(0) O=n72_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(6) I1=n64(6) I2=n72 I3=n113(0) O=n72_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n68(31) I1=n64(31) I2=n113(0) I3=n72 O=n72_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(30) I1=n64(30) I2=n113(0) I3=n72 O=n72_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(21) I1=n64(21) I2=n113(0) I3=n72 O=n72_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(20) I1=n64(20) I2=n113(0) I3=n72 O=n72_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(19) I1=n64(19) I2=n113(0) I3=n72 O=n72_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(18) I1=n64(18) I2=n113(0) I3=n72 O=n72_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(17) I1=n64(17) I2=n113(0) I3=n72 O=n72_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(16) I1=n64(16) I2=n113(0) I3=n72 O=n72_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(29) I1=n64(29) I2=n113(0) I3=n72 O=n72_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(28) I1=n64(28) I2=n113(0) I3=n72 O=n72_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(27) I1=n64(27) I2=n113(0) I3=n72 O=n72_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(26) I1=n64(26) I2=n113(0) I3=n72 O=n72_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(25) I1=n64(25) I2=n113(0) I3=n72 O=n72_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(24) I1=n64(24) I2=n113(0) I3=n72 O=n72_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(23) I1=n64(23) I2=n113(0) I3=n72 O=n72_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n68(22) I1=n64(22) I2=n113(0) I3=n72 O=n72_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n72 D=n72_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3521.1-3526.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n41(0) O=n72_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n612(0) I1=n612(1) I2=n612(2) I3=n612(3) O=n743_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n612(0) I1=n612(1) I2=n612(2) I3=n536_LUT4_I3_O O=n743_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n612(0) I1=n612(1) I2=n612(2) I3=n612(3) O=n743_LUT4_I0_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n536_LUT4_I3_O I2=n612(1) I3=n612(0) O=n743_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n536_LUT4_I3_O I3=n612(0) O=n743_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n612(0) D=n743_LUT4_I3_O(0) QCK=$iopadmap$clock_c QEN=n2097 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4107.1-4112.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n747 I3=n2062 O=n751_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n747 D=n747_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4265.1-4270.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n612(0) I3=n2062 O=n747_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n751 I3=n2062 O=n755_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n751 D=n751_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4271.1-4276.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n755 I3=n2062 O=n759_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n755 D=n755_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4277.1-4282.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n759 I2=n2059 I3=n804(0) O=n759_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n759 I2=n2059 I3=n804(0) O=n759_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n759 I3=n767(0) O=n759_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=n759 D=n759_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4283.1-4288.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n765(5) D=n725_LUT4_I3_O_LUT4_I2_O(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4289.1-4294.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n765(4) D=n725_LUT4_I3_O_LUT4_I2_O(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4289.1-4294.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n765(3) D=n725_LUT4_I3_O_LUT4_I2_O(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4289.1-4294.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n765(2) D=n725_LUT4_I3_O_LUT4_I2_O(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4289.1-4294.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n765(1) D=n725_LUT4_I3_O_LUT4_I2_O(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4289.1-4294.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n765(0) D=n725_LUT4_I3_O_LUT4_I2_O(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4289.1-4294.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n767(0) I2=n2059 I3=n759 O=n772_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n767(0) D=n772_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4295.1-4300.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n725 I2=n767(0) I3=n2062 O=n772_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n2062 I2=n777 I3=n2091_LUT4_O_I3 O=n866_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n777 O=n777_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n777 D=n777_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4301.1-4306.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n725 I3=n2062 O=n777_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n788(31) D=n701(15) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(30) D=n701(14) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(21) D=n701(5) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(20) D=n701(4) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(19) D=n701(3) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(18) D=n701(2) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(17) D=n701(1) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(16) D=n701(0) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(15) D=n708(15) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(14) D=n708(14) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(13) D=n708(13) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(12) D=n708(12) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(29) D=n701(13) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(11) D=n708(11) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(10) D=n708(10) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(9) D=n708(9) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(8) D=n708(8) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(7) D=n708(7) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(6) D=n708(6) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(5) D=n708(5) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(4) D=n708(4) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(3) D=n708(3) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(2) D=n708(2) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(28) D=n701(12) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(1) D=n708(1) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(0) D=n708(0) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(27) D=n701(11) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(26) D=n701(10) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(25) D=n701(9) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(24) D=n701(8) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(23) D=n701(7) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n788(22) D=n701(6) QCK=$iopadmap$clock_c QEN=n759_LUT4_I2_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4307.1-4311.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(31) D=n701(15) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(30) D=n701(14) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(21) D=n701(5) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(20) D=n701(4) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(19) D=n701(3) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(18) D=n701(2) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(17) D=n701(1) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(16) D=n701(0) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(15) D=n708(15) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(14) D=n708(14) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(13) D=n708(13) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(12) D=n708(12) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(29) D=n701(13) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(11) D=n708(11) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(10) D=n708(10) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(9) D=n708(9) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(8) D=n708(8) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(7) D=n708(7) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(6) D=n708(6) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(5) D=n708(5) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(4) D=n708(4) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(3) D=n708(3) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(2) D=n708(2) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(28) D=n701(12) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(1) D=n708(1) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(0) D=n708(0) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(27) D=n701(11) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(26) D=n701(10) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(25) D=n701(9) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(24) D=n701(8) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(23) D=n701(7) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n792(22) D=n701(6) QCK=$iopadmap$clock_c QEN=n772_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4317.1-4321.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n792(15) I1=n788(15) I2=n796 I3=n837(0) O=n796_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(14) I1=n788(14) I2=n796 I3=n837(0) O=n796_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(5) I1=n788(5) I2=n796 I3=n837(0) O=n796_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(4) I1=n788(4) I2=n796 I3=n837(0) O=n796_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(3) I1=n788(3) I2=n796 I3=n837(0) O=n796_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(2) I1=n788(2) I2=n796 I3=n837(0) O=n796_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(1) I1=n788(1) I2=n796 I3=n837(0) O=n796_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n788(0) I1=n792(0) I2=n796 I3=n837(0) O=n796_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n792(13) I1=n788(13) I2=n796 I3=n837(0) O=n796_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(12) I1=n788(12) I2=n796 I3=n837(0) O=n796_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(11) I1=n788(11) I2=n796 I3=n837(0) O=n796_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(10) I1=n788(10) I2=n796 I3=n837(0) O=n796_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(9) I1=n788(9) I2=n796 I3=n837(0) O=n796_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(8) I1=n788(8) I2=n796 I3=n837(0) O=n796_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(7) I1=n788(7) I2=n796 I3=n837(0) O=n796_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(6) I1=n788(6) I2=n796 I3=n837(0) O=n796_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n792(31) I1=n788(31) I2=n837(0) I3=n796 O=n796_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(30) I1=n788(30) I2=n837(0) I3=n796 O=n796_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(21) I1=n788(21) I2=n837(0) I3=n796 O=n796_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(20) I1=n788(20) I2=n837(0) I3=n796 O=n796_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(19) I1=n788(19) I2=n837(0) I3=n796 O=n796_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(18) I1=n788(18) I2=n837(0) I3=n796 O=n796_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(17) I1=n788(17) I2=n837(0) I3=n796 O=n796_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(16) I1=n788(16) I2=n837(0) I3=n796 O=n796_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(29) I1=n788(29) I2=n837(0) I3=n796 O=n796_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(28) I1=n788(28) I2=n837(0) I3=n796 O=n796_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(27) I1=n788(27) I2=n837(0) I3=n796 O=n796_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(26) I1=n788(26) I2=n837(0) I3=n796 O=n796_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(25) I1=n788(25) I2=n837(0) I3=n796 O=n796_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(24) I1=n788(24) I2=n837(0) I3=n796 O=n796_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(23) I1=n788(23) I2=n837(0) I3=n796 O=n796_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n792(22) I1=n788(22) I2=n837(0) I3=n796 O=n796_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n796 D=n796_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4327.1-4332.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n767(0) O=n796_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n804(0) D=n809_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4339.1-4344.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n804(0) I2=n725 I3=n2062 O=n809_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=n825(31) D=n701(15) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(30) D=n701(14) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(21) D=n701(5) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(20) D=n701(4) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(19) D=n701(3) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(18) D=n701(2) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(17) D=n701(1) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(16) D=n701(0) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(15) D=n708(15) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(14) D=n708(14) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(13) D=n708(13) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(12) D=n708(12) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(29) D=n701(13) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(11) D=n708(11) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(10) D=n708(10) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(9) D=n708(9) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(8) D=n708(8) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(7) D=n708(7) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(6) D=n708(6) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(5) D=n708(5) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(4) D=n708(4) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(3) D=n708(3) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(2) D=n708(2) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(28) D=n701(12) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(1) D=n708(1) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(0) D=n708(0) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(27) D=n701(11) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(26) D=n701(10) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(25) D=n701(9) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(24) D=n701(8) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(23) D=n701(7) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n825(22) D=n701(6) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4345.1-4349.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(31) D=n701(15) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(30) D=n701(14) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(21) D=n701(5) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(20) D=n701(4) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(19) D=n701(3) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(18) D=n701(2) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(17) D=n701(1) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(16) D=n701(0) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(15) D=n708(15) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(14) D=n708(14) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(13) D=n708(13) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(12) D=n708(12) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(29) D=n701(13) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(11) D=n708(11) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(10) D=n708(10) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(9) D=n708(9) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(8) D=n708(8) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(7) D=n708(7) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(6) D=n708(6) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(5) D=n708(5) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(4) D=n708(4) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(3) D=n708(3) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(2) D=n708(2) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(28) D=n701(12) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(1) D=n708(1) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(0) D=n708(0) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(27) D=n701(11) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(26) D=n701(10) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(25) D=n701(9) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(24) D=n701(8) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(23) D=n701(7) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n829(22) D=n701(6) QCK=$iopadmap$clock_c QEN=n759_LUT4_I1_1_O QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4355.1-4359.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n829(15) I1=n825(15) I2=n833 I3=n837(0) O=n833_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(14) I1=n825(14) I2=n833 I3=n837(0) O=n833_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(5) I1=n825(5) I2=n833 I3=n837(0) O=n833_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(4) I1=n825(4) I2=n833 I3=n837(0) O=n833_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(3) I1=n825(3) I2=n833 I3=n837(0) O=n833_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(2) I1=n825(2) I2=n833 I3=n837(0) O=n833_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(1) I1=n825(1) I2=n833 I3=n837(0) O=n833_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n825(0) I1=n829(0) I2=n833 I3=n837(0) O=n833_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=n829(13) I1=n825(13) I2=n833 I3=n837(0) O=n833_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(12) I1=n825(12) I2=n833 I3=n837(0) O=n833_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(11) I1=n825(11) I2=n833 I3=n837(0) O=n833_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(10) I1=n825(10) I2=n833 I3=n837(0) O=n833_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(9) I1=n825(9) I2=n833 I3=n837(0) O=n833_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(8) I1=n825(8) I2=n833 I3=n837(0) O=n833_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(7) I1=n825(7) I2=n833 I3=n837(0) O=n833_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(6) I1=n825(6) I2=n833 I3=n837(0) O=n833_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=n829(31) I1=n825(31) I2=n837(0) I3=n833 O=n833_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(30) I1=n825(30) I2=n837(0) I3=n833 O=n833_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(21) I1=n825(21) I2=n837(0) I3=n833 O=n833_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(20) I1=n825(20) I2=n837(0) I3=n833 O=n833_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(19) I1=n825(19) I2=n837(0) I3=n833 O=n833_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(18) I1=n825(18) I2=n837(0) I3=n833 O=n833_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(17) I1=n825(17) I2=n837(0) I3=n833 O=n833_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(16) I1=n825(16) I2=n837(0) I3=n833 O=n833_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(29) I1=n825(29) I2=n837(0) I3=n833 O=n833_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(28) I1=n825(28) I2=n837(0) I3=n833 O=n833_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(27) I1=n825(27) I2=n837(0) I3=n833 O=n833_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(26) I1=n825(26) I2=n837(0) I3=n833 O=n833_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(25) I1=n825(25) I2=n837(0) I3=n833 O=n833_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(24) I1=n825(24) I2=n837(0) I3=n833 O=n833_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(23) I1=n825(23) I2=n837(0) I3=n833 O=n833_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=n829(22) I1=n825(22) I2=n837(0) I3=n833 O=n833_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=n833 D=n833_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4365.1-4370.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n804(0) O=n833_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=n837(0) D=n842_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4371.1-4376.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n777_LUT4_I3_O I3=n842_ff_CQZ_D_LUT4_O_I3 O=n842_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n765(1) I1=n765(0) I2=n842_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n837(0) O=n842_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=n765(2) I1=n765(3) I2=n765(4) I3=n765(5) O=n842_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=n853(6) D=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(6) QCK=$iopadmap$clock_c QEN=n2091 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4377.1-4382.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n853(5) D=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(5) QCK=$iopadmap$clock_c QEN=n2091 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4377.1-4382.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n853(4) D=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(4) QCK=$iopadmap$clock_c QEN=n2091 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4377.1-4382.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n853(3) D=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(3) QCK=$iopadmap$clock_c QEN=n2091 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4377.1-4382.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n853(2) D=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(2) QCK=$iopadmap$clock_c QEN=n2091 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4377.1-4382.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n853(1) D=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(1) QCK=$iopadmap$clock_c QEN=n2091 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4377.1-4382.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2059 I2=n80(0) I3=n11(6) O=n85_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n2059 I2=n11(6) I3=n80(0) O=n85_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=n80(0) D=n85_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:3533.1-3538.18|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n80(0) I2=n51_ff_CQZ_D I3=n26_LUT4_I2_O O=n85_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n857(0) I3=n866_LUT4_I1_I2 O=n2091_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n857(0) D=n866_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4383.1-4388.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n866 I2=n866_LUT4_I1_I2 I3=n2062 O=n954_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n853(5) I2=n853(6) I3=n866_LUT4_I1_I2_LUT4_O_I3 O=n866_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n866_LUT4_I1_I2_LUT4_O_I3 I1=n853(5) I2=n853(6) I3=n777_LUT4_I3_O O=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1019 I1=n777_LUT4_I3_O I2=n853(5) I3=n866_LUT4_I1_I2_LUT4_O_I3 O=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n777_LUT4_I3_O I2=n853(4) I3=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n777_LUT4_I3_O I3=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O_LUT4_O_1_I3 O=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n853(0) I1=n853(1) I2=n853(2) I3=n853(3) O=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n853(0) I1=n853(1) I2=n853(2) I3=n777_LUT4_I3_O O=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1019 I1=n777_LUT4_I3_O I2=n853(1) I3=n853(0) O=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n777_LUT4_I3_O I3=n853(0) O=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n853(4) I3=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=n866_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n853(0) I1=n853(1) I2=n853(2) I3=n853(3) O=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=n866 D=n866_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4389.1-4394.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(15) D=n872_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(14) D=n872_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(5) D=n872_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(4) D=n872_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(3) D=n872_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(2) D=n872_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(1) D=n872_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(0) D=n872_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(13) D=n872_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(12) D=n872_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(11) D=n872_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(10) D=n872_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(9) D=n872_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(8) D=n872_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(7) D=n872_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n872(6) D=n872_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4395.1-4400.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_O I3=n796_LUT4_I2_O O=n872_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_1_O I3=n796_LUT4_I2_1_O O=n872_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_10_O I3=n796_LUT4_I2_10_O O=n872_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_11_O I3=n796_LUT4_I2_11_O O=n872_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_12_O I3=n796_LUT4_I2_12_O O=n872_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_13_O I3=n796_LUT4_I2_13_O O=n872_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_14_O I3=n796_LUT4_I2_14_O O=n872_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_15_O I3=n796_LUT4_I2_15_O O=n872_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_2_O I3=n796_LUT4_I2_2_O O=n872_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_3_O I3=n796_LUT4_I2_3_O O=n872_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_4_O I3=n796_LUT4_I2_4_O O=n872_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_5_O I3=n796_LUT4_I2_5_O O=n872_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_6_O I3=n796_LUT4_I2_6_O O=n872_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_7_O I3=n796_LUT4_I2_7_O O=n872_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_8_O I3=n796_LUT4_I2_8_O O=n872_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n796_LUT4_I3_9_O I3=n796_LUT4_I2_9_O O=n872_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=n878(15) D=n878_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(14) D=n878_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(5) D=n878_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(4) D=n878_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(3) D=n878_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(2) D=n878_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(1) D=n878_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(0) D=n878_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(13) D=n878_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(12) D=n878_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(11) D=n878_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(10) D=n878_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(9) D=n878_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(8) D=n878_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(7) D=n878_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n878(6) D=n878_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4401.1-4406.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_O I3=n833_LUT4_I2_O O=n878_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_1_O I3=n833_LUT4_I2_1_O O=n878_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_10_O I3=n833_LUT4_I2_10_O O=n878_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_11_O I3=n833_LUT4_I2_11_O O=n878_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_12_O I3=n833_LUT4_I2_12_O O=n878_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_13_O I3=n833_LUT4_I2_13_O O=n878_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_14_O I3=n833_LUT4_I2_14_O O=n878_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_15_O I3=n833_LUT4_I2_15_O O=n878_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_2_O I3=n833_LUT4_I2_2_O O=n878_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_3_O I3=n833_LUT4_I2_3_O O=n878_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_4_O I3=n833_LUT4_I2_4_O O=n878_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_5_O I3=n833_LUT4_I2_5_O O=n878_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_6_O I3=n833_LUT4_I2_6_O O=n878_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_7_O I3=n833_LUT4_I2_7_O O=n878_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_8_O I3=n833_LUT4_I2_8_O O=n878_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n2062 I2=n833_LUT4_I3_9_O I3=n833_LUT4_I2_9_O O=n878_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n884(7) I3=n2062 O=n888_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n884(6) I3=n2062 O=n888_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n884(5) I3=n2062 O=n888_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n884(4) I3=n2062 O=n888_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n884(3) I3=n2062 O=n888_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n884(2) I3=n2062 O=n888_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n884(1) I3=n2062 O=n888_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n884(0) I3=n2062 O=n888_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n884(7) D=n884_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4407.1-4412.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n884(6) D=n884_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4407.1-4412.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n884(5) D=n884_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4407.1-4412.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n884(4) D=n884_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4407.1-4412.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n884(3) D=n884_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4407.1-4412.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n884(2) D=n884_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4407.1-4412.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n884(1) D=n884_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4407.1-4412.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n884(0) D=n884_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4407.1-4412.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(15) I3=n2062 O=n884_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(14) I3=n2062 O=n884_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(13) I3=n2062 O=n884_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(12) I3=n2062 O=n884_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(11) I3=n2062 O=n884_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(10) I3=n2062 O=n884_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(9) I3=n2062 O=n884_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(8) I3=n2062 O=n884_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n888(7) D=n888_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4413.1-4418.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n888(6) D=n888_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4413.1-4418.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n888(5) D=n888_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4413.1-4418.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n888(4) D=n888_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4413.1-4418.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n888(3) D=n888_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4413.1-4418.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n888(2) D=n888_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4413.1-4418.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n888(1) D=n888_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4413.1-4418.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n888(0) D=n888_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4413.1-4418.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n892(7) I3=n2062 O=n896_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n892(6) I3=n2062 O=n896_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n892(5) I3=n2062 O=n896_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n892(4) I3=n2062 O=n896_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n892(3) I3=n2062 O=n896_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n892(2) I3=n2062 O=n896_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n892(1) I3=n2062 O=n896_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n892(0) I3=n2062 O=n896_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n892(7) D=n892_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4419.1-4424.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n892(6) D=n892_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4419.1-4424.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n892(5) D=n892_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4419.1-4424.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n892(4) D=n892_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4419.1-4424.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n892(3) D=n892_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4419.1-4424.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n892(2) D=n892_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4419.1-4424.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n892(1) D=n892_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4419.1-4424.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n892(0) D=n892_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4419.1-4424.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(7) I3=n2062 O=n892_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(6) I3=n2062 O=n892_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(5) I3=n2062 O=n892_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(4) I3=n2062 O=n892_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(3) I3=n2062 O=n892_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(2) I3=n2062 O=n892_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(1) I3=n2062 O=n892_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n872(0) I3=n2062 O=n892_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n896(7) D=n896_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4425.1-4430.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n896(6) D=n896_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4425.1-4430.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n896(5) D=n896_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4425.1-4430.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n896(4) D=n896_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4425.1-4430.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n896(3) D=n896_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4425.1-4430.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n896(2) D=n896_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4425.1-4430.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n896(1) D=n896_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4425.1-4430.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n896(0) D=n896_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4425.1-4430.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(15) D=n899_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(14) D=n899_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(5) D=n899_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(4) D=n1019 QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(3) D=n853(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(2) D=n899_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(1) D=n899_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(0) D=n899_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(13) D=n899_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(12) D=n899_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(11) D=n899_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(10) D=n899_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(9) D=n899_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(8) D=n899_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(7) D=n899_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n899(6) D=n899_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4431.1-4442.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n1019 I3=n853(6) O=n899_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt LUT4 I0=n1019 I1=n1019 I2=n853(6) I3=n899_ff_CQZ_D(5) O=n899_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n853(4) I2=n853(5) I3=n853(6) O=n899_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n853(5) I3=n853(4) O=n899_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n853(4) I3=n853(6) O=n899_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n1019 I1=n853(5) I2=n853(6) I3=n853(4) O=n899_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=n1019 I1=n853(4) I2=n853(5) I3=n853(6) O=n899_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n853(6) I3=n899_ff_CQZ_D(0) O=n899_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899_ff_CQZ_D(7) I3=n899_ff_CQZ_D(15) O=n899_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=n1019 I1=n853(5) I2=n853(4) I3=n853(6) O=n899_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n853(5) I3=n853(4) O=n899_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899_ff_CQZ_D(5) I3=n899_ff_CQZ_D(1) O=n899_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=n907(7) D=n907_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4443.1-4448.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n907(6) D=n907_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4443.1-4448.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n907(5) D=n907_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4443.1-4448.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n907(4) D=n907_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4443.1-4448.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n907(3) D=n907_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4443.1-4448.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n907(2) D=n907_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4443.1-4448.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n907(1) D=n907_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4443.1-4448.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n907(0) D=n907_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4443.1-4448.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n907_ff_CQZ_D_LUT4_O_I3 O=n907_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n2062 I1=n907_ff_CQZ_D_LUT4_O_1_I1 I2=n907_ff_CQZ_D_LUT4_O_1_I2 I3=n907_ff_CQZ_D_LUT4_O_1_I3 O=n907_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_2_I3 I2=n907_ff_CQZ_D_LUT4_O_2_I2 I3=n907_ff_CQZ_D_LUT4_O_2_I1 O=n907_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_1_I3 I3=n907_ff_CQZ_D_LUT4_O_1_I2 O=n907_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=n878(15) I3=n899(12) O=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n899(13) I2=n878(13) I3=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(11) I1=n899(15) I2=n878(12) I3=n899(14) O=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(11) I1=n878(12) I2=n899(15) I3=n899(14) O=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=n899(13) I3=n878(14) O=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n907_ff_CQZ_D_LUT4_O_2_I1 I2=n907_ff_CQZ_D_LUT4_O_2_I2 I3=n907_ff_CQZ_D_LUT4_O_2_I3 O=n907_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n899(10) I2=n878(15) I3=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(13) I1=n899(12) I2=n878(14) I3=n899(11) O=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(13) I1=n878(14) I2=n899(12) I3=n899(11) O=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n907_ff_CQZ_D_LUT4_O_3_I3 O=n907_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n907_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n907_ff_CQZ_D_LUT4_O_4_I3 O=n907_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_5_I1 I1=n907_ff_CQZ_D_LUT4_O_5_I3 I2=n907_ff_CQZ_D_LUT4_O_5_I2 I3=n907_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I3=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n907_ff_CQZ_D_LUT4_O_5_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I3 O=n907_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_5_I1 I1=n907_ff_CQZ_D_LUT4_O_5_I3 I2=n907_ff_CQZ_D_LUT4_O_5_I2 I3=n907_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n907_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n899(8) I3=n878(15) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(10) I3=n878(12) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(10) I1=n899(12) I2=n878(11) I3=n899(11) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(9) I1=n899(13) I2=n899(14) I3=n878(8) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(10) I1=n899(13) I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n878(9) I1=n899(14) I2=n899(13) I3=n878(8) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n878(9) I1=n899(14) I2=n899(15) I3=n878(8) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n899(10) I3=n878(13) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n878(11) I1=n899(12) I2=n878(12) I3=n899(11) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n899(8) I1=n878(15) I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(9) I3=n878(14) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(11) I3=n878(11) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n899(10) I3=n878(14) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n899(13) I3=n878(11) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n878(9) I1=n899(15) I2=n878(10) I3=n899(14) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n899(13) I2=n878(10) I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(9) I1=n899(15) I2=n899(14) I3=n878(8) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n899(13) I3=n878(10) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I2=n899(9) I3=n878(15) O=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n899(10) I2=n878(14) I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(12) I1=n899(12) I2=n878(13) I3=n899(11) O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(12) I1=n878(13) I2=n899(12) I3=n899(11) O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n899(10) I3=n878(15) O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n899(13) I3=n878(12) O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=n899(13) I2=n878(11) I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(9) I1=n878(10) I2=n899(15) I3=n899(14) O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n899(9) I2=n878(15) I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n899(10) I2=n878(13) I3=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n899(12) I2=n878(12) I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n907_ff_CQZ_D_LUT4_O_6_I3 O=n907_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(9) I3=n878(13) O=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n907_ff_CQZ_D_LUT4_O_7_I3 O=n907_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100110011
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111000000000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(8) I3=n899(10) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(9) I3=n878(9) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110011001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(8) I3=n899(8) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n878(9) I1=n899(10) I2=n899(11) I3=n878(8) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(10) I1=n899(9) I2=n878(11) I3=n899(8) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(8) I3=n878(10) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(11) I3=n878(9) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(9) I3=n878(12) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n899(13) I3=n878(8) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(12) I3=n878(9) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(8) I3=n878(14) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n878(9) I1=n899(11) I2=n899(12) I3=n878(8) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(10) I3=n878(10) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(12) I1=n899(8) I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n878(12) I3=n899(8) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n878(9) I1=n899(10) I2=n899(11) I3=n878(8) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(9) I3=n878(11) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(8) I3=n878(13) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n899(13) I1=n878(8) I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(10) I3=n878(11) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(9) I1=n899(12) I2=n878(10) I3=n899(11) O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I1=n907_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I3=n907_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_2_I1 I1=n907_ff_CQZ_D_LUT4_O_2_I2 I2=n907_ff_CQZ_D_LUT4_O_2_I3 I3=n907_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_1_I3 I3=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n878(14) I1=n878(15) I2=n899(12) I3=n899(11) O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n878(15) I1=n899(12) I2=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0 I3=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n878(14) I1=n899(12) I2=n878(15) I3=n899(11) O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n899(13) I3=n878(13) O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n899(13) I2=n878(12) I3=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(10) I1=n899(15) I2=n878(11) I3=n899(14) O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(10) I1=n878(11) I2=n899(15) I3=n899(14) O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I3=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I3=n907_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n878(15) I1=n899(14) I2=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n878(13) I3=n899(15) O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(15) I3=n878(14) O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(13) I3=n878(15) O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n899(15) I3=n878(13) O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n899(13) I2=n878(14) I3=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(12) I1=n899(15) I2=n878(13) I3=n899(14) O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(12) I1=n878(13) I2=n899(15) I3=n899(14) O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n878(15) I2=n899(15) I3=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(14) I3=n878(14) O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(15) I1=n899(14) I2=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n907_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=n913(7) D=n913_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4449.1-4454.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n913(6) D=n913_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4449.1-4454.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n913(5) D=n913_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4449.1-4454.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n913(4) D=n913_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4449.1-4454.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n913(3) D=n913_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4449.1-4454.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n913(2) D=n913_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4449.1-4454.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n913(1) D=n913_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4449.1-4454.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n913(0) D=n913_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4449.1-4454.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n913_ff_CQZ_D_LUT4_O_I3 O=n913_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_1_I1 I2=n913_ff_CQZ_D_LUT4_O_1_I2 I3=n2062 O=n913_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_2_I2 I2=n913_ff_CQZ_D_LUT4_O_2_I3 I3=n913_ff_CQZ_D_LUT4_O_2_I1 O=n913_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n913_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I3=n913_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=n913_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n913_ff_CQZ_D_LUT4_O_2_I1 I2=n913_ff_CQZ_D_LUT4_O_2_I2 I3=n913_ff_CQZ_D_LUT4_O_2_I3 O=n913_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 I2=n878(4) I3=n899(6) O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n899(5) I2=n878(4) I3=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(5) I1=n899(4) I2=n878(6) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(5) I1=n878(6) I2=n899(4) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n878(6) I1=n899(5) I2=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n878(5) I1=n899(6) I2=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I3=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(4) I3=n878(7) O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n878(7) I3=n899(2) O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=n878(7) I1=n899(3) I2=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(4) I3=n878(6) O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(5) I3=n878(5) O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I2=n899(6) I3=n878(4) O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(7) I3=n878(3) O=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=n878(5) I3=n899(6) O=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n878(7) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(7) I3=n878(4) O=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=n899(5) I3=n878(7) O=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n878(6) I1=n899(5) I2=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n913_ff_CQZ_D_LUT4_O_3_I3 O=n913_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n913_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n913_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=n878(3) I3=n899(6) O=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I2=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I3=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n913_ff_CQZ_D_LUT4_O_4_I3 O=n913_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_5_I1 I1=n913_ff_CQZ_D_LUT4_O_5_I3 I2=n913_ff_CQZ_D_LUT4_O_5_I2 I3=n913_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n913_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n2062 I1=n913_ff_CQZ_D_LUT4_O_5_I1 I2=n913_ff_CQZ_D_LUT4_O_5_I2 I3=n913_ff_CQZ_D_LUT4_O_5_I3 O=n913_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_5_I1 I1=n913_ff_CQZ_D_LUT4_O_5_I3 I2=n913_ff_CQZ_D_LUT4_O_5_I2 I3=n913_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I3 I2=n913_ff_CQZ_D_LUT4_O_6_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I1 O=n913_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n878(2) I3=n899(6) O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n899(5) I2=n878(2) I3=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(3) I1=n899(4) I2=n878(4) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(3) I1=n878(4) I2=n899(4) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(7) I3=n878(1) O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n878(3) I1=n899(6) I2=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=n899(5) I2=n878(3) I3=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(4) I1=n878(5) I2=n899(4) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(7) I3=n878(2) O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n878(7) I2=n899(2) I3=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(1) I3=n878(6) O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n899(5) I3=n878(4) O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n2062 I1=n913_ff_CQZ_D_LUT4_O_6_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I3 O=n913_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n1019 I1=n899(6) I2=n878(0) I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n899(5) I2=n878(0) I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(1) I1=n899(4) I2=n878(2) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(1) I1=n878(2) I2=n899(4) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n899(2) I2=n878(2) I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n899(0) I1=n878(4) I2=n878(3) I3=n899(1) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n899(0) I1=n878(3) I2=n878(4) I3=n899(1) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=n899(5) I3=n878(0) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n899(2) I3=n878(3) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=n899(6) I3=n878(0) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n878(1) I1=n899(6) I2=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I3=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n899(5) I3=n878(1) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n899(2) I2=n878(3) I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n899(0) I1=n878(5) I2=n878(4) I3=n899(1) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n899(0) I1=n878(4) I2=n878(5) I3=n899(1) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n899(2) I3=n878(4) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n899(5) I3=n878(2) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n899(0) I1=n878(7) I2=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(2) I3=n878(5) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n899(2) I2=n878(4) I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n899(0) I1=n878(6) I2=n878(5) I3=n899(1) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n899(0) I1=n878(5) I2=n878(6) I3=n899(1) O=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=n878(1) I3=n899(6) O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n899(5) I2=n878(1) I3=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(2) I1=n899(4) I2=n878(3) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(2) I1=n878(3) I2=n899(4) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(7) I3=n878(0) O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n878(2) I1=n899(6) I2=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n878(6) I1=n899(2) I2=n878(7) I3=n899(1) O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n899(5) I3=n878(3) O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n878(4) I1=n899(4) I2=n878(5) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=n899(0) I3=n878(7) O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n913_ff_CQZ_D_LUT4_O_7_I3 O=n913_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I0 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(0) I3=n899(0) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(2) I3=n878(0) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(1) I3=n878(1) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(2) I3=n899(0) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n878(0) I1=n899(3) I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n899(2) I3=n878(2) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n899(0) I1=n878(2) I2=n878(3) I3=n899(1) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(2) I3=n878(1) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n899(0) I1=n878(3) I2=n878(2) I3=n899(1) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(1) I1=n899(3) I2=n878(0) I3=n899(4) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n878(0) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n878(1) I1=n878(0) I2=n899(4) I3=n899(3) O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_2_I1 I1=n913_ff_CQZ_D_LUT4_O_2_I3 I2=n913_ff_CQZ_D_LUT4_O_2_I2 I3=n913_ff_CQZ_D_LUT4_O_1_I2 O=n913_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n913_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=n913_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=n1019 I1=n899(5) I2=n878(7) I3=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n878(6) I1=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n899(6) O=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n878(6) I1=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n899(6) O=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n1019 I1=n899(5) I2=n878(6) I3=n913_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(7) I3=n878(5) O=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(6) I1=n899(7) I2=n878(7) I3=n899(6) O=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(6) I1=n899(6) I2=n899(7) I3=n878(7) O=n913_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt ff CQZ=n918(7) D=n918_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4455.1-4460.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n918(6) D=n918_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4455.1-4460.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n918(5) D=n918_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4455.1-4460.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n918(4) D=n918_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4455.1-4460.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n918(3) D=n918_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4455.1-4460.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n918(2) D=n918_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4455.1-4460.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n918(1) D=n918_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4455.1-4460.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n918(0) D=n918_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4455.1-4460.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n918_ff_CQZ_D_LUT4_O_I1 I2=n913(7) I3=n907(7) O=n918_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n918_ff_CQZ_D_LUT4_O_1_I1 I2=n913(6) I3=n907(6) O=n918_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n907(5) I2=n913(5) I3=n918_ff_CQZ_D_LUT4_O_2_I1 O=n918_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n918_ff_CQZ_D_LUT4_O_2_I1 I2=n913(5) I3=n907(5) O=n918_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n907(4) I2=n913(4) I3=n918_ff_CQZ_D_LUT4_O_3_I1 O=n918_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n918_ff_CQZ_D_LUT4_O_3_I1 I2=n913(4) I3=n907(4) O=n918_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n907(3) I2=n913(3) I3=n918_ff_CQZ_D_LUT4_O_4_I1 O=n918_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n918_ff_CQZ_D_LUT4_O_4_I1 I2=n913(3) I3=n907(3) O=n918_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n907(2) I2=n913(2) I3=n918_ff_CQZ_D_LUT4_O_5_I1 O=n918_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n918_ff_CQZ_D_LUT4_O_5_I1 I2=n913(2) I3=n907(2) O=n918_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n913(1) I1=n907(1) I2=n907(0) I3=n913(0) O=n918_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n918_ff_CQZ_D_LUT4_O_6_I3 O=n918_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n907(0) I1=n913(0) I2=n913(1) I3=n907(1) O=n918_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n907(0) I2=n913(0) I3=n2062 O=n918_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n907(6) I2=n913(6) I3=n918_ff_CQZ_D_LUT4_O_1_I1 O=n918_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=n924(7) D=n924_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4461.1-4466.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n924(6) D=n924_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4461.1-4466.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n924(5) D=n924_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4461.1-4466.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n924(4) D=n924_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4461.1-4466.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n924(3) D=n924_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4461.1-4466.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n924(2) D=n924_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4461.1-4466.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n924(1) D=n924_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4461.1-4466.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n924(0) D=n924_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4461.1-4466.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_I1 I2=n2062 I3=n924_ff_CQZ_D_LUT4_O_I3 O=n924_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=n2062 I1=n924_ff_CQZ_D_LUT4_O_1_I1 I2=n924_ff_CQZ_D_LUT4_O_1_I2 I3=n924_ff_CQZ_D_LUT4_O_1_I3 O=n924_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_2_I3 I2=n924_ff_CQZ_D_LUT4_O_2_I2 I3=n924_ff_CQZ_D_LUT4_O_2_I1 O=n924_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_1_I3 I3=n924_ff_CQZ_D_LUT4_O_1_I2 O=n924_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=n878(15) I3=n899(4) O=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=n899(5) I2=n878(13) I3=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(11) I1=n899(7) I2=n878(12) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(11) I1=n878(12) I2=n899(7) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=n899(5) I3=n878(14) O=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n924_ff_CQZ_D_LUT4_O_2_I1 I2=n924_ff_CQZ_D_LUT4_O_2_I2 I3=n924_ff_CQZ_D_LUT4_O_2_I3 O=n924_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=n899(2) I2=n878(15) I3=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(13) I1=n899(4) I2=n878(14) I3=n899(3) O=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(13) I1=n878(14) I2=n899(4) I3=n899(3) O=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n924_ff_CQZ_D_LUT4_O_3_I3 O=n924_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n924_ff_CQZ_D_LUT4_O_4_I3 O=n924_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_5_I1 I1=n924_ff_CQZ_D_LUT4_O_5_I3 I2=n924_ff_CQZ_D_LUT4_O_5_I2 I3=n924_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n924_ff_CQZ_D_LUT4_O_5_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I3 O=n924_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_5_I1 I1=n924_ff_CQZ_D_LUT4_O_5_I3 I2=n924_ff_CQZ_D_LUT4_O_5_I2 I3=n924_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 I2=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 O=n924_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(2) I3=n878(12) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(10) I1=n899(4) I2=n878(11) I3=n899(3) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(9) I1=n899(5) I2=n878(8) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(10) I1=n899(5) I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n878(9) I1=n878(8) I2=n899(6) I3=n899(5) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n878(9) I1=n899(6) I2=n878(8) I3=n899(7) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n899(2) I3=n878(13) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n878(11) I1=n899(4) I2=n878(12) I3=n899(3) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(15) I1=n899(0) I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(1) I3=n878(14) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(3) I3=n878(11) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=n899(2) I3=n878(14) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n899(5) I3=n878(11) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n878(9) I1=n899(7) I2=n878(10) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=n899(5) I2=n878(10) I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(9) I1=n878(8) I2=n899(7) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=n899(5) I3=n878(10) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I2=n899(1) I3=n878(15) O=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=n899(2) I2=n878(14) I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(12) I1=n899(4) I2=n878(13) I3=n899(3) O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(12) I1=n878(13) I2=n899(4) I3=n899(3) O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=n899(2) I3=n878(15) O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n899(5) I3=n878(12) O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=n899(5) I2=n878(11) I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(9) I1=n878(10) I2=n899(7) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n899(1) I2=n878(15) I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=n899(2) I2=n878(13) I3=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n899(4) I2=n878(12) I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n924_ff_CQZ_D_LUT4_O_6_I3 O=n924_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_7_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I2 I3=n2062 O=n924_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_7_I1 I3=n924_ff_CQZ_D_LUT4_O_7_I2 O=n924_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n899(0) I1=n878(12) I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n899(0) I3=n878(12) O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n878(9) I1=n878(8) I2=n899(3) I3=n899(2) O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(1) I3=n878(11) O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n899(0) I1=n878(13) I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2 I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I1 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n878(10) I2=n899(0) I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n878(9) I1=n899(2) I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=n899(0) I1=n878(11) I2=n878(10) I3=n899(1) O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(3) I3=n878(8) O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n899(2) I1=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110011001111
+.subckt LUT4 I0=n878(9) I1=n899(2) I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n878(8) I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n878(9) I1=n899(1) I2=n878(10) I3=n899(0) O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=n878(9) I1=n899(1) I2=n899(0) I3=n899(2) O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=n878(9) I1=n899(0) I2=n878(10) I3=n899(1) O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=n878(15) I3=n899(0) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(1) I3=n878(13) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n899(0) I1=n878(13) I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=n878(8) I1=n899(5) I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n878(13) I1=n899(0) I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(1) I3=n878(12) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(2) I3=n878(10) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(3) I3=n878(9) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(9) I1=n899(3) I2=n878(8) I3=n899(4) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n878(8) I3=n899(5) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(2) I3=n878(11) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(9) I1=n899(4) I2=n878(10) I3=n899(3) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(4) I3=n878(9) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(14) I3=n899(0) O=n924_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_2_I1 I1=n924_ff_CQZ_D_LUT4_O_2_I2 I2=n924_ff_CQZ_D_LUT4_O_2_I3 I3=n924_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_1_I3 I3=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n878(14) I1=n878(15) I2=n899(4) I3=n899(3) O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n878(15) I1=n899(4) I2=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0 I3=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n878(14) I1=n899(4) I2=n878(15) I3=n899(3) O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=n899(5) I3=n878(13) O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n899(5) I2=n878(12) I3=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(10) I1=n899(7) I2=n878(11) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(10) I1=n878(11) I2=n899(7) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I3=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I3=n924_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n878(15) I1=n899(6) I2=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n878(13) I3=n899(7) O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(7) I3=n878(14) O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(5) I3=n878(15) O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=n899(7) I3=n878(13) O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=n899(5) I2=n878(14) I3=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(12) I1=n899(7) I2=n878(13) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(12) I1=n878(13) I2=n899(7) I3=n899(6) O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n878(15) I2=n899(7) I3=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(6) I3=n878(14) O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(15) I1=n899(6) I2=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n924_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=n930(7) D=n930_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4467.1-4472.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n930(6) D=n930_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4467.1-4472.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n930(5) D=n930_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4467.1-4472.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n930(4) D=n930_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4467.1-4472.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n930(3) D=n930_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4467.1-4472.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n930(2) D=n930_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4467.1-4472.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n930(1) D=n930_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4467.1-4472.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n930(0) D=n930_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4467.1-4472.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n930_ff_CQZ_D_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_I3 O=n930_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n930_ff_CQZ_D_LUT4_O_1_I1 I2=n930_ff_CQZ_D_LUT4_O_1_I2 I3=n930_ff_CQZ_D_LUT4_O_1_I3 O=n930_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I1=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I3=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n878(5) I1=n878(6) I2=n899(13) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n930_ff_CQZ_D_LUT4_O_2_I3 O=n930_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n930_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 I3=n930_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 I3=n930_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n930_ff_CQZ_D_LUT4_O_3_I3 O=n930_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_4_I1 I1=n930_ff_CQZ_D_LUT4_O_4_I3 I2=n930_ff_CQZ_D_LUT4_O_4_I2 I3=n930_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n930_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n1019 I2=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 I3=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n2062 I1=n930_ff_CQZ_D_LUT4_O_4_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I3 O=n930_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_4_I1 I1=n930_ff_CQZ_D_LUT4_O_4_I3 I2=n930_ff_CQZ_D_LUT4_O_4_I2 I3=n930_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I1=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I3=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 I2=n899(10) I3=n878(6) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n878(3) I1=n899(13) I2=n878(4) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n899(14) I3=n878(2) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n878(1) I1=n899(15) I2=n878(5) I3=n899(11) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n878(0) I3=n899(15) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(11) I3=n878(4) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n899(10) I1=n878(6) I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(9) I3=n878(7) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 I2=n899(10) I3=n878(7) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n878(4) I1=n899(13) I2=n878(5) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=n899(14) I3=n878(3) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n878(2) I1=n899(15) I2=n878(6) I3=n899(11) O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=n1019 I1=n899(14) I2=n878(2) I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n899(10) I2=n878(7) I3=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n899(13) I2=n878(4) I3=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n878(4) I1=n878(5) I2=n899(13) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n878(5) I1=n899(13) I2=n878(6) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(7) I1=n899(11) I2=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=n899(14) I2=n878(3) I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n930_ff_CQZ_D_LUT4_O_5_I3 O=n930_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I2=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I3=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I2=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I3=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 O=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n930_ff_CQZ_D_LUT4_O_6_I3 O=n930_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I1 I1=n930_ff_CQZ_D_LUT4_O_7_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I2 I3=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n899(10) I1=n878(5) I2=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(9) I3=n878(6) O=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n2062 I1=n930_ff_CQZ_D_LUT4_O_7_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I3 O=n930_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I1 I1=n930_ff_CQZ_D_LUT4_O_7_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I2 I3=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=n899(8) I1=n878(3) I2=n878(0) I3=n899(11) O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n878(2) I1=n899(10) I2=n878(3) I3=n899(9) O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(0) I3=n899(8) O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(2) I3=n899(8) O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(10) I3=n878(0) O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n899(8) I1=n878(3) I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n878(3) I3=n899(8) O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(11) I3=n878(0) O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(1) I1=n899(10) I2=n878(2) I3=n899(9) O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n899(10) I2=n878(2) I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(9) I3=n878(1) O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n899(9) I2=n878(2) I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I3=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=n878(4) I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=n899(9) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=n899(8) I1=n878(4) I2=n878(0) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(10) I3=n878(3) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n878(3) I1=n899(11) I2=n878(0) I3=n899(14) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(1) I1=n899(13) I2=n878(2) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(6) I3=n899(8) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=n878(2) I3=n899(11) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=n1019 I1=n878(5) I2=n899(9) I3=n899(8) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=n878(1) I1=n899(12) I2=n878(5) I3=n899(9) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(10) I3=n878(4) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(11) I3=n878(1) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n899(8) I1=n878(4) I2=n878(0) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(4) I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=n899(9) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111000011
+.subckt LUT4 I0=n878(2) I1=n899(11) I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(5) I3=n899(8) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(1) I1=n899(12) I2=n878(0) I3=n899(13) O=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(13) I3=n878(2) O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(12) I3=n878(3) O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n878(7) I3=n899(8) O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=n878(4) I1=n899(11) I2=n878(0) I3=n899(15) O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(14) I3=n878(1) O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n878(3) I1=n878(0) I2=n899(14) I3=n899(11) O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=n899(10) I3=n878(5) O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110100101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(13) I3=n878(1) O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I1=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 I2=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I3=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=n899(9) I1=n878(5) I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_1_I2 I2=n930_ff_CQZ_D_LUT4_O_1_I3 I3=n930_ff_CQZ_D_LUT4_O_1_I1 O=n930_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n878(5) I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=n899(14) I3=n878(7) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110001001100
+.subckt LUT4 I0=n1019 I1=n899(11) I2=n878(2) I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(15) I3=n878(6) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=n899(13) I2=n878(7) I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=n878(4) I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n878(6) I3=n899(14) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(15) I3=n878(5) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n878(6) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(14) I3=n878(4) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n878(6) I1=n878(7) I2=n899(13) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=n899(13) I3=n878(7) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=n1019 I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=n878(6) I1=n899(13) I2=n878(7) I3=n899(12) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n878(4) I1=n899(15) I2=n878(5) I3=n899(14) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=n878(7) I3=n899(11) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(15) I3=n878(3) O=n930_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n899(15) I3=n930_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=n930_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n878(5) I1=n878(6) I2=n899(14) I3=n878(7) O=n930_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000001111111
+.subckt ff CQZ=n935(7) D=n935_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4473.1-4478.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n935(6) D=n935_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4473.1-4478.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n935(5) D=n935_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4473.1-4478.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n935(4) D=n935_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4473.1-4478.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n935(3) D=n935_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4473.1-4478.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n935(2) D=n935_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4473.1-4478.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n935(1) D=n935_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4473.1-4478.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n935(0) D=n935_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4473.1-4478.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n935_ff_CQZ_D_LUT4_O_I1 I2=n924(7) I3=n930(7) O=n935_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n935_ff_CQZ_D_LUT4_O_1_I1 I2=n924(6) I3=n930(6) O=n935_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n930(5) I2=n924(5) I3=n935_ff_CQZ_D_LUT4_O_2_I1 O=n935_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n935_ff_CQZ_D_LUT4_O_2_I1 I2=n924(5) I3=n930(5) O=n935_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n930(4) I2=n924(4) I3=n935_ff_CQZ_D_LUT4_O_3_I1 O=n935_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n935_ff_CQZ_D_LUT4_O_3_I1 I2=n924(4) I3=n930(4) O=n935_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n930(3) I2=n924(3) I3=n935_ff_CQZ_D_LUT4_O_4_I1 O=n935_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n935_ff_CQZ_D_LUT4_O_4_I1 I2=n924(3) I3=n930(3) O=n935_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n930(2) I2=n924(2) I3=n935_ff_CQZ_D_LUT4_O_5_I1 O=n935_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n935_ff_CQZ_D_LUT4_O_5_I1 I2=n924(2) I3=n930(2) O=n935_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n924(1) I1=n930(1) I2=n924(0) I3=n930(0) O=n935_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n935_ff_CQZ_D_LUT4_O_6_I3 O=n935_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n924(0) I1=n930(0) I2=n924(1) I3=n930(1) O=n935_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n930(0) I2=n924(0) I3=n2062 O=n935_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n930(6) I2=n924(6) I3=n935_ff_CQZ_D_LUT4_O_1_I1 O=n935_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n942(15) D=n942_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(14) D=n942_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(5) D=n942_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(4) D=n942_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(3) D=n942_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(2) D=n942_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(1) D=n942_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(0) D=n942_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(13) D=n942_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(12) D=n942_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(11) D=n942_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(10) D=n942_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(9) D=n942_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(8) D=n942_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(7) D=n942_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n942(6) D=n942_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4479.1-4484.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_I1 I2=n918(7) I3=n888(7) O=n942_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_1_I1 I2=n918(6) I3=n888(6) O=n942_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_10_I1 I2=n935(4) I3=n896(4) O=n942_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n896(3) I2=n935(3) I3=n942_ff_CQZ_D_LUT4_O_11_I1 O=n942_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_11_I1 I2=n935(3) I3=n896(3) O=n942_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n896(2) I2=n935(2) I3=n942_ff_CQZ_D_LUT4_O_12_I1 O=n942_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_12_I1 I2=n935(2) I3=n896(2) O=n942_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n935(1) I1=n896(1) I2=n896(0) I3=n935(0) O=n942_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n942_ff_CQZ_D_LUT4_O_13_I3 O=n942_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n935(0) I1=n896(0) I2=n935(1) I3=n896(1) O=n942_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n1019 I1=n888(0) I2=n918(0) I3=n2062 O=n942_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n896(0) I2=n935(0) I3=n2062 O=n942_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=n1019 I1=n888(5) I2=n918(5) I3=n942_ff_CQZ_D_LUT4_O_2_I1 O=n942_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_2_I1 I2=n918(5) I3=n888(5) O=n942_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n888(4) I2=n918(4) I3=n942_ff_CQZ_D_LUT4_O_3_I1 O=n942_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_3_I1 I2=n918(4) I3=n888(4) O=n942_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n888(3) I2=n918(3) I3=n942_ff_CQZ_D_LUT4_O_4_I1 O=n942_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_4_I1 I2=n918(3) I3=n888(3) O=n942_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n888(2) I2=n918(2) I3=n942_ff_CQZ_D_LUT4_O_5_I1 O=n942_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_5_I1 I2=n918(2) I3=n888(2) O=n942_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n918(1) I1=n888(1) I2=n888(0) I3=n918(0) O=n942_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n942_ff_CQZ_D_LUT4_O_6_I3 O=n942_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n918(0) I1=n888(0) I2=n918(1) I3=n888(1) O=n942_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_7_I1 I2=n935(7) I3=n896(7) O=n942_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n896(6) I2=n935(6) I3=n942_ff_CQZ_D_LUT4_O_8_I1 O=n942_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_8_I1 I2=n935(6) I3=n896(6) O=n942_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n896(5) I2=n935(5) I3=n942_ff_CQZ_D_LUT4_O_9_I1 O=n942_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n2062 I1=n942_ff_CQZ_D_LUT4_O_9_I1 I2=n935(5) I3=n896(5) O=n942_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=n1019 I1=n896(4) I2=n935(4) I3=n942_ff_CQZ_D_LUT4_O_10_I1 O=n942_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=n1019 I1=n888(6) I2=n918(6) I3=n942_ff_CQZ_D_LUT4_O_1_I1 O=n942_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt ff CQZ=n949(15) D=n949_ff_CQZ_D(15) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(14) D=n949_ff_CQZ_D(14) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(5) D=n949_ff_CQZ_D(5) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(4) D=n949_ff_CQZ_D(4) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(3) D=n949_ff_CQZ_D(3) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(2) D=n949_ff_CQZ_D(2) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(1) D=n949_ff_CQZ_D(1) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(0) D=n942_ff_CQZ_D(0) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(13) D=n949_ff_CQZ_D(13) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(12) D=n949_ff_CQZ_D(12) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(11) D=n949_ff_CQZ_D(11) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(10) D=n949_ff_CQZ_D(10) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(9) D=n949_ff_CQZ_D(9) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(8) D=n942_ff_CQZ_D(8) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(7) D=n949_ff_CQZ_D(7) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n949(6) D=n949_ff_CQZ_D(6) QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4485.1-4490.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_I1 I2=n918(7) I3=n888(7) O=n949_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_1_I1 I2=n918(6) I3=n888(6) O=n949_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_10_I1 I2=n935(4) I3=n896(4) O=n949_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n896(3) I2=n935(3) I3=n949_ff_CQZ_D_LUT4_O_11_I1 O=n949_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_11_I1 I2=n935(3) I3=n896(3) O=n949_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n896(2) I2=n935(2) I3=n949_ff_CQZ_D_LUT4_O_12_I1 O=n949_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_12_I1 I2=n935(2) I3=n896(2) O=n949_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n935(1) I1=n896(1) I2=n896(0) I3=n935(0) O=n949_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n949_ff_CQZ_D_LUT4_O_13_I3 O=n949_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n896(0) I1=n935(0) I2=n935(1) I3=n896(1) O=n949_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n1019 I1=n888(5) I2=n918(5) I3=n949_ff_CQZ_D_LUT4_O_2_I1 O=n949_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_2_I1 I2=n918(5) I3=n888(5) O=n949_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n888(4) I2=n918(4) I3=n949_ff_CQZ_D_LUT4_O_3_I1 O=n949_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_3_I1 I2=n918(4) I3=n888(4) O=n949_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n888(3) I2=n918(3) I3=n949_ff_CQZ_D_LUT4_O_4_I1 O=n949_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_4_I1 I2=n918(3) I3=n888(3) O=n949_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n888(2) I2=n918(2) I3=n949_ff_CQZ_D_LUT4_O_5_I1 O=n949_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_5_I1 I2=n918(2) I3=n888(2) O=n949_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n918(1) I1=n888(1) I2=n888(0) I3=n918(0) O=n949_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n949_ff_CQZ_D_LUT4_O_6_I3 O=n949_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n888(0) I1=n918(0) I2=n918(1) I3=n888(1) O=n949_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_7_I1 I2=n935(7) I3=n896(7) O=n949_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n896(6) I2=n935(6) I3=n949_ff_CQZ_D_LUT4_O_8_I1 O=n949_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_8_I1 I2=n935(6) I3=n896(6) O=n949_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n896(5) I2=n935(5) I3=n949_ff_CQZ_D_LUT4_O_9_I1 O=n949_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n2062 I1=n949_ff_CQZ_D_LUT4_O_9_I1 I2=n935(5) I3=n896(5) O=n949_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=n1019 I1=n896(4) I2=n935(4) I3=n949_ff_CQZ_D_LUT4_O_10_I1 O=n949_ff_CQZ_D_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n888(6) I2=n918(6) I3=n949_ff_CQZ_D_LUT4_O_1_I1 O=n949_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=n1019 I1=n1019 I2=n954 I3=n2062 O=n958_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n954 D=n954_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4491.1-4496.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n958 I3=n2062 O=n962_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n958 D=n958_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4497.1-4502.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n962 I3=n2062 O=n966_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n962 D=n962_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4503.1-4508.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n1008(1) O=n966_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=n966_LUT4_I3_O I2=n1006(4) I3=n966_LUT4_I3_O_LUT4_I1_I3 O=n966_LUT4_I3_O_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n966_LUT4_I3_O I2=n1006(1) I3=n1006(0) O=n966_LUT4_I3_O_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1006(0) I1=n1006(1) I2=n1006(2) I3=n1006(3) O=n966_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=n1019 I1=n1019 I2=n966_LUT4_I3_O I3=n966_LUT4_I3_O_LUT4_I2_I3 O=n966_LUT4_I3_O_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n966_LUT4_I3_O I3=n1006(0) O=n966_LUT4_I3_O_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1006(0) I1=n1006(1) I2=n1006(2) I3=n1006(3) O=n966_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n966_LUT4_I3_O_LUT4_I1_I3 I1=n1006(4) I2=n1006(5) I3=n966_LUT4_I3_O O=n966_LUT4_I3_O_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n1006(0) I1=n1006(1) I2=n1006(2) I3=n966_LUT4_I3_O O=n966_LUT4_I3_O_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=n1008(1) D=n966_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4509.1-4514.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=n853(0) D=n866_LUT4_I1_I2_LUT4_O_I3_LUT4_I3_O(0) QCK=$iopadmap$clock_c QEN=n2091 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4377.1-4382.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n988 I3=n2062 O=n992_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n988 D=n988_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4539.1-4544.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n853(0) I3=n2062 O=n988_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n992 I3=n2062 O=n996_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n992 D=n992_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4545.1-4550.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n1019 I1=n1019 I2=n996 I3=n2062 O=n1000_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=n996 D=n996_ff_CQZ_D QCK=$iopadmap$clock_c QEN=n2059 QRT=n1019 QST=n1019
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/cf_fft_256_8/rtl/cf_fft_256_8.v:4551.1-4556.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=n26_LUT4_I2_I3 I1=n17(0) I2=n14(1) I3=n2062 O=n26_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=n1019 I1=n1019 I2=n2062 I3=n14(1) O=sync_i_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=n1019 I1=sync_i_LUT4_I3_O I2=n11(4) I3=n29_LUT4_I1_I0 O=sync_i_LUT4_I3_O_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=sync_i_LUT4_I3_O I2=n11(1) I3=n11(0) O=sync_i_LUT4_I3_O_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=n1019 I1=n1019 I2=sync_i_LUT4_I3_O I3=n29_LUT4_I3_O O=sync_i_LUT4_I3_O_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n1019 I1=n1019 I2=sync_i_LUT4_I3_O I3=sync_i_LUT4_I3_O_LUT4_I2_1_I3 O=sync_i_LUT4_I3_O_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n11(0) I1=n11(1) I2=n11(2) I3=n11(3) O=sync_i_LUT4_I3_O_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=n1019 I1=n1019 I2=sync_i_LUT4_I3_O I3=n11(0) O=sync_i_LUT4_I3_O_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=n29_LUT4_I1_I0 I1=n11(4) I2=n11(5) I3=sync_i_LUT4_I3_O O=sync_i_LUT4_I3_O_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=n11(0) I1=n11(1) I2=n11(2) I3=sync_i_LUT4_I3_O O=sync_i_LUT4_I3_O_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.end
diff --git a/BENCHMARK/cf_fft_256_8/rtl/cf_fft_256_8.v b/BENCHMARK/cf_fft_256_8/rtl/cf_fft_256_8.v
new file mode 100644
index 0000000..c12ce4c
--- /dev/null
+++ b/BENCHMARK/cf_fft_256_8/rtl/cf_fft_256_8.v
@@ -0,0 +1,5959 @@
+//
+//  Copyright (c) 2003 Launchbird Design Systems, Inc.
+//  All rights reserved.
+//  
+//  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+//    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+//    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+//  
+//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+//  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+//  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+//  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  
+//  
+//  Overview:
+//  
+//    Performs a radix 2 Fast Fourier Transform.
+//    The FFT architecture is pipelined on a rank basis; each rank has its own butterfly and ranks are
+//    isolated from each other using memory interleavers.  This FFT can perform calcualations on continuous
+//    streaming data (one data set right after another).  More over, inputs and outputs are passed in pairs,
+//    doubling the bandwidth.  For instance, a 2048 point FFT can perform a transform every 1024 cycles.
+//  
+//  Interface:
+//  
+//    Synchronization:
+//      clock_c  : Clock input.
+//      enable_i : Synchronous enable.
+//      reset_i  : Synchronous reset.
+//  
+//    Inputs:
+//      sync_i     : Input sync pulse must occur one frame prior to data input.
+//      data_0_i   : Input data 0.  Width is 2 * precision.  Real on the left, imag on the right.
+//      data_1_i   : Input data 1.  Width is 2 * precision.  Real on the left, imag on the right.
+//  
+//    Outputs:
+//      sync_o     : Output sync pulse occurs one frame before data output.
+//      data_0_o   : Output data 0.  Width is 2 * precision.  Real on the left, imag on the right.
+//      data_1_o   : Output data 1.  Width is 2 * precision.  Real on the left, imag on the right.
+//  
+//  Built In Parameters:
+//  
+//    FFT Points   = 256
+//    Precision    = 8
+//  
+//  
+//  
+//  
+//  Generated by Confluence 0.3.0  --  Launchbird Design Systems, Inc.  --  www.launchbird.com
+//  
+//  Interface
+//  
+//    Build Name    : cf_fft_256_8
+//    Clock Domains : clock_c  
+//    Input  : enable_i(1)
+//    Input  : reset_i(1)
+//    Input  : sync_i(1)
+//    Input  : data_0_i(16)
+//    Input  : data_1_i(16)
+//    Output : sync_o(1)
+//    Output : data_0_o(16)
+//    Output : data_1_o(16)
+//  
+//  
+//  
+
+module cf_fft_256_8 (clock_c, enable_i, reset_i, sync_i, data_0_i, data_1_i, sync_o, data_0_o, data_1_o);
+input  clock_c;
+input  enable_i;
+input  reset_i;
+input  sync_i;
+input  [15:0] data_0_i;
+input  [15:0] data_1_i;
+output sync_o;
+output [15:0] data_0_o;
+output [15:0] data_1_o;
+wire   [6:0] n4;
+wire   [6:0] n7;
+wire   n8;
+wire   [6:0] n12;
+wire   n13;
+wire   [1:0] n14;
+wire   n15;
+wire   [2:0] n17;
+wire   n18;
+wire   n19;
+wire   n27;
+wire   [31:0] n28;
+wire   n29;
+wire   n30;
+wire   [5:0] n31;
+wire   [5:0] n32;
+wire   [5:0] n33;
+wire   [5:0] n36;
+wire   [1:0] n41;
+wire   n42;
+wire   n43;
+wire   n47;
+wire   n53;
+wire   [1:0] n54;
+wire   [2:0] n55;
+wire   [3:0] n56;
+wire   [4:0] n57;
+wire   [5:0] n58;
+wire   n59;
+wire   n60;
+wire   n65;
+wire   [31:0] n73;
+wire   [5:0] n75;
+wire   [1:0] n80;
+wire   n81;
+wire   n82;
+wire   n86;
+wire   n98;
+wire   n102;
+wire   [31:0] n110;
+wire   [1:0] n111;
+wire   [2:0] n113;
+wire   n114;
+wire   n115;
+wire   [15:0] n119;
+wire   [15:0] n120;
+wire   [15:0] n121;
+wire   [15:0] n122;
+wire   [15:0] n123;
+wire   [15:0] n124;
+wire   [6:0] n126;
+wire   n130;
+wire   [1:0] n131;
+wire   [2:0] n133;
+wire   n134;
+wire   n135;
+wire   n143;
+wire   [7:0] n149;
+wire   [7:0] n150;
+wire   [7:0] n155;
+wire   [7:0] n156;
+wire   [7:0] n177;
+wire   [7:0] n178;
+wire   [15:0] n179;
+wire   [7:0] n180;
+wire   [15:0] n185;
+wire   [7:0] n186;
+wire   [7:0] n191;
+wire   [15:0] n196;
+wire   [7:0] n197;
+wire   [15:0] n202;
+wire   [7:0] n203;
+wire   [7:0] n208;
+wire   [7:0] n213;
+wire   [7:0] n214;
+wire   [15:0] n215;
+wire   [7:0] n220;
+wire   [7:0] n221;
+wire   [15:0] n222;
+wire   [31:0] n227;
+wire   [5:0] n244;
+wire   n261;
+wire   n278;
+wire   [5:0] n280;
+wire   [1:0] n285;
+wire   n286;
+wire   n287;
+wire   n291;
+wire   n296;
+wire   [1:0] n297;
+wire   [2:0] n298;
+wire   [3:0] n299;
+wire   [4:0] n300;
+wire   [5:0] n301;
+wire   n302;
+wire   n303;
+wire   n307;
+wire   [31:0] n315;
+wire   [5:0] n317;
+wire   [1:0] n322;
+wire   n323;
+wire   n324;
+wire   n328;
+wire   n340;
+wire   n344;
+wire   [31:0] n352;
+wire   [1:0] n353;
+wire   [2:0] n355;
+wire   n356;
+wire   n357;
+wire   [15:0] n361;
+wire   [15:0] n362;
+wire   [15:0] n363;
+wire   [15:0] n364;
+wire   [15:0] n365;
+wire   [15:0] n366;
+wire   [6:0] n368;
+wire   n372;
+wire   [1:0] n373;
+wire   [2:0] n375;
+wire   n376;
+wire   n377;
+wire   n385;
+wire   n386;
+wire   [7:0] n391;
+wire   [7:0] n392;
+wire   [7:0] n397;
+wire   [7:0] n398;
+wire   [7:0] n418;
+wire   [7:0] n419;
+wire   [15:0] n420;
+wire   [7:0] n421;
+wire   [15:0] n426;
+wire   [7:0] n427;
+wire   [7:0] n432;
+wire   [15:0] n437;
+wire   [7:0] n438;
+wire   [15:0] n443;
+wire   [7:0] n444;
+wire   [7:0] n449;
+wire   [7:0] n454;
+wire   [7:0] n455;
+wire   [15:0] n456;
+wire   [7:0] n461;
+wire   [7:0] n462;
+wire   [15:0] n463;
+wire   [31:0] n468;
+wire   [5:0] n485;
+wire   n502;
+wire   n519;
+wire   [5:0] n521;
+wire   [1:0] n526;
+wire   n527;
+wire   n528;
+wire   n532;
+wire   n537;
+wire   [1:0] n538;
+wire   [2:0] n539;
+wire   [3:0] n540;
+wire   [4:0] n541;
+wire   [5:0] n542;
+wire   n543;
+wire   n544;
+wire   n548;
+wire   [31:0] n556;
+wire   [5:0] n558;
+wire   [1:0] n563;
+wire   n564;
+wire   n565;
+wire   n569;
+wire   n581;
+wire   n585;
+wire   [31:0] n593;
+wire   [1:0] n594;
+wire   [2:0] n596;
+wire   n597;
+wire   n598;
+wire   [15:0] n602;
+wire   [15:0] n603;
+wire   [15:0] n604;
+wire   [15:0] n605;
+wire   [15:0] n606;
+wire   [15:0] n607;
+wire   [6:0] n609;
+wire   n613;
+wire   [1:0] n614;
+wire   [2:0] n616;
+wire   n617;
+wire   n618;
+wire   n626;
+wire   [1:0] n627;
+wire   [7:0] n632;
+wire   [7:0] n633;
+wire   [7:0] n638;
+wire   [7:0] n639;
+wire   [7:0] n659;
+wire   [7:0] n660;
+wire   [15:0] n661;
+wire   [7:0] n662;
+wire   [15:0] n667;
+wire   [7:0] n668;
+wire   [7:0] n673;
+wire   [15:0] n678;
+wire   [7:0] n679;
+wire   [15:0] n684;
+wire   [7:0] n685;
+wire   [7:0] n690;
+wire   [7:0] n695;
+wire   [7:0] n696;
+wire   [15:0] n697;
+wire   [7:0] n702;
+wire   [7:0] n703;
+wire   [15:0] n704;
+wire   [31:0] n709;
+wire   [5:0] n726;
+wire   n743;
+wire   n760;
+wire   [5:0] n762;
+wire   [1:0] n767;
+wire   n768;
+wire   n769;
+wire   n773;
+wire   n778;
+wire   [1:0] n779;
+wire   [2:0] n780;
+wire   [3:0] n781;
+wire   [4:0] n782;
+wire   [5:0] n783;
+wire   n784;
+wire   n785;
+wire   n789;
+wire   [31:0] n797;
+wire   [5:0] n799;
+wire   [1:0] n804;
+wire   n805;
+wire   n806;
+wire   n810;
+wire   n822;
+wire   n826;
+wire   [31:0] n834;
+wire   [1:0] n835;
+wire   [2:0] n837;
+wire   n838;
+wire   n839;
+wire   [15:0] n843;
+wire   [15:0] n844;
+wire   [15:0] n845;
+wire   [15:0] n846;
+wire   [15:0] n847;
+wire   [15:0] n848;
+wire   [6:0] n850;
+wire   n854;
+wire   [1:0] n855;
+wire   [2:0] n857;
+wire   n858;
+wire   n859;
+wire   n867;
+wire   [2:0] n868;
+wire   [7:0] n873;
+wire   [7:0] n874;
+wire   [7:0] n879;
+wire   [7:0] n880;
+wire   [7:0] n900;
+wire   [7:0] n901;
+wire   [15:0] n902;
+wire   [7:0] n903;
+wire   [15:0] n908;
+wire   [7:0] n909;
+wire   [7:0] n914;
+wire   [15:0] n919;
+wire   [7:0] n920;
+wire   [15:0] n925;
+wire   [7:0] n926;
+wire   [7:0] n931;
+wire   [7:0] n936;
+wire   [7:0] n937;
+wire   [15:0] n938;
+wire   [7:0] n943;
+wire   [7:0] n944;
+wire   [15:0] n945;
+wire   [31:0] n950;
+wire   [5:0] n967;
+wire   n984;
+wire   n1001;
+wire   [5:0] n1003;
+wire   [1:0] n1008;
+wire   n1009;
+wire   n1010;
+wire   n1014;
+wire   n1019;
+wire   [1:0] n1020;
+wire   [2:0] n1021;
+wire   [3:0] n1022;
+wire   [4:0] n1023;
+wire   [5:0] n1024;
+wire   n1025;
+wire   n1026;
+wire   n1030;
+wire   [31:0] n1038;
+wire   [5:0] n1040;
+wire   [1:0] n1045;
+wire   n1046;
+wire   n1047;
+wire   n1051;
+wire   n1063;
+wire   n1067;
+wire   [31:0] n1075;
+wire   [1:0] n1076;
+wire   [2:0] n1078;
+wire   n1079;
+wire   n1080;
+wire   [15:0] n1084;
+wire   [15:0] n1085;
+wire   [15:0] n1086;
+wire   [15:0] n1087;
+wire   [15:0] n1088;
+wire   [15:0] n1089;
+wire   [6:0] n1091;
+wire   n1095;
+wire   [1:0] n1096;
+wire   [2:0] n1098;
+wire   n1099;
+wire   n1100;
+wire   n1108;
+wire   [3:0] n1109;
+wire   [7:0] n1114;
+wire   [7:0] n1115;
+wire   [7:0] n1120;
+wire   [7:0] n1121;
+wire   [7:0] n1141;
+wire   [7:0] n1142;
+wire   [15:0] n1143;
+wire   [7:0] n1144;
+wire   [15:0] n1149;
+wire   [7:0] n1150;
+wire   [7:0] n1155;
+wire   [15:0] n1160;
+wire   [7:0] n1161;
+wire   [15:0] n1166;
+wire   [7:0] n1167;
+wire   [7:0] n1172;
+wire   [7:0] n1177;
+wire   [7:0] n1178;
+wire   [15:0] n1179;
+wire   [7:0] n1184;
+wire   [7:0] n1185;
+wire   [15:0] n1186;
+wire   [31:0] n1191;
+wire   [5:0] n1208;
+wire   n1225;
+wire   n1242;
+wire   [5:0] n1244;
+wire   [1:0] n1249;
+wire   n1250;
+wire   n1251;
+wire   n1255;
+wire   n1260;
+wire   [1:0] n1261;
+wire   [2:0] n1262;
+wire   [3:0] n1263;
+wire   [4:0] n1264;
+wire   [5:0] n1265;
+wire   n1266;
+wire   n1267;
+wire   n1271;
+wire   [31:0] n1279;
+wire   [5:0] n1281;
+wire   [1:0] n1286;
+wire   n1287;
+wire   n1288;
+wire   n1292;
+wire   n1304;
+wire   n1308;
+wire   [31:0] n1316;
+wire   [1:0] n1317;
+wire   [2:0] n1319;
+wire   n1320;
+wire   n1321;
+wire   [15:0] n1325;
+wire   [15:0] n1326;
+wire   [15:0] n1327;
+wire   [15:0] n1328;
+wire   [15:0] n1329;
+wire   [15:0] n1330;
+wire   [6:0] n1332;
+wire   n1336;
+wire   [1:0] n1337;
+wire   [2:0] n1339;
+wire   n1340;
+wire   n1341;
+wire   n1349;
+wire   [4:0] n1350;
+wire   [7:0] n1355;
+wire   [7:0] n1356;
+wire   [7:0] n1361;
+wire   [7:0] n1362;
+wire   [7:0] n1382;
+wire   [7:0] n1383;
+wire   [15:0] n1384;
+wire   [7:0] n1385;
+wire   [15:0] n1390;
+wire   [7:0] n1391;
+wire   [7:0] n1396;
+wire   [15:0] n1401;
+wire   [7:0] n1402;
+wire   [15:0] n1407;
+wire   [7:0] n1408;
+wire   [7:0] n1413;
+wire   [7:0] n1418;
+wire   [7:0] n1419;
+wire   [15:0] n1420;
+wire   [7:0] n1425;
+wire   [7:0] n1426;
+wire   [15:0] n1427;
+wire   [31:0] n1432;
+wire   [5:0] n1449;
+wire   n1466;
+wire   n1483;
+wire   [5:0] n1485;
+wire   [1:0] n1490;
+wire   n1491;
+wire   n1492;
+wire   n1496;
+wire   n1501;
+wire   [1:0] n1502;
+wire   [2:0] n1503;
+wire   [3:0] n1504;
+wire   [4:0] n1505;
+wire   [5:0] n1506;
+wire   n1507;
+wire   n1508;
+wire   n1512;
+wire   [31:0] n1520;
+wire   [5:0] n1522;
+wire   [1:0] n1527;
+wire   n1528;
+wire   n1529;
+wire   n1533;
+wire   n1545;
+wire   n1549;
+wire   [31:0] n1557;
+wire   [1:0] n1558;
+wire   [2:0] n1560;
+wire   n1561;
+wire   n1562;
+wire   [15:0] n1566;
+wire   [15:0] n1567;
+wire   [15:0] n1568;
+wire   [15:0] n1569;
+wire   [15:0] n1570;
+wire   [15:0] n1571;
+wire   [6:0] n1573;
+wire   n1577;
+wire   [1:0] n1578;
+wire   [2:0] n1580;
+wire   n1581;
+wire   n1582;
+wire   n1590;
+wire   [5:0] n1591;
+wire   [7:0] n1596;
+wire   [7:0] n1597;
+wire   [7:0] n1602;
+wire   [7:0] n1603;
+wire   [7:0] n1623;
+wire   [7:0] n1624;
+wire   [15:0] n1625;
+wire   [7:0] n1626;
+wire   [15:0] n1631;
+wire   [7:0] n1632;
+wire   [7:0] n1637;
+wire   [15:0] n1642;
+wire   [7:0] n1643;
+wire   [15:0] n1648;
+wire   [7:0] n1649;
+wire   [7:0] n1654;
+wire   [7:0] n1659;
+wire   [7:0] n1660;
+wire   [15:0] n1661;
+wire   [7:0] n1666;
+wire   [7:0] n1667;
+wire   [15:0] n1668;
+wire   [31:0] n1673;
+wire   [5:0] n1690;
+wire   n1707;
+wire   n1724;
+wire   [5:0] n1726;
+wire   [1:0] n1731;
+wire   n1732;
+wire   n1733;
+wire   n1737;
+wire   n1742;
+wire   [1:0] n1743;
+wire   [2:0] n1744;
+wire   [3:0] n1745;
+wire   [4:0] n1746;
+wire   [5:0] n1747;
+wire   n1748;
+wire   n1749;
+wire   n1753;
+wire   [31:0] n1761;
+wire   [5:0] n1763;
+wire   [1:0] n1768;
+wire   n1769;
+wire   n1770;
+wire   n1774;
+wire   n1786;
+wire   n1790;
+wire   [31:0] n1798;
+wire   [1:0] n1799;
+wire   [2:0] n1801;
+wire   n1802;
+wire   n1803;
+wire   [15:0] n1807;
+wire   [15:0] n1808;
+wire   [15:0] n1809;
+wire   [15:0] n1810;
+wire   [15:0] n1811;
+wire   [15:0] n1812;
+wire   [6:0] n1814;
+wire   n1818;
+wire   [1:0] n1819;
+wire   [2:0] n1821;
+wire   n1822;
+wire   n1823;
+wire   n1831;
+wire   [6:0] n1832;
+wire   [7:0] n1837;
+wire   [7:0] n1838;
+wire   [7:0] n1843;
+wire   [7:0] n1844;
+wire   [7:0] n1864;
+wire   [7:0] n1865;
+wire   [15:0] n1866;
+wire   [7:0] n1867;
+wire   [15:0] n1872;
+wire   [7:0] n1873;
+wire   [7:0] n1878;
+wire   [15:0] n1883;
+wire   [7:0] n1884;
+wire   [15:0] n1889;
+wire   [7:0] n1890;
+wire   [7:0] n1895;
+wire   [7:0] n1900;
+wire   [7:0] n1901;
+wire   [15:0] n1902;
+wire   [7:0] n1907;
+wire   [7:0] n1908;
+wire   [15:0] n1909;
+wire   [31:0] n1914;
+wire   [5:0] n1931;
+wire   n1948;
+wire   n1965;
+wire   [5:0] n1967;
+wire   [1:0] n1972;
+wire   n1973;
+wire   n1974;
+wire   n1978;
+wire   n1983;
+wire   [1:0] n1984;
+wire   [2:0] n1985;
+wire   [3:0] n1986;
+wire   [4:0] n1987;
+wire   [5:0] n1988;
+wire   n1989;
+wire   n1990;
+wire   n1994;
+wire   [31:0] n2002;
+wire   [5:0] n2004;
+wire   [1:0] n2009;
+wire   n2010;
+wire   n2011;
+wire   n2015;
+wire   n2027;
+wire   n2031;
+wire   [31:0] n2039;
+wire   [1:0] n2040;
+wire   [2:0] n2042;
+wire   n2043;
+wire   n2044;
+wire   [15:0] n2048;
+wire   [15:0] n2049;
+wire   [15:0] n2050;
+wire   [15:0] n2051;
+wire   [15:0] n2052;
+wire   [15:0] n2053;
+wire   n2059;
+wire   n2060;
+wire   n2061;
+wire   n2062;
+wire   n2063;
+wire   n2064;
+wire   n2065;
+wire   n2066;
+wire   n2067;
+wire   n2068;
+wire   n2069;
+wire   n2070;
+wire   n2071;
+wire   n2072;
+wire   n2073;
+wire   n2074;
+wire   n2075;
+wire   n2076;
+wire   n2077;
+wire   n2078;
+wire   n2079;
+wire   n2080;
+wire   n2081;
+wire   n2082;
+wire   n2083;
+wire   n2084;
+wire   n2085;
+wire   n2086;
+wire   n2087;
+wire   n2088;
+wire   n2089;
+wire   n2090;
+wire   n2091;
+wire   n2092;
+wire   n2093;
+wire   n2094;
+wire   n2095;
+wire   n2096;
+wire   n2097;
+wire   n2098;
+wire   n2099;
+wire   n2100;
+wire   n2101;
+wire   n2102;
+wire   n2103;
+wire   n2104;
+wire   n2105;
+wire   n2106;
+wire   n2107;
+wire   n2108;
+wire   n2109;
+wire   n2110;
+wire   n2111;
+wire   n2112;
+wire   n2113;
+wire   n2114;
+wire   n2115;
+wire   n2116;
+reg    [6:0] n11;
+reg    n22;
+reg    n26;
+reg    [5:0] n39;
+reg    n46;
+reg    n51;
+wire   [31:0] n64;
+reg    [5:0] n64ra;
+reg    [31:0] n64m ;
+wire   [31:0] n68;
+reg    [5:0] n68ra;
+reg    [31:0] n68m ;
+reg    n72;
+reg    [5:0] n78;
+reg    n85;
+wire   [31:0] n101;
+reg    [5:0] n101ra;
+reg    [31:0] n101m ;
+wire   [31:0] n105;
+reg    [5:0] n105ra;
+reg    [31:0] n105m ;
+reg    n109;
+reg    n118;
+reg    [6:0] n129;
+reg    n138;
+reg    n142;
+reg    [15:0] n148;
+reg    [15:0] n154;
+reg    [7:0] n161;
+reg    [7:0] n165;
+reg    [7:0] n169;
+reg    [7:0] n173;
+reg    [15:0] n176;
+reg    [7:0] n184;
+reg    [7:0] n190;
+reg    [7:0] n195;
+reg    [7:0] n201;
+reg    [7:0] n207;
+reg    [7:0] n212;
+reg    [15:0] n219;
+reg    [15:0] n226;
+reg    n231;
+reg    n235;
+reg    n239;
+reg    n243;
+reg    [5:0] n248;
+reg    [5:0] n252;
+reg    [5:0] n256;
+reg    [5:0] n260;
+reg    n265;
+reg    n269;
+reg    n273;
+reg    n277;
+reg    [5:0] n283;
+reg    n290;
+reg    n295;
+wire   [31:0] n306;
+reg    [5:0] n306ra;
+reg    [31:0] n306m ;
+wire   [31:0] n310;
+reg    [5:0] n310ra;
+reg    [31:0] n310m ;
+reg    n314;
+reg    [5:0] n320;
+reg    n327;
+wire   [31:0] n343;
+reg    [5:0] n343ra;
+reg    [31:0] n343m ;
+wire   [31:0] n347;
+reg    [5:0] n347ra;
+reg    [31:0] n347m ;
+reg    n351;
+reg    n360;
+reg    [6:0] n371;
+reg    n380;
+reg    n384;
+reg    [15:0] n390;
+reg    [15:0] n396;
+reg    [7:0] n402;
+reg    [7:0] n406;
+reg    [7:0] n410;
+reg    [7:0] n414;
+reg    [15:0] n417;
+reg    [7:0] n425;
+reg    [7:0] n431;
+reg    [7:0] n436;
+reg    [7:0] n442;
+reg    [7:0] n448;
+reg    [7:0] n453;
+reg    [15:0] n460;
+reg    [15:0] n467;
+reg    n472;
+reg    n476;
+reg    n480;
+reg    n484;
+reg    [5:0] n489;
+reg    [5:0] n493;
+reg    [5:0] n497;
+reg    [5:0] n501;
+reg    n506;
+reg    n510;
+reg    n514;
+reg    n518;
+reg    [5:0] n524;
+reg    n531;
+reg    n536;
+wire   [31:0] n547;
+reg    [5:0] n547ra;
+reg    [31:0] n547m ;
+wire   [31:0] n551;
+reg    [5:0] n551ra;
+reg    [31:0] n551m ;
+reg    n555;
+reg    [5:0] n561;
+reg    n568;
+wire   [31:0] n584;
+reg    [5:0] n584ra;
+reg    [31:0] n584m ;
+wire   [31:0] n588;
+reg    [5:0] n588ra;
+reg    [31:0] n588m ;
+reg    n592;
+reg    n601;
+reg    [6:0] n612;
+reg    n621;
+reg    n625;
+reg    [15:0] n631;
+reg    [15:0] n637;
+reg    [7:0] n643;
+reg    [7:0] n647;
+reg    [7:0] n651;
+reg    [7:0] n655;
+reg    [15:0] n658;
+reg    [7:0] n666;
+reg    [7:0] n672;
+reg    [7:0] n677;
+reg    [7:0] n683;
+reg    [7:0] n689;
+reg    [7:0] n694;
+reg    [15:0] n701;
+reg    [15:0] n708;
+reg    n713;
+reg    n717;
+reg    n721;
+reg    n725;
+reg    [5:0] n730;
+reg    [5:0] n734;
+reg    [5:0] n738;
+reg    [5:0] n742;
+reg    n747;
+reg    n751;
+reg    n755;
+reg    n759;
+reg    [5:0] n765;
+reg    n772;
+reg    n777;
+wire   [31:0] n788;
+reg    [5:0] n788ra;
+reg    [31:0] n788m ;
+wire   [31:0] n792;
+reg    [5:0] n792ra;
+reg    [31:0] n792m ;
+reg    n796;
+reg    [5:0] n802;
+reg    n809;
+wire   [31:0] n825;
+reg    [5:0] n825ra;
+reg    [31:0] n825m ;
+wire   [31:0] n829;
+reg    [5:0] n829ra;
+reg    [31:0] n829m ;
+reg    n833;
+reg    n842;
+reg    [6:0] n853;
+reg    n862;
+reg    n866;
+reg    [15:0] n872;
+reg    [15:0] n878;
+reg    [7:0] n884;
+reg    [7:0] n888;
+reg    [7:0] n892;
+reg    [7:0] n896;
+reg    [15:0] n899;
+reg    [7:0] n907;
+reg    [7:0] n913;
+reg    [7:0] n918;
+reg    [7:0] n924;
+reg    [7:0] n930;
+reg    [7:0] n935;
+reg    [15:0] n942;
+reg    [15:0] n949;
+reg    n954;
+reg    n958;
+reg    n962;
+reg    n966;
+reg    [5:0] n971;
+reg    [5:0] n975;
+reg    [5:0] n979;
+reg    [5:0] n983;
+reg    n988;
+reg    n992;
+reg    n996;
+reg    n1000;
+reg    [5:0] n1006;
+reg    n1013;
+reg    n1018;
+wire   [31:0] n1029;
+reg    [5:0] n1029ra;
+reg    [31:0] n1029m ;
+wire   [31:0] n1033;
+reg    [5:0] n1033ra;
+reg    [31:0] n1033m ;
+reg    n1037;
+reg    [5:0] n1043;
+reg    n1050;
+wire   [31:0] n1066;
+reg    [5:0] n1066ra;
+reg    [31:0] n1066m ;
+wire   [31:0] n1070;
+reg    [5:0] n1070ra;
+reg    [31:0] n1070m ;
+reg    n1074;
+reg    n1083;
+reg    [6:0] n1094;
+reg    n1103;
+reg    n1107;
+reg    [15:0] n1113;
+reg    [15:0] n1119;
+reg    [7:0] n1125;
+reg    [7:0] n1129;
+reg    [7:0] n1133;
+reg    [7:0] n1137;
+reg    [15:0] n1140;
+reg    [7:0] n1148;
+reg    [7:0] n1154;
+reg    [7:0] n1159;
+reg    [7:0] n1165;
+reg    [7:0] n1171;
+reg    [7:0] n1176;
+reg    [15:0] n1183;
+reg    [15:0] n1190;
+reg    n1195;
+reg    n1199;
+reg    n1203;
+reg    n1207;
+reg    [5:0] n1212;
+reg    [5:0] n1216;
+reg    [5:0] n1220;
+reg    [5:0] n1224;
+reg    n1229;
+reg    n1233;
+reg    n1237;
+reg    n1241;
+reg    [5:0] n1247;
+reg    n1254;
+reg    n1259;
+wire   [31:0] n1270;
+reg    [5:0] n1270ra;
+reg    [31:0] n1270m ;
+wire   [31:0] n1274;
+reg    [5:0] n1274ra;
+reg    [31:0] n1274m ;
+reg    n1278;
+reg    [5:0] n1284;
+reg    n1291;
+wire   [31:0] n1307;
+reg    [5:0] n1307ra;
+reg    [31:0] n1307m ;
+wire   [31:0] n1311;
+reg    [5:0] n1311ra;
+reg    [31:0] n1311m ;
+reg    n1315;
+reg    n1324;
+reg    [6:0] n1335;
+reg    n1344;
+reg    n1348;
+reg    [15:0] n1354;
+reg    [15:0] n1360;
+reg    [7:0] n1366;
+reg    [7:0] n1370;
+reg    [7:0] n1374;
+reg    [7:0] n1378;
+reg    [15:0] n1381;
+reg    [7:0] n1389;
+reg    [7:0] n1395;
+reg    [7:0] n1400;
+reg    [7:0] n1406;
+reg    [7:0] n1412;
+reg    [7:0] n1417;
+reg    [15:0] n1424;
+reg    [15:0] n1431;
+reg    n1436;
+reg    n1440;
+reg    n1444;
+reg    n1448;
+reg    [5:0] n1453;
+reg    [5:0] n1457;
+reg    [5:0] n1461;
+reg    [5:0] n1465;
+reg    n1470;
+reg    n1474;
+reg    n1478;
+reg    n1482;
+reg    [5:0] n1488;
+reg    n1495;
+reg    n1500;
+wire   [31:0] n1511;
+reg    [5:0] n1511ra;
+reg    [31:0] n1511m ;
+wire   [31:0] n1515;
+reg    [5:0] n1515ra;
+reg    [31:0] n1515m ;
+reg    n1519;
+reg    [5:0] n1525;
+reg    n1532;
+wire   [31:0] n1548;
+reg    [5:0] n1548ra;
+reg    [31:0] n1548m ;
+wire   [31:0] n1552;
+reg    [5:0] n1552ra;
+reg    [31:0] n1552m ;
+reg    n1556;
+reg    n1565;
+reg    [6:0] n1576;
+reg    n1585;
+reg    n1589;
+reg    [15:0] n1595;
+reg    [15:0] n1601;
+reg    [7:0] n1607;
+reg    [7:0] n1611;
+reg    [7:0] n1615;
+reg    [7:0] n1619;
+reg    [15:0] n1622;
+reg    [7:0] n1630;
+reg    [7:0] n1636;
+reg    [7:0] n1641;
+reg    [7:0] n1647;
+reg    [7:0] n1653;
+reg    [7:0] n1658;
+reg    [15:0] n1665;
+reg    [15:0] n1672;
+reg    n1677;
+reg    n1681;
+reg    n1685;
+reg    n1689;
+reg    [5:0] n1694;
+reg    [5:0] n1698;
+reg    [5:0] n1702;
+reg    [5:0] n1706;
+reg    n1711;
+reg    n1715;
+reg    n1719;
+reg    n1723;
+reg    [5:0] n1729;
+reg    n1736;
+reg    n1741;
+wire   [31:0] n1752;
+reg    [5:0] n1752ra;
+reg    [31:0] n1752m ;
+wire   [31:0] n1756;
+reg    [5:0] n1756ra;
+reg    [31:0] n1756m ;
+reg    n1760;
+reg    [5:0] n1766;
+reg    n1773;
+wire   [31:0] n1789;
+reg    [5:0] n1789ra;
+reg    [31:0] n1789m ;
+wire   [31:0] n1793;
+reg    [5:0] n1793ra;
+reg    [31:0] n1793m ;
+reg    n1797;
+reg    n1806;
+reg    [6:0] n1817;
+reg    n1826;
+reg    n1830;
+reg    [15:0] n1836;
+reg    [15:0] n1842;
+reg    [7:0] n1848;
+reg    [7:0] n1852;
+reg    [7:0] n1856;
+reg    [7:0] n1860;
+reg    [15:0] n1863;
+reg    [7:0] n1871;
+reg    [7:0] n1877;
+reg    [7:0] n1882;
+reg    [7:0] n1888;
+reg    [7:0] n1894;
+reg    [7:0] n1899;
+reg    [15:0] n1906;
+reg    [15:0] n1913;
+reg    n1918;
+reg    n1922;
+reg    n1926;
+reg    n1930;
+reg    [5:0] n1935;
+reg    [5:0] n1939;
+reg    [5:0] n1943;
+reg    [5:0] n1947;
+reg    n1952;
+reg    n1956;
+reg    n1960;
+reg    n1964;
+reg    [5:0] n1970;
+reg    n1977;
+reg    n1982;
+wire   [31:0] n1993;
+reg    [5:0] n1993ra;
+reg    [31:0] n1993m ;
+wire   [31:0] n1997;
+reg    [5:0] n1997ra;
+reg    [31:0] n1997m ;
+reg    n2001;
+reg    [5:0] n2007;
+reg    n2014;
+wire   [31:0] n2030;
+reg    [5:0] n2030ra;
+reg    [31:0] n2030m ;
+wire   [31:0] n2034;
+reg    [5:0] n2034ra;
+reg    [31:0] n2034m ;
+reg    n2038;
+reg    n2047;
+assign n4 = 7'b0000001;
+assign n7 = n11 + n4;
+assign n8 = 1'b0;
+assign n12 = 7'b1111111;
+assign n13 = n11 == n12;
+assign n14 = {sync_i, n13};
+assign n15 = 1'b1;
+assign n17 = {n14, n22};
+assign n18 =
+  n17 == 3'b000 ? n8 :
+  n17 == 3'b010 ? n8 :
+  n17 == 3'b100 ? n15 :
+  n17 == 3'b110 ? n15 :
+  n17 == 3'b001 ? n15 :
+  n17 == 3'b011 ? n8 :
+  n17 == 3'b101 ? n15 :
+  n15;
+assign n19 =
+  n17 == 3'b000 ? n8 :
+  n17 == 3'b010 ? n8 :
+  n17 == 3'b100 ? n15 :
+  n17 == 3'b110 ? n15 :
+  n17 == 3'b001 ? n15 :
+  n17 == 3'b011 ? n8 :
+  n17 == 3'b101 ? n15 :
+  n15;
+assign n27 = n26 & n13;
+assign n28 = {data_0_i, data_1_i};
+assign n29 = n11[6];
+assign n30 = ~n29;
+assign n31 = {n11[5],
+  n11[4],
+  n11[3],
+  n11[2],
+  n11[1],
+  n11[0]};
+assign n32 = {n31[0],
+  n31[1],
+  n31[2],
+  n31[3],
+  n31[4],
+  n31[5]};
+assign n33 = 6'b000001;
+assign n36 = n39 + n33;
+assign n41 = {n27, n46};
+assign n42 =
+  n41 == 2'b00 ? n8 :
+  n41 == 2'b10 ? n8 :
+  n41 == 2'b01 ? n15 :
+  n15;
+assign n43 =
+  n41 == 2'b00 ? n8 :
+  n41 == 2'b10 ? n15 :
+  n41 == 2'b01 ? n15 :
+  n8;
+assign n47 = ~n42;
+assign n53 = n8;
+assign n54 = {n8, n53};
+assign n55 = {n8, n54};
+assign n56 = {n8, n55};
+assign n57 = {n8, n56};
+assign n58 = {n8, n57};
+assign n59 = n39 == n58;
+assign n60 = n30 & n47;
+assign n65 = n30 & n42;
+assign n73 =
+  n72 == 1'b0 ? n64 :
+  n68;
+assign n75 = n78 + n33;
+assign n80 = {n27, n85};
+assign n81 =
+  n80 == 2'b00 ? n8 :
+  n80 == 2'b10 ? n8 :
+  n80 == 2'b01 ? n15 :
+  n15;
+assign n82 =
+  n80 == 2'b00 ? n8 :
+  n80 == 2'b10 ? n15 :
+  n80 == 2'b01 ? n15 :
+  n8;
+assign n86 = ~n81;
+assign n98 = n29 & n86;
+assign n102 = n29 & n81;
+assign n110 =
+  n109 == 1'b0 ? n101 :
+  n105;
+assign n111 = {n59, n51};
+assign n113 = {n111, n118};
+assign n114 =
+  n113 == 3'b000 ? n8 :
+  n113 == 3'b010 ? n8 :
+  n113 == 3'b100 ? n8 :
+  n113 == 3'b110 ? n8 :
+  n113 == 3'b001 ? n15 :
+  n113 == 3'b011 ? n15 :
+  n113 == 3'b101 ? n15 :
+  n15;
+assign n115 =
+  n113 == 3'b000 ? n8 :
+  n113 == 3'b010 ? n8 :
+  n113 == 3'b100 ? n15 :
+  n113 == 3'b110 ? n8 :
+  n113 == 3'b001 ? n15 :
+  n113 == 3'b011 ? n8 :
+  n113 == 3'b101 ? n15 :
+  n8;
+assign n119 = {n73[31],
+  n73[30],
+  n73[29],
+  n73[28],
+  n73[27],
+  n73[26],
+  n73[25],
+  n73[24],
+  n73[23],
+  n73[22],
+  n73[21],
+  n73[20],
+  n73[19],
+  n73[18],
+  n73[17],
+  n73[16]};
+assign n120 = {n73[15],
+  n73[14],
+  n73[13],
+  n73[12],
+  n73[11],
+  n73[10],
+  n73[9],
+  n73[8],
+  n73[7],
+  n73[6],
+  n73[5],
+  n73[4],
+  n73[3],
+  n73[2],
+  n73[1],
+  n73[0]};
+assign n121 = {n110[31],
+  n110[30],
+  n110[29],
+  n110[28],
+  n110[27],
+  n110[26],
+  n110[25],
+  n110[24],
+  n110[23],
+  n110[22],
+  n110[21],
+  n110[20],
+  n110[19],
+  n110[18],
+  n110[17],
+  n110[16]};
+assign n122 = {n110[15],
+  n110[14],
+  n110[13],
+  n110[12],
+  n110[11],
+  n110[10],
+  n110[9],
+  n110[8],
+  n110[7],
+  n110[6],
+  n110[5],
+  n110[4],
+  n110[3],
+  n110[2],
+  n110[1],
+  n110[0]};
+assign n123 =
+  n114 == 1'b0 ? n119 :
+  n120;
+assign n124 =
+  n114 == 1'b0 ? n121 :
+  n122;
+assign n126 = n129 + n4;
+assign n130 = n129 == n12;
+assign n131 = {n51, n130};
+assign n133 = {n131, n138};
+assign n134 =
+  n133 == 3'b000 ? n8 :
+  n133 == 3'b010 ? n8 :
+  n133 == 3'b100 ? n15 :
+  n133 == 3'b110 ? n15 :
+  n133 == 3'b001 ? n15 :
+  n133 == 3'b011 ? n8 :
+  n133 == 3'b101 ? n15 :
+  n15;
+assign n135 =
+  n133 == 3'b000 ? n8 :
+  n133 == 3'b010 ? n8 :
+  n133 == 3'b100 ? n15 :
+  n133 == 3'b110 ? n15 :
+  n133 == 3'b001 ? n15 :
+  n133 == 3'b011 ? n8 :
+  n133 == 3'b101 ? n15 :
+  n15;
+assign n143 = n142 & n130;
+assign n149 = {n148[15],
+  n148[14],
+  n148[13],
+  n148[12],
+  n148[11],
+  n148[10],
+  n148[9],
+  n148[8]};
+assign n150 = {n148[7],
+  n148[6],
+  n148[5],
+  n148[4],
+  n148[3],
+  n148[2],
+  n148[1],
+  n148[0]};
+assign n155 = {n154[15],
+  n154[14],
+  n154[13],
+  n154[12],
+  n154[11],
+  n154[10],
+  n154[9],
+  n154[8]};
+assign n156 = {n154[7],
+  n154[6],
+  n154[5],
+  n154[4],
+  n154[3],
+  n154[2],
+  n154[1],
+  n154[0]};
+assign n177 = {n176[15],
+  n176[14],
+  n176[13],
+  n176[12],
+  n176[11],
+  n176[10],
+  n176[9],
+  n176[8]};
+assign n178 = {n176[7],
+  n176[6],
+  n176[5],
+  n176[4],
+  n176[3],
+  n176[2],
+  n176[1],
+  n176[0]};
+assign n179 = {n155} * {n177};
+assign n180 = {n179[14],
+  n179[13],
+  n179[12],
+  n179[11],
+  n179[10],
+  n179[9],
+  n179[8],
+  n179[7]};
+assign n185 = {n156} * {n178};
+assign n186 = {n185[14],
+  n185[13],
+  n185[12],
+  n185[11],
+  n185[10],
+  n185[9],
+  n185[8],
+  n185[7]};
+assign n191 = n184 - n190;
+assign n196 = {n155} * {n178};
+assign n197 = {n196[14],
+  n196[13],
+  n196[12],
+  n196[11],
+  n196[10],
+  n196[9],
+  n196[8],
+  n196[7]};
+assign n202 = {n156} * {n177};
+assign n203 = {n202[14],
+  n202[13],
+  n202[12],
+  n202[11],
+  n202[10],
+  n202[9],
+  n202[8],
+  n202[7]};
+assign n208 = n201 + n207;
+assign n213 = n165 + n195;
+assign n214 = n173 + n212;
+assign n215 = {n213, n214};
+assign n220 = n165 - n195;
+assign n221 = n173 - n212;
+assign n222 = {n220, n221};
+assign n227 = {n219, n226};
+assign n244 = {n129[6],
+  n129[5],
+  n129[4],
+  n129[3],
+  n129[2],
+  n129[1]};
+assign n261 = n129[0];
+assign n278 = ~n277;
+assign n280 = n283 + n33;
+assign n285 = {n243, n290};
+assign n286 =
+  n285 == 2'b00 ? n8 :
+  n285 == 2'b10 ? n8 :
+  n285 == 2'b01 ? n15 :
+  n15;
+assign n287 =
+  n285 == 2'b00 ? n8 :
+  n285 == 2'b10 ? n15 :
+  n285 == 2'b01 ? n15 :
+  n8;
+assign n291 = ~n286;
+assign n296 = n8;
+assign n297 = {n8, n296};
+assign n298 = {n8, n297};
+assign n299 = {n8, n298};
+assign n300 = {n8, n299};
+assign n301 = {n8, n300};
+assign n302 = n283 == n301;
+assign n303 = n278 & n291;
+assign n307 = n278 & n286;
+assign n315 =
+  n314 == 1'b0 ? n306 :
+  n310;
+assign n317 = n320 + n33;
+assign n322 = {n243, n327};
+assign n323 =
+  n322 == 2'b00 ? n8 :
+  n322 == 2'b10 ? n8 :
+  n322 == 2'b01 ? n15 :
+  n15;
+assign n324 =
+  n322 == 2'b00 ? n8 :
+  n322 == 2'b10 ? n15 :
+  n322 == 2'b01 ? n15 :
+  n8;
+assign n328 = ~n323;
+assign n340 = n277 & n328;
+assign n344 = n277 & n323;
+assign n352 =
+  n351 == 1'b0 ? n343 :
+  n347;
+assign n353 = {n302, n295};
+assign n355 = {n353, n360};
+assign n356 =
+  n355 == 3'b000 ? n8 :
+  n355 == 3'b010 ? n8 :
+  n355 == 3'b100 ? n8 :
+  n355 == 3'b110 ? n8 :
+  n355 == 3'b001 ? n15 :
+  n355 == 3'b011 ? n15 :
+  n355 == 3'b101 ? n15 :
+  n15;
+assign n357 =
+  n355 == 3'b000 ? n8 :
+  n355 == 3'b010 ? n8 :
+  n355 == 3'b100 ? n15 :
+  n355 == 3'b110 ? n8 :
+  n355 == 3'b001 ? n15 :
+  n355 == 3'b011 ? n8 :
+  n355 == 3'b101 ? n15 :
+  n8;
+assign n361 = {n315[31],
+  n315[30],
+  n315[29],
+  n315[28],
+  n315[27],
+  n315[26],
+  n315[25],
+  n315[24],
+  n315[23],
+  n315[22],
+  n315[21],
+  n315[20],
+  n315[19],
+  n315[18],
+  n315[17],
+  n315[16]};
+assign n362 = {n315[15],
+  n315[14],
+  n315[13],
+  n315[12],
+  n315[11],
+  n315[10],
+  n315[9],
+  n315[8],
+  n315[7],
+  n315[6],
+  n315[5],
+  n315[4],
+  n315[3],
+  n315[2],
+  n315[1],
+  n315[0]};
+assign n363 = {n352[31],
+  n352[30],
+  n352[29],
+  n352[28],
+  n352[27],
+  n352[26],
+  n352[25],
+  n352[24],
+  n352[23],
+  n352[22],
+  n352[21],
+  n352[20],
+  n352[19],
+  n352[18],
+  n352[17],
+  n352[16]};
+assign n364 = {n352[15],
+  n352[14],
+  n352[13],
+  n352[12],
+  n352[11],
+  n352[10],
+  n352[9],
+  n352[8],
+  n352[7],
+  n352[6],
+  n352[5],
+  n352[4],
+  n352[3],
+  n352[2],
+  n352[1],
+  n352[0]};
+assign n365 =
+  n356 == 1'b0 ? n361 :
+  n362;
+assign n366 =
+  n356 == 1'b0 ? n363 :
+  n364;
+assign n368 = n371 + n4;
+assign n372 = n371 == n12;
+assign n373 = {n295, n372};
+assign n375 = {n373, n380};
+assign n376 =
+  n375 == 3'b000 ? n8 :
+  n375 == 3'b010 ? n8 :
+  n375 == 3'b100 ? n15 :
+  n375 == 3'b110 ? n15 :
+  n375 == 3'b001 ? n15 :
+  n375 == 3'b011 ? n8 :
+  n375 == 3'b101 ? n15 :
+  n15;
+assign n377 =
+  n375 == 3'b000 ? n8 :
+  n375 == 3'b010 ? n8 :
+  n375 == 3'b100 ? n15 :
+  n375 == 3'b110 ? n15 :
+  n375 == 3'b001 ? n15 :
+  n375 == 3'b011 ? n8 :
+  n375 == 3'b101 ? n15 :
+  n15;
+assign n385 = n384 & n372;
+assign n386 = n371[6];
+assign n391 = {n390[15],
+  n390[14],
+  n390[13],
+  n390[12],
+  n390[11],
+  n390[10],
+  n390[9],
+  n390[8]};
+assign n392 = {n390[7],
+  n390[6],
+  n390[5],
+  n390[4],
+  n390[3],
+  n390[2],
+  n390[1],
+  n390[0]};
+assign n397 = {n396[15],
+  n396[14],
+  n396[13],
+  n396[12],
+  n396[11],
+  n396[10],
+  n396[9],
+  n396[8]};
+assign n398 = {n396[7],
+  n396[6],
+  n396[5],
+  n396[4],
+  n396[3],
+  n396[2],
+  n396[1],
+  n396[0]};
+assign n418 = {n417[15],
+  n417[14],
+  n417[13],
+  n417[12],
+  n417[11],
+  n417[10],
+  n417[9],
+  n417[8]};
+assign n419 = {n417[7],
+  n417[6],
+  n417[5],
+  n417[4],
+  n417[3],
+  n417[2],
+  n417[1],
+  n417[0]};
+assign n420 = {n397} * {n418};
+assign n421 = {n420[14],
+  n420[13],
+  n420[12],
+  n420[11],
+  n420[10],
+  n420[9],
+  n420[8],
+  n420[7]};
+assign n426 = {n398} * {n419};
+assign n427 = {n426[14],
+  n426[13],
+  n426[12],
+  n426[11],
+  n426[10],
+  n426[9],
+  n426[8],
+  n426[7]};
+assign n432 = n425 - n431;
+assign n437 = {n397} * {n419};
+assign n438 = {n437[14],
+  n437[13],
+  n437[12],
+  n437[11],
+  n437[10],
+  n437[9],
+  n437[8],
+  n437[7]};
+assign n443 = {n398} * {n418};
+assign n444 = {n443[14],
+  n443[13],
+  n443[12],
+  n443[11],
+  n443[10],
+  n443[9],
+  n443[8],
+  n443[7]};
+assign n449 = n442 + n448;
+assign n454 = n406 + n436;
+assign n455 = n414 + n453;
+assign n456 = {n454, n455};
+assign n461 = n406 - n436;
+assign n462 = n414 - n453;
+assign n463 = {n461, n462};
+assign n468 = {n460, n467};
+assign n485 = {n371[6],
+  n371[5],
+  n371[4],
+  n371[3],
+  n371[2],
+  n371[1]};
+assign n502 = n371[0];
+assign n519 = ~n518;
+assign n521 = n524 + n33;
+assign n526 = {n484, n531};
+assign n527 =
+  n526 == 2'b00 ? n8 :
+  n526 == 2'b10 ? n8 :
+  n526 == 2'b01 ? n15 :
+  n15;
+assign n528 =
+  n526 == 2'b00 ? n8 :
+  n526 == 2'b10 ? n15 :
+  n526 == 2'b01 ? n15 :
+  n8;
+assign n532 = ~n527;
+assign n537 = n8;
+assign n538 = {n8, n537};
+assign n539 = {n8, n538};
+assign n540 = {n8, n539};
+assign n541 = {n8, n540};
+assign n542 = {n8, n541};
+assign n543 = n524 == n542;
+assign n544 = n519 & n532;
+assign n548 = n519 & n527;
+assign n556 =
+  n555 == 1'b0 ? n547 :
+  n551;
+assign n558 = n561 + n33;
+assign n563 = {n484, n568};
+assign n564 =
+  n563 == 2'b00 ? n8 :
+  n563 == 2'b10 ? n8 :
+  n563 == 2'b01 ? n15 :
+  n15;
+assign n565 =
+  n563 == 2'b00 ? n8 :
+  n563 == 2'b10 ? n15 :
+  n563 == 2'b01 ? n15 :
+  n8;
+assign n569 = ~n564;
+assign n581 = n518 & n569;
+assign n585 = n518 & n564;
+assign n593 =
+  n592 == 1'b0 ? n584 :
+  n588;
+assign n594 = {n543, n536};
+assign n596 = {n594, n601};
+assign n597 =
+  n596 == 3'b000 ? n8 :
+  n596 == 3'b010 ? n8 :
+  n596 == 3'b100 ? n8 :
+  n596 == 3'b110 ? n8 :
+  n596 == 3'b001 ? n15 :
+  n596 == 3'b011 ? n15 :
+  n596 == 3'b101 ? n15 :
+  n15;
+assign n598 =
+  n596 == 3'b000 ? n8 :
+  n596 == 3'b010 ? n8 :
+  n596 == 3'b100 ? n15 :
+  n596 == 3'b110 ? n8 :
+  n596 == 3'b001 ? n15 :
+  n596 == 3'b011 ? n8 :
+  n596 == 3'b101 ? n15 :
+  n8;
+assign n602 = {n556[31],
+  n556[30],
+  n556[29],
+  n556[28],
+  n556[27],
+  n556[26],
+  n556[25],
+  n556[24],
+  n556[23],
+  n556[22],
+  n556[21],
+  n556[20],
+  n556[19],
+  n556[18],
+  n556[17],
+  n556[16]};
+assign n603 = {n556[15],
+  n556[14],
+  n556[13],
+  n556[12],
+  n556[11],
+  n556[10],
+  n556[9],
+  n556[8],
+  n556[7],
+  n556[6],
+  n556[5],
+  n556[4],
+  n556[3],
+  n556[2],
+  n556[1],
+  n556[0]};
+assign n604 = {n593[31],
+  n593[30],
+  n593[29],
+  n593[28],
+  n593[27],
+  n593[26],
+  n593[25],
+  n593[24],
+  n593[23],
+  n593[22],
+  n593[21],
+  n593[20],
+  n593[19],
+  n593[18],
+  n593[17],
+  n593[16]};
+assign n605 = {n593[15],
+  n593[14],
+  n593[13],
+  n593[12],
+  n593[11],
+  n593[10],
+  n593[9],
+  n593[8],
+  n593[7],
+  n593[6],
+  n593[5],
+  n593[4],
+  n593[3],
+  n593[2],
+  n593[1],
+  n593[0]};
+assign n606 =
+  n597 == 1'b0 ? n602 :
+  n603;
+assign n607 =
+  n597 == 1'b0 ? n604 :
+  n605;
+assign n609 = n612 + n4;
+assign n613 = n612 == n12;
+assign n614 = {n536, n613};
+assign n616 = {n614, n621};
+assign n617 =
+  n616 == 3'b000 ? n8 :
+  n616 == 3'b010 ? n8 :
+  n616 == 3'b100 ? n15 :
+  n616 == 3'b110 ? n15 :
+  n616 == 3'b001 ? n15 :
+  n616 == 3'b011 ? n8 :
+  n616 == 3'b101 ? n15 :
+  n15;
+assign n618 =
+  n616 == 3'b000 ? n8 :
+  n616 == 3'b010 ? n8 :
+  n616 == 3'b100 ? n15 :
+  n616 == 3'b110 ? n15 :
+  n616 == 3'b001 ? n15 :
+  n616 == 3'b011 ? n8 :
+  n616 == 3'b101 ? n15 :
+  n15;
+assign n626 = n625 & n613;
+assign n627 = {n612[6],
+  n612[5]};
+assign n632 = {n631[15],
+  n631[14],
+  n631[13],
+  n631[12],
+  n631[11],
+  n631[10],
+  n631[9],
+  n631[8]};
+assign n633 = {n631[7],
+  n631[6],
+  n631[5],
+  n631[4],
+  n631[3],
+  n631[2],
+  n631[1],
+  n631[0]};
+assign n638 = {n637[15],
+  n637[14],
+  n637[13],
+  n637[12],
+  n637[11],
+  n637[10],
+  n637[9],
+  n637[8]};
+assign n639 = {n637[7],
+  n637[6],
+  n637[5],
+  n637[4],
+  n637[3],
+  n637[2],
+  n637[1],
+  n637[0]};
+assign n659 = {n658[15],
+  n658[14],
+  n658[13],
+  n658[12],
+  n658[11],
+  n658[10],
+  n658[9],
+  n658[8]};
+assign n660 = {n658[7],
+  n658[6],
+  n658[5],
+  n658[4],
+  n658[3],
+  n658[2],
+  n658[1],
+  n658[0]};
+assign n661 = {n638} * {n659};
+assign n662 = {n661[14],
+  n661[13],
+  n661[12],
+  n661[11],
+  n661[10],
+  n661[9],
+  n661[8],
+  n661[7]};
+assign n667 = {n639} * {n660};
+assign n668 = {n667[14],
+  n667[13],
+  n667[12],
+  n667[11],
+  n667[10],
+  n667[9],
+  n667[8],
+  n667[7]};
+assign n673 = n666 - n672;
+assign n678 = {n638} * {n660};
+assign n679 = {n678[14],
+  n678[13],
+  n678[12],
+  n678[11],
+  n678[10],
+  n678[9],
+  n678[8],
+  n678[7]};
+assign n684 = {n639} * {n659};
+assign n685 = {n684[14],
+  n684[13],
+  n684[12],
+  n684[11],
+  n684[10],
+  n684[9],
+  n684[8],
+  n684[7]};
+assign n690 = n683 + n689;
+assign n695 = n647 + n677;
+assign n696 = n655 + n694;
+assign n697 = {n695, n696};
+assign n702 = n647 - n677;
+assign n703 = n655 - n694;
+assign n704 = {n702, n703};
+assign n709 = {n701, n708};
+assign n726 = {n612[6],
+  n612[5],
+  n612[4],
+  n612[3],
+  n612[2],
+  n612[1]};
+assign n743 = n612[0];
+assign n760 = ~n759;
+assign n762 = n765 + n33;
+assign n767 = {n725, n772};
+assign n768 =
+  n767 == 2'b00 ? n8 :
+  n767 == 2'b10 ? n8 :
+  n767 == 2'b01 ? n15 :
+  n15;
+assign n769 =
+  n767 == 2'b00 ? n8 :
+  n767 == 2'b10 ? n15 :
+  n767 == 2'b01 ? n15 :
+  n8;
+assign n773 = ~n768;
+assign n778 = n8;
+assign n779 = {n8, n778};
+assign n780 = {n8, n779};
+assign n781 = {n8, n780};
+assign n782 = {n8, n781};
+assign n783 = {n8, n782};
+assign n784 = n765 == n783;
+assign n785 = n760 & n773;
+assign n789 = n760 & n768;
+assign n797 =
+  n796 == 1'b0 ? n788 :
+  n792;
+assign n799 = n802 + n33;
+assign n804 = {n725, n809};
+assign n805 =
+  n804 == 2'b00 ? n8 :
+  n804 == 2'b10 ? n8 :
+  n804 == 2'b01 ? n15 :
+  n15;
+assign n806 =
+  n804 == 2'b00 ? n8 :
+  n804 == 2'b10 ? n15 :
+  n804 == 2'b01 ? n15 :
+  n8;
+assign n810 = ~n805;
+assign n822 = n759 & n810;
+assign n826 = n759 & n805;
+assign n834 =
+  n833 == 1'b0 ? n825 :
+  n829;
+assign n835 = {n784, n777};
+assign n837 = {n835, n842};
+assign n838 =
+  n837 == 3'b000 ? n8 :
+  n837 == 3'b010 ? n8 :
+  n837 == 3'b100 ? n8 :
+  n837 == 3'b110 ? n8 :
+  n837 == 3'b001 ? n15 :
+  n837 == 3'b011 ? n15 :
+  n837 == 3'b101 ? n15 :
+  n15;
+assign n839 =
+  n837 == 3'b000 ? n8 :
+  n837 == 3'b010 ? n8 :
+  n837 == 3'b100 ? n15 :
+  n837 == 3'b110 ? n8 :
+  n837 == 3'b001 ? n15 :
+  n837 == 3'b011 ? n8 :
+  n837 == 3'b101 ? n15 :
+  n8;
+assign n843 = {n797[31],
+  n797[30],
+  n797[29],
+  n797[28],
+  n797[27],
+  n797[26],
+  n797[25],
+  n797[24],
+  n797[23],
+  n797[22],
+  n797[21],
+  n797[20],
+  n797[19],
+  n797[18],
+  n797[17],
+  n797[16]};
+assign n844 = {n797[15],
+  n797[14],
+  n797[13],
+  n797[12],
+  n797[11],
+  n797[10],
+  n797[9],
+  n797[8],
+  n797[7],
+  n797[6],
+  n797[5],
+  n797[4],
+  n797[3],
+  n797[2],
+  n797[1],
+  n797[0]};
+assign n845 = {n834[31],
+  n834[30],
+  n834[29],
+  n834[28],
+  n834[27],
+  n834[26],
+  n834[25],
+  n834[24],
+  n834[23],
+  n834[22],
+  n834[21],
+  n834[20],
+  n834[19],
+  n834[18],
+  n834[17],
+  n834[16]};
+assign n846 = {n834[15],
+  n834[14],
+  n834[13],
+  n834[12],
+  n834[11],
+  n834[10],
+  n834[9],
+  n834[8],
+  n834[7],
+  n834[6],
+  n834[5],
+  n834[4],
+  n834[3],
+  n834[2],
+  n834[1],
+  n834[0]};
+assign n847 =
+  n838 == 1'b0 ? n843 :
+  n844;
+assign n848 =
+  n838 == 1'b0 ? n845 :
+  n846;
+assign n850 = n853 + n4;
+assign n854 = n853 == n12;
+assign n855 = {n777, n854};
+assign n857 = {n855, n862};
+assign n858 =
+  n857 == 3'b000 ? n8 :
+  n857 == 3'b010 ? n8 :
+  n857 == 3'b100 ? n15 :
+  n857 == 3'b110 ? n15 :
+  n857 == 3'b001 ? n15 :
+  n857 == 3'b011 ? n8 :
+  n857 == 3'b101 ? n15 :
+  n15;
+assign n859 =
+  n857 == 3'b000 ? n8 :
+  n857 == 3'b010 ? n8 :
+  n857 == 3'b100 ? n15 :
+  n857 == 3'b110 ? n15 :
+  n857 == 3'b001 ? n15 :
+  n857 == 3'b011 ? n8 :
+  n857 == 3'b101 ? n15 :
+  n15;
+assign n867 = n866 & n854;
+assign n868 = {n853[6],
+  n853[5],
+  n853[4]};
+assign n873 = {n872[15],
+  n872[14],
+  n872[13],
+  n872[12],
+  n872[11],
+  n872[10],
+  n872[9],
+  n872[8]};
+assign n874 = {n872[7],
+  n872[6],
+  n872[5],
+  n872[4],
+  n872[3],
+  n872[2],
+  n872[1],
+  n872[0]};
+assign n879 = {n878[15],
+  n878[14],
+  n878[13],
+  n878[12],
+  n878[11],
+  n878[10],
+  n878[9],
+  n878[8]};
+assign n880 = {n878[7],
+  n878[6],
+  n878[5],
+  n878[4],
+  n878[3],
+  n878[2],
+  n878[1],
+  n878[0]};
+assign n900 = {n899[15],
+  n899[14],
+  n899[13],
+  n899[12],
+  n899[11],
+  n899[10],
+  n899[9],
+  n899[8]};
+assign n901 = {n899[7],
+  n899[6],
+  n899[5],
+  n899[4],
+  n899[3],
+  n899[2],
+  n899[1],
+  n899[0]};
+assign n902 = {n879} * {n900};
+assign n903 = {n902[14],
+  n902[13],
+  n902[12],
+  n902[11],
+  n902[10],
+  n902[9],
+  n902[8],
+  n902[7]};
+assign n908 = {n880} * {n901};
+assign n909 = {n908[14],
+  n908[13],
+  n908[12],
+  n908[11],
+  n908[10],
+  n908[9],
+  n908[8],
+  n908[7]};
+assign n914 = n907 - n913;
+assign n919 = {n879} * {n901};
+assign n920 = {n919[14],
+  n919[13],
+  n919[12],
+  n919[11],
+  n919[10],
+  n919[9],
+  n919[8],
+  n919[7]};
+assign n925 = {n880} * {n900};
+assign n926 = {n925[14],
+  n925[13],
+  n925[12],
+  n925[11],
+  n925[10],
+  n925[9],
+  n925[8],
+  n925[7]};
+assign n931 = n924 + n930;
+assign n936 = n888 + n918;
+assign n937 = n896 + n935;
+assign n938 = {n936, n937};
+assign n943 = n888 - n918;
+assign n944 = n896 - n935;
+assign n945 = {n943, n944};
+assign n950 = {n942, n949};
+assign n967 = {n853[6],
+  n853[5],
+  n853[4],
+  n853[3],
+  n853[2],
+  n853[1]};
+assign n984 = n853[0];
+assign n1001 = ~n1000;
+assign n1003 = n1006 + n33;
+assign n1008 = {n966, n1013};
+assign n1009 =
+  n1008 == 2'b00 ? n8 :
+  n1008 == 2'b10 ? n8 :
+  n1008 == 2'b01 ? n15 :
+  n15;
+assign n1010 =
+  n1008 == 2'b00 ? n8 :
+  n1008 == 2'b10 ? n15 :
+  n1008 == 2'b01 ? n15 :
+  n8;
+assign n1014 = ~n1009;
+assign n1019 = n8;
+assign n1020 = {n8, n1019};
+assign n1021 = {n8, n1020};
+assign n1022 = {n8, n1021};
+assign n1023 = {n8, n1022};
+assign n1024 = {n8, n1023};
+assign n1025 = n1006 == n1024;
+assign n1026 = n1001 & n1014;
+assign n1030 = n1001 & n1009;
+assign n1038 =
+  n1037 == 1'b0 ? n1029 :
+  n1033;
+assign n1040 = n1043 + n33;
+assign n1045 = {n966, n1050};
+assign n1046 =
+  n1045 == 2'b00 ? n8 :
+  n1045 == 2'b10 ? n8 :
+  n1045 == 2'b01 ? n15 :
+  n15;
+assign n1047 =
+  n1045 == 2'b00 ? n8 :
+  n1045 == 2'b10 ? n15 :
+  n1045 == 2'b01 ? n15 :
+  n8;
+assign n1051 = ~n1046;
+assign n1063 = n1000 & n1051;
+assign n1067 = n1000 & n1046;
+assign n1075 =
+  n1074 == 1'b0 ? n1066 :
+  n1070;
+assign n1076 = {n1025, n1018};
+assign n1078 = {n1076, n1083};
+assign n1079 =
+  n1078 == 3'b000 ? n8 :
+  n1078 == 3'b010 ? n8 :
+  n1078 == 3'b100 ? n8 :
+  n1078 == 3'b110 ? n8 :
+  n1078 == 3'b001 ? n15 :
+  n1078 == 3'b011 ? n15 :
+  n1078 == 3'b101 ? n15 :
+  n15;
+assign n1080 =
+  n1078 == 3'b000 ? n8 :
+  n1078 == 3'b010 ? n8 :
+  n1078 == 3'b100 ? n15 :
+  n1078 == 3'b110 ? n8 :
+  n1078 == 3'b001 ? n15 :
+  n1078 == 3'b011 ? n8 :
+  n1078 == 3'b101 ? n15 :
+  n8;
+assign n1084 = {n1038[31],
+  n1038[30],
+  n1038[29],
+  n1038[28],
+  n1038[27],
+  n1038[26],
+  n1038[25],
+  n1038[24],
+  n1038[23],
+  n1038[22],
+  n1038[21],
+  n1038[20],
+  n1038[19],
+  n1038[18],
+  n1038[17],
+  n1038[16]};
+assign n1085 = {n1038[15],
+  n1038[14],
+  n1038[13],
+  n1038[12],
+  n1038[11],
+  n1038[10],
+  n1038[9],
+  n1038[8],
+  n1038[7],
+  n1038[6],
+  n1038[5],
+  n1038[4],
+  n1038[3],
+  n1038[2],
+  n1038[1],
+  n1038[0]};
+assign n1086 = {n1075[31],
+  n1075[30],
+  n1075[29],
+  n1075[28],
+  n1075[27],
+  n1075[26],
+  n1075[25],
+  n1075[24],
+  n1075[23],
+  n1075[22],
+  n1075[21],
+  n1075[20],
+  n1075[19],
+  n1075[18],
+  n1075[17],
+  n1075[16]};
+assign n1087 = {n1075[15],
+  n1075[14],
+  n1075[13],
+  n1075[12],
+  n1075[11],
+  n1075[10],
+  n1075[9],
+  n1075[8],
+  n1075[7],
+  n1075[6],
+  n1075[5],
+  n1075[4],
+  n1075[3],
+  n1075[2],
+  n1075[1],
+  n1075[0]};
+assign n1088 =
+  n1079 == 1'b0 ? n1084 :
+  n1085;
+assign n1089 =
+  n1079 == 1'b0 ? n1086 :
+  n1087;
+assign n1091 = n1094 + n4;
+assign n1095 = n1094 == n12;
+assign n1096 = {n1018, n1095};
+assign n1098 = {n1096, n1103};
+assign n1099 =
+  n1098 == 3'b000 ? n8 :
+  n1098 == 3'b010 ? n8 :
+  n1098 == 3'b100 ? n15 :
+  n1098 == 3'b110 ? n15 :
+  n1098 == 3'b001 ? n15 :
+  n1098 == 3'b011 ? n8 :
+  n1098 == 3'b101 ? n15 :
+  n15;
+assign n1100 =
+  n1098 == 3'b000 ? n8 :
+  n1098 == 3'b010 ? n8 :
+  n1098 == 3'b100 ? n15 :
+  n1098 == 3'b110 ? n15 :
+  n1098 == 3'b001 ? n15 :
+  n1098 == 3'b011 ? n8 :
+  n1098 == 3'b101 ? n15 :
+  n15;
+assign n1108 = n1107 & n1095;
+assign n1109 = {n1094[6],
+  n1094[5],
+  n1094[4],
+  n1094[3]};
+assign n1114 = {n1113[15],
+  n1113[14],
+  n1113[13],
+  n1113[12],
+  n1113[11],
+  n1113[10],
+  n1113[9],
+  n1113[8]};
+assign n1115 = {n1113[7],
+  n1113[6],
+  n1113[5],
+  n1113[4],
+  n1113[3],
+  n1113[2],
+  n1113[1],
+  n1113[0]};
+assign n1120 = {n1119[15],
+  n1119[14],
+  n1119[13],
+  n1119[12],
+  n1119[11],
+  n1119[10],
+  n1119[9],
+  n1119[8]};
+assign n1121 = {n1119[7],
+  n1119[6],
+  n1119[5],
+  n1119[4],
+  n1119[3],
+  n1119[2],
+  n1119[1],
+  n1119[0]};
+assign n1141 = {n1140[15],
+  n1140[14],
+  n1140[13],
+  n1140[12],
+  n1140[11],
+  n1140[10],
+  n1140[9],
+  n1140[8]};
+assign n1142 = {n1140[7],
+  n1140[6],
+  n1140[5],
+  n1140[4],
+  n1140[3],
+  n1140[2],
+  n1140[1],
+  n1140[0]};
+assign n1143 = {n1120} * {n1141};
+assign n1144 = {n1143[14],
+  n1143[13],
+  n1143[12],
+  n1143[11],
+  n1143[10],
+  n1143[9],
+  n1143[8],
+  n1143[7]};
+assign n1149 = {n1121} * {n1142};
+assign n1150 = {n1149[14],
+  n1149[13],
+  n1149[12],
+  n1149[11],
+  n1149[10],
+  n1149[9],
+  n1149[8],
+  n1149[7]};
+assign n1155 = n1148 - n1154;
+assign n1160 = {n1120} * {n1142};
+assign n1161 = {n1160[14],
+  n1160[13],
+  n1160[12],
+  n1160[11],
+  n1160[10],
+  n1160[9],
+  n1160[8],
+  n1160[7]};
+assign n1166 = {n1121} * {n1141};
+assign n1167 = {n1166[14],
+  n1166[13],
+  n1166[12],
+  n1166[11],
+  n1166[10],
+  n1166[9],
+  n1166[8],
+  n1166[7]};
+assign n1172 = n1165 + n1171;
+assign n1177 = n1129 + n1159;
+assign n1178 = n1137 + n1176;
+assign n1179 = {n1177, n1178};
+assign n1184 = n1129 - n1159;
+assign n1185 = n1137 - n1176;
+assign n1186 = {n1184, n1185};
+assign n1191 = {n1183, n1190};
+assign n1208 = {n1094[6],
+  n1094[5],
+  n1094[4],
+  n1094[3],
+  n1094[2],
+  n1094[1]};
+assign n1225 = n1094[0];
+assign n1242 = ~n1241;
+assign n1244 = n1247 + n33;
+assign n1249 = {n1207, n1254};
+assign n1250 =
+  n1249 == 2'b00 ? n8 :
+  n1249 == 2'b10 ? n8 :
+  n1249 == 2'b01 ? n15 :
+  n15;
+assign n1251 =
+  n1249 == 2'b00 ? n8 :
+  n1249 == 2'b10 ? n15 :
+  n1249 == 2'b01 ? n15 :
+  n8;
+assign n1255 = ~n1250;
+assign n1260 = n8;
+assign n1261 = {n8, n1260};
+assign n1262 = {n8, n1261};
+assign n1263 = {n8, n1262};
+assign n1264 = {n8, n1263};
+assign n1265 = {n8, n1264};
+assign n1266 = n1247 == n1265;
+assign n1267 = n1242 & n1255;
+assign n1271 = n1242 & n1250;
+assign n1279 =
+  n1278 == 1'b0 ? n1270 :
+  n1274;
+assign n1281 = n1284 + n33;
+assign n1286 = {n1207, n1291};
+assign n1287 =
+  n1286 == 2'b00 ? n8 :
+  n1286 == 2'b10 ? n8 :
+  n1286 == 2'b01 ? n15 :
+  n15;
+assign n1288 =
+  n1286 == 2'b00 ? n8 :
+  n1286 == 2'b10 ? n15 :
+  n1286 == 2'b01 ? n15 :
+  n8;
+assign n1292 = ~n1287;
+assign n1304 = n1241 & n1292;
+assign n1308 = n1241 & n1287;
+assign n1316 =
+  n1315 == 1'b0 ? n1307 :
+  n1311;
+assign n1317 = {n1266, n1259};
+assign n1319 = {n1317, n1324};
+assign n1320 =
+  n1319 == 3'b000 ? n8 :
+  n1319 == 3'b010 ? n8 :
+  n1319 == 3'b100 ? n8 :
+  n1319 == 3'b110 ? n8 :
+  n1319 == 3'b001 ? n15 :
+  n1319 == 3'b011 ? n15 :
+  n1319 == 3'b101 ? n15 :
+  n15;
+assign n1321 =
+  n1319 == 3'b000 ? n8 :
+  n1319 == 3'b010 ? n8 :
+  n1319 == 3'b100 ? n15 :
+  n1319 == 3'b110 ? n8 :
+  n1319 == 3'b001 ? n15 :
+  n1319 == 3'b011 ? n8 :
+  n1319 == 3'b101 ? n15 :
+  n8;
+assign n1325 = {n1279[31],
+  n1279[30],
+  n1279[29],
+  n1279[28],
+  n1279[27],
+  n1279[26],
+  n1279[25],
+  n1279[24],
+  n1279[23],
+  n1279[22],
+  n1279[21],
+  n1279[20],
+  n1279[19],
+  n1279[18],
+  n1279[17],
+  n1279[16]};
+assign n1326 = {n1279[15],
+  n1279[14],
+  n1279[13],
+  n1279[12],
+  n1279[11],
+  n1279[10],
+  n1279[9],
+  n1279[8],
+  n1279[7],
+  n1279[6],
+  n1279[5],
+  n1279[4],
+  n1279[3],
+  n1279[2],
+  n1279[1],
+  n1279[0]};
+assign n1327 = {n1316[31],
+  n1316[30],
+  n1316[29],
+  n1316[28],
+  n1316[27],
+  n1316[26],
+  n1316[25],
+  n1316[24],
+  n1316[23],
+  n1316[22],
+  n1316[21],
+  n1316[20],
+  n1316[19],
+  n1316[18],
+  n1316[17],
+  n1316[16]};
+assign n1328 = {n1316[15],
+  n1316[14],
+  n1316[13],
+  n1316[12],
+  n1316[11],
+  n1316[10],
+  n1316[9],
+  n1316[8],
+  n1316[7],
+  n1316[6],
+  n1316[5],
+  n1316[4],
+  n1316[3],
+  n1316[2],
+  n1316[1],
+  n1316[0]};
+assign n1329 =
+  n1320 == 1'b0 ? n1325 :
+  n1326;
+assign n1330 =
+  n1320 == 1'b0 ? n1327 :
+  n1328;
+assign n1332 = n1335 + n4;
+assign n1336 = n1335 == n12;
+assign n1337 = {n1259, n1336};
+assign n1339 = {n1337, n1344};
+assign n1340 =
+  n1339 == 3'b000 ? n8 :
+  n1339 == 3'b010 ? n8 :
+  n1339 == 3'b100 ? n15 :
+  n1339 == 3'b110 ? n15 :
+  n1339 == 3'b001 ? n15 :
+  n1339 == 3'b011 ? n8 :
+  n1339 == 3'b101 ? n15 :
+  n15;
+assign n1341 =
+  n1339 == 3'b000 ? n8 :
+  n1339 == 3'b010 ? n8 :
+  n1339 == 3'b100 ? n15 :
+  n1339 == 3'b110 ? n15 :
+  n1339 == 3'b001 ? n15 :
+  n1339 == 3'b011 ? n8 :
+  n1339 == 3'b101 ? n15 :
+  n15;
+assign n1349 = n1348 & n1336;
+assign n1350 = {n1335[6],
+  n1335[5],
+  n1335[4],
+  n1335[3],
+  n1335[2]};
+assign n1355 = {n1354[15],
+  n1354[14],
+  n1354[13],
+  n1354[12],
+  n1354[11],
+  n1354[10],
+  n1354[9],
+  n1354[8]};
+assign n1356 = {n1354[7],
+  n1354[6],
+  n1354[5],
+  n1354[4],
+  n1354[3],
+  n1354[2],
+  n1354[1],
+  n1354[0]};
+assign n1361 = {n1360[15],
+  n1360[14],
+  n1360[13],
+  n1360[12],
+  n1360[11],
+  n1360[10],
+  n1360[9],
+  n1360[8]};
+assign n1362 = {n1360[7],
+  n1360[6],
+  n1360[5],
+  n1360[4],
+  n1360[3],
+  n1360[2],
+  n1360[1],
+  n1360[0]};
+assign n1382 = {n1381[15],
+  n1381[14],
+  n1381[13],
+  n1381[12],
+  n1381[11],
+  n1381[10],
+  n1381[9],
+  n1381[8]};
+assign n1383 = {n1381[7],
+  n1381[6],
+  n1381[5],
+  n1381[4],
+  n1381[3],
+  n1381[2],
+  n1381[1],
+  n1381[0]};
+assign n1384 = {n1361} * {n1382};
+assign n1385 = {n1384[14],
+  n1384[13],
+  n1384[12],
+  n1384[11],
+  n1384[10],
+  n1384[9],
+  n1384[8],
+  n1384[7]};
+assign n1390 = {n1362} * {n1383};
+assign n1391 = {n1390[14],
+  n1390[13],
+  n1390[12],
+  n1390[11],
+  n1390[10],
+  n1390[9],
+  n1390[8],
+  n1390[7]};
+assign n1396 = n1389 - n1395;
+assign n1401 = {n1361} * {n1383};
+assign n1402 = {n1401[14],
+  n1401[13],
+  n1401[12],
+  n1401[11],
+  n1401[10],
+  n1401[9],
+  n1401[8],
+  n1401[7]};
+assign n1407 = {n1362} * {n1382};
+assign n1408 = {n1407[14],
+  n1407[13],
+  n1407[12],
+  n1407[11],
+  n1407[10],
+  n1407[9],
+  n1407[8],
+  n1407[7]};
+assign n1413 = n1406 + n1412;
+assign n1418 = n1370 + n1400;
+assign n1419 = n1378 + n1417;
+assign n1420 = {n1418, n1419};
+assign n1425 = n1370 - n1400;
+assign n1426 = n1378 - n1417;
+assign n1427 = {n1425, n1426};
+assign n1432 = {n1424, n1431};
+assign n1449 = {n1335[6],
+  n1335[5],
+  n1335[4],
+  n1335[3],
+  n1335[2],
+  n1335[1]};
+assign n1466 = n1335[0];
+assign n1483 = ~n1482;
+assign n1485 = n1488 + n33;
+assign n1490 = {n1448, n1495};
+assign n1491 =
+  n1490 == 2'b00 ? n8 :
+  n1490 == 2'b10 ? n8 :
+  n1490 == 2'b01 ? n15 :
+  n15;
+assign n1492 =
+  n1490 == 2'b00 ? n8 :
+  n1490 == 2'b10 ? n15 :
+  n1490 == 2'b01 ? n15 :
+  n8;
+assign n1496 = ~n1491;
+assign n1501 = n8;
+assign n1502 = {n8, n1501};
+assign n1503 = {n8, n1502};
+assign n1504 = {n8, n1503};
+assign n1505 = {n8, n1504};
+assign n1506 = {n8, n1505};
+assign n1507 = n1488 == n1506;
+assign n1508 = n1483 & n1496;
+assign n1512 = n1483 & n1491;
+assign n1520 =
+  n1519 == 1'b0 ? n1511 :
+  n1515;
+assign n1522 = n1525 + n33;
+assign n1527 = {n1448, n1532};
+assign n1528 =
+  n1527 == 2'b00 ? n8 :
+  n1527 == 2'b10 ? n8 :
+  n1527 == 2'b01 ? n15 :
+  n15;
+assign n1529 =
+  n1527 == 2'b00 ? n8 :
+  n1527 == 2'b10 ? n15 :
+  n1527 == 2'b01 ? n15 :
+  n8;
+assign n1533 = ~n1528;
+assign n1545 = n1482 & n1533;
+assign n1549 = n1482 & n1528;
+assign n1557 =
+  n1556 == 1'b0 ? n1548 :
+  n1552;
+assign n1558 = {n1507, n1500};
+assign n1560 = {n1558, n1565};
+assign n1561 =
+  n1560 == 3'b000 ? n8 :
+  n1560 == 3'b010 ? n8 :
+  n1560 == 3'b100 ? n8 :
+  n1560 == 3'b110 ? n8 :
+  n1560 == 3'b001 ? n15 :
+  n1560 == 3'b011 ? n15 :
+  n1560 == 3'b101 ? n15 :
+  n15;
+assign n1562 =
+  n1560 == 3'b000 ? n8 :
+  n1560 == 3'b010 ? n8 :
+  n1560 == 3'b100 ? n15 :
+  n1560 == 3'b110 ? n8 :
+  n1560 == 3'b001 ? n15 :
+  n1560 == 3'b011 ? n8 :
+  n1560 == 3'b101 ? n15 :
+  n8;
+assign n1566 = {n1520[31],
+  n1520[30],
+  n1520[29],
+  n1520[28],
+  n1520[27],
+  n1520[26],
+  n1520[25],
+  n1520[24],
+  n1520[23],
+  n1520[22],
+  n1520[21],
+  n1520[20],
+  n1520[19],
+  n1520[18],
+  n1520[17],
+  n1520[16]};
+assign n1567 = {n1520[15],
+  n1520[14],
+  n1520[13],
+  n1520[12],
+  n1520[11],
+  n1520[10],
+  n1520[9],
+  n1520[8],
+  n1520[7],
+  n1520[6],
+  n1520[5],
+  n1520[4],
+  n1520[3],
+  n1520[2],
+  n1520[1],
+  n1520[0]};
+assign n1568 = {n1557[31],
+  n1557[30],
+  n1557[29],
+  n1557[28],
+  n1557[27],
+  n1557[26],
+  n1557[25],
+  n1557[24],
+  n1557[23],
+  n1557[22],
+  n1557[21],
+  n1557[20],
+  n1557[19],
+  n1557[18],
+  n1557[17],
+  n1557[16]};
+assign n1569 = {n1557[15],
+  n1557[14],
+  n1557[13],
+  n1557[12],
+  n1557[11],
+  n1557[10],
+  n1557[9],
+  n1557[8],
+  n1557[7],
+  n1557[6],
+  n1557[5],
+  n1557[4],
+  n1557[3],
+  n1557[2],
+  n1557[1],
+  n1557[0]};
+assign n1570 =
+  n1561 == 1'b0 ? n1566 :
+  n1567;
+assign n1571 =
+  n1561 == 1'b0 ? n1568 :
+  n1569;
+assign n1573 = n1576 + n4;
+assign n1577 = n1576 == n12;
+assign n1578 = {n1500, n1577};
+assign n1580 = {n1578, n1585};
+assign n1581 =
+  n1580 == 3'b000 ? n8 :
+  n1580 == 3'b010 ? n8 :
+  n1580 == 3'b100 ? n15 :
+  n1580 == 3'b110 ? n15 :
+  n1580 == 3'b001 ? n15 :
+  n1580 == 3'b011 ? n8 :
+  n1580 == 3'b101 ? n15 :
+  n15;
+assign n1582 =
+  n1580 == 3'b000 ? n8 :
+  n1580 == 3'b010 ? n8 :
+  n1580 == 3'b100 ? n15 :
+  n1580 == 3'b110 ? n15 :
+  n1580 == 3'b001 ? n15 :
+  n1580 == 3'b011 ? n8 :
+  n1580 == 3'b101 ? n15 :
+  n15;
+assign n1590 = n1589 & n1577;
+assign n1591 = {n1576[6],
+  n1576[5],
+  n1576[4],
+  n1576[3],
+  n1576[2],
+  n1576[1]};
+assign n1596 = {n1595[15],
+  n1595[14],
+  n1595[13],
+  n1595[12],
+  n1595[11],
+  n1595[10],
+  n1595[9],
+  n1595[8]};
+assign n1597 = {n1595[7],
+  n1595[6],
+  n1595[5],
+  n1595[4],
+  n1595[3],
+  n1595[2],
+  n1595[1],
+  n1595[0]};
+assign n1602 = {n1601[15],
+  n1601[14],
+  n1601[13],
+  n1601[12],
+  n1601[11],
+  n1601[10],
+  n1601[9],
+  n1601[8]};
+assign n1603 = {n1601[7],
+  n1601[6],
+  n1601[5],
+  n1601[4],
+  n1601[3],
+  n1601[2],
+  n1601[1],
+  n1601[0]};
+assign n1623 = {n1622[15],
+  n1622[14],
+  n1622[13],
+  n1622[12],
+  n1622[11],
+  n1622[10],
+  n1622[9],
+  n1622[8]};
+assign n1624 = {n1622[7],
+  n1622[6],
+  n1622[5],
+  n1622[4],
+  n1622[3],
+  n1622[2],
+  n1622[1],
+  n1622[0]};
+assign n1625 = {n1602} * {n1623};
+assign n1626 = {n1625[14],
+  n1625[13],
+  n1625[12],
+  n1625[11],
+  n1625[10],
+  n1625[9],
+  n1625[8],
+  n1625[7]};
+assign n1631 = {n1603} * {n1624};
+assign n1632 = {n1631[14],
+  n1631[13],
+  n1631[12],
+  n1631[11],
+  n1631[10],
+  n1631[9],
+  n1631[8],
+  n1631[7]};
+assign n1637 = n1630 - n1636;
+assign n1642 = {n1602} * {n1624};
+assign n1643 = {n1642[14],
+  n1642[13],
+  n1642[12],
+  n1642[11],
+  n1642[10],
+  n1642[9],
+  n1642[8],
+  n1642[7]};
+assign n1648 = {n1603} * {n1623};
+assign n1649 = {n1648[14],
+  n1648[13],
+  n1648[12],
+  n1648[11],
+  n1648[10],
+  n1648[9],
+  n1648[8],
+  n1648[7]};
+assign n1654 = n1647 + n1653;
+assign n1659 = n1611 + n1641;
+assign n1660 = n1619 + n1658;
+assign n1661 = {n1659, n1660};
+assign n1666 = n1611 - n1641;
+assign n1667 = n1619 - n1658;
+assign n1668 = {n1666, n1667};
+assign n1673 = {n1665, n1672};
+assign n1690 = {n1576[6],
+  n1576[5],
+  n1576[4],
+  n1576[3],
+  n1576[2],
+  n1576[1]};
+assign n1707 = n1576[0];
+assign n1724 = ~n1723;
+assign n1726 = n1729 + n33;
+assign n1731 = {n1689, n1736};
+assign n1732 =
+  n1731 == 2'b00 ? n8 :
+  n1731 == 2'b10 ? n8 :
+  n1731 == 2'b01 ? n15 :
+  n15;
+assign n1733 =
+  n1731 == 2'b00 ? n8 :
+  n1731 == 2'b10 ? n15 :
+  n1731 == 2'b01 ? n15 :
+  n8;
+assign n1737 = ~n1732;
+assign n1742 = n8;
+assign n1743 = {n8, n1742};
+assign n1744 = {n8, n1743};
+assign n1745 = {n8, n1744};
+assign n1746 = {n8, n1745};
+assign n1747 = {n8, n1746};
+assign n1748 = n1729 == n1747;
+assign n1749 = n1724 & n1737;
+assign n1753 = n1724 & n1732;
+assign n1761 =
+  n1760 == 1'b0 ? n1752 :
+  n1756;
+assign n1763 = n1766 + n33;
+assign n1768 = {n1689, n1773};
+assign n1769 =
+  n1768 == 2'b00 ? n8 :
+  n1768 == 2'b10 ? n8 :
+  n1768 == 2'b01 ? n15 :
+  n15;
+assign n1770 =
+  n1768 == 2'b00 ? n8 :
+  n1768 == 2'b10 ? n15 :
+  n1768 == 2'b01 ? n15 :
+  n8;
+assign n1774 = ~n1769;
+assign n1786 = n1723 & n1774;
+assign n1790 = n1723 & n1769;
+assign n1798 =
+  n1797 == 1'b0 ? n1789 :
+  n1793;
+assign n1799 = {n1748, n1741};
+assign n1801 = {n1799, n1806};
+assign n1802 =
+  n1801 == 3'b000 ? n8 :
+  n1801 == 3'b010 ? n8 :
+  n1801 == 3'b100 ? n8 :
+  n1801 == 3'b110 ? n8 :
+  n1801 == 3'b001 ? n15 :
+  n1801 == 3'b011 ? n15 :
+  n1801 == 3'b101 ? n15 :
+  n15;
+assign n1803 =
+  n1801 == 3'b000 ? n8 :
+  n1801 == 3'b010 ? n8 :
+  n1801 == 3'b100 ? n15 :
+  n1801 == 3'b110 ? n8 :
+  n1801 == 3'b001 ? n15 :
+  n1801 == 3'b011 ? n8 :
+  n1801 == 3'b101 ? n15 :
+  n8;
+assign n1807 = {n1761[31],
+  n1761[30],
+  n1761[29],
+  n1761[28],
+  n1761[27],
+  n1761[26],
+  n1761[25],
+  n1761[24],
+  n1761[23],
+  n1761[22],
+  n1761[21],
+  n1761[20],
+  n1761[19],
+  n1761[18],
+  n1761[17],
+  n1761[16]};
+assign n1808 = {n1761[15],
+  n1761[14],
+  n1761[13],
+  n1761[12],
+  n1761[11],
+  n1761[10],
+  n1761[9],
+  n1761[8],
+  n1761[7],
+  n1761[6],
+  n1761[5],
+  n1761[4],
+  n1761[3],
+  n1761[2],
+  n1761[1],
+  n1761[0]};
+assign n1809 = {n1798[31],
+  n1798[30],
+  n1798[29],
+  n1798[28],
+  n1798[27],
+  n1798[26],
+  n1798[25],
+  n1798[24],
+  n1798[23],
+  n1798[22],
+  n1798[21],
+  n1798[20],
+  n1798[19],
+  n1798[18],
+  n1798[17],
+  n1798[16]};
+assign n1810 = {n1798[15],
+  n1798[14],
+  n1798[13],
+  n1798[12],
+  n1798[11],
+  n1798[10],
+  n1798[9],
+  n1798[8],
+  n1798[7],
+  n1798[6],
+  n1798[5],
+  n1798[4],
+  n1798[3],
+  n1798[2],
+  n1798[1],
+  n1798[0]};
+assign n1811 =
+  n1802 == 1'b0 ? n1807 :
+  n1808;
+assign n1812 =
+  n1802 == 1'b0 ? n1809 :
+  n1810;
+assign n1814 = n1817 + n4;
+assign n1818 = n1817 == n12;
+assign n1819 = {n1741, n1818};
+assign n1821 = {n1819, n1826};
+assign n1822 =
+  n1821 == 3'b000 ? n8 :
+  n1821 == 3'b010 ? n8 :
+  n1821 == 3'b100 ? n15 :
+  n1821 == 3'b110 ? n15 :
+  n1821 == 3'b001 ? n15 :
+  n1821 == 3'b011 ? n8 :
+  n1821 == 3'b101 ? n15 :
+  n15;
+assign n1823 =
+  n1821 == 3'b000 ? n8 :
+  n1821 == 3'b010 ? n8 :
+  n1821 == 3'b100 ? n15 :
+  n1821 == 3'b110 ? n15 :
+  n1821 == 3'b001 ? n15 :
+  n1821 == 3'b011 ? n8 :
+  n1821 == 3'b101 ? n15 :
+  n15;
+assign n1831 = n1830 & n1818;
+assign n1832 = {n1817[6],
+  n1817[5],
+  n1817[4],
+  n1817[3],
+  n1817[2],
+  n1817[1],
+  n1817[0]};
+assign n1837 = {n1836[15],
+  n1836[14],
+  n1836[13],
+  n1836[12],
+  n1836[11],
+  n1836[10],
+  n1836[9],
+  n1836[8]};
+assign n1838 = {n1836[7],
+  n1836[6],
+  n1836[5],
+  n1836[4],
+  n1836[3],
+  n1836[2],
+  n1836[1],
+  n1836[0]};
+assign n1843 = {n1842[15],
+  n1842[14],
+  n1842[13],
+  n1842[12],
+  n1842[11],
+  n1842[10],
+  n1842[9],
+  n1842[8]};
+assign n1844 = {n1842[7],
+  n1842[6],
+  n1842[5],
+  n1842[4],
+  n1842[3],
+  n1842[2],
+  n1842[1],
+  n1842[0]};
+assign n1864 = {n1863[15],
+  n1863[14],
+  n1863[13],
+  n1863[12],
+  n1863[11],
+  n1863[10],
+  n1863[9],
+  n1863[8]};
+assign n1865 = {n1863[7],
+  n1863[6],
+  n1863[5],
+  n1863[4],
+  n1863[3],
+  n1863[2],
+  n1863[1],
+  n1863[0]};
+assign n1866 = {n1843} * {n1864};
+assign n1867 = {n1866[14],
+  n1866[13],
+  n1866[12],
+  n1866[11],
+  n1866[10],
+  n1866[9],
+  n1866[8],
+  n1866[7]};
+assign n1872 = {n1844} * {n1865};
+assign n1873 = {n1872[14],
+  n1872[13],
+  n1872[12],
+  n1872[11],
+  n1872[10],
+  n1872[9],
+  n1872[8],
+  n1872[7]};
+assign n1878 = n1871 - n1877;
+assign n1883 = {n1843} * {n1865};
+assign n1884 = {n1883[14],
+  n1883[13],
+  n1883[12],
+  n1883[11],
+  n1883[10],
+  n1883[9],
+  n1883[8],
+  n1883[7]};
+assign n1889 = {n1844} * {n1864};
+assign n1890 = {n1889[14],
+  n1889[13],
+  n1889[12],
+  n1889[11],
+  n1889[10],
+  n1889[9],
+  n1889[8],
+  n1889[7]};
+assign n1895 = n1888 + n1894;
+assign n1900 = n1852 + n1882;
+assign n1901 = n1860 + n1899;
+assign n1902 = {n1900, n1901};
+assign n1907 = n1852 - n1882;
+assign n1908 = n1860 - n1899;
+assign n1909 = {n1907, n1908};
+assign n1914 = {n1906, n1913};
+assign n1931 = {n1817[6],
+  n1817[5],
+  n1817[4],
+  n1817[3],
+  n1817[2],
+  n1817[1]};
+assign n1948 = n1817[0];
+assign n1965 = ~n1964;
+assign n1967 = n1970 + n33;
+assign n1972 = {n1930, n1977};
+assign n1973 =
+  n1972 == 2'b00 ? n8 :
+  n1972 == 2'b10 ? n8 :
+  n1972 == 2'b01 ? n15 :
+  n15;
+assign n1974 =
+  n1972 == 2'b00 ? n8 :
+  n1972 == 2'b10 ? n15 :
+  n1972 == 2'b01 ? n15 :
+  n8;
+assign n1978 = ~n1973;
+assign n1983 = n8;
+assign n1984 = {n8, n1983};
+assign n1985 = {n8, n1984};
+assign n1986 = {n8, n1985};
+assign n1987 = {n8, n1986};
+assign n1988 = {n8, n1987};
+assign n1989 = n1970 == n1988;
+assign n1990 = n1965 & n1978;
+assign n1994 = n1965 & n1973;
+assign n2002 =
+  n2001 == 1'b0 ? n1993 :
+  n1997;
+assign n2004 = n2007 + n33;
+assign n2009 = {n1930, n2014};
+assign n2010 =
+  n2009 == 2'b00 ? n8 :
+  n2009 == 2'b10 ? n8 :
+  n2009 == 2'b01 ? n15 :
+  n15;
+assign n2011 =
+  n2009 == 2'b00 ? n8 :
+  n2009 == 2'b10 ? n15 :
+  n2009 == 2'b01 ? n15 :
+  n8;
+assign n2015 = ~n2010;
+assign n2027 = n1964 & n2015;
+assign n2031 = n1964 & n2010;
+assign n2039 =
+  n2038 == 1'b0 ? n2030 :
+  n2034;
+assign n2040 = {n1989, n1982};
+assign n2042 = {n2040, n2047};
+assign n2043 =
+  n2042 == 3'b000 ? n8 :
+  n2042 == 3'b010 ? n8 :
+  n2042 == 3'b100 ? n8 :
+  n2042 == 3'b110 ? n8 :
+  n2042 == 3'b001 ? n15 :
+  n2042 == 3'b011 ? n15 :
+  n2042 == 3'b101 ? n15 :
+  n15;
+assign n2044 =
+  n2042 == 3'b000 ? n8 :
+  n2042 == 3'b010 ? n8 :
+  n2042 == 3'b100 ? n15 :
+  n2042 == 3'b110 ? n8 :
+  n2042 == 3'b001 ? n15 :
+  n2042 == 3'b011 ? n8 :
+  n2042 == 3'b101 ? n15 :
+  n8;
+assign n2048 = {n2002[31],
+  n2002[30],
+  n2002[29],
+  n2002[28],
+  n2002[27],
+  n2002[26],
+  n2002[25],
+  n2002[24],
+  n2002[23],
+  n2002[22],
+  n2002[21],
+  n2002[20],
+  n2002[19],
+  n2002[18],
+  n2002[17],
+  n2002[16]};
+assign n2049 = {n2002[15],
+  n2002[14],
+  n2002[13],
+  n2002[12],
+  n2002[11],
+  n2002[10],
+  n2002[9],
+  n2002[8],
+  n2002[7],
+  n2002[6],
+  n2002[5],
+  n2002[4],
+  n2002[3],
+  n2002[2],
+  n2002[1],
+  n2002[0]};
+assign n2050 = {n2039[31],
+  n2039[30],
+  n2039[29],
+  n2039[28],
+  n2039[27],
+  n2039[26],
+  n2039[25],
+  n2039[24],
+  n2039[23],
+  n2039[22],
+  n2039[21],
+  n2039[20],
+  n2039[19],
+  n2039[18],
+  n2039[17],
+  n2039[16]};
+assign n2051 = {n2039[15],
+  n2039[14],
+  n2039[13],
+  n2039[12],
+  n2039[11],
+  n2039[10],
+  n2039[9],
+  n2039[8],
+  n2039[7],
+  n2039[6],
+  n2039[5],
+  n2039[4],
+  n2039[3],
+  n2039[2],
+  n2039[1],
+  n2039[0]};
+assign n2052 =
+  n2043 == 1'b0 ? n2048 :
+  n2049;
+assign n2053 =
+  n2043 == 1'b0 ? n2050 :
+  n2051;
+assign sync_o = n1982;
+assign data_0_o = n2052;
+assign data_1_o = n2053;
+assign n2059 = enable_i & n15;
+assign n2060 = n8 | n2059;
+assign n2061 = n15 & n2060;
+assign n2062 = reset_i | n8;
+assign n2063 = n1930 | n2062;
+assign n2064 = n1930 | n2062;
+assign n2065 = n1822 & n15;
+assign n2066 = n2062 | n2065;
+assign n2067 = n2061 & n2066;
+assign n2068 = n1741 | n2062;
+assign n2069 = n1689 | n2062;
+assign n2070 = n1689 | n2062;
+assign n2071 = n1581 & n15;
+assign n2072 = n2062 | n2071;
+assign n2073 = n2061 & n2072;
+assign n2074 = n1500 | n2062;
+assign n2075 = n1448 | n2062;
+assign n2076 = n1448 | n2062;
+assign n2077 = n1340 & n15;
+assign n2078 = n2062 | n2077;
+assign n2079 = n2061 & n2078;
+assign n2080 = n1259 | n2062;
+assign n2081 = n1207 | n2062;
+assign n2082 = n1207 | n2062;
+assign n2083 = n1099 & n15;
+assign n2084 = n2062 | n2083;
+assign n2085 = n2061 & n2084;
+assign n2086 = n1018 | n2062;
+assign n2087 = n966 | n2062;
+assign n2088 = n966 | n2062;
+assign n2089 = n858 & n15;
+assign n2090 = n2062 | n2089;
+assign n2091 = n2061 & n2090;
+assign n2092 = n777 | n2062;
+assign n2093 = n725 | n2062;
+assign n2094 = n725 | n2062;
+assign n2095 = n617 & n15;
+assign n2096 = n2062 | n2095;
+assign n2097 = n2061 & n2096;
+assign n2098 = n536 | n2062;
+assign n2099 = n484 | n2062;
+assign n2100 = n484 | n2062;
+assign n2101 = n376 & n15;
+assign n2102 = n2062 | n2101;
+assign n2103 = n2061 & n2102;
+assign n2104 = n295 | n2062;
+assign n2105 = n243 | n2062;
+assign n2106 = n243 | n2062;
+assign n2107 = n134 & n15;
+assign n2108 = n2062 | n2107;
+assign n2109 = n2061 & n2108;
+assign n2110 = n51 | n2062;
+assign n2111 = n27 | n2062;
+assign n2112 = n27 | n2062;
+assign n2113 = n18 & n15;
+assign n2114 = n2062 | n2113;
+assign n2115 = n2061 & n2114;
+assign n2116 = sync_i | n2062;
+always @ (posedge clock_c)
+  if (n2115 == 1'b1)
+    if (n2116 == 1'b1)
+      n11 <= 7'b0000000;
+    else
+      n11 <= n7;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n22 <= 1'b0;
+    else
+      n22 <= n19;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n26 <= 1'b0;
+    else
+      n26 <= n18;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2112 == 1'b1)
+      n39 <= 6'b000000;
+    else
+      n39 <= n36;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n46 <= 1'b0;
+    else
+      n46 <= n43;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n51 <= 1'b0;
+    else
+      n51 <= n27;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n60 == 1'b1)
+      n64m <= n28;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n64ra <= n39;
+  end
+assign n64 = n64m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n65 == 1'b1)
+      n68m <= n28;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n68ra <= n39;
+  end
+assign n68 = n68m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n72 <= 1'b0;
+    else
+      n72 <= n47;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2111 == 1'b1)
+      n78 <= 6'b000000;
+    else
+      n78 <= n75;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n85 <= 1'b0;
+    else
+      n85 <= n82;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n98 == 1'b1)
+      n101m <= n28;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n101ra <= n78;
+  end
+assign n101 = n101m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n102 == 1'b1)
+      n105m <= n28;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n105ra <= n78;
+  end
+assign n105 = n105m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n109 <= 1'b0;
+    else
+      n109 <= n86;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n118 <= 1'b0;
+    else
+      n118 <= n115;
+always @ (posedge clock_c)
+  if (n2109 == 1'b1)
+    if (n2110 == 1'b1)
+      n129 <= 7'b0000000;
+    else
+      n129 <= n126;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n138 <= 1'b0;
+    else
+      n138 <= n135;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n142 <= 1'b0;
+    else
+      n142 <= n134;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n148 <= 16'b0000000000000000;
+    else
+      n148 <= n123;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n154 <= 16'b0000000000000000;
+    else
+      n154 <= n124;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n161 <= 8'b00000000;
+    else
+      n161 <= n149;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n165 <= 8'b00000000;
+    else
+      n165 <= n161;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n169 <= 8'b00000000;
+    else
+      n169 <= n150;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n173 <= 8'b00000000;
+    else
+      n173 <= n169;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    case (n8)
+      1'b0 : n176 <= 16'b0111111100000000;
+      1'b1 : n176 <= 16'b0000000010000000;
+    endcase
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n184 <= 8'b00000000;
+    else
+      n184 <= n180;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n190 <= 8'b00000000;
+    else
+      n190 <= n186;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n195 <= 8'b00000000;
+    else
+      n195 <= n191;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n201 <= 8'b00000000;
+    else
+      n201 <= n197;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n207 <= 8'b00000000;
+    else
+      n207 <= n203;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n212 <= 8'b00000000;
+    else
+      n212 <= n208;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n219 <= 16'b0000000000000000;
+    else
+      n219 <= n215;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n226 <= 16'b0000000000000000;
+    else
+      n226 <= n222;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n231 <= 1'b0;
+    else
+      n231 <= n143;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n235 <= 1'b0;
+    else
+      n235 <= n231;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n239 <= 1'b0;
+    else
+      n239 <= n235;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n243 <= 1'b0;
+    else
+      n243 <= n239;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n248 <= 6'b000000;
+    else
+      n248 <= n244;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n252 <= 6'b000000;
+    else
+      n252 <= n248;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n256 <= 6'b000000;
+    else
+      n256 <= n252;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n260 <= 6'b000000;
+    else
+      n260 <= n256;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n265 <= 1'b0;
+    else
+      n265 <= n261;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n269 <= 1'b0;
+    else
+      n269 <= n265;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n273 <= 1'b0;
+    else
+      n273 <= n269;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n277 <= 1'b0;
+    else
+      n277 <= n273;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2106 == 1'b1)
+      n283 <= 6'b000000;
+    else
+      n283 <= n280;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n290 <= 1'b0;
+    else
+      n290 <= n287;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n295 <= 1'b0;
+    else
+      n295 <= n243;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n303 == 1'b1)
+      n306m <= n227;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n306ra <= n283;
+  end
+assign n306 = n306m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n307 == 1'b1)
+      n310m <= n227;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n310ra <= n283;
+  end
+assign n310 = n310m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n314 <= 1'b0;
+    else
+      n314 <= n291;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2105 == 1'b1)
+      n320 <= 6'b000000;
+    else
+      n320 <= n317;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n327 <= 1'b0;
+    else
+      n327 <= n324;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n340 == 1'b1)
+      n343m <= n227;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n343ra <= n320;
+  end
+assign n343 = n343m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n344 == 1'b1)
+      n347m <= n227;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n347ra <= n320;
+  end
+assign n347 = n347m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n351 <= 1'b0;
+    else
+      n351 <= n328;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n360 <= 1'b0;
+    else
+      n360 <= n357;
+always @ (posedge clock_c)
+  if (n2103 == 1'b1)
+    if (n2104 == 1'b1)
+      n371 <= 7'b0000000;
+    else
+      n371 <= n368;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n380 <= 1'b0;
+    else
+      n380 <= n377;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n384 <= 1'b0;
+    else
+      n384 <= n376;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n390 <= 16'b0000000000000000;
+    else
+      n390 <= n365;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n396 <= 16'b0000000000000000;
+    else
+      n396 <= n366;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n402 <= 8'b00000000;
+    else
+      n402 <= n391;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n406 <= 8'b00000000;
+    else
+      n406 <= n402;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n410 <= 8'b00000000;
+    else
+      n410 <= n392;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n414 <= 8'b00000000;
+    else
+      n414 <= n410;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    case (n386)
+      1'b0 : n417 <= 16'b0111111100000000;
+      1'b1 : n417 <= 16'b0000000010000000;
+    endcase
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n425 <= 8'b00000000;
+    else
+      n425 <= n421;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n431 <= 8'b00000000;
+    else
+      n431 <= n427;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n436 <= 8'b00000000;
+    else
+      n436 <= n432;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n442 <= 8'b00000000;
+    else
+      n442 <= n438;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n448 <= 8'b00000000;
+    else
+      n448 <= n444;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n453 <= 8'b00000000;
+    else
+      n453 <= n449;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n460 <= 16'b0000000000000000;
+    else
+      n460 <= n456;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n467 <= 16'b0000000000000000;
+    else
+      n467 <= n463;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n472 <= 1'b0;
+    else
+      n472 <= n385;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n476 <= 1'b0;
+    else
+      n476 <= n472;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n480 <= 1'b0;
+    else
+      n480 <= n476;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n484 <= 1'b0;
+    else
+      n484 <= n480;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n489 <= 6'b000000;
+    else
+      n489 <= n485;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n493 <= 6'b000000;
+    else
+      n493 <= n489;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n497 <= 6'b000000;
+    else
+      n497 <= n493;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n501 <= 6'b000000;
+    else
+      n501 <= n497;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n506 <= 1'b0;
+    else
+      n506 <= n502;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n510 <= 1'b0;
+    else
+      n510 <= n506;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n514 <= 1'b0;
+    else
+      n514 <= n510;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n518 <= 1'b0;
+    else
+      n518 <= n514;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2100 == 1'b1)
+      n524 <= 6'b000000;
+    else
+      n524 <= n521;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n531 <= 1'b0;
+    else
+      n531 <= n528;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n536 <= 1'b0;
+    else
+      n536 <= n484;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n544 == 1'b1)
+      n547m <= n468;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n547ra <= n524;
+  end
+assign n547 = n547m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n548 == 1'b1)
+      n551m <= n468;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n551ra <= n524;
+  end
+assign n551 = n551m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n555 <= 1'b0;
+    else
+      n555 <= n532;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2099 == 1'b1)
+      n561 <= 6'b000000;
+    else
+      n561 <= n558;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n568 <= 1'b0;
+    else
+      n568 <= n565;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n581 == 1'b1)
+      n584m <= n468;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n584ra <= n561;
+  end
+assign n584 = n584m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n585 == 1'b1)
+      n588m <= n468;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n588ra <= n561;
+  end
+assign n588 = n588m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n592 <= 1'b0;
+    else
+      n592 <= n569;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n601 <= 1'b0;
+    else
+      n601 <= n598;
+always @ (posedge clock_c)
+  if (n2097 == 1'b1)
+    if (n2098 == 1'b1)
+      n612 <= 7'b0000000;
+    else
+      n612 <= n609;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n621 <= 1'b0;
+    else
+      n621 <= n618;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n625 <= 1'b0;
+    else
+      n625 <= n617;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n631 <= 16'b0000000000000000;
+    else
+      n631 <= n606;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n637 <= 16'b0000000000000000;
+    else
+      n637 <= n607;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n643 <= 8'b00000000;
+    else
+      n643 <= n632;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n647 <= 8'b00000000;
+    else
+      n647 <= n643;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n651 <= 8'b00000000;
+    else
+      n651 <= n633;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n655 <= 8'b00000000;
+    else
+      n655 <= n651;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    case (n627)
+      2'b00 : n658 <= 16'b0111111100000000;
+      2'b01 : n658 <= 16'b0101101010100101;
+      2'b10 : n658 <= 16'b0000000010000000;
+      2'b11 : n658 <= 16'b1010010110100101;
+    endcase
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n666 <= 8'b00000000;
+    else
+      n666 <= n662;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n672 <= 8'b00000000;
+    else
+      n672 <= n668;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n677 <= 8'b00000000;
+    else
+      n677 <= n673;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n683 <= 8'b00000000;
+    else
+      n683 <= n679;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n689 <= 8'b00000000;
+    else
+      n689 <= n685;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n694 <= 8'b00000000;
+    else
+      n694 <= n690;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n701 <= 16'b0000000000000000;
+    else
+      n701 <= n697;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n708 <= 16'b0000000000000000;
+    else
+      n708 <= n704;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n713 <= 1'b0;
+    else
+      n713 <= n626;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n717 <= 1'b0;
+    else
+      n717 <= n713;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n721 <= 1'b0;
+    else
+      n721 <= n717;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n725 <= 1'b0;
+    else
+      n725 <= n721;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n730 <= 6'b000000;
+    else
+      n730 <= n726;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n734 <= 6'b000000;
+    else
+      n734 <= n730;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n738 <= 6'b000000;
+    else
+      n738 <= n734;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n742 <= 6'b000000;
+    else
+      n742 <= n738;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n747 <= 1'b0;
+    else
+      n747 <= n743;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n751 <= 1'b0;
+    else
+      n751 <= n747;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n755 <= 1'b0;
+    else
+      n755 <= n751;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n759 <= 1'b0;
+    else
+      n759 <= n755;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2094 == 1'b1)
+      n765 <= 6'b000000;
+    else
+      n765 <= n762;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n772 <= 1'b0;
+    else
+      n772 <= n769;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n777 <= 1'b0;
+    else
+      n777 <= n725;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n785 == 1'b1)
+      n788m <= n709;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n788ra <= n765;
+  end
+assign n788 = n788m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n789 == 1'b1)
+      n792m <= n709;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n792ra <= n765;
+  end
+assign n792 = n792m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n796 <= 1'b0;
+    else
+      n796 <= n773;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2093 == 1'b1)
+      n802 <= 6'b000000;
+    else
+      n802 <= n799;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n809 <= 1'b0;
+    else
+      n809 <= n806;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n822 == 1'b1)
+      n825m <= n709;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n825ra <= n802;
+  end
+assign n825 = n825m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n826 == 1'b1)
+      n829m <= n709;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n829ra <= n802;
+  end
+assign n829 = n829m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n833 <= 1'b0;
+    else
+      n833 <= n810;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n842 <= 1'b0;
+    else
+      n842 <= n839;
+always @ (posedge clock_c)
+  if (n2091 == 1'b1)
+    if (n2092 == 1'b1)
+      n853 <= 7'b0000000;
+    else
+      n853 <= n850;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n862 <= 1'b0;
+    else
+      n862 <= n859;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n866 <= 1'b0;
+    else
+      n866 <= n858;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n872 <= 16'b0000000000000000;
+    else
+      n872 <= n847;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n878 <= 16'b0000000000000000;
+    else
+      n878 <= n848;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n884 <= 8'b00000000;
+    else
+      n884 <= n873;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n888 <= 8'b00000000;
+    else
+      n888 <= n884;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n892 <= 8'b00000000;
+    else
+      n892 <= n874;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n896 <= 8'b00000000;
+    else
+      n896 <= n892;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    case (n868)
+      3'b000 : n899 <= 16'b0111111100000000;
+      3'b001 : n899 <= 16'b0111011011001111;
+      3'b010 : n899 <= 16'b0101101010100101;
+      3'b011 : n899 <= 16'b0011000010001001;
+      3'b100 : n899 <= 16'b0000000010000000;
+      3'b101 : n899 <= 16'b1100111110001001;
+      3'b110 : n899 <= 16'b1010010110100101;
+      3'b111 : n899 <= 16'b1000100111001111;
+    endcase
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n907 <= 8'b00000000;
+    else
+      n907 <= n903;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n913 <= 8'b00000000;
+    else
+      n913 <= n909;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n918 <= 8'b00000000;
+    else
+      n918 <= n914;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n924 <= 8'b00000000;
+    else
+      n924 <= n920;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n930 <= 8'b00000000;
+    else
+      n930 <= n926;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n935 <= 8'b00000000;
+    else
+      n935 <= n931;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n942 <= 16'b0000000000000000;
+    else
+      n942 <= n938;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n949 <= 16'b0000000000000000;
+    else
+      n949 <= n945;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n954 <= 1'b0;
+    else
+      n954 <= n867;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n958 <= 1'b0;
+    else
+      n958 <= n954;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n962 <= 1'b0;
+    else
+      n962 <= n958;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n966 <= 1'b0;
+    else
+      n966 <= n962;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n971 <= 6'b000000;
+    else
+      n971 <= n967;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n975 <= 6'b000000;
+    else
+      n975 <= n971;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n979 <= 6'b000000;
+    else
+      n979 <= n975;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n983 <= 6'b000000;
+    else
+      n983 <= n979;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n988 <= 1'b0;
+    else
+      n988 <= n984;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n992 <= 1'b0;
+    else
+      n992 <= n988;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n996 <= 1'b0;
+    else
+      n996 <= n992;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1000 <= 1'b0;
+    else
+      n1000 <= n996;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2088 == 1'b1)
+      n1006 <= 6'b000000;
+    else
+      n1006 <= n1003;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1013 <= 1'b0;
+    else
+      n1013 <= n1010;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1018 <= 1'b0;
+    else
+      n1018 <= n966;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1026 == 1'b1)
+      n1029m <= n950;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1029ra <= n1006;
+  end
+assign n1029 = n1029m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1030 == 1'b1)
+      n1033m <= n950;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1033ra <= n1006;
+  end
+assign n1033 = n1033m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1037 <= 1'b0;
+    else
+      n1037 <= n1014;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2087 == 1'b1)
+      n1043 <= 6'b000000;
+    else
+      n1043 <= n1040;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1050 <= 1'b0;
+    else
+      n1050 <= n1047;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1063 == 1'b1)
+      n1066m <= n950;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1066ra <= n1043;
+  end
+assign n1066 = n1066m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1067 == 1'b1)
+      n1070m <= n950;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1070ra <= n1043;
+  end
+assign n1070 = n1070m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1074 <= 1'b0;
+    else
+      n1074 <= n1051;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1083 <= 1'b0;
+    else
+      n1083 <= n1080;
+always @ (posedge clock_c)
+  if (n2085 == 1'b1)
+    if (n2086 == 1'b1)
+      n1094 <= 7'b0000000;
+    else
+      n1094 <= n1091;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1103 <= 1'b0;
+    else
+      n1103 <= n1100;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1107 <= 1'b0;
+    else
+      n1107 <= n1099;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1113 <= 16'b0000000000000000;
+    else
+      n1113 <= n1088;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1119 <= 16'b0000000000000000;
+    else
+      n1119 <= n1089;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1125 <= 8'b00000000;
+    else
+      n1125 <= n1114;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1129 <= 8'b00000000;
+    else
+      n1129 <= n1125;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1133 <= 8'b00000000;
+    else
+      n1133 <= n1115;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1137 <= 8'b00000000;
+    else
+      n1137 <= n1133;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    case (n1109)
+      4'b0000 : n1140 <= 16'b0111111100000000;
+      4'b0001 : n1140 <= 16'b0111110111100111;
+      4'b0010 : n1140 <= 16'b0111011011001111;
+      4'b0011 : n1140 <= 16'b0110101010111000;
+      4'b0100 : n1140 <= 16'b0101101010100101;
+      4'b0101 : n1140 <= 16'b0100011110010101;
+      4'b0110 : n1140 <= 16'b0011000010001001;
+      4'b0111 : n1140 <= 16'b0001100010000010;
+      4'b1000 : n1140 <= 16'b0000000010000000;
+      4'b1001 : n1140 <= 16'b1110011110000010;
+      4'b1010 : n1140 <= 16'b1100111110001001;
+      4'b1011 : n1140 <= 16'b1011100010010101;
+      4'b1100 : n1140 <= 16'b1010010110100101;
+      4'b1101 : n1140 <= 16'b1001010110111000;
+      4'b1110 : n1140 <= 16'b1000100111001111;
+      4'b1111 : n1140 <= 16'b1000001011100111;
+    endcase
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1148 <= 8'b00000000;
+    else
+      n1148 <= n1144;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1154 <= 8'b00000000;
+    else
+      n1154 <= n1150;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1159 <= 8'b00000000;
+    else
+      n1159 <= n1155;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1165 <= 8'b00000000;
+    else
+      n1165 <= n1161;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1171 <= 8'b00000000;
+    else
+      n1171 <= n1167;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1176 <= 8'b00000000;
+    else
+      n1176 <= n1172;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1183 <= 16'b0000000000000000;
+    else
+      n1183 <= n1179;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1190 <= 16'b0000000000000000;
+    else
+      n1190 <= n1186;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1195 <= 1'b0;
+    else
+      n1195 <= n1108;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1199 <= 1'b0;
+    else
+      n1199 <= n1195;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1203 <= 1'b0;
+    else
+      n1203 <= n1199;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1207 <= 1'b0;
+    else
+      n1207 <= n1203;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1212 <= 6'b000000;
+    else
+      n1212 <= n1208;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1216 <= 6'b000000;
+    else
+      n1216 <= n1212;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1220 <= 6'b000000;
+    else
+      n1220 <= n1216;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1224 <= 6'b000000;
+    else
+      n1224 <= n1220;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1229 <= 1'b0;
+    else
+      n1229 <= n1225;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1233 <= 1'b0;
+    else
+      n1233 <= n1229;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1237 <= 1'b0;
+    else
+      n1237 <= n1233;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1241 <= 1'b0;
+    else
+      n1241 <= n1237;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2082 == 1'b1)
+      n1247 <= 6'b000000;
+    else
+      n1247 <= n1244;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1254 <= 1'b0;
+    else
+      n1254 <= n1251;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1259 <= 1'b0;
+    else
+      n1259 <= n1207;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1267 == 1'b1)
+      n1270m <= n1191;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1270ra <= n1247;
+  end
+assign n1270 = n1270m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1271 == 1'b1)
+      n1274m <= n1191;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1274ra <= n1247;
+  end
+assign n1274 = n1274m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1278 <= 1'b0;
+    else
+      n1278 <= n1255;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2081 == 1'b1)
+      n1284 <= 6'b000000;
+    else
+      n1284 <= n1281;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1291 <= 1'b0;
+    else
+      n1291 <= n1288;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1304 == 1'b1)
+      n1307m <= n1191;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1307ra <= n1284;
+  end
+assign n1307 = n1307m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1308 == 1'b1)
+      n1311m <= n1191;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1311ra <= n1284;
+  end
+assign n1311 = n1311m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1315 <= 1'b0;
+    else
+      n1315 <= n1292;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1324 <= 1'b0;
+    else
+      n1324 <= n1321;
+always @ (posedge clock_c)
+  if (n2079 == 1'b1)
+    if (n2080 == 1'b1)
+      n1335 <= 7'b0000000;
+    else
+      n1335 <= n1332;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1344 <= 1'b0;
+    else
+      n1344 <= n1341;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1348 <= 1'b0;
+    else
+      n1348 <= n1340;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1354 <= 16'b0000000000000000;
+    else
+      n1354 <= n1329;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1360 <= 16'b0000000000000000;
+    else
+      n1360 <= n1330;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1366 <= 8'b00000000;
+    else
+      n1366 <= n1355;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1370 <= 8'b00000000;
+    else
+      n1370 <= n1366;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1374 <= 8'b00000000;
+    else
+      n1374 <= n1356;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1378 <= 8'b00000000;
+    else
+      n1378 <= n1374;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    case (n1350)
+      5'b00000 : n1381 <= 16'b0111111100000000;
+      5'b00001 : n1381 <= 16'b0111111111110011;
+      5'b00010 : n1381 <= 16'b0111110111100111;
+      5'b00011 : n1381 <= 16'b0111101011011010;
+      5'b00100 : n1381 <= 16'b0111011011001111;
+      5'b00101 : n1381 <= 16'b0111000011000011;
+      5'b00110 : n1381 <= 16'b0110101010111000;
+      5'b00111 : n1381 <= 16'b0110001010101110;
+      5'b01000 : n1381 <= 16'b0101101010100101;
+      5'b01001 : n1381 <= 16'b0101000110011101;
+      5'b01010 : n1381 <= 16'b0100011110010101;
+      5'b01011 : n1381 <= 16'b0011110010001111;
+      5'b01100 : n1381 <= 16'b0011000010001001;
+      5'b01101 : n1381 <= 16'b0010010110000101;
+      5'b01110 : n1381 <= 16'b0001100010000010;
+      5'b01111 : n1381 <= 16'b0000110010000000;
+      5'b10000 : n1381 <= 16'b0000000010000000;
+      5'b10001 : n1381 <= 16'b1111001110000000;
+      5'b10010 : n1381 <= 16'b1110011110000010;
+      5'b10011 : n1381 <= 16'b1101101010000101;
+      5'b10100 : n1381 <= 16'b1100111110001001;
+      5'b10101 : n1381 <= 16'b1100001110001111;
+      5'b10110 : n1381 <= 16'b1011100010010101;
+      5'b10111 : n1381 <= 16'b1010111010011101;
+      5'b11000 : n1381 <= 16'b1010010110100101;
+      5'b11001 : n1381 <= 16'b1001110110101110;
+      5'b11010 : n1381 <= 16'b1001010110111000;
+      5'b11011 : n1381 <= 16'b1000111111000011;
+      5'b11100 : n1381 <= 16'b1000100111001111;
+      5'b11101 : n1381 <= 16'b1000010111011010;
+      5'b11110 : n1381 <= 16'b1000001011100111;
+      5'b11111 : n1381 <= 16'b1000000011110011;
+    endcase
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1389 <= 8'b00000000;
+    else
+      n1389 <= n1385;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1395 <= 8'b00000000;
+    else
+      n1395 <= n1391;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1400 <= 8'b00000000;
+    else
+      n1400 <= n1396;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1406 <= 8'b00000000;
+    else
+      n1406 <= n1402;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1412 <= 8'b00000000;
+    else
+      n1412 <= n1408;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1417 <= 8'b00000000;
+    else
+      n1417 <= n1413;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1424 <= 16'b0000000000000000;
+    else
+      n1424 <= n1420;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1431 <= 16'b0000000000000000;
+    else
+      n1431 <= n1427;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1436 <= 1'b0;
+    else
+      n1436 <= n1349;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1440 <= 1'b0;
+    else
+      n1440 <= n1436;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1444 <= 1'b0;
+    else
+      n1444 <= n1440;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1448 <= 1'b0;
+    else
+      n1448 <= n1444;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1453 <= 6'b000000;
+    else
+      n1453 <= n1449;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1457 <= 6'b000000;
+    else
+      n1457 <= n1453;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1461 <= 6'b000000;
+    else
+      n1461 <= n1457;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1465 <= 6'b000000;
+    else
+      n1465 <= n1461;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1470 <= 1'b0;
+    else
+      n1470 <= n1466;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1474 <= 1'b0;
+    else
+      n1474 <= n1470;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1478 <= 1'b0;
+    else
+      n1478 <= n1474;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1482 <= 1'b0;
+    else
+      n1482 <= n1478;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2076 == 1'b1)
+      n1488 <= 6'b000000;
+    else
+      n1488 <= n1485;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1495 <= 1'b0;
+    else
+      n1495 <= n1492;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1500 <= 1'b0;
+    else
+      n1500 <= n1448;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1508 == 1'b1)
+      n1511m <= n1432;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1511ra <= n1488;
+  end
+assign n1511 = n1511m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1512 == 1'b1)
+      n1515m <= n1432;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1515ra <= n1488;
+  end
+assign n1515 = n1515m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1519 <= 1'b0;
+    else
+      n1519 <= n1496;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2075 == 1'b1)
+      n1525 <= 6'b000000;
+    else
+      n1525 <= n1522;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1532 <= 1'b0;
+    else
+      n1532 <= n1529;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1545 == 1'b1)
+      n1548m <= n1432;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1548ra <= n1525;
+  end
+assign n1548 = n1548m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1549 == 1'b1)
+      n1552m <= n1432;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1552ra <= n1525;
+  end
+assign n1552 = n1552m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1556 <= 1'b0;
+    else
+      n1556 <= n1533;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1565 <= 1'b0;
+    else
+      n1565 <= n1562;
+always @ (posedge clock_c)
+  if (n2073 == 1'b1)
+    if (n2074 == 1'b1)
+      n1576 <= 7'b0000000;
+    else
+      n1576 <= n1573;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1585 <= 1'b0;
+    else
+      n1585 <= n1582;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1589 <= 1'b0;
+    else
+      n1589 <= n1581;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1595 <= 16'b0000000000000000;
+    else
+      n1595 <= n1570;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1601 <= 16'b0000000000000000;
+    else
+      n1601 <= n1571;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1607 <= 8'b00000000;
+    else
+      n1607 <= n1596;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1611 <= 8'b00000000;
+    else
+      n1611 <= n1607;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1615 <= 8'b00000000;
+    else
+      n1615 <= n1597;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1619 <= 8'b00000000;
+    else
+      n1619 <= n1615;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    case (n1591)
+      6'b000000 : n1622 <= 16'b0111111100000000;
+      6'b000001 : n1622 <= 16'b0111111111111001;
+      6'b000010 : n1622 <= 16'b0111111111110011;
+      6'b000011 : n1622 <= 16'b0111111011101101;
+      6'b000100 : n1622 <= 16'b0111110111100111;
+      6'b000101 : n1622 <= 16'b0111110011100000;
+      6'b000110 : n1622 <= 16'b0111101011011010;
+      6'b000111 : n1622 <= 16'b0111100011010100;
+      6'b001000 : n1622 <= 16'b0111011011001111;
+      6'b001001 : n1622 <= 16'b0111001111001001;
+      6'b001010 : n1622 <= 16'b0111000011000011;
+      6'b001011 : n1622 <= 16'b0110110110111110;
+      6'b001100 : n1622 <= 16'b0110101010111000;
+      6'b001101 : n1622 <= 16'b0110011010110011;
+      6'b001110 : n1622 <= 16'b0110001010101110;
+      6'b001111 : n1622 <= 16'b0101111010101010;
+      6'b010000 : n1622 <= 16'b0101101010100101;
+      6'b010001 : n1622 <= 16'b0101010110100001;
+      6'b010010 : n1622 <= 16'b0101000110011101;
+      6'b010011 : n1622 <= 16'b0100110010011001;
+      6'b010100 : n1622 <= 16'b0100011110010101;
+      6'b010101 : n1622 <= 16'b0100000110010010;
+      6'b010110 : n1622 <= 16'b0011110010001111;
+      6'b010111 : n1622 <= 16'b0011011010001100;
+      6'b011000 : n1622 <= 16'b0011000010001001;
+      6'b011001 : n1622 <= 16'b0010101110000111;
+      6'b011010 : n1622 <= 16'b0010010110000101;
+      6'b011011 : n1622 <= 16'b0001111110000011;
+      6'b011100 : n1622 <= 16'b0001100010000010;
+      6'b011101 : n1622 <= 16'b0001001010000001;
+      6'b011110 : n1622 <= 16'b0000110010000000;
+      6'b011111 : n1622 <= 16'b0000011010000000;
+      6'b100000 : n1622 <= 16'b0000000010000000;
+      6'b100001 : n1622 <= 16'b1111100110000000;
+      6'b100010 : n1622 <= 16'b1111001110000000;
+      6'b100011 : n1622 <= 16'b1110110110000001;
+      6'b100100 : n1622 <= 16'b1110011110000010;
+      6'b100101 : n1622 <= 16'b1110000010000011;
+      6'b100110 : n1622 <= 16'b1101101010000101;
+      6'b100111 : n1622 <= 16'b1101010010000111;
+      6'b101000 : n1622 <= 16'b1100111110001001;
+      6'b101001 : n1622 <= 16'b1100100110001100;
+      6'b101010 : n1622 <= 16'b1100001110001111;
+      6'b101011 : n1622 <= 16'b1011111010010010;
+      6'b101100 : n1622 <= 16'b1011100010010101;
+      6'b101101 : n1622 <= 16'b1011001110011001;
+      6'b101110 : n1622 <= 16'b1010111010011101;
+      6'b101111 : n1622 <= 16'b1010101010100001;
+      6'b110000 : n1622 <= 16'b1010010110100101;
+      6'b110001 : n1622 <= 16'b1010000110101010;
+      6'b110010 : n1622 <= 16'b1001110110101110;
+      6'b110011 : n1622 <= 16'b1001100110110011;
+      6'b110100 : n1622 <= 16'b1001010110111000;
+      6'b110101 : n1622 <= 16'b1001001010111110;
+      6'b110110 : n1622 <= 16'b1000111111000011;
+      6'b110111 : n1622 <= 16'b1000110011001001;
+      6'b111000 : n1622 <= 16'b1000100111001111;
+      6'b111001 : n1622 <= 16'b1000011111010100;
+      6'b111010 : n1622 <= 16'b1000010111011010;
+      6'b111011 : n1622 <= 16'b1000001111100000;
+      6'b111100 : n1622 <= 16'b1000001011100111;
+      6'b111101 : n1622 <= 16'b1000000111101101;
+      6'b111110 : n1622 <= 16'b1000000011110011;
+      6'b111111 : n1622 <= 16'b1000000011111001;
+    endcase
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1630 <= 8'b00000000;
+    else
+      n1630 <= n1626;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1636 <= 8'b00000000;
+    else
+      n1636 <= n1632;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1641 <= 8'b00000000;
+    else
+      n1641 <= n1637;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1647 <= 8'b00000000;
+    else
+      n1647 <= n1643;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1653 <= 8'b00000000;
+    else
+      n1653 <= n1649;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1658 <= 8'b00000000;
+    else
+      n1658 <= n1654;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1665 <= 16'b0000000000000000;
+    else
+      n1665 <= n1661;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1672 <= 16'b0000000000000000;
+    else
+      n1672 <= n1668;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1677 <= 1'b0;
+    else
+      n1677 <= n1590;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1681 <= 1'b0;
+    else
+      n1681 <= n1677;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1685 <= 1'b0;
+    else
+      n1685 <= n1681;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1689 <= 1'b0;
+    else
+      n1689 <= n1685;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1694 <= 6'b000000;
+    else
+      n1694 <= n1690;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1698 <= 6'b000000;
+    else
+      n1698 <= n1694;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1702 <= 6'b000000;
+    else
+      n1702 <= n1698;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1706 <= 6'b000000;
+    else
+      n1706 <= n1702;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1711 <= 1'b0;
+    else
+      n1711 <= n1707;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1715 <= 1'b0;
+    else
+      n1715 <= n1711;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1719 <= 1'b0;
+    else
+      n1719 <= n1715;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1723 <= 1'b0;
+    else
+      n1723 <= n1719;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2070 == 1'b1)
+      n1729 <= 6'b000000;
+    else
+      n1729 <= n1726;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1736 <= 1'b0;
+    else
+      n1736 <= n1733;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1741 <= 1'b0;
+    else
+      n1741 <= n1689;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1749 == 1'b1)
+      n1752m <= n1673;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1752ra <= n1729;
+  end
+assign n1752 = n1752m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1753 == 1'b1)
+      n1756m <= n1673;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1756ra <= n1729;
+  end
+assign n1756 = n1756m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1760 <= 1'b0;
+    else
+      n1760 <= n1737;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2069 == 1'b1)
+      n1766 <= 6'b000000;
+    else
+      n1766 <= n1763;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1773 <= 1'b0;
+    else
+      n1773 <= n1770;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1786 == 1'b1)
+      n1789m <= n1673;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1789ra <= n1766;
+  end
+assign n1789 = n1789m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1790 == 1'b1)
+      n1793m <= n1673;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1793ra <= n1766;
+  end
+assign n1793 = n1793m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1797 <= 1'b0;
+    else
+      n1797 <= n1774;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1806 <= 1'b0;
+    else
+      n1806 <= n1803;
+always @ (posedge clock_c)
+  if (n2067 == 1'b1)
+    if (n2068 == 1'b1)
+      n1817 <= 7'b0000000;
+    else
+      n1817 <= n1814;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1826 <= 1'b0;
+    else
+      n1826 <= n1823;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1830 <= 1'b0;
+    else
+      n1830 <= n1822;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1836 <= 16'b0000000000000000;
+    else
+      n1836 <= n1811;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1842 <= 16'b0000000000000000;
+    else
+      n1842 <= n1812;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1848 <= 8'b00000000;
+    else
+      n1848 <= n1837;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1852 <= 8'b00000000;
+    else
+      n1852 <= n1848;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1856 <= 8'b00000000;
+    else
+      n1856 <= n1838;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1860 <= 8'b00000000;
+    else
+      n1860 <= n1856;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    case (n1832)
+      7'b0000000 : n1863 <= 16'b0111111100000000;
+      7'b0000001 : n1863 <= 16'b0111111111111100;
+      7'b0000010 : n1863 <= 16'b0111111111111001;
+      7'b0000011 : n1863 <= 16'b0111111111110110;
+      7'b0000100 : n1863 <= 16'b0111111111110011;
+      7'b0000101 : n1863 <= 16'b0111111111110000;
+      7'b0000110 : n1863 <= 16'b0111111011101101;
+      7'b0000111 : n1863 <= 16'b0111111011101010;
+      7'b0001000 : n1863 <= 16'b0111110111100111;
+      7'b0001001 : n1863 <= 16'b0111110011100011;
+      7'b0001010 : n1863 <= 16'b0111110011100000;
+      7'b0001011 : n1863 <= 16'b0111101111011101;
+      7'b0001100 : n1863 <= 16'b0111101011011010;
+      7'b0001101 : n1863 <= 16'b0111100111010111;
+      7'b0001110 : n1863 <= 16'b0111100011010100;
+      7'b0001111 : n1863 <= 16'b0111011111010001;
+      7'b0010000 : n1863 <= 16'b0111011011001111;
+      7'b0010001 : n1863 <= 16'b0111010111001100;
+      7'b0010010 : n1863 <= 16'b0111001111001001;
+      7'b0010011 : n1863 <= 16'b0111001011000110;
+      7'b0010100 : n1863 <= 16'b0111000011000011;
+      7'b0010101 : n1863 <= 16'b0110111111000000;
+      7'b0010110 : n1863 <= 16'b0110110110111110;
+      7'b0010111 : n1863 <= 16'b0110110010111011;
+      7'b0011000 : n1863 <= 16'b0110101010111000;
+      7'b0011001 : n1863 <= 16'b0110100010110110;
+      7'b0011010 : n1863 <= 16'b0110011010110011;
+      7'b0011011 : n1863 <= 16'b0110010010110001;
+      7'b0011100 : n1863 <= 16'b0110001010101110;
+      7'b0011101 : n1863 <= 16'b0110000010101100;
+      7'b0011110 : n1863 <= 16'b0101111010101010;
+      7'b0011111 : n1863 <= 16'b0101110010100111;
+      7'b0100000 : n1863 <= 16'b0101101010100101;
+      7'b0100001 : n1863 <= 16'b0101100010100011;
+      7'b0100010 : n1863 <= 16'b0101010110100001;
+      7'b0100011 : n1863 <= 16'b0101001110011111;
+      7'b0100100 : n1863 <= 16'b0101000110011101;
+      7'b0100101 : n1863 <= 16'b0100111010011011;
+      7'b0100110 : n1863 <= 16'b0100110010011001;
+      7'b0100111 : n1863 <= 16'b0100100110010111;
+      7'b0101000 : n1863 <= 16'b0100011110010101;
+      7'b0101001 : n1863 <= 16'b0100010010010011;
+      7'b0101010 : n1863 <= 16'b0100000110010010;
+      7'b0101011 : n1863 <= 16'b0011111110010000;
+      7'b0101100 : n1863 <= 16'b0011110010001111;
+      7'b0101101 : n1863 <= 16'b0011100110001101;
+      7'b0101110 : n1863 <= 16'b0011011010001100;
+      7'b0101111 : n1863 <= 16'b0011001110001010;
+      7'b0110000 : n1863 <= 16'b0011000010001001;
+      7'b0110001 : n1863 <= 16'b0010111010001000;
+      7'b0110010 : n1863 <= 16'b0010101110000111;
+      7'b0110011 : n1863 <= 16'b0010100010000110;
+      7'b0110100 : n1863 <= 16'b0010010110000101;
+      7'b0110101 : n1863 <= 16'b0010001010000100;
+      7'b0110110 : n1863 <= 16'b0001111110000011;
+      7'b0110111 : n1863 <= 16'b0001110010000011;
+      7'b0111000 : n1863 <= 16'b0001100010000010;
+      7'b0111001 : n1863 <= 16'b0001010110000001;
+      7'b0111010 : n1863 <= 16'b0001001010000001;
+      7'b0111011 : n1863 <= 16'b0000111110000000;
+      7'b0111100 : n1863 <= 16'b0000110010000000;
+      7'b0111101 : n1863 <= 16'b0000100110000000;
+      7'b0111110 : n1863 <= 16'b0000011010000000;
+      7'b0111111 : n1863 <= 16'b0000001110000000;
+      7'b1000000 : n1863 <= 16'b0000000010000000;
+      7'b1000001 : n1863 <= 16'b1111110010000000;
+      7'b1000010 : n1863 <= 16'b1111100110000000;
+      7'b1000011 : n1863 <= 16'b1111011010000000;
+      7'b1000100 : n1863 <= 16'b1111001110000000;
+      7'b1000101 : n1863 <= 16'b1111000010000000;
+      7'b1000110 : n1863 <= 16'b1110110110000001;
+      7'b1000111 : n1863 <= 16'b1110101010000001;
+      7'b1001000 : n1863 <= 16'b1110011110000010;
+      7'b1001001 : n1863 <= 16'b1110001110000011;
+      7'b1001010 : n1863 <= 16'b1110000010000011;
+      7'b1001011 : n1863 <= 16'b1101110110000100;
+      7'b1001100 : n1863 <= 16'b1101101010000101;
+      7'b1001101 : n1863 <= 16'b1101011110000110;
+      7'b1001110 : n1863 <= 16'b1101010010000111;
+      7'b1001111 : n1863 <= 16'b1101000110001000;
+      7'b1010000 : n1863 <= 16'b1100111110001001;
+      7'b1010001 : n1863 <= 16'b1100110010001010;
+      7'b1010010 : n1863 <= 16'b1100100110001100;
+      7'b1010011 : n1863 <= 16'b1100011010001101;
+      7'b1010100 : n1863 <= 16'b1100001110001111;
+      7'b1010101 : n1863 <= 16'b1100000010010000;
+      7'b1010110 : n1863 <= 16'b1011111010010010;
+      7'b1010111 : n1863 <= 16'b1011101110010011;
+      7'b1011000 : n1863 <= 16'b1011100010010101;
+      7'b1011001 : n1863 <= 16'b1011011010010111;
+      7'b1011010 : n1863 <= 16'b1011001110011001;
+      7'b1011011 : n1863 <= 16'b1011000110011011;
+      7'b1011100 : n1863 <= 16'b1010111010011101;
+      7'b1011101 : n1863 <= 16'b1010110010011111;
+      7'b1011110 : n1863 <= 16'b1010101010100001;
+      7'b1011111 : n1863 <= 16'b1010011110100011;
+      7'b1100000 : n1863 <= 16'b1010010110100101;
+      7'b1100001 : n1863 <= 16'b1010001110100111;
+      7'b1100010 : n1863 <= 16'b1010000110101010;
+      7'b1100011 : n1863 <= 16'b1001111110101100;
+      7'b1100100 : n1863 <= 16'b1001110110101110;
+      7'b1100101 : n1863 <= 16'b1001101110110001;
+      7'b1100110 : n1863 <= 16'b1001100110110011;
+      7'b1100111 : n1863 <= 16'b1001011110110110;
+      7'b1101000 : n1863 <= 16'b1001010110111000;
+      7'b1101001 : n1863 <= 16'b1001001110111011;
+      7'b1101010 : n1863 <= 16'b1001001010111110;
+      7'b1101011 : n1863 <= 16'b1001000011000000;
+      7'b1101100 : n1863 <= 16'b1000111111000011;
+      7'b1101101 : n1863 <= 16'b1000110111000110;
+      7'b1101110 : n1863 <= 16'b1000110011001001;
+      7'b1101111 : n1863 <= 16'b1000101011001100;
+      7'b1110000 : n1863 <= 16'b1000100111001111;
+      7'b1110001 : n1863 <= 16'b1000100011010001;
+      7'b1110010 : n1863 <= 16'b1000011111010100;
+      7'b1110011 : n1863 <= 16'b1000011011010111;
+      7'b1110100 : n1863 <= 16'b1000010111011010;
+      7'b1110101 : n1863 <= 16'b1000010011011101;
+      7'b1110110 : n1863 <= 16'b1000001111100000;
+      7'b1110111 : n1863 <= 16'b1000001111100011;
+      7'b1111000 : n1863 <= 16'b1000001011100111;
+      7'b1111001 : n1863 <= 16'b1000000111101010;
+      7'b1111010 : n1863 <= 16'b1000000111101101;
+      7'b1111011 : n1863 <= 16'b1000000011110000;
+      7'b1111100 : n1863 <= 16'b1000000011110011;
+      7'b1111101 : n1863 <= 16'b1000000011110110;
+      7'b1111110 : n1863 <= 16'b1000000011111001;
+      7'b1111111 : n1863 <= 16'b1000000011111100;
+    endcase
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1871 <= 8'b00000000;
+    else
+      n1871 <= n1867;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1877 <= 8'b00000000;
+    else
+      n1877 <= n1873;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1882 <= 8'b00000000;
+    else
+      n1882 <= n1878;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1888 <= 8'b00000000;
+    else
+      n1888 <= n1884;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1894 <= 8'b00000000;
+    else
+      n1894 <= n1890;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1899 <= 8'b00000000;
+    else
+      n1899 <= n1895;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1906 <= 16'b0000000000000000;
+    else
+      n1906 <= n1902;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1913 <= 16'b0000000000000000;
+    else
+      n1913 <= n1909;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1918 <= 1'b0;
+    else
+      n1918 <= n1831;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1922 <= 1'b0;
+    else
+      n1922 <= n1918;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1926 <= 1'b0;
+    else
+      n1926 <= n1922;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1930 <= 1'b0;
+    else
+      n1930 <= n1926;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1935 <= 6'b000000;
+    else
+      n1935 <= n1931;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1939 <= 6'b000000;
+    else
+      n1939 <= n1935;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1943 <= 6'b000000;
+    else
+      n1943 <= n1939;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1947 <= 6'b000000;
+    else
+      n1947 <= n1943;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1952 <= 1'b0;
+    else
+      n1952 <= n1948;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1956 <= 1'b0;
+    else
+      n1956 <= n1952;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1960 <= 1'b0;
+    else
+      n1960 <= n1956;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1964 <= 1'b0;
+    else
+      n1964 <= n1960;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2064 == 1'b1)
+      n1970 <= 6'b000000;
+    else
+      n1970 <= n1967;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1977 <= 1'b0;
+    else
+      n1977 <= n1974;
+always @ (posedge clock_c)
+begin
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n1982 <= 1'b0;
+    else
+      n1982 <= n1930;
+end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1990 == 1'b1)
+      n1993m <= n1914;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1993ra <= n1970;
+	end
+assign n1993 = n1993m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n1994 == 1'b1)
+      n1997m <= n1914;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n1997ra <= n1970;
+  end
+assign n1997 = n1997m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n2001 <= 1'b0;
+    else
+      n2001 <= n1978;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2063 == 1'b1)
+      n2007 <= 6'b000000;
+    else
+      n2007 <= n2004;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n2014 <= 1'b0;
+    else
+      n2014 <= n2011;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n2027 == 1'b1)
+      n2030m <= n1914;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n2030ra <= n2007;
+  end
+assign n2030 = n2030m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    if (n2031 == 1'b1)
+      n2034m <= n1914;
+	end
+always @ (posedge clock_c)
+  if (n2061 == 1'b1) begin
+    n2034ra <= n2007;
+  end
+assign n2034 = n2034m;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n2038 <= 1'b0;
+    else
+      n2038 <= n2015;
+always @ (posedge clock_c)
+  if (n2061 == 1'b1)
+    if (n2062 == 1'b1)
+      n2047 <= 1'b0;
+    else
+      n2047 <= n2044;
+endmodule
+
+
diff --git a/BENCHMARK/counter120bitx5/counter120bitx5_yosys.blif b/BENCHMARK/counter120bitx5/counter120bitx5_yosys.blif
new file mode 100644
index 0000000..d294f65
--- /dev/null
+++ b/BENCHMARK/counter120bitx5/counter120bitx5_yosys.blif
@@ -0,0 +1,7055 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model counter120bitx5
+.inputs clk1 clk2 clk3 clk4 clk5 reset
+.outputs out1x(0) out1x(1) out1x(2) out1x(3) out1x(4) out1x(5) out1x(6) out1x(7) out1x(8) out1x(9) out1x(10) out1x(11) out1x(12) out1x(13) out2x(0) out2x(1) out2x(2) out2x(3) out2x(4) out2x(5) out2x(6) out2x(7) out2x(8) out2x(9) out2x(10) out2x(11) out2x(12) out2x(13) out3x(0) out3x(1) out3x(2) out3x(3) out3x(4) out3x(5) out3x(6) out3x(7) out3x(8) out3x(9) out3x(10) out3x(11) out3x(12) out3x(13) out4x(0) out4x(1) out4x(2) out4x(3) out4x(4) out4x(5) out4x(6) out4x(7) out4x(8) out4x(9) out4x(10) out4x(11) out4x(12) out4x(13) out5x(0) out5x(1) out5x(2) out5x(3) out5x(4) out5x(5) out5x(6) out5x(7) out5x(8) out5x(9) out5x(10) out5x(11) out5x(12) out5x(13)
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_1 a=$auto$hilomap.cc:39:hilomap_worker$10927
+.subckt logic_0 a=$auto$hilomap.cc:47:hilomap_worker$10925
+.subckt in_buff A=clk1 Q=$iopadmap$clk1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=clk2 Q=$iopadmap$clk2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=clk3 Q=$iopadmap$clk3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=clk4 Q=$iopadmap$clk4
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=clk5 Q=$iopadmap$clk5
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=cnt1(0) Q=out1x(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(1) Q=out1x(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(117) Q=out1x(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(118) Q=out1x(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(119) Q=out1x(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(120) Q=out1x(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(2) Q=out1x(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(3) Q=out1x(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(4) Q=out1x(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(5) Q=out1x(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(6) Q=out1x(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(7) Q=out1x(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(115) Q=out1x(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt1(116) Q=out1x(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(0) Q=out2x(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(1) Q=out2x(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(117) Q=out2x(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(118) Q=out2x(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(119) Q=out2x(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(120) Q=out2x(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(2) Q=out2x(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(3) Q=out2x(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(4) Q=out2x(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(5) Q=out2x(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(6) Q=out2x(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(7) Q=out2x(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(115) Q=out2x(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt2(116) Q=out2x(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(0) Q=out3x(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(1) Q=out3x(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(117) Q=out3x(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(118) Q=out3x(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(119) Q=out3x(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(120) Q=out3x(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(2) Q=out3x(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(3) Q=out3x(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(4) Q=out3x(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(5) Q=out3x(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(6) Q=out3x(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(7) Q=out3x(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(115) Q=out3x(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt3(116) Q=out3x(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(0) Q=out4x(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(1) Q=out4x(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(117) Q=out4x(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(118) Q=out4x(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(119) Q=out4x(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(120) Q=out4x(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(2) Q=out4x(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(3) Q=out4x(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(4) Q=out4x(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(5) Q=out4x(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(6) Q=out4x(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(7) Q=out4x(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(115) Q=out4x(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt4(116) Q=out4x(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(0) Q=out5x(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(1) Q=out5x(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(117) Q=out5x(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(118) Q=out5x(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(119) Q=out5x(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(120) Q=out5x(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(2) Q=out5x(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(3) Q=out5x(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(4) Q=out5x(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(5) Q=out5x(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(6) Q=out5x(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(7) Q=out5x(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(115) Q=out5x(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cnt5(116) Q=out5x(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=reset Q=$iopadmap$reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt ff CQZ=cnt1(120) D=cnt1_ff_CQZ_D(120) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(119) D=cnt1_ff_CQZ_D(119) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(110) D=cnt1_ff_CQZ_D(110) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(20) D=cnt1_ff_CQZ_D(20) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(19) D=cnt1_ff_CQZ_D(19) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(18) D=cnt1_ff_CQZ_D(18) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(17) D=cnt1_ff_CQZ_D(17) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(16) D=cnt1_ff_CQZ_D(16) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(15) D=cnt1_ff_CQZ_D(15) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(14) D=cnt1_ff_CQZ_D(14) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(13) D=cnt1_ff_CQZ_D(13) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(12) D=cnt1_ff_CQZ_D(12) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(11) D=cnt1_ff_CQZ_D(11) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(109) D=cnt1_ff_CQZ_D(109) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(10) D=cnt1_ff_CQZ_D(10) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(9) D=cnt1_ff_CQZ_D(9) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(8) D=cnt1_ff_CQZ_D(8) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(7) D=cnt1_ff_CQZ_D(7) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(6) D=cnt1_ff_CQZ_D(6) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(5) D=cnt1_ff_CQZ_D(5) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(4) D=cnt1_ff_CQZ_D(4) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(3) D=cnt1_ff_CQZ_D(3) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(2) D=cnt1_ff_CQZ_D(2) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(1) D=cnt1_ff_CQZ_D(1) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(108) D=cnt1_ff_CQZ_D(108) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(0) D=cnt1_ff_CQZ_D(0) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(107) D=cnt1_ff_CQZ_D(107) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(106) D=cnt1_ff_CQZ_D(106) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(105) D=cnt1_ff_CQZ_D(105) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(104) D=cnt1_ff_CQZ_D(104) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(103) D=cnt1_ff_CQZ_D(103) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(102) D=cnt1_ff_CQZ_D(102) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(101) D=cnt1_ff_CQZ_D(101) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(118) D=cnt1_ff_CQZ_D(118) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(100) D=cnt1_ff_CQZ_D(100) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(99) D=cnt1_ff_CQZ_D(99) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(98) D=cnt1_ff_CQZ_D(98) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(97) D=cnt1_ff_CQZ_D(97) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(96) D=cnt1_ff_CQZ_D(96) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(95) D=cnt1_ff_CQZ_D(95) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(94) D=cnt1_ff_CQZ_D(94) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(93) D=cnt1_ff_CQZ_D(93) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(92) D=cnt1_ff_CQZ_D(92) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(91) D=cnt1_ff_CQZ_D(91) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(117) D=cnt1_ff_CQZ_D(117) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(90) D=cnt1_ff_CQZ_D(90) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(89) D=cnt1_ff_CQZ_D(89) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(88) D=cnt1_ff_CQZ_D(88) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(87) D=cnt1_ff_CQZ_D(87) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(86) D=cnt1_ff_CQZ_D(86) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(85) D=cnt1_ff_CQZ_D(85) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(84) D=cnt1_ff_CQZ_D(84) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(83) D=cnt1_ff_CQZ_D(83) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(82) D=cnt1_ff_CQZ_D(82) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(81) D=cnt1_ff_CQZ_D(81) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(116) D=cnt1_ff_CQZ_D(116) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(80) D=cnt1_ff_CQZ_D(80) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(79) D=cnt1_ff_CQZ_D(79) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(78) D=cnt1_ff_CQZ_D(78) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(77) D=cnt1_ff_CQZ_D(77) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(76) D=cnt1_ff_CQZ_D(76) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(75) D=cnt1_ff_CQZ_D(75) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(74) D=cnt1_ff_CQZ_D(74) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(73) D=cnt1_ff_CQZ_D(73) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(72) D=cnt1_ff_CQZ_D(72) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(71) D=cnt1_ff_CQZ_D(71) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(115) D=cnt1_ff_CQZ_D(115) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(70) D=cnt1_ff_CQZ_D(70) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(69) D=cnt1_ff_CQZ_D(69) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(68) D=cnt1_ff_CQZ_D(68) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(67) D=cnt1_ff_CQZ_D(67) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(66) D=cnt1_ff_CQZ_D(66) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(65) D=cnt1_ff_CQZ_D(65) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(64) D=cnt1_ff_CQZ_D(64) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(63) D=cnt1_ff_CQZ_D(63) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(62) D=cnt1_ff_CQZ_D(62) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(61) D=cnt1_ff_CQZ_D(61) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(114) D=cnt1_ff_CQZ_D(114) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(60) D=cnt1_ff_CQZ_D(60) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(59) D=cnt1_ff_CQZ_D(59) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(58) D=cnt1_ff_CQZ_D(58) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(57) D=cnt1_ff_CQZ_D(57) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(56) D=cnt1_ff_CQZ_D(56) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(55) D=cnt1_ff_CQZ_D(55) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(54) D=cnt1_ff_CQZ_D(54) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(53) D=cnt1_ff_CQZ_D(53) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(52) D=cnt1_ff_CQZ_D(52) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(51) D=cnt1_ff_CQZ_D(51) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(113) D=cnt1_ff_CQZ_D(113) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(50) D=cnt1_ff_CQZ_D(50) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(49) D=cnt1_ff_CQZ_D(49) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(48) D=cnt1_ff_CQZ_D(48) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(47) D=cnt1_ff_CQZ_D(47) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(46) D=cnt1_ff_CQZ_D(46) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(45) D=cnt1_ff_CQZ_D(45) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(44) D=cnt1_ff_CQZ_D(44) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(43) D=cnt1_ff_CQZ_D(43) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(42) D=cnt1_ff_CQZ_D(42) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(41) D=cnt1_ff_CQZ_D(41) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(112) D=cnt1_ff_CQZ_D(112) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(40) D=cnt1_ff_CQZ_D(40) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(39) D=cnt1_ff_CQZ_D(39) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(38) D=cnt1_ff_CQZ_D(38) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(37) D=cnt1_ff_CQZ_D(37) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(36) D=cnt1_ff_CQZ_D(36) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(35) D=cnt1_ff_CQZ_D(35) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(34) D=cnt1_ff_CQZ_D(34) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(33) D=cnt1_ff_CQZ_D(33) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(32) D=cnt1_ff_CQZ_D(32) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(31) D=cnt1_ff_CQZ_D(31) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(111) D=cnt1_ff_CQZ_D(111) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(30) D=cnt1_ff_CQZ_D(30) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(29) D=cnt1_ff_CQZ_D(29) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(28) D=cnt1_ff_CQZ_D(28) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(27) D=cnt1_ff_CQZ_D(27) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(26) D=cnt1_ff_CQZ_D(26) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(25) D=cnt1_ff_CQZ_D(25) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(24) D=cnt1_ff_CQZ_D(24) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(23) D=cnt1_ff_CQZ_D(23) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(22) D=cnt1_ff_CQZ_D(22) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt1(21) D=cnt1_ff_CQZ_D(21) QCK=$iopadmap$clk1 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:31.1-43.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_I0 I1=cnt1(119) I2=$iopadmap$reset I3=cnt1(120) O=cnt1_ff_CQZ_D(120)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(119) I2=cnt1_ff_CQZ_D_LUT4_O_I0 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(119)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(110) I2=cnt1_ff_CQZ_D_LUT4_O_9_I0 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_101_I2 I1=cnt1(19) I2=$iopadmap$reset I3=cnt1(20) O=cnt1_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(19) I2=cnt1_ff_CQZ_D_LUT4_O_101_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_104_I2 I1=cnt1(16) I2=cnt1(17) I3=cnt1(18) O=cnt1_ff_CQZ_D_LUT4_O_101_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_102_I3 O=cnt1_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_104_I2 I1=cnt1(16) I2=cnt1(17) I3=cnt1(18) O=cnt1_ff_CQZ_D_LUT4_O_102_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_104_I2 I1=cnt1(16) I2=$iopadmap$reset I3=cnt1(17) O=cnt1_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(16) I2=cnt1_ff_CQZ_D_LUT4_O_104_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_107_I2 I1=cnt1(13) I2=cnt1(14) I3=cnt1(15) O=cnt1_ff_CQZ_D_LUT4_O_104_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_105_I3 O=cnt1_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_107_I2 I1=cnt1(13) I2=cnt1(14) I3=cnt1(15) O=cnt1_ff_CQZ_D_LUT4_O_105_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_107_I2 I1=cnt1(13) I2=$iopadmap$reset I3=cnt1(14) O=cnt1_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(13) I2=cnt1_ff_CQZ_D_LUT4_O_107_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_110_I2 I1=cnt1(10) I2=cnt1(11) I3=cnt1(12) O=cnt1_ff_CQZ_D_LUT4_O_107_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_108_I3 O=cnt1_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_110_I2 I1=cnt1(10) I2=cnt1(11) I3=cnt1(12) O=cnt1_ff_CQZ_D_LUT4_O_108_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_110_I2 I1=cnt1(10) I2=$iopadmap$reset I3=cnt1(11) O=cnt1_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_11_I3 O=cnt1_ff_CQZ_D(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(10) I2=cnt1_ff_CQZ_D_LUT4_O_110_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_113_I2 I1=cnt1(7) I2=cnt1(8) I3=cnt1(9) O=cnt1_ff_CQZ_D_LUT4_O_110_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_111_I3 O=cnt1_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_113_I2 I1=cnt1(7) I2=cnt1(8) I3=cnt1(9) O=cnt1_ff_CQZ_D_LUT4_O_111_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_113_I2 I1=cnt1(7) I2=$iopadmap$reset I3=cnt1(8) O=cnt1_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(7) I2=cnt1_ff_CQZ_D_LUT4_O_113_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_116_I2 I1=cnt1(4) I2=cnt1(5) I3=cnt1(6) O=cnt1_ff_CQZ_D_LUT4_O_113_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_114_I3 O=cnt1_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_116_I2 I1=cnt1(4) I2=cnt1(5) I3=cnt1(6) O=cnt1_ff_CQZ_D_LUT4_O_114_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_116_I2 I1=cnt1(4) I2=$iopadmap$reset I3=cnt1(5) O=cnt1_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(4) I2=cnt1_ff_CQZ_D_LUT4_O_116_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1(0) I1=cnt1(1) I2=cnt1(2) I3=cnt1(3) O=cnt1_ff_CQZ_D_LUT4_O_116_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_117_I3 O=cnt1_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1(0) I1=cnt1(1) I2=cnt1(2) I3=cnt1(3) O=cnt1_ff_CQZ_D_LUT4_O_117_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1(0) I1=cnt1(1) I2=$iopadmap$reset I3=cnt1(2) O=cnt1_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(1) I2=cnt1(0) I3=$iopadmap$reset O=cnt1_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_13_I2 I1=cnt1(107) I2=cnt1(108) I3=cnt1(109) O=cnt1_ff_CQZ_D_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_13_I2 I1=cnt1(107) I2=$iopadmap$reset I3=cnt1(108) O=cnt1_ff_CQZ_D(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt1(0) I3=$iopadmap$reset O=cnt1_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(107) I2=cnt1_ff_CQZ_D_LUT4_O_13_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_16_I2 I1=cnt1(104) I2=cnt1(105) I3=cnt1(106) O=cnt1_ff_CQZ_D_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_14_I3 O=cnt1_ff_CQZ_D(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_16_I2 I1=cnt1(104) I2=cnt1(105) I3=cnt1(106) O=cnt1_ff_CQZ_D_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_16_I2 I1=cnt1(104) I2=$iopadmap$reset I3=cnt1(105) O=cnt1_ff_CQZ_D(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(104) I2=cnt1_ff_CQZ_D_LUT4_O_16_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_19_I2 I1=cnt1(101) I2=cnt1(102) I3=cnt1(103) O=cnt1_ff_CQZ_D_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_17_I3 O=cnt1_ff_CQZ_D(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_19_I2 I1=cnt1(101) I2=cnt1(102) I3=cnt1(103) O=cnt1_ff_CQZ_D_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_19_I2 I1=cnt1(101) I2=$iopadmap$reset I3=cnt1(102) O=cnt1_ff_CQZ_D(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(101) I2=cnt1_ff_CQZ_D_LUT4_O_19_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_22_I2 I1=cnt1(98) I2=cnt1(99) I3=cnt1(100) O=cnt1_ff_CQZ_D_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_2_I3 O=cnt1_ff_CQZ_D(118)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_20_I3 O=cnt1_ff_CQZ_D(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_22_I2 I1=cnt1(98) I2=cnt1(99) I3=cnt1(100) O=cnt1_ff_CQZ_D_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_22_I2 I1=cnt1(98) I2=$iopadmap$reset I3=cnt1(99) O=cnt1_ff_CQZ_D(99)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(98) I2=cnt1_ff_CQZ_D_LUT4_O_22_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(98)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_25_I2 I1=cnt1(95) I2=cnt1(96) I3=cnt1(97) O=cnt1_ff_CQZ_D_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_23_I3 O=cnt1_ff_CQZ_D(97)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_25_I2 I1=cnt1(95) I2=cnt1(96) I3=cnt1(97) O=cnt1_ff_CQZ_D_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_25_I2 I1=cnt1(95) I2=$iopadmap$reset I3=cnt1(96) O=cnt1_ff_CQZ_D(96)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(95) I2=cnt1_ff_CQZ_D_LUT4_O_25_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(95)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_28_I2 I1=cnt1(92) I2=cnt1(93) I3=cnt1(94) O=cnt1_ff_CQZ_D_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_26_I3 O=cnt1_ff_CQZ_D(94)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_28_I2 I1=cnt1(92) I2=cnt1(93) I3=cnt1(94) O=cnt1_ff_CQZ_D_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_28_I2 I1=cnt1(92) I2=$iopadmap$reset I3=cnt1(93) O=cnt1_ff_CQZ_D(93)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(92) I2=cnt1_ff_CQZ_D_LUT4_O_28_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(92)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_31_I2 I1=cnt1(89) I2=cnt1(90) I3=cnt1(91) O=cnt1_ff_CQZ_D_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_29_I3 O=cnt1_ff_CQZ_D(91)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_31_I2 I1=cnt1(89) I2=cnt1(90) I3=cnt1(91) O=cnt1_ff_CQZ_D_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_4_I2 I1=cnt1(116) I2=cnt1(117) I3=cnt1(118) O=cnt1_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_4_I2 I1=cnt1(116) I2=$iopadmap$reset I3=cnt1(117) O=cnt1_ff_CQZ_D(117)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_31_I2 I1=cnt1(89) I2=$iopadmap$reset I3=cnt1(90) O=cnt1_ff_CQZ_D(90)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(89) I2=cnt1_ff_CQZ_D_LUT4_O_31_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(89)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_34_I2 I1=cnt1(86) I2=cnt1(87) I3=cnt1(88) O=cnt1_ff_CQZ_D_LUT4_O_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_32_I3 O=cnt1_ff_CQZ_D(88)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_34_I2 I1=cnt1(86) I2=cnt1(87) I3=cnt1(88) O=cnt1_ff_CQZ_D_LUT4_O_32_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_34_I2 I1=cnt1(86) I2=$iopadmap$reset I3=cnt1(87) O=cnt1_ff_CQZ_D(87)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(86) I2=cnt1_ff_CQZ_D_LUT4_O_34_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(86)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_37_I2 I1=cnt1(83) I2=cnt1(84) I3=cnt1(85) O=cnt1_ff_CQZ_D_LUT4_O_34_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_35_I3 O=cnt1_ff_CQZ_D(85)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_37_I2 I1=cnt1(83) I2=cnt1(84) I3=cnt1(85) O=cnt1_ff_CQZ_D_LUT4_O_35_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_37_I2 I1=cnt1(83) I2=$iopadmap$reset I3=cnt1(84) O=cnt1_ff_CQZ_D(84)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(83) I2=cnt1_ff_CQZ_D_LUT4_O_37_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(83)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_40_I2 I1=cnt1(80) I2=cnt1(81) I3=cnt1(82) O=cnt1_ff_CQZ_D_LUT4_O_37_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_38_I3 O=cnt1_ff_CQZ_D(82)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_40_I2 I1=cnt1(80) I2=cnt1(81) I3=cnt1(82) O=cnt1_ff_CQZ_D_LUT4_O_38_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_40_I2 I1=cnt1(80) I2=$iopadmap$reset I3=cnt1(81) O=cnt1_ff_CQZ_D(81)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(116) I2=cnt1_ff_CQZ_D_LUT4_O_4_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(116)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(80) I2=cnt1_ff_CQZ_D_LUT4_O_40_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_42_I2 I1=cnt1(78) I2=$iopadmap$reset I3=cnt1(79) O=cnt1_ff_CQZ_D(79)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(78) I2=cnt1_ff_CQZ_D_LUT4_O_42_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(78)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(79) I2=cnt1(78) I3=cnt1_ff_CQZ_D_LUT4_O_42_I2 O=cnt1_ff_CQZ_D_LUT4_O_40_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_45_I2 I1=cnt1(75) I2=cnt1(76) I3=cnt1(77) O=cnt1_ff_CQZ_D_LUT4_O_42_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_43_I3 O=cnt1_ff_CQZ_D(77)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_45_I2 I1=cnt1(75) I2=cnt1(76) I3=cnt1(77) O=cnt1_ff_CQZ_D_LUT4_O_43_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_45_I2 I1=cnt1(75) I2=$iopadmap$reset I3=cnt1(76) O=cnt1_ff_CQZ_D(76)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(75) I2=cnt1_ff_CQZ_D_LUT4_O_45_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(75)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_48_I2 I1=cnt1(72) I2=cnt1(73) I3=cnt1(74) O=cnt1_ff_CQZ_D_LUT4_O_45_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_46_I3 O=cnt1_ff_CQZ_D(74)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_48_I2 I1=cnt1(72) I2=cnt1(73) I3=cnt1(74) O=cnt1_ff_CQZ_D_LUT4_O_46_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_48_I2 I1=cnt1(72) I2=$iopadmap$reset I3=cnt1(73) O=cnt1_ff_CQZ_D(73)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(72) I2=cnt1_ff_CQZ_D_LUT4_O_48_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(72)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_53_I2 I1=cnt1_ff_CQZ_D_LUT4_O_49_I1 I2=$iopadmap$reset I3=cnt1(71) O=cnt1_ff_CQZ_D(71)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(71) I2=cnt1_ff_CQZ_D_LUT4_O_49_I1 I3=cnt1_ff_CQZ_D_LUT4_O_53_I2 O=cnt1_ff_CQZ_D_LUT4_O_48_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1(67) I1=cnt1(68) I2=cnt1(69) I3=cnt1(70) O=cnt1_ff_CQZ_D_LUT4_O_49_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_7_I2 I1=cnt1(113) I2=cnt1(114) I3=cnt1(115) O=cnt1_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_5_I3 O=cnt1_ff_CQZ_D(115)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_51_I2 I1=cnt1(69) I2=$iopadmap$reset I3=cnt1(70) O=cnt1_ff_CQZ_D(70)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(69) I2=cnt1_ff_CQZ_D_LUT4_O_51_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(69)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt1(68) I3=cnt1_ff_CQZ_D_LUT4_O_52_I2 O=cnt1_ff_CQZ_D_LUT4_O_51_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(68) I2=cnt1_ff_CQZ_D_LUT4_O_52_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(68)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt1(67) I3=cnt1_ff_CQZ_D_LUT4_O_53_I2 O=cnt1_ff_CQZ_D_LUT4_O_52_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(67) I2=cnt1_ff_CQZ_D_LUT4_O_53_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(67)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_55_I2 I1=cnt1(65) I2=$iopadmap$reset I3=cnt1(66) O=cnt1_ff_CQZ_D(66)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(65) I2=cnt1_ff_CQZ_D_LUT4_O_55_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(65)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(64) I2=cnt1(63) I3=cnt1_ff_CQZ_D_LUT4_O_57_I2 O=cnt1_ff_CQZ_D_LUT4_O_55_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_57_I2 I1=cnt1(63) I2=$iopadmap$reset I3=cnt1(64) O=cnt1_ff_CQZ_D(64)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(63) I2=cnt1_ff_CQZ_D_LUT4_O_57_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(63)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(62) I2=cnt1(61) I3=cnt1_ff_CQZ_D_LUT4_O_58_I0 O=cnt1_ff_CQZ_D_LUT4_O_57_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_58_I0 I1=cnt1(61) I2=$iopadmap$reset I3=cnt1(62) O=cnt1_ff_CQZ_D(62)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_58_I0 I1=cnt1_ff_CQZ_D_LUT4_O_58_I0_LUT4_I0_I1 I2=cnt1(61) I3=cnt1(62) O=cnt1_ff_CQZ_D_LUT4_O_53_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1(63) I1=cnt1(64) I2=cnt1(65) I3=cnt1(66) O=cnt1_ff_CQZ_D_LUT4_O_58_I0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_61_I0 I1=cnt1(58) I2=cnt1(59) I3=cnt1(60) O=cnt1_ff_CQZ_D_LUT4_O_58_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_60_I2 I1=cnt1(60) I2=$iopadmap$reset I3=cnt1(61) O=cnt1_ff_CQZ_D(61)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_7_I2 I1=cnt1(113) I2=cnt1(114) I3=cnt1(115) O=cnt1_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_7_I2 I1=cnt1(113) I2=$iopadmap$reset I3=cnt1(114) O=cnt1_ff_CQZ_D(114)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(60) I2=cnt1_ff_CQZ_D_LUT4_O_60_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(60)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(59) I2=cnt1(58) I3=cnt1_ff_CQZ_D_LUT4_O_61_I0 O=cnt1_ff_CQZ_D_LUT4_O_60_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_61_I0 I1=cnt1(58) I2=$iopadmap$reset I3=cnt1(59) O=cnt1_ff_CQZ_D(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_64_I0 I1=cnt1(55) I2=cnt1(56) I3=cnt1(57) O=cnt1_ff_CQZ_D_LUT4_O_61_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_63_I2 I1=cnt1(57) I2=$iopadmap$reset I3=cnt1(58) O=cnt1_ff_CQZ_D(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(57) I2=cnt1_ff_CQZ_D_LUT4_O_63_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(56) I2=cnt1(55) I3=cnt1_ff_CQZ_D_LUT4_O_64_I0 O=cnt1_ff_CQZ_D_LUT4_O_63_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_64_I0 I1=cnt1(55) I2=$iopadmap$reset I3=cnt1(56) O=cnt1_ff_CQZ_D(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_67_I0 I1=cnt1(52) I2=cnt1(53) I3=cnt1(54) O=cnt1_ff_CQZ_D_LUT4_O_64_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_66_I2 I1=cnt1(54) I2=$iopadmap$reset I3=cnt1(55) O=cnt1_ff_CQZ_D(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(54) I2=cnt1_ff_CQZ_D_LUT4_O_66_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(53) I2=cnt1(52) I3=cnt1_ff_CQZ_D_LUT4_O_67_I0 O=cnt1_ff_CQZ_D_LUT4_O_66_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_67_I0 I1=cnt1(52) I2=$iopadmap$reset I3=cnt1(53) O=cnt1_ff_CQZ_D(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_70_I0 I1=cnt1(49) I2=cnt1(50) I3=cnt1(51) O=cnt1_ff_CQZ_D_LUT4_O_67_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_69_I2 I1=cnt1(51) I2=$iopadmap$reset I3=cnt1(52) O=cnt1_ff_CQZ_D(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(51) I2=cnt1_ff_CQZ_D_LUT4_O_69_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(50) I2=cnt1(49) I3=cnt1_ff_CQZ_D_LUT4_O_70_I0 O=cnt1_ff_CQZ_D_LUT4_O_69_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(113) I2=cnt1_ff_CQZ_D_LUT4_O_7_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(113)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_70_I0 I1=cnt1(49) I2=$iopadmap$reset I3=cnt1(50) O=cnt1_ff_CQZ_D(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_74_I2 I1=cnt1(46) I2=cnt1(47) I3=cnt1(48) O=cnt1_ff_CQZ_D_LUT4_O_70_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_72_I2 I1=cnt1(48) I2=$iopadmap$reset I3=cnt1(49) O=cnt1_ff_CQZ_D(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(48) I2=cnt1_ff_CQZ_D_LUT4_O_72_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(47) I2=cnt1(46) I3=cnt1_ff_CQZ_D_LUT4_O_74_I2 O=cnt1_ff_CQZ_D_LUT4_O_72_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_74_I2 I1=cnt1(46) I2=$iopadmap$reset I3=cnt1(47) O=cnt1_ff_CQZ_D(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(46) I2=cnt1_ff_CQZ_D_LUT4_O_74_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_77_I2 I1=cnt1(43) I2=cnt1(44) I3=cnt1(45) O=cnt1_ff_CQZ_D_LUT4_O_74_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_75_I3 O=cnt1_ff_CQZ_D(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_77_I2 I1=cnt1(43) I2=cnt1(44) I3=cnt1(45) O=cnt1_ff_CQZ_D_LUT4_O_75_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_77_I2 I1=cnt1(43) I2=$iopadmap$reset I3=cnt1(44) O=cnt1_ff_CQZ_D(44)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(43) I2=cnt1_ff_CQZ_D_LUT4_O_77_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_80_I2 I1=cnt1(40) I2=cnt1(41) I3=cnt1(42) O=cnt1_ff_CQZ_D_LUT4_O_77_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_78_I3 O=cnt1_ff_CQZ_D(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_80_I2 I1=cnt1(40) I2=cnt1(41) I3=cnt1(42) O=cnt1_ff_CQZ_D_LUT4_O_78_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_80_I2 I1=cnt1(40) I2=$iopadmap$reset I3=cnt1(41) O=cnt1_ff_CQZ_D(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_9_I0 I1=cnt1(110) I2=cnt1(111) I3=cnt1(112) O=cnt1_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_8_I3 O=cnt1_ff_CQZ_D(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(40) I2=cnt1_ff_CQZ_D_LUT4_O_80_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_85_I2 I1=cnt1_ff_CQZ_D_LUT4_O_81_I1 I2=$iopadmap$reset I3=cnt1(39) O=cnt1_ff_CQZ_D(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_89_I2 I1=cnt1_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2 I2=cnt1_ff_CQZ_D_LUT4_O_81_I1 I3=cnt1(39) O=cnt1_ff_CQZ_D_LUT4_O_80_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1(35) I1=cnt1(36) I2=cnt1(37) I3=cnt1(38) O=cnt1_ff_CQZ_D_LUT4_O_81_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_83_I2 I1=cnt1(37) I2=$iopadmap$reset I3=cnt1(38) O=cnt1_ff_CQZ_D(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(37) I2=cnt1_ff_CQZ_D_LUT4_O_83_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(36) I2=cnt1(35) I3=cnt1_ff_CQZ_D_LUT4_O_85_I2 O=cnt1_ff_CQZ_D_LUT4_O_83_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_85_I2 I1=cnt1(35) I2=$iopadmap$reset I3=cnt1(36) O=cnt1_ff_CQZ_D(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(35) I2=cnt1_ff_CQZ_D_LUT4_O_85_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt1_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2 I3=cnt1_ff_CQZ_D_LUT4_O_89_I2 O=cnt1_ff_CQZ_D_LUT4_O_85_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cnt1(31) I1=cnt1(32) I2=cnt1(33) I3=cnt1(34) O=cnt1_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_87_I2 I1=cnt1(33) I2=$iopadmap$reset I3=cnt1(34) O=cnt1_ff_CQZ_D(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(33) I2=cnt1_ff_CQZ_D_LUT4_O_87_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(32) I2=cnt1(31) I3=cnt1_ff_CQZ_D_LUT4_O_89_I2 O=cnt1_ff_CQZ_D_LUT4_O_87_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_89_I2 I1=cnt1(31) I2=$iopadmap$reset I3=cnt1(32) O=cnt1_ff_CQZ_D(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(31) I2=cnt1_ff_CQZ_D_LUT4_O_89_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_92_I2 I1=cnt1(28) I2=cnt1(29) I3=cnt1(30) O=cnt1_ff_CQZ_D_LUT4_O_89_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_9_I0 I1=cnt1(110) I2=cnt1(111) I3=cnt1(112) O=cnt1_ff_CQZ_D_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_9_I0 I1=cnt1(110) I2=$iopadmap$reset I3=cnt1(111) O=cnt1_ff_CQZ_D(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_90_I3 O=cnt1_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_92_I2 I1=cnt1(28) I2=cnt1(29) I3=cnt1(30) O=cnt1_ff_CQZ_D_LUT4_O_90_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_92_I2 I1=cnt1(28) I2=$iopadmap$reset I3=cnt1(29) O=cnt1_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(28) I2=cnt1_ff_CQZ_D_LUT4_O_92_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_95_I2 I1=cnt1(25) I2=cnt1(26) I3=cnt1(27) O=cnt1_ff_CQZ_D_LUT4_O_92_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_93_I3 O=cnt1_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_95_I2 I1=cnt1(25) I2=cnt1(26) I3=cnt1(27) O=cnt1_ff_CQZ_D_LUT4_O_93_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_95_I2 I1=cnt1(25) I2=$iopadmap$reset I3=cnt1(26) O=cnt1_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(25) I2=cnt1_ff_CQZ_D_LUT4_O_95_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_98_I2 I1=cnt1(22) I2=cnt1(23) I3=cnt1(24) O=cnt1_ff_CQZ_D_LUT4_O_95_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_96_I3 O=cnt1_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_98_I2 I1=cnt1(22) I2=cnt1(23) I3=cnt1(24) O=cnt1_ff_CQZ_D_LUT4_O_96_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_98_I2 I1=cnt1(22) I2=$iopadmap$reset I3=cnt1(23) O=cnt1_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt1(22) I2=cnt1_ff_CQZ_D_LUT4_O_98_I2 I3=$iopadmap$reset O=cnt1_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_101_I2 I1=cnt1(19) I2=cnt1(20) I3=cnt1(21) O=cnt1_ff_CQZ_D_LUT4_O_98_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt1_ff_CQZ_D_LUT4_O_99_I3 O=cnt1_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_101_I2 I1=cnt1(19) I2=cnt1(20) I3=cnt1(21) O=cnt1_ff_CQZ_D_LUT4_O_99_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_13_I2 I1=cnt1(107) I2=cnt1(108) I3=cnt1(109) O=cnt1_ff_CQZ_D_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt1_ff_CQZ_D_LUT4_O_4_I2 I1=cnt1(116) I2=cnt1(117) I3=cnt1(118) O=cnt1_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cnt2(120) D=cnt2_ff_CQZ_D(120) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(119) D=cnt2_ff_CQZ_D(119) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(110) D=cnt2_ff_CQZ_D(110) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(20) D=cnt2_ff_CQZ_D(20) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(19) D=cnt2_ff_CQZ_D(19) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(18) D=cnt2_ff_CQZ_D(18) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(17) D=cnt2_ff_CQZ_D(17) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(16) D=cnt2_ff_CQZ_D(16) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(15) D=cnt2_ff_CQZ_D(15) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(14) D=cnt2_ff_CQZ_D(14) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(13) D=cnt2_ff_CQZ_D(13) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(12) D=cnt2_ff_CQZ_D(12) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(11) D=cnt2_ff_CQZ_D(11) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(109) D=cnt2_ff_CQZ_D(109) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(10) D=cnt2_ff_CQZ_D(10) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(9) D=cnt2_ff_CQZ_D(9) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(8) D=cnt2_ff_CQZ_D(8) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(7) D=cnt2_ff_CQZ_D(7) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(6) D=cnt2_ff_CQZ_D(6) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(5) D=cnt2_ff_CQZ_D(5) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(4) D=cnt2_ff_CQZ_D(4) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(3) D=cnt2_ff_CQZ_D(3) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(2) D=cnt2_ff_CQZ_D(2) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(1) D=cnt2_ff_CQZ_D(1) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(108) D=cnt2_ff_CQZ_D(108) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(0) D=cnt2_ff_CQZ_D(0) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(107) D=cnt2_ff_CQZ_D(107) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(106) D=cnt2_ff_CQZ_D(106) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(105) D=cnt2_ff_CQZ_D(105) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(104) D=cnt2_ff_CQZ_D(104) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(103) D=cnt2_ff_CQZ_D(103) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(102) D=cnt2_ff_CQZ_D(102) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(101) D=cnt2_ff_CQZ_D(101) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(118) D=cnt2_ff_CQZ_D(118) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(100) D=cnt2_ff_CQZ_D(100) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(99) D=cnt2_ff_CQZ_D(99) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(98) D=cnt2_ff_CQZ_D(98) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(97) D=cnt2_ff_CQZ_D(97) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(96) D=cnt2_ff_CQZ_D(96) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(95) D=cnt2_ff_CQZ_D(95) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(94) D=cnt2_ff_CQZ_D(94) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(93) D=cnt2_ff_CQZ_D(93) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(92) D=cnt2_ff_CQZ_D(92) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(91) D=cnt2_ff_CQZ_D(91) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(117) D=cnt2_ff_CQZ_D(117) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(90) D=cnt2_ff_CQZ_D(90) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(89) D=cnt2_ff_CQZ_D(89) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(88) D=cnt2_ff_CQZ_D(88) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(87) D=cnt2_ff_CQZ_D(87) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(86) D=cnt2_ff_CQZ_D(86) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(85) D=cnt2_ff_CQZ_D(85) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(84) D=cnt2_ff_CQZ_D(84) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(83) D=cnt2_ff_CQZ_D(83) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(82) D=cnt2_ff_CQZ_D(82) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(81) D=cnt2_ff_CQZ_D(81) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(116) D=cnt2_ff_CQZ_D(116) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(80) D=cnt2_ff_CQZ_D(80) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(79) D=cnt2_ff_CQZ_D(79) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(78) D=cnt2_ff_CQZ_D(78) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(77) D=cnt2_ff_CQZ_D(77) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(76) D=cnt2_ff_CQZ_D(76) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(75) D=cnt2_ff_CQZ_D(75) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(74) D=cnt2_ff_CQZ_D(74) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(73) D=cnt2_ff_CQZ_D(73) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(72) D=cnt2_ff_CQZ_D(72) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(71) D=cnt2_ff_CQZ_D(71) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(115) D=cnt2_ff_CQZ_D(115) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(70) D=cnt2_ff_CQZ_D(70) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(69) D=cnt2_ff_CQZ_D(69) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(68) D=cnt2_ff_CQZ_D(68) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(67) D=cnt2_ff_CQZ_D(67) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(66) D=cnt2_ff_CQZ_D(66) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(65) D=cnt2_ff_CQZ_D(65) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(64) D=cnt2_ff_CQZ_D(64) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(63) D=cnt2_ff_CQZ_D(63) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(62) D=cnt2_ff_CQZ_D(62) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(61) D=cnt2_ff_CQZ_D(61) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(114) D=cnt2_ff_CQZ_D(114) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(60) D=cnt2_ff_CQZ_D(60) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(59) D=cnt2_ff_CQZ_D(59) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(58) D=cnt2_ff_CQZ_D(58) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(57) D=cnt2_ff_CQZ_D(57) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(56) D=cnt2_ff_CQZ_D(56) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(55) D=cnt2_ff_CQZ_D(55) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(54) D=cnt2_ff_CQZ_D(54) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(53) D=cnt2_ff_CQZ_D(53) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(52) D=cnt2_ff_CQZ_D(52) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(51) D=cnt2_ff_CQZ_D(51) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(113) D=cnt2_ff_CQZ_D(113) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(50) D=cnt2_ff_CQZ_D(50) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(49) D=cnt2_ff_CQZ_D(49) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(48) D=cnt2_ff_CQZ_D(48) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(47) D=cnt2_ff_CQZ_D(47) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(46) D=cnt2_ff_CQZ_D(46) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(45) D=cnt2_ff_CQZ_D(45) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(44) D=cnt2_ff_CQZ_D(44) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(43) D=cnt2_ff_CQZ_D(43) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(42) D=cnt2_ff_CQZ_D(42) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(41) D=cnt2_ff_CQZ_D(41) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(112) D=cnt2_ff_CQZ_D(112) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(40) D=cnt2_ff_CQZ_D(40) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(39) D=cnt2_ff_CQZ_D(39) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(38) D=cnt2_ff_CQZ_D(38) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(37) D=cnt2_ff_CQZ_D(37) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(36) D=cnt2_ff_CQZ_D(36) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(35) D=cnt2_ff_CQZ_D(35) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(34) D=cnt2_ff_CQZ_D(34) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(33) D=cnt2_ff_CQZ_D(33) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(32) D=cnt2_ff_CQZ_D(32) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(31) D=cnt2_ff_CQZ_D(31) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(111) D=cnt2_ff_CQZ_D(111) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(30) D=cnt2_ff_CQZ_D(30) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(29) D=cnt2_ff_CQZ_D(29) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(28) D=cnt2_ff_CQZ_D(28) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(27) D=cnt2_ff_CQZ_D(27) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(26) D=cnt2_ff_CQZ_D(26) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(25) D=cnt2_ff_CQZ_D(25) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(24) D=cnt2_ff_CQZ_D(24) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(23) D=cnt2_ff_CQZ_D(23) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(22) D=cnt2_ff_CQZ_D(22) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt2(21) D=cnt2_ff_CQZ_D(21) QCK=$iopadmap$clk2 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:46.1-58.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_I0 I1=cnt2(119) I2=$iopadmap$reset I3=cnt2(120) O=cnt2_ff_CQZ_D(120)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(119) I2=cnt2_ff_CQZ_D_LUT4_O_I0 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(119)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(110) I2=cnt2_ff_CQZ_D_LUT4_O_9_I0 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_101_I2 I1=cnt2(19) I2=$iopadmap$reset I3=cnt2(20) O=cnt2_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(19) I2=cnt2_ff_CQZ_D_LUT4_O_101_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_104_I2 I1=cnt2(16) I2=cnt2(17) I3=cnt2(18) O=cnt2_ff_CQZ_D_LUT4_O_101_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_102_I3 O=cnt2_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_104_I2 I1=cnt2(16) I2=cnt2(17) I3=cnt2(18) O=cnt2_ff_CQZ_D_LUT4_O_102_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_104_I2 I1=cnt2(16) I2=$iopadmap$reset I3=cnt2(17) O=cnt2_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(16) I2=cnt2_ff_CQZ_D_LUT4_O_104_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_107_I2 I1=cnt2(13) I2=cnt2(14) I3=cnt2(15) O=cnt2_ff_CQZ_D_LUT4_O_104_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_105_I3 O=cnt2_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_107_I2 I1=cnt2(13) I2=cnt2(14) I3=cnt2(15) O=cnt2_ff_CQZ_D_LUT4_O_105_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_107_I2 I1=cnt2(13) I2=$iopadmap$reset I3=cnt2(14) O=cnt2_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(13) I2=cnt2_ff_CQZ_D_LUT4_O_107_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_110_I2 I1=cnt2(10) I2=cnt2(11) I3=cnt2(12) O=cnt2_ff_CQZ_D_LUT4_O_107_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_108_I3 O=cnt2_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_110_I2 I1=cnt2(10) I2=cnt2(11) I3=cnt2(12) O=cnt2_ff_CQZ_D_LUT4_O_108_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_110_I2 I1=cnt2(10) I2=$iopadmap$reset I3=cnt2(11) O=cnt2_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_11_I3 O=cnt2_ff_CQZ_D(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(10) I2=cnt2_ff_CQZ_D_LUT4_O_110_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_113_I2 I1=cnt2(7) I2=cnt2(8) I3=cnt2(9) O=cnt2_ff_CQZ_D_LUT4_O_110_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_111_I3 O=cnt2_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_113_I2 I1=cnt2(7) I2=cnt2(8) I3=cnt2(9) O=cnt2_ff_CQZ_D_LUT4_O_111_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_113_I2 I1=cnt2(7) I2=$iopadmap$reset I3=cnt2(8) O=cnt2_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(7) I2=cnt2_ff_CQZ_D_LUT4_O_113_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_116_I2 I1=cnt2(4) I2=cnt2(5) I3=cnt2(6) O=cnt2_ff_CQZ_D_LUT4_O_113_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_114_I3 O=cnt2_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_116_I2 I1=cnt2(4) I2=cnt2(5) I3=cnt2(6) O=cnt2_ff_CQZ_D_LUT4_O_114_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_116_I2 I1=cnt2(4) I2=$iopadmap$reset I3=cnt2(5) O=cnt2_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(4) I2=cnt2_ff_CQZ_D_LUT4_O_116_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2(0) I1=cnt2(1) I2=cnt2(2) I3=cnt2(3) O=cnt2_ff_CQZ_D_LUT4_O_116_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_117_I3 O=cnt2_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2(0) I1=cnt2(1) I2=cnt2(2) I3=cnt2(3) O=cnt2_ff_CQZ_D_LUT4_O_117_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2(0) I1=cnt2(1) I2=$iopadmap$reset I3=cnt2(2) O=cnt2_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(1) I2=cnt2(0) I3=$iopadmap$reset O=cnt2_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_13_I2 I1=cnt2(107) I2=cnt2(108) I3=cnt2(109) O=cnt2_ff_CQZ_D_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_13_I2 I1=cnt2(107) I2=$iopadmap$reset I3=cnt2(108) O=cnt2_ff_CQZ_D(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt2(0) I3=$iopadmap$reset O=cnt2_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(107) I2=cnt2_ff_CQZ_D_LUT4_O_13_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_16_I2 I1=cnt2(104) I2=cnt2(105) I3=cnt2(106) O=cnt2_ff_CQZ_D_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_14_I3 O=cnt2_ff_CQZ_D(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_16_I2 I1=cnt2(104) I2=cnt2(105) I3=cnt2(106) O=cnt2_ff_CQZ_D_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_16_I2 I1=cnt2(104) I2=$iopadmap$reset I3=cnt2(105) O=cnt2_ff_CQZ_D(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(104) I2=cnt2_ff_CQZ_D_LUT4_O_16_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_19_I2 I1=cnt2(101) I2=cnt2(102) I3=cnt2(103) O=cnt2_ff_CQZ_D_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_17_I3 O=cnt2_ff_CQZ_D(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_19_I2 I1=cnt2(101) I2=cnt2(102) I3=cnt2(103) O=cnt2_ff_CQZ_D_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_19_I2 I1=cnt2(101) I2=$iopadmap$reset I3=cnt2(102) O=cnt2_ff_CQZ_D(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(101) I2=cnt2_ff_CQZ_D_LUT4_O_19_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_22_I2 I1=cnt2(98) I2=cnt2(99) I3=cnt2(100) O=cnt2_ff_CQZ_D_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_2_I3 O=cnt2_ff_CQZ_D(118)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_20_I3 O=cnt2_ff_CQZ_D(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_22_I2 I1=cnt2(98) I2=cnt2(99) I3=cnt2(100) O=cnt2_ff_CQZ_D_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_22_I2 I1=cnt2(98) I2=$iopadmap$reset I3=cnt2(99) O=cnt2_ff_CQZ_D(99)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(98) I2=cnt2_ff_CQZ_D_LUT4_O_22_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(98)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_25_I2 I1=cnt2(95) I2=cnt2(96) I3=cnt2(97) O=cnt2_ff_CQZ_D_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_23_I3 O=cnt2_ff_CQZ_D(97)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_25_I2 I1=cnt2(95) I2=cnt2(96) I3=cnt2(97) O=cnt2_ff_CQZ_D_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_25_I2 I1=cnt2(95) I2=$iopadmap$reset I3=cnt2(96) O=cnt2_ff_CQZ_D(96)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(95) I2=cnt2_ff_CQZ_D_LUT4_O_25_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(95)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_28_I2 I1=cnt2(92) I2=cnt2(93) I3=cnt2(94) O=cnt2_ff_CQZ_D_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_26_I3 O=cnt2_ff_CQZ_D(94)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_28_I2 I1=cnt2(92) I2=cnt2(93) I3=cnt2(94) O=cnt2_ff_CQZ_D_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_28_I2 I1=cnt2(92) I2=$iopadmap$reset I3=cnt2(93) O=cnt2_ff_CQZ_D(93)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(92) I2=cnt2_ff_CQZ_D_LUT4_O_28_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(92)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_31_I2 I1=cnt2(89) I2=cnt2(90) I3=cnt2(91) O=cnt2_ff_CQZ_D_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_29_I3 O=cnt2_ff_CQZ_D(91)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_31_I2 I1=cnt2(89) I2=cnt2(90) I3=cnt2(91) O=cnt2_ff_CQZ_D_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_4_I2 I1=cnt2(116) I2=cnt2(117) I3=cnt2(118) O=cnt2_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_4_I2 I1=cnt2(116) I2=$iopadmap$reset I3=cnt2(117) O=cnt2_ff_CQZ_D(117)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_31_I2 I1=cnt2(89) I2=$iopadmap$reset I3=cnt2(90) O=cnt2_ff_CQZ_D(90)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(89) I2=cnt2_ff_CQZ_D_LUT4_O_31_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(89)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_34_I2 I1=cnt2(86) I2=cnt2(87) I3=cnt2(88) O=cnt2_ff_CQZ_D_LUT4_O_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_32_I3 O=cnt2_ff_CQZ_D(88)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_34_I2 I1=cnt2(86) I2=cnt2(87) I3=cnt2(88) O=cnt2_ff_CQZ_D_LUT4_O_32_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_34_I2 I1=cnt2(86) I2=$iopadmap$reset I3=cnt2(87) O=cnt2_ff_CQZ_D(87)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(86) I2=cnt2_ff_CQZ_D_LUT4_O_34_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(86)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_37_I2 I1=cnt2(83) I2=cnt2(84) I3=cnt2(85) O=cnt2_ff_CQZ_D_LUT4_O_34_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_35_I3 O=cnt2_ff_CQZ_D(85)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_37_I2 I1=cnt2(83) I2=cnt2(84) I3=cnt2(85) O=cnt2_ff_CQZ_D_LUT4_O_35_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_37_I2 I1=cnt2(83) I2=$iopadmap$reset I3=cnt2(84) O=cnt2_ff_CQZ_D(84)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(83) I2=cnt2_ff_CQZ_D_LUT4_O_37_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(83)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_40_I2 I1=cnt2(80) I2=cnt2(81) I3=cnt2(82) O=cnt2_ff_CQZ_D_LUT4_O_37_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_38_I3 O=cnt2_ff_CQZ_D(82)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_40_I2 I1=cnt2(80) I2=cnt2(81) I3=cnt2(82) O=cnt2_ff_CQZ_D_LUT4_O_38_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_40_I2 I1=cnt2(80) I2=$iopadmap$reset I3=cnt2(81) O=cnt2_ff_CQZ_D(81)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(116) I2=cnt2_ff_CQZ_D_LUT4_O_4_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(116)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(80) I2=cnt2_ff_CQZ_D_LUT4_O_40_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_42_I2 I1=cnt2(78) I2=$iopadmap$reset I3=cnt2(79) O=cnt2_ff_CQZ_D(79)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(78) I2=cnt2_ff_CQZ_D_LUT4_O_42_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(78)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(79) I2=cnt2(78) I3=cnt2_ff_CQZ_D_LUT4_O_42_I2 O=cnt2_ff_CQZ_D_LUT4_O_40_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_45_I2 I1=cnt2(75) I2=cnt2(76) I3=cnt2(77) O=cnt2_ff_CQZ_D_LUT4_O_42_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_43_I3 O=cnt2_ff_CQZ_D(77)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_45_I2 I1=cnt2(75) I2=cnt2(76) I3=cnt2(77) O=cnt2_ff_CQZ_D_LUT4_O_43_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_45_I2 I1=cnt2(75) I2=$iopadmap$reset I3=cnt2(76) O=cnt2_ff_CQZ_D(76)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(75) I2=cnt2_ff_CQZ_D_LUT4_O_45_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(75)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_48_I2 I1=cnt2(72) I2=cnt2(73) I3=cnt2(74) O=cnt2_ff_CQZ_D_LUT4_O_45_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_46_I3 O=cnt2_ff_CQZ_D(74)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_48_I2 I1=cnt2(72) I2=cnt2(73) I3=cnt2(74) O=cnt2_ff_CQZ_D_LUT4_O_46_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_48_I2 I1=cnt2(72) I2=$iopadmap$reset I3=cnt2(73) O=cnt2_ff_CQZ_D(73)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(72) I2=cnt2_ff_CQZ_D_LUT4_O_48_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(72)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_53_I2 I1=cnt2_ff_CQZ_D_LUT4_O_49_I1 I2=$iopadmap$reset I3=cnt2(71) O=cnt2_ff_CQZ_D(71)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(71) I2=cnt2_ff_CQZ_D_LUT4_O_49_I1 I3=cnt2_ff_CQZ_D_LUT4_O_53_I2 O=cnt2_ff_CQZ_D_LUT4_O_48_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2(67) I1=cnt2(68) I2=cnt2(69) I3=cnt2(70) O=cnt2_ff_CQZ_D_LUT4_O_49_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_7_I2 I1=cnt2(113) I2=cnt2(114) I3=cnt2(115) O=cnt2_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_5_I3 O=cnt2_ff_CQZ_D(115)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_51_I2 I1=cnt2(69) I2=$iopadmap$reset I3=cnt2(70) O=cnt2_ff_CQZ_D(70)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(69) I2=cnt2_ff_CQZ_D_LUT4_O_51_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(69)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt2(68) I3=cnt2_ff_CQZ_D_LUT4_O_52_I2 O=cnt2_ff_CQZ_D_LUT4_O_51_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(68) I2=cnt2_ff_CQZ_D_LUT4_O_52_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(68)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt2(67) I3=cnt2_ff_CQZ_D_LUT4_O_53_I2 O=cnt2_ff_CQZ_D_LUT4_O_52_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(67) I2=cnt2_ff_CQZ_D_LUT4_O_53_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(67)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_55_I2 I1=cnt2(65) I2=$iopadmap$reset I3=cnt2(66) O=cnt2_ff_CQZ_D(66)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(65) I2=cnt2_ff_CQZ_D_LUT4_O_55_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(65)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(64) I2=cnt2(63) I3=cnt2_ff_CQZ_D_LUT4_O_57_I2 O=cnt2_ff_CQZ_D_LUT4_O_55_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_57_I2 I1=cnt2(63) I2=$iopadmap$reset I3=cnt2(64) O=cnt2_ff_CQZ_D(64)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(63) I2=cnt2_ff_CQZ_D_LUT4_O_57_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(63)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(62) I2=cnt2(61) I3=cnt2_ff_CQZ_D_LUT4_O_58_I0 O=cnt2_ff_CQZ_D_LUT4_O_57_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_58_I0 I1=cnt2(61) I2=$iopadmap$reset I3=cnt2(62) O=cnt2_ff_CQZ_D(62)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_58_I0 I1=cnt2_ff_CQZ_D_LUT4_O_58_I0_LUT4_I0_I1 I2=cnt2(61) I3=cnt2(62) O=cnt2_ff_CQZ_D_LUT4_O_53_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2(63) I1=cnt2(64) I2=cnt2(65) I3=cnt2(66) O=cnt2_ff_CQZ_D_LUT4_O_58_I0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_61_I0 I1=cnt2(58) I2=cnt2(59) I3=cnt2(60) O=cnt2_ff_CQZ_D_LUT4_O_58_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_60_I2 I1=cnt2(60) I2=$iopadmap$reset I3=cnt2(61) O=cnt2_ff_CQZ_D(61)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_7_I2 I1=cnt2(113) I2=cnt2(114) I3=cnt2(115) O=cnt2_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_7_I2 I1=cnt2(113) I2=$iopadmap$reset I3=cnt2(114) O=cnt2_ff_CQZ_D(114)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(60) I2=cnt2_ff_CQZ_D_LUT4_O_60_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(60)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(59) I2=cnt2(58) I3=cnt2_ff_CQZ_D_LUT4_O_61_I0 O=cnt2_ff_CQZ_D_LUT4_O_60_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_61_I0 I1=cnt2(58) I2=$iopadmap$reset I3=cnt2(59) O=cnt2_ff_CQZ_D(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_64_I0 I1=cnt2(55) I2=cnt2(56) I3=cnt2(57) O=cnt2_ff_CQZ_D_LUT4_O_61_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_63_I2 I1=cnt2(57) I2=$iopadmap$reset I3=cnt2(58) O=cnt2_ff_CQZ_D(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(57) I2=cnt2_ff_CQZ_D_LUT4_O_63_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(56) I2=cnt2(55) I3=cnt2_ff_CQZ_D_LUT4_O_64_I0 O=cnt2_ff_CQZ_D_LUT4_O_63_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_64_I0 I1=cnt2(55) I2=$iopadmap$reset I3=cnt2(56) O=cnt2_ff_CQZ_D(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_67_I0 I1=cnt2(52) I2=cnt2(53) I3=cnt2(54) O=cnt2_ff_CQZ_D_LUT4_O_64_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_66_I2 I1=cnt2(54) I2=$iopadmap$reset I3=cnt2(55) O=cnt2_ff_CQZ_D(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(54) I2=cnt2_ff_CQZ_D_LUT4_O_66_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(53) I2=cnt2(52) I3=cnt2_ff_CQZ_D_LUT4_O_67_I0 O=cnt2_ff_CQZ_D_LUT4_O_66_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_67_I0 I1=cnt2(52) I2=$iopadmap$reset I3=cnt2(53) O=cnt2_ff_CQZ_D(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_70_I0 I1=cnt2(49) I2=cnt2(50) I3=cnt2(51) O=cnt2_ff_CQZ_D_LUT4_O_67_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_69_I2 I1=cnt2(51) I2=$iopadmap$reset I3=cnt2(52) O=cnt2_ff_CQZ_D(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(51) I2=cnt2_ff_CQZ_D_LUT4_O_69_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(50) I2=cnt2(49) I3=cnt2_ff_CQZ_D_LUT4_O_70_I0 O=cnt2_ff_CQZ_D_LUT4_O_69_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(113) I2=cnt2_ff_CQZ_D_LUT4_O_7_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(113)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_70_I0 I1=cnt2(49) I2=$iopadmap$reset I3=cnt2(50) O=cnt2_ff_CQZ_D(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_74_I2 I1=cnt2(46) I2=cnt2(47) I3=cnt2(48) O=cnt2_ff_CQZ_D_LUT4_O_70_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_72_I2 I1=cnt2(48) I2=$iopadmap$reset I3=cnt2(49) O=cnt2_ff_CQZ_D(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(48) I2=cnt2_ff_CQZ_D_LUT4_O_72_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(47) I2=cnt2(46) I3=cnt2_ff_CQZ_D_LUT4_O_74_I2 O=cnt2_ff_CQZ_D_LUT4_O_72_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_74_I2 I1=cnt2(46) I2=$iopadmap$reset I3=cnt2(47) O=cnt2_ff_CQZ_D(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(46) I2=cnt2_ff_CQZ_D_LUT4_O_74_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_77_I2 I1=cnt2(43) I2=cnt2(44) I3=cnt2(45) O=cnt2_ff_CQZ_D_LUT4_O_74_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_75_I3 O=cnt2_ff_CQZ_D(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_77_I2 I1=cnt2(43) I2=cnt2(44) I3=cnt2(45) O=cnt2_ff_CQZ_D_LUT4_O_75_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_77_I2 I1=cnt2(43) I2=$iopadmap$reset I3=cnt2(44) O=cnt2_ff_CQZ_D(44)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(43) I2=cnt2_ff_CQZ_D_LUT4_O_77_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_80_I2 I1=cnt2(40) I2=cnt2(41) I3=cnt2(42) O=cnt2_ff_CQZ_D_LUT4_O_77_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_78_I3 O=cnt2_ff_CQZ_D(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_80_I2 I1=cnt2(40) I2=cnt2(41) I3=cnt2(42) O=cnt2_ff_CQZ_D_LUT4_O_78_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_80_I2 I1=cnt2(40) I2=$iopadmap$reset I3=cnt2(41) O=cnt2_ff_CQZ_D(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_9_I0 I1=cnt2(110) I2=cnt2(111) I3=cnt2(112) O=cnt2_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_8_I3 O=cnt2_ff_CQZ_D(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(40) I2=cnt2_ff_CQZ_D_LUT4_O_80_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_85_I2 I1=cnt2_ff_CQZ_D_LUT4_O_81_I1 I2=$iopadmap$reset I3=cnt2(39) O=cnt2_ff_CQZ_D(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_89_I2 I1=cnt2_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2 I2=cnt2_ff_CQZ_D_LUT4_O_81_I1 I3=cnt2(39) O=cnt2_ff_CQZ_D_LUT4_O_80_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2(35) I1=cnt2(36) I2=cnt2(37) I3=cnt2(38) O=cnt2_ff_CQZ_D_LUT4_O_81_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_83_I2 I1=cnt2(37) I2=$iopadmap$reset I3=cnt2(38) O=cnt2_ff_CQZ_D(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(37) I2=cnt2_ff_CQZ_D_LUT4_O_83_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(36) I2=cnt2(35) I3=cnt2_ff_CQZ_D_LUT4_O_85_I2 O=cnt2_ff_CQZ_D_LUT4_O_83_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_85_I2 I1=cnt2(35) I2=$iopadmap$reset I3=cnt2(36) O=cnt2_ff_CQZ_D(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(35) I2=cnt2_ff_CQZ_D_LUT4_O_85_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt2_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2 I3=cnt2_ff_CQZ_D_LUT4_O_89_I2 O=cnt2_ff_CQZ_D_LUT4_O_85_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cnt2(31) I1=cnt2(32) I2=cnt2(33) I3=cnt2(34) O=cnt2_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_87_I2 I1=cnt2(33) I2=$iopadmap$reset I3=cnt2(34) O=cnt2_ff_CQZ_D(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(33) I2=cnt2_ff_CQZ_D_LUT4_O_87_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(32) I2=cnt2(31) I3=cnt2_ff_CQZ_D_LUT4_O_89_I2 O=cnt2_ff_CQZ_D_LUT4_O_87_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_89_I2 I1=cnt2(31) I2=$iopadmap$reset I3=cnt2(32) O=cnt2_ff_CQZ_D(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(31) I2=cnt2_ff_CQZ_D_LUT4_O_89_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_92_I2 I1=cnt2(28) I2=cnt2(29) I3=cnt2(30) O=cnt2_ff_CQZ_D_LUT4_O_89_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_9_I0 I1=cnt2(110) I2=cnt2(111) I3=cnt2(112) O=cnt2_ff_CQZ_D_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_9_I0 I1=cnt2(110) I2=$iopadmap$reset I3=cnt2(111) O=cnt2_ff_CQZ_D(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_90_I3 O=cnt2_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_92_I2 I1=cnt2(28) I2=cnt2(29) I3=cnt2(30) O=cnt2_ff_CQZ_D_LUT4_O_90_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_92_I2 I1=cnt2(28) I2=$iopadmap$reset I3=cnt2(29) O=cnt2_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(28) I2=cnt2_ff_CQZ_D_LUT4_O_92_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_95_I2 I1=cnt2(25) I2=cnt2(26) I3=cnt2(27) O=cnt2_ff_CQZ_D_LUT4_O_92_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_93_I3 O=cnt2_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_95_I2 I1=cnt2(25) I2=cnt2(26) I3=cnt2(27) O=cnt2_ff_CQZ_D_LUT4_O_93_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_95_I2 I1=cnt2(25) I2=$iopadmap$reset I3=cnt2(26) O=cnt2_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(25) I2=cnt2_ff_CQZ_D_LUT4_O_95_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_98_I2 I1=cnt2(22) I2=cnt2(23) I3=cnt2(24) O=cnt2_ff_CQZ_D_LUT4_O_95_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_96_I3 O=cnt2_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_98_I2 I1=cnt2(22) I2=cnt2(23) I3=cnt2(24) O=cnt2_ff_CQZ_D_LUT4_O_96_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_98_I2 I1=cnt2(22) I2=$iopadmap$reset I3=cnt2(23) O=cnt2_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt2(22) I2=cnt2_ff_CQZ_D_LUT4_O_98_I2 I3=$iopadmap$reset O=cnt2_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_101_I2 I1=cnt2(19) I2=cnt2(20) I3=cnt2(21) O=cnt2_ff_CQZ_D_LUT4_O_98_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt2_ff_CQZ_D_LUT4_O_99_I3 O=cnt2_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_101_I2 I1=cnt2(19) I2=cnt2(20) I3=cnt2(21) O=cnt2_ff_CQZ_D_LUT4_O_99_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_13_I2 I1=cnt2(107) I2=cnt2(108) I3=cnt2(109) O=cnt2_ff_CQZ_D_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt2_ff_CQZ_D_LUT4_O_4_I2 I1=cnt2(116) I2=cnt2(117) I3=cnt2(118) O=cnt2_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cnt3(3) D=cnt3_ff_CQZ_D(3) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(2) D=cnt3_ff_CQZ_D(2) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(114) D=cnt3_ff_CQZ_D(114) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(24) D=cnt3_ff_CQZ_D(24) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(23) D=cnt3_ff_CQZ_D(23) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(22) D=cnt3_ff_CQZ_D(22) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(21) D=cnt3_ff_CQZ_D(21) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(20) D=cnt3_ff_CQZ_D(20) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(19) D=cnt3_ff_CQZ_D(19) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(18) D=cnt3_ff_CQZ_D(18) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(17) D=cnt3_ff_CQZ_D(17) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(16) D=cnt3_ff_CQZ_D(16) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(15) D=cnt3_ff_CQZ_D(15) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(113) D=cnt3_ff_CQZ_D(113) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(14) D=cnt3_ff_CQZ_D(14) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(13) D=cnt3_ff_CQZ_D(13) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(12) D=cnt3_ff_CQZ_D(12) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(11) D=cnt3_ff_CQZ_D(11) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(10) D=cnt3_ff_CQZ_D(10) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(9) D=cnt3_ff_CQZ_D(9) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(8) D=cnt3_ff_CQZ_D(8) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(7) D=cnt3_ff_CQZ_D(7) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(6) D=cnt3_ff_CQZ_D(6) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(5) D=cnt3_ff_CQZ_D(5) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(112) D=cnt3_ff_CQZ_D(112) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(4) D=cnt3_ff_CQZ_D(4) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(111) D=cnt3_ff_CQZ_D(111) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(110) D=cnt3_ff_CQZ_D(110) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(109) D=cnt3_ff_CQZ_D(109) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(108) D=cnt3_ff_CQZ_D(108) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(107) D=cnt3_ff_CQZ_D(107) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(106) D=cnt3_ff_CQZ_D(106) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(105) D=cnt3_ff_CQZ_D(105) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(1) D=cnt3_ff_CQZ_D(1) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(104) D=cnt3_ff_CQZ_D(104) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(103) D=cnt3_ff_CQZ_D(103) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(102) D=cnt3_ff_CQZ_D(102) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(101) D=cnt3_ff_CQZ_D(101) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(100) D=cnt3_ff_CQZ_D(100) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(99) D=cnt3_ff_CQZ_D(99) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(98) D=cnt3_ff_CQZ_D(98) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(97) D=cnt3_ff_CQZ_D(97) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(96) D=cnt3_ff_CQZ_D(96) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(95) D=cnt3_ff_CQZ_D(95) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(0) D=cnt3_ff_CQZ_D(0) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(94) D=cnt3_ff_CQZ_D(94) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(93) D=cnt3_ff_CQZ_D(93) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(92) D=cnt3_ff_CQZ_D(92) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(91) D=cnt3_ff_CQZ_D(91) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(90) D=cnt3_ff_CQZ_D(90) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(89) D=cnt3_ff_CQZ_D(89) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(88) D=cnt3_ff_CQZ_D(88) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(87) D=cnt3_ff_CQZ_D(87) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(86) D=cnt3_ff_CQZ_D(86) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(85) D=cnt3_ff_CQZ_D(85) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(120) D=cnt3_ff_CQZ_D(120) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(84) D=cnt3_ff_CQZ_D(84) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(83) D=cnt3_ff_CQZ_D(83) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(82) D=cnt3_ff_CQZ_D(82) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(81) D=cnt3_ff_CQZ_D(81) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(80) D=cnt3_ff_CQZ_D(80) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(79) D=cnt3_ff_CQZ_D(79) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(78) D=cnt3_ff_CQZ_D(78) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(77) D=cnt3_ff_CQZ_D(77) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(76) D=cnt3_ff_CQZ_D(76) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(75) D=cnt3_ff_CQZ_D(75) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(119) D=cnt3_ff_CQZ_D(119) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(74) D=cnt3_ff_CQZ_D(74) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(73) D=cnt3_ff_CQZ_D(73) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(72) D=cnt3_ff_CQZ_D(72) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(71) D=cnt3_ff_CQZ_D(71) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(70) D=cnt3_ff_CQZ_D(70) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(69) D=cnt3_ff_CQZ_D(69) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(68) D=cnt3_ff_CQZ_D(68) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(67) D=cnt3_ff_CQZ_D(67) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(66) D=cnt3_ff_CQZ_D(66) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(65) D=cnt3_ff_CQZ_D(65) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(118) D=cnt3_ff_CQZ_D(118) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(64) D=cnt3_ff_CQZ_D(64) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(63) D=cnt3_ff_CQZ_D(63) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(62) D=cnt3_ff_CQZ_D(62) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(61) D=cnt3_ff_CQZ_D(61) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(60) D=cnt3_ff_CQZ_D(60) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(59) D=cnt3_ff_CQZ_D(59) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(58) D=cnt3_ff_CQZ_D(58) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(57) D=cnt3_ff_CQZ_D(57) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(56) D=cnt3_ff_CQZ_D(56) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(55) D=cnt3_ff_CQZ_D(55) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(117) D=cnt3_ff_CQZ_D(117) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(54) D=cnt3_ff_CQZ_D(54) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(53) D=cnt3_ff_CQZ_D(53) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(52) D=cnt3_ff_CQZ_D(52) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(51) D=cnt3_ff_CQZ_D(51) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(50) D=cnt3_ff_CQZ_D(50) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(49) D=cnt3_ff_CQZ_D(49) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(48) D=cnt3_ff_CQZ_D(48) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(47) D=cnt3_ff_CQZ_D(47) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(46) D=cnt3_ff_CQZ_D(46) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(45) D=cnt3_ff_CQZ_D(45) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(116) D=cnt3_ff_CQZ_D(116) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(44) D=cnt3_ff_CQZ_D(44) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(43) D=cnt3_ff_CQZ_D(43) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(42) D=cnt3_ff_CQZ_D(42) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(41) D=cnt3_ff_CQZ_D(41) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(40) D=cnt3_ff_CQZ_D(40) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(39) D=cnt3_ff_CQZ_D(39) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(38) D=cnt3_ff_CQZ_D(38) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(37) D=cnt3_ff_CQZ_D(37) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(36) D=cnt3_ff_CQZ_D(36) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(35) D=cnt3_ff_CQZ_D(35) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(115) D=cnt3_ff_CQZ_D(115) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(34) D=cnt3_ff_CQZ_D(34) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(33) D=cnt3_ff_CQZ_D(33) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(32) D=cnt3_ff_CQZ_D(32) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(31) D=cnt3_ff_CQZ_D(31) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(30) D=cnt3_ff_CQZ_D(30) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(29) D=cnt3_ff_CQZ_D(29) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(28) D=cnt3_ff_CQZ_D(28) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(27) D=cnt3_ff_CQZ_D(27) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(26) D=cnt3_ff_CQZ_D(26) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt3(25) D=cnt3_ff_CQZ_D(25) QCK=$iopadmap$clk3 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:59.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_I0 I1=cnt3(119) I2=$iopadmap$reset I3=cnt3(120) O=cnt3_ff_CQZ_D(120)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(119) I2=cnt3_ff_CQZ_D_LUT4_O_I0 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(119)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(110) I2=cnt3_ff_CQZ_D_LUT4_O_9_I0 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_101_I2 I1=cnt3(19) I2=$iopadmap$reset I3=cnt3(20) O=cnt3_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(19) I2=cnt3_ff_CQZ_D_LUT4_O_101_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_104_I2 I1=cnt3(16) I2=cnt3(17) I3=cnt3(18) O=cnt3_ff_CQZ_D_LUT4_O_101_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_102_I3 O=cnt3_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_104_I2 I1=cnt3(16) I2=cnt3(17) I3=cnt3(18) O=cnt3_ff_CQZ_D_LUT4_O_102_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_104_I2 I1=cnt3(16) I2=$iopadmap$reset I3=cnt3(17) O=cnt3_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(16) I2=cnt3_ff_CQZ_D_LUT4_O_104_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_107_I2 I1=cnt3(13) I2=cnt3(14) I3=cnt3(15) O=cnt3_ff_CQZ_D_LUT4_O_104_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_105_I3 O=cnt3_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_107_I2 I1=cnt3(13) I2=cnt3(14) I3=cnt3(15) O=cnt3_ff_CQZ_D_LUT4_O_105_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_107_I2 I1=cnt3(13) I2=$iopadmap$reset I3=cnt3(14) O=cnt3_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(13) I2=cnt3_ff_CQZ_D_LUT4_O_107_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_110_I2 I1=cnt3(10) I2=cnt3(11) I3=cnt3(12) O=cnt3_ff_CQZ_D_LUT4_O_107_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_108_I3 O=cnt3_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_110_I2 I1=cnt3(10) I2=cnt3(11) I3=cnt3(12) O=cnt3_ff_CQZ_D_LUT4_O_108_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_110_I2 I1=cnt3(10) I2=$iopadmap$reset I3=cnt3(11) O=cnt3_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_11_I3 O=cnt3_ff_CQZ_D(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(10) I2=cnt3_ff_CQZ_D_LUT4_O_110_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_113_I2 I1=cnt3(7) I2=cnt3(8) I3=cnt3(9) O=cnt3_ff_CQZ_D_LUT4_O_110_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_111_I3 O=cnt3_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_113_I2 I1=cnt3(7) I2=cnt3(8) I3=cnt3(9) O=cnt3_ff_CQZ_D_LUT4_O_111_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_113_I2 I1=cnt3(7) I2=$iopadmap$reset I3=cnt3(8) O=cnt3_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(7) I2=cnt3_ff_CQZ_D_LUT4_O_113_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_116_I2 I1=cnt3(4) I2=cnt3(5) I3=cnt3(6) O=cnt3_ff_CQZ_D_LUT4_O_113_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_114_I3 O=cnt3_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_116_I2 I1=cnt3(4) I2=cnt3(5) I3=cnt3(6) O=cnt3_ff_CQZ_D_LUT4_O_114_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_116_I2 I1=cnt3(4) I2=$iopadmap$reset I3=cnt3(5) O=cnt3_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(4) I2=cnt3_ff_CQZ_D_LUT4_O_116_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3(0) I1=cnt3(1) I2=cnt3(2) I3=cnt3(3) O=cnt3_ff_CQZ_D_LUT4_O_116_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_117_I3 O=cnt3_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3(0) I1=cnt3(1) I2=cnt3(2) I3=cnt3(3) O=cnt3_ff_CQZ_D_LUT4_O_117_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3(0) I1=cnt3(1) I2=$iopadmap$reset I3=cnt3(2) O=cnt3_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(1) I2=cnt3(0) I3=$iopadmap$reset O=cnt3_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_13_I2 I1=cnt3(107) I2=cnt3(108) I3=cnt3(109) O=cnt3_ff_CQZ_D_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_13_I2 I1=cnt3(107) I2=$iopadmap$reset I3=cnt3(108) O=cnt3_ff_CQZ_D(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt3(0) I3=$iopadmap$reset O=cnt3_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(107) I2=cnt3_ff_CQZ_D_LUT4_O_13_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_16_I2 I1=cnt3(104) I2=cnt3(105) I3=cnt3(106) O=cnt3_ff_CQZ_D_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_14_I3 O=cnt3_ff_CQZ_D(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_16_I2 I1=cnt3(104) I2=cnt3(105) I3=cnt3(106) O=cnt3_ff_CQZ_D_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_16_I2 I1=cnt3(104) I2=$iopadmap$reset I3=cnt3(105) O=cnt3_ff_CQZ_D(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(104) I2=cnt3_ff_CQZ_D_LUT4_O_16_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_19_I2 I1=cnt3(101) I2=cnt3(102) I3=cnt3(103) O=cnt3_ff_CQZ_D_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_17_I3 O=cnt3_ff_CQZ_D(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_19_I2 I1=cnt3(101) I2=cnt3(102) I3=cnt3(103) O=cnt3_ff_CQZ_D_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_19_I2 I1=cnt3(101) I2=$iopadmap$reset I3=cnt3(102) O=cnt3_ff_CQZ_D(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(101) I2=cnt3_ff_CQZ_D_LUT4_O_19_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_22_I2 I1=cnt3(98) I2=cnt3(99) I3=cnt3(100) O=cnt3_ff_CQZ_D_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_2_I3 O=cnt3_ff_CQZ_D(118)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_20_I3 O=cnt3_ff_CQZ_D(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_22_I2 I1=cnt3(98) I2=cnt3(99) I3=cnt3(100) O=cnt3_ff_CQZ_D_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_22_I2 I1=cnt3(98) I2=$iopadmap$reset I3=cnt3(99) O=cnt3_ff_CQZ_D(99)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(98) I2=cnt3_ff_CQZ_D_LUT4_O_22_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(98)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_25_I2 I1=cnt3(95) I2=cnt3(96) I3=cnt3(97) O=cnt3_ff_CQZ_D_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_23_I3 O=cnt3_ff_CQZ_D(97)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_25_I2 I1=cnt3(95) I2=cnt3(96) I3=cnt3(97) O=cnt3_ff_CQZ_D_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_25_I2 I1=cnt3(95) I2=$iopadmap$reset I3=cnt3(96) O=cnt3_ff_CQZ_D(96)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(95) I2=cnt3_ff_CQZ_D_LUT4_O_25_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(95)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_28_I2 I1=cnt3(92) I2=cnt3(93) I3=cnt3(94) O=cnt3_ff_CQZ_D_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_26_I3 O=cnt3_ff_CQZ_D(94)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_28_I2 I1=cnt3(92) I2=cnt3(93) I3=cnt3(94) O=cnt3_ff_CQZ_D_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_28_I2 I1=cnt3(92) I2=$iopadmap$reset I3=cnt3(93) O=cnt3_ff_CQZ_D(93)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(92) I2=cnt3_ff_CQZ_D_LUT4_O_28_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(92)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_31_I2 I1=cnt3(89) I2=cnt3(90) I3=cnt3(91) O=cnt3_ff_CQZ_D_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_29_I3 O=cnt3_ff_CQZ_D(91)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_31_I2 I1=cnt3(89) I2=cnt3(90) I3=cnt3(91) O=cnt3_ff_CQZ_D_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_4_I2 I1=cnt3(116) I2=cnt3(117) I3=cnt3(118) O=cnt3_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_4_I2 I1=cnt3(116) I2=$iopadmap$reset I3=cnt3(117) O=cnt3_ff_CQZ_D(117)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_31_I2 I1=cnt3(89) I2=$iopadmap$reset I3=cnt3(90) O=cnt3_ff_CQZ_D(90)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(89) I2=cnt3_ff_CQZ_D_LUT4_O_31_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(89)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_34_I2 I1=cnt3(86) I2=cnt3(87) I3=cnt3(88) O=cnt3_ff_CQZ_D_LUT4_O_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_32_I3 O=cnt3_ff_CQZ_D(88)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_34_I2 I1=cnt3(86) I2=cnt3(87) I3=cnt3(88) O=cnt3_ff_CQZ_D_LUT4_O_32_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_34_I2 I1=cnt3(86) I2=$iopadmap$reset I3=cnt3(87) O=cnt3_ff_CQZ_D(87)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(86) I2=cnt3_ff_CQZ_D_LUT4_O_34_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(86)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_37_I2 I1=cnt3(83) I2=cnt3(84) I3=cnt3(85) O=cnt3_ff_CQZ_D_LUT4_O_34_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_35_I3 O=cnt3_ff_CQZ_D(85)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_37_I2 I1=cnt3(83) I2=cnt3(84) I3=cnt3(85) O=cnt3_ff_CQZ_D_LUT4_O_35_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_37_I2 I1=cnt3(83) I2=$iopadmap$reset I3=cnt3(84) O=cnt3_ff_CQZ_D(84)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(83) I2=cnt3_ff_CQZ_D_LUT4_O_37_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(83)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_40_I2 I1=cnt3(80) I2=cnt3(81) I3=cnt3(82) O=cnt3_ff_CQZ_D_LUT4_O_37_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_38_I3 O=cnt3_ff_CQZ_D(82)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_40_I2 I1=cnt3(80) I2=cnt3(81) I3=cnt3(82) O=cnt3_ff_CQZ_D_LUT4_O_38_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_40_I2 I1=cnt3(80) I2=$iopadmap$reset I3=cnt3(81) O=cnt3_ff_CQZ_D(81)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(116) I2=cnt3_ff_CQZ_D_LUT4_O_4_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(116)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(80) I2=cnt3_ff_CQZ_D_LUT4_O_40_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_42_I2 I1=cnt3(78) I2=$iopadmap$reset I3=cnt3(79) O=cnt3_ff_CQZ_D(79)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(78) I2=cnt3_ff_CQZ_D_LUT4_O_42_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(78)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(79) I2=cnt3(78) I3=cnt3_ff_CQZ_D_LUT4_O_42_I2 O=cnt3_ff_CQZ_D_LUT4_O_40_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_45_I2 I1=cnt3(75) I2=cnt3(76) I3=cnt3(77) O=cnt3_ff_CQZ_D_LUT4_O_42_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_43_I3 O=cnt3_ff_CQZ_D(77)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_45_I2 I1=cnt3(75) I2=cnt3(76) I3=cnt3(77) O=cnt3_ff_CQZ_D_LUT4_O_43_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_45_I2 I1=cnt3(75) I2=$iopadmap$reset I3=cnt3(76) O=cnt3_ff_CQZ_D(76)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(75) I2=cnt3_ff_CQZ_D_LUT4_O_45_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(75)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_48_I2 I1=cnt3(72) I2=cnt3(73) I3=cnt3(74) O=cnt3_ff_CQZ_D_LUT4_O_45_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_46_I3 O=cnt3_ff_CQZ_D(74)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_48_I2 I1=cnt3(72) I2=cnt3(73) I3=cnt3(74) O=cnt3_ff_CQZ_D_LUT4_O_46_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_48_I2 I1=cnt3(72) I2=$iopadmap$reset I3=cnt3(73) O=cnt3_ff_CQZ_D(73)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(72) I2=cnt3_ff_CQZ_D_LUT4_O_48_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(72)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_53_I2 I1=cnt3_ff_CQZ_D_LUT4_O_49_I1 I2=$iopadmap$reset I3=cnt3(71) O=cnt3_ff_CQZ_D(71)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(71) I2=cnt3_ff_CQZ_D_LUT4_O_49_I1 I3=cnt3_ff_CQZ_D_LUT4_O_53_I2 O=cnt3_ff_CQZ_D_LUT4_O_48_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3(67) I1=cnt3(68) I2=cnt3(69) I3=cnt3(70) O=cnt3_ff_CQZ_D_LUT4_O_49_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_7_I2 I1=cnt3(113) I2=cnt3(114) I3=cnt3(115) O=cnt3_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_5_I3 O=cnt3_ff_CQZ_D(115)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_51_I2 I1=cnt3(69) I2=$iopadmap$reset I3=cnt3(70) O=cnt3_ff_CQZ_D(70)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(69) I2=cnt3_ff_CQZ_D_LUT4_O_51_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(69)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt3(68) I3=cnt3_ff_CQZ_D_LUT4_O_52_I2 O=cnt3_ff_CQZ_D_LUT4_O_51_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(68) I2=cnt3_ff_CQZ_D_LUT4_O_52_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(68)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt3(67) I3=cnt3_ff_CQZ_D_LUT4_O_53_I2 O=cnt3_ff_CQZ_D_LUT4_O_52_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(67) I2=cnt3_ff_CQZ_D_LUT4_O_53_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(67)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_55_I2 I1=cnt3(65) I2=$iopadmap$reset I3=cnt3(66) O=cnt3_ff_CQZ_D(66)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(65) I2=cnt3_ff_CQZ_D_LUT4_O_55_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(65)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(64) I2=cnt3(63) I3=cnt3_ff_CQZ_D_LUT4_O_57_I2 O=cnt3_ff_CQZ_D_LUT4_O_55_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_57_I2 I1=cnt3(63) I2=$iopadmap$reset I3=cnt3(64) O=cnt3_ff_CQZ_D(64)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(63) I2=cnt3_ff_CQZ_D_LUT4_O_57_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(63)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(62) I2=cnt3(61) I3=cnt3_ff_CQZ_D_LUT4_O_58_I0 O=cnt3_ff_CQZ_D_LUT4_O_57_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_58_I0 I1=cnt3(61) I2=$iopadmap$reset I3=cnt3(62) O=cnt3_ff_CQZ_D(62)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_58_I0 I1=cnt3_ff_CQZ_D_LUT4_O_58_I0_LUT4_I0_I1 I2=cnt3(61) I3=cnt3(62) O=cnt3_ff_CQZ_D_LUT4_O_53_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3(63) I1=cnt3(64) I2=cnt3(65) I3=cnt3(66) O=cnt3_ff_CQZ_D_LUT4_O_58_I0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_61_I0 I1=cnt3(58) I2=cnt3(59) I3=cnt3(60) O=cnt3_ff_CQZ_D_LUT4_O_58_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_60_I2 I1=cnt3(60) I2=$iopadmap$reset I3=cnt3(61) O=cnt3_ff_CQZ_D(61)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_7_I2 I1=cnt3(113) I2=cnt3(114) I3=cnt3(115) O=cnt3_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_7_I2 I1=cnt3(113) I2=$iopadmap$reset I3=cnt3(114) O=cnt3_ff_CQZ_D(114)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(60) I2=cnt3_ff_CQZ_D_LUT4_O_60_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(60)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(59) I2=cnt3(58) I3=cnt3_ff_CQZ_D_LUT4_O_61_I0 O=cnt3_ff_CQZ_D_LUT4_O_60_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_61_I0 I1=cnt3(58) I2=$iopadmap$reset I3=cnt3(59) O=cnt3_ff_CQZ_D(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_64_I0 I1=cnt3(55) I2=cnt3(56) I3=cnt3(57) O=cnt3_ff_CQZ_D_LUT4_O_61_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_63_I2 I1=cnt3(57) I2=$iopadmap$reset I3=cnt3(58) O=cnt3_ff_CQZ_D(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(57) I2=cnt3_ff_CQZ_D_LUT4_O_63_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(56) I2=cnt3(55) I3=cnt3_ff_CQZ_D_LUT4_O_64_I0 O=cnt3_ff_CQZ_D_LUT4_O_63_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_64_I0 I1=cnt3(55) I2=$iopadmap$reset I3=cnt3(56) O=cnt3_ff_CQZ_D(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_67_I0 I1=cnt3(52) I2=cnt3(53) I3=cnt3(54) O=cnt3_ff_CQZ_D_LUT4_O_64_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_66_I2 I1=cnt3(54) I2=$iopadmap$reset I3=cnt3(55) O=cnt3_ff_CQZ_D(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(54) I2=cnt3_ff_CQZ_D_LUT4_O_66_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(53) I2=cnt3(52) I3=cnt3_ff_CQZ_D_LUT4_O_67_I0 O=cnt3_ff_CQZ_D_LUT4_O_66_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_67_I0 I1=cnt3(52) I2=$iopadmap$reset I3=cnt3(53) O=cnt3_ff_CQZ_D(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_70_I0 I1=cnt3(49) I2=cnt3(50) I3=cnt3(51) O=cnt3_ff_CQZ_D_LUT4_O_67_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_69_I2 I1=cnt3(51) I2=$iopadmap$reset I3=cnt3(52) O=cnt3_ff_CQZ_D(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(51) I2=cnt3_ff_CQZ_D_LUT4_O_69_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(50) I2=cnt3(49) I3=cnt3_ff_CQZ_D_LUT4_O_70_I0 O=cnt3_ff_CQZ_D_LUT4_O_69_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(113) I2=cnt3_ff_CQZ_D_LUT4_O_7_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(113)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_70_I0 I1=cnt3(49) I2=$iopadmap$reset I3=cnt3(50) O=cnt3_ff_CQZ_D(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_74_I2 I1=cnt3(46) I2=cnt3(47) I3=cnt3(48) O=cnt3_ff_CQZ_D_LUT4_O_70_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_72_I2 I1=cnt3(48) I2=$iopadmap$reset I3=cnt3(49) O=cnt3_ff_CQZ_D(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(48) I2=cnt3_ff_CQZ_D_LUT4_O_72_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(47) I2=cnt3(46) I3=cnt3_ff_CQZ_D_LUT4_O_74_I2 O=cnt3_ff_CQZ_D_LUT4_O_72_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_74_I2 I1=cnt3(46) I2=$iopadmap$reset I3=cnt3(47) O=cnt3_ff_CQZ_D(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(46) I2=cnt3_ff_CQZ_D_LUT4_O_74_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_77_I2 I1=cnt3(43) I2=cnt3(44) I3=cnt3(45) O=cnt3_ff_CQZ_D_LUT4_O_74_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_75_I3 O=cnt3_ff_CQZ_D(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_77_I2 I1=cnt3(43) I2=cnt3(44) I3=cnt3(45) O=cnt3_ff_CQZ_D_LUT4_O_75_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_77_I2 I1=cnt3(43) I2=$iopadmap$reset I3=cnt3(44) O=cnt3_ff_CQZ_D(44)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(43) I2=cnt3_ff_CQZ_D_LUT4_O_77_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_80_I2 I1=cnt3(40) I2=cnt3(41) I3=cnt3(42) O=cnt3_ff_CQZ_D_LUT4_O_77_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_78_I3 O=cnt3_ff_CQZ_D(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_80_I2 I1=cnt3(40) I2=cnt3(41) I3=cnt3(42) O=cnt3_ff_CQZ_D_LUT4_O_78_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_80_I2 I1=cnt3(40) I2=$iopadmap$reset I3=cnt3(41) O=cnt3_ff_CQZ_D(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_9_I0 I1=cnt3(110) I2=cnt3(111) I3=cnt3(112) O=cnt3_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_8_I3 O=cnt3_ff_CQZ_D(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(40) I2=cnt3_ff_CQZ_D_LUT4_O_80_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_85_I2 I1=cnt3_ff_CQZ_D_LUT4_O_81_I1 I2=$iopadmap$reset I3=cnt3(39) O=cnt3_ff_CQZ_D(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_89_I2 I1=cnt3_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2 I2=cnt3_ff_CQZ_D_LUT4_O_81_I1 I3=cnt3(39) O=cnt3_ff_CQZ_D_LUT4_O_80_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3(35) I1=cnt3(36) I2=cnt3(37) I3=cnt3(38) O=cnt3_ff_CQZ_D_LUT4_O_81_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_83_I2 I1=cnt3(37) I2=$iopadmap$reset I3=cnt3(38) O=cnt3_ff_CQZ_D(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(37) I2=cnt3_ff_CQZ_D_LUT4_O_83_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(36) I2=cnt3(35) I3=cnt3_ff_CQZ_D_LUT4_O_85_I2 O=cnt3_ff_CQZ_D_LUT4_O_83_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_85_I2 I1=cnt3(35) I2=$iopadmap$reset I3=cnt3(36) O=cnt3_ff_CQZ_D(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(35) I2=cnt3_ff_CQZ_D_LUT4_O_85_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt3_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2 I3=cnt3_ff_CQZ_D_LUT4_O_89_I2 O=cnt3_ff_CQZ_D_LUT4_O_85_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cnt3(31) I1=cnt3(32) I2=cnt3(33) I3=cnt3(34) O=cnt3_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_87_I2 I1=cnt3(33) I2=$iopadmap$reset I3=cnt3(34) O=cnt3_ff_CQZ_D(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(33) I2=cnt3_ff_CQZ_D_LUT4_O_87_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(32) I2=cnt3(31) I3=cnt3_ff_CQZ_D_LUT4_O_89_I2 O=cnt3_ff_CQZ_D_LUT4_O_87_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_89_I2 I1=cnt3(31) I2=$iopadmap$reset I3=cnt3(32) O=cnt3_ff_CQZ_D(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(31) I2=cnt3_ff_CQZ_D_LUT4_O_89_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_92_I2 I1=cnt3(28) I2=cnt3(29) I3=cnt3(30) O=cnt3_ff_CQZ_D_LUT4_O_89_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_9_I0 I1=cnt3(110) I2=cnt3(111) I3=cnt3(112) O=cnt3_ff_CQZ_D_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_9_I0 I1=cnt3(110) I2=$iopadmap$reset I3=cnt3(111) O=cnt3_ff_CQZ_D(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_90_I3 O=cnt3_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_92_I2 I1=cnt3(28) I2=cnt3(29) I3=cnt3(30) O=cnt3_ff_CQZ_D_LUT4_O_90_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_92_I2 I1=cnt3(28) I2=$iopadmap$reset I3=cnt3(29) O=cnt3_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(28) I2=cnt3_ff_CQZ_D_LUT4_O_92_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_95_I2 I1=cnt3(25) I2=cnt3(26) I3=cnt3(27) O=cnt3_ff_CQZ_D_LUT4_O_92_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_93_I3 O=cnt3_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_95_I2 I1=cnt3(25) I2=cnt3(26) I3=cnt3(27) O=cnt3_ff_CQZ_D_LUT4_O_93_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_95_I2 I1=cnt3(25) I2=$iopadmap$reset I3=cnt3(26) O=cnt3_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(25) I2=cnt3_ff_CQZ_D_LUT4_O_95_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_98_I2 I1=cnt3(22) I2=cnt3(23) I3=cnt3(24) O=cnt3_ff_CQZ_D_LUT4_O_95_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_96_I3 O=cnt3_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_98_I2 I1=cnt3(22) I2=cnt3(23) I3=cnt3(24) O=cnt3_ff_CQZ_D_LUT4_O_96_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_98_I2 I1=cnt3(22) I2=$iopadmap$reset I3=cnt3(23) O=cnt3_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt3(22) I2=cnt3_ff_CQZ_D_LUT4_O_98_I2 I3=$iopadmap$reset O=cnt3_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_101_I2 I1=cnt3(19) I2=cnt3(20) I3=cnt3(21) O=cnt3_ff_CQZ_D_LUT4_O_98_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt3_ff_CQZ_D_LUT4_O_99_I3 O=cnt3_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_101_I2 I1=cnt3(19) I2=cnt3(20) I3=cnt3(21) O=cnt3_ff_CQZ_D_LUT4_O_99_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_13_I2 I1=cnt3(107) I2=cnt3(108) I3=cnt3(109) O=cnt3_ff_CQZ_D_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt3_ff_CQZ_D_LUT4_O_4_I2 I1=cnt3(116) I2=cnt3(117) I3=cnt3(118) O=cnt3_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cnt4(120) D=cnt4_ff_CQZ_D(120) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(119) D=cnt4_ff_CQZ_D(119) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(110) D=cnt4_ff_CQZ_D(110) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(20) D=cnt4_ff_CQZ_D(20) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(19) D=cnt4_ff_CQZ_D(19) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(18) D=cnt4_ff_CQZ_D(18) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(17) D=cnt4_ff_CQZ_D(17) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(16) D=cnt4_ff_CQZ_D(16) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(15) D=cnt4_ff_CQZ_D(15) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(14) D=cnt4_ff_CQZ_D(14) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(13) D=cnt4_ff_CQZ_D(13) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(12) D=cnt4_ff_CQZ_D(12) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(11) D=cnt4_ff_CQZ_D(11) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(109) D=cnt4_ff_CQZ_D(109) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(10) D=cnt4_ff_CQZ_D(10) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(9) D=cnt4_ff_CQZ_D(9) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(8) D=cnt4_ff_CQZ_D(8) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(7) D=cnt4_ff_CQZ_D(7) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(6) D=cnt4_ff_CQZ_D(6) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(5) D=cnt4_ff_CQZ_D(5) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(4) D=cnt4_ff_CQZ_D(4) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(3) D=cnt4_ff_CQZ_D(3) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(2) D=cnt4_ff_CQZ_D(2) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(1) D=cnt4_ff_CQZ_D(1) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(108) D=cnt4_ff_CQZ_D(108) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(0) D=cnt4_ff_CQZ_D(0) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(107) D=cnt4_ff_CQZ_D(107) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(106) D=cnt4_ff_CQZ_D(106) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(105) D=cnt4_ff_CQZ_D(105) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(104) D=cnt4_ff_CQZ_D(104) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(103) D=cnt4_ff_CQZ_D(103) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(102) D=cnt4_ff_CQZ_D(102) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(101) D=cnt4_ff_CQZ_D(101) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(118) D=cnt4_ff_CQZ_D(118) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(100) D=cnt4_ff_CQZ_D(100) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(99) D=cnt4_ff_CQZ_D(99) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(98) D=cnt4_ff_CQZ_D(98) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(97) D=cnt4_ff_CQZ_D(97) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(96) D=cnt4_ff_CQZ_D(96) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(95) D=cnt4_ff_CQZ_D(95) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(94) D=cnt4_ff_CQZ_D(94) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(93) D=cnt4_ff_CQZ_D(93) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(92) D=cnt4_ff_CQZ_D(92) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(91) D=cnt4_ff_CQZ_D(91) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(117) D=cnt4_ff_CQZ_D(117) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(90) D=cnt4_ff_CQZ_D(90) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(89) D=cnt4_ff_CQZ_D(89) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(88) D=cnt4_ff_CQZ_D(88) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(87) D=cnt4_ff_CQZ_D(87) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(86) D=cnt4_ff_CQZ_D(86) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(85) D=cnt4_ff_CQZ_D(85) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(84) D=cnt4_ff_CQZ_D(84) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(83) D=cnt4_ff_CQZ_D(83) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(82) D=cnt4_ff_CQZ_D(82) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(81) D=cnt4_ff_CQZ_D(81) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(116) D=cnt4_ff_CQZ_D(116) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(80) D=cnt4_ff_CQZ_D(80) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(79) D=cnt4_ff_CQZ_D(79) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(78) D=cnt4_ff_CQZ_D(78) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(77) D=cnt4_ff_CQZ_D(77) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(76) D=cnt4_ff_CQZ_D(76) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(75) D=cnt4_ff_CQZ_D(75) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(74) D=cnt4_ff_CQZ_D(74) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(73) D=cnt4_ff_CQZ_D(73) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(72) D=cnt4_ff_CQZ_D(72) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(71) D=cnt4_ff_CQZ_D(71) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(115) D=cnt4_ff_CQZ_D(115) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(70) D=cnt4_ff_CQZ_D(70) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(69) D=cnt4_ff_CQZ_D(69) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(68) D=cnt4_ff_CQZ_D(68) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(67) D=cnt4_ff_CQZ_D(67) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(66) D=cnt4_ff_CQZ_D(66) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(65) D=cnt4_ff_CQZ_D(65) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(64) D=cnt4_ff_CQZ_D(64) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(63) D=cnt4_ff_CQZ_D(63) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(62) D=cnt4_ff_CQZ_D(62) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(61) D=cnt4_ff_CQZ_D(61) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(114) D=cnt4_ff_CQZ_D(114) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(60) D=cnt4_ff_CQZ_D(60) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(59) D=cnt4_ff_CQZ_D(59) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(58) D=cnt4_ff_CQZ_D(58) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(57) D=cnt4_ff_CQZ_D(57) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(56) D=cnt4_ff_CQZ_D(56) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(55) D=cnt4_ff_CQZ_D(55) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(54) D=cnt4_ff_CQZ_D(54) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(53) D=cnt4_ff_CQZ_D(53) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(52) D=cnt4_ff_CQZ_D(52) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(51) D=cnt4_ff_CQZ_D(51) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(113) D=cnt4_ff_CQZ_D(113) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(50) D=cnt4_ff_CQZ_D(50) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(49) D=cnt4_ff_CQZ_D(49) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(48) D=cnt4_ff_CQZ_D(48) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(47) D=cnt4_ff_CQZ_D(47) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(46) D=cnt4_ff_CQZ_D(46) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(45) D=cnt4_ff_CQZ_D(45) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(44) D=cnt4_ff_CQZ_D(44) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(43) D=cnt4_ff_CQZ_D(43) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(42) D=cnt4_ff_CQZ_D(42) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(41) D=cnt4_ff_CQZ_D(41) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(112) D=cnt4_ff_CQZ_D(112) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(40) D=cnt4_ff_CQZ_D(40) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(39) D=cnt4_ff_CQZ_D(39) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(38) D=cnt4_ff_CQZ_D(38) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(37) D=cnt4_ff_CQZ_D(37) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(36) D=cnt4_ff_CQZ_D(36) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(35) D=cnt4_ff_CQZ_D(35) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(34) D=cnt4_ff_CQZ_D(34) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(33) D=cnt4_ff_CQZ_D(33) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(32) D=cnt4_ff_CQZ_D(32) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(31) D=cnt4_ff_CQZ_D(31) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(111) D=cnt4_ff_CQZ_D(111) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(30) D=cnt4_ff_CQZ_D(30) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(29) D=cnt4_ff_CQZ_D(29) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(28) D=cnt4_ff_CQZ_D(28) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(27) D=cnt4_ff_CQZ_D(27) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(26) D=cnt4_ff_CQZ_D(26) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(25) D=cnt4_ff_CQZ_D(25) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(24) D=cnt4_ff_CQZ_D(24) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(23) D=cnt4_ff_CQZ_D(23) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(22) D=cnt4_ff_CQZ_D(22) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt4(21) D=cnt4_ff_CQZ_D(21) QCK=$iopadmap$clk4 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:72.1-84.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_I0 I1=cnt4(119) I2=$iopadmap$reset I3=cnt4(120) O=cnt4_ff_CQZ_D(120)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(119) I2=cnt4_ff_CQZ_D_LUT4_O_I0 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(119)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(110) I2=cnt4_ff_CQZ_D_LUT4_O_9_I0 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_101_I2 I1=cnt4(19) I2=$iopadmap$reset I3=cnt4(20) O=cnt4_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(19) I2=cnt4_ff_CQZ_D_LUT4_O_101_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_104_I2 I1=cnt4(16) I2=cnt4(17) I3=cnt4(18) O=cnt4_ff_CQZ_D_LUT4_O_101_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_102_I3 O=cnt4_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_104_I2 I1=cnt4(16) I2=cnt4(17) I3=cnt4(18) O=cnt4_ff_CQZ_D_LUT4_O_102_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_104_I2 I1=cnt4(16) I2=$iopadmap$reset I3=cnt4(17) O=cnt4_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(16) I2=cnt4_ff_CQZ_D_LUT4_O_104_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_107_I2 I1=cnt4(13) I2=cnt4(14) I3=cnt4(15) O=cnt4_ff_CQZ_D_LUT4_O_104_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_105_I3 O=cnt4_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_107_I2 I1=cnt4(13) I2=cnt4(14) I3=cnt4(15) O=cnt4_ff_CQZ_D_LUT4_O_105_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_107_I2 I1=cnt4(13) I2=$iopadmap$reset I3=cnt4(14) O=cnt4_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(13) I2=cnt4_ff_CQZ_D_LUT4_O_107_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_110_I2 I1=cnt4(10) I2=cnt4(11) I3=cnt4(12) O=cnt4_ff_CQZ_D_LUT4_O_107_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_108_I3 O=cnt4_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_110_I2 I1=cnt4(10) I2=cnt4(11) I3=cnt4(12) O=cnt4_ff_CQZ_D_LUT4_O_108_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_110_I2 I1=cnt4(10) I2=$iopadmap$reset I3=cnt4(11) O=cnt4_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_11_I3 O=cnt4_ff_CQZ_D(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(10) I2=cnt4_ff_CQZ_D_LUT4_O_110_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_113_I2 I1=cnt4(7) I2=cnt4(8) I3=cnt4(9) O=cnt4_ff_CQZ_D_LUT4_O_110_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_111_I3 O=cnt4_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_113_I2 I1=cnt4(7) I2=cnt4(8) I3=cnt4(9) O=cnt4_ff_CQZ_D_LUT4_O_111_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_113_I2 I1=cnt4(7) I2=$iopadmap$reset I3=cnt4(8) O=cnt4_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(7) I2=cnt4_ff_CQZ_D_LUT4_O_113_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_116_I2 I1=cnt4(4) I2=cnt4(5) I3=cnt4(6) O=cnt4_ff_CQZ_D_LUT4_O_113_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_114_I3 O=cnt4_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_116_I2 I1=cnt4(4) I2=cnt4(5) I3=cnt4(6) O=cnt4_ff_CQZ_D_LUT4_O_114_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_116_I2 I1=cnt4(4) I2=$iopadmap$reset I3=cnt4(5) O=cnt4_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(4) I2=cnt4_ff_CQZ_D_LUT4_O_116_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4(0) I1=cnt4(1) I2=cnt4(2) I3=cnt4(3) O=cnt4_ff_CQZ_D_LUT4_O_116_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_117_I3 O=cnt4_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4(0) I1=cnt4(1) I2=cnt4(2) I3=cnt4(3) O=cnt4_ff_CQZ_D_LUT4_O_117_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4(0) I1=cnt4(1) I2=$iopadmap$reset I3=cnt4(2) O=cnt4_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(1) I2=cnt4(0) I3=$iopadmap$reset O=cnt4_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_13_I2 I1=cnt4(107) I2=cnt4(108) I3=cnt4(109) O=cnt4_ff_CQZ_D_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_13_I2 I1=cnt4(107) I2=$iopadmap$reset I3=cnt4(108) O=cnt4_ff_CQZ_D(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4(0) O=cnt4_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(107) I2=cnt4_ff_CQZ_D_LUT4_O_13_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_16_I2 I1=cnt4(104) I2=cnt4(105) I3=cnt4(106) O=cnt4_ff_CQZ_D_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_14_I3 O=cnt4_ff_CQZ_D(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_16_I2 I1=cnt4(104) I2=cnt4(105) I3=cnt4(106) O=cnt4_ff_CQZ_D_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_16_I2 I1=cnt4(104) I2=$iopadmap$reset I3=cnt4(105) O=cnt4_ff_CQZ_D(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(104) I2=cnt4_ff_CQZ_D_LUT4_O_16_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_19_I2 I1=cnt4(101) I2=cnt4(102) I3=cnt4(103) O=cnt4_ff_CQZ_D_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_17_I3 O=cnt4_ff_CQZ_D(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_19_I2 I1=cnt4(101) I2=cnt4(102) I3=cnt4(103) O=cnt4_ff_CQZ_D_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_19_I2 I1=cnt4(101) I2=$iopadmap$reset I3=cnt4(102) O=cnt4_ff_CQZ_D(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(101) I2=cnt4_ff_CQZ_D_LUT4_O_19_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_22_I2 I1=cnt4(98) I2=cnt4(99) I3=cnt4(100) O=cnt4_ff_CQZ_D_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_2_I3 O=cnt4_ff_CQZ_D(118)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_20_I3 O=cnt4_ff_CQZ_D(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_22_I2 I1=cnt4(98) I2=cnt4(99) I3=cnt4(100) O=cnt4_ff_CQZ_D_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_22_I2 I1=cnt4(98) I2=$iopadmap$reset I3=cnt4(99) O=cnt4_ff_CQZ_D(99)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(98) I2=cnt4_ff_CQZ_D_LUT4_O_22_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(98)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_25_I2 I1=cnt4(95) I2=cnt4(96) I3=cnt4(97) O=cnt4_ff_CQZ_D_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_23_I3 O=cnt4_ff_CQZ_D(97)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_25_I2 I1=cnt4(95) I2=cnt4(96) I3=cnt4(97) O=cnt4_ff_CQZ_D_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_25_I2 I1=cnt4(95) I2=$iopadmap$reset I3=cnt4(96) O=cnt4_ff_CQZ_D(96)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(95) I2=cnt4_ff_CQZ_D_LUT4_O_25_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(95)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_28_I2 I1=cnt4(92) I2=cnt4(93) I3=cnt4(94) O=cnt4_ff_CQZ_D_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_26_I3 O=cnt4_ff_CQZ_D(94)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_28_I2 I1=cnt4(92) I2=cnt4(93) I3=cnt4(94) O=cnt4_ff_CQZ_D_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_28_I2 I1=cnt4(92) I2=$iopadmap$reset I3=cnt4(93) O=cnt4_ff_CQZ_D(93)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(92) I2=cnt4_ff_CQZ_D_LUT4_O_28_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(92)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_31_I2 I1=cnt4(89) I2=cnt4(90) I3=cnt4(91) O=cnt4_ff_CQZ_D_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_29_I3 O=cnt4_ff_CQZ_D(91)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_31_I2 I1=cnt4(89) I2=cnt4(90) I3=cnt4(91) O=cnt4_ff_CQZ_D_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_4_I2 I1=cnt4(116) I2=cnt4(117) I3=cnt4(118) O=cnt4_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_4_I2 I1=cnt4(116) I2=$iopadmap$reset I3=cnt4(117) O=cnt4_ff_CQZ_D(117)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_31_I2 I1=cnt4(89) I2=$iopadmap$reset I3=cnt4(90) O=cnt4_ff_CQZ_D(90)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(89) I2=cnt4_ff_CQZ_D_LUT4_O_31_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(89)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_34_I2 I1=cnt4(86) I2=cnt4(87) I3=cnt4(88) O=cnt4_ff_CQZ_D_LUT4_O_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_32_I3 O=cnt4_ff_CQZ_D(88)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_34_I2 I1=cnt4(86) I2=cnt4(87) I3=cnt4(88) O=cnt4_ff_CQZ_D_LUT4_O_32_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_34_I2 I1=cnt4(86) I2=$iopadmap$reset I3=cnt4(87) O=cnt4_ff_CQZ_D(87)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(86) I2=cnt4_ff_CQZ_D_LUT4_O_34_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(86)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_37_I2 I1=cnt4(83) I2=cnt4(84) I3=cnt4(85) O=cnt4_ff_CQZ_D_LUT4_O_34_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_35_I3 O=cnt4_ff_CQZ_D(85)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_37_I2 I1=cnt4(83) I2=cnt4(84) I3=cnt4(85) O=cnt4_ff_CQZ_D_LUT4_O_35_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_37_I2 I1=cnt4(83) I2=$iopadmap$reset I3=cnt4(84) O=cnt4_ff_CQZ_D(84)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(83) I2=cnt4_ff_CQZ_D_LUT4_O_37_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(83)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_40_I2 I1=cnt4(80) I2=cnt4(81) I3=cnt4(82) O=cnt4_ff_CQZ_D_LUT4_O_37_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_38_I3 O=cnt4_ff_CQZ_D(82)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_40_I2 I1=cnt4(80) I2=cnt4(81) I3=cnt4(82) O=cnt4_ff_CQZ_D_LUT4_O_38_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_40_I2 I1=cnt4(80) I2=$iopadmap$reset I3=cnt4(81) O=cnt4_ff_CQZ_D(81)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(116) I2=cnt4_ff_CQZ_D_LUT4_O_4_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(116)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(80) I2=cnt4_ff_CQZ_D_LUT4_O_40_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_42_I2 I1=cnt4(78) I2=$iopadmap$reset I3=cnt4(79) O=cnt4_ff_CQZ_D(79)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(78) I2=cnt4_ff_CQZ_D_LUT4_O_42_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(78)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(79) I2=cnt4(78) I3=cnt4_ff_CQZ_D_LUT4_O_42_I2 O=cnt4_ff_CQZ_D_LUT4_O_40_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_45_I2 I1=cnt4(75) I2=cnt4(76) I3=cnt4(77) O=cnt4_ff_CQZ_D_LUT4_O_42_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_43_I3 O=cnt4_ff_CQZ_D(77)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_45_I2 I1=cnt4(75) I2=cnt4(76) I3=cnt4(77) O=cnt4_ff_CQZ_D_LUT4_O_43_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_45_I2 I1=cnt4(75) I2=$iopadmap$reset I3=cnt4(76) O=cnt4_ff_CQZ_D(76)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(75) I2=cnt4_ff_CQZ_D_LUT4_O_45_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(75)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_48_I2 I1=cnt4(72) I2=cnt4(73) I3=cnt4(74) O=cnt4_ff_CQZ_D_LUT4_O_45_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_46_I3 O=cnt4_ff_CQZ_D(74)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_48_I2 I1=cnt4(72) I2=cnt4(73) I3=cnt4(74) O=cnt4_ff_CQZ_D_LUT4_O_46_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_48_I2 I1=cnt4(72) I2=$iopadmap$reset I3=cnt4(73) O=cnt4_ff_CQZ_D(73)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(72) I2=cnt4_ff_CQZ_D_LUT4_O_48_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(72)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_53_I2 I1=cnt4_ff_CQZ_D_LUT4_O_49_I1 I2=$iopadmap$reset I3=cnt4(71) O=cnt4_ff_CQZ_D(71)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(71) I2=cnt4_ff_CQZ_D_LUT4_O_49_I1 I3=cnt4_ff_CQZ_D_LUT4_O_53_I2 O=cnt4_ff_CQZ_D_LUT4_O_48_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4(67) I1=cnt4(68) I2=cnt4(69) I3=cnt4(70) O=cnt4_ff_CQZ_D_LUT4_O_49_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_7_I2 I1=cnt4(113) I2=cnt4(114) I3=cnt4(115) O=cnt4_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_5_I3 O=cnt4_ff_CQZ_D(115)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_51_I2 I1=cnt4(69) I2=$iopadmap$reset I3=cnt4(70) O=cnt4_ff_CQZ_D(70)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(69) I2=cnt4_ff_CQZ_D_LUT4_O_51_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(69)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt4(68) I3=cnt4_ff_CQZ_D_LUT4_O_52_I2 O=cnt4_ff_CQZ_D_LUT4_O_51_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(68) I2=cnt4_ff_CQZ_D_LUT4_O_52_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(68)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt4(67) I3=cnt4_ff_CQZ_D_LUT4_O_53_I2 O=cnt4_ff_CQZ_D_LUT4_O_52_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(67) I2=cnt4_ff_CQZ_D_LUT4_O_53_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(67)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_55_I2 I1=cnt4(65) I2=$iopadmap$reset I3=cnt4(66) O=cnt4_ff_CQZ_D(66)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(65) I2=cnt4_ff_CQZ_D_LUT4_O_55_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(65)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(64) I2=cnt4(63) I3=cnt4_ff_CQZ_D_LUT4_O_57_I2 O=cnt4_ff_CQZ_D_LUT4_O_55_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_57_I2 I1=cnt4(63) I2=$iopadmap$reset I3=cnt4(64) O=cnt4_ff_CQZ_D(64)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(63) I2=cnt4_ff_CQZ_D_LUT4_O_57_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(63)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(62) I2=cnt4(61) I3=cnt4_ff_CQZ_D_LUT4_O_58_I0 O=cnt4_ff_CQZ_D_LUT4_O_57_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_58_I0 I1=cnt4(61) I2=$iopadmap$reset I3=cnt4(62) O=cnt4_ff_CQZ_D(62)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_58_I0 I1=cnt4_ff_CQZ_D_LUT4_O_58_I0_LUT4_I0_I1 I2=cnt4(61) I3=cnt4(62) O=cnt4_ff_CQZ_D_LUT4_O_53_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4(63) I1=cnt4(64) I2=cnt4(65) I3=cnt4(66) O=cnt4_ff_CQZ_D_LUT4_O_58_I0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_61_I0 I1=cnt4(58) I2=cnt4(59) I3=cnt4(60) O=cnt4_ff_CQZ_D_LUT4_O_58_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_60_I2 I1=cnt4(60) I2=$iopadmap$reset I3=cnt4(61) O=cnt4_ff_CQZ_D(61)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_7_I2 I1=cnt4(113) I2=cnt4(114) I3=cnt4(115) O=cnt4_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_7_I2 I1=cnt4(113) I2=$iopadmap$reset I3=cnt4(114) O=cnt4_ff_CQZ_D(114)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(60) I2=cnt4_ff_CQZ_D_LUT4_O_60_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(60)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(59) I2=cnt4(58) I3=cnt4_ff_CQZ_D_LUT4_O_61_I0 O=cnt4_ff_CQZ_D_LUT4_O_60_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_61_I0 I1=cnt4(58) I2=$iopadmap$reset I3=cnt4(59) O=cnt4_ff_CQZ_D(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_64_I0 I1=cnt4(55) I2=cnt4(56) I3=cnt4(57) O=cnt4_ff_CQZ_D_LUT4_O_61_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_63_I2 I1=cnt4(57) I2=$iopadmap$reset I3=cnt4(58) O=cnt4_ff_CQZ_D(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(57) I2=cnt4_ff_CQZ_D_LUT4_O_63_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(56) I2=cnt4(55) I3=cnt4_ff_CQZ_D_LUT4_O_64_I0 O=cnt4_ff_CQZ_D_LUT4_O_63_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_64_I0 I1=cnt4(55) I2=$iopadmap$reset I3=cnt4(56) O=cnt4_ff_CQZ_D(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_67_I0 I1=cnt4(52) I2=cnt4(53) I3=cnt4(54) O=cnt4_ff_CQZ_D_LUT4_O_64_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_66_I2 I1=cnt4(54) I2=$iopadmap$reset I3=cnt4(55) O=cnt4_ff_CQZ_D(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(54) I2=cnt4_ff_CQZ_D_LUT4_O_66_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(53) I2=cnt4(52) I3=cnt4_ff_CQZ_D_LUT4_O_67_I0 O=cnt4_ff_CQZ_D_LUT4_O_66_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_67_I0 I1=cnt4(52) I2=$iopadmap$reset I3=cnt4(53) O=cnt4_ff_CQZ_D(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_70_I0 I1=cnt4(49) I2=cnt4(50) I3=cnt4(51) O=cnt4_ff_CQZ_D_LUT4_O_67_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_69_I2 I1=cnt4(51) I2=$iopadmap$reset I3=cnt4(52) O=cnt4_ff_CQZ_D(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(51) I2=cnt4_ff_CQZ_D_LUT4_O_69_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(50) I2=cnt4(49) I3=cnt4_ff_CQZ_D_LUT4_O_70_I0 O=cnt4_ff_CQZ_D_LUT4_O_69_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(113) I2=cnt4_ff_CQZ_D_LUT4_O_7_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(113)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_70_I0 I1=cnt4(49) I2=$iopadmap$reset I3=cnt4(50) O=cnt4_ff_CQZ_D(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_74_I2 I1=cnt4(46) I2=cnt4(47) I3=cnt4(48) O=cnt4_ff_CQZ_D_LUT4_O_70_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_72_I2 I1=cnt4(48) I2=$iopadmap$reset I3=cnt4(49) O=cnt4_ff_CQZ_D(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(48) I2=cnt4_ff_CQZ_D_LUT4_O_72_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(47) I2=cnt4(46) I3=cnt4_ff_CQZ_D_LUT4_O_74_I2 O=cnt4_ff_CQZ_D_LUT4_O_72_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_74_I2 I1=cnt4(46) I2=$iopadmap$reset I3=cnt4(47) O=cnt4_ff_CQZ_D(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(46) I2=cnt4_ff_CQZ_D_LUT4_O_74_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_77_I2 I1=cnt4(43) I2=cnt4(44) I3=cnt4(45) O=cnt4_ff_CQZ_D_LUT4_O_74_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_75_I3 O=cnt4_ff_CQZ_D(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_77_I2 I1=cnt4(43) I2=cnt4(44) I3=cnt4(45) O=cnt4_ff_CQZ_D_LUT4_O_75_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_77_I2 I1=cnt4(43) I2=$iopadmap$reset I3=cnt4(44) O=cnt4_ff_CQZ_D(44)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(43) I2=cnt4_ff_CQZ_D_LUT4_O_77_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_80_I2 I1=cnt4(40) I2=cnt4(41) I3=cnt4(42) O=cnt4_ff_CQZ_D_LUT4_O_77_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_78_I3 O=cnt4_ff_CQZ_D(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_80_I2 I1=cnt4(40) I2=cnt4(41) I3=cnt4(42) O=cnt4_ff_CQZ_D_LUT4_O_78_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_80_I2 I1=cnt4(40) I2=$iopadmap$reset I3=cnt4(41) O=cnt4_ff_CQZ_D(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_9_I0 I1=cnt4(110) I2=cnt4(111) I3=cnt4(112) O=cnt4_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_8_I3 O=cnt4_ff_CQZ_D(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(40) I2=cnt4_ff_CQZ_D_LUT4_O_80_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_85_I2 I1=cnt4_ff_CQZ_D_LUT4_O_81_I1 I2=$iopadmap$reset I3=cnt4(39) O=cnt4_ff_CQZ_D(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_89_I2 I1=cnt4_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2 I2=cnt4_ff_CQZ_D_LUT4_O_81_I1 I3=cnt4(39) O=cnt4_ff_CQZ_D_LUT4_O_80_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4(35) I1=cnt4(36) I2=cnt4(37) I3=cnt4(38) O=cnt4_ff_CQZ_D_LUT4_O_81_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_83_I2 I1=cnt4(37) I2=$iopadmap$reset I3=cnt4(38) O=cnt4_ff_CQZ_D(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(37) I2=cnt4_ff_CQZ_D_LUT4_O_83_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(36) I2=cnt4(35) I3=cnt4_ff_CQZ_D_LUT4_O_85_I2 O=cnt4_ff_CQZ_D_LUT4_O_83_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_85_I2 I1=cnt4(35) I2=$iopadmap$reset I3=cnt4(36) O=cnt4_ff_CQZ_D(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(35) I2=cnt4_ff_CQZ_D_LUT4_O_85_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt4_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2 I3=cnt4_ff_CQZ_D_LUT4_O_89_I2 O=cnt4_ff_CQZ_D_LUT4_O_85_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cnt4(31) I1=cnt4(32) I2=cnt4(33) I3=cnt4(34) O=cnt4_ff_CQZ_D_LUT4_O_85_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_87_I2 I1=cnt4(33) I2=$iopadmap$reset I3=cnt4(34) O=cnt4_ff_CQZ_D(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(33) I2=cnt4_ff_CQZ_D_LUT4_O_87_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(32) I2=cnt4(31) I3=cnt4_ff_CQZ_D_LUT4_O_89_I2 O=cnt4_ff_CQZ_D_LUT4_O_87_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_89_I2 I1=cnt4(31) I2=$iopadmap$reset I3=cnt4(32) O=cnt4_ff_CQZ_D(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(31) I2=cnt4_ff_CQZ_D_LUT4_O_89_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_92_I2 I1=cnt4(28) I2=cnt4(29) I3=cnt4(30) O=cnt4_ff_CQZ_D_LUT4_O_89_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_9_I0 I1=cnt4(110) I2=cnt4(111) I3=cnt4(112) O=cnt4_ff_CQZ_D_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_9_I0 I1=cnt4(110) I2=$iopadmap$reset I3=cnt4(111) O=cnt4_ff_CQZ_D(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_90_I3 O=cnt4_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_92_I2 I1=cnt4(28) I2=cnt4(29) I3=cnt4(30) O=cnt4_ff_CQZ_D_LUT4_O_90_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_92_I2 I1=cnt4(28) I2=$iopadmap$reset I3=cnt4(29) O=cnt4_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(28) I2=cnt4_ff_CQZ_D_LUT4_O_92_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_95_I2 I1=cnt4(25) I2=cnt4(26) I3=cnt4(27) O=cnt4_ff_CQZ_D_LUT4_O_92_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_93_I3 O=cnt4_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_95_I2 I1=cnt4(25) I2=cnt4(26) I3=cnt4(27) O=cnt4_ff_CQZ_D_LUT4_O_93_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_95_I2 I1=cnt4(25) I2=$iopadmap$reset I3=cnt4(26) O=cnt4_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(25) I2=cnt4_ff_CQZ_D_LUT4_O_95_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_98_I2 I1=cnt4(22) I2=cnt4(23) I3=cnt4(24) O=cnt4_ff_CQZ_D_LUT4_O_95_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_96_I3 O=cnt4_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_98_I2 I1=cnt4(22) I2=cnt4(23) I3=cnt4(24) O=cnt4_ff_CQZ_D_LUT4_O_96_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_98_I2 I1=cnt4(22) I2=$iopadmap$reset I3=cnt4(23) O=cnt4_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt4(22) I2=cnt4_ff_CQZ_D_LUT4_O_98_I2 I3=$iopadmap$reset O=cnt4_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_101_I2 I1=cnt4(19) I2=cnt4(20) I3=cnt4(21) O=cnt4_ff_CQZ_D_LUT4_O_98_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt4_ff_CQZ_D_LUT4_O_99_I3 O=cnt4_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_101_I2 I1=cnt4(19) I2=cnt4(20) I3=cnt4(21) O=cnt4_ff_CQZ_D_LUT4_O_99_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_13_I2 I1=cnt4(107) I2=cnt4(108) I3=cnt4(109) O=cnt4_ff_CQZ_D_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt4_ff_CQZ_D_LUT4_O_4_I2 I1=cnt4(116) I2=cnt4(117) I3=cnt4(118) O=cnt4_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cnt5(120) D=cnt5_ff_CQZ_D(120) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(119) D=cnt5_ff_CQZ_D(119) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(110) D=cnt5_ff_CQZ_D(110) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(20) D=cnt5_ff_CQZ_D(20) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(19) D=cnt5_ff_CQZ_D(19) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(18) D=cnt5_ff_CQZ_D(18) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(17) D=cnt5_ff_CQZ_D(17) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(16) D=cnt5_ff_CQZ_D(16) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(15) D=cnt5_ff_CQZ_D(15) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(14) D=cnt5_ff_CQZ_D(14) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(13) D=cnt5_ff_CQZ_D(13) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(12) D=cnt5_ff_CQZ_D(12) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(11) D=cnt5_ff_CQZ_D(11) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(109) D=cnt5_ff_CQZ_D(109) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(10) D=cnt5_ff_CQZ_D(10) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(9) D=cnt5_ff_CQZ_D(9) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(8) D=cnt5_ff_CQZ_D(8) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(7) D=cnt5_ff_CQZ_D(7) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(6) D=cnt5_ff_CQZ_D(6) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(5) D=cnt5_ff_CQZ_D(5) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(4) D=cnt5_ff_CQZ_D(4) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(3) D=cnt5_ff_CQZ_D(3) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(2) D=cnt5_ff_CQZ_D(2) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(1) D=cnt5_ff_CQZ_D(1) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(108) D=cnt5_ff_CQZ_D(108) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(0) D=cnt5_ff_CQZ_D(0) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(107) D=cnt5_ff_CQZ_D(107) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(106) D=cnt5_ff_CQZ_D(106) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(105) D=cnt5_ff_CQZ_D(105) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(104) D=cnt5_ff_CQZ_D(104) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(103) D=cnt5_ff_CQZ_D(103) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(102) D=cnt5_ff_CQZ_D(102) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(101) D=cnt5_ff_CQZ_D(101) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(118) D=cnt5_ff_CQZ_D(118) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(100) D=cnt5_ff_CQZ_D(100) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(99) D=cnt5_ff_CQZ_D(99) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(98) D=cnt5_ff_CQZ_D(98) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(97) D=cnt5_ff_CQZ_D(97) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(96) D=cnt5_ff_CQZ_D(96) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(95) D=cnt5_ff_CQZ_D(95) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(94) D=cnt5_ff_CQZ_D(94) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(93) D=cnt5_ff_CQZ_D(93) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(92) D=cnt5_ff_CQZ_D(92) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(91) D=cnt5_ff_CQZ_D(91) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(117) D=cnt5_ff_CQZ_D(117) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(90) D=cnt5_ff_CQZ_D(90) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(89) D=cnt5_ff_CQZ_D(89) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(88) D=cnt5_ff_CQZ_D(88) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(87) D=cnt5_ff_CQZ_D(87) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(86) D=cnt5_ff_CQZ_D(86) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(85) D=cnt5_ff_CQZ_D(85) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(84) D=cnt5_ff_CQZ_D(84) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(83) D=cnt5_ff_CQZ_D(83) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(82) D=cnt5_ff_CQZ_D(82) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(81) D=cnt5_ff_CQZ_D(81) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(116) D=cnt5_ff_CQZ_D(116) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(80) D=cnt5_ff_CQZ_D(80) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(79) D=cnt5_ff_CQZ_D(79) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(78) D=cnt5_ff_CQZ_D(78) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(77) D=cnt5_ff_CQZ_D(77) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(76) D=cnt5_ff_CQZ_D(76) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(75) D=cnt5_ff_CQZ_D(75) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(74) D=cnt5_ff_CQZ_D(74) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(73) D=cnt5_ff_CQZ_D(73) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(72) D=cnt5_ff_CQZ_D(72) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(71) D=cnt5_ff_CQZ_D(71) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(115) D=cnt5_ff_CQZ_D(115) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(70) D=cnt5_ff_CQZ_D(70) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(69) D=cnt5_ff_CQZ_D(69) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(68) D=cnt5_ff_CQZ_D(68) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(67) D=cnt5_ff_CQZ_D(67) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(66) D=cnt5_ff_CQZ_D(66) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(65) D=cnt5_ff_CQZ_D(65) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(64) D=cnt5_ff_CQZ_D(64) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(63) D=cnt5_ff_CQZ_D(63) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(62) D=cnt5_ff_CQZ_D(62) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(61) D=cnt5_ff_CQZ_D(61) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(114) D=cnt5_ff_CQZ_D(114) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(60) D=cnt5_ff_CQZ_D(60) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(59) D=cnt5_ff_CQZ_D(59) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(58) D=cnt5_ff_CQZ_D(58) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(57) D=cnt5_ff_CQZ_D(57) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(56) D=cnt5_ff_CQZ_D(56) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(55) D=cnt5_ff_CQZ_D(55) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(54) D=cnt5_ff_CQZ_D(54) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(53) D=cnt5_ff_CQZ_D(53) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(52) D=cnt5_ff_CQZ_D(52) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(51) D=cnt5_ff_CQZ_D(51) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(113) D=cnt5_ff_CQZ_D(113) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(50) D=cnt5_ff_CQZ_D(50) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(49) D=cnt5_ff_CQZ_D(49) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(48) D=cnt5_ff_CQZ_D(48) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(47) D=cnt5_ff_CQZ_D(47) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(46) D=cnt5_ff_CQZ_D(46) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(45) D=cnt5_ff_CQZ_D(45) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(44) D=cnt5_ff_CQZ_D(44) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(43) D=cnt5_ff_CQZ_D(43) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(42) D=cnt5_ff_CQZ_D(42) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(41) D=cnt5_ff_CQZ_D(41) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(112) D=cnt5_ff_CQZ_D(112) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(40) D=cnt5_ff_CQZ_D(40) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(39) D=cnt5_ff_CQZ_D(39) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(38) D=cnt5_ff_CQZ_D(38) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(37) D=cnt5_ff_CQZ_D(37) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(36) D=cnt5_ff_CQZ_D(36) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(35) D=cnt5_ff_CQZ_D(35) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(34) D=cnt5_ff_CQZ_D(34) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(33) D=cnt5_ff_CQZ_D(33) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(32) D=cnt5_ff_CQZ_D(32) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(31) D=cnt5_ff_CQZ_D(31) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(111) D=cnt5_ff_CQZ_D(111) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(30) D=cnt5_ff_CQZ_D(30) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(29) D=cnt5_ff_CQZ_D(29) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(28) D=cnt5_ff_CQZ_D(28) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(27) D=cnt5_ff_CQZ_D(27) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(26) D=cnt5_ff_CQZ_D(26) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(25) D=cnt5_ff_CQZ_D(25) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(24) D=cnt5_ff_CQZ_D(24) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(23) D=cnt5_ff_CQZ_D(23) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(22) D=cnt5_ff_CQZ_D(22) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cnt5(21) D=cnt5_ff_CQZ_D(21) QCK=$iopadmap$clk5 QEN=$auto$hilomap.cc:39:hilomap_worker$10927 QRT=$auto$hilomap.cc:47:hilomap_worker$10925 QST=$auto$hilomap.cc:47:hilomap_worker$10925
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter120bitx5/rtl/counter_5_120_13.v:86.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt5(0) I3=$iopadmap$reset O=cnt5_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_2_I2 I1=cnt5(119) I2=$iopadmap$reset I3=cnt5(120) O=cnt5_ff_CQZ_D(120)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_11_I2 I1=cnt5(110) I2=$iopadmap$reset I3=cnt5(111) O=cnt5_ff_CQZ_D(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_100_I3 O=cnt5_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_102_I2 I1=cnt5(19) I2=cnt5(20) I3=cnt5(21) O=cnt5_ff_CQZ_D_LUT4_O_100_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_102_I2 I1=cnt5(19) I2=$iopadmap$reset I3=cnt5(20) O=cnt5_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(19) I2=cnt5_ff_CQZ_D_LUT4_O_102_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_105_I2 I1=cnt5(16) I2=cnt5(17) I3=cnt5(18) O=cnt5_ff_CQZ_D_LUT4_O_102_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_103_I3 O=cnt5_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_105_I2 I1=cnt5(16) I2=cnt5(17) I3=cnt5(18) O=cnt5_ff_CQZ_D_LUT4_O_103_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_105_I2 I1=cnt5(16) I2=$iopadmap$reset I3=cnt5(17) O=cnt5_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(16) I2=cnt5_ff_CQZ_D_LUT4_O_105_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_108_I2 I1=cnt5(13) I2=cnt5(14) I3=cnt5(15) O=cnt5_ff_CQZ_D_LUT4_O_105_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_106_I3 O=cnt5_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_108_I2 I1=cnt5(13) I2=cnt5(14) I3=cnt5(15) O=cnt5_ff_CQZ_D_LUT4_O_106_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_108_I2 I1=cnt5(13) I2=$iopadmap$reset I3=cnt5(14) O=cnt5_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(13) I2=cnt5_ff_CQZ_D_LUT4_O_108_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_111_I2 I1=cnt5(10) I2=cnt5(11) I3=cnt5(12) O=cnt5_ff_CQZ_D_LUT4_O_108_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_109_I3 O=cnt5_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_111_I2 I1=cnt5(10) I2=cnt5(11) I3=cnt5(12) O=cnt5_ff_CQZ_D_LUT4_O_109_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(110) I2=cnt5_ff_CQZ_D_LUT4_O_11_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_111_I2 I1=cnt5(10) I2=$iopadmap$reset I3=cnt5(11) O=cnt5_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(10) I2=cnt5_ff_CQZ_D_LUT4_O_111_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_114_I2 I1=cnt5(7) I2=cnt5(8) I3=cnt5(9) O=cnt5_ff_CQZ_D_LUT4_O_111_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_112_I3 O=cnt5_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_114_I2 I1=cnt5(7) I2=cnt5(8) I3=cnt5(9) O=cnt5_ff_CQZ_D_LUT4_O_112_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_114_I2 I1=cnt5(7) I2=$iopadmap$reset I3=cnt5(8) O=cnt5_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(7) I2=cnt5_ff_CQZ_D_LUT4_O_114_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_117_I2 I1=cnt5(4) I2=cnt5(5) I3=cnt5(6) O=cnt5_ff_CQZ_D_LUT4_O_114_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_115_I3 O=cnt5_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_117_I2 I1=cnt5(4) I2=cnt5(5) I3=cnt5(6) O=cnt5_ff_CQZ_D_LUT4_O_115_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_117_I2 I1=cnt5(4) I2=$iopadmap$reset I3=cnt5(5) O=cnt5_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(4) I2=cnt5_ff_CQZ_D_LUT4_O_117_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5(0) I1=cnt5(1) I2=cnt5(2) I3=cnt5(3) O=cnt5_ff_CQZ_D_LUT4_O_117_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_118_I3 O=cnt5_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5(0) I1=cnt5(1) I2=cnt5(2) I3=cnt5(3) O=cnt5_ff_CQZ_D_LUT4_O_118_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5(0) I1=cnt5(1) I2=$iopadmap$reset I3=cnt5(2) O=cnt5_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_14_I2 I1=cnt5(107) I2=cnt5(108) I3=cnt5(109) O=cnt5_ff_CQZ_D_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_12_I3 O=cnt5_ff_CQZ_D(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(1) I2=cnt5(0) I3=$iopadmap$reset O=cnt5_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_14_I2 I1=cnt5(107) I2=cnt5(108) I3=cnt5(109) O=cnt5_ff_CQZ_D_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_14_I2 I1=cnt5(107) I2=$iopadmap$reset I3=cnt5(108) O=cnt5_ff_CQZ_D(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(107) I2=cnt5_ff_CQZ_D_LUT4_O_14_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_17_I2 I1=cnt5(104) I2=cnt5(105) I3=cnt5(106) O=cnt5_ff_CQZ_D_LUT4_O_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_15_I3 O=cnt5_ff_CQZ_D(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_17_I2 I1=cnt5(104) I2=cnt5(105) I3=cnt5(106) O=cnt5_ff_CQZ_D_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_17_I2 I1=cnt5(104) I2=$iopadmap$reset I3=cnt5(105) O=cnt5_ff_CQZ_D(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(104) I2=cnt5_ff_CQZ_D_LUT4_O_17_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_20_I2 I1=cnt5(101) I2=cnt5(102) I3=cnt5(103) O=cnt5_ff_CQZ_D_LUT4_O_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_18_I3 O=cnt5_ff_CQZ_D(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_20_I2 I1=cnt5(101) I2=cnt5(102) I3=cnt5(103) O=cnt5_ff_CQZ_D_LUT4_O_18_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_20_I2 I1=cnt5(101) I2=$iopadmap$reset I3=cnt5(102) O=cnt5_ff_CQZ_D(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(119) I2=cnt5_ff_CQZ_D_LUT4_O_2_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(119)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(101) I2=cnt5_ff_CQZ_D_LUT4_O_20_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_23_I2 I1=cnt5(98) I2=cnt5(99) I3=cnt5(100) O=cnt5_ff_CQZ_D_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_21_I3 O=cnt5_ff_CQZ_D(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_23_I2 I1=cnt5(98) I2=cnt5(99) I3=cnt5(100) O=cnt5_ff_CQZ_D_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_23_I2 I1=cnt5(98) I2=$iopadmap$reset I3=cnt5(99) O=cnt5_ff_CQZ_D(99)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(98) I2=cnt5_ff_CQZ_D_LUT4_O_23_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(98)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_26_I2 I1=cnt5(95) I2=cnt5(96) I3=cnt5(97) O=cnt5_ff_CQZ_D_LUT4_O_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_24_I3 O=cnt5_ff_CQZ_D(97)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_26_I2 I1=cnt5(95) I2=cnt5(96) I3=cnt5(97) O=cnt5_ff_CQZ_D_LUT4_O_24_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_26_I2 I1=cnt5(95) I2=$iopadmap$reset I3=cnt5(96) O=cnt5_ff_CQZ_D(96)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(95) I2=cnt5_ff_CQZ_D_LUT4_O_26_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(95)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_29_I2 I1=cnt5(92) I2=cnt5(93) I3=cnt5(94) O=cnt5_ff_CQZ_D_LUT4_O_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_27_I3 O=cnt5_ff_CQZ_D(94)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_29_I2 I1=cnt5(92) I2=cnt5(93) I3=cnt5(94) O=cnt5_ff_CQZ_D_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_29_I2 I1=cnt5(92) I2=$iopadmap$reset I3=cnt5(93) O=cnt5_ff_CQZ_D(93)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(92) I2=cnt5_ff_CQZ_D_LUT4_O_29_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(92)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_32_I2 I1=cnt5(89) I2=cnt5(90) I3=cnt5(91) O=cnt5_ff_CQZ_D_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_5_I2 I1=cnt5(116) I2=cnt5(117) I3=cnt5(118) O=cnt5_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_3_I3 O=cnt5_ff_CQZ_D(118)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_30_I3 O=cnt5_ff_CQZ_D(91)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_32_I2 I1=cnt5(89) I2=cnt5(90) I3=cnt5(91) O=cnt5_ff_CQZ_D_LUT4_O_30_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_32_I2 I1=cnt5(89) I2=$iopadmap$reset I3=cnt5(90) O=cnt5_ff_CQZ_D(90)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(89) I2=cnt5_ff_CQZ_D_LUT4_O_32_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(89)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_35_I2 I1=cnt5(86) I2=cnt5(87) I3=cnt5(88) O=cnt5_ff_CQZ_D_LUT4_O_32_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_33_I3 O=cnt5_ff_CQZ_D(88)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_35_I2 I1=cnt5(86) I2=cnt5(87) I3=cnt5(88) O=cnt5_ff_CQZ_D_LUT4_O_33_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_35_I2 I1=cnt5(86) I2=$iopadmap$reset I3=cnt5(87) O=cnt5_ff_CQZ_D(87)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(86) I2=cnt5_ff_CQZ_D_LUT4_O_35_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(86)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_38_I2 I1=cnt5(83) I2=cnt5(84) I3=cnt5(85) O=cnt5_ff_CQZ_D_LUT4_O_35_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_36_I3 O=cnt5_ff_CQZ_D(85)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_38_I2 I1=cnt5(83) I2=cnt5(84) I3=cnt5(85) O=cnt5_ff_CQZ_D_LUT4_O_36_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_38_I2 I1=cnt5(83) I2=$iopadmap$reset I3=cnt5(84) O=cnt5_ff_CQZ_D(84)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(83) I2=cnt5_ff_CQZ_D_LUT4_O_38_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(83)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_41_I2 I1=cnt5(80) I2=cnt5(81) I3=cnt5(82) O=cnt5_ff_CQZ_D_LUT4_O_38_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_39_I3 O=cnt5_ff_CQZ_D(82)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_41_I2 I1=cnt5(80) I2=cnt5(81) I3=cnt5(82) O=cnt5_ff_CQZ_D_LUT4_O_39_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_5_I2 I1=cnt5(116) I2=cnt5(117) I3=cnt5(118) O=cnt5_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_5_I2 I1=cnt5(116) I2=$iopadmap$reset I3=cnt5(117) O=cnt5_ff_CQZ_D(117)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_41_I2 I1=cnt5(80) I2=$iopadmap$reset I3=cnt5(81) O=cnt5_ff_CQZ_D(81)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(80) I2=cnt5_ff_CQZ_D_LUT4_O_41_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_43_I2 I1=cnt5(78) I2=$iopadmap$reset I3=cnt5(79) O=cnt5_ff_CQZ_D(79)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(78) I2=cnt5_ff_CQZ_D_LUT4_O_43_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(78)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(79) I2=cnt5(78) I3=cnt5_ff_CQZ_D_LUT4_O_43_I2 O=cnt5_ff_CQZ_D_LUT4_O_41_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_46_I2 I1=cnt5(75) I2=cnt5(76) I3=cnt5(77) O=cnt5_ff_CQZ_D_LUT4_O_43_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_44_I3 O=cnt5_ff_CQZ_D(77)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_46_I2 I1=cnt5(75) I2=cnt5(76) I3=cnt5(77) O=cnt5_ff_CQZ_D_LUT4_O_44_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_46_I2 I1=cnt5(75) I2=$iopadmap$reset I3=cnt5(76) O=cnt5_ff_CQZ_D(76)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(75) I2=cnt5_ff_CQZ_D_LUT4_O_46_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(75)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_49_I2 I1=cnt5(72) I2=cnt5(73) I3=cnt5(74) O=cnt5_ff_CQZ_D_LUT4_O_46_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_47_I3 O=cnt5_ff_CQZ_D(74)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_49_I2 I1=cnt5(72) I2=cnt5(73) I3=cnt5(74) O=cnt5_ff_CQZ_D_LUT4_O_47_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_49_I2 I1=cnt5(72) I2=$iopadmap$reset I3=cnt5(73) O=cnt5_ff_CQZ_D(73)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(72) I2=cnt5_ff_CQZ_D_LUT4_O_49_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(72)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(116) I2=cnt5_ff_CQZ_D_LUT4_O_5_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(116)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_54_I2 I1=cnt5_ff_CQZ_D_LUT4_O_50_I1 I2=$iopadmap$reset I3=cnt5(71) O=cnt5_ff_CQZ_D(71)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(71) I2=cnt5_ff_CQZ_D_LUT4_O_50_I1 I3=cnt5_ff_CQZ_D_LUT4_O_54_I2 O=cnt5_ff_CQZ_D_LUT4_O_49_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5(67) I1=cnt5(68) I2=cnt5(69) I3=cnt5(70) O=cnt5_ff_CQZ_D_LUT4_O_50_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_52_I2 I1=cnt5(69) I2=$iopadmap$reset I3=cnt5(70) O=cnt5_ff_CQZ_D(70)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(69) I2=cnt5_ff_CQZ_D_LUT4_O_52_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(69)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt5(68) I3=cnt5_ff_CQZ_D_LUT4_O_53_I2 O=cnt5_ff_CQZ_D_LUT4_O_52_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(68) I2=cnt5_ff_CQZ_D_LUT4_O_53_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(68)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt5(67) I3=cnt5_ff_CQZ_D_LUT4_O_54_I2 O=cnt5_ff_CQZ_D_LUT4_O_53_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(67) I2=cnt5_ff_CQZ_D_LUT4_O_54_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(67)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_56_I2 I1=cnt5(65) I2=$iopadmap$reset I3=cnt5(66) O=cnt5_ff_CQZ_D(66)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(65) I2=cnt5_ff_CQZ_D_LUT4_O_56_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(65)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(64) I2=cnt5(63) I3=cnt5_ff_CQZ_D_LUT4_O_58_I2 O=cnt5_ff_CQZ_D_LUT4_O_56_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_58_I2 I1=cnt5(63) I2=$iopadmap$reset I3=cnt5(64) O=cnt5_ff_CQZ_D(64)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(63) I2=cnt5_ff_CQZ_D_LUT4_O_58_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(63)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(62) I2=cnt5(61) I3=cnt5_ff_CQZ_D_LUT4_O_59_I0 O=cnt5_ff_CQZ_D_LUT4_O_58_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_59_I0 I1=cnt5(61) I2=$iopadmap$reset I3=cnt5(62) O=cnt5_ff_CQZ_D(62)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_59_I0 I1=cnt5_ff_CQZ_D_LUT4_O_59_I0_LUT4_I0_I1 I2=cnt5(61) I3=cnt5(62) O=cnt5_ff_CQZ_D_LUT4_O_54_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5(63) I1=cnt5(64) I2=cnt5(65) I3=cnt5(66) O=cnt5_ff_CQZ_D_LUT4_O_59_I0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_62_I0 I1=cnt5(58) I2=cnt5(59) I3=cnt5(60) O=cnt5_ff_CQZ_D_LUT4_O_59_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_8_I2 I1=cnt5(113) I2=cnt5(114) I3=cnt5(115) O=cnt5_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_6_I3 O=cnt5_ff_CQZ_D(115)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_61_I2 I1=cnt5(60) I2=$iopadmap$reset I3=cnt5(61) O=cnt5_ff_CQZ_D(61)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(60) I2=cnt5_ff_CQZ_D_LUT4_O_61_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(60)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(59) I2=cnt5(58) I3=cnt5_ff_CQZ_D_LUT4_O_62_I0 O=cnt5_ff_CQZ_D_LUT4_O_61_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_62_I0 I1=cnt5(58) I2=$iopadmap$reset I3=cnt5(59) O=cnt5_ff_CQZ_D(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_65_I0 I1=cnt5(55) I2=cnt5(56) I3=cnt5(57) O=cnt5_ff_CQZ_D_LUT4_O_62_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_64_I2 I1=cnt5(57) I2=$iopadmap$reset I3=cnt5(58) O=cnt5_ff_CQZ_D(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(57) I2=cnt5_ff_CQZ_D_LUT4_O_64_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(56) I2=cnt5(55) I3=cnt5_ff_CQZ_D_LUT4_O_65_I0 O=cnt5_ff_CQZ_D_LUT4_O_64_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_65_I0 I1=cnt5(55) I2=$iopadmap$reset I3=cnt5(56) O=cnt5_ff_CQZ_D(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_68_I0 I1=cnt5(52) I2=cnt5(53) I3=cnt5(54) O=cnt5_ff_CQZ_D_LUT4_O_65_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_67_I2 I1=cnt5(54) I2=$iopadmap$reset I3=cnt5(55) O=cnt5_ff_CQZ_D(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(54) I2=cnt5_ff_CQZ_D_LUT4_O_67_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(53) I2=cnt5(52) I3=cnt5_ff_CQZ_D_LUT4_O_68_I0 O=cnt5_ff_CQZ_D_LUT4_O_67_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_68_I0 I1=cnt5(52) I2=$iopadmap$reset I3=cnt5(53) O=cnt5_ff_CQZ_D(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_71_I0 I1=cnt5(49) I2=cnt5(50) I3=cnt5(51) O=cnt5_ff_CQZ_D_LUT4_O_68_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_70_I2 I1=cnt5(51) I2=$iopadmap$reset I3=cnt5(52) O=cnt5_ff_CQZ_D(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_8_I2 I1=cnt5(113) I2=cnt5(114) I3=cnt5(115) O=cnt5_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_8_I2 I1=cnt5(113) I2=$iopadmap$reset I3=cnt5(114) O=cnt5_ff_CQZ_D(114)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(51) I2=cnt5_ff_CQZ_D_LUT4_O_70_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(50) I2=cnt5(49) I3=cnt5_ff_CQZ_D_LUT4_O_71_I0 O=cnt5_ff_CQZ_D_LUT4_O_70_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_71_I0 I1=cnt5(49) I2=$iopadmap$reset I3=cnt5(50) O=cnt5_ff_CQZ_D(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_75_I2 I1=cnt5(46) I2=cnt5(47) I3=cnt5(48) O=cnt5_ff_CQZ_D_LUT4_O_71_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_73_I2 I1=cnt5(48) I2=$iopadmap$reset I3=cnt5(49) O=cnt5_ff_CQZ_D(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(48) I2=cnt5_ff_CQZ_D_LUT4_O_73_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(47) I2=cnt5(46) I3=cnt5_ff_CQZ_D_LUT4_O_75_I2 O=cnt5_ff_CQZ_D_LUT4_O_73_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_75_I2 I1=cnt5(46) I2=$iopadmap$reset I3=cnt5(47) O=cnt5_ff_CQZ_D(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(46) I2=cnt5_ff_CQZ_D_LUT4_O_75_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_78_I2 I1=cnt5(43) I2=cnt5(44) I3=cnt5(45) O=cnt5_ff_CQZ_D_LUT4_O_75_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_76_I3 O=cnt5_ff_CQZ_D(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_78_I2 I1=cnt5(43) I2=cnt5(44) I3=cnt5(45) O=cnt5_ff_CQZ_D_LUT4_O_76_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_78_I2 I1=cnt5(43) I2=$iopadmap$reset I3=cnt5(44) O=cnt5_ff_CQZ_D(44)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(43) I2=cnt5_ff_CQZ_D_LUT4_O_78_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_81_I2 I1=cnt5(40) I2=cnt5(41) I3=cnt5(42) O=cnt5_ff_CQZ_D_LUT4_O_78_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_79_I3 O=cnt5_ff_CQZ_D(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_81_I2 I1=cnt5(40) I2=cnt5(41) I3=cnt5(42) O=cnt5_ff_CQZ_D_LUT4_O_79_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(113) I2=cnt5_ff_CQZ_D_LUT4_O_8_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(113)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_81_I2 I1=cnt5(40) I2=$iopadmap$reset I3=cnt5(41) O=cnt5_ff_CQZ_D(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(40) I2=cnt5_ff_CQZ_D_LUT4_O_81_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_86_I2 I1=cnt5_ff_CQZ_D_LUT4_O_82_I1 I2=$iopadmap$reset I3=cnt5(39) O=cnt5_ff_CQZ_D(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_90_I2 I1=cnt5_ff_CQZ_D_LUT4_O_86_I2_LUT4_O_I2 I2=cnt5_ff_CQZ_D_LUT4_O_82_I1 I3=cnt5(39) O=cnt5_ff_CQZ_D_LUT4_O_81_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5(35) I1=cnt5(36) I2=cnt5(37) I3=cnt5(38) O=cnt5_ff_CQZ_D_LUT4_O_82_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_84_I2 I1=cnt5(37) I2=$iopadmap$reset I3=cnt5(38) O=cnt5_ff_CQZ_D(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(37) I2=cnt5_ff_CQZ_D_LUT4_O_84_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(36) I2=cnt5(35) I3=cnt5_ff_CQZ_D_LUT4_O_86_I2 O=cnt5_ff_CQZ_D_LUT4_O_84_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_86_I2 I1=cnt5(35) I2=$iopadmap$reset I3=cnt5(36) O=cnt5_ff_CQZ_D(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(35) I2=cnt5_ff_CQZ_D_LUT4_O_86_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=cnt5_ff_CQZ_D_LUT4_O_86_I2_LUT4_O_I2 I3=cnt5_ff_CQZ_D_LUT4_O_90_I2 O=cnt5_ff_CQZ_D_LUT4_O_86_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cnt5(31) I1=cnt5(32) I2=cnt5(33) I3=cnt5(34) O=cnt5_ff_CQZ_D_LUT4_O_86_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_88_I2 I1=cnt5(33) I2=$iopadmap$reset I3=cnt5(34) O=cnt5_ff_CQZ_D(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(33) I2=cnt5_ff_CQZ_D_LUT4_O_88_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(32) I2=cnt5(31) I3=cnt5_ff_CQZ_D_LUT4_O_90_I2 O=cnt5_ff_CQZ_D_LUT4_O_88_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_90_I2 I1=cnt5(31) I2=$iopadmap$reset I3=cnt5(32) O=cnt5_ff_CQZ_D(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_11_I2 I1=cnt5(110) I2=cnt5(111) I3=cnt5(112) O=cnt5_ff_CQZ_D_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_9_I3 O=cnt5_ff_CQZ_D(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(31) I2=cnt5_ff_CQZ_D_LUT4_O_90_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_93_I2 I1=cnt5(28) I2=cnt5(29) I3=cnt5(30) O=cnt5_ff_CQZ_D_LUT4_O_90_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_91_I3 O=cnt5_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_93_I2 I1=cnt5(28) I2=cnt5(29) I3=cnt5(30) O=cnt5_ff_CQZ_D_LUT4_O_91_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_93_I2 I1=cnt5(28) I2=$iopadmap$reset I3=cnt5(29) O=cnt5_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(28) I2=cnt5_ff_CQZ_D_LUT4_O_93_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_96_I2 I1=cnt5(25) I2=cnt5(26) I3=cnt5(27) O=cnt5_ff_CQZ_D_LUT4_O_93_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_94_I3 O=cnt5_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_96_I2 I1=cnt5(25) I2=cnt5(26) I3=cnt5(27) O=cnt5_ff_CQZ_D_LUT4_O_94_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_96_I2 I1=cnt5(25) I2=$iopadmap$reset I3=cnt5(26) O=cnt5_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(25) I2=cnt5_ff_CQZ_D_LUT4_O_96_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_99_I2 I1=cnt5(22) I2=cnt5(23) I3=cnt5(24) O=cnt5_ff_CQZ_D_LUT4_O_96_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=$auto$hilomap.cc:47:hilomap_worker$10925 I2=$iopadmap$reset I3=cnt5_ff_CQZ_D_LUT4_O_97_I3 O=cnt5_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_99_I2 I1=cnt5(22) I2=cnt5(23) I3=cnt5(24) O=cnt5_ff_CQZ_D_LUT4_O_97_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_99_I2 I1=cnt5(22) I2=$iopadmap$reset I3=cnt5(23) O=cnt5_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$10925 I1=cnt5(22) I2=cnt5_ff_CQZ_D_LUT4_O_99_I2 I3=$iopadmap$reset O=cnt5_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_102_I2 I1=cnt5(19) I2=cnt5(20) I3=cnt5(21) O=cnt5_ff_CQZ_D_LUT4_O_99_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cnt5_ff_CQZ_D_LUT4_O_11_I2 I1=cnt5(110) I2=cnt5(111) I3=cnt5(112) O=cnt5_ff_CQZ_D_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.end
diff --git a/BENCHMARK/counter120bitx5/rtl/counter_5_120_13.v b/BENCHMARK/counter120bitx5/rtl/counter_5_120_13.v
new file mode 100644
index 0000000..c9d2bd2
--- /dev/null
+++ b/BENCHMARK/counter120bitx5/rtl/counter_5_120_13.v
@@ -0,0 +1,102 @@
+// 5 counter with 5 clock domain
+// each counter has 130 bits
+// each counter has 21 output
+
+// test: placement , routing and performace for each clock domain
+
+module counter120bitx5(clk1,clk2,clk3,clk4,clk5,out1x,out2x,out3x,out4x,out5x,reset);
+
+input clk1,clk2,clk3,clk4,clk5,reset;
+
+output [13:0] out1x;
+output [13:0] out2x;
+output [13:0] out3x;
+output [13:0] out4x;
+output [13:0] out5x;
+
+reg [120:0] cnt1;
+reg [120:0] cnt2;
+reg [120:0] cnt3;
+reg [120:0] cnt4;
+reg [120:0] cnt5;
+
+
+assign out1x = {cnt1[120:115],cnt1[7:0]};
+assign out2x = {cnt2[120:115],cnt2[7:0]};
+assign out3x = {cnt3[120:115],cnt3[7:0]};
+assign out4x = {cnt4[120:115],cnt4[7:0]};
+assign out5x = {cnt5[120:115],cnt5[7:0]};
+                     
+
+always  @(posedge clk1)
+
+begin
+
+    if (reset)
+
+        cnt1 <=1'b0;
+
+    else
+
+        cnt1 <= cnt1+1;
+
+end
+
+
+always  @(posedge clk2)
+
+begin
+
+    if (reset)
+
+        cnt2 <=1'b0;
+
+    else
+
+        cnt2 <= cnt2 +1;
+
+end
+always  @(posedge clk3)
+
+begin
+
+    if (reset)
+
+        cnt3 <=1'b0;
+
+    else
+
+        cnt3 <= cnt3 +1;
+
+end
+always  @(posedge clk4)
+
+begin
+
+    if (reset)
+
+        cnt4 <=1'b0;
+
+    else
+
+        cnt4 <= cnt4 +1;
+
+end
+
+always  @(posedge clk5)
+
+begin
+
+    if (reset)
+
+        cnt5 <=1'b0;
+
+    else
+
+        cnt5 <= cnt5 +1;
+
+end
+
+
+endmodule
+
diff --git a/BENCHMARK/counter_16bit/counter_16bit_yosys.blif b/BENCHMARK/counter_16bit/counter_16bit_yosys.blif
new file mode 100644
index 0000000..77c4a5a
--- /dev/null
+++ b/BENCHMARK/counter_16bit/counter_16bit_yosys.blif
@@ -0,0 +1,246 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model top
+.inputs clk reset enable
+.outputs count(0) count(1) count(2) count(3) count(4) count(5) count(6) count(7) count(8) count(9) count(10) count(11) count(12) count(13) count(14) count(15)
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_0 a=$auto$hilomap.cc:47:hilomap_worker$708
+.subckt in_buff A=clk Q=$iopadmap$clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=$iopadmap$count(0) Q=count(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(1) Q=count(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(10) Q=count(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(11) Q=count(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(12) Q=count(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(13) Q=count(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(14) Q=count(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(15) Q=count(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(2) Q=count(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(3) Q=count(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(4) Q=count(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(5) Q=count(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(6) Q=count(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(7) Q=count(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(8) Q=count(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$count(9) Q=count(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=enable Q=$iopadmap$enable
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=reset Q=$iopadmap$reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt ff CQZ=$iopadmap$count(15) D=count_ff_CQZ_D(15) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(14) D=count_ff_CQZ_D(14) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(5) D=count_ff_CQZ_D(5) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(4) D=count_ff_CQZ_D(4) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(3) D=count_ff_CQZ_D(3) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(2) D=count_ff_CQZ_D(2) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(1) D=count_ff_CQZ_D(1) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(0) D=count_ff_CQZ_D(0) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(13) D=count_ff_CQZ_D(13) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(12) D=count_ff_CQZ_D(12) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(11) D=count_ff_CQZ_D(11) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(10) D=count_ff_CQZ_D(10) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(9) D=count_ff_CQZ_D(9) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(8) D=count_ff_CQZ_D(8) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(7) D=count_ff_CQZ_D(7) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$count(6) D=count_ff_CQZ_D(6) QCK=$iopadmap$clk QEN=enable_LUT4_I2_O QRT=$auto$hilomap.cc:47:hilomap_worker$708 QST=$auto$hilomap.cc:47:hilomap_worker$708
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/counter_16bit/rtl/counter_16bit.v:14.1-19.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$auto$hilomap.cc:47:hilomap_worker$708 I2=$iopadmap$enable I3=$iopadmap$reset O=enable_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$auto$hilomap.cc:47:hilomap_worker$708 I2=$iopadmap$reset I3=reset_LUT4_I2_I3 O=count_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_I2 I1=$iopadmap$count(13) I2=$iopadmap$reset I3=$iopadmap$count(14) O=count_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$auto$hilomap.cc:47:hilomap_worker$708 I2=$iopadmap$reset I3=reset_LUT4_I2_2_I3 O=count_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_1_I2 I1=$iopadmap$count(10) I2=$iopadmap$count(11) I3=$iopadmap$count(12) O=reset_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=reset_LUT4_I3_1_I2 I1=$iopadmap$count(10) I2=$iopadmap$reset I3=$iopadmap$count(11) O=count_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$auto$hilomap.cc:47:hilomap_worker$708 I2=$iopadmap$reset I3=reset_LUT4_I2_4_I3 O=count_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I2 I1=$iopadmap$count(7) I2=$iopadmap$count(8) I3=$iopadmap$count(9) O=reset_LUT4_I2_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=reset_LUT4_I3_2_I2 I1=$iopadmap$count(7) I2=$iopadmap$reset I3=$iopadmap$count(8) O=count_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$auto$hilomap.cc:47:hilomap_worker$708 I2=$iopadmap$reset I3=reset_LUT4_I2_6_I3 O=count_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_3_I2 I1=$iopadmap$count(4) I2=$iopadmap$count(5) I3=$iopadmap$count(6) O=reset_LUT4_I2_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=reset_LUT4_I3_3_I2 I1=$iopadmap$count(4) I2=$iopadmap$reset I3=$iopadmap$count(5) O=count_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$auto$hilomap.cc:47:hilomap_worker$708 I2=$iopadmap$reset I3=reset_LUT4_I2_8_I3 O=count_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$count(0) I1=$iopadmap$count(1) I2=$iopadmap$count(2) I3=$iopadmap$count(3) O=reset_LUT4_I2_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=$iopadmap$count(0) I1=$iopadmap$count(1) I2=$iopadmap$reset I3=$iopadmap$count(2) O=count_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=reset_LUT4_I3_I2 I1=$iopadmap$count(13) I2=$iopadmap$count(14) I3=$iopadmap$count(15) O=reset_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$iopadmap$count(13) I2=reset_LUT4_I3_I2 I3=$iopadmap$reset O=count_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$iopadmap$count(10) I2=reset_LUT4_I3_1_I2 I3=$iopadmap$reset O=count_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=reset_LUT4_I3_2_I2 I1=$iopadmap$count(7) I2=$iopadmap$count(8) I3=$iopadmap$count(9) O=reset_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$iopadmap$count(7) I2=reset_LUT4_I3_2_I2 I3=$iopadmap$reset O=count_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=reset_LUT4_I3_3_I2 I1=$iopadmap$count(4) I2=$iopadmap$count(5) I3=$iopadmap$count(6) O=reset_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$iopadmap$count(4) I2=reset_LUT4_I3_3_I2 I3=$iopadmap$reset O=count_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$iopadmap$count(0) I1=$iopadmap$count(1) I2=$iopadmap$count(2) I3=$iopadmap$count(3) O=reset_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$iopadmap$count(1) I2=$iopadmap$count(0) I3=$iopadmap$reset O=count_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$708 I1=$auto$hilomap.cc:47:hilomap_worker$708 I2=$iopadmap$count(0) I3=$iopadmap$reset O=count_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_1_I2 I1=$iopadmap$count(10) I2=$iopadmap$count(11) I3=$iopadmap$count(12) O=reset_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.end
diff --git a/BENCHMARK/counter_16bit/rtl/counter_16bit.v b/BENCHMARK/counter_16bit/rtl/counter_16bit.v
new file mode 100644
index 0000000..f3504e0
--- /dev/null
+++ b/BENCHMARK/counter_16bit/rtl/counter_16bit.v
@@ -0,0 +1,21 @@
+//
+// Copyright (c) 2020 QuickLogic Corporation.  All Rights Reserved.
+//
+// Description :
+//    Example of asimple 16 bit up counter in Verilog HDL
+//
+// Version 1.0 : Initial Creation
+//
+module top (clk, reset, enable, count);
+input clk, reset, enable;
+output [15:0] count;
+reg [15:0] count;                                   
+
+always @ (posedge clk)
+if (reset == 1'b1) begin
+  count <= 0;
+end else if ( enable == 1'b1) begin
+  count <= count + 1;
+end
+
+endmodule  
diff --git a/BENCHMARK/dct_mac/dct_mac_yosys.blif b/BENCHMARK/dct_mac/dct_mac_yosys.blif
new file mode 100644
index 0000000..af9f578
--- /dev/null
+++ b/BENCHMARK/dct_mac/dct_mac_yosys.blif
@@ -0,0 +1,3661 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model dct_mac
+.inputs clk ena dclr din(0) din(1) din(2) din(3) din(4) din(5) din(6) din(7) coef(0) coef(1) coef(2) coef(3) coef(4) coef(5) coef(6) coef(7) coef(8) coef(9) coef(10) coef(11) coef(12) coef(13) coef(14) coef(15)
+.outputs result(0) result(1) result(2) result(3) result(4) result(5) result(6) result(7) result(8) result(9) result(10) result(11) result(12) result(13) result(14) result(15) result(16) result(17) result(18) result(19) result(20) result(21) result(22) result(23) result(24) result(25) result(26)
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_0 a=mult_res_ff_CQZ_18_D(10)
+.subckt in_buff A=clk Q=$iopadmap$clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(0) Q=icoef(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(1) Q=icoef(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(10) Q=icoef(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(11) Q=icoef(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(12) Q=icoef(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(13) Q=icoef(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(14) Q=icoef(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(15) Q=icoef(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(2) Q=icoef(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(3) Q=icoef(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(4) Q=icoef(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(5) Q=icoef(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(6) Q=icoef(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(7) Q=icoef(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(8) Q=icoef(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=coef(9) Q=icoef(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dclr Q=$iopadmap$dclr
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(0) Q=idin(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(1) Q=idin(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(2) Q=idin(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(3) Q=idin(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(4) Q=idin(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(5) Q=idin(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(6) Q=idin(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(7) Q=idin(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=ena Q=$iopadmap$ena
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=$iopadmap$result(0) Q=result(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(1) Q=result(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(10) Q=result(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(11) Q=result(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(12) Q=result(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(13) Q=result(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(14) Q=result(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(15) Q=result(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(16) Q=result(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(17) Q=result(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(18) Q=result(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(19) Q=result(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(2) Q=result(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(20) Q=result(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(21) Q=result(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(22) Q=result(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(23) Q=result(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(24) Q=result(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(25) Q=result(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(26) Q=result(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(3) Q=result(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(4) Q=result(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(5) Q=result(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(6) Q=result(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(7) Q=result(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(8) Q=result(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$result(9) Q=result(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_I1 I2=$iopadmap$result(26) I3=ext_mult_res(23) O=result_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_1_I1 I2=$iopadmap$result(25) I3=ext_mult_res(23) O=result_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_10_I1 I2=$iopadmap$result(14) I3=ext_mult_res(14) O=result_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=dclr_LUT4_I0_10_I1 I1=ext_mult_res(14) I2=$iopadmap$result(14) I3=dclr_LUT4_I0_10_I1_LUT4_I0_I3 O=dclr_LUT4_I0_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(15) I3=ext_mult_res(15) O=dclr_LUT4_I0_10_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=ext_mult_res(13) I1=$iopadmap$result(13) I2=dclr_LUT4_I0_11_I1_LUT4_O_I3 I3=dclr_LUT4_I0_11_I1_LUT4_O_I2 O=dclr_LUT4_I0_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_11_I1 I2=$iopadmap$result(13) I3=ext_mult_res(13) O=result_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=dclr_LUT4_I0_11_I1_LUT4_O_I2 I3=dclr_LUT4_I0_11_I1_LUT4_O_I3 O=dclr_LUT4_I0_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(12) I3=ext_mult_res(12) O=dclr_LUT4_I0_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_12_I1 I2=$iopadmap$result(11) I3=ext_mult_res(11) O=result_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=dclr_LUT4_I0_12_I1 I1=ext_mult_res(11) I2=$iopadmap$result(11) I3=dclr_LUT4_I1_2_I3_LUT4_O_I3 O=dclr_LUT4_I0_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=ext_mult_res(10) I1=dclr_LUT4_I0_13_I1_LUT4_O_I2 I2=dclr_LUT4_I0_13_I1_LUT4_O_I3 I3=$iopadmap$result(10) O=dclr_LUT4_I0_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_13_I1 I2=$iopadmap$result(10) I3=ext_mult_res(10) O=result_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=dclr_LUT4_I0_13_I1_LUT4_O_I2 I3=dclr_LUT4_I0_13_I1_LUT4_O_I3 O=dclr_LUT4_I0_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(9) I3=ext_mult_res(9) O=dclr_LUT4_I0_13_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_14_I1 I2=$iopadmap$result(9) I3=ext_mult_res(9) O=result_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=$iopadmap$result(8) I2=ext_mult_res(8) I3=dclr_LUT4_I0_15_I1 O=dclr_LUT4_I0_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_15_I1 I2=$iopadmap$result(8) I3=ext_mult_res(8) O=result_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=dclr_LUT4_I0_15_I1 I1=ext_mult_res(8) I2=$iopadmap$result(8) I3=dclr_LUT4_I0_15_I1_LUT4_I0_I3 O=dclr_LUT4_I0_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(9) I3=ext_mult_res(9) O=dclr_LUT4_I0_15_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=ext_mult_res(7) I1=$iopadmap$result(7) I2=dclr_LUT4_I0_16_I1_LUT4_O_I3 I3=dclr_LUT4_I0_16_I1_LUT4_O_I2 O=dclr_LUT4_I0_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_16_I1 I2=$iopadmap$result(7) I3=ext_mult_res(7) O=result_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=dclr_LUT4_I0_16_I1_LUT4_O_I2 I3=dclr_LUT4_I0_16_I1_LUT4_O_I3 O=dclr_LUT4_I0_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(6) I3=ext_mult_res(6) O=dclr_LUT4_I0_16_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_17_I1 I2=$iopadmap$result(6) I3=ext_mult_res(6) O=result_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=$iopadmap$result(5) I2=ext_mult_res(5) I3=dclr_LUT4_I0_18_I1 O=dclr_LUT4_I0_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_18_I1 I2=$iopadmap$result(5) I3=ext_mult_res(5) O=result_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=dclr_LUT4_I0_18_I1 I1=ext_mult_res(5) I2=$iopadmap$result(5) I3=dclr_LUT4_I0_18_I1_LUT4_I0_I3 O=dclr_LUT4_I0_16_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(6) I3=ext_mult_res(6) O=dclr_LUT4_I0_18_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=ext_mult_res(4) I1=$iopadmap$result(4) I2=dclr_LUT4_I0_19_I1_LUT4_O_I3 I3=dclr_LUT4_I0_19_I1_LUT4_O_I2 O=dclr_LUT4_I0_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_19_I1 I2=$iopadmap$result(4) I3=ext_mult_res(4) O=result_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=dclr_LUT4_I0_19_I1_LUT4_O_I2 I3=dclr_LUT4_I0_19_I1_LUT4_O_I3 O=dclr_LUT4_I0_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(3) I3=ext_mult_res(3) O=dclr_LUT4_I0_19_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=dclr_LUT4_I0_I1_LUT4_O_I3 I2=$iopadmap$result(24) I3=ext_mult_res(23) O=dclr_LUT4_I0_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_2_I1 I2=$iopadmap$result(23) I3=ext_mult_res(23) O=result_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_20_I1 I2=$iopadmap$result(3) I3=ext_mult_res(3) O=result_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=$iopadmap$result(2) I2=ext_mult_res(2) I3=dclr_LUT4_I0_21_I1 O=dclr_LUT4_I0_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_21_I1 I2=$iopadmap$result(2) I3=ext_mult_res(2) O=result_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=dclr_LUT4_I0_21_I1 I1=ext_mult_res(2) I2=$iopadmap$result(2) I3=dclr_LUT4_I0_21_I1_LUT4_I0_I3 O=dclr_LUT4_I0_19_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(3) I3=ext_mult_res(3) O=dclr_LUT4_I0_21_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=ext_mult_res(1) I1=$iopadmap$result(1) I2=$iopadmap$result(0) I3=ext_mult_res(0) O=dclr_LUT4_I0_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_22_I1 I2=$iopadmap$result(1) I3=ext_mult_res(1) O=result_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(0) I3=ext_mult_res(0) O=dclr_LUT4_I0_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dclr_LUT4_I0_2_I1 I1=$iopadmap$result(23) I2=ext_mult_res(23) I3=$iopadmap$result(24) O=dclr_LUT4_I0_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101100101111
+.subckt LUT4 I0=ext_mult_res(22) I1=dclr_LUT4_I0_3_I1_LUT4_O_I2 I2=dclr_LUT4_I0_3_I1_LUT4_O_I3 I3=$iopadmap$result(22) O=dclr_LUT4_I0_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_3_I1 I2=$iopadmap$result(22) I3=ext_mult_res(22) O=result_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=dclr_LUT4_I0_3_I1_LUT4_O_I2 I3=dclr_LUT4_I0_3_I1_LUT4_O_I3 O=dclr_LUT4_I0_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(21) I3=ext_mult_res(21) O=dclr_LUT4_I0_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_4_I1 I2=$iopadmap$result(21) I3=ext_mult_res(21) O=result_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=$iopadmap$result(20) I2=ext_mult_res(20) I3=dclr_LUT4_I0_5_I1 O=dclr_LUT4_I0_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_5_I1 I2=$iopadmap$result(20) I3=ext_mult_res(20) O=result_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=dclr_LUT4_I0_5_I1 I1=ext_mult_res(20) I2=$iopadmap$result(20) I3=dclr_LUT4_I0_5_I1_LUT4_I0_I3 O=dclr_LUT4_I0_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(21) I3=ext_mult_res(21) O=dclr_LUT4_I0_5_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=ext_mult_res(19) I1=$iopadmap$result(19) I2=dclr_LUT4_I0_6_I1_LUT4_O_I3 I3=dclr_LUT4_I0_6_I1_LUT4_O_I2 O=dclr_LUT4_I0_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_6_I1 I2=$iopadmap$result(19) I3=ext_mult_res(19) O=result_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=dclr_LUT4_I0_6_I1_LUT4_O_I2 I3=dclr_LUT4_I0_6_I1_LUT4_O_I3 O=dclr_LUT4_I0_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(18) I3=ext_mult_res(18) O=dclr_LUT4_I0_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_7_I1 I2=$iopadmap$result(17) I3=ext_mult_res(17) O=result_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=dclr_LUT4_I0_7_I1 I1=ext_mult_res(17) I2=$iopadmap$result(17) I3=dclr_LUT4_I1_1_I3_LUT4_O_I3 O=dclr_LUT4_I0_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=ext_mult_res(16) I1=dclr_LUT4_I0_8_I1_LUT4_O_I2 I2=dclr_LUT4_I0_8_I1_LUT4_O_I3 I3=$iopadmap$result(16) O=dclr_LUT4_I0_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_8_I1 I2=$iopadmap$result(16) I3=ext_mult_res(16) O=result_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=dclr_LUT4_I0_8_I1_LUT4_O_I2 I3=dclr_LUT4_I0_8_I1_LUT4_O_I3 O=dclr_LUT4_I0_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(15) I3=ext_mult_res(15) O=dclr_LUT4_I0_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$dclr I1=dclr_LUT4_I0_9_I1 I2=$iopadmap$result(15) I3=ext_mult_res(15) O=result_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=$iopadmap$result(14) I2=ext_mult_res(14) I3=dclr_LUT4_I0_10_I1 O=dclr_LUT4_I0_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$result(24) I1=ext_mult_res(23) I2=$iopadmap$result(25) I3=dclr_LUT4_I0_I1_LUT4_O_I3 O=dclr_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100100011111100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=$iopadmap$dclr I2=ext_mult_res(23) I3=dclr_LUT4_I1_I3 O=result_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=$iopadmap$dclr I2=ext_mult_res(18) I3=dclr_LUT4_I1_1_I3 O=result_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=dclr_LUT4_I0_7_I1 I1=ext_mult_res(17) I2=$iopadmap$result(17) I3=dclr_LUT4_I1_1_I3_LUT4_O_I3 O=dclr_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(18) I3=ext_mult_res(18) O=dclr_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=$iopadmap$dclr I2=ext_mult_res(12) I3=dclr_LUT4_I1_2_I3 O=result_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=dclr_LUT4_I0_12_I1 I1=ext_mult_res(11) I2=$iopadmap$result(11) I3=dclr_LUT4_I1_2_I3_LUT4_O_I3 O=dclr_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=$iopadmap$result(12) I3=ext_mult_res(12) O=dclr_LUT4_I1_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=dclr_LUT4_I0_2_I1 I1=ext_mult_res(23) I2=$iopadmap$result(23) I3=$iopadmap$result(24) O=dclr_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001100011100111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=ext_mult_res(0) I2=$iopadmap$result(0) I3=$iopadmap$dclr O=result_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt ff CQZ=ext_mult_res(23) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(23) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(22) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(22) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(13) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(13) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(12) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(12) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(11) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(11) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(10) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(10) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(9) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(9) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(8) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(8) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(7) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(7) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(6) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(6) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(5) D=mult_res_ff_CQZ_18_D(5) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I3 O=mult_res_ff_CQZ_18_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I3_LUT4_I2_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_16_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_16_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O I3=mult_res_ff_CQZ_18_D_LUT4_O_I3_LUT4_I2_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_11_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_11_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_11_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=idin(2) I3=icoef(8) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=idin(5) I1=icoef(5) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=idin(5) I3=icoef(4) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=idin(2) I2=icoef(8) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=icoef(6) I1=idin(4) I2=icoef(7) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(6) I1=icoef(7) I2=idin(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_11_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_11_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_11_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_11_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_11_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=idin(5) I1=icoef(4) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(3) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=idin(5) I3=icoef(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=idin(2) I3=icoef(7) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=idin(2) I2=icoef(7) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=icoef(5) I1=idin(4) I2=icoef(6) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(5) I1=icoef(6) I2=idin(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_14_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_14_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_14_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=idin(5) I1=icoef(3) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(1) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(2) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=idin(2) I3=icoef(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=idin(2) I2=icoef(6) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=icoef(4) I1=idin(4) I2=icoef(5) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(4) I1=icoef(5) I2=idin(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=icoef(7) I1=icoef(8) I2=idin(0) I3=idin(1) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=idin(2) I3=icoef(5) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=icoef(3) I1=idin(4) I2=icoef(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(2) I3=idin(5) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=idin(6) I1=icoef(1) I2=icoef(0) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=idin(6) I1=icoef(0) I2=idin(5) I3=icoef(1) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=idin(2) I2=icoef(5) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=idin(4) I2=icoef(4) I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=icoef(8) I3=icoef(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=idin(1) I2=idin(0) I3=icoef(7) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_12_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2_LUT4_I0_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_14_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_14_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_14_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_14_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_14_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I1 I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2_LUT4_I0_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=icoef(5) I1=icoef(6) I2=idin(0) I3=idin(1) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I0 I1=icoef(6) I2=icoef(7) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_16_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_16_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_16_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_16_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_2_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_2_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_2_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(14) I1=idin(5) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=idin(5) I3=icoef(13) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_2_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_2_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_2_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=idin(3) I2=idin(2) I3=icoef(15) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(4) I3=icoef(14) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=icoef(15) I1=idin(3) I2=idin(2) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=idin(5) I1=icoef(13) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(11) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(12) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=idin(5) I3=icoef(12) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_5_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_5_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_5_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=idin(2) I3=icoef(14) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=idin(5) I1=icoef(11) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(9) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(10) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=idin(5) I3=icoef(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=icoef(2) I1=icoef(3) I2=icoef(4) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=idin(5) I3=icoef(11) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=idin(5) I1=icoef(12) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(11) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=idin(3) I3=icoef(14) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(2) I3=icoef(15) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=icoef(14) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(4) I3=icoef(13) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_5_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_5_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_5_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=idin(2) I3=icoef(13) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=idin(5) I1=icoef(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(8) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(9) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=idin(5) I3=icoef(9) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=idin(2) I2=icoef(13) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=icoef(11) I1=idin(4) I2=icoef(12) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(11) I1=icoef(12) I2=idin(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=idin(2) I2=icoef(14) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=icoef(12) I1=idin(4) I2=icoef(13) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(12) I1=icoef(13) I2=idin(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=idin(2) I3=icoef(11) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=idin(5) I1=icoef(8) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(7) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=idin(5) I3=icoef(7) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=idin(2) I2=icoef(11) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=icoef(9) I1=idin(4) I2=icoef(10) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(9) I1=icoef(10) I2=idin(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011100010001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(11) I3=icoef(13) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=icoef(14) I1=idin(1) I2=icoef(15) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=icoef(12) I3=icoef(14) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=idin(1) I2=idin(0) I3=icoef(13) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=idin(2) I3=icoef(12) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=idin(5) I1=icoef(9) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(7) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(8) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=idin(5) I3=icoef(8) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=idin(2) I2=icoef(12) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=icoef(10) I1=idin(4) I2=icoef(11) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(10) I1=icoef(11) I2=idin(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=icoef(14) I1=idin(0) I2=idin(1) I3=icoef(15) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_8_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=idin(2) I3=icoef(9) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=idin(5) I1=icoef(6) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(4) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(5) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=idin(5) I3=icoef(5) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(4) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=idin(2) I2=icoef(9) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=icoef(7) I1=idin(4) I2=icoef(8) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(7) I1=icoef(8) I2=idin(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=icoef(8) I1=icoef(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=icoef(10) I1=idin(1) I2=icoef(11) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I0 I2=icoef(6) I3=icoef(7) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=icoef(7) I1=idin(1) I2=icoef(8) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(8) I1=idin(1) I2=icoef(9) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(8) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=icoef(10) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(1) I3=icoef(9) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(8) I3=icoef(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=icoef(10) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=icoef(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=icoef(12) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100001110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=idin(0) I3=icoef(13) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(1) I3=icoef(12) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=icoef(10) I1=icoef(12) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(1) I3=icoef(11) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=idin(2) I3=icoef(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=idin(5) I1=icoef(7) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(5) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(6) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=idin(5) I3=icoef(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=idin(2) I2=icoef(10) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=icoef(8) I1=idin(4) I2=icoef(9) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(8) I1=icoef(9) I2=idin(4) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=icoef(12) I2=icoef(10) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=icoef(11) I1=icoef(13) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=icoef(14) I1=idin(0) I2=icoef(13) I3=idin(1) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_10_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001000011100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=icoef(15) I2=idin(1) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=idin(10) I2=icoef(1) I3=icoef(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(2) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(3) I1=icoef(4) I2=icoef(5) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=icoef(4) I1=icoef(5) I2=icoef(6) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=icoef(3) I1=icoef(4) I2=icoef(5) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=icoef(2) I1=icoef(3) I2=icoef(4) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(0) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=idin(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=icoef(14) I1=icoef(13) I2=icoef(12) I3=icoef(15) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=icoef(15) I1=idin(6) I2=idin(5) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101010101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100110010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=icoef(10) I1=icoef(11) I2=icoef(12) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=icoef(6) I1=icoef(7) I2=icoef(8) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(11) I1=icoef(12) I2=icoef(13) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=icoef(10) I1=icoef(11) I2=icoef(12) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=icoef(7) I1=icoef(8) I2=icoef(9) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(15) I1=idin(6) I2=idin(5) I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(14) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=icoef(13) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=icoef(15) I2=idin(10) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=idin(6) I2=idin(5) I3=icoef(15) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(14) I1=icoef(12) I2=icoef(13) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=icoef(11) I1=icoef(12) I2=icoef(13) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=icoef(8) I1=icoef(9) I2=icoef(10) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100100010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=icoef(7) I1=icoef(8) I2=icoef(9) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(8) I1=icoef(9) I2=icoef(10) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=icoef(5) I1=icoef(6) I2=icoef(7) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=icoef(4) I1=icoef(5) I2=icoef(6) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=icoef(1) I1=icoef(2) I2=icoef(3) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=idin(4) I1=idin(3) I2=idin(2) I3=icoef(15) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=icoef(14) I3=idin(5) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(10) I3=icoef(12) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=icoef(13) I3=idin(6) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=idin(4) I1=idin(3) I2=idin(2) I3=icoef(15) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=idin(10) I3=icoef(13) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(6) I3=icoef(14) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(5) I3=icoef(15) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=icoef(6) I1=icoef(7) I2=icoef(8) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=icoef(1) I1=icoef(2) I2=icoef(3) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=icoef(9) I1=icoef(10) I2=icoef(11) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(9) I1=icoef(10) I2=icoef(11) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=icoef(5) I1=icoef(6) I2=icoef(7) I3=idin(10) O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100011101110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010000001011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I2 I1=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_1_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_19_D_LUT4_O_I2 I2=mult_res_ff_CQZ_19_D_LUT4_O_I3 I3=mult_res_ff_CQZ_19_D_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0 I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I2 I1=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I3 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=icoef(4) I1=idin(1) I2=icoef(5) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2 I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I0 I2=icoef(4) I3=icoef(5) O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=icoef(5) I1=idin(1) I2=icoef(6) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(6) I1=idin(1) I2=icoef(7) I3=idin(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=icoef(4) I1=icoef(6) I2=icoef(5) I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=icoef(3) I1=icoef(4) I2=idin(0) I3=idin(1) O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I3 I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_1_O I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I3=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_1_O I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I2=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I3 I2=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I1 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2 I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_1_O O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(5) I3=icoef(0) O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(2) I3=icoef(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=icoef(1) I1=idin(4) I2=icoef(2) I3=idin(3) O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3 I1=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=icoef(2) I3=idin(2) O=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_18_D_LUT4_O_I3 I3=mult_res_ff_CQZ_18_D_LUT4_O_I2 O=mult_res_ff_CQZ_18_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_19_D_LUT4_O_I3 I2=mult_res_ff_CQZ_19_D_LUT4_O_I1 I3=mult_res_ff_CQZ_19_D_LUT4_O_I0 O=mult_res_ff_CQZ_18_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt ff CQZ=ext_mult_res(4) D=mult_res_ff_CQZ_18_D(4) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=mult_res_ff_CQZ_19_D_LUT4_O_I0 I1=mult_res_ff_CQZ_19_D_LUT4_O_I1 I2=mult_res_ff_CQZ_19_D_LUT4_O_I2 I3=mult_res_ff_CQZ_19_D_LUT4_O_I3 O=mult_res_ff_CQZ_18_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I1 I2=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I2 I3=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_19_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(2) I1=idin(2) I2=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3 I3=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(4) I3=icoef(0) O=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2 I2=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I1_LUT4_O_I2 O=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=icoef(2) I1=icoef(3) I2=idin(0) I3=idin(1) O=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I3 I2=mult_res_ff_CQZ_20_D_LUT4_O_I1 I3=mult_res_ff_CQZ_20_D_LUT4_O_I2 O=mult_res_ff_CQZ_19_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=mult_res_ff_CQZ_20_D_LUT4_O_I1 I1=mult_res_ff_CQZ_20_D_LUT4_O_I2 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3 I3=mult_res_ff_CQZ_20_D_LUT4_O_I0 O=mult_res_ff_CQZ_19_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=idin(2) I2=icoef(0) I3=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_19_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I3=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3 O=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(4) I3=icoef(2) O=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110111111010100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(3) I3=icoef(1) O=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=ext_mult_res(21) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(21) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(3) D=mult_res_ff_CQZ_18_D(3) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=mult_res_ff_CQZ_20_D_LUT4_O_I0 I1=mult_res_ff_CQZ_20_D_LUT4_O_I1 I2=mult_res_ff_CQZ_20_D_LUT4_O_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3 O=mult_res_ff_CQZ_18_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_res_ff_CQZ_21_D_LUT4_O_I2 I1=mult_res_ff_CQZ_21_D_LUT4_O_I3 I2=icoef(0) I3=idin(2) O=mult_res_ff_CQZ_20_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_20_D_LUT4_O_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_21_D_LUT4_O_I2 O=mult_res_ff_CQZ_20_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=icoef(1) I1=icoef(2) I2=idin(0) I3=idin(1) O=mult_res_ff_CQZ_20_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=icoef(0) I1=idin(3) I2=icoef(1) I3=idin(2) O=mult_res_ff_CQZ_20_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I1_LUT4_O_I2 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3 O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2 O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_I3 O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_I3 O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I0 I1=icoef(4) I2=icoef(5) I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2 O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(1) I3=idin(0) O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I3_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I3_I1 I2=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I1_O O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=icoef(3) I1=idin(1) I2=icoef(4) I3=idin(0) O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O I3=mult_res_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(3) I3=icoef(3) O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=idin(6) I1=icoef(0) I2=idin(5) I3=icoef(1) O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(2) I3=icoef(4) O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O_LUT4_I3_I1 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O_LUT4_I3_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_15_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O_LUT4_I3_I1 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O_LUT4_I3_I2 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O O=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O_LUT4_O_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I1=mult_res_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1 I3=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=mult_res_ff_CQZ_20_D_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100001000101011
+.subckt LUT4 I0=icoef(2) I1=idin(1) I2=icoef(3) I3=idin(0) O=mult_res_ff_CQZ_20_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt ff CQZ=ext_mult_res(2) D=mult_res_ff_CQZ_18_D(2) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=icoef(0) I1=idin(2) I2=mult_res_ff_CQZ_21_D_LUT4_O_I2 I3=mult_res_ff_CQZ_21_D_LUT4_O_I3 O=mult_res_ff_CQZ_18_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=icoef(0) I1=icoef(1) I2=idin(0) I3=idin(1) O=mult_res_ff_CQZ_21_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_21_D_LUT4_O_I2 I2=mult_res_ff_CQZ_20_D_LUT4_O_I3 I3=mult_res_ff_CQZ_21_D_LUT4_O_I3 O=mult_res_ff_CQZ_19_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=icoef(1) I1=idin(1) I2=icoef(2) I3=idin(0) O=mult_res_ff_CQZ_21_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt ff CQZ=ext_mult_res(1) D=mult_res_ff_CQZ_18_D(1) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=icoef(0) I1=idin(1) I2=icoef(1) I3=idin(0) O=mult_res_ff_CQZ_18_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010001000
+.subckt ff CQZ=ext_mult_res(0) D=mult_res_ff_CQZ_18_D(0) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=mult_res_ff_CQZ_18_D(10) I1=mult_res_ff_CQZ_18_D(10) I2=idin(0) I3=icoef(0) O=mult_res_ff_CQZ_18_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=ext_mult_res(20) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(20) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(19) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(19) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(18) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(18) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(17) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(17) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(16) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(16) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(15) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(15) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=ext_mult_res(14) D=mult_res_ff_CQZ_18_D_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O(14) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:98.2-100.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(26) D=result_ff_CQZ_D(26) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(25) D=result_ff_CQZ_D(25) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(16) D=result_ff_CQZ_D(16) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(15) D=result_ff_CQZ_D(15) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(14) D=result_ff_CQZ_D(14) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(13) D=result_ff_CQZ_D(13) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(12) D=result_ff_CQZ_D(12) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(11) D=result_ff_CQZ_D(11) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(10) D=result_ff_CQZ_D(10) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(9) D=result_ff_CQZ_D(9) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(8) D=result_ff_CQZ_D(8) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(7) D=result_ff_CQZ_D(7) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(24) D=result_ff_CQZ_D(24) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(6) D=result_ff_CQZ_D(6) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(5) D=result_ff_CQZ_D(5) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(4) D=result_ff_CQZ_D(4) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(3) D=result_ff_CQZ_D(3) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(2) D=result_ff_CQZ_D(2) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(1) D=result_ff_CQZ_D(1) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(0) D=result_ff_CQZ_D(0) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(23) D=result_ff_CQZ_D(23) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(22) D=result_ff_CQZ_D(22) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(21) D=result_ff_CQZ_D(21) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(20) D=result_ff_CQZ_D(20) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(19) D=result_ff_CQZ_D(19) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(18) D=result_ff_CQZ_D(18) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$result(17) D=result_ff_CQZ_D(17) QCK=$iopadmap$clk QEN=$iopadmap$ena QRT=mult_res_ff_CQZ_18_D(10) QST=mult_res_ff_CQZ_18_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/dct_mac/rtl/dct_mac.v:105.2-110.43|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.end
diff --git a/BENCHMARK/dct_mac/rtl/dct.v b/BENCHMARK/dct_mac/rtl/dct.v
new file mode 100644
index 0000000..62b3070
--- /dev/null
+++ b/BENCHMARK/dct_mac/rtl/dct.v
@@ -0,0 +1,311 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Discrete Cosine Transform, Parallel implementation         ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: dct.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
+//
+//  $Date: 2002-10-31 12:50:03 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.2  2002/10/23 09:06:59  rherveille
+//               Improved many files.
+//               Fixed some bugs in Run-Length-Encoder.
+//               Removed dependency on ud_cnt and ro_cnt.
+//               Started (Motion)JPEG hardware encoder project.
+//
+
+//synopsys translate_off
+`include "timescale.v"
+//synopsys translate_on
+
+module dct(
+	clk,
+	ena,
+	rst,
+	dstrb,
+	din,
+	dout_00, dout_01, dout_02, dout_03, dout_04, dout_05, dout_06, dout_07,
+	dout_10, dout_11, dout_12, dout_13, dout_14, dout_15, dout_16, dout_17,
+	dout_20, dout_21, dout_22, dout_23, dout_24, dout_25, dout_26, dout_27,
+	dout_30, dout_31, dout_32, dout_33, dout_34, dout_35, dout_36, dout_37,
+	dout_40, dout_41, dout_42, dout_43, dout_44, dout_45, dout_46, dout_47,
+	dout_50, dout_51, dout_52, dout_53, dout_54, dout_55, dout_56, dout_57,
+	dout_60, dout_61, dout_62, dout_63, dout_64, dout_65, dout_66, dout_67,
+	dout_70, dout_71, dout_72, dout_73, dout_74, dout_75, dout_76, dout_77,
+	douten
+);
+
+	//
+	// parameters
+	//
+	// Worst case errors (Din = 64* -128) remain in decimal bit
+	// when using 13bit coefficients
+	//
+	// For ultra-high
+	parameter coef_width = 11;
+	parameter di_width = 8;
+	parameter do_width = 12;
+
+	//
+	// inputs & outputs
+	//
+
+	input clk;
+	input ena;
+	input rst;   // active low asynchronous reset
+
+	input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
+	input  [di_width:1] din;
+	output [do_width:1]
+		dout_00, dout_01, dout_02, dout_03, dout_04, dout_05, dout_06, dout_07,
+		dout_10, dout_11, dout_12, dout_13, dout_14, dout_15, dout_16, dout_17,
+		dout_20, dout_21, dout_22, dout_23, dout_24, dout_25, dout_26, dout_27,
+		dout_30, dout_31, dout_32, dout_33, dout_34, dout_35, dout_36, dout_37,
+		dout_40, dout_41, dout_42, dout_43, dout_44, dout_45, dout_46, dout_47,
+		dout_50, dout_51, dout_52, dout_53, dout_54, dout_55, dout_56, dout_57,
+		dout_60, dout_61, dout_62, dout_63, dout_64, dout_65, dout_66, dout_67,
+		dout_70, dout_71, dout_72, dout_73, dout_74, dout_75, dout_76, dout_77;
+
+	output douten; // data-out enable
+	reg douten;
+
+	//
+	// variables
+	//
+	reg go, dgo, ddgo, ddcnt, dddcnt;
+	reg [di_width:1] ddin;
+
+	//
+	// module body
+	//
+
+	// generate sample counter
+	reg  [5:0] sample_cnt;
+	wire       dcnt     = &sample_cnt;
+
+	always @(posedge clk or negedge rst)
+	  if (~rst)
+	     sample_cnt <= #1 6'h0;
+	  else if (ena)
+	    if(dstrb)
+	      sample_cnt <= #1 6'h0;
+	    else if(~dcnt)
+	      sample_cnt <= #1 sample_cnt + 6'h1;
+
+	// internal signals
+	always @(posedge clk or negedge rst)
+	  if (~rst)
+	  begin
+	      go     <= #1 1'b0;
+		  dgo    <= #1 1'b0;
+		  ddgo   <= #1 1'b0;
+		  ddin   <= #1 0;
+
+	      douten <= #1 1'b0;
+	      ddcnt  <= #1 1'b1;
+	      dddcnt <= #1 1'b1;
+	  end
+	  else if (ena)
+	  begin
+	      go     <= #1 dstrb;
+	      dgo    <= #1 go;
+	      ddgo   <= #1 dgo;
+	      ddin   <= #1 din;
+
+	      ddcnt  <= #1 dcnt;
+	      dddcnt <= #1 ddcnt;
+
+	      douten <= #1 ddcnt & ~dddcnt;
+	  end
+
+	// Hookup DCT units
+
+	// V = 0
+	dctub #(coef_width, di_width, 3'h0)
+	dct_block_0 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(sample_cnt[2:0]),
+		.y(sample_cnt[5:3]),
+		.ddin(ddin),
+		.dout0(dout_00), // (U,V) = (0,0)
+		.dout1(dout_01), // (U,V) = (0,1)
+		.dout2(dout_02), // (U,V) = (0,2)
+		.dout3(dout_03), // (U,V) = (0,3)
+		.dout4(dout_04), // (U,V) = (0,4)
+		.dout5(dout_05), // (U,V) = (0,5)
+		.dout6(dout_06), // (U,V) = (0,6)
+		.dout7(dout_07)  // (U,V) = (0,7)
+	);
+
+	// V = 1
+	dctub #(coef_width, di_width, 3'h1)
+	dct_block_1 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(sample_cnt[2:0]),
+		.y(sample_cnt[5:3]),
+		.ddin(ddin),
+		.dout0(dout_10), // (U,V) = (1,0)
+		.dout1(dout_11), // (U,V) = (1,1)
+		.dout2(dout_12), // (U,V) = (1,2)
+		.dout3(dout_13), // (U,V) = (1,3)
+		.dout4(dout_14), // (U,V) = (1,4)
+		.dout5(dout_15), // (U,V) = (1,5)
+		.dout6(dout_16), // (U,V) = (1,6)
+		.dout7(dout_17)  // (U,V) = (1,7)
+	);
+
+	// V = 2
+	dctub #(coef_width, di_width, 3'h2)
+	dct_block_2 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(sample_cnt[2:0]),
+		.y(sample_cnt[5:3]),
+		.ddin(ddin),
+		.dout0(dout_20), // (U,V) = (2,0)
+		.dout1(dout_21), // (U,V) = (2,1)
+		.dout2(dout_22), // (U,V) = (2,2)
+		.dout3(dout_23), // (U,V) = (2,3)
+		.dout4(dout_24), // (U,V) = (2,4)
+		.dout5(dout_25), // (U,V) = (2,5)
+		.dout6(dout_26), // (U,V) = (2,6)
+		.dout7(dout_27)  // (U,V) = (2,7)
+	);
+
+	// V = 3
+	dctub #(coef_width, di_width, 3'h3)
+	dct_block_3 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(sample_cnt[2:0]),
+		.y(sample_cnt[5:3]),
+		.ddin(ddin),
+		.dout0(dout_30), // (U,V) = (3,0)
+		.dout1(dout_31), // (U,V) = (3,1)
+		.dout2(dout_32), // (U,V) = (3,2)
+		.dout3(dout_33), // (U,V) = (3,3)
+		.dout4(dout_34), // (U,V) = (3,4)
+		.dout5(dout_35), // (U,V) = (3,5)
+		.dout6(dout_36), // (U,V) = (3,6)
+		.dout7(dout_37)  // (U,V) = (3,7)
+	);
+
+	// V = 4
+	dctub #(coef_width, di_width, 3'h4)
+	dct_block_4 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(sample_cnt[2:0]),
+		.y(sample_cnt[5:3]),
+		.ddin(ddin),
+		.dout0(dout_40), // (U,V) = (4,0)
+		.dout1(dout_41), // (U,V) = (4,1)
+		.dout2(dout_42), // (U,V) = (4,2)
+		.dout3(dout_43), // (U,V) = (4,3)
+		.dout4(dout_44), // (U,V) = (4,4)
+		.dout5(dout_45), // (U,V) = (4,5)
+		.dout6(dout_46), // (U,V) = (4,6)
+		.dout7(dout_47)  // (U,V) = (4,7)
+	);
+
+	// V = 5
+	dctub #(coef_width, di_width, 3'h5)
+	dct_block_5 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(sample_cnt[2:0]),
+		.y(sample_cnt[5:3]),
+		.ddin(ddin),
+		.dout0(dout_50), // (U,V) = (5,0)
+		.dout1(dout_51), // (U,V) = (5,1)
+		.dout2(dout_52), // (U,V) = (5,2)
+		.dout3(dout_53), // (U,V) = (5,3)
+		.dout4(dout_54), // (U,V) = (5,4)
+		.dout5(dout_55), // (U,V) = (5,5)
+		.dout6(dout_56), // (U,V) = (5,6)
+		.dout7(dout_57)  // (U,V) = (5,7)
+	);
+
+	// V = 6
+	dctub #(coef_width, di_width, 3'h6)
+	dct_block_6 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(sample_cnt[2:0]),
+		.y(sample_cnt[5:3]),
+		.ddin(ddin),
+		.dout0(dout_60), // (U,V) = (6,0)
+		.dout1(dout_61), // (U,V) = (6,1)
+		.dout2(dout_62), // (U,V) = (6,2)
+		.dout3(dout_63), // (U,V) = (6,3)
+		.dout4(dout_64), // (U,V) = (6,4)
+		.dout5(dout_65), // (U,V) = (6,5)
+		.dout6(dout_66), // (U,V) = (6,6)
+		.dout7(dout_67)  // (U,V) = (6,7)
+	);
+
+	// V = 7
+	dctub #(coef_width, di_width, 3'h7)
+	dct_block_7 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(sample_cnt[2:0]),
+		.y(sample_cnt[5:3]),
+		.ddin(ddin),
+		.dout0(dout_70), // (U,V) = (7,0)
+		.dout1(dout_71), // (U,V) = (7,1)
+		.dout2(dout_72), // (U,V) = (7,2)
+		.dout3(dout_73), // (U,V) = (7,3)
+		.dout4(dout_74), // (U,V) = (7,4)
+		.dout5(dout_75), // (U,V) = (7,5)
+		.dout6(dout_76), // (U,V) = (7,6)
+		.dout7(dout_77)  // (U,V) = (7,7)
+	);
+endmodule
diff --git a/BENCHMARK/dct_mac/rtl/dct_cos_table.v b/BENCHMARK/dct_mac/rtl/dct_cos_table.v
new file mode 100644
index 0000000..a188edf
--- /dev/null
+++ b/BENCHMARK/dct_mac/rtl/dct_cos_table.v
@@ -0,0 +1,4362 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Discrete Cosine Transform, cosine table                    ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: dct_cos_table.v,v 1.2 2002-10-23 09:06:59 rherveille Exp $
+//
+//  $Date: 2002-10-23 09:06:59 $
+//  $Revision: 1.2 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+
+
+function [31:0] dct_cos_table;
+
+	//
+	// inputs & outputs
+	//
+	input [2:0] x,y,u,v; // table entry
+
+begin
+	//
+	// Table definition
+	//
+	// Function: cos( (2x +1) * u * pi)/16) * cos( (2y +1) * v * pi)/16)
+	//
+	// select bits:
+	// 11:9 - V
+	//  8:6 - U
+	//  5:3 - Y
+	//  2:0 - X
+
+	case ( {v,u} ) // synopsys full_case parallel_case
+		6'h00:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h01: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h02: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h03: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h04: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h05: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h06: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h07: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h08: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h09: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0a: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0d: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0e: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0f: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h10: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h11: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h12: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h13: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h14: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h15: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h16: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h17: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h18: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h19: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1a: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1d: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1e: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1f: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h20: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h21: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h22: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h23: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h24: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h25: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h26: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h27: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h28: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h29: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2a: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2d: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2e: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2f: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h30: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h31: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h32: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h33: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h34: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h35: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h36: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h37: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h38: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h39: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3a: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3d: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3e: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3f: dct_cos_table = 32'h20000000; // = +0.500000
+			endcase
+		6'h01:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h01: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h02: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h03: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h04: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h05: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h06: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h07: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h08: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h09: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0b: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h10: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h11: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h12: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h13: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h14: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h15: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h16: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h17: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h18: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h19: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1b: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h20: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h21: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h22: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h23: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h24: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h25: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h26: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h27: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h28: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h29: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2b: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h30: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h31: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h32: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h33: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h34: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h35: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h36: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h37: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h38: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h39: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3b: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+			endcase
+		6'h02:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h01: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h02: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h03: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h04: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h05: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h06: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h07: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h08: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h09: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h10: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h11: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h12: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h13: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h14: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h15: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h16: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h17: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h18: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h19: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h1a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h1f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h20: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h21: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h22: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h23: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h24: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h25: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h26: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h27: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h28: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h29: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h30: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h31: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h32: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h33: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h34: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h35: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h36: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h37: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h38: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h39: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+			endcase
+		6'h03:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h01: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h02: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h03: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h04: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h05: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h06: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h07: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h08: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h09: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0c: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h10: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h11: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h12: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h13: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h14: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h15: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h16: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h17: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h18: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h19: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1c: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h20: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h21: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h22: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h23: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h24: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h25: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h26: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h27: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h28: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h29: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2c: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h30: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h31: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h32: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h33: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h34: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h35: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h36: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h37: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h38: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h39: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3c: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+			endcase
+		6'h04:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h01: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h02: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h03: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h04: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h05: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h06: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h07: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h08: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h09: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0a: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0d: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0e: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0f: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h10: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h11: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h12: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h13: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h14: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h15: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h16: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h17: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h18: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h19: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h1a: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h1b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1d: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h1e: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h1f: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h20: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h21: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h22: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h23: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h24: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h25: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h26: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h27: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h28: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h29: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2a: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2d: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2e: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2f: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h30: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h31: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h32: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h33: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h34: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h35: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h36: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h37: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h38: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h39: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h3a: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h3b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3d: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h3e: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h3f: dct_cos_table = 32'h20000000; // = +0.500000
+			endcase
+		6'h05:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h01: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h02: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h03: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h04: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h05: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h06: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h07: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h08: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h09: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h10: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h11: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h12: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h13: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h14: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h15: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h16: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h17: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h18: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h19: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h20: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h21: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h22: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h23: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h24: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h25: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h26: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h27: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h28: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h29: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h30: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h31: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h32: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h33: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h34: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h35: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h36: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h37: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h38: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h39: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3f: dct_cos_table = 32'he6db9640; // = -0.392847
+			endcase
+		6'h06:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h01: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h02: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h03: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h04: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h05: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h06: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h07: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h08: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h09: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0f: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h10: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h11: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h12: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h13: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h14: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h15: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h16: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h17: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h18: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h19: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h1b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h1e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1f: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h20: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h21: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h22: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h23: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h24: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h25: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h26: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h27: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h28: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h29: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2f: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h30: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h31: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h32: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h33: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h34: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h35: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h36: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h37: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h38: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h39: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3f: dct_cos_table = 32'h11517a7b; // = +0.270598
+			endcase
+		6'h07:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h01: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h02: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h03: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h04: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h05: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h06: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h07: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h08: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h09: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0c: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0f: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h10: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h11: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h12: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h13: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h14: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h15: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h16: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h17: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h18: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h19: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1c: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1f: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h20: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h21: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h22: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h23: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h24: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h25: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h26: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h27: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h28: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h29: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2c: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2f: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h30: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h31: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h32: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h33: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h34: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h35: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h36: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h37: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h38: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h39: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3c: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3f: dct_cos_table = 32'hf72bd511; // = -0.137950
+			endcase
+		6'h08:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h01: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h02: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h03: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h04: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h05: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h06: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h07: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h08: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h09: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0c: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0d: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0e: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0f: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h10: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h11: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h12: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h13: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h14: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h15: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h16: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h17: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h18: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h19: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1b: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1c: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1d: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1f: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h20: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h21: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h22: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h23: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h24: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h25: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h26: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h27: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h28: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h29: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2a: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2e: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h30: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h31: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h32: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h33: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h34: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h35: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h36: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h37: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h38: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h39: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3c: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3d: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3e: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+			endcase
+		6'h09:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h01: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h02: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h03: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h04: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h05: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h06: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h07: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h08: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h09: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h0a: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h0b: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h0c: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h0d: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h0e: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h0f: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h10: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h11: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h12: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h13: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h14: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h15: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h16: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h17: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h18: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h19: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h1a: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h1b: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h1c: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h1d: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h1e: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h1f: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h20: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h21: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h22: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h23: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h24: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h25: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h26: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h27: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h28: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h29: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h2a: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h2b: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h2c: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h2d: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h2e: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h2f: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h30: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h31: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h32: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h33: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h34: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h35: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h36: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h37: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h38: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h39: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h3a: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h3b: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h3c: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h3d: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h3e: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h3f: dct_cos_table = 32'h3d906bcf; // = +0.961940
+			endcase
+		6'h0a:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h01: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h02: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h03: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h04: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h05: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h06: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h07: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h08: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h09: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h0a: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h0b: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h0c: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h0d: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h0e: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h0f: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h10: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h11: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h12: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h13: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h14: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h15: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h16: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h17: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h18: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h19: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h1a: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h1b: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h1c: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h1d: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h1e: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h1f: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h20: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h21: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h22: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h23: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h24: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h25: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h26: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h27: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h28: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h29: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h2a: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h2b: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h2c: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h2d: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h2e: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h2f: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h30: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h31: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h32: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h33: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h34: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h35: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h36: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h37: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h38: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h39: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h3a: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h3b: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h3c: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h3d: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h3e: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h3f: dct_cos_table = 32'hc6020207; // = -0.906127
+			endcase
+		6'h0b:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h01: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h02: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h03: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h04: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h05: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h06: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h07: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h08: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h09: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h0a: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h0b: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h0c: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h0d: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h0e: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h0f: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h10: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h11: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h12: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h13: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h14: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h15: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h16: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h17: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h18: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h19: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h1a: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h1b: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h1c: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h1d: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h1e: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h1f: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h20: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h21: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h22: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h23: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h24: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h25: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h26: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h27: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h28: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h29: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h2a: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h2b: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h2c: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h2d: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h2e: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h2f: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h30: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h31: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h32: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h33: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h34: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h35: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h36: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h37: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h38: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h39: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h3a: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h3b: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h3c: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h3d: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h3e: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h3f: dct_cos_table = 32'h34310a35; // = +0.815493
+			endcase
+		6'h0c:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h01: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h02: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h03: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h04: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h05: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h06: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h07: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h08: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h09: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0a: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0c: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0f: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h10: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h11: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h12: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h13: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h14: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h15: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h16: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h17: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h18: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h19: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1a: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1b: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1c: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1e: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1f: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h20: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h21: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h22: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h23: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h24: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h25: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h26: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h27: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h28: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h29: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2d: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h30: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h31: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h32: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h33: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h34: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h35: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h36: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h37: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h38: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h39: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3a: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3c: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+			endcase
+		6'h0d:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h01: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h02: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h03: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h04: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h05: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h06: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h07: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h08: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h09: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h0a: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h0b: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h0c: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h0d: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h0e: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h0f: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h10: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h11: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h12: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h13: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h14: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h15: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h16: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h17: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h18: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h19: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h1a: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h1b: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h1c: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h1d: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h1e: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h1f: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h20: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h21: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h22: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h23: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h24: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h25: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h26: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h27: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h28: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h29: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h2a: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h2b: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h2c: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h2d: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h2e: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h2f: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h30: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h31: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h32: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h33: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h34: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h35: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h36: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h37: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h38: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h39: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h3a: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h3b: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h3c: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h3d: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h3e: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h3f: dct_cos_table = 32'h22df8fb9; // = +0.544895
+			endcase
+		6'h0e:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h01: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h02: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h03: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h04: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h05: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h06: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h07: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h08: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h09: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h0a: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h0b: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h0c: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h0d: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h0e: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h0f: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h10: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h11: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h12: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h13: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h14: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h15: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h16: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h17: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h18: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h19: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h1a: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h1b: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h1c: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h1d: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h1e: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h1f: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h20: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h21: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h22: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h23: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h24: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h25: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h26: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h27: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h28: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h29: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h2a: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h2b: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h2c: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h2d: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h2e: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h2f: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h30: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h31: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h32: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h33: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h34: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h35: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h36: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h37: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h38: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h39: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h3a: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h3b: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h3c: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h3d: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h3e: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h3f: dct_cos_table = 32'he7fa96b8; // = -0.375330
+			endcase
+		6'h0f:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h01: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h02: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h03: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h04: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h05: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h06: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h07: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h08: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h09: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h0a: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h0b: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h0c: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h0d: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h0e: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h0f: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h10: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h11: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h12: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h13: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h14: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h15: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h16: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h17: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h18: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h19: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h1a: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h1b: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h1c: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h1d: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h1e: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h1f: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h20: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h21: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h22: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h23: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h24: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h25: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h26: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h27: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h28: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h29: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h2a: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h2b: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h2c: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h2d: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h2e: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h2f: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h30: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h31: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h32: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h33: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h34: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h35: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h36: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h37: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h38: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h39: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h3a: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h3b: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h3c: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h3d: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h3e: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h3f: dct_cos_table = 32'h0c3ef153; // = +0.191342
+			endcase
+		6'h10:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h01: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h02: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h03: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h04: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h05: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h06: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h07: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h08: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h09: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0a: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0b: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0c: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0d: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0f: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h10: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h11: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h12: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h13: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h14: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h15: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h16: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h17: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h18: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h19: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1a: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1d: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1f: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h20: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h21: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h22: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h23: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h24: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h25: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h26: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h27: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h28: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h29: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2e: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2f: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h30: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h31: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h32: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h33: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h34: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h35: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h36: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h37: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h38: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h39: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3b: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3c: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3e: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+			endcase
+		6'h11:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h01: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h02: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h03: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h04: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h05: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h06: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h07: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h08: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h09: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h0a: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h0b: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h0c: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h0d: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h0e: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h0f: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h10: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h11: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h12: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h13: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h14: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h15: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h16: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h17: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h18: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h19: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h1a: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h1b: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h1c: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h1d: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h1e: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h1f: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h20: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h21: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h22: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h23: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h24: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h25: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h26: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h27: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h28: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h29: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h2a: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h2b: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h2c: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h2d: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h2e: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h2f: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h30: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h31: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h32: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h33: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h34: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h35: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h36: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h37: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h38: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h39: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h3a: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h3b: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h3c: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h3d: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h3e: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h3f: dct_cos_table = 32'hc6020207; // = -0.906127
+			endcase
+		6'h12:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h01: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h02: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h03: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h04: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h05: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h06: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h07: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h08: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h09: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h0a: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h0b: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h0c: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h0d: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h0e: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h0f: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h10: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h11: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h12: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h13: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h14: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h15: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h16: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h17: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h18: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h19: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h1a: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h1b: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h1c: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h1d: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h1e: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h1f: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h20: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h21: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h22: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h23: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h24: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h25: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h26: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h27: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h28: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h29: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h2a: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h2b: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h2c: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h2d: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h2e: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h2f: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h30: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h31: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h32: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h33: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h34: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h35: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h36: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h37: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h38: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h39: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h3a: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h3b: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h3c: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h3d: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h3e: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h3f: dct_cos_table = 32'h36a09e66; // = +0.853553
+			endcase
+		6'h13:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h01: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h02: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h03: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h04: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h05: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h06: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h07: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h08: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h09: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h0a: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h0b: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h0c: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h0d: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h0e: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h0f: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h10: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h11: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h12: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h13: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h14: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h15: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h16: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h17: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h18: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h19: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h1a: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h1b: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h1c: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h1d: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h1e: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h1f: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h20: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h21: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h22: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h23: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h24: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h25: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h26: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h27: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h28: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h29: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h2a: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h2b: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h2c: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h2d: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h2e: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h2f: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h30: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h31: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h32: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h33: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h34: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h35: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h36: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h37: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h38: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h39: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h3a: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h3b: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h3c: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h3d: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h3e: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h3f: dct_cos_table = 32'hced62cf7; // = -0.768178
+			endcase
+		6'h14:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h01: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h02: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h03: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h04: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h05: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h06: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h07: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h08: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h09: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0b: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0c: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0e: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0f: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h10: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h11: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h12: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h13: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h14: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h15: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h16: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h17: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h18: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h19: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h1a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h1b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h1e: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h1f: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h20: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h21: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h22: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h23: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h24: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h25: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h26: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h27: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h28: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h29: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2a: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2d: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2f: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h30: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h31: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h32: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h33: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h34: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h35: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h36: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h37: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h38: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h39: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3a: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3b: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3c: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3d: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+			endcase
+		6'h15:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h01: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h02: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h03: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h04: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h05: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h06: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h07: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h08: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h09: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h0a: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h0b: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h0c: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h0d: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h0e: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h0f: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h10: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h11: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h12: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h13: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h14: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h15: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h16: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h17: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h18: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h19: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h1a: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h1b: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h1c: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h1d: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h1e: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h1f: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h20: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h21: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h22: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h23: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h24: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h25: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h26: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h27: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h28: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h29: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h2a: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h2b: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h2c: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h2d: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h2e: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h2f: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h30: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h31: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h32: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h33: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h34: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h35: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h36: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h37: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h38: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h39: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h3a: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h3b: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h3c: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h3d: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h3e: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h3f: dct_cos_table = 32'hdf266bc8; // = -0.513280
+			endcase
+		6'h16:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h01: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h02: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h03: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h04: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h05: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h06: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h07: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h08: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h09: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h0a: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h0b: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h0c: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h0d: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h0e: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h0f: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h10: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h11: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h12: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h13: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h14: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h15: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h16: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h17: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h18: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h19: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h1a: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h1b: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h1c: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h1d: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h1e: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h1f: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h20: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h21: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h22: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h23: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h24: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h25: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h26: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h27: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h28: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h29: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h2a: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h2b: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h2c: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h2d: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h2e: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h2f: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h30: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h31: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h32: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h33: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h34: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h35: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h36: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h37: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h38: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h39: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h3a: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h3b: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h3c: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h3d: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h3e: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h3f: dct_cos_table = 32'h16a09e66; // = +0.353553
+			endcase
+		6'h17:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h01: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h02: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h03: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h04: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h05: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h06: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h07: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h08: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h09: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h0a: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h0b: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h0c: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h0d: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h0e: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h0f: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h10: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h11: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h12: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h13: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h14: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h15: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h16: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h17: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h18: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h19: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h1a: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h1b: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h1c: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h1d: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h1e: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h1f: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h20: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h21: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h22: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h23: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h24: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h25: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h26: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h27: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h28: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h29: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h2a: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h2b: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h2c: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h2d: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h2e: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h2f: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h30: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h31: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h32: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h33: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h34: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h35: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h36: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h37: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h38: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h39: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h3a: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h3b: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h3c: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h3d: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h3e: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h3f: dct_cos_table = 32'hf476f2d6; // = -0.180240
+			endcase
+		6'h18:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h01: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h02: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h03: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h04: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h05: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h06: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h07: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h08: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h09: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0a: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0b: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0e: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0f: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h10: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h11: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h12: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h13: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h14: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h15: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h16: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h17: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h18: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h19: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1a: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1e: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h20: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h21: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h22: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h23: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h24: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h25: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h26: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h27: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h28: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h29: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2a: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2b: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2c: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2f: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h30: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h31: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h32: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h33: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h34: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h35: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h36: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h37: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h38: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h39: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3a: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3b: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+			endcase
+		6'h19:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h01: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h02: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h03: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h04: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h05: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h06: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h07: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h08: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h09: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h0a: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h0b: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h0c: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h0d: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h0e: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h0f: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h10: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h11: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h12: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h13: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h14: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h15: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h16: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h17: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h18: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h19: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h1a: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h1b: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h1c: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h1d: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h1e: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h1f: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h20: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h21: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h22: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h23: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h24: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h25: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h26: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h27: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h28: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h29: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h2a: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h2b: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h2c: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h2d: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h2e: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h2f: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h30: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h31: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h32: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h33: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h34: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h35: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h36: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h37: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h38: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h39: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h3a: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h3b: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h3c: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h3d: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h3e: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h3f: dct_cos_table = 32'h34310a35; // = +0.815493
+			endcase
+		6'h1a:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h01: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h02: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h03: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h04: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h05: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h06: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h07: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h08: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h09: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h0a: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h0b: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h0c: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h0d: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h0e: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h0f: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h10: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h11: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h12: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h13: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h14: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h15: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h16: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h17: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h18: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h19: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h1a: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h1b: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h1c: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h1d: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h1e: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h1f: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h20: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h21: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h22: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h23: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h24: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h25: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h26: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h27: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h28: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h29: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h2a: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h2b: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h2c: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h2d: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h2e: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h2f: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h30: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h31: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h32: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h33: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h34: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h35: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h36: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h37: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h38: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h39: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h3a: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h3b: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h3c: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h3d: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h3e: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h3f: dct_cos_table = 32'hced62cf7; // = -0.768178
+			endcase
+		6'h1b:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h01: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h02: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h03: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h04: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h05: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h06: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h07: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h08: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h09: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h0a: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h0b: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h0c: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h0d: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h0e: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h0f: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h10: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h11: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h12: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h13: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h14: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h15: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h16: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h17: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h18: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h19: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h1a: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h1b: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h1c: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h1d: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h1e: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h1f: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h20: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h21: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h22: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h23: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h24: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h25: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h26: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h27: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h28: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h29: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h2a: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h2b: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h2c: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h2d: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h2e: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h2f: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h30: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h31: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h32: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h33: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h34: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h35: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h36: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h37: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h38: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h39: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h3a: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h3b: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h3c: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h3d: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h3e: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h3f: dct_cos_table = 32'h2c3ef153; // = +0.691342
+			endcase
+		6'h1c:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h01: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h02: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h03: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h04: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h05: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h06: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h07: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h08: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h09: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0b: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0d: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0f: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h10: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h11: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h12: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h13: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h14: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h15: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h16: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h17: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h18: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h19: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1d: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h20: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h21: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h22: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h23: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h24: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h25: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h26: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h27: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h28: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h29: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2b: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2c: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2d: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2e: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2f: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h30: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h31: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h32: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h33: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h34: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h35: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h36: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h37: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h38: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h39: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3b: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3d: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3e: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+			endcase
+		6'h1d:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h01: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h02: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h03: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h04: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h05: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h06: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h07: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h08: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h09: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h0a: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h0b: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h0c: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h0d: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h0e: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h0f: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h10: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h11: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h12: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h13: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h14: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h15: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h16: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h17: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h18: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h19: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h1a: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h1b: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h1c: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h1d: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h1e: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h1f: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h20: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h21: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h22: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h23: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h24: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h25: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h26: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h27: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h28: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h29: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h2a: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h2b: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h2c: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h2d: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h2e: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h2f: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h30: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h31: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h32: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h33: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h34: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h35: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h36: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h37: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h38: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h39: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h3a: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h3b: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h3c: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h3d: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h3e: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h3f: dct_cos_table = 32'h1d906bcf; // = +0.461940
+			endcase
+		6'h1e:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h01: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h02: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h03: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h04: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h05: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h06: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h07: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h08: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h09: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h0a: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h0b: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h0c: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h0d: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h0e: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h0f: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h10: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h11: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h12: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h13: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h14: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h15: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h16: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h17: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h18: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h19: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h1a: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h1b: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h1c: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h1d: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h1e: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h1f: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h20: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h21: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h22: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h23: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h24: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h25: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h26: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h27: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h28: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h29: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h2a: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h2b: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h2c: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h2d: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h2e: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h2f: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h30: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h31: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h32: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h33: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h34: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h35: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h36: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h37: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h38: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h39: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h3a: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h3b: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h3c: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h3d: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h3e: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h3f: dct_cos_table = 32'heba2c7e7; // = -0.318190
+			endcase
+		6'h1f:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h01: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h02: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h03: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h04: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h05: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h06: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h07: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h08: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h09: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h0a: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h0b: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h0c: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h0d: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h0e: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h0f: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h10: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h11: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h12: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h13: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h14: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h15: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h16: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h17: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h18: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h19: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h1a: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h1b: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h1c: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h1d: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h1e: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h1f: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h20: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h21: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h22: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h23: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h24: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h25: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h26: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h27: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h28: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h29: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h2a: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h2b: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h2c: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h2d: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h2e: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h2f: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h30: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h31: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h32: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h33: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h34: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h35: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h36: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h37: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h38: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h39: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h3a: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h3b: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h3c: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h3d: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h3e: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h3f: dct_cos_table = 32'h0a61ad13; // = +0.162212
+			endcase
+		6'h20:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h01: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h02: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h03: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h04: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h05: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h06: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h07: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h08: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h09: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0a: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0b: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0c: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0d: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0e: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0f: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h10: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h11: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h12: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h13: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h14: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h15: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h16: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h17: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h18: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h19: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1a: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1d: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1e: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1f: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h20: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h21: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h22: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h23: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h24: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h25: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h26: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h27: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h28: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h29: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2a: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2b: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2c: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2d: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2e: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2f: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h30: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h31: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h32: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h33: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h34: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h35: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h36: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h37: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h38: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h39: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3a: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3d: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3e: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3f: dct_cos_table = 32'h20000000; // = +0.500000
+			endcase
+		6'h21:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h01: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h02: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h03: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h04: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h05: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h06: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h07: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h08: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h09: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0a: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0b: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0c: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0d: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0e: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0f: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h10: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h11: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h12: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h13: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h14: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h15: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h16: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h17: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h18: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h19: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1b: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h20: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h21: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h22: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h23: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h24: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h25: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h26: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h27: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h28: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h29: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2a: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2b: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2c: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2d: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2e: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2f: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h30: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h31: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h32: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h33: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h34: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h35: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h36: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h37: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h38: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h39: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3b: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+			endcase
+		6'h22:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h01: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h02: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h03: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h04: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h05: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h06: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h07: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h08: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h09: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0a: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0b: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0c: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0d: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0e: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h0f: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h10: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h11: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h12: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h13: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h14: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h15: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h16: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h17: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h18: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h19: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h1a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h1f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h20: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h21: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h22: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h23: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h24: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h25: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h26: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h27: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h28: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h29: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2a: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2b: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2c: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2d: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2e: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h2f: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h30: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h31: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h32: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h33: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h34: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h35: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h36: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h37: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h38: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h39: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+			endcase
+		6'h23:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h01: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h02: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h03: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h04: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h05: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h06: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h07: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h08: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h09: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0a: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0b: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0d: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0e: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0f: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h10: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h11: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h12: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h13: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h14: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h15: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h16: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h17: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h18: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h19: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1c: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h20: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h21: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h22: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h23: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h24: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h25: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h26: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h27: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h28: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h29: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2a: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2b: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2d: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2e: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2f: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h30: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h31: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h32: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h33: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h34: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h35: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h36: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h37: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h38: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h39: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3c: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+			endcase
+		6'h24:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h01: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h02: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h03: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h04: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h05: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h06: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h07: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h08: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h09: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0a: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h0b: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h0c: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h0d: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h0e: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h0f: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h10: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h11: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h12: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h13: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h14: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h15: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h16: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h17: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h18: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h19: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h1a: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h1b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h1c: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h1d: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h1e: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h1f: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h20: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h21: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h22: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h23: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h24: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h25: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h26: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h27: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h28: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h29: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2a: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2b: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2c: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h2d: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h2e: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h2f: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h30: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h31: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h32: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h33: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h34: dct_cos_table = 32'he0000001; // = -0.500000
+				6'h35: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h36: dct_cos_table = 32'h1fffffff; // = +0.500000
+				6'h37: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h38: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h39: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h3a: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h3b: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3c: dct_cos_table = 32'h20000000; // = +0.500000
+				6'h3d: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h3e: dct_cos_table = 32'he0000000; // = -0.500000
+				6'h3f: dct_cos_table = 32'h20000000; // = +0.500000
+			endcase
+		6'h25:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h01: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h02: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h03: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h04: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h05: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h06: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h07: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h08: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h09: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0a: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h0b: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0c: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0d: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h0e: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0f: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h10: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h11: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h12: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h13: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h14: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h15: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h16: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h17: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h18: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h19: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h1b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h1e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h20: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h21: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h22: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h23: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h24: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h25: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h26: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h27: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h28: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h29: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2a: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2b: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2c: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2d: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2e: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2f: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h30: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h31: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h32: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h33: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h34: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h35: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h36: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h37: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h38: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h39: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3f: dct_cos_table = 32'he6db9640; // = -0.392847
+			endcase
+		6'h26:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h01: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h02: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h03: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h04: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h05: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h06: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h07: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h08: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h09: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0a: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0b: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0c: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h0d: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0e: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0f: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h10: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h11: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h12: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h13: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h14: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h15: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h16: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h17: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h18: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h19: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h1b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h1e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h1f: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h20: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h21: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h22: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h23: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h24: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h25: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h26: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h27: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h28: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h29: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2a: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2b: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2c: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h2d: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2e: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2f: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h30: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h31: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h32: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h33: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h34: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h35: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h36: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h37: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h38: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h39: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h3e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h3f: dct_cos_table = 32'h11517a7b; // = +0.270598
+			endcase
+		6'h27:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h01: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h02: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h03: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h04: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h05: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h06: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h07: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h08: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h09: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0a: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h0b: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0c: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0d: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h0e: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0f: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h10: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h11: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h12: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h13: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h14: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h15: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h16: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h17: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h18: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h19: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h1a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1c: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h1f: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h20: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h21: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h22: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h23: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h24: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h25: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h26: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h27: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h28: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h29: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h2a: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2b: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h2c: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h2d: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2e: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h2f: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h30: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h31: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h32: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h33: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h34: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h35: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h36: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h37: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h38: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h39: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h3b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h3c: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h3d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h3e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3f: dct_cos_table = 32'hf72bd511; // = -0.137950
+			endcase
+		6'h28:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h01: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h02: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h03: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h04: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h05: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h06: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h07: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h08: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h09: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0c: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0d: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0e: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h10: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h11: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h12: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h13: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h14: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h15: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h16: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h17: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h18: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h19: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1c: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1d: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1e: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1f: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h20: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h21: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h22: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h23: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h24: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h25: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h26: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h27: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h28: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h29: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2a: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2b: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2e: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2f: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h30: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h31: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h32: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h33: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h34: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h35: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h36: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h37: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h38: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h39: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3a: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3e: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3f: dct_cos_table = 32'he6db9640; // = -0.392847
+			endcase
+		6'h29:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h01: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h02: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h03: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h04: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h05: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h06: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h07: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h08: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h09: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h0a: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h0b: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h0c: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h0d: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h0e: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h0f: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h10: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h11: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h12: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h13: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h14: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h15: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h16: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h17: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h18: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h19: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h1a: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h1b: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h1c: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h1d: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h1e: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h1f: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h20: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h21: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h22: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h23: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h24: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h25: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h26: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h27: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h28: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h29: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h2a: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h2b: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h2c: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h2d: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h2e: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h2f: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h30: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h31: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h32: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h33: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h34: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h35: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h36: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h37: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h38: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h39: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h3a: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h3b: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h3c: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h3d: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h3e: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h3f: dct_cos_table = 32'h22df8fb9; // = +0.544895
+			endcase
+		6'h2a:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h01: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h02: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h03: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h04: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h05: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h06: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h07: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h08: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h09: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h0a: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h0b: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h0c: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h0d: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h0e: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h0f: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h10: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h11: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h12: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h13: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h14: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h15: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h16: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h17: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h18: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h19: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h1a: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h1b: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h1c: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h1d: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h1e: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h1f: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h20: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h21: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h22: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h23: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h24: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h25: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h26: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h27: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h28: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h29: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h2a: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h2b: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h2c: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h2d: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h2e: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h2f: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h30: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h31: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h32: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h33: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h34: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h35: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h36: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h37: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h38: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h39: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h3a: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h3b: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h3c: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h3d: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h3e: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h3f: dct_cos_table = 32'hdf266bc8; // = -0.513280
+			endcase
+		6'h2b:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h01: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h02: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h03: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h04: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h05: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h06: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h07: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h08: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h09: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h0a: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h0b: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h0c: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h0d: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h0e: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h0f: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h10: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h11: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h12: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h13: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h14: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h15: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h16: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h17: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h18: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h19: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h1a: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h1b: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h1c: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h1d: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h1e: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h1f: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h20: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h21: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h22: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h23: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h24: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h25: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h26: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h27: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h28: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h29: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h2a: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h2b: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h2c: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h2d: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h2e: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h2f: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h30: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h31: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h32: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h33: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h34: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h35: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h36: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h37: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h38: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h39: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h3a: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h3b: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h3c: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h3d: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h3e: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h3f: dct_cos_table = 32'h1d906bcf; // = +0.461940
+			endcase
+		6'h2c:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h01: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h02: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h03: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h04: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h05: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h06: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h07: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h08: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h09: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0a: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0c: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h0d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h0f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h10: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h11: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h12: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h13: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h14: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h15: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h16: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h17: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h18: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h19: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1a: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1b: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1c: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h1d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h1f: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h20: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h21: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h22: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h23: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h24: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h25: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h26: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h27: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h28: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h29: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2b: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h2d: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h2f: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h30: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h31: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h32: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h33: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h34: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h35: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h36: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h37: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h38: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h39: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h3d: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h3f: dct_cos_table = 32'he6db9640; // = -0.392847
+			endcase
+		6'h2d:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h01: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h02: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h03: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h04: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h05: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h06: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h07: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h08: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h09: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h0a: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h0b: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h0c: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h0d: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h0e: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h0f: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h10: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h11: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h12: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h13: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h14: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h15: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h16: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h17: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h18: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h19: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h1a: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h1b: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h1c: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h1d: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h1e: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h1f: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h20: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h21: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h22: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h23: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h24: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h25: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h26: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h27: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h28: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h29: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h2a: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h2b: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h2c: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h2d: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h2e: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h2f: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h30: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h31: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h32: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h33: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h34: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h35: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h36: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h37: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h38: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h39: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h3a: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h3b: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h3c: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h3d: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h3e: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h3f: dct_cos_table = 32'h13c10eac; // = +0.308658
+			endcase
+		6'h2e:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h01: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h02: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h03: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h04: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h05: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h06: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h07: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h08: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h09: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h0a: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h0b: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h0c: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h0d: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h0e: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h0f: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h10: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h11: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h12: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h13: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h14: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h15: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h16: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h17: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h18: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h19: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h1a: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h1b: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h1c: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h1d: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h1e: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h1f: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h20: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h21: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h22: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h23: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h24: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h25: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h26: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h27: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h28: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h29: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h2a: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h2b: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h2c: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h2d: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h2e: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h2f: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h30: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h31: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h32: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h33: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h34: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h35: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h36: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h37: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h38: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h39: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h3a: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h3b: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h3c: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h3d: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h3e: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h3f: dct_cos_table = 32'hf264a36a; // = -0.212608
+			endcase
+		6'h2f:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h01: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h02: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h03: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h04: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h05: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h06: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h07: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h08: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h09: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h0a: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h0b: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h0c: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h0d: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h0e: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h0f: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h10: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h11: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h12: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h13: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h14: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h15: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h16: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h17: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h18: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h19: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h1a: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h1b: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h1c: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h1d: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h1e: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h1f: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h20: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h21: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h22: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h23: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h24: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h25: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h26: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h27: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h28: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h29: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h2a: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h2b: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h2c: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h2d: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h2e: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h2f: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h30: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h31: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h32: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h33: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h34: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h35: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h36: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h37: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h38: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h39: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h3a: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h3b: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h3c: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h3d: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h3e: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h3f: dct_cos_table = 32'h06efcd68; // = +0.108386
+			endcase
+		6'h30:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h01: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h02: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h03: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h04: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h05: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h06: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h07: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h08: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h09: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0a: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0d: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0f: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h10: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h11: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h12: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h13: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h14: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h15: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h16: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h17: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h18: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h19: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1e: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1f: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h20: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h21: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h22: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h23: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h24: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h25: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h26: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h27: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h28: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h29: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2b: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2c: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2e: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h30: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h31: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h32: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h33: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h34: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h35: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h36: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h37: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h38: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h39: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3a: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3b: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3c: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3d: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3f: dct_cos_table = 32'h11517a7b; // = +0.270598
+			endcase
+		6'h31:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h01: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h02: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h03: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h04: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h05: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h06: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h07: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h08: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h09: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h0a: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h0b: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h0c: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h0d: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h0e: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h0f: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h10: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h11: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h12: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h13: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h14: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h15: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h16: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h17: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h18: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h19: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h1a: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h1b: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h1c: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h1d: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h1e: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h1f: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h20: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h21: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h22: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h23: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h24: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h25: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h26: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h27: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h28: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h29: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h2a: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h2b: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h2c: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h2d: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h2e: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h2f: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h30: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h31: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h32: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h33: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h34: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h35: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h36: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h37: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h38: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h39: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h3a: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h3b: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h3c: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h3d: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h3e: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h3f: dct_cos_table = 32'he7fa96b8; // = -0.375330
+			endcase
+		6'h32:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h01: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h02: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h03: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h04: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h05: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h06: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h07: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h08: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h09: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h0a: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h0b: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h0c: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h0d: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h0e: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h0f: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h10: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h11: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h12: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h13: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h14: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h15: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h16: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h17: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h18: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h19: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h1a: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h1b: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h1c: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h1d: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h1e: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h1f: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h20: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h21: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h22: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h23: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h24: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h25: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h26: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h27: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h28: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h29: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h2a: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h2b: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h2c: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h2d: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h2e: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h2f: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h30: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h31: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h32: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h33: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h34: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h35: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h36: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h37: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h38: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h39: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h3a: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h3b: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h3c: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h3d: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h3e: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h3f: dct_cos_table = 32'h16a09e66; // = +0.353553
+			endcase
+		6'h33:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h01: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h02: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h03: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h04: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h05: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h06: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h07: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h08: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h09: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h0a: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h0b: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h0c: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h0d: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h0e: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h0f: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h10: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h11: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h12: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h13: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h14: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h15: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h16: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h17: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h18: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h19: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h1a: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h1b: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h1c: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h1d: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h1e: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h1f: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h20: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h21: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h22: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h23: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h24: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h25: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h26: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h27: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h28: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h29: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h2a: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h2b: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h2c: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h2d: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h2e: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h2f: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h30: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h31: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h32: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h33: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h34: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h35: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h36: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h37: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h38: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h39: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h3a: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h3b: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h3c: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h3d: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h3e: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h3f: dct_cos_table = 32'heba2c7e7; // = -0.318190
+			endcase
+		6'h34:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h01: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h02: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h03: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h04: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h05: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h06: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h07: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h08: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h09: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0a: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0b: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0c: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h0d: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0e: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h0f: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h10: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h11: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h12: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h13: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h14: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h15: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h16: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h17: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h18: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h19: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h1a: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h1b: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1c: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h1d: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h1e: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h1f: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h20: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h21: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h22: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h23: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h24: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h25: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h26: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h27: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h28: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h29: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2a: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2b: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2c: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h2d: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2e: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h2f: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h30: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h31: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h32: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h33: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h34: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h35: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h36: dct_cos_table = 32'h29cf5d22; // = +0.653281
+				6'h37: dct_cos_table = 32'hd630a2de; // = -0.653281
+				6'h38: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h39: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3a: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3b: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3c: dct_cos_table = 32'h11517a7b; // = +0.270598
+				6'h3d: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3e: dct_cos_table = 32'heeae8585; // = -0.270598
+				6'h3f: dct_cos_table = 32'h11517a7b; // = +0.270598
+			endcase
+		6'h35:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h01: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h02: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h03: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h04: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h05: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h06: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h07: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h08: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h09: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h0a: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h0b: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h0c: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h0d: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h0e: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h0f: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h10: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h11: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h12: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h13: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h14: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h15: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h16: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h17: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h18: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h19: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h1a: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h1b: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h1c: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h1d: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h1e: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h1f: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h20: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h21: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h22: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h23: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h24: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h25: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h26: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h27: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h28: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h29: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h2a: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h2b: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h2c: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h2d: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h2e: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h2f: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h30: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h31: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h32: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h33: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h34: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h35: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h36: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h37: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h38: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h39: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h3a: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h3b: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h3c: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h3d: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h3e: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h3f: dct_cos_table = 32'hf264a36a; // = -0.212608
+			endcase
+		6'h36:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h01: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h02: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h03: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h04: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h05: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h06: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h07: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h08: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h09: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h0a: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h0b: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h0c: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h0d: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h0e: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h0f: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h10: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h11: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h12: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h13: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h14: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h15: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h16: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h17: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h18: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h19: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h1a: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h1b: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h1c: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h1d: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h1e: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h1f: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h20: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h21: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h22: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h23: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h24: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h25: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h26: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h27: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h28: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h29: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h2a: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h2b: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h2c: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h2d: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h2e: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h2f: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h30: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h31: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h32: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h33: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h34: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h35: dct_cos_table = 32'hc95f619a; // = -0.853553
+				6'h36: dct_cos_table = 32'h36a09e66; // = +0.853553
+				6'h37: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h38: dct_cos_table = 32'h095f6199; // = +0.146447
+				6'h39: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h3a: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h3b: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h3c: dct_cos_table = 32'hf6a09e67; // = -0.146447
+				6'h3d: dct_cos_table = 32'h16a09e66; // = +0.353553
+				6'h3e: dct_cos_table = 32'he95f619a; // = -0.353553
+				6'h3f: dct_cos_table = 32'h095f6199; // = +0.146447
+			endcase
+		6'h37:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h01: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h02: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h03: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h04: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h05: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h06: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h07: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h08: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h09: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h0a: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h0b: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h0c: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h0d: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h0e: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h0f: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h10: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h11: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h12: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h13: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h14: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h15: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h16: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h17: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h18: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h19: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h1a: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h1b: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h1c: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h1d: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h1e: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h1f: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h20: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h21: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h22: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h23: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h24: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h25: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h26: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h27: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h28: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h29: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h2a: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h2b: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h2c: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h2d: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h2e: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h2f: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h30: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h31: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h32: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h33: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h34: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h35: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h36: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h37: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h38: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h39: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h3a: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h3b: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h3c: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h3d: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h3e: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h3f: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+			endcase
+		6'h38:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h01: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h02: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h03: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h04: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h05: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h06: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h07: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h08: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h09: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0a: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0d: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0e: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h10: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h11: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h12: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h13: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h14: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h15: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h16: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h17: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h18: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h19: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1a: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1c: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1d: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1e: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h20: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h21: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h22: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h23: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h24: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h25: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h26: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h27: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h28: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h29: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2a: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2b: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2d: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2e: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h30: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h31: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h32: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h33: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h34: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h35: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h36: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h37: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h38: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h39: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3a: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3b: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3d: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3e: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3f: dct_cos_table = 32'hf72bd511; // = -0.137950
+			endcase
+		6'h39:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h01: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h02: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h03: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h04: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h05: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h06: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h07: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h08: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h09: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h0a: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h0b: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h0c: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h0d: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h0e: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h0f: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h10: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h11: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h12: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h13: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h14: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h15: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h16: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h17: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h18: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h19: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h1a: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h1b: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h1c: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h1d: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h1e: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h1f: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h20: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h21: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h22: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h23: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h24: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h25: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h26: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h27: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h28: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h29: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h2a: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h2b: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h2c: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h2d: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h2e: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h2f: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h30: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h31: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h32: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h33: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h34: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h35: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h36: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h37: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h38: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h39: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h3a: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h3b: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h3c: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h3d: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h3e: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h3f: dct_cos_table = 32'h0c3ef153; // = +0.191342
+			endcase
+		6'h3a:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h01: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h02: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h03: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h04: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h05: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h06: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h07: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h08: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h09: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h0a: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h0b: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h0c: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h0d: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h0e: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h0f: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h10: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h11: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h12: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h13: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h14: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h15: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h16: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h17: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h18: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h19: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h1a: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h1b: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h1c: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h1d: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h1e: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h1f: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h20: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h21: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h22: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h23: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h24: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h25: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h26: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h27: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h28: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h29: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h2a: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h2b: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h2c: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h2d: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h2e: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h2f: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h30: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h31: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h32: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h33: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h34: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h35: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h36: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h37: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h38: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h39: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h3a: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h3b: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h3c: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h3d: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h3e: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h3f: dct_cos_table = 32'hf476f2d6; // = -0.180240
+			endcase
+		6'h3b:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h01: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h02: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h03: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h04: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h05: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h06: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h07: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h08: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h09: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h0a: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h0b: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h0c: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h0d: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h0e: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h0f: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h10: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h11: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h12: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h13: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h14: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h15: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h16: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h17: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h18: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h19: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h1a: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h1b: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h1c: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h1d: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h1e: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h1f: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h20: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h21: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h22: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h23: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h24: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h25: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h26: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h27: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h28: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h29: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h2a: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h2b: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h2c: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h2d: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h2e: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h2f: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h30: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h31: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h32: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h33: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h34: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h35: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h36: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h37: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h38: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h39: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h3a: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h3b: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h3c: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h3d: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h3e: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h3f: dct_cos_table = 32'h0a61ad13; // = +0.162212
+			endcase
+		6'h3c:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h01: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h02: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h03: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h04: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h05: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h06: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h07: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h08: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h09: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0a: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0b: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0c: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h0d: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0e: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h0f: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h10: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h11: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h12: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h13: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h14: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h15: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h16: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h17: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h18: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h19: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1a: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1b: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1c: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h1d: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1e: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h1f: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h20: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h21: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h22: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h23: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h24: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h25: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h26: dct_cos_table = 32'hd39d5e9e; // = -0.693520
+				6'h27: dct_cos_table = 32'h2c62a162; // = +0.693520
+				6'h28: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h29: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2a: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2b: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2c: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h2d: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2e: dct_cos_table = 32'h25a0c5df; // = +0.587938
+				6'h2f: dct_cos_table = 32'hda5f3a21; // = -0.587938
+				6'h30: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h31: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h32: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h33: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h34: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h35: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h36: dct_cos_table = 32'he6db9640; // = -0.392847
+				6'h37: dct_cos_table = 32'h192469c0; // = +0.392847
+				6'h38: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h39: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3a: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3b: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3c: dct_cos_table = 32'hf72bd511; // = -0.137950
+				6'h3d: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3e: dct_cos_table = 32'h08d42aef; // = +0.137950
+				6'h3f: dct_cos_table = 32'hf72bd511; // = -0.137950
+			endcase
+		6'h3d:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h01: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h02: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h03: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h04: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h05: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h06: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h07: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h08: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h09: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h0a: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h0b: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h0c: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h0d: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h0e: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h0f: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h10: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h11: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h12: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h13: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h14: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h15: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h16: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h17: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h18: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h19: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h1a: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h1b: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h1c: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h1d: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h1e: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h1f: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h20: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h21: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h22: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h23: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h24: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h25: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h26: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h27: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h28: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h29: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h2a: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h2b: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h2c: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h2d: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h2e: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h2f: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h30: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h31: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h32: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h33: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h34: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h35: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h36: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h37: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h38: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h39: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h3a: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h3b: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h3c: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h3d: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h3e: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h3f: dct_cos_table = 32'h06efcd68; // = +0.108386
+			endcase
+		6'h3e:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h01: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h02: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h03: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h04: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h05: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h06: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h07: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h08: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h09: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h0a: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h0b: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h0c: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h0d: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h0e: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h0f: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h10: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h11: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h12: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h13: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h14: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h15: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h16: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h17: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h18: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h19: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h1a: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h1b: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h1c: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h1d: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h1e: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h1f: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h20: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h21: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h22: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h23: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h24: dct_cos_table = 32'he7fa96b8; // = -0.375330
+				6'h25: dct_cos_table = 32'h39fdfdf9; // = +0.906127
+				6'h26: dct_cos_table = 32'hc6020207; // = -0.906127
+				6'h27: dct_cos_table = 32'h18056948; // = +0.375330
+				6'h28: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h29: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h2a: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h2b: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h2c: dct_cos_table = 32'h145d3819; // = +0.318190
+				6'h2d: dct_cos_table = 32'hced62cf7; // = -0.768178
+				6'h2e: dct_cos_table = 32'h3129d309; // = +0.768178
+				6'h2f: dct_cos_table = 32'heba2c7e7; // = -0.318190
+				6'h30: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h31: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h32: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h33: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h34: dct_cos_table = 32'hf264a36a; // = -0.212608
+				6'h35: dct_cos_table = 32'h20d99438; // = +0.513280
+				6'h36: dct_cos_table = 32'hdf266bc8; // = -0.513280
+				6'h37: dct_cos_table = 32'h0d9b5c96; // = +0.212608
+				6'h38: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+				6'h39: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h3a: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h3b: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h3c: dct_cos_table = 32'h04c731a6; // = +0.074658
+				6'h3d: dct_cos_table = 32'hf476f2d6; // = -0.180240
+				6'h3e: dct_cos_table = 32'h0b890d2a; // = +0.180240
+				6'h3f: dct_cos_table = 32'hfb38ce5a; // = -0.074658
+			endcase
+		6'h3f:
+			case ( {y,x} )	// synopsys full_case parallel_case
+				6'h00: dct_cos_table = 32'h026f9430; // = +0.038060
+				6'h01: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h02: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h03: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h04: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h05: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h06: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h07: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h08: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h09: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h0a: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h0b: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h0c: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h0d: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h0e: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h0f: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h10: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h11: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h12: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h13: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h14: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h15: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h16: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h17: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h18: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h19: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h1a: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h1b: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h1c: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h1d: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h1e: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h1f: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h20: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h21: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h22: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h23: dct_cos_table = 32'hc26f9431; // = -0.961940
+				6'h24: dct_cos_table = 32'h3d906bcf; // = +0.961940
+				6'h25: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h26: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h27: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h28: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h29: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h2a: dct_cos_table = 32'hd3c10ead; // = -0.691342
+				6'h2b: dct_cos_table = 32'h34310a35; // = +0.815493
+				6'h2c: dct_cos_table = 32'hcbcef5cb; // = -0.815493
+				6'h2d: dct_cos_table = 32'h2c3ef153; // = +0.691342
+				6'h2e: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h2f: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h30: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h31: dct_cos_table = 32'hec3ef154; // = -0.308658
+				6'h32: dct_cos_table = 32'h1d906bcf; // = +0.461940
+				6'h33: dct_cos_table = 32'hdd207047; // = -0.544895
+				6'h34: dct_cos_table = 32'h22df8fb9; // = +0.544895
+				6'h35: dct_cos_table = 32'he26f9431; // = -0.461940
+				6'h36: dct_cos_table = 32'h13c10eac; // = +0.308658
+				6'h37: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h38: dct_cos_table = 32'hfd906bd0; // = -0.038060
+				6'h39: dct_cos_table = 32'h06efcd68; // = +0.108386
+				6'h3a: dct_cos_table = 32'hf59e52ed; // = -0.162212
+				6'h3b: dct_cos_table = 32'h0c3ef153; // = +0.191342
+				6'h3c: dct_cos_table = 32'hf3c10ead; // = -0.191342
+				6'h3d: dct_cos_table = 32'h0a61ad13; // = +0.162212
+				6'h3e: dct_cos_table = 32'hf9103298; // = -0.108386
+				6'h3f: dct_cos_table = 32'h026f9430; // = +0.038060
+			endcase
+	endcase
+
+end
+endfunction
+
+
diff --git a/BENCHMARK/dct_mac/rtl/dct_mac.v b/BENCHMARK/dct_mac/rtl/dct_mac.v
new file mode 100644
index 0000000..e64b6bf
--- /dev/null
+++ b/BENCHMARK/dct_mac/rtl/dct_mac.v
@@ -0,0 +1,123 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Discrete Cosine Transform, MAC unit                        ////
+////                                                             ////
+////  Virtex-II: Block-Multiplier is used                        ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: dct_mac.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
+//
+//  $Date: 2002-10-31 12:50:03 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.2  2002/10/23 09:06:59  rherveille
+//               Improved many files.
+//               Fixed some bugs in Run-Length-Encoder.
+//               Removed dependency on ud_cnt and ro_cnt.
+//               Started (Motion)JPEG hardware encoder project.
+//
+
+//synopsys translate_off
+`include "timescale.v"
+//synopsys translate_on
+
+module dct_mac(clk, ena, dclr, din, coef, result);
+
+	//
+	// parameters
+	//
+	parameter dwidth = 8;
+	parameter cwidth = 16;
+	parameter mwidth = dwidth + cwidth;  // multiplier result
+	parameter rwidth = mwidth +3;        // add 3 bits for growth
+
+	//
+	// inputs & outputs
+	//
+	input               clk;    // clock input
+	input               ena;    // clock enable
+	input               dclr;   // start new mac (delayed 1 cycle)
+	input  [dwidth-1:0] din;    // data input
+	input  [cwidth-1:0] coef;   // coefficient input
+	output [rwidth-1:0] result; // mac-result
+	reg [rwidth -1:0] result;
+
+	//
+	// variables
+	//
+	wire [mwidth-1:0] idin;
+	wire [mwidth-1:0] icoef;
+
+	reg  [mwidth -1:0] mult_res /* synthesis syn_multstyle="block_mult" syn_pipeline=1*/ ;
+	wire [rwidth -1:0] ext_mult_res;
+
+
+	//
+	// module body
+	//
+	assign icoef = { {(mwidth-cwidth){coef[cwidth-1]}}, coef};
+	assign idin  = { {(mwidth-dwidth){din[dwidth-1]}}, din};
+
+	// generate multiplier structure
+	always @(posedge clk)
+	  if(ena)
+	    mult_res <= #1 icoef * idin;
+
+	assign ext_mult_res = { {3{mult_res[mwidth-1]}}, mult_res};
+
+	// generate adder structure
+	always @(posedge clk)
+	  if(ena)
+	    if(dclr)
+	      result <= #1 ext_mult_res;
+	    else
+	      result <= #1 ext_mult_res + result;
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/BENCHMARK/dct_mac/rtl/dct_syn.v b/BENCHMARK/dct_mac/rtl/dct_syn.v
new file mode 100644
index 0000000..0e0c6ac
--- /dev/null
+++ b/BENCHMARK/dct_mac/rtl/dct_syn.v
@@ -0,0 +1,95 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Discrete Cosine Transform Synthesis Test                   ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Synthesis results:                                         ////
+////                                                             ////
+////                                                             ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: dct_syn.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
+//
+//  $Date: 2002-10-31 12:50:03 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.2  2002/10/23 09:06:59  rherveille
+//               Improved many files.
+//               Fixed some bugs in Run-Length-Encoder.
+//               Removed dependency on ud_cnt and ro_cnt.
+//               Started (Motion)JPEG hardware encoder project.
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+module dct_syn(clk, ena, rst, dstrb, din, dout, den);
+
+	input clk;
+	input ena;
+	input rst;
+
+	input dstrb;
+	input [7:0] din;
+	
+	output [11:0] dout;
+	output den;
+
+	//
+	// DCT unit
+	//
+
+	// As little as 11bits coefficients can be used while
+	// all errors remain in the decimal bit range (dout[0])
+	// total errors =  5(14bit resolution)
+	//              = 12(13bit resolution)
+	//              = 26(12bit resolution)
+	//              = 54(11bit resolution)
+	fdct #(13) dut (
+		.clk(clk),
+		.ena(1'b1),
+		.rst(rst),
+		.dstrb(dstrb),
+		.din(din),
+		.dout(dout),
+		.douten(den)
+	);
+
+endmodule
diff --git a/BENCHMARK/dct_mac/rtl/dctu.v b/BENCHMARK/dct_mac/rtl/dctu.v
new file mode 100644
index 0000000..9a76209
--- /dev/null
+++ b/BENCHMARK/dct_mac/rtl/dctu.v
@@ -0,0 +1,106 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Discrete Cosine Transform Unit                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: dctu.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
+//
+//  $Date: 2002-10-31 12:50:03 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.2  2002/10/23 09:06:59  rherveille
+//               Improved many files.
+//               Fixed some bugs in Run-Length-Encoder.
+//               Removed dependency on ud_cnt and ro_cnt.
+//               Started (Motion)JPEG hardware encoder project.
+//
+
+
+//synopsys translate_off
+`include "timescale.v"
+//synopsys translate_on
+
+module dctu(clk, ena, ddgo, x, y, ddin, dout);
+
+	parameter coef_width = 16;
+	parameter di_width = 8;
+	parameter [2:0] v = 0;
+	parameter [2:0] u = 0;
+
+	//
+	// inputs & outputs
+	//
+
+	input clk;
+	input ena;
+	input ddgo;               // double delayed go signal
+	input [2:0] x, y;
+
+	input  [di_width:1] ddin; // delayed data input
+	output [11:0] dout;
+
+	//
+	// variables
+	//
+	reg [      31:0] coef;
+
+	wire [coef_width +10:0] result;
+	`include "dct_cos_table.v"
+	//
+	// module body
+	//
+
+	// hookup cosine-table
+	always @(posedge clk)
+	  if(ena)
+	    coef <= #1 dct_cos_table(x, y, u, v);
+
+	// hookup dct-mac unit
+	dct_mac #(8, coef_width)
+	macu (
+		.clk(clk),
+		.ena(ena),
+		.dclr(ddgo),
+		.din(ddin),
+		.coef( coef[31:31 -coef_width +1] ),
+		.result(result)
+	);
+
+	assign dout = result[coef_width +10: coef_width -1];
+endmodule
diff --git a/BENCHMARK/dct_mac/rtl/dctub.v b/BENCHMARK/dct_mac/rtl/dctub.v
new file mode 100644
index 0000000..5026119
--- /dev/null
+++ b/BENCHMARK/dct_mac/rtl/dctub.v
@@ -0,0 +1,169 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Discrete Cosine Transform, DCT unit block                  ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: dctub.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
+//
+//  $Date: 2002-10-31 12:50:03 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.2  2002/10/23 09:06:59  rherveille
+//               Improved many files.
+//               Fixed some bugs in Run-Length-Encoder.
+//               Removed dependency on ud_cnt and ro_cnt.
+//               Started (Motion)JPEG hardware encoder project.
+//
+
+
+//synopsys translate_off
+`include "timescale.v"
+//synopsys translate_on
+
+module dctub(clk, ena, ddgo, x, y, ddin,
+		dout0, dout1, dout2, dout3, dout4, dout5, dout6, dout7);
+
+	parameter coef_width = 16;
+	parameter di_width = 8;
+	parameter [2:0] v = 3'h0;
+
+	//
+	// inputs & outputs
+	//
+	input clk;
+	input ena;
+	input ddgo;               // double delayed go strobe
+	input [2:0] x, y;
+
+	input  [di_width:1] ddin; // delayed data input
+	output [11:0] dout0, dout1, dout2, dout3, dout4, dout5, dout6, dout7;
+
+	//
+	// module body
+	//
+
+	// Hookup DCT units
+	dctu #(coef_width, di_width, v, 3'h0)
+	dct_unit_0 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(x),
+		.y(y),
+		.ddin(ddin),
+		.dout(dout0)
+	);
+
+	dctu #(coef_width, di_width, v, 3'h1)
+	dct_unit_1 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(x),
+		.y(y),
+		.ddin(ddin),
+		.dout(dout1)
+	);
+
+	dctu #(coef_width, di_width, v, 3'h2)
+	dct_unit_2 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(x),
+		.y(y),
+		.ddin(ddin),
+		.dout(dout2)
+	);
+
+	dctu #(coef_width, di_width, v, 3'h3)
+	dct_unit_3 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(x),
+		.y(y),
+		.ddin(ddin),
+		.dout(dout3)
+	);
+
+	dctu #(coef_width, di_width, v, 3'h4)
+	dct_unit_4 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(x),
+		.y(y),
+		.ddin(ddin),
+		.dout(dout4)
+	);
+
+	dctu #(coef_width, di_width, v, 3'h5)
+	dct_unit_5 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(x),
+		.y(y),
+		.ddin(ddin),
+		.dout(dout5)
+	);
+
+	dctu #(coef_width, di_width, v, 3'h6)
+	dct_unit_6 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(x),
+		.y(y),
+		.ddin(ddin),
+		.dout(dout6)
+	);
+
+	dctu #(coef_width, di_width, v, 3'h7)
+	dct_unit_7 (
+		.clk(clk),
+		.ena(ena),
+		.ddgo(ddgo),
+		.x(x),
+		.y(y),
+		.ddin(ddin),
+		.dout(dout7)
+	);
+endmodule
diff --git a/BENCHMARK/dct_mac/rtl/fdct.v b/BENCHMARK/dct_mac/rtl/fdct.v
new file mode 100644
index 0000000..7dea2a3
--- /dev/null
+++ b/BENCHMARK/dct_mac/rtl/fdct.v
@@ -0,0 +1,292 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Forward Discrete Cosine Transform and ZigZag unit          ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: fdct.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
+//
+//  $Date: 2002-10-31 12:50:03 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.2  2002/10/23 09:06:59  rherveille
+//               Improved many files.
+//               Fixed some bugs in Run-Length-Encoder.
+//               Removed dependency on ud_cnt and ro_cnt.
+//               Started (Motion)JPEG hardware encoder project.
+//
+
+
+//synopsys translate_off
+`include "timescale.v"
+//synopsys translate_on
+
+module fdct(clk, ena, rst, dstrb, din, dout, douten);
+
+	//
+	// parameters
+	//
+
+	////////////////////////////////////////////////////////////////////
+	//                                                                //
+	// ITU-T.81, ITU-T.83 & Coefficient resolution notes              //
+	//                                                                //
+	////////////////////////////////////////////////////////////////////
+	//                                                                //
+	// Worst case error (all input values -128) is                    //
+	// zero (i.e. no errors) when using 15bit coefficients            //
+	//                                                                //
+	// Using less bits for the coefficients produces a biterror       //
+	// approx. equal to (15 - used_coefficient-bits).                 //
+	// i.e. 14bit coefficients, errors in dout-bit[0] only            //
+	//      13bit coefficients, errors in dout-bits[1:0]              //
+	//      12bit coefficients, errors in dout-bits[2:0] etc.         //
+	// Tests with real non-continous tone image data have shown that  //
+	// even when using 13bit coefficients errors remain in the lsb    //
+	// only (i.e. dout-bit[0]                                         //
+	//                                                                //
+	// The amount of coefficient-bits needed is dependent on the      //
+	// desired quality.                                               //
+	// The JPEG-standard compliance specs.(ITU-T.83) prescribe        //
+	// that the output of the combined DCT AND Quantization unit      //
+	// shall not exceed 1 for the desired quality.                    //
+	//                                                                //
+	// This means for high quantization levels, lesser bits           //
+	// for the DCT unit can be used.                                  //
+	//                                                                //
+	// Looking at the recommended "quantization tables for generic    //
+	// compliance testing of DCT-based processes" (ITU-T.83 annex B)  //
+	// it can be noticed that relatively large quantization values    //
+	// are being used. Errors in the lower-order bits should          //
+	// therefore not be visible.                                      //
+	// For certain applications some of the lower-order bits could    //
+	// actually be discarded. When looking at the luminance and       //
+	// chrominance example quantization tables (ITU-T.81 annex K)     //
+	// it can be seen that the smallest quantization value is ten     //
+	// (qnt_val_min = 10). This means that the lowest 2bits can be    //
+	// discarded (set to zero '0') without having any effect on the   //
+	// final result. In this example 11 bit or 12 bit coefficients    //
+	// would be sufficient.                                           //
+	//                                                                //
+	////////////////////////////////////////////////////////////////////
+
+	parameter coef_width = 11;
+	parameter di_width = 8;
+	parameter do_width = 12;
+
+	//
+	// inputs & outputs
+	//
+	input clk;                    // system clock
+	input ena;                    // clock enable
+	input rst;                    // active low asynchronous reset
+
+	input dstrb;                  // data-strobe. Present dstrb 1clk-cycle before data block
+	input  [di_width-1:0] din;
+	output [do_width-1:0] dout;
+	output                douten; // data-out enable
+
+	//
+	// variables
+	//
+
+	wire doe;
+
+	wire [do_width -1:0]  // results from DCT module
+		res00, res01, res02, res03, res04, res05, res06, res07,
+		res10, res11, res12, res13, res14, res15, res16, res17,
+		res20, res21, res22, res23, res24, res25, res26, res27,
+		res30, res31, res32, res33, res34, res35, res36, res37, 
+		res40, res41, res42, res43, res44, res45, res46, res47,
+		res50, res51, res52, res53, res54, res55, res56, res57, 
+		res60, res61, res62, res63, res64, res65, res66, res67,
+		res70, res71, res72, res73, res74, res75, res76, res77;
+
+
+	//
+	// module body
+	//
+
+	// Hookup DCT module
+	dct #(coef_width, di_width, do_width)
+	dct_mod(
+		.clk(clk),
+		.ena(ena),
+		.rst(rst),
+		.dstrb(dstrb),
+		.din(din),
+		.dout_00(res00),
+		.dout_01(res01),
+		.dout_02(res02),
+		.dout_03(res03),
+		.dout_04(res04),
+		.dout_05(res05),
+		.dout_06(res06),
+		.dout_07(res07),
+		.dout_10(res10),
+		.dout_11(res11),
+		.dout_12(res12),
+		.dout_13(res13),
+		.dout_14(res14),
+		.dout_15(res15),
+		.dout_16(res16),
+		.dout_17(res17),
+		.dout_20(res20),
+		.dout_21(res21),
+		.dout_22(res22),
+		.dout_23(res23),
+		.dout_24(res24),
+		.dout_25(res25),
+		.dout_26(res26),
+		.dout_27(res27),
+		.dout_30(res30),
+		.dout_31(res31),
+		.dout_32(res32),
+		.dout_33(res33),
+		.dout_34(res34),
+		.dout_35(res35),
+		.dout_36(res36),
+		.dout_37(res37),
+		.dout_40(res40),
+		.dout_41(res41),
+		.dout_42(res42),
+		.dout_43(res43),
+		.dout_44(res44),
+		.dout_45(res45),
+		.dout_46(res46),
+		.dout_47(res47),
+		.dout_50(res50),
+		.dout_51(res51),
+		.dout_52(res52),
+		.dout_53(res53),
+		.dout_54(res54),
+		.dout_55(res55),
+		.dout_56(res56),
+		.dout_57(res57),
+		.dout_60(res60),
+		.dout_61(res61),
+		.dout_62(res62),
+		.dout_63(res63),
+		.dout_64(res64),
+		.dout_65(res65),
+		.dout_66(res66),
+		.dout_67(res67),
+		.dout_70(res70),
+		.dout_71(res71),
+		.dout_72(res72),
+		.dout_73(res73),
+		.dout_74(res74),
+		.dout_75(res75),
+		.dout_76(res76),
+		.dout_77(res77),
+		.douten(doe)
+	);
+
+	// Hookup ZigZag unit
+	zigzag zigzag_mod(
+		.clk(clk), 
+		.ena(ena),
+		.dstrb(doe),
+		.din_00(res00),
+		.din_01(res01),
+		.din_02(res02),
+		.din_03(res03),
+		.din_04(res04),
+		.din_05(res05),
+		.din_06(res06),
+		.din_07(res07),
+		.din_10(res10),
+		.din_11(res11),
+		.din_12(res12),
+		.din_13(res13),
+		.din_14(res14),
+		.din_15(res15),
+		.din_16(res16),
+		.din_17(res17),
+		.din_20(res20),
+		.din_21(res21),
+		.din_22(res22),
+		.din_23(res23),
+		.din_24(res24),
+		.din_25(res25),
+		.din_26(res26),
+		.din_27(res27),
+		.din_30(res30),
+		.din_31(res31),
+		.din_32(res32),
+		.din_33(res33),
+		.din_34(res34),
+		.din_35(res35),
+		.din_36(res36),
+		.din_37(res37),
+		.din_40(res40),
+		.din_41(res41),
+		.din_42(res42),
+		.din_43(res43),
+		.din_44(res44),
+		.din_45(res45),
+		.din_46(res46),
+		.din_47(res47),
+		.din_50(res50),
+		.din_51(res51),
+		.din_52(res52),
+		.din_53(res53),
+		.din_54(res54),
+		.din_55(res55),
+		.din_56(res56),
+		.din_57(res57),
+		.din_60(res60),
+		.din_61(res61),
+		.din_62(res62),
+		.din_63(res63),
+		.din_64(res64),
+		.din_65(res65),
+		.din_66(res66),
+		.din_67(res67),
+		.din_70(res70),
+		.din_71(res71),
+		.din_72(res72),
+		.din_73(res73),
+		.din_74(res74),
+		.din_75(res75),
+		.din_76(res76),
+		.din_77(res77),
+		.dout(dout),
+		.douten(douten)
+	);
+endmodule
diff --git a/BENCHMARK/dct_mac/rtl/zigzag.v b/BENCHMARK/dct_mac/rtl/zigzag.v
new file mode 100644
index 0000000..b770350
--- /dev/null
+++ b/BENCHMARK/dct_mac/rtl/zigzag.v
@@ -0,0 +1,201 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Zig-Zag Unit                                               ////
+////  Performs zigzag-ing, as used by many DCT based encoders    ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: zigzag.v,v 1.2 2002-10-23 09:06:59 rherveille Exp $
+//
+//  $Date: 2002-10-23 09:06:59 $
+//  $Revision: 1.2 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+module zigzag(
+	clk, 
+	ena, 
+	dstrb, 
+	din_00, din_01, din_02, din_03, din_04, din_05, din_06, din_07,
+	din_10, din_11, din_12, din_13, din_14, din_15, din_16, din_17,
+	din_20, din_21, din_22, din_23, din_24, din_25, din_26, din_27,
+	din_30, din_31, din_32, din_33, din_34, din_35, din_36, din_37,
+	din_40, din_41, din_42, din_43, din_44, din_45, din_46, din_47,
+	din_50, din_51, din_52, din_53, din_54, din_55, din_56, din_57,
+	din_60, din_61, din_62, din_63, din_64, din_65, din_66, din_67,
+	din_70, din_71, din_72, din_73, din_74, din_75, din_76, din_77,
+	dout,
+	douten
+);
+
+	//
+	// inputs & outputs
+	//
+
+	input clk;                    // system clock
+	input ena;                    // clock enable
+
+	input dstrb;                  // data-strobe. Present dstrb 1clk-cycle before data block
+	input [11:0]
+		din_00, din_01, din_02, din_03, din_04, din_05, din_06, din_07,
+		din_10, din_11, din_12, din_13, din_14, din_15, din_16, din_17,
+		din_20, din_21, din_22, din_23, din_24, din_25, din_26, din_27,
+		din_30, din_31, din_32, din_33, din_34, din_35, din_36, din_37,
+		din_40, din_41, din_42, din_43, din_44, din_45, din_46, din_47,
+		din_50, din_51, din_52, din_53, din_54, din_55, din_56, din_57,
+		din_60, din_61, din_62, din_63, din_64, din_65, din_66, din_67,
+		din_70, din_71, din_72, din_73, din_74, din_75, din_76, din_77;
+	output [11:0] dout;
+	output        douten; // data-out enable
+
+	//
+	// variables
+	//
+
+	reg ld_zigzag;
+	reg [11:0] sresult [63:0]; // store results for zig-zagging
+
+	//
+	// module body
+	//
+
+	always @(posedge clk)
+	  if(ena)
+	    ld_zigzag <= #1 dstrb;
+
+	assign douten = ld_zigzag;
+
+
+	//
+	// Generate zig-zag structure
+	//
+	// This implicates that the quantization step be performed after
+	// the zig-zagging.
+	//
+	//    0: 1: 2: 3: 4: 5: 6: 7:		0: 1: 2: 3: 4: 5: 6: 7:
+	// 0: 63 62 58 57 49 48 36 35		3f 3e 3a 39 31 30 24 23
+	// 1: 61 59 56 50 47 37 34 21		3d 3b 38 32 2f 25 22 15
+	// 2: 60 55 51 46 38 33 22 20		3c 37 33 2e 26 21 16 14
+	// 3: 54 52 45 39 32 23 19 10		36 34 2d 27 20 17 13 0a
+	// 4: 53 44 40 31 24 18 11 09		35 2c 28 1f 18 12 0b 09
+	// 5: 43 41 30 25 17 12 08 03		2b 29 1e 19 11 0c 08 03
+	// 6: 42 29 26 16 13 07 04 02		2a 1d 1a 10 0d 07 04 02
+	// 7: 28 27 15 14 06 05 01 00		1c 1b 0f 0e 06 05 01 00
+	//
+	// zig-zag the DCT results
+	integer n;
+
+	always @(posedge clk)
+	  if(ena)
+	    if(ld_zigzag)   // reload results-register file
+	    begin
+	        sresult[63] <= #1 din_00;
+	        sresult[62] <= #1 din_01;
+	        sresult[61] <= #1 din_10;
+	        sresult[60] <= #1 din_20;
+	        sresult[59] <= #1 din_11;
+	        sresult[58] <= #1 din_02;
+	        sresult[57] <= #1 din_03;
+	        sresult[56] <= #1 din_12;
+	        sresult[55] <= #1 din_21;
+	        sresult[54] <= #1 din_30;
+	        sresult[53] <= #1 din_40;
+	        sresult[52] <= #1 din_31;
+	        sresult[51] <= #1 din_22;
+	        sresult[50] <= #1 din_13;
+	        sresult[49] <= #1 din_04;
+	        sresult[48] <= #1 din_05;
+	        sresult[47] <= #1 din_14;
+	        sresult[46] <= #1 din_23;
+	        sresult[45] <= #1 din_32;
+	        sresult[44] <= #1 din_41;
+	        sresult[43] <= #1 din_50;
+	        sresult[42] <= #1 din_60;
+	        sresult[41] <= #1 din_51;
+	        sresult[40] <= #1 din_42;
+	        sresult[39] <= #1 din_33;
+	        sresult[38] <= #1 din_24;
+	        sresult[37] <= #1 din_15;
+	        sresult[36] <= #1 din_06;
+	        sresult[35] <= #1 din_07;
+	        sresult[34] <= #1 din_16;
+	        sresult[33] <= #1 din_25;
+	        sresult[32] <= #1 din_34;
+	        sresult[31] <= #1 din_43;
+	        sresult[30] <= #1 din_52;
+	        sresult[29] <= #1 din_61;
+	        sresult[28] <= #1 din_70;
+	        sresult[27] <= #1 din_71;
+	        sresult[26] <= #1 din_62;
+	        sresult[25] <= #1 din_53;
+	        sresult[24] <= #1 din_44;
+	        sresult[23] <= #1 din_35;
+	        sresult[22] <= #1 din_26;
+	        sresult[21] <= #1 din_17;
+	        sresult[20] <= #1 din_27;
+	        sresult[19] <= #1 din_36;
+	        sresult[18] <= #1 din_45;
+	        sresult[17] <= #1 din_54;
+	        sresult[16] <= #1 din_63;
+	        sresult[15] <= #1 din_72;
+	        sresult[14] <= #1 din_73;
+	        sresult[13] <= #1 din_64;
+	        sresult[12] <= #1 din_55;
+	        sresult[11] <= #1 din_46;
+	        sresult[10] <= #1 din_37;
+	        sresult[09] <= #1 din_47;
+	        sresult[08] <= #1 din_56;
+	        sresult[07] <= #1 din_65;
+	        sresult[06] <= #1 din_74;
+	        sresult[05] <= #1 din_75;
+	        sresult[04] <= #1 din_66;
+	        sresult[03] <= #1 din_57;
+	        sresult[02] <= #1 din_67;
+	        sresult[01] <= #1 din_76;
+	        sresult[00] <= #1 din_77;
+	    end
+	  else       // shift results out
+	    for (n=1; n<=63; n=n+1) // do not change sresult[0]
+	       sresult[n] <= #1 sresult[n -1];
+
+	assign dout = sresult[63];
+endmodule
diff --git a/BENCHMARK/des_perf/des_perf_yosys.blif b/BENCHMARK/des_perf/des_perf_yosys.blif
new file mode 100644
index 0000000..704f7ed
--- /dev/null
+++ b/BENCHMARK/des_perf/des_perf_yosys.blif
@@ -0,0 +1,60192 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model des_perf
+.inputs desIn(0) desIn(1) desIn(2) desIn(3) desIn(4) desIn(5) desIn(6) desIn(7) desIn(8) desIn(9) desIn(10) desIn(11) desIn(12) desIn(13) desIn(14) desIn(15) desIn(16) desIn(17) desIn(18) desIn(19) desIn(20) desIn(21) desIn(22) desIn(23) desIn(24) desIn(25) desIn(26) desIn(27) desIn(28) desIn(29) desIn(30) desIn(31) desIn(32) desIn(33) desIn(34) desIn(35) desIn(36) desIn(37) desIn(38) desIn(39) desIn(40) desIn(41) desIn(42) desIn(43) desIn(44) desIn(45) desIn(46) desIn(47) desIn(48) desIn(49) desIn(50) desIn(51) desIn(52) desIn(53) desIn(54) desIn(55) desIn(56) desIn(57) desIn(58) desIn(59) desIn(60) desIn(61) desIn(62) desIn(63) key(0) key(1) key(2) key(3) key(4) key(5) key(6) key(7) key(8) key(9) key(10) key(11) key(12) key(13) key(14) key(15) key(16) key(17) key(18) key(19) key(20) key(21) key(22) key(23) key(24) key(25) key(26) key(27) key(28) key(29) key(30) key(31) key(32) key(33) key(34) key(35) key(36) key(37) key(38) key(39) key(40) key(41) key(42) key(43) key(44) key(45) key(46) key(47) key(48) key(49) key(50) key(51) key(52) key(53) key(54) key(55) decrypt clk
+.outputs desOut(0) desOut(1) desOut(2) desOut(3) desOut(4) desOut(5) desOut(6) desOut(7) desOut(8) desOut(9) desOut(10) desOut(11) desOut(12) desOut(13) desOut(14) desOut(15) desOut(16) desOut(17) desOut(18) desOut(19) desOut(20) desOut(21) desOut(22) desOut(23) desOut(24) desOut(25) desOut(26) desOut(27) desOut(28) desOut(29) desOut(30) desOut(31) desOut(32) desOut(33) desOut(34) desOut(35) desOut(36) desOut(37) desOut(38) desOut(39) desOut(40) desOut(41) desOut(42) desOut(43) desOut(44) desOut(45) desOut(46) desOut(47) desOut(48) desOut(49) desOut(50) desOut(51) desOut(52) desOut(53) desOut(54) desOut(55) desOut(56) desOut(57) desOut(58) desOut(59) desOut(60) desOut(61) desOut(62) desOut(63)
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_1 a=$auto$hilomap.cc:39:hilomap_worker$256819
+.subckt logic_0 a=K1(1)
+.subckt in_buff A=clk Q=uk.clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=decrypt Q=uk.decrypt
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(0) Q=$iopadmap$desIn(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(1) Q=$iopadmap$desIn(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(10) Q=$iopadmap$desIn(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(11) Q=$iopadmap$desIn(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(12) Q=$iopadmap$desIn(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(13) Q=$iopadmap$desIn(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(14) Q=$iopadmap$desIn(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(15) Q=$iopadmap$desIn(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(16) Q=$iopadmap$desIn(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(17) Q=$iopadmap$desIn(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(18) Q=$iopadmap$desIn(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(19) Q=$iopadmap$desIn(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(2) Q=$iopadmap$desIn(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(20) Q=$iopadmap$desIn(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(21) Q=$iopadmap$desIn(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(22) Q=$iopadmap$desIn(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(23) Q=$iopadmap$desIn(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(24) Q=$iopadmap$desIn(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(25) Q=$iopadmap$desIn(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(26) Q=$iopadmap$desIn(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(27) Q=$iopadmap$desIn(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(28) Q=$iopadmap$desIn(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(29) Q=$iopadmap$desIn(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(3) Q=$iopadmap$desIn(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(30) Q=$iopadmap$desIn(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(31) Q=$iopadmap$desIn(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(32) Q=$iopadmap$desIn(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(33) Q=$iopadmap$desIn(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(34) Q=$iopadmap$desIn(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(35) Q=$iopadmap$desIn(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(36) Q=$iopadmap$desIn(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(37) Q=$iopadmap$desIn(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(38) Q=$iopadmap$desIn(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(39) Q=$iopadmap$desIn(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(4) Q=$iopadmap$desIn(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(40) Q=$iopadmap$desIn(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(41) Q=$iopadmap$desIn(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(42) Q=$iopadmap$desIn(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(43) Q=$iopadmap$desIn(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(44) Q=$iopadmap$desIn(44)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(45) Q=$iopadmap$desIn(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(46) Q=$iopadmap$desIn(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(47) Q=$iopadmap$desIn(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(48) Q=$iopadmap$desIn(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(49) Q=$iopadmap$desIn(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(5) Q=$iopadmap$desIn(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(50) Q=$iopadmap$desIn(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(51) Q=$iopadmap$desIn(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(52) Q=$iopadmap$desIn(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(53) Q=$iopadmap$desIn(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(54) Q=$iopadmap$desIn(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(55) Q=$iopadmap$desIn(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(56) Q=$iopadmap$desIn(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(57) Q=$iopadmap$desIn(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(58) Q=$iopadmap$desIn(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(59) Q=$iopadmap$desIn(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(6) Q=$iopadmap$desIn(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(60) Q=$iopadmap$desIn(60)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=desIn(61) Q=$iopadmap$desIn(61)
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+.subckt in_buff A=key(32) Q=$iopadmap$key(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(33) Q=$iopadmap$key(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(34) Q=$iopadmap$key(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(35) Q=$iopadmap$key(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(36) Q=$iopadmap$key(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(37) Q=$iopadmap$key(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(38) Q=$iopadmap$key(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(39) Q=$iopadmap$key(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(4) Q=$iopadmap$key(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(40) Q=$iopadmap$key(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(41) Q=$iopadmap$key(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(42) Q=$iopadmap$key(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(43) Q=$iopadmap$key(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(44) Q=$iopadmap$key(44)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(45) Q=$iopadmap$key(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(46) Q=$iopadmap$key(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(47) Q=$iopadmap$key(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(48) Q=$iopadmap$key(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(49) Q=$iopadmap$key(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(5) Q=$iopadmap$key(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(50) Q=$iopadmap$key(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(51) Q=$iopadmap$key(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(52) Q=$iopadmap$key(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(53) Q=$iopadmap$key(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(54) Q=$iopadmap$key(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(55) Q=$iopadmap$key(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(6) Q=$iopadmap$key(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(7) Q=$iopadmap$key(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(8) Q=$iopadmap$key(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=key(9) Q=$iopadmap$key(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt LUT4 I0=FP_LUT4_O_I0 I1=FP_LUT4_O_I1 I2=FP_LUT4_O_I2 I3=L14(2) O=FP(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_I1_O I1=FP_LUT4_O_1_I1 I2=FP_LUT4_O_1_I2 I3=L14(10) O=FP(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=FP_LUT4_O_10_I0 I1=FP_LUT4_O_10_I1 I2=FP_LUT4_O_10_I2 I3=L14(7) O=FP(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_10_I0_LUT4_O_I1 I2=FP_LUT4_O_10_I0_LUT4_O_I2 I3=FP_LUT4_O_3_I3_LUT4_O_I1 O=FP_LUT4_O_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_I3_I1 I2=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_I3_I2 I3=FP_LUT4_O_10_I0_LUT4_O_I1 O=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=FP_LUT4_O_10_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I3=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_10_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I1 I2=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_10_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_10_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_10_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=FP_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_10_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I1 O=FP_LUT4_O_10_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_10_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0 I1=FP_LUT4_O_10_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I2 I3=FP_LUT4_O_31_I2_LUT4_O_I3 O=FP_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3 O=FP_LUT4_O_10_I1_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3 O=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r14(38) I1=uk.K_r14(31) I2=uk.decrypt I3=FP(61) O=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2 O=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2 O=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2 O=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r14(2) I1=uk.K_r14(50) I2=uk.decrypt I3=FP(56) O=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_10_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I3=FP_LUT4_O_10_I1_LUT4_I1_I2_LUT4_O_I3 O=FP_LUT4_O_10_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_10_I1_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_10_I1 I3=FP_LUT4_O_31_I2_LUT4_O_I2 O=FP_LUT4_O_14_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_10_I1_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I3=FP_LUT4_O_10_I1_LUT4_O_I3 O=FP_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_10_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O O=FP_LUT4_O_10_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I1_LUT4_I1_I2_LUT4_O_I3 I2=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_10_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_10_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_I2_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_31_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I2=FP_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O O=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=uk.K_r14(0) I1=uk.K_r14(52) I2=uk.decrypt I3=FP(59) O=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(42) I1=uk.K_r14(35) I2=uk.decrypt I3=FP(60) O=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(22) I1=uk.K_r14(15) I2=uk.decrypt I3=FP(58) O=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(37) I1=uk.K_r14(30) I2=uk.decrypt I3=FP(57) O=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_10_I2_LUT4_O_I0 I1=FP_LUT4_O_31_I2_LUT4_O_I1 I2=FP_LUT4_O_10_I2_LUT4_O_I2 I3=FP_LUT4_O_10_I2_LUT4_O_I3 O=FP_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_10_I2_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_10_I2_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_10_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=FP_LUT4_O_10_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_10_I1_LUT4_I1_I2_LUT4_O_I3 O=FP_LUT4_O_10_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=FP_LUT4_O_10_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_10_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_6_I0 I1=FP_LUT4_O_11_I1 I2=FP_LUT4_O_11_I2 I3=L14(8) O=FP(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_11_I1_LUT4_O_I2 I3=FP_LUT4_O_11_I1_LUT4_O_I3 O=FP_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I2_LUT4_O_I1 I2=FP_LUT4_O_25_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2 O=FP_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_23_I0 I1=FP_LUT4_O_12_I1 I2=FP_LUT4_O_12_I2 I3=L14(9) O=FP(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=FP_LUT4_O_23_I1_LUT4_O_I2 I1=FP_LUT4_O_23_I1_LUT4_O_I1 I2=FP_LUT4_O_12_I1_LUT4_O_I2 I3=FP_LUT4_O_12_I1_LUT4_O_I3 O=FP_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_12_I1_LUT4_O_I2 I3=FP_LUT4_O_12_I1_LUT4_O_I3 O=FP_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_23_I2_LUT4_O_I2 I3=FP_LUT4_O_2_I1_LUT4_O_I3 O=FP_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=FP_LUT4_O_13_I0 I1=FP_LUT4_O_13_I1 I2=FP_LUT4_O_13_I2 I3=L14(11) O=FP(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_20_I2_LUT4_O_I1 I2=FP_LUT4_O_13_I0_LUT4_O_I2 I3=FP_LUT4_O_13_I0_LUT4_O_I3 O=FP_LUT4_O_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=FP_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_13_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_20_I2_LUT4_O_I2 I3=FP_LUT4_O_29_I0_LUT4_O_I3 O=FP_LUT4_O_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_13_I1_LUT4_O_I1 I2=FP_LUT4_O_13_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I3 O=FP_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_13_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=uk.K_r14(9) I1=uk.K_r14(2) I2=uk.decrypt I3=FP(55) O=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(29) I1=uk.K_r14(22) I2=uk.decrypt I3=FP(53) O=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(51) I1=uk.K_r14(44) I2=uk.decrypt I3=FP(54) O=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(35) I1=uk.K_r14(28) I2=uk.decrypt I3=FP(56) O=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_20_I1_LUT4_O_I2 O=FP_LUT4_O_13_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_13_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_13_I2_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_13_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_13_I2_LUT4_O_I1 I2=FP_LUT4_O_13_I2_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L14(12) I2=FP_LUT4_O_14_I2 I3=FP_LUT4_O_14_I3 O=FP(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=FP_LUT4_O_31_I3_LUT4_O_I3 I1=FP_LUT4_O_3_I3_LUT4_O_I2_LUT4_I2_O I2=FP_LUT4_O_3_I2 I3=FP_LUT4_O_14_I2_LUT4_O_I3 O=FP_LUT4_O_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_14_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_14_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_14_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I3=FP_LUT4_O_10_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_14_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_14_I3_LUT4_O_I0 I1=FP_LUT4_O_3_I3_LUT4_O_I1 I2=FP_LUT4_O_14_I3_LUT4_O_I2 I3=FP_LUT4_O_3_I3_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_10_I2_LUT4_O_I0 I2=FP_LUT4_O_31_I2_LUT4_O_I1 I3=FP_LUT4_O_31_I2_LUT4_O_I3 O=FP_LUT4_O_14_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_15_I0 I1=FP_LUT4_O_15_I1 I2=FP_LUT4_O_15_I2 I3=L14(13) O=FP(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=FP_LUT4_O_15_I0_LUT4_O_I0 I1=FP_LUT4_O_I0_LUT4_O_I3 I2=FP_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_15_I0_LUT4_O_I3 O=FP_LUT4_O_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I2=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_19_I2_LUT4_O_I2 O=FP_LUT4_O_15_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_15_I0_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_15_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_15_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_15_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_15_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=FP_LUT4_O_15_I2_LUT4_O_I2 I2=FP_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_15_I1_LUT4_O_I3 O=FP_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_15_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=FP_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_15_I2_LUT4_O_I1 I2=FP_LUT4_O_15_I2_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_15_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_28_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L14(14) I3=FP_LUT4_O_16_I3 O=FP(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=FP_LUT4_O_6_I0_LUT4_O_I3 I1=FP_LUT4_O_25_I1 I2=FP_LUT4_O_16_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I0_LUT4_O_I1 O=FP_LUT4_O_16_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 I1=FP_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_11_I1_LUT4_O_I2 O=FP_LUT4_O_16_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_17_I0 I1=FP_LUT4_O_17_I1 I2=FP_LUT4_O_17_I2 I3=L14(15) O=FP(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_8_I0_LUT4_O_I2 I2=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_I0_O I3=FP_LUT4_O_8_I0_LUT4_O_I0 O=FP_LUT4_O_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_8_I2_LUT4_O_I2 I1=FP_LUT4_O_17_I1_LUT4_O_I1 I2=FP_LUT4_O_27_I2_LUT4_O_I1 I3=FP_LUT4_O_22_I2_LUT4_O_I2 O=FP_LUT4_O_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_17_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_17_I2_LUT4_O_I1 I2=FP_LUT4_O_17_I2_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I0 O=FP_LUT4_O_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_17_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_17_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_17_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_17_I2_LUT4_O_I2 I1=FP_LUT4_O_22_I1_LUT4_O_I2 I2=FP_LUT4_O_17_I2_LUT4_O_I1 I3=FP_LUT4_O_22_I1_LUT4_O_I3 O=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_8_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_18_I0 I1=FP_LUT4_O_18_I1 I2=FP_LUT4_O_18_I2 I3=L14(16) O=FP(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_9_I0_LUT4_O_I3 I3=FP_LUT4_O_30_I0_LUT4_O_I2 O=FP_LUT4_O_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_18_I1_LUT4_O_I2 I3=FP_LUT4_O_18_I1_LUT4_O_I3 O=FP_LUT4_O_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_9_I0_LUT4_O_I1 I3=FP_LUT4_O_18_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_18_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_9_I2_LUT4_I3_I2_LUT4_O_I1 I3=FP_LUT4_O_18_I2_LUT4_O_I0 O=FP_LUT4_O_18_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=FP_LUT4_O_30_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I2=FP_LUT4_O_18_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I3 O=FP_LUT4_O_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_18_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r14(5) I1=uk.K_r14(55) I2=uk.decrypt I3=FP(45) O=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2 O=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r14(53) I1=uk.K_r14(46) I2=uk.decrypt I3=FP(40) O=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_9_I0_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0 I3=FP_LUT4_O_18_I2_LUT4_O_I2 O=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_18_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=uk.K_r14(34) I1=uk.K_r14(27) I2=uk.decrypt I3=FP(43) O=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(17) I1=uk.K_r14(10) I2=uk.decrypt I3=FP(44) O=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(25) I1=uk.K_r14(18) I2=uk.decrypt I3=FP(41) O=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(33) I1=uk.K_r14(26) I2=uk.decrypt I3=FP(42) O=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_18_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_18_I2_LUT4_O_I0 O=FP_LUT4_O_18_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 O=FP_LUT4_O_18_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L14(18) I2=FP_LUT4_O_19_I2 I3=FP_LUT4_O_19_I3 O=FP(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I1 I2=FP_LUT4_O_19_I2_LUT4_O_I2 I3=FP_LUT4_O_28_I0_LUT4_O_I3 O=FP_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_19_I3_LUT4_O_I1 I2=FP_LUT4_O_15_I1 I3=FP_LUT4_O_28_I1_LUT4_O_I3 O=FP_LUT4_O_19_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_19_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_1_I1_LUT4_O_I0 I1=FP_LUT4_O_1_I1_LUT4_O_I1 I2=FP_LUT4_O_1_I1_LUT4_O_I2 I3=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=FP_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I3 I2=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_5_I3_LUT4_O_I0 O=FP_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 O=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I3 O=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 O=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_5_I2_LUT4_O_I2 I1=FP_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_21_I1_LUT4_O_I2 I3=FP_LUT4_O_1_I2_LUT4_O_I1 O=FP_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I3 I1=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 O=FP_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_1_I2_LUT4_O_I1 I2=FP_LUT4_O_1_I2_LUT4_O_I2 I3=FP_LUT4_O_1_I2_LUT4_O_I3 O=FP_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I3 I1=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_1_I2_LUT4_O_I3 I1=FP_LUT4_O_1_I2_LUT4_O_I2 I2=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_I1_I2 I3=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_I1_I3 O=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I3 I1=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2 I3=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I3 O=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_5_I2_LUT4_O_I1 I3=FP_LUT4_O_21_I0_LUT4_O_I2 O=FP_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_2_I0 I1=FP_LUT4_O_2_I1 I2=FP_LUT4_O_2_I2 I3=L14(17) O=FP(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=FP_LUT4_O_7_I0 I1=FP_LUT4_O_20_I1 I2=FP_LUT4_O_20_I2 I3=L14(19) O=FP(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_20_I1_LUT4_O_I1 I2=FP_LUT4_O_20_I1_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3 O=FP_LUT4_O_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_20_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_13_I2_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_20_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_20_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_13_I1_LUT4_O_I1 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_20_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_20_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_20_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_20_I2_LUT4_O_I1 I2=FP_LUT4_O_20_I2_LUT4_O_I2 I3=FP_LUT4_O_7_I2_LUT4_O_I0 O=FP_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_20_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_20_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_20_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_20_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_20_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_21_I0 I1=FP_LUT4_O_21_I1 I2=FP_LUT4_O_21_I2 I3=L14(20) O=FP(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_21_I0_LUT4_O_I2 I3=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_I1_O O=FP_LUT4_O_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_21_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_21_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_21_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_21_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I3 I2=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_21_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_21_I1_LUT4_O_I2 I3=FP_LUT4_O_5_I2_LUT4_O_I2 O=FP_LUT4_O_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_21_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_21_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_21_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I3 I1=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_21_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_21_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_5_I3_LUT4_O_I1 I2=FP_LUT4_O_26_I2 I3=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=FP_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_8_I0 I1=FP_LUT4_O_22_I1 I2=FP_LUT4_O_22_I2 I3=L14(21) O=FP(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I1 I1=FP_LUT4_O_8_I0_LUT4_O_I2 I2=FP_LUT4_O_22_I1_LUT4_O_I2 I3=FP_LUT4_O_22_I1_LUT4_O_I3 O=FP_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_22_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_22_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_22_I2_LUT4_O_I2 I3=FP_LUT4_O_27_I2_LUT4_O_I3 O=FP_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_22_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_27_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_23_I0 I1=FP_LUT4_O_23_I1 I2=FP_LUT4_O_23_I2 I3=L14(23) O=FP(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I0 I1=FP_LUT4_O_2_I0_LUT4_O_I2 I2=FP_LUT4_O_23_I0_LUT4_O_I2 I3=FP_LUT4_O_23_I0_LUT4_O_I3 O=FP_LUT4_O_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_23_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_23_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I1 I1=FP_LUT4_O_23_I1_LUT4_O_I1 I2=FP_LUT4_O_23_I1_LUT4_O_I2 I3=FP_LUT4_O_23_I1_LUT4_O_I3 O=FP_LUT4_O_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_23_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_23_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_23_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_23_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_23_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_23_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_23_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_23_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I0 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_23_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_23_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_2_I0_LUT4_O_I2 I2=FP_LUT4_O_23_I2_LUT4_O_I2 I3=FP_LUT4_O_2_I1_LUT4_O_I2 O=FP_LUT4_O_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_23_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_23_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_23_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_23_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_23_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_24_I0 I1=FP_LUT4_O_24_I1 I2=FP_LUT4_O_24_I2 I3=L14(24) O=FP(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_18_I1_LUT4_O_I2 I2=FP_LUT4_O_24_I0_LUT4_O_I2 I3=FP_LUT4_O_24_I0_LUT4_O_I3 O=FP_LUT4_O_24_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=FP_LUT4_O_24_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_24_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_24_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_24_I0_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_9_I0_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_24_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0 I3=FP_LUT4_O_18_I2_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_24_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_24_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_24_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000001
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_24_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_30_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_24_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_24_I1_LUT4_O_I1 I2=FP_LUT4_O_24_I1_LUT4_O_I2 I3=FP_LUT4_O_9_I1 O=FP_LUT4_O_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_9_I0_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_24_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_9_I2_LUT4_I3_I2_LUT4_O_I1 I2=FP_LUT4_O_9_I2_LUT4_I3_I1_LUT4_O_I1 I3=FP_LUT4_O_18_I2_LUT4_O_I0 O=FP_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_9_I1_LUT4_O_I2 O=FP_LUT4_O_24_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_18_I2 I2=FP_LUT4_O_30_I1_LUT4_O_I1 I3=FP_LUT4_O_30_I1_LUT4_O_I0 O=FP_LUT4_O_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_25_I0 I1=FP_LUT4_O_25_I1 I2=FP_LUT4_O_25_I2 I3=L14(25) O=FP(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=FP_LUT4_O_6_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I0_LUT4_O_I1 I2=FP_LUT4_O_6_I0_LUT4_O_I3 I3=FP_LUT4_O_6_I0_LUT4_O_I2 O=FP_LUT4_O_25_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_11_I1_LUT4_O_I3 I3=FP_LUT4_O_6_I1_LUT4_O_I2 O=FP_LUT4_O_25_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_25_I1_LUT4_O_I1 I2=FP_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I0 I3=FP_LUT4_O_25_I1_LUT4_O_I3 O=FP_LUT4_O_25_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_25_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I1 O=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_25_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r14(52) I1=uk.K_r14(45) I2=uk.decrypt I3=FP(53) O=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(36) I1=uk.K_r14(29) I2=uk.decrypt I3=FP(48) O=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_25_I2_LUT4_I1_I0 I1=FP_LUT4_O_25_I2 I2=FP_LUT4_O_6_I2_LUT4_O_I2 I3=FP_LUT4_O_25_I2_LUT4_I1_I3 O=FP_LUT4_O_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_25_I2_LUT4_I1_I0_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I1 I2=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_25_I2_LUT4_O_I2 I3=FP_LUT4_O_25_I2_LUT4_O_I3 O=FP_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_26_I0 I1=FP_LUT4_O_26_I1 I2=FP_LUT4_O_26_I2 I3=L14(26) O=FP(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_I1_O I1=FP_LUT4_O_1_I1_LUT4_O_I2 I2=FP_LUT4_O_21_I1 I3=FP_LUT4_O_1_I2_LUT4_O_I3 O=FP_LUT4_O_26_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_26_I1_LUT4_O_I1 I2=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I3=FP_LUT4_O_26_I1_LUT4_O_I3 O=FP_LUT4_O_26_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_26_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I2=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_26_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_26_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I3 O=FP_LUT4_O_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_26_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I2=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_26_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=uk.K_r14(55) I1=uk.K_r14(48) I2=uk.decrypt I3=FP(45) O=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(24) I1=uk.K_r14(17) I2=uk.decrypt I3=FP(46) O=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(32) I1=uk.K_r14(25) I2=uk.decrypt I3=FP(47) O=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(40) I1=uk.K_r14(33) I2=uk.decrypt I3=FP(48) O=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_26_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r14(20) I1=uk.K_r14(13) I2=uk.decrypt I3=FP(49) O=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(4) I1=uk.K_r14(54) I2=uk.decrypt I3=FP(44) O=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=L14(27) I2=FP_LUT4_O_27_I2 I3=FP_LUT4_O_27_I3 O=FP(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_27_I2_LUT4_O_I1 I2=FP_LUT4_O_27_I2_LUT4_O_I2 I3=FP_LUT4_O_27_I2_LUT4_O_I3 O=FP_LUT4_O_27_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_27_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_27_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_27_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_27_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_27_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_27_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_27_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_17_I1_LUT4_O_I1 I3=FP_LUT4_O_27_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_27_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_27_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_27_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 O=FP_LUT4_O_27_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_27_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_27_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_8_I0_LUT4_O_I3 I2=FP_LUT4_O_8_I0_LUT4_O_I2 I3=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_I0_O O=FP_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=FP_LUT4_O_28_I0 I1=FP_LUT4_O_28_I1 I2=FP_LUT4_O_28_I2 I3=L14(28) O=FP(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_I0_LUT4_O_I0 I3=FP_LUT4_O_28_I0_LUT4_O_I3 O=FP_LUT4_O_28_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_15_I2 I2=FP_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_28_I1_LUT4_O_I3 O=FP_LUT4_O_28_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_28_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_28_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_28_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_28_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_28_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_28_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_28_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_I0_LUT4_O_I1 I3=FP_LUT4_O_15_I0_LUT4_O_I0 O=FP_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_29_I0 I1=FP_LUT4_O_7_I0 I2=FP_LUT4_O_29_I2 I3=L14(29) O=FP(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=FP_LUT4_O_13_I0 I1=FP_LUT4_O_29_I0_LUT4_O_I1 I2=FP_LUT4_O_7_I2_LUT4_O_I1 I3=FP_LUT4_O_29_I0_LUT4_O_I3 O=FP_LUT4_O_29_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_7_I2_LUT4_O_I1 I3=FP_LUT4_O_29_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_29_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=FP_LUT4_O_29_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_29_I0_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_29_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_29_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I0 I2=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_29_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_29_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_13_I1_LUT4_O_I2 I3=FP_LUT4_O_20_I1_LUT4_O_I1 O=FP_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I0 I1=FP_LUT4_O_2_I0_LUT4_O_I1 I2=FP_LUT4_O_2_I0_LUT4_O_I2 I3=FP_LUT4_O_2_I0_LUT4_O_I3 O=FP_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=FP_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_2_I1_LUT4_O_I2 I3=FP_LUT4_O_2_I1_LUT4_O_I3 O=FP_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_2_I2_LUT4_O_I2 I3=FP_LUT4_O_4_I1_LUT4_O_I3 O=FP_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I1=FP_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L14(22) I2=FP_LUT4_O_3_I2 I3=FP_LUT4_O_3_I3 O=FP(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=FP_LUT4_O_30_I0 I1=FP_LUT4_O_30_I1 I2=FP_LUT4_O_18_I1 I3=L14(30) O=FP(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_30_I0_LUT4_O_I2 I3=FP_LUT4_O_9_I0_LUT4_O_I2 O=FP_LUT4_O_30_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_24_I1_LUT4_O_I2 I3=FP_LUT4_O_24_I1_LUT4_O_I1 O=FP_LUT4_O_30_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_30_I1_LUT4_O_I0 I1=FP_LUT4_O_30_I1_LUT4_O_I1 I2=FP_LUT4_O_30_I1_LUT4_O_I2 I3=FP_LUT4_O_30_I1_LUT4_O_I3 O=FP_LUT4_O_30_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_30_I1_LUT4_O_I0_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_30_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_I3_O I2=FP_LUT4_O_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_30_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_30_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_30_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_30_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_9_I2_LUT4_I3_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0 I3=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_30_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L14(32) I2=FP_LUT4_O_31_I2 I3=FP_LUT4_O_31_I3 O=FP(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_31_I2_LUT4_O_I1 I2=FP_LUT4_O_31_I2_LUT4_O_I2 I3=FP_LUT4_O_31_I2_LUT4_O_I3 O=FP_LUT4_O_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=FP_LUT4_O_31_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011001100110101
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_10_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I3=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I3=FP_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_31_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O O=FP_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_31_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_31_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I2_LUT4_O_I0 O=FP_LUT4_O_31_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=FP_LUT4_O_10_I2_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_31_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I3=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_31_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_3_I2 I1=FP_LUT4_O_3_I3_LUT4_O_I2_LUT4_I2_O I2=FP_LUT4_O_31_I3_LUT4_O_I2 I3=FP_LUT4_O_31_I3_LUT4_O_I3 O=FP_LUT4_O_31_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_31_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I3=FP_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I1 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_10_I0_LUT4_O_I1 I3=FP_LUT4_O_31_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_31_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_3_I2_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_10_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=FP_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_3_I3_LUT4_O_I0 I1=FP_LUT4_O_3_I3_LUT4_O_I1 I2=FP_LUT4_O_3_I3_LUT4_O_I2 I3=FP_LUT4_O_3_I3_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=FP_LUT4_O_3_I2 I1=FP_LUT4_O_14_I2_LUT4_O_I3 I2=FP_LUT4_O_31_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I0_LUT4_O_I2 O=FP_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_I3_O I2=FP_LUT4_O_3_I3_LUT4_O_I2 I3=FP_LUT4_O_31_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_3_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I3=FP_LUT4_O_10_I1_LUT4_O_I3 O=FP_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_10_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_10_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_10_I1_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=FP_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0 I1=FP_LUT4_O_4_I1 I2=FP_LUT4_O_4_I2 I3=L14(31) O=FP(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I2 I3=FP_LUT4_O_2_I1_LUT4_O_I3 O=FP_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=FP_LUT4_O_2_I1_LUT4_O_I3 I1=FP_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I2=FP_LUT4_O_2_I1_LUT4_O_I2 I3=FP_LUT4_O_23_I2_LUT4_O_I2 O=FP_LUT4_O_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=FP_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 I1=FP_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r14(47) I1=uk.K_r14(40) I2=uk.decrypt I3=FP(64) O=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r14(41) I1=uk.K_r14(34) I2=uk.decrypt I3=FP(37) O=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=uk.K_r14(11) I1=uk.K_r14(4) I2=uk.decrypt I3=FP(33) O=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(13) I1=uk.K_r14(6) I2=uk.decrypt I3=FP(36) O=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(3) I1=uk.K_r14(53) I2=uk.decrypt I3=FP(35) O=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(26) I1=uk.K_r14(19) I2=uk.decrypt I3=FP(34) O=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_4_I1_LUT4_O_I1 I2=FP_LUT4_O_4_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I1_LUT4_O_I3 O=FP_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=FP_LUT4_O_23_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I0 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_4_I2 I2=FP_LUT4_O_2_I2_LUT4_O_I2 I3=FP_LUT4_O_23_I1_LUT4_O_I3 O=FP_LUT4_O_23_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_4_I2_LUT4_O_I2 I3=FP_LUT4_O_4_I2_LUT4_O_I3 O=FP_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_4_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L14(1) I2=FP_LUT4_O_5_I2 I3=FP_LUT4_O_5_I3 O=FP(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_5_I2_LUT4_O_I1 I2=FP_LUT4_O_5_I2_LUT4_O_I2 I3=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_I1_O O=FP_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I3 I1=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I0 I3=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1 I2=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I3 I1=FP_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2 I3=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I3 O=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 O=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 O=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=FP_LUT4_O_5_I3_LUT4_O_I0 I1=FP_LUT4_O_5_I3_LUT4_O_I1 I2=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I3=FP_LUT4_O_26_I1 O=FP_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I3 I1=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_26_I2_LUT4_O_I3 I1=FP_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I0 I1=FP_LUT4_O_6_I1 I2=FP_LUT4_O_6_I2 I3=L14(3) O=FP(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I0_LUT4_O_I1 I2=FP_LUT4_O_6_I0_LUT4_O_I2 I3=FP_LUT4_O_6_I0_LUT4_O_I3 O=FP_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_6_I2_LUT4_O_I1 I3=FP_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_25_I1_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_25_I1 I1=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_25_I1_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_25_I2_LUT4_I1_I0_LUT4_O_I2 O=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I3 I2=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_6_I1_LUT4_O_I2 I3=FP_LUT4_O_6_I1_LUT4_O_I3 O=FP_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I3 I2=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I3 I3=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I2_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I3 O=FP_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_I1_I0_LUT4_O_I2 I2=FP_LUT4_O_25_I2_LUT4_I1_I3_LUT4_O_I1 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_25_I1_LUT4_O_I3 I1=FP_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_25_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_25_I2_LUT4_I1_I0_LUT4_O_I2 O=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=uk.K_r14(8) I1=uk.K_r14(1) I2=uk.decrypt I3=FP(51) O=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(23) I1=uk.K_r14(16) I2=uk.decrypt I3=FP(52) O=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(21) I1=uk.K_r14(14) I2=uk.decrypt I3=FP(50) O=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(31) I1=uk.K_r14(51) I2=uk.decrypt I3=FP(49) O=FP_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_25_I1 O=FP_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_7_I0 I1=FP_LUT4_O_7_I1 I2=FP_LUT4_O_7_I2 I3=L14(4) O=FP(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_7_I0_LUT4_O_I1 I2=FP_LUT4_O_13_I1 I3=FP_LUT4_O_7_I0_LUT4_O_I3 O=FP_LUT4_O_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_7_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_20_I1_LUT4_O_I1 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_7_I1_LUT4_O_I1 O=FP_LUT4_O_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_13_I2_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r14(14) I1=uk.K_r14(7) I2=uk.decrypt I3=FP(52) O=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r14(30) I1=uk.K_r14(23) I2=uk.decrypt I3=FP(57) O=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_7_I1_LUT4_O_I1 I2=FP_LUT4_O_7_I1_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I1 O=FP_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_13_I1_LUT4_O_I1 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_13_I1_LUT4_O_I1 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_7_I2_LUT4_O_I0 I1=FP_LUT4_O_7_I2_LUT4_O_I1 I2=FP_LUT4_O_7_I2_LUT4_O_I2 I3=FP_LUT4_O_7_I2_LUT4_O_I3 O=FP_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_13_I0_LUT4_O_I3 I3=FP_LUT4_O_29_I0_LUT4_O_I1 O=FP_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 O=FP_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I2=FP_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_7_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 O=FP_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I1 I1=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I0 I2=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_13_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=FP_LUT4_O_8_I0 I1=FP_LUT4_O_8_I1 I2=FP_LUT4_O_8_I2 I3=L14(5) O=FP(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=FP_LUT4_O_8_I0_LUT4_O_I0 I1=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_I0_O I2=FP_LUT4_O_8_I0_LUT4_O_I2 I3=FP_LUT4_O_8_I0_LUT4_O_I3 O=FP_LUT4_O_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I1 I2=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I2 O=FP_LUT4_O_8_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_17_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_I1_O I3=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_17_I2_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I3 O=FP_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_8_I1_LUT4_O_I2 I2=FP_LUT4_O_17_I2_LUT4_O_I2_LUT4_I0_O I3=FP_LUT4_O_8_I0_LUT4_O_I0_LUT4_O_I0 O=FP_LUT4_O_8_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_8_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_8_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 O=FP_LUT4_O_8_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_17_I2_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_8_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_8_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_8_I1_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r14(16) I1=uk.K_r14(9) I2=uk.decrypt I3=FP(60) O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(28) I1=uk.K_r14(21) I2=uk.decrypt I3=FP(33) O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=uk.K_r14(43) I1=uk.K_r14(36) I2=uk.decrypt I3=FP(61) O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(7) I1=uk.K_r14(0) I2=uk.decrypt I3=FP(64) O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(44) I1=uk.K_r14(37) I2=uk.decrypt I3=FP(62) O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(1) I1=uk.K_r14(49) I2=uk.decrypt I3=FP(63) O=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_8_I2_LUT4_O_I2 I3=FP_LUT4_O_8_I2_LUT4_O_I3 O=FP_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 O=FP_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_27_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_27_I2_LUT4_O_I2 I1=FP_LUT4_O_17_I1_LUT4_O_I1 I2=FP_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_9_I0 I1=FP_LUT4_O_9_I1 I2=FP_LUT4_O_9_I2 I3=L14(6) O=FP(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=FP_LUT4_O_9_I0_LUT4_O_I0 I1=FP_LUT4_O_9_I0_LUT4_O_I1 I2=FP_LUT4_O_9_I0_LUT4_O_I2 I3=FP_LUT4_O_9_I0_LUT4_O_I3 O=FP_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=FP_LUT4_O_24_I0_LUT4_O_I3 I1=FP_LUT4_O_30_I1_LUT4_O_I0 I2=FP_LUT4_O_18_I1_LUT4_O_I3 I3=FP_LUT4_O_9_I0_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_9_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I2=FP_LUT4_O_18_I2_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_9_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_9_I0_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=FP_LUT4_O_9_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_9_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_9_I0_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_24_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_9_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I0 I2=FP_LUT4_O_30_I1_LUT4_O_I1 I3=FP_LUT4_O_9_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_9_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_9_I1_LUT4_I3_I1 I2=FP_LUT4_O_24_I1_LUT4_O_I1 I3=FP_LUT4_O_9_I1 O=FP_LUT4_O_9_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=FP_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_9_I1_LUT4_I3_I1_LUT4_O_I3 O=FP_LUT4_O_9_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_9_I2_LUT4_I3_I1_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_9_I1_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_9_I1_LUT4_O_I2 I3=FP_LUT4_O_9_I1_LUT4_O_I3 O=FP_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=FP_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I2=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_9_I2_LUT4_I3_I1_LUT4_O_I1 I2=FP_LUT4_O_9_I0_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_18_I2_LUT4_O_I0 O=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_9_I2_LUT4_I3_I1 I2=FP_LUT4_O_9_I2_LUT4_I3_I2 I3=FP_LUT4_O_9_I2 O=FP_LUT4_O_30_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_9_I2_LUT4_I3_I1_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=FP_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2 O=FP_LUT4_O_9_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 O=FP_LUT4_O_9_I2_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_9_I2_LUT4_I3_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I0 I3=FP_LUT4_O_24_I0_LUT4_O_I2_LUT4_O_I2 O=FP_LUT4_O_9_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 O=FP_LUT4_O_9_I2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_9_I2_LUT4_O_I2 I3=FP_LUT4_O_9_I2_LUT4_O_I3 O=FP_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0 O=FP_LUT4_O_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_9_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 O=FP_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I1 I1=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I0 I2=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_18_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_I0_LUT4_O_I0 I1=FP_LUT4_O_I0_LUT4_O_I1 I2=FP_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=FP_LUT4_O_19_I2_LUT4_O_I2 I1=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I2 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_15_I2_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=FP_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_28_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=FP_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I0_LUT4_O_I2 I2=FP_LUT4_O_I1 I3=FP_LUT4_O_I0_LUT4_O_I1 O=FP_LUT4_O_28_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=FP_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=FP_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=uk.K_r14(6) I1=uk.K_r14(24) I2=uk.decrypt I3=FP(37) O=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(54) I1=uk.K_r14(47) I2=uk.decrypt I3=FP(38) O=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(39) I1=uk.K_r14(32) I2=uk.decrypt I3=FP(40) O=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r14(48) I1=uk.K_r14(41) I2=uk.decrypt I3=FP(39) O=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0 I1=FP_LUT4_O_I2_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3 I1=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r14(19) I1=uk.K_r14(12) I2=uk.decrypt I3=FP(41) O=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r14(27) I1=uk.K_r14(20) I2=uk.decrypt I3=FP(36) O=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I3=FP_LUT4_O_I1_LUT4_O_I3 O=FP_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=FP_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=FP_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=FP_LUT4_O_15_I2_LUT4_O_I2 I2=FP_LUT4_O_19_I3_LUT4_O_I1 I3=FP_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=FP_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=FP_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=FP_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=FP_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=FP_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O O=FP_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=FP_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=FP_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=FP_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L0(2) I2=L0_LUT4_I1_I2 I3=L0_LUT4_I1_I3 O=R1_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L0(6) I2=L0_LUT4_I1_1_I2 I3=L0_LUT4_I1_1_I3 O=R1_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L0(30) I2=L0_LUT4_I1_10_I2 I3=L0_LUT4_I3_9_I0 O=R1_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_8_I2_LUT4_O_I2 I2=L0_LUT4_I1_8_I2_LUT4_O_I1 I3=L0_LUT4_I3_9_I2_LUT4_O_I3 O=L0_LUT4_I1_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L0(31) I2=L0_LUT4_I1_11_I2 I3=L0_LUT4_I1_11_I3 O=R1_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=L0_LUT4_I3_6_I1_LUT4_O_I0 I1=L0_LUT4_I1_11_I2_LUT4_O_I1 I2=L0_LUT4_I1_11_I2_LUT4_O_I2 I3=L0_LUT4_I1_11_I2_LUT4_O_I3 O=L0_LUT4_I1_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_11_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_11_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_11_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I1 I3=R0_LUT4_I3_40_O_LUT4_I2_1_O O=L0_LUT4_I1_11_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_41_O_LUT4_I2_O I1=L0_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_2_O I3=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 O=L0_LUT4_I1_11_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_11_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_1_O I3=L0_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 O=L0_LUT4_I1_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_11_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R0_LUT4_I3_40_O_LUT4_I2_O O=L0_LUT4_I1_11_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_41_O_LUT4_I2_O I1=L0_LUT4_I1_11_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_2_O I3=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I1 O=L0_LUT4_I1_11_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_6_I1_LUT4_O_I2 I1=L0_LUT4_I3_6_I1_LUT4_O_I3 I2=L0_LUT4_I1_11_I2_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I1_11_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_11_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2 I2=R0_LUT4_I3_40_O_LUT4_I2_2_O I3=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_11_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_41_O_LUT4_I2_O I1=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R0_LUT4_I3_40_O_LUT4_I2_1_O I3=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_11_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I1_11_I3_LUT4_O_I0 I1=L0_LUT4_I1_11_I3_LUT4_O_I1 I2=L0_LUT4_I2_I3_LUT4_O_I1 I3=L0_LUT4_I3_6_I2_LUT4_O_I3 O=L0_LUT4_I1_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_2_O I1=L0_LUT4_I1_11_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_1_O I3=L0_LUT4_I1_11_I3_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I1_11_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_38_O I1=R0_LUT4_I3_37_O I2=R0_LUT4_I3_36_O I3=R0_LUT4_I3_39_O O=L0_LUT4_I1_11_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_41_O_LUT4_I2_O I1=L0_LUT4_I1_11_I3_LUT4_O_I0_LUT4_O_I3 I2=L0_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I3=R0_LUT4_I3_40_O_LUT4_I2_1_O O=L0_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_39_O I1=R0_LUT4_I3_38_O I2=R0_LUT4_I3_37_O I3=R0_LUT4_I3_36_O O=L0_LUT4_I1_11_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_41_O_LUT4_I2_O O=L0_LUT4_I1_11_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_37_O I1=R0_LUT4_I3_38_O I2=R0_LUT4_I3_39_O I3=R0_LUT4_I3_36_O O=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_39_O I1=R0_LUT4_I3_38_O I2=R0_LUT4_I3_36_O I3=R0_LUT4_I3_37_O O=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_1_I2 I3=L0_LUT4_I1_1_I3_LUT4_O_I2 O=L0_LUT4_I3_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_1_I2 I3=L0_LUT4_I1_1_I3_LUT4_O_I2 O=L0_LUT4_I3_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_1_I2_LUT4_O_I1 I2=L0_LUT4_I1_1_I2_LUT4_O_I2 I3=R0_LUT4_I3_34_O_LUT4_I2_O O=L0_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_35_O_LUT4_I2_O I3=L0_LUT4_I1_8_I3_LUT4_O_I0_LUT4_O_I0 O=L0_LUT4_I1_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_8_I3_LUT4_O_I0_LUT4_O_I3 I3=R0_LUT4_I3_34_O_LUT4_I2_2_O O=L0_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_30_O I1=R0_LUT4_I3_32_O I2=R0_LUT4_I3_31_O I3=R0_LUT4_I3_33_O O=L0_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_33_O I1=R0_LUT4_I3_32_O I2=R0_LUT4_I3_31_O I3=R0_LUT4_I3_30_O O=L0_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L0_LUT4_I3_9_I1_LUT4_O_I2 I1=L0_LUT4_I1_1_I3_LUT4_O_I1 I2=L0_LUT4_I1_1_I3_LUT4_O_I2 I3=L0_LUT4_I1_1_I3_LUT4_O_I3 O=L0_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L0_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I1=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I1_8_I2_LUT4_O_I1 I3=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_35_O_LUT4_I2_O I3=L0_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R0_LUT4_I3_34_O_LUT4_I2_2_O I3=L0_LUT4_I1_1_I2_LUT4_O_I2 O=L0_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_8_I3_LUT4_O_I0 I2=L0_LUT4_I1_8_I3_LUT4_O_I1 I3=L0_LUT4_I3_9_I0_LUT4_O_I2 O=L0_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L0(10) I2=L0_LUT4_I1_2_I2 I3=L0_LUT4_I1_2_I3 O=R1_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_2_I2_LUT4_O_I1 I2=L0_LUT4_I1_2_I2_LUT4_O_I2 I3=L0_LUT4_I1_2_I2_LUT4_O_I3 O=L0_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_10_O_LUT4_I2_2_O I3=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_7_O I1=R0_LUT4_I3_8_O I2=R0_LUT4_I3_9_O I3=R0_LUT4_I3_6_O O=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_9_O I1=R0_LUT4_I3_8_O I2=R0_LUT4_I3_7_O I3=R0_LUT4_I3_6_O O=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_10_O_LUT4_I2_1_O I2=R0_LUT4_I3_11_O_LUT4_I2_O I3=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I1 O=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_8_O I1=R0_LUT4_I3_7_O I2=R0_LUT4_I3_6_O I3=R0_LUT4_I3_9_O O=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_9_O I1=R0_LUT4_I3_8_O I2=R0_LUT4_I3_7_O I3=R0_LUT4_I3_6_O O=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I3_13_I1_LUT4_O_I0 I2=R0_LUT4_I3_11_O_LUT4_I2_O I3=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_8_O I1=R0_LUT4_I3_6_O I2=R0_LUT4_I3_7_O I3=R0_LUT4_I3_9_O O=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I1_2_I2_LUT4_O_I3 I3=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_I3 O=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I2 I3=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3 O=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=R0_LUT4_I3_10_O_LUT4_I2_1_O I2=L0_LUT4_I3_13_I1_LUT4_O_I0 I3=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=L0_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_11_O_LUT4_I2_O I3=L0_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 O=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I0 I1=L0_LUT4_I3_11_I0_LUT4_O_I2 I2=L0_LUT4_I3_11_I0_LUT4_O_I1 I3=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I3_13_I2_LUT4_O_I0 I2=R0_LUT4_I3_10_O_LUT4_I2_2_O I3=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_11_O_LUT4_I2_O I1=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I1 O=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I1_2_I3_LUT4_O_I0 I1=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_O I2=L0_LUT4_I1_2_I3_LUT4_O_I2 I3=L0_LUT4_I1_2_I3_LUT4_O_I3 O=L0_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I0 I1=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_LUT4_I3_10_O I3=R0_LUT4_I3_11_O O=L0_LUT4_I1_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=R0_LUT4_I3_9_O I1=R0_LUT4_I3_8_O I2=R0_LUT4_I3_7_O I3=R0_LUT4_I3_6_O O=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_9_O I1=R0_LUT4_I3_6_O I2=R0_LUT4_I3_7_O I3=R0_LUT4_I3_8_O O=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L0_LUT4_I3_13_I1_LUT4_O_I2 I1=L0_LUT4_I3_13_I2_LUT4_O_I2 I2=L0_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_4_I2_LUT4_O_I1 O=L0_LUT4_I1_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_11_O_LUT4_I2_O I1=L0_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I1_4_I3_LUT4_O_I2 I1=L0_LUT4_I1_2_I3_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_11_I1_LUT4_O_I2 I3=L0_LUT4_I1_2_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=L0_LUT4_I3_13_I2_LUT4_O_I0 I2=R0_LUT4_I3_11_O I3=R0_LUT4_I3_10_O O=L0_LUT4_I1_2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I0 I2=R0_LUT4_I3_11_O_LUT4_I2_O I3=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=L0_LUT4_I1_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0(22) I2=L0_LUT4_I1_3_I2 I3=L0_LUT4_I1_3_I3 O=R1_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_3_I2_LUT4_O_I1 I2=L0_LUT4_I1_3_I2_LUT4_O_I2 I3=L0_LUT4_I3_I0_LUT4_O_I3 O=L0_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_I2_I1 I2=L0_LUT4_I1_3_I2_LUT4_O_I1 I3=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_I2_I3 O=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_17_I2_LUT4_O_I2 I3=R0_LUT4_I3_46_O_LUT4_I2_2_O O=L0_LUT4_I1_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_47_O_LUT4_I2_O I3=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_O I1=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_46_O_LUT4_I2_1_O I3=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_2_O I1=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3 O=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_1_O I1=L0_LUT4_I3_17_I2_LUT4_O_I2 I2=R0_LUT4_I3_47_O_LUT4_I2_O I3=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 O=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_47_O_LUT4_I2_O I1=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_46_O_LUT4_I2_2_O I3=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 I3=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_46_O_LUT4_I2_O I2=R0_LUT4_I3_46_O_LUT4_I2_1_O I3=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 O=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_43_O I1=R0_LUT4_I3_42_O I2=R0_LUT4_I3_45_O I3=R0_LUT4_I3_44_O O=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L0_LUT4_I1_6_I3_LUT4_O_I2 I1=L0_LUT4_I1_3_I3_LUT4_O_I1 I2=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_I2_O I3=L0_LUT4_I1_3_I3_LUT4_O_I3 O=L0_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_2_O I1=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 O=L0_LUT4_I1_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_LUT4_I3_45_O I1=R0_LUT4_I3_44_O I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I1=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_46_O_LUT4_I2_O I3=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R0_LUT4_I3_45_O I1=R0_LUT4_I3_44_O I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_1_O I1=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_47_O_LUT4_I2_O I3=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_17_I1_LUT4_O_I2 I3=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2 O=L0_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L0(1) I2=L0_LUT4_I1_4_I2 I3=L0_LUT4_I1_4_I3 O=R1_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_4_I2_LUT4_O_I1 I2=L0_LUT4_I1_4_I2_LUT4_O_I2 I3=L0_LUT4_I3_13_I1 O=L0_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 I2=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_11_O_LUT4_I2_O O=L0_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 O=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_7_O I1=R0_LUT4_I3_6_O I2=R0_LUT4_I3_9_O I3=R0_LUT4_I3_8_O O=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_LUT4_I3_11_O_LUT4_I2_O I3=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_9_O I1=R0_LUT4_I3_7_O I2=R0_LUT4_I3_6_O I3=R0_LUT4_I3_8_O O=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_2_I2_LUT4_O_I2 I2=L0_LUT4_I1_4_I3_LUT4_O_I2 I3=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_O O=L0_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_11_O_LUT4_I2_O I3=L0_LUT4_I3_13_I2_LUT4_O_I0 O=L0_LUT4_I1_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_10_O_LUT4_I2_O O=L0_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I0 O=L0_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0(11) I2=L0_LUT4_I1_5_I2 I3=L0_LUT4_I1_5_I3 O=R1_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_5_I2_LUT4_O_I1 I2=L0_LUT4_I1_5_I2_LUT4_O_I2 I3=L0_LUT4_I1_5_I2_LUT4_O_I3 O=L0_LUT4_I1_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_28_O_LUT4_I2_2_O I3=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 O=L0_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_1_O I1=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_29_O_LUT4_I2_O O=L0_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_27_O I1=R0_LUT4_I3_25_O I2=R0_LUT4_I3_24_O I3=R0_LUT4_I3_26_O O=L0_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_26_O I1=R0_LUT4_I3_24_O I2=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_I3_I2 I3=L0_LUT4_I1_5_I2_LUT4_O_I2 O=L0_LUT4_I3_3_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R0_LUT4_I3_29_O_LUT4_I2_O I1=R0_LUT4_I3_28_O_LUT4_I2_1_O I2=R0_LUT4_I3_27_O I3=R0_LUT4_I3_25_O O=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010000100001100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_29_O_LUT4_I2_O I3=L0_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_24_O I1=R0_LUT4_I3_26_O I2=R0_LUT4_I3_25_O I3=R0_LUT4_I3_27_O O=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_1_O I1=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_28_O_LUT4_I2_2_O I3=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_25_O I1=R0_LUT4_I3_26_O I2=R0_LUT4_I3_27_O I3=R0_LUT4_I3_24_O O=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I3_10_I2_LUT4_O_I1 O=L0_LUT4_I1_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_1_O I1=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_28_O_LUT4_I2_2_O O=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_27_O I1=R0_LUT4_I3_26_O I2=R0_LUT4_I3_24_O I3=R0_LUT4_I3_25_O O=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_29_O_LUT4_I2_O O=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_26_O I1=R0_LUT4_I3_25_O I2=R0_LUT4_I3_24_O I3=R0_LUT4_I3_27_O O=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L0_LUT4_I3_3_I0_LUT4_O_I3 I1=L0_LUT4_I3_3_I0_LUT4_O_I1 I2=L0_LUT4_I3_16_I2_LUT4_O_I3_LUT4_I3_O I3=L0_LUT4_I1_5_I3_LUT4_O_I3 O=L0_LUT4_I1_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L0_LUT4_I3_3_I1_LUT4_O_I3 I2=L0_LUT4_I3_16_I1_LUT4_O_I1 I3=L0_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R0_LUT4_I3_29_O_LUT4_I2_O I3=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L0_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_1_O I1=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_LUT4_I3_28_O_LUT4_I2_2_O I3=L0_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L0_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0(12) I2=L0_LUT4_I1_6_I2 I3=L0_LUT4_I1_6_I3 O=R1_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=L0_LUT4_I1_6_I2_LUT4_O_I0 I1=L0_LUT4_I3_I0_LUT4_O_I3 I2=L0_LUT4_I1_3_I2_LUT4_O_I1 I3=L0_LUT4_I1_6_I2_LUT4_O_I3 O=L0_LUT4_I1_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0 I1=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=L0_LUT4_I1_3_I2_LUT4_O_I2 O=L0_LUT4_I1_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_O I1=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_LUT4_I3_45_O I1=R0_LUT4_I3_43_O I2=R0_LUT4_I3_44_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_1_O I1=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3 O=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_LUT4_I3_45_O I1=R0_LUT4_I3_43_O I2=R0_LUT4_I3_42_O I3=R0_LUT4_I3_44_O O=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_45_O I1=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_46_O_LUT4_I2_2_O I3=R0_LUT4_I3_44_O O=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_46_O_LUT4_I2_1_O I2=R0_LUT4_I3_47_O_LUT4_I2_O I3=L0_LUT4_I3_17_I2_LUT4_O_I2 O=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I1_6_I3_LUT4_O_I0 I1=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_I2_O I2=L0_LUT4_I1_6_I3_LUT4_O_I2 I3=L0_LUT4_I1_6_I3_LUT4_O_I3 O=L0_LUT4_I1_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=L0_LUT4_I1_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_17_I1_LUT4_O_I2 I3=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I1_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L0(13) I2=L0_LUT4_I1_7_I2 I3=L0_LUT4_I1_7_I3 O=R1_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=L0_LUT4_I1_7_I2_LUT4_O_I0 I1=L0_LUT4_I1_7_I2_LUT4_O_I1 I2=L0_LUT4_I1_7_I2_LUT4_O_I2 I3=L0_LUT4_I1_7_I2_LUT4_O_I3 O=L0_LUT4_I1_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I1_7_I2_LUT4_O_I0_LUT4_O_I0 I1=L0_LUT4_I3_15_I2_LUT4_O_I3 I2=L0_LUT4_I3_15_I2_LUT4_O_I2 I3=L0_LUT4_I1_7_I2_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I1_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_23_O_LUT4_I2_O O=L0_LUT4_I1_7_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_1_O I1=L0_LUT4_I3_15_I1_LUT4_I0_I1_LUT4_O_I0 I2=R0_LUT4_I3_22_O_LUT4_I2_2_O I3=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I1_7_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I3_15_I1_LUT4_I0_I1_LUT4_O_I0 I2=R0_LUT4_I3_22_O_LUT4_I2_2_O I3=L0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1 O=L0_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_23_O_LUT4_I2_O I3=L0_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_21_O I1=R0_LUT4_I3_20_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_18_O O=L0_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_1_O I1=L0_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 I3=R0_LUT4_I3_22_O_LUT4_I2_2_O O=L0_LUT4_I1_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_7_I3_LUT4_O_I1 I2=L0_LUT4_I1_7_I3_LUT4_O_I2 I3=L0_LUT4_I3_1_I2_LUT4_O_I3 O=L0_LUT4_I1_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_23_O_LUT4_I2_O I3=L0_LUT4_I3_15_I1_LUT4_O_I2 O=L0_LUT4_I1_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_22_O_LUT4_I2_1_O O=L0_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L0_LUT4_I3_1_I2_LUT4_O_I2 I1=L0_LUT4_I3_1_I2_LUT4_O_I1 I2=L0_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I2=R0_LUT4_I3_22_O_LUT4_I2_2_O I3=L0_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1 O=L0_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_1_O I1=L0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_23_O_LUT4_I2_O O=L0_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0(24) I2=L0_LUT4_I1_8_I2 I3=L0_LUT4_I1_8_I3 O=R1_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=L0_LUT4_I1_8_I2_LUT4_O_I0 I1=L0_LUT4_I1_8_I2_LUT4_O_I1 I2=L0_LUT4_I1_8_I2_LUT4_O_I2 I3=L0_LUT4_I1_8_I2_LUT4_O_I3 O=L0_LUT4_I1_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I2 I3=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I1_8_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_34_O_LUT4_I2_1_O O=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_34_O_LUT4_I2_O O=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_34_O_LUT4_I2_O I3=L0_LUT4_I1_8_I3_LUT4_O_I1_LUT4_O_I1 O=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=R0_LUT4_I3_34_O_LUT4_I2_2_O O=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_1_I2_LUT4_O_I2 I3=R0_LUT4_I3_35_O_LUT4_I2_O O=L0_LUT4_I1_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_34_O_LUT4_I2_O O=L0_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R0_LUT4_I3_34_O_LUT4_I2_2_O O=L0_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I0 I1=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_2_O I1=L0_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2 I2=R0_LUT4_I3_35_O_LUT4_I2_O I3=L0_LUT4_I1_8_I3_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I1_8_I3_LUT4_O_I0_LUT4_O_I0 I2=R0_LUT4_I3_34_O_LUT4_I2_O I3=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_33_O I1=R0_LUT4_I3_32_O I2=R0_LUT4_I3_31_O I3=R0_LUT4_I3_30_O O=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=R0_LUT4_I3_34_O_LUT4_I2_O O=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=R0_LUT4_I3_35_O_LUT4_I2_O I3=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I1_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_32_O I1=R0_LUT4_I3_30_O I2=R0_LUT4_I3_31_O I3=R0_LUT4_I3_33_O O=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_2_O I1=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2 I3=R0_LUT4_I3_35_O_LUT4_I2_O O=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_O I1=R0_LUT4_I3_34_O_LUT4_I2_1_O I2=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R0_LUT4_I3_33_O I1=R0_LUT4_I3_32_O I2=R0_LUT4_I3_31_O I3=R0_LUT4_I3_30_O O=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_34_O_LUT4_I2_O O=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_33_O I1=R0_LUT4_I3_32_O I2=R0_LUT4_I3_31_O I3=R0_LUT4_I3_30_O O=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L0_LUT4_I1_8_I3_LUT4_O_I0 I1=L0_LUT4_I1_8_I3_LUT4_O_I1 I2=L0_LUT4_I3_9_I0_LUT4_O_I1 I3=L0_LUT4_I3_9_I0_LUT4_O_I3 O=L0_LUT4_I1_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=L0_LUT4_I1_8_I3_LUT4_O_I0_LUT4_O_I0 I1=R0_LUT4_I3_34_O_LUT4_I2_O I2=R0_LUT4_I3_35_O_LUT4_I2_O I3=L0_LUT4_I1_8_I3_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I1_8_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_32_O I1=R0_LUT4_I3_31_O I2=R0_LUT4_I3_33_O I3=R0_LUT4_I3_30_O O=L0_LUT4_I1_8_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_31_O I1=R0_LUT4_I3_30_O I2=R0_LUT4_I3_33_O I3=R0_LUT4_I3_32_O O=L0_LUT4_I1_8_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I1_8_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_34_O_LUT4_I2_2_O I3=L0_LUT4_I1_8_I3_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_8_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_33_O I1=R0_LUT4_I3_32_O I2=R0_LUT4_I3_31_O I3=R0_LUT4_I3_30_O O=L0_LUT4_I1_8_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_32_O I1=R0_LUT4_I3_33_O I2=R0_LUT4_I3_31_O I3=R0_LUT4_I3_30_O O=L0_LUT4_I1_8_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L0(25) I2=L0_LUT4_I1_9_I2 I3=L0_LUT4_I1_9_I3 O=R1_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I2_LUT4_O_I1 I2=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_I1_O O=L0_LUT4_I1_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_2_I2_LUT4_O_I2 I3=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L0_LUT4_I1_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I3_O I1=L0_LUT4_I1_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I0 I3=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_9_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I1_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_LUT4_I3_O_LUT4_I2_1_O O=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_5_O I1=R0_LUT4_I3_4_O I2=R0_LUT4_I3_3_O I3=R0_LUT4_I3_2_O O=L0_LUT4_I1_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L0_LUT4_I1_9_I3_LUT4_O_I0 I1=L0_LUT4_I1_9_I3_LUT4_O_I1 I2=L0_LUT4_I1_9_I3_LUT4_O_I2 I3=L0_LUT4_I1_9_I3_LUT4_O_I3 O=L0_LUT4_I1_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I3_LUT4_O_I0_LUT4_O_I1 I2=L0_LUT4_I1_9_I3_LUT4_O_I0_LUT4_O_I2 I3=L0_LUT4_I3_7_I2_LUT4_O_I2 O=L0_LUT4_I1_9_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_LUT4_I3_O_LUT4_I2_1_O I3=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I1_9_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I3_O I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_O_LUT4_I2_2_O O=L0_LUT4_I1_9_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_9_I3_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I2 O=L0_LUT4_I1_9_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_1_O I1=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_O_LUT4_I2_2_O O=L0_LUT4_I1_9_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R0_LUT4_I3_O_LUT4_I3_O O=L0_LUT4_I1_9_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_9_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_1_O I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_O_LUT4_I3_O I3=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_LUT4_I3_O_LUT4_I2_1_O O=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=R0_LUT4_I3_O_LUT4_I3_O I3=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I2 O=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O I2=R0_LUT4_I3_O_LUT4_I2_2_O I3=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_5_O I1=R0_LUT4_I3_4_O I2=R0_LUT4_I3_3_O I3=R0_LUT4_I3_2_O O=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_5_O I1=R0_LUT4_I3_2_O I2=R0_LUT4_I3_3_O I3=R0_LUT4_I3_4_O O=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_O_LUT4_I2_2_O I3=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_4_O I1=R0_LUT4_I3_2_O I2=R0_LUT4_I3_3_O I3=R0_LUT4_I3_5_O O=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_2_O I1=R0_LUT4_I3_4_O I2=R0_LUT4_I3_3_O I3=R0_LUT4_I3_5_O O=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I3_O I1=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_O_LUT4_I2_2_O O=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R0_LUT4_I3_O_LUT4_I2_1_O I3=L0_LUT4_I1_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_O_LUT4_I3_O I3=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_LUT4_I3_O_LUT4_I2_2_O O=L0_LUT4_I1_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L0_LUT4_I1_I2_LUT4_O_I0 I1=L0_LUT4_I1_7_I2 I2=L0_LUT4_I1_I2_LUT4_O_I2 I3=L0_LUT4_I1_I2_LUT4_O_I3 O=L0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=L0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_22_O_LUT4_I2_1_O I2=L0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I1_7_I3_LUT4_O_I2 O=L0_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_LUT4_I3_21_O I1=R0_LUT4_I3_18_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_20_O O=L0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_1_I0_LUT4_O_I1_LUT4_I1_O I2=L0_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I3 I3=R0_LUT4_I3_22_O_LUT4_I2_1_O O=L0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_2_O I1=R0_LUT4_I3_23_O_LUT4_I2_O I2=L0_LUT4_I1_I3_LUT4_O_I2 I3=L0_LUT4_I1_I3_LUT4_O_I3 O=L0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R0_LUT4_I3_21_O I1=R0_LUT4_I3_20_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_18_O O=L0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_22_O_LUT4_I2_2_O O=L0_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_21_O I1=R0_LUT4_I3_19_O I2=R0_LUT4_I3_18_O I3=R0_LUT4_I3_20_O O=L0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_21_O I1=R0_LUT4_I3_20_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_18_O O=L0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0(17) I3=L0_LUT4_I2_I3 O=R1_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0(21) I3=L0_LUT4_I2_1_I3 O=R1_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L0_LUT4_I3_8_I0 I1=L0_LUT4_I2_1_I3_LUT4_O_I1 I2=L0_LUT4_I3_4_I0 I3=L0_LUT4_I2_1_I3_LUT4_O_I3 O=L0_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_I2_O I1=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I3 I3=L0_LUT4_I3_4_I1_LUT4_O_I3 O=L0_LUT4_I2_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1 I3=L0_LUT4_I3_4_I1_LUT4_O_I3 O=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I3_O I1=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=R0_LUT4_I3_16_O_LUT4_I2_O I3=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_14_O I1=R0_LUT4_I3_13_O I2=R0_LUT4_I3_15_O I3=R0_LUT4_I3_12_O O=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_8_I2_LUT4_O_I2 I2=L0_LUT4_I3_14_I2_LUT4_O_I1 I3=L0_LUT4_I3_14_I2_LUT4_O_I3 O=L0_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L0_LUT4_I2_I3_LUT4_O_I0 I1=L0_LUT4_I2_I3_LUT4_O_I1 I2=L0_LUT4_I2_I3_LUT4_O_I2 I3=L0_LUT4_I2_I3_LUT4_O_I3 O=L0_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_6_I2_LUT4_O_I1 I3=L0_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_2_O I3=L0_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_41_O_LUT4_I2_O I1=L0_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_1_O I3=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=L0_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_12_I2_LUT4_O_I1 I3=L0_LUT4_I3_6_I2_LUT4_O_I2 O=L0_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 I3=L0_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_12_I2_LUT4_O_I1 I3=L0_LUT4_I3_6_I2_LUT4_O_I3 O=L0_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_11_I2_LUT4_O_I3 I3=L0_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L0_LUT4_I3_I0 I1=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I2=L0_LUT4_I3_I2 I3=L0(7) O=R1_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L0_LUT4_I3_1_I0 I1=L0_LUT4_I3_1_I1 I2=L0_LUT4_I3_1_I2 I3=L0(18) O=R1_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L0_LUT4_I3_3_I0 I1=L0_LUT4_I3_10_I1 I2=L0_LUT4_I3_10_I2 I3=L0(19) O=R1_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L0_LUT4_I3_16_I2_LUT4_O_I2 I3=L0_LUT4_I3_3_I1_LUT4_O_I0 O=L0_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_10_I2_LUT4_O_I1 I2=L0_LUT4_I1_5_I2_LUT4_O_I2 I3=L0_LUT4_I3_3_I2_LUT4_O_I0 O=L0_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_29_O_LUT4_I2_O I1=L0_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R0_LUT4_I3_28_O_LUT4_I2_2_O I3=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_29_O_LUT4_I2_O I1=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_28_O_LUT4_I2_2_O O=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=L0_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_28_O_LUT4_I2_1_O O=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O I2=R0_LUT4_I3_28_O_LUT4_I2_O I3=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_26_O I1=R0_LUT4_I3_25_O I2=R0_LUT4_I3_27_O I3=R0_LUT4_I3_24_O O=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_28_O_LUT4_I2_1_O O=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_11_I0 I1=L0_LUT4_I3_11_I1 I2=L0_LUT4_I3_11_I2 I3=L0(20) O=R1_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011101111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_11_I0_LUT4_O_I1 I2=L0_LUT4_I3_11_I0_LUT4_O_I2 I3=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_O O=L0_LUT4_I3_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_11_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_8_O I1=R0_LUT4_I3_9_O I2=R0_LUT4_I3_7_O I3=R0_LUT4_I3_6_O O=L0_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_8_O I1=R0_LUT4_I3_7_O I2=R0_LUT4_I3_9_O I3=R0_LUT4_I3_6_O O=L0_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_13_I1_LUT4_O_I0 I3=R0_LUT4_I3_11_O_LUT4_I2_O O=L0_LUT4_I3_11_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_9_O I1=R0_LUT4_I3_7_O I2=R0_LUT4_I3_8_O I3=R0_LUT4_I3_6_O O=L0_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_2_I2_LUT4_O_I1 I2=L0_LUT4_I3_11_I1_LUT4_O_I2 I3=L0_LUT4_I1_4_I3_LUT4_O_I2 O=L0_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_2_I2_LUT4_O_I1 O=L0_LUT4_I3_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3 I2=R0_LUT4_I3_11_O_LUT4_I2_O I3=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_4_I2_LUT4_O_I2 I3=L0_LUT4_I3_13_I2 O=L0_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L0_LUT4_I3_6_I0 I1=L0_LUT4_I3_12_I1 I2=L0_LUT4_I3_12_I2 I3=L0(23) O=R1_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L0_LUT4_I1_11_I2_LUT4_O_I1 I1=L0_LUT4_I3_6_I1_LUT4_O_I1 I2=L0_LUT4_I3_6_I1_LUT4_O_I0 I3=L0_LUT4_I1_11_I2_LUT4_O_I2 O=L0_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_12_I2_LUT4_O_I1 I2=L0_LUT4_I2_I3_LUT4_O_I0 I3=L0_LUT4_I3_6_I2_LUT4_O_I2 O=L0_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_12_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_41_O_LUT4_I2_O I1=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 I2=L0_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_40_O_LUT4_I2_1_O O=L0_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_40_O_LUT4_I2_2_O O=L0_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_13_I0 I1=L0_LUT4_I3_13_I1 I2=L0_LUT4_I3_13_I2 I3=L0(26) O=R1_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_I2_O I1=L0_LUT4_I1_2_I3_LUT4_O_I3 I2=L0_LUT4_I3_11_I1 I3=L0_LUT4_I3_13_I0_LUT4_O_I3 O=L0_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=L0_LUT4_I1_2_I2_LUT4_O_I3 I1=L0_LUT4_I1_2_I2_LUT4_O_I2 I2=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I0 I3=L0_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L0_LUT4_I3_13_I1_LUT4_O_I0 I1=R0_LUT4_I3_10_O_LUT4_I2_1_O I2=L0_LUT4_I3_13_I1_LUT4_O_I2 I3=L0_LUT4_I3_13_I1_LUT4_O_I3 O=L0_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_LUT4_I3_9_O I1=R0_LUT4_I3_8_O I2=R0_LUT4_I3_7_O I3=R0_LUT4_I3_6_O O=L0_LUT4_I3_13_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_13_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I1 I3=R0_LUT4_I3_11_O_LUT4_I2_O O=L0_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_6_O I1=R0_LUT4_I3_8_O I2=R0_LUT4_I3_7_O I3=R0_LUT4_I3_9_O O=L0_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_10_O_LUT4_I2_O O=L0_LUT4_I3_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_11_O_LUT4_I2_O O=L0_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_9_O I1=R0_LUT4_I3_8_O I2=R0_LUT4_I3_6_O I3=R0_LUT4_I3_7_O O=L0_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L0_LUT4_I3_13_I2_LUT4_O_I0 I1=R0_LUT4_I3_10_O_LUT4_I2_2_O I2=L0_LUT4_I3_13_I2_LUT4_O_I2 I3=L0_LUT4_I3_13_I2_LUT4_O_I3 O=L0_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_LUT4_I3_9_O I1=R0_LUT4_I3_8_O I2=R0_LUT4_I3_7_O I3=R0_LUT4_I3_6_O O=L0_LUT4_I3_13_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_LUT4_I3_10_O_LUT4_I2_1_O I3=L0_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_2_O I1=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_11_O_LUT4_I2_O O=L0_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I1 I3=R0_LUT4_I3_10_O_LUT4_I2_1_O O=L0_LUT4_I3_13_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_10_O_LUT4_I2_O I1=L0_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I0 I3=R0_LUT4_I3_11_O_LUT4_I2_O O=L0_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_4_I0 I1=L0_LUT4_I3_14_I1 I2=L0_LUT4_I3_14_I2 I3=L0(27) O=R1_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_I2_O I1=L0_LUT4_I3_4_I0_LUT4_O_I0 I2=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=L0_LUT4_I3_14_I1_LUT4_O_I3 O=L0_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_8_I1_LUT4_O_I3 I2=L0_LUT4_I3_8_I1_LUT4_O_I2 I3=L0_LUT4_I3_4_I1_LUT4_O_I3 O=L0_LUT4_I3_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L0_LUT4_I3_8_I2_LUT4_O_I3 I1=L0_LUT4_I3_14_I2_LUT4_O_I1 I2=L0_LUT4_I3_4_I2_LUT4_O_I0 I3=L0_LUT4_I3_14_I2_LUT4_O_I3 O=L0_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_14_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_16_O_LUT4_I2_2_O O=L0_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I3_O I1=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_LUT4_I3_16_O_LUT4_I2_O I3=L0_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1 I3=R0_LUT4_I3_16_O_LUT4_I2_O O=L0_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R0_LUT4_I3_16_O_LUT4_I3_O O=L0_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R0_LUT4_I3_16_O_LUT4_I2_2_O O=L0_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_15_I0 I1=L0_LUT4_I3_15_I1 I2=L0_LUT4_I3_15_I2 I3=L0(28) O=R1_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_7_I3_LUT4_O_I2 I2=L0_LUT4_I3_15_I0_LUT4_O_I2 I3=L0_LUT4_I1_I2_LUT4_O_I2 O=L0_LUT4_I3_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L0_LUT4_I3_1_I1_LUT4_O_I3 I1=L0_LUT4_I1_7_I3_LUT4_O_I1 I2=L0_LUT4_I3_1_I1_LUT4_O_I2 I3=L0_LUT4_I3_1_I1_LUT4_O_I1 O=L0_LUT4_I3_15_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I3_15_I1 I1=L0_LUT4_I3_15_I1_LUT4_I0_I1 I2=L0_LUT4_I3_15_I1_LUT4_I0_I2 I3=L0_LUT4_I3_15_I2_LUT4_I2_I3 O=L0_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I3_15_I1_LUT4_I0_I1_LUT4_O_I0 I1=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_22_O_LUT4_I2_1_O I3=L0_LUT4_I3_15_I1_LUT4_I0_I1_LUT4_O_I3 O=L0_LUT4_I3_15_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R0_LUT4_I3_19_O I1=R0_LUT4_I3_18_O I2=R0_LUT4_I3_21_O I3=R0_LUT4_I3_20_O O=L0_LUT4_I3_15_I1_LUT4_I0_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O I1=L0_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_LUT4_I3_23_O O=L0_LUT4_I3_15_I1_LUT4_I0_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I2=L0_LUT4_I3_15_I1_LUT4_I0_I2_LUT4_O_I2 I3=L0_LUT4_I1_7_I2_LUT4_O_I0_LUT4_O_I0 O=L0_LUT4_I3_15_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_LUT4_I3_18_O I1=R0_LUT4_I3_20_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_22_O_LUT4_I2_2_O O=L0_LUT4_I3_15_I1_LUT4_I0_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_15_I1_LUT4_O_I1 I2=L0_LUT4_I3_15_I1_LUT4_O_I2 I3=R0_LUT4_I3_22_O_LUT4_I2_O O=L0_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_22_O_LUT4_I2_1_O O=L0_LUT4_I3_15_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_23_O_LUT4_I2_O I1=L0_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_22_O_LUT4_I2_2_O I3=L0_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_21_O I1=R0_LUT4_I3_20_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_18_O O=L0_LUT4_I3_15_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_15_I2 I3=L0_LUT4_I3_15_I2_LUT4_I2_I3 O=L0_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_15_I2_LUT4_I2_I3_LUT4_O_I2 I3=L0_LUT4_I3_15_I2_LUT4_I2_I3_LUT4_O_I3 O=L0_LUT4_I3_15_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_15_I1_LUT4_I0_I1_LUT4_O_I0 I3=R0_LUT4_I3_23_O_LUT4_I2_O O=L0_LUT4_I3_15_I2_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_1_O I1=L0_LUT4_I1_I3_LUT4_O_I2 I2=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_LUT4_I3_22_O_LUT4_I2_2_O O=L0_LUT4_I3_15_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_15_I2_LUT4_O_I2 I3=L0_LUT4_I3_15_I2_LUT4_O_I3 O=L0_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_1_O I1=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_LUT4_I3_23_O_LUT4_I2_O O=L0_LUT4_I3_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_18_O I1=R0_LUT4_I3_20_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_21_O O=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_20_O I1=R0_LUT4_I3_19_O I2=R0_LUT4_I3_18_O I3=R0_LUT4_I3_21_O O=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I1_I3_LUT4_O_I2 I2=R0_LUT4_I3_22_O_LUT4_I2_2_O I3=L0_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 O=L0_LUT4_I3_15_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_16_I0 I1=L0_LUT4_I3_16_I1 I2=L0_LUT4_I3_16_I2 I3=L0(29) O=R1_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L0_LUT4_I3_3_I0_LUT4_O_I3 I1=L0_LUT4_I3_16_I2_LUT4_O_I3_LUT4_I3_O I2=L0_LUT4_I3_16_I0_LUT4_O_I2 I3=L0_LUT4_I3_3_I0_LUT4_O_I1 O=L0_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_3_I2_LUT4_O_I0_LUT4_O_I3 I3=L0_LUT4_I1_5_I2_LUT4_O_I3 O=L0_LUT4_I3_16_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_16_I1_LUT4_O_I1 I2=L0_LUT4_I3_3_I1_LUT4_O_I3 I3=L0_LUT4_I3_3_I1_LUT4_O_I0 O=L0_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_28_O_LUT4_I2_O O=L0_LUT4_I3_16_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=L0_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_28_O_LUT4_I2_2_O O=L0_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_27_O I1=R0_LUT4_I3_26_O I2=R0_LUT4_I3_25_O I3=R0_LUT4_I3_24_O O=L0_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_16_I2_LUT4_O_I2 I3=L0_LUT4_I3_16_I2_LUT4_O_I3 O=L0_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_1_O I1=L0_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_LUT4_I3_28_O_LUT4_I2_2_O O=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_27_O I1=R0_LUT4_I3_26_O I2=R0_LUT4_I3_25_O I3=R0_LUT4_I3_24_O O=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_29_O_LUT4_I2_O I3=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_27_O I1=R0_LUT4_I3_25_O I2=R0_LUT4_I3_26_O I3=R0_LUT4_I3_24_O O=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3 I3=L0_LUT4_I3_16_I2_LUT4_O_I3 O=L0_LUT4_I3_16_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_28_O_LUT4_I2_2_O I3=L0_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 O=L0_LUT4_I3_16_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_28_O_LUT4_I2_O O=L0_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_1_O I1=L0_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R0_LUT4_I3_29_O_LUT4_I2_O I3=L0_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=L0_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_17_I0 I1=L0_LUT4_I3_17_I1 I2=L0_LUT4_I3_17_I2 I3=L0(32) O=R1_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L0_LUT4_I1_6_I3_LUT4_O_I2 I1=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_I2_O I2=L0_LUT4_I1_6_I2_LUT4_O_I0 I3=L0_LUT4_I3_17_I0_LUT4_O_I3 O=L0_LUT4_I3_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_6_I2_LUT4_O_I3 I3=L0_LUT4_I3_I0_LUT4_O_I2 O=L0_LUT4_I3_17_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_17_I1_LUT4_O_I2 I3=L0_LUT4_I3_I2_LUT4_O_I0 O=L0_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_17_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_O I1=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_47_O_LUT4_I2_O O=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_1_O I1=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_46_O_LUT4_I2_2_O O=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_47_O_LUT4_I2_O I1=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_46_O_LUT4_I2_2_O O=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_O I1=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=R0_LUT4_I3_46_O_LUT4_I2_1_O I3=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I3 O=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_46_O_LUT4_I2_2_O I2=R0_LUT4_I3_47_O_LUT4_I2_O I3=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_45_O I1=R0_LUT4_I3_44_O I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_I2_LUT4_O_I1 I3=L0_LUT4_I3_17_I2 O=L0_LUT4_I1_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_17_I2_LUT4_O_I1 I2=L0_LUT4_I3_17_I2_LUT4_O_I2 I3=R0_LUT4_I3_46_O_LUT4_I2_O O=L0_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 I3=R0_LUT4_I3_46_O_LUT4_I2_1_O O=L0_LUT4_I3_17_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_47_O_LUT4_I2_O I1=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=R0_LUT4_I3_46_O_LUT4_I2_2_O I3=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L0_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_43_O I1=R0_LUT4_I3_44_O I2=R0_LUT4_I3_45_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I3_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_1_O I1=L0_LUT4_I3_1_I0_LUT4_O_I1 I2=L0_LUT4_I3_1_I0_LUT4_O_I2 I3=L0_LUT4_I1_I2_LUT4_O_I0 O=L0_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000011111111
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I3_1_I0_LUT4_O_I1 I2=L0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_23_O_LUT4_I2_O O=L0_LUT4_I3_1_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_1_O I1=L0_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 I2=R0_LUT4_I3_23_O_LUT4_I2_O I3=L0_LUT4_I3_1_I0_LUT4_O_I1 O=L0_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_20_O I1=R0_LUT4_I3_21_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_18_O O=L0_LUT4_I3_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L0_LUT4_I3_15_I1_LUT4_O_I1 I1=L0_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I1_7_I2_LUT4_O_I1 I3=L0_LUT4_I1_7_I2_LUT4_O_I0 O=L0_LUT4_I3_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I3_15_I1_LUT4_O_I2 I1=L0_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_LUT4_I3_22_O_LUT4_I2_O I3=L0_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R0_LUT4_I3_23_O_LUT4_I2_O I1=L0_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I3_15_I1_LUT4_I0_I1_LUT4_O_I0 I3=R0_LUT4_I3_22_O_LUT4_I2_2_O O=L0_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_1_I1_LUT4_O_I1 I2=L0_LUT4_I3_1_I1_LUT4_O_I2 I3=L0_LUT4_I3_1_I1_LUT4_O_I3 O=L0_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_22_O_LUT4_I2_2_O I3=L0_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I3 I2=L0_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1 I3=R0_LUT4_I3_22_O_LUT4_I2_1_O O=L0_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_21_O I1=R0_LUT4_I3_19_O I2=R0_LUT4_I3_20_O I3=R0_LUT4_I3_18_O O=L0_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_21_O I1=R0_LUT4_I3_20_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_18_O O=L0_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_1_O I1=L0_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_23_O_LUT4_I2_O I3=L0_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 I2=R0_LUT4_I3_22_O_LUT4_I2_2_O I3=L0_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_21_O I1=R0_LUT4_I3_20_O I2=R0_LUT4_I3_18_O I3=R0_LUT4_I3_19_O O=L0_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_20_O I1=R0_LUT4_I3_18_O I2=R0_LUT4_I3_19_O I3=R0_LUT4_I3_21_O O=L0_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I2=L0_LUT4_I1_I3_LUT4_O_I2 I3=R0_LUT4_I3_22_O_LUT4_I2_2_O O=L0_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_1_I2_LUT4_O_I1 I2=L0_LUT4_I3_1_I2_LUT4_O_I2 I3=L0_LUT4_I3_1_I2_LUT4_O_I3 O=L0_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L0_LUT4_I3_15_I1_LUT4_O_I2 I1=R0_LUT4_I3_22_O_LUT4_I2_1_O I2=L0_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_23_O_LUT4_I2_O O=L0_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_19_O I1=R0_LUT4_I3_20_O I2=R0_LUT4_I3_21_O I3=R0_LUT4_I3_18_O O=L0_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_22_O_LUT4_I2_O I1=L0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0 I2=R0_LUT4_I3_22_O_LUT4_I2_2_O I3=L0_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_20_O I1=R0_LUT4_I3_19_O I2=R0_LUT4_I3_21_O I3=R0_LUT4_I3_18_O O=L0_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_22_O_LUT4_I2_2_O I3=L0_LUT4_I3_15_I1_LUT4_O_I2 O=L0_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0 I3=R0_LUT4_I3_23_O_LUT4_I2_O O=L0_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L0_LUT4_I3_2_I0 I1=L0_LUT4_I3_2_I1 I2=L0_LUT4_I3_2_I2 I3=L0(3) O=R1_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_5_I0_LUT4_O_I3 I3=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_I1_O O=L0_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_9_I3_LUT4_O_I0 I3=L0_LUT4_I1_9_I3_LUT4_O_I3 O=L0_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L0_LUT4_I3_2_I2_LUT4_O_I0 I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L0_LUT4_I3_2_I2_LUT4_O_I2 I3=L0_LUT4_I3_2_I2_LUT4_O_I3 O=L0_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_2_I2_LUT4_O_I0 I2=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_I1_I2 I3=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I2 O=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1 I2=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_LUT4_I3_O_LUT4_I3_O O=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_LUT4_I3_O_LUT4_I2_2_O I3=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I1 I2=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_LUT4_I3_O_LUT4_I2_O O=L0_LUT4_I3_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_O_LUT4_I2_1_O I3=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=R0_LUT4_I3_O_LUT4_I3_O I2=R0_LUT4_I3_O_LUT4_I2_2_O I3=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_5_O I1=R0_LUT4_I3_4_O I2=R0_LUT4_I3_3_O I3=R0_LUT4_I3_2_O O=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_5_O I1=R0_LUT4_I3_4_O I2=R0_LUT4_I3_3_O I3=R0_LUT4_I3_2_O O=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_LUT4_I3_O_LUT4_I2_1_O O=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_5_O I1=R0_LUT4_I3_4_O I2=R0_LUT4_I3_3_O I3=R0_LUT4_I3_2_O O=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_5_O I1=R0_LUT4_I3_3_O I2=R0_LUT4_I3_4_O I3=R0_LUT4_I3_2_O O=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I3_O I1=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_O_LUT4_I2_2_O I3=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_3_O I1=R0_LUT4_I3_4_O I2=R0_LUT4_I3_5_O I3=R0_LUT4_I3_2_O O=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_4_O I1=R0_LUT4_I3_5_O I2=R0_LUT4_I3_3_O I3=R0_LUT4_I3_2_O O=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_LUT4_I3_O_LUT4_I3_O I3=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_1_O I1=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_O_LUT4_I2_2_O I3=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L0_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_3_I0 I1=L0_LUT4_I3_3_I1 I2=L0_LUT4_I3_3_I2 I3=L0(4) O=R1_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_3_I0_LUT4_O_I1 I2=L0_LUT4_I3_16_I2_LUT4_O_I3_LUT4_I3_O I3=L0_LUT4_I3_3_I0_LUT4_O_I3 O=L0_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L0_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I0 I1=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2 I2=L0_LUT4_I3_16_I2_LUT4_O_I2 I3=L0_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=L0_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 I2=R0_LUT4_I3_28_O I3=R0_LUT4_I3_29_O O=L0_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=K1(1) I1=R0_LUT4_I3_28_O_LUT4_I2_1_O I2=L0_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L0_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=R0_LUT4_I3_27_O I1=R0_LUT4_I3_26_O I2=R0_LUT4_I3_25_O I3=R0_LUT4_I3_24_O O=L0_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I3 I2=L0_LUT4_I3_3_I1_LUT4_O_I3 I3=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L0_LUT4_I3_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L0_LUT4_I3_3_I1_LUT4_O_I0 I1=L0_LUT4_I3_16_I2_LUT4_O_I3_LUT4_I3_O I2=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I3=L0_LUT4_I3_3_I1_LUT4_O_I3 O=L0_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L0_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L0_LUT4_I3_3_I1_LUT4_O_I3 I2=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2 I3=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_LUT4_I3_28_O_LUT4_I2_1_O I2=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_LUT4_I3_27_O I1=R0_LUT4_I3_26_O I2=R0_LUT4_I3_25_O I3=R0_LUT4_I3_24_O O=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_1_O I1=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_29_O_LUT4_I2_O I3=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_29_O I1=L0_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=L0_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_28_O O=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 I2=R0_LUT4_I3_28_O_LUT4_I2_2_O I3=L0_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_29_O_LUT4_I2_O I3=L0_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=L0_LUT4_I3_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_28_O_LUT4_I2_2_O O=L0_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_28_O_LUT4_I2_1_O O=L0_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_3_I2_LUT4_O_I0 I1=L0_LUT4_I3_3_I2_LUT4_O_I1 I2=L0_LUT4_I3_3_I2_LUT4_O_I2 I3=L0_LUT4_I3_3_I2_LUT4_O_I3 O=L0_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_5_I2_LUT4_O_I1 I2=L0_LUT4_I3_3_I2_LUT4_O_I1 I3=L0_LUT4_I3_3_I2_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I2=L0_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_29_O_LUT4_I2_O O=L0_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_1_O I1=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_28_O_LUT4_I2_2_O O=L0_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_26_O I1=R0_LUT4_I3_27_O I2=R0_LUT4_I3_25_O I3=R0_LUT4_I3_24_O O=L0_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_1_O I1=L0_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_28_O_LUT4_I2_2_O I3=L0_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_26_O I1=R0_LUT4_I3_24_O I2=R0_LUT4_I3_25_O I3=R0_LUT4_I3_27_O O=L0_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_27_O I1=R0_LUT4_I3_26_O I2=R0_LUT4_I3_25_O I3=R0_LUT4_I3_24_O O=L0_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_LUT4_I3_28_O_LUT4_I2_O I1=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_29_O_LUT4_I2_O O=L0_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_25_O I1=R0_LUT4_I3_24_O I2=R0_LUT4_I3_27_O I3=R0_LUT4_I3_26_O O=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_27_O I1=R0_LUT4_I3_24_O I2=R0_LUT4_I3_25_O I3=R0_LUT4_I3_26_O O=L0_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L0_LUT4_I3_4_I0 I1=L0_LUT4_I3_4_I1 I2=L0_LUT4_I3_4_I2 I3=L0(5) O=R1_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L0_LUT4_I3_4_I0_LUT4_O_I0 I1=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=L0_LUT4_I3_4_I0_LUT4_O_I2 I3=L0_LUT4_I3_4_I0_LUT4_O_I3 O=L0_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_4_I1_LUT4_O_I1 I2=L0_LUT4_I3_4_I1_LUT4_O_I0 I3=L0_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_16_O_LUT4_I2_1_O I2=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0 I3=L0_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I3_O I1=L0_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0 I2=R0_LUT4_I3_16_O_LUT4_I2_2_O I3=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_17_O I1=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_LUT4_I3_16_O_LUT4_I2_2_O I3=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000111011
+.subckt LUT4 I0=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0 I1=L0_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3 I2=R0_LUT4_I3_16_O_LUT4_I2_2_O I3=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_15_O I1=R0_LUT4_I3_13_O I2=R0_LUT4_I3_12_O I3=R0_LUT4_I3_14_O O=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 I2=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 I3=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0 O=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_16_O_LUT4_I2_O I2=R0_LUT4_I3_16_O_LUT4_I2_2_O I3=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_4_I1_LUT4_O_I0 I1=L0_LUT4_I3_4_I1_LUT4_O_I1 I2=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_I2_O I3=L0_LUT4_I3_4_I1_LUT4_O_I3 O=L0_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111110000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_LUT4_I3_16_O_LUT4_I2_O I3=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_15_O I1=R0_LUT4_I3_14_O I2=R0_LUT4_I3_13_O I3=R0_LUT4_I3_12_O O=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_12_O I1=R0_LUT4_I3_14_O I2=R0_LUT4_I3_13_O I3=R0_LUT4_I3_15_O O=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R0_LUT4_I3_16_O_LUT4_I3_O I2=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010011
+.subckt LUT4 I0=R0_LUT4_I3_14_O I1=R0_LUT4_I3_12_O I2=R0_LUT4_I3_13_O I3=R0_LUT4_I3_15_O O=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_15_O I1=R0_LUT4_I3_14_O I2=R0_LUT4_I3_12_O I3=R0_LUT4_I3_13_O O=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0 I3=R0_LUT4_I3_16_O_LUT4_I2_O O=L0_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_16_O_LUT4_I2_2_O I2=R0_LUT4_I3_16_O_LUT4_I3_O I3=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0 O=L0_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_4_I2_LUT4_O_I0 I1=L0_LUT4_I3_8_I2_LUT4_O_I1 I2=L0_LUT4_I3_4_I2_LUT4_O_I2 I3=L0_LUT4_I3_4_I2_LUT4_O_I3 O=L0_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1 I2=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3 I3=R0_LUT4_I3_16_O_LUT4_I2_2_O O=L0_LUT4_I3_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_16_O_LUT4_I2_1_O O=L0_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I3_O I1=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R0_LUT4_I3_16_O_LUT4_I2_O I3=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1 O=L0_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_15_O I1=R0_LUT4_I3_14_O I2=R0_LUT4_I3_13_O I3=R0_LUT4_I3_12_O O=L0_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L0_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0 I1=R0_LUT4_I3_16_O_LUT4_I2_2_O I2=R0_LUT4_I3_16_O_LUT4_I2_O I3=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_14_O I1=R0_LUT4_I3_13_O I2=R0_LUT4_I3_12_O I3=R0_LUT4_I3_15_O O=L0_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_16_O_LUT4_I3_O I2=R0_LUT4_I3_16_O_LUT4_I2_1_O I3=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_15_O I1=R0_LUT4_I3_14_O I2=R0_LUT4_I3_13_O I3=R0_LUT4_I3_12_O O=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_13_O I1=R0_LUT4_I3_12_O I2=R0_LUT4_I3_15_O I3=R0_LUT4_I3_14_O O=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L0_LUT4_I3_5_I0 I1=L0_LUT4_I3_5_I1 I2=L0_LUT4_I3_5_I2 I3=L0(8) O=R1_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011101111
+.subckt LUT4 I0=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_I1_O I1=L0_LUT4_I3_2_I2 I2=L0_LUT4_I3_5_I0_LUT4_O_I2 I3=L0_LUT4_I3_5_I0_LUT4_O_I3 O=L0_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_7_I2_LUT4_O_I1 I3=L0_LUT4_I1_9_I3_LUT4_O_I1 O=L0_LUT4_I3_5_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I0 I1=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_O_LUT4_I2_2_O I3=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I2 O=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I2=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=R0_LUT4_I3_O_LUT4_I2_O O=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_2_O I1=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=R0_LUT4_I3_O_LUT4_I2_1_O I2=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_O_LUT4_I2_1_O I3=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_5_O I1=R0_LUT4_I3_4_O I2=R0_LUT4_I3_2_O I3=R0_LUT4_I3_3_O O=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_4_O I1=R0_LUT4_I3_3_O I2=R0_LUT4_I3_2_O I3=R0_LUT4_I3_5_O O=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_9_I2_LUT4_O_I1 I3=L0_LUT4_I3_7_I0_LUT4_O_I2 O=L0_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_2_I2_LUT4_O_I3 I3=L0_LUT4_I3_2_I2_LUT4_O_I0 O=L0_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L0_LUT4_I3_6_I0 I1=L0_LUT4_I3_6_I1 I2=L0_LUT4_I3_6_I2 I3=L0(9) O=R1_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L0_LUT4_I3_6_I0_LUT4_O_I0 I1=L0_LUT4_I3_6_I0_LUT4_O_I1 I2=L0_LUT4_I3_6_I0_LUT4_O_I2 I3=L0_LUT4_I2_I3_LUT4_O_I2 O=L0_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 I1=L0_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2 I3=R0_LUT4_I3_40_O_LUT4_I2_1_O O=L0_LUT4_I3_6_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=R0_LUT4_I3_39_O I1=R0_LUT4_I3_37_O I2=R0_LUT4_I3_38_O I3=R0_LUT4_I3_36_O O=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_38_O I1=R0_LUT4_I3_36_O I2=R0_LUT4_I3_37_O I3=R0_LUT4_I3_39_O O=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I1=L0_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_2_O I3=L0_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R0_LUT4_I3_38_O I1=R0_LUT4_I3_39_O I2=R0_LUT4_I3_37_O I3=R0_LUT4_I3_36_O O=L0_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_LUT4_I3_40_O_LUT4_I2_2_O I3=L0_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 O=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 I2=R0_LUT4_I3_40_O_LUT4_I2_O I3=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R0_LUT4_I3_39_O I1=R0_LUT4_I3_38_O I2=R0_LUT4_I3_37_O I3=R0_LUT4_I3_36_O O=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_41_O_LUT4_I2_O I1=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I2=L0_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L0_LUT4_I3_6_I1_LUT4_O_I0 I1=L0_LUT4_I3_6_I1_LUT4_O_I1 I2=L0_LUT4_I3_6_I1_LUT4_O_I2 I3=L0_LUT4_I3_6_I1_LUT4_O_I3 O=L0_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L0_LUT4_I1_11_I2_LUT4_O_I2 I1=L0_LUT4_I1_11_I2_LUT4_O_I3 I2=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2 I3=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I2 I2=R0_LUT4_I3_41_O_LUT4_I2_O I3=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_37_O I1=R0_LUT4_I3_36_O I2=R0_LUT4_I3_39_O I3=R0_LUT4_I3_38_O O=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_2_O I1=L0_LUT4_I1_11_I3_LUT4_O_I0_LUT4_O_I3 I2=R0_LUT4_I3_40_O_LUT4_I2_1_O I3=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_39_O I1=R0_LUT4_I3_37_O I2=R0_LUT4_I3_36_O I3=R0_LUT4_I3_38_O O=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L0_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 I1=R0_LUT4_I3_41_O_LUT4_I2_O I2=L0_LUT4_I3_6_I1_LUT4_O_I1 I3=L0_LUT4_I3_6_I1_LUT4_O_I1_LUT4_I2_I3 O=L0_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_6_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I1 I2=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R0_LUT4_I3_40_O_LUT4_I2_1_O O=L0_LUT4_I3_6_I1_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I1_11_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_2_O I3=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_6_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=R0_LUT4_I3_40_O_LUT4_I2_2_O I3=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2 O=L0_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_41_O_LUT4_I2_O I1=L0_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_1_O I3=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I2 O=L0_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_2_O I1=L0_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_1_O I3=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 O=L0_LUT4_I3_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_38_O I1=R0_LUT4_I3_37_O I2=R0_LUT4_I3_39_O I3=R0_LUT4_I3_36_O O=L0_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_41_O_LUT4_I2_O I3=L0_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_39_O I1=R0_LUT4_I3_36_O I2=R0_LUT4_I3_37_O I3=R0_LUT4_I3_38_O O=L0_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_39_O I1=R0_LUT4_I3_38_O I2=R0_LUT4_I3_37_O I3=R0_LUT4_I3_36_O O=L0_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_6_I2_LUT4_O_I1 I2=L0_LUT4_I3_6_I2_LUT4_O_I2 I3=L0_LUT4_I3_6_I2_LUT4_O_I3 O=L0_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 I2=R0_LUT4_I3_40_O_LUT4_I2_1_O I3=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2 O=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_41_O_LUT4_I2_O I1=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_LUT4_I3_40_O_LUT4_I2_2_O I3=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_36_O I1=R0_LUT4_I3_38_O I2=R0_LUT4_I3_37_O I3=R0_LUT4_I3_39_O O=L0_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_LUT4_I3_40_O_LUT4_I2_2_O O=L0_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 I3=R0_LUT4_I3_40_O_LUT4_I2_1_O O=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_O I1=L0_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 I2=R0_LUT4_I3_41_O_LUT4_I2_O I3=L0_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_39_O I1=R0_LUT4_I3_38_O I2=R0_LUT4_I3_37_O I3=R0_LUT4_I3_36_O O=L0_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_LUT4_I3_40_O_LUT4_I2_O O=L0_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2 I3=R0_LUT4_I3_41_O_LUT4_I2_O O=L0_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_40_O_LUT4_I2_2_O I1=L0_LUT4_I1_11_I3_LUT4_O_I1_LUT4_O_I2 I2=R0_LUT4_I3_40_O_LUT4_I2_1_O I3=L0_LUT4_I1_11_I3_LUT4_O_I0_LUT4_O_I1 O=L0_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_39_O I1=R0_LUT4_I3_38_O I2=R0_LUT4_I3_37_O I3=R0_LUT4_I3_36_O O=L0_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I3_7_I0 I1=L0_LUT4_I3_7_I1 I2=L0_LUT4_I3_7_I2 I3=L0(14) O=R1_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I2_LUT4_O_I1 I2=L0_LUT4_I3_7_I0_LUT4_O_I2 I3=L0_LUT4_I3_2_I2_LUT4_O_I0_LUT4_I1_O O=L0_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_O_LUT4_I2_2_O I3=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=L0_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_2_O I1=L0_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_LUT4_I3_O_LUT4_I2_1_O O=L0_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=K1(1) I1=R0_LUT4_I3_O_LUT4_I3_O I2=R0_LUT4_I3_4_O I3=R0_LUT4_I3_5_O O=L0_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L0_LUT4_I3_5_I0_LUT4_O_I3 I3=L0_LUT4_I3_2_I2 O=L0_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_7_I2_LUT4_O_I1 I2=L0_LUT4_I3_7_I2_LUT4_O_I2 I3=L0_LUT4_I1_9_I3_LUT4_O_I2 O=L0_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_1_O I1=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_O_LUT4_I2_2_O I3=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L0_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R0_LUT4_I3_O_LUT4_I3_O I3=L0_LUT4_I1_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_1_O I1=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_LUT4_I3_O_LUT4_I3_O O=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_5_O I1=R0_LUT4_I3_3_O I2=R0_LUT4_I3_2_O I3=R0_LUT4_I3_4_O O=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_4_O I1=R0_LUT4_I3_3_O I2=R0_LUT4_I3_5_O I3=R0_LUT4_I3_2_O O=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_O_LUT4_I2_O I1=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R0_LUT4_I3_O_LUT4_I2_2_O O=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_3_O I1=R0_LUT4_I3_2_O I2=R0_LUT4_I3_5_O I3=R0_LUT4_I3_4_O O=L0_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L0_LUT4_I3_8_I0 I1=L0_LUT4_I3_8_I1 I2=L0_LUT4_I3_8_I2 I3=L0(15) O=R1_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111100000
+.subckt LUT4 I0=L0_LUT4_I3_4_I0_LUT4_O_I0 I1=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_I2_O I3=L0_LUT4_I3_8_I0_LUT4_O_I3 O=L0_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 I3=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0 O=L0_LUT4_I3_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I3_O I1=L0_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3 I3=R0_LUT4_I3_16_O_LUT4_I2_2_O O=L0_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_I2_O I2=L0_LUT4_I3_8_I1_LUT4_O_I2 I3=L0_LUT4_I3_8_I1_LUT4_O_I3 O=L0_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3 I2=R0_LUT4_I3_16_O_LUT4_I2_O I3=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 O=L0_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_I2_I0 I1=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I3_8_I1_LUT4_O_I3 I3=L0_LUT4_I3_8_I1_LUT4_O_I2 O=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3 I1=L0_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 I2=R0_LUT4_I3_16_O I3=R0_LUT4_I3_17_O O=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_16_O_LUT4_I2_2_O I2=R0_LUT4_I3_16_O_LUT4_I3_O I3=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_15_O I1=R0_LUT4_I3_12_O I2=R0_LUT4_I3_13_O I3=R0_LUT4_I3_14_O O=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_14_O I1=R0_LUT4_I3_15_O I2=R0_LUT4_I3_13_O I3=R0_LUT4_I3_12_O O=L0_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_8_I2_LUT4_O_I1 I2=L0_LUT4_I3_8_I2_LUT4_O_I2 I3=L0_LUT4_I3_8_I2_LUT4_O_I3 O=L0_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I3_O I1=L0_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_14_I2_LUT4_O_I1 I3=L0_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_LUT4_I3_16_O_LUT4_I2_2_O O=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_15_O I1=R0_LUT4_I3_14_O I2=R0_LUT4_I3_13_O I3=R0_LUT4_I3_12_O O=L0_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_16_O_LUT4_I2_O O=L0_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R0_LUT4_I3_16_O_LUT4_I2_2_O I3=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I3_O I1=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R0_LUT4_I3_16_O_LUT4_I2_2_O I3=L0_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_15_O I1=R0_LUT4_I3_14_O I2=R0_LUT4_I3_13_O I3=R0_LUT4_I3_12_O O=L0_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=R0_LUT4_I3_16_O_LUT4_I2_O I3=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I2_1_O I1=L0_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0 I2=R0_LUT4_I3_16_O_LUT4_I2_O I3=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_15_O I1=R0_LUT4_I3_13_O I2=R0_LUT4_I3_14_O I3=R0_LUT4_I3_12_O O=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_16_O_LUT4_I3_O I1=L0_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=R0_LUT4_I3_16_O_LUT4_I2_2_O I3=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_13_O I1=R0_LUT4_I3_14_O I2=R0_LUT4_I3_15_O I3=R0_LUT4_I3_12_O O=L0_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L0_LUT4_I3_9_I0 I1=L0_LUT4_I3_9_I1 I2=L0_LUT4_I3_9_I2 I3=L0(16) O=R1_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L0_LUT4_I3_9_I0_LUT4_O_I0 I1=L0_LUT4_I3_9_I0_LUT4_O_I1 I2=L0_LUT4_I3_9_I0_LUT4_O_I2 I3=L0_LUT4_I3_9_I0_LUT4_O_I3 O=L0_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I2 I3=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_9_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I1_8_I3_LUT4_O_I1_LUT4_O_I3 I2=R0_LUT4_I3_34_O_LUT4_I2_2_O I3=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_33_O I1=R0_LUT4_I3_31_O I2=R0_LUT4_I3_32_O I3=R0_LUT4_I3_30_O O=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_O I1=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_35_O_LUT4_I2_O I3=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_33_O I1=R0_LUT4_I3_30_O I2=R0_LUT4_I3_31_O I3=R0_LUT4_I3_32_O O=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_33_O I1=R0_LUT4_I3_31_O I2=R0_LUT4_I3_30_O I3=R0_LUT4_I3_32_O O=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_34_O_LUT4_I2_2_O O=L0_LUT4_I3_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_8_I3_LUT4_O_I0_LUT4_O_I3 I2=L0_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R0_LUT4_I3_35_O_LUT4_I2_O O=L0_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=R0_LUT4_I3_32_O I1=R0_LUT4_I3_31_O I2=R0_LUT4_I3_30_O I3=R0_LUT4_I3_33_O O=L0_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_35_O_LUT4_I2_O I1=R0_LUT4_I3_34_O_LUT4_I2_2_O I2=L0_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_9_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R0_LUT4_I3_31_O I1=R0_LUT4_I3_32_O I2=R0_LUT4_I3_33_O I3=R0_LUT4_I3_30_O O=L0_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_2_O I1=L0_LUT4_I1_8_I3_LUT4_O_I0_LUT4_O_I0 I2=R0_LUT4_I3_35_O_LUT4_I2_O I3=L0_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2 O=L0_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_9_I1_LUT4_O_I2 I3=L0_LUT4_I3_9_I1_LUT4_O_I3 O=L0_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I1_8_I2_LUT4_O_I2 O=L0_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I1=R0_LUT4_I3_34_O_LUT4_I2_1_O I2=L0_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2 I3=L0_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_2_O I1=L0_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R0_LUT4_I3_34_O_LUT4_I2_O O=L0_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I1_8_I2_LUT4_O_I3 I3=L0_LUT4_I3_9_I2_LUT4_O_I3 O=L0_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_1_O I1=L0_LUT4_I1_1_I2_LUT4_O_I2 I2=R0_LUT4_I3_34_O_LUT4_I2_O I3=L0_LUT4_I1_8_I3_LUT4_O_I1_LUT4_O_I3 O=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I1_8_I3_LUT4_O_I1_LUT4_O_I1 I1=R0_LUT4_I3_34_O_LUT4_I2_2_O I2=R0_LUT4_I3_35_O_LUT4_I2_O I3=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_33_O I1=R0_LUT4_I3_32_O I2=R0_LUT4_I3_30_O I3=R0_LUT4_I3_31_O O=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_LUT4_I3_35_O_LUT4_I2_O I1=R0_LUT4_I3_34_O_LUT4_I2_2_O I2=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R0_LUT4_I3_34_O_LUT4_I2_2_O I1=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L0_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=R0_LUT4_I3_35_O_LUT4_I2_O O=L0_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_I2_O I1=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=L0_LUT4_I3_I0_LUT4_O_I2 I3=L0_LUT4_I3_I0_LUT4_O_I3 O=L0_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_O I1=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_47_O_LUT4_I2_O I3=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1 O=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_44_O I1=R0_LUT4_I3_43_O I2=R0_LUT4_I3_45_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_O I1=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1 I2=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3 I3=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2 O=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=R0_LUT4_I3_44_O I1=R0_LUT4_I3_45_O I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110111001111
+.subckt LUT4 I0=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_LUT4_I3_46_O_LUT4_I2_1_O I2=R0_LUT4_I3_46_O_LUT4_I2_2_O I3=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_LUT4_I3_44_O I2=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R0_LUT4_I3_45_O O=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R0_LUT4_I3_44_O I1=R0_LUT4_I3_43_O I2=R0_LUT4_I3_42_O I3=R0_LUT4_I3_45_O O=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0 I1=L0_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I2=L0_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R0_LUT4_I3_43_O I2=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=R0_LUT4_I3_45_O O=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=R0_LUT4_I3_46_O_LUT4_I2_O I2=R0_LUT4_I3_42_O I3=R0_LUT4_I3_44_O O=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I1_3_I2_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_O I1=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3 I2=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_LUT4_I3_46_O_LUT4_I2_1_O O=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_47_O_LUT4_I2_O I1=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I3=R0_LUT4_I3_46_O_LUT4_I2_2_O O=L0_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_I2_LUT4_O_I0 I1=L0_LUT4_I3_I2_LUT4_O_I1 I2=L0_LUT4_I3_I2_LUT4_O_I2 I3=L0_LUT4_I3_I2_LUT4_O_I3 O=L0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2 I3=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I3 O=L0_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_O I1=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_LUT4_I3_45_O I1=R0_LUT4_I3_44_O I2=R0_LUT4_I3_46_O_LUT4_I2_1_O I3=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_47_O_LUT4_I2_O I1=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_LUT4_I3_46_O_LUT4_I2_2_O I3=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=L0_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_LUT4_I3_46_O_LUT4_I2_O I3=R0_LUT4_I3_46_O_LUT4_I2_1_O O=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011001100110101
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_44_O I3=R0_LUT4_I3_45_O O=L0_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_LUT4_I3_46_O_LUT4_I2_O O=L0_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1 I3=R0_LUT4_I3_46_O_LUT4_I2_1_O O=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_LUT4_I3_47_O_LUT4_I2_O I1=L0_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_46_O_LUT4_I2_2_O I3=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_45_O I1=R0_LUT4_I3_44_O I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_O I1=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_LUT4_I3_47_O_LUT4_I2_O I3=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=L0_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_42_O I1=R0_LUT4_I3_44_O I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_45_O O=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_45_O I1=R0_LUT4_I3_44_O I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_LUT4_I3_46_O_LUT4_I2_1_O I1=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_LUT4_I3_46_O_LUT4_I2_2_O I3=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3 O=L0_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_LUT4_I3_44_O I1=R0_LUT4_I3_45_O I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_42_O O=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_LUT4_I3_44_O I1=R0_LUT4_I3_42_O I2=R0_LUT4_I3_43_O I3=R0_LUT4_I3_45_O O=L0_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt ff CQZ=L0(1) D=IP(33) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(2) D=IP(34) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(11) D=IP(43) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(12) D=IP(44) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(13) D=IP(45) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(14) D=IP(46) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(15) D=IP(47) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(16) D=IP(48) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(17) D=IP(49) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(18) D=IP(50) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(19) D=IP(51) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(20) D=IP(52) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(3) D=IP(35) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(21) D=IP(53) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(22) D=IP(54) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(23) D=IP(55) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(24) D=IP(56) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(25) D=IP(57) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(26) D=IP(58) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(27) D=IP(59) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(28) D=IP(60) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(29) D=IP(61) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(30) D=IP(62) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(4) D=IP(36) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(31) D=IP(63) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(32) D=IP(64) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(5) D=IP(37) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(6) D=IP(38) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(7) D=IP(39) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(8) D=IP(40) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(9) D=IP(41) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L0(10) D=IP(42) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:108.1-109.25|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L10(1) I2=L10_LUT4_I1_I2 I3=L10_LUT4_I1_I3 O=R11_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=L10(7) I2=L10_LUT4_I1_1_I2 I3=L10_LUT4_I1_1_I3 O=R11_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_1_I2_LUT4_O_I1 I2=L10_LUT4_I1_1_I2_LUT4_O_I2 I3=L10_LUT4_I1_1_I2_LUT4_O_I3 O=L10_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_16_I1_LUT4_O_I1 I2=L10_LUT4_I3_16_I1_LUT4_O_I3 I3=L10_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I1_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=L10_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_46_O_LUT4_I2_2_O I3=R10_LUT4_I3_46_O_LUT4_I2_O O=L10_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I0 I1=R10_LUT4_I3_46_O_LUT4_I2_2_O I2=L10_LUT4_I3_4_I2_LUT4_I2_I1 I3=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R10_LUT4_I3_44_O I1=R10_LUT4_I3_42_O I2=R10_LUT4_I3_43_O I3=R10_LUT4_I3_45_O O=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I2 I3=R10_LUT4_I3_46_O_LUT4_I2_O O=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_45_O I1=R10_LUT4_I3_44_O I2=R10_LUT4_I3_43_O I3=R10_LUT4_I3_42_O O=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_16_I1_LUT4_O_I3_LUT4_O_I3 I3=L10_LUT4_I1_1_I2_LUT4_O_I3 O=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_2_O I1=L10_LUT4_I3_4_I0_LUT4_O_I1 I2=L10_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I1_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I0 I3=R10_LUT4_I3_46_O_LUT4_I2_O O=L10_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 I2=R10_LUT4_I3_46_O_LUT4_I2_1_O I3=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_4_I0_LUT4_O_I2 I2=L10_LUT4_I1_1_I3_LUT4_O_I2 I3=L10_LUT4_I1_1_I3_LUT4_O_I3 O=L10_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_1_O I1=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_46_O_LUT4_I2_O I3=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_45_O I1=R10_LUT4_I3_43_O I2=R10_LUT4_I3_42_O I3=R10_LUT4_I3_44_O O=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_45_O I1=R10_LUT4_I3_44_O I2=R10_LUT4_I3_43_O I3=R10_LUT4_I3_42_O O=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_46_O_LUT4_I2_2_O I3=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_4_I1_LUT4_O_I3 I1=L10_LUT4_I3_26_I1_LUT4_O_I2 I2=L10_LUT4_I1_1_I3_LUT4_O_I2 I3=L10_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=R10_LUT4_I3_47_O_LUT4_I2_O I2=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=L10_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=R10_LUT4_I3_46_O_LUT4_I2_1_O I2=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 I3=R10_LUT4_I3_46_O_LUT4_I2_O O=L10_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10(26) I2=L10_LUT4_I1_2_I2 I3=L10_LUT4_I1_2_I3 O=R11_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_2_I2_LUT4_O_I1 I2=L10_LUT4_I1_2_I2_LUT4_O_I2 I3=L10_LUT4_I1_I3_LUT4_O_I2 O=L10_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_2_O O=L10_LUT4_I1_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R10_LUT4_I3_10_O_LUT4_I2_O O=L10_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=L10_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_2_O O=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_9_O I1=R10_LUT4_I3_8_O I2=R10_LUT4_I3_6_O I3=R10_LUT4_I3_7_O O=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_9_O I1=R10_LUT4_I3_8_O I2=R10_LUT4_I3_7_O I3=R10_LUT4_I3_6_O O=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=L10_LUT4_I2_I3_LUT4_O_I2 I2=L10_LUT4_I3_22_I1 I3=L10_LUT4_I1_2_I3_LUT4_O_I3 O=L10_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L10_LUT4_I1_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L10_LUT4_I1_I2_LUT4_O_I2 I3=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=L10_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_11_O_LUT4_I2_O O=L10_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_O O=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_2_O I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_9_O I1=R10_LUT4_I3_6_O I2=R10_LUT4_I3_7_O I3=R10_LUT4_I3_8_O O=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_9_O I1=R10_LUT4_I3_8_O I2=R10_LUT4_I3_7_O I3=R10_LUT4_I3_6_O O=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I1_I3_LUT4_O_I0 I1=L10_LUT4_I1_I3_LUT4_O_I1 I2=L10_LUT4_I1_I3_LUT4_O_I2 I3=L10_LUT4_I1_I3_LUT4_O_I3 O=L10_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2 I3=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3 O=L10_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_1_O O=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_7_O I1=R10_LUT4_I3_6_O I2=R10_LUT4_I3_9_O I3=R10_LUT4_I3_8_O O=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_9_O I1=R10_LUT4_I3_8_O I2=R10_LUT4_I3_7_O I3=R10_LUT4_I3_6_O O=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_2_O O=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_9_O I1=R10_LUT4_I3_7_O I2=R10_LUT4_I3_8_O I3=R10_LUT4_I3_6_O O=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_8_O I1=R10_LUT4_I3_7_O I2=R10_LUT4_I3_9_O I3=R10_LUT4_I3_6_O O=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_10_O_LUT4_I2_2_O I3=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_8_O I1=R10_LUT4_I3_7_O I2=R10_LUT4_I3_6_O I3=R10_LUT4_I3_9_O O=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L10_LUT4_I1_I3_LUT4_O_I3 I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_O O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_9_O I1=R10_LUT4_I3_8_O I2=R10_LUT4_I3_7_O I3=R10_LUT4_I3_6_O O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_8_O I1=R10_LUT4_I3_9_O I2=R10_LUT4_I3_7_O I3=R10_LUT4_I3_6_O O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_9_O I1=R10_LUT4_I3_7_O I2=R10_LUT4_I3_6_O I3=R10_LUT4_I3_8_O O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_2_O O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R10_LUT4_I3_10_O_LUT4_I2_2_O I3=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_7_O I1=R10_LUT4_I3_8_O I2=R10_LUT4_I3_9_O I3=R10_LUT4_I3_6_O O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_2_O I1=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I2=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_10_O_LUT4_I2_O O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I2=R10_LUT4_I3_11_O_LUT4_I2_O I3=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_8_O I1=R10_LUT4_I3_6_O I2=R10_LUT4_I3_7_O I3=R10_LUT4_I3_9_O O=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_22_I2_LUT4_O_I2 I3=L10_LUT4_I1_2_I2_LUT4_O_I2 O=L10_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10(10) I3=L10_LUT4_I2_I3 O=R11_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10(15) I3=L10_LUT4_I2_1_I3 O=R11_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L10_LUT4_I2_1_I3_LUT4_O_I0 I1=L10_LUT4_I3_6_I0_LUT4_I0_O I2=L10_LUT4_I2_1_I3_LUT4_O_I2 I3=L10_LUT4_I2_1_I3_LUT4_O_I3 O=L10_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L10_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3 O=L10_LUT4_I2_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_16_O_LUT4_I2_O I3=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_17_O_LUT4_I2_O I1=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0 I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_6_I0_LUT4_O_I3 I3=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O O=L10_LUT4_I2_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L10_LUT4_I2_I3_LUT4_O_I0 I1=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=L10_LUT4_I2_I3_LUT4_O_I2 I3=L10_LUT4_I2_I3_LUT4_O_I3 O=L10_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L10_LUT4_I1_I3_LUT4_O_I3 I1=L10_LUT4_I1_I3_LUT4_O_I1 I2=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I1_I2_LUT4_O_I2 I1=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_22_I1_LUT4_O_I2 I3=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_1_O O=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_O O=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_10_O_LUT4_I2_2_O I3=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_O I1=L10_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R10_LUT4_I3_10_O_LUT4_I2_2_O O=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3 O=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_O I1=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_11_O_LUT4_I2_O O=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_O O=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_10_O_LUT4_I2_1_O O=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_10_O_LUT4_I2_2_O I3=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_I0 I1=L10_LUT4_I3_I1 I2=L10_LUT4_I3_I2 I3=L10(2) O=R11_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I1=L10_LUT4_I3_1_I1 I2=L10_LUT4_I3_1_I2 I3=L10(6) O=R11_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L10_LUT4_I3_10_I0 I1=L10_LUT4_I3_21_I0 I2=L10_LUT4_I3_10_I2 I3=L10(29) O=R11_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_21_I2_LUT4_O_I1 I3=L10_LUT4_I3_2_I1 O=L10_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_2_I2_LUT4_O_I2 I3=L10_LUT4_I3_21_I1_LUT4_O_I1 O=L10_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L10_LUT4_I3_14_I0 I1=L10_LUT4_I3_11_I1 I2=L10_LUT4_I3_11_I2 I3=L10(3) O=R11_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I0_LUT4_O_I3 I2=L10_LUT4_I3_8_I0_LUT4_O_I1 I3=L10_LUT4_I3_8_I0_LUT4_O_I2 O=L10_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_18_I2_LUT4_O_I2 I2=L10_LUT4_I3_14_I2_LUT4_O_I3 I3=L10_LUT4_I3_11_I2_LUT4_O_I3 O=L10_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3 I2=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I3_8_I2_LUT4_O_I3 O=L10_LUT4_I3_11_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L10_LUT4_I3_21_I0 I1=L10_LUT4_I3_12_I1 I2=L10_LUT4_I3_12_I2 I3=L10(4) O=R11_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_12_I1_LUT4_O_I1 I2=L10_LUT4_I3_12_I1_LUT4_O_I2 I3=L10_LUT4_I3_21_I0_LUT4_O_I1 O=L10_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_O I1=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_28_O_LUT4_I2_1_O I3=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 O=L10_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=R10_LUT4_I3_29_O_LUT4_I2_O I2=R10_LUT4_I3_28_O_LUT4_I2_2_O I3=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_1_O I1=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_28_O_LUT4_I2_2_O I3=L10_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2 O=L10_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_O I1=L10_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_29_O_LUT4_I2_O O=L10_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_21_I2_LUT4_O_I1 I1=L10_LUT4_I3_2_I0_LUT4_O_I3 I2=L10_LUT4_I3_12_I2_LUT4_O_I2 I3=L10_LUT4_I3_12_I2_LUT4_O_I3 O=L10_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_2_O I1=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_29_O_LUT4_I2_O I3=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_O I1=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 I2=R10_LUT4_I3_28_O_LUT4_I2_1_O I3=L10_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I3_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_13_I0 I1=L10_LUT4_I3_13_I1 I2=L10_LUT4_I3_13_I2 I3=L10(5) O=R11_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L10_LUT4_I2_1_I3_LUT4_O_I0 I1=L10_LUT4_I3_6_I1_LUT4_O_I0 I2=L10_LUT4_I3_6_I0_LUT4_I0_O I3=L10_LUT4_I3_13_I0_LUT4_O_I3 O=L10_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=L10_LUT4_I3_13_I1_LUT4_O_I0 I1=L10_LUT4_I3_6_I2_LUT4_O_I1 I2=L10_LUT4_I3_13_I1_LUT4_O_I2 I3=L10_LUT4_I3_13_I1_LUT4_O_I3 O=L10_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_13_I1_LUT4_O_I0_LUT4_O_I1 I2=L10_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 I3=R10_LUT4_I3_16_O_LUT4_I2_1_O O=L10_LUT4_I3_13_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_13_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3 I3=R10_LUT4_I3_16_O_LUT4_I2_O O=L10_LUT4_I3_13_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_17_O_LUT4_I2_O I1=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L10_LUT4_I3_13_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_17_O_LUT4_I2_O I1=L10_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_16_O_LUT4_I2_2_O O=L10_LUT4_I3_13_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_14_O I1=R10_LUT4_I3_12_O I2=R10_LUT4_I3_13_O I3=R10_LUT4_I3_15_O O=L10_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_16_O_LUT4_I2_O I3=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I3_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_15_O I1=R10_LUT4_I3_13_O I2=R10_LUT4_I3_14_O I3=R10_LUT4_I3_12_O O=L10_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_13_I2_LUT4_I2_I1 I2=L10_LUT4_I3_13_I2 I3=L10_LUT4_I3_13_I1_LUT4_O_I0 O=L10_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_13_I2_LUT4_O_I1 I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_13_I2_LUT4_O_I3 O=L10_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_16_O_LUT4_I2_O O=L10_LUT4_I3_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_I3 I2=R10_LUT4_I3_17_O_LUT4_I2_O I3=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_13_I2_LUT4_O_I3 I2=R10_LUT4_I3_16_O_LUT4_I2_O I3=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_I3 O=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_15_O I1=R10_LUT4_I3_12_O I2=R10_LUT4_I3_13_O I3=R10_LUT4_I3_14_O O=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O I1=L10_LUT4_I3_6_I0_LUT4_I1_I3_LUT4_O_I2 I2=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2 I3=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3 O=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_O I1=L10_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2 I2=L10_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_16_O_LUT4_I2_2_O O=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I2=L10_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_17_O_LUT4_I2_O O=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_15_O I1=R10_LUT4_I3_14_O I2=R10_LUT4_I3_13_O I3=R10_LUT4_I3_12_O O=L10_LUT4_I3_13_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_14_I0 I1=L10_LUT4_I3_14_I1 I2=L10_LUT4_I3_14_I2 I3=L10(8) O=R11_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_18_I2 I2=L10_LUT4_I3_14_I0_LUT4_O_I2 I3=L10_LUT4_I3_18_I0_LUT4_O_I3 O=L10_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_14_I0_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_8_I2_LUT4_O_I1 O=L10_LUT4_I3_14_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I3_O I1=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_8_I1_LUT4_I1_I2 I3=L10_LUT4_I3_14_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_14_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_O_LUT4_I2_2_O I3=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_14_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_18_I1_LUT4_O_I1 I3=L10_LUT4_I3_8_I0_LUT4_O_I0 O=L10_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_18_I2_LUT4_O_I2 I2=L10_LUT4_I3_8_I2_LUT4_O_I1 I3=L10_LUT4_I3_14_I2_LUT4_O_I3 O=L10_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_O_LUT4_I2_2_O I3=L10_LUT4_I3_8_I1_LUT4_I1_I2 O=L10_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_O_LUT4_I2_1_O I3=L10_LUT4_I3_18_I2_LUT4_O_I0 O=L10_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_O_LUT4_I3_O I3=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_24_I0 I1=L10_LUT4_I3_15_I1 I2=L10_LUT4_I3_15_I2 I3=L10(9) O=R11_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_15_I1_LUT4_O_I1 I2=L10_LUT4_I3_24_I1_LUT4_O_I1 I3=L10_LUT4_I3_24_I1_LUT4_O_I2 O=L10_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_15_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_41_O_LUT4_I2_O I3=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_1_O I1=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I3 I2=L10_LUT4_I3_24_I0_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_40_O_LUT4_I2_2_O O=L10_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_24_I2_LUT4_O_I2 I3=L10_LUT4_I3_3_I1_LUT4_O_I3 O=L10_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L10_LUT4_I3_26_I0 I1=L10_LUT4_I3_16_I1 I2=L10_LUT4_I3_16_I2 I3=L10(12) O=R11_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L10_LUT4_I3_26_I2_LUT4_O_I3 I1=L10_LUT4_I3_16_I1_LUT4_O_I1 I2=L10_LUT4_I3_16_I1_LUT4_O_I2 I3=L10_LUT4_I3_16_I1_LUT4_O_I3 O=L10_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_16_I1_LUT4_O_I1_LUT4_I3_I1 I2=L10_LUT4_I3_16_I1_LUT4_O_I1_LUT4_I3_I2 I3=L10_LUT4_I3_16_I1_LUT4_O_I1 O=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_1_O I1=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R10_LUT4_I3_46_O_LUT4_I2_O I3=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_16_I1_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3 I2=R10_LUT4_I3_46_O_LUT4_I2_2_O I3=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I0 O=L10_LUT4_I3_16_I1_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_16_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_46_O_LUT4_I2_1_O I3=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_2_O I1=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=R10_LUT4_I3_46_O_LUT4_I2_O O=L10_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_1_I2_LUT4_O_I2 I3=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3 O=L10_LUT4_I3_16_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_16_I1_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I3_16_I1_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_16_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_2_O I1=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3 I2=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_46_O_LUT4_I2_O O=L10_LUT4_I3_16_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I0 I2=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_46_O_LUT4_I2_1_O O=L10_LUT4_I3_16_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_26_I1_LUT4_O_I2 I2=L10_LUT4_I3_4_I1_LUT4_O_I3 I3=L10_LUT4_I3_4_I1_LUT4_O_I1 O=L10_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L10_LUT4_I3_17_I0 I1=L10_LUT4_I3_17_I1 I2=L10_LUT4_I3_17_I2 I3=L10(13) O=R11_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=L10_LUT4_I3_I0_LUT4_O_I2 I1=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I2=L10_LUT4_I3_I0_LUT4_O_I1 I3=L10_LUT4_I3_17_I0_LUT4_O_I3 O=L10_LUT4_I3_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_I1_LUT4_O_I1 I2=L10_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=L10_LUT4_I3_17_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L10_LUT4_I3_17_I1_LUT4_O_I0 I1=R10_LUT4_I3_23_O_LUT4_I2_O I2=L10_LUT4_I3_I2_LUT4_O_I1 I3=L10_LUT4_I3_17_I1_LUT4_O_I3 O=L10_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R10_LUT4_I3_21_O I1=R10_LUT4_I3_20_O I2=R10_LUT4_I3_19_O I3=R10_LUT4_I3_18_O O=L10_LUT4_I3_17_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_22_O_LUT4_I2_1_O I3=L10_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_17_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_20_I2_LUT4_I3_I2_LUT4_O_I3 I2=R10_LUT4_I3_22_O_LUT4_I2_2_O I3=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_21_O I1=R10_LUT4_I3_20_O I2=R10_LUT4_I3_19_O I3=R10_LUT4_I3_18_O O=L10_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_17_I2_LUT4_O_I1 I2=R10_LUT4_I3_22_O_LUT4_I2_2_O I3=L10_LUT4_I3_17_I1_LUT4_O_I0 O=L10_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_22_O_LUT4_I2_1_O O=L10_LUT4_I3_17_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_20_I2_LUT4_I3_I1_LUT4_O_I3 I2=R10_LUT4_I3_23_O_LUT4_I2_O I3=L10_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 O=L10_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_21_O I1=R10_LUT4_I3_18_O I2=R10_LUT4_I3_19_O I3=R10_LUT4_I3_20_O O=L10_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L10_LUT4_I3_18_I0 I1=L10_LUT4_I3_18_I1 I2=L10_LUT4_I3_18_I2 I3=L10(14) O=R11_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_8_I2_LUT4_O_I3 I3=L10_LUT4_I3_18_I0_LUT4_O_I3 O=L10_LUT4_I3_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=L10_LUT4_I3_8_I2_LUT4_O_I3 I1=L10_LUT4_I3_8_I1_LUT4_I1_O I2=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_18_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I3_O I1=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_O_LUT4_I2_1_O I3=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_5_O I1=R10_LUT4_I3_3_O I2=R10_LUT4_I3_4_O I3=R10_LUT4_I3_2_O O=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_O_LUT4_I2_2_O O=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_4_O I1=R10_LUT4_I3_5_O I2=R10_LUT4_I3_3_O I3=R10_LUT4_I3_2_O O=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_5_O I1=R10_LUT4_I3_4_O I2=R10_LUT4_I3_3_O I3=R10_LUT4_I3_2_O O=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_18_I1_LUT4_O_I1 I2=L10_LUT4_I3_18_I1_LUT4_O_I2 I3=L10_LUT4_I3_8_I0_LUT4_O_I2 O=L10_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_18_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_8_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_1_I1 I3=R10_LUT4_I3_O_LUT4_I2_2_O O=L10_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I3_O I1=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_I1 I2=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I3=R10_LUT4_I3_O_LUT4_I2_1_O O=L10_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_18_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I3_O I1=L10_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_O_LUT4_I2_1_O I3=L10_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_4_O I1=R10_LUT4_I3_3_O I2=R10_LUT4_I3_5_O I3=R10_LUT4_I3_2_O O=L10_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 I2=R10_LUT4_I3_O_LUT4_I2_2_O I3=L10_LUT4_I3_8_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_18_I2_LUT4_O_I0 I1=R10_LUT4_I3_O_LUT4_I2_2_O I2=L10_LUT4_I3_18_I2_LUT4_O_I2 I3=L10_LUT4_I3_18_I2_LUT4_O_I3 O=L10_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R10_LUT4_I3_5_O I1=R10_LUT4_I3_4_O I2=R10_LUT4_I3_3_O I3=R10_LUT4_I3_2_O O=L10_LUT4_I3_18_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_18_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_O_LUT4_I2_1_O O=L10_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I3_O I1=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_O_LUT4_I2_2_O O=L10_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_O_LUT4_I2_1_O O=L10_LUT4_I3_18_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_O_LUT4_I3_O O=L10_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_2_O I1=R10_LUT4_I3_4_O I2=R10_LUT4_I3_3_O I3=R10_LUT4_I3_5_O O=L10_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L10_LUT4_I3_19_I0 I1=L10_LUT4_I3_25_I1 I2=L10_LUT4_I3_19_I2 I3=L10(16) O=R11_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_25_I2 I2=L10_LUT4_I3_19_I0_LUT4_O_I2 I3=L10_LUT4_I3_1_I1_LUT4_O_I3 O=L10_LUT4_I3_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=L10_LUT4_I3_19_I2_LUT4_I3_I0 I1=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I2=L10_LUT4_I3_25_I2_LUT4_O_I3 I3=L10_LUT4_I3_19_I2 O=L10_LUT4_I3_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_5_I0_LUT4_O_I0_LUT4_I3_1_O I3=L10_LUT4_I3_19_I2_LUT4_I3_I0_LUT4_O_I3 O=L10_LUT4_I3_19_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_35_O_LUT4_I2_O I1=L10_LUT4_I3_25_I1_LUT4_O_I3_LUT4_O_I0 I2=R10_LUT4_I3_34_O_LUT4_I2_2_O I3=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I3_19_I2_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_2_O I1=R10_LUT4_I3_34_O_LUT4_I2_1_O I2=L10_LUT4_I3_19_I2_LUT4_O_I2 I3=L10_LUT4_I3_19_I2_LUT4_O_I3 O=L10_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_19_I2_LUT4_O_I2_LUT4_I2_I1 I2=L10_LUT4_I3_19_I2_LUT4_O_I2 I3=R10_LUT4_I3_34_O_LUT4_I2_1_O O=L10_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_35_O_LUT4_I2_O I1=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I2=L10_LUT4_I3_25_I1_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_34_O_LUT4_I2_2_O O=L10_LUT4_I3_19_I2_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_33_O I1=R10_LUT4_I3_32_O I2=R10_LUT4_I3_31_O I3=R10_LUT4_I3_30_O O=L10_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_1_O I1=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_34_O_LUT4_I2_2_O I3=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I3_19_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_1_I1_LUT4_O_I0 I1=L10_LUT4_I3_5_I1_LUT4_O_I1 I2=L10_LUT4_I3_1_I1_LUT4_O_I2 I3=L10_LUT4_I3_1_I1_LUT4_O_I3 O=L10_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=R10_LUT4_I3_35_O_LUT4_I2_O I1=R10_LUT4_I3_34_O_LUT4_I2_O I2=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_35_O_LUT4_I2_O O=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_32_O I1=R10_LUT4_I3_33_O I2=R10_LUT4_I3_31_O I3=R10_LUT4_I3_30_O O=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_35_O_LUT4_I2_O I3=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_32_O I1=R10_LUT4_I3_30_O I2=R10_LUT4_I3_31_O I3=R10_LUT4_I3_33_O O=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_33_O I1=R10_LUT4_I3_32_O I2=R10_LUT4_I3_30_O I3=R10_LUT4_I3_31_O O=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L10_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I0 I1=L10_LUT4_I3_19_I2_LUT4_I3_I0 I2=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I3=L10_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_1_I2_LUT4_O_I3 I1=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R10_LUT4_I3_34_O I3=R10_LUT4_I3_35_O O=L10_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_35_O_LUT4_I2_O O=L10_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_1_I1_LUT4_O_I2 I2=L10_LUT4_I3_1_I2 I3=L10_LUT4_I3_5_I1_LUT4_O_I1 O=L10_LUT4_I3_19_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_1_I2_LUT4_O_I1 I2=R10_LUT4_I3_34_O_LUT4_I2_2_O I3=L10_LUT4_I3_1_I2_LUT4_O_I3 O=L10_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_34_O_LUT4_I2_1_O O=L10_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_35_O_LUT4_I2_O O=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_33_O I1=R10_LUT4_I3_32_O I2=R10_LUT4_I3_31_O I3=R10_LUT4_I3_30_O O=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_31_O I1=R10_LUT4_I3_32_O I2=R10_LUT4_I3_33_O I3=R10_LUT4_I3_30_O O=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_33_O I1=R10_LUT4_I3_32_O I2=R10_LUT4_I3_31_O I3=R10_LUT4_I3_30_O O=L10_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L10_LUT4_I3_2_I0 I1=L10_LUT4_I3_2_I1 I2=L10_LUT4_I3_2_I2 I3=L10(11) O=R11_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L10_LUT4_I3_20_I0 I1=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I2=L10_LUT4_I3_20_I2 I3=L10(18) O=R11_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=L10_LUT4_I3_17_I2 I1=L10_LUT4_I3_9_I0_LUT4_O_I2 I2=L10_LUT4_I3_I2_LUT4_O_I1 I3=L10_LUT4_I3_20_I0_LUT4_O_I3 O=L10_LUT4_I3_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_20_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_2_O I1=L10_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I2=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_22_O_LUT4_I2_1_O O=L10_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I2=R10_LUT4_I3_23_O_LUT4_I2_O I3=L10_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L10_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_20_I2_LUT4_I3_I1 I2=L10_LUT4_I3_20_I2_LUT4_I3_I2 I3=L10_LUT4_I3_20_I2 O=L10_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I3 I2=R10_LUT4_I3_23_O_LUT4_I2_O I3=L10_LUT4_I3_20_I2_LUT4_I3_I1_LUT4_O_I3 O=L10_LUT4_I3_20_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_21_O I1=R10_LUT4_I3_20_O I2=R10_LUT4_I3_18_O I3=R10_LUT4_I3_19_O O=L10_LUT4_I3_20_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_2_O I1=L10_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_22_O_LUT4_I2_1_O I3=L10_LUT4_I3_20_I2_LUT4_I3_I2_LUT4_O_I3 O=L10_LUT4_I3_20_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_20_O I1=R10_LUT4_I3_18_O I2=R10_LUT4_I3_19_O I3=R10_LUT4_I3_21_O O=L10_LUT4_I3_20_I2_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_20_I2_LUT4_O_I1 I2=L10_LUT4_I3_20_I2_LUT4_O_I2 I3=L10_LUT4_I3_I1_LUT4_O_I1 O=L10_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_2_O I1=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_22_O_LUT4_I2_1_O O=L10_LUT4_I3_20_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_20_O I1=R10_LUT4_I3_19_O I2=R10_LUT4_I3_21_O I3=R10_LUT4_I3_18_O O=L10_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_23_O_LUT4_I2_O I3=L10_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_19_O I1=R10_LUT4_I3_18_O I2=R10_LUT4_I3_21_O I3=R10_LUT4_I3_20_O O=L10_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_20_O I1=R10_LUT4_I3_21_O I2=R10_LUT4_I3_19_O I3=R10_LUT4_I3_18_O O=L10_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L10_LUT4_I3_21_I0 I1=L10_LUT4_I3_21_I1 I2=L10_LUT4_I3_21_I2 I3=L10(19) O=R11_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_21_I0_LUT4_O_I1 I2=L10_LUT4_I3_2_I2 I3=L10_LUT4_I3_21_I0_LUT4_O_I3 O=L10_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_21_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_O I1=L10_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_28_O_LUT4_I2_1_O I3=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=L10_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_26_O I1=R10_LUT4_I3_24_O I2=R10_LUT4_I3_25_O I3=R10_LUT4_I3_27_O O=L10_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L10_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=R10_LUT4_I3_28_O_LUT4_I2_2_O I2=R10_LUT4_I3_29_O_LUT4_I2_O I3=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_21_I1_LUT4_O_I1 I1=L10_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I3_12_I1_LUT4_O_I1 O=L10_LUT4_I3_21_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I1=L10_LUT4_I3_2_I2_LUT4_O_I0 I2=R10_LUT4_I3_29_O I3=R10_LUT4_I3_28_O O=L10_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_O I1=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_29_O_LUT4_I2_O O=L10_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_21_I1_LUT4_O_I1 I2=L10_LUT4_I3_21_I1_LUT4_O_I2 I3=L10_LUT4_I3_21_I0_LUT4_O_I3 O=L10_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_2_I2_LUT4_O_I0 I3=R10_LUT4_I3_28_O_LUT4_I2_O O=L10_LUT4_I3_21_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_28_O_LUT4_I2_1_O I3=L10_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_2_O I1=L10_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_29_O_LUT4_I2_O I3=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_26_O I1=R10_LUT4_I3_25_O I2=R10_LUT4_I3_27_O I3=R10_LUT4_I3_24_O O=L10_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_21_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_1_O I1=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_29_O_LUT4_I2_O I3=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=L10_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_O I1=L10_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=R10_LUT4_I3_28_O_LUT4_I2_2_O I3=L10_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_26_O I1=R10_LUT4_I3_27_O I2=R10_LUT4_I3_25_O I3=R10_LUT4_I3_24_O O=L10_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L10_LUT4_I3_21_I2_LUT4_O_I0 I1=L10_LUT4_I3_21_I2_LUT4_O_I1 I2=L10_LUT4_I3_2_I0_LUT4_O_I2 I3=L10_LUT4_I3_2_I1_LUT4_O_I3 O=L10_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_2_O I1=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I3_2_I0_LUT4_O_I3 I3=L10_LUT4_I3_21_I2_LUT4_O_I0_LUT4_O_I3 O=L10_LUT4_I3_21_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_21_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_28_O_LUT4_I2_O O=L10_LUT4_I3_21_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_1_O I1=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=R10_LUT4_I3_29_O_LUT4_I2_O I3=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_21_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_29_O_LUT4_I2_O I1=L10_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_2_I0_LUT4_O_I2 I3=L10_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_21_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_2_O I1=L10_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R10_LUT4_I3_29_O_LUT4_I2_O O=L10_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_27_O I1=R10_LUT4_I3_26_O I2=R10_LUT4_I3_25_O I3=R10_LUT4_I3_24_O O=L10_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 I1=L10_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_29_O I3=R10_LUT4_I3_28_O O=L10_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=L10_LUT4_I3_22_I0 I1=L10_LUT4_I3_22_I1 I2=L10_LUT4_I3_22_I2 I3=L10(20) O=R11_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L10_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=L10_LUT4_I3_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_22_I1_LUT4_O_I2 I3=L10_LUT4_I1_I2_LUT4_O_I2 O=L10_LUT4_I3_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_22_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L10_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_10_O_LUT4_I2_2_O O=L10_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_6_O I1=R10_LUT4_I3_8_O I2=R10_LUT4_I3_7_O I3=R10_LUT4_I3_9_O O=L10_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_I3_LUT4_O_I0 I2=L10_LUT4_I3_22_I2_LUT4_O_I2 I3=L10_LUT4_I1_2_I2_LUT4_O_I1 O=L10_LUT4_I3_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_22_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_11_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_2_O I1=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R10_LUT4_I3_10_O_LUT4_I2_1_O I3=L10_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R10_LUT4_I3_11_O_LUT4_I2_O O=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O I2=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R10_LUT4_I3_10_O_LUT4_I2_O O=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_9_O I1=R10_LUT4_I3_8_O I2=R10_LUT4_I3_7_O I3=R10_LUT4_I3_6_O O=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R10_LUT4_I3_10_O_LUT4_I2_O I1=L10_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R10_LUT4_I3_10_O_LUT4_I2_2_O I3=L10_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_22_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_23_I0 I1=L10_LUT4_I3_23_I1 I2=L10_LUT4_I3_23_I2 I3=L10(21) O=R11_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_6_I1_LUT4_O_I0 I2=L10_LUT4_I2_1_I3_LUT4_O_I0 I3=L10_LUT4_I3_6_I0_LUT4_I0_O O=L10_LUT4_I3_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_6_I0_LUT4_O_I2 I2=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L10_LUT4_I3_6_I0_LUT4_I0_O O=L10_LUT4_I3_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_23_I2_LUT4_O_I1 I2=L10_LUT4_I3_23_I2_LUT4_O_I2 I3=L10_LUT4_I3_6_I2_LUT4_O_I0 O=L10_LUT4_I3_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_O I1=L10_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_23_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_17_O_LUT4_I2_O I3=L10_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_23_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_17_O_LUT4_I2_O I1=L10_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_6_I0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_15_O I1=R10_LUT4_I3_14_O I2=R10_LUT4_I3_13_O I3=R10_LUT4_I3_12_O O=L10_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_I3 I1=R10_LUT4_I3_17_O_LUT4_I2_O I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_15_O I1=R10_LUT4_I3_14_O I2=R10_LUT4_I3_13_O I3=R10_LUT4_I3_12_O O=L10_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L10_LUT4_I3_24_I0 I1=L10_LUT4_I3_24_I1 I2=L10_LUT4_I3_24_I2 I3=L10(23) O=R11_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L10_LUT4_I3_7_I0_LUT4_O_I0 I1=L10_LUT4_I3_3_I0_LUT4_O_I2 I2=L10_LUT4_I3_24_I0_LUT4_O_I2 I3=L10_LUT4_I3_24_I0_LUT4_O_I3 O=L10_LUT4_I3_24_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_24_I0_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_24_I0_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_40_O_LUT4_I2_1_O O=L10_LUT4_I3_24_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_38_O I1=R10_LUT4_I3_37_O I2=R10_LUT4_I3_36_O I3=R10_LUT4_I3_39_O O=L10_LUT4_I3_24_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_37_O I1=R10_LUT4_I3_38_O I2=R10_LUT4_I3_39_O I3=R10_LUT4_I3_36_O O=L10_LUT4_I3_24_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_41_O_LUT4_I2_O I1=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_40_O_LUT4_I2_2_O I3=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_24_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_36_O I1=R10_LUT4_I3_38_O I2=R10_LUT4_I3_37_O I3=R10_LUT4_I3_39_O O=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_37_O I1=R10_LUT4_I3_36_O I2=R10_LUT4_I3_39_O I3=R10_LUT4_I3_38_O O=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L10_LUT4_I3_7_I1 I1=L10_LUT4_I3_24_I1_LUT4_O_I1 I2=L10_LUT4_I3_24_I1_LUT4_O_I2 I3=L10_LUT4_I3_24_I1_LUT4_O_I3 O=L10_LUT4_I3_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_24_I1_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_24_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_24_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_40_O_LUT4_I2_2_O I3=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 O=L10_LUT4_I3_24_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_1_O I1=L10_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_41_O_LUT4_I2_O I3=L10_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_24_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_24_I1_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_40_O_LUT4_I2_O O=L10_LUT4_I3_24_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_40_O_LUT4_I2_2_O I3=L10_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_24_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_1_O I1=L10_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_41_O_LUT4_I2_O I3=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_3_I0_LUT4_O_I2 I2=L10_LUT4_I3_24_I2_LUT4_O_I2 I3=L10_LUT4_I3_3_I1_LUT4_O_I2 O=L10_LUT4_I3_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_24_I2_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_24_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_24_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I3 I2=L10_LUT4_I3_24_I0_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_41_O_LUT4_I2_O O=L10_LUT4_I3_24_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_1_O I1=L10_LUT4_I3_24_I0_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_40_O_LUT4_I2_2_O O=L10_LUT4_I3_24_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_25_I0 I1=L10_LUT4_I3_25_I1 I2=L10_LUT4_I3_25_I2 I3=L10(30) O=R11_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_25_I0_LUT4_O_I2 I3=L10_LUT4_I3_5_I1_LUT4_O_I3 O=L10_LUT4_I3_25_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L10_LUT4_I3_19_I2_LUT4_I3_I0 I1=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I2=L10_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_25_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_35_O_LUT4_I2_O I3=L10_LUT4_I3_25_I1_LUT4_O_I2_LUT4_O_I2 O=L10_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_1_O I1=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I3_25_I1_LUT4_O_I3_LUT4_O_I0 I3=R10_LUT4_I3_34_O_LUT4_I2_2_O O=L10_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_25_I1_LUT4_O_I1 I2=L10_LUT4_I3_25_I1_LUT4_O_I2 I3=L10_LUT4_I3_25_I1_LUT4_O_I3 O=L10_LUT4_I3_25_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_5_I2_LUT4_O_I2 I2=L10_LUT4_I3_25_I1_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_35_O_LUT4_I2_O O=L10_LUT4_I3_25_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_33_O I1=R10_LUT4_I3_31_O I2=R10_LUT4_I3_30_O I3=R10_LUT4_I3_32_O O=L10_LUT4_I3_25_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_25_I1_LUT4_O_I2_LUT4_I3_I2 I3=L10_LUT4_I3_25_I1_LUT4_O_I2 O=L10_LUT4_I3_5_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_35_O_LUT4_I2_O I1=R10_LUT4_I3_34_O_LUT4_I2_O I2=L10_LUT4_I3_25_I1_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_25_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_25_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R10_LUT4_I3_33_O I1=R10_LUT4_I3_32_O I2=R10_LUT4_I3_31_O I3=R10_LUT4_I3_30_O O=L10_LUT4_I3_25_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_25_I1_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_35_O_LUT4_I2_O I3=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L10_LUT4_I3_25_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_25_I1_LUT4_O_I3_LUT4_O_I0 I1=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_35_O I3=R10_LUT4_I3_34_O O=L10_LUT4_I3_25_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=R10_LUT4_I3_30_O I1=R10_LUT4_I3_32_O I2=R10_LUT4_I3_31_O I3=R10_LUT4_I3_33_O O=L10_LUT4_I3_25_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_1_I1_LUT4_O_I2 I3=L10_LUT4_I3_25_I2_LUT4_O_I3 O=L10_LUT4_I3_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_35_O_LUT4_I2_O I3=L10_LUT4_I3_1_I2_LUT4_O_I3 O=L10_LUT4_I3_25_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_35_O_LUT4_I2_O I1=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R10_LUT4_I3_34_O_LUT4_I2_O O=L10_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=L10_LUT4_I3_26_I0 I1=L10_LUT4_I3_26_I1 I2=L10_LUT4_I3_26_I2 I3=L10(32) O=R11_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_1_I3_LUT4_O_I3 I3=L10_LUT4_I3_26_I0_LUT4_O_I3 O=L10_LUT4_I3_26_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I1_1_I3_LUT4_O_I2 I2=L10_LUT4_I3_26_I1_LUT4_O_I2 I3=L10_LUT4_I3_4_I0 O=L10_LUT4_I3_26_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_26_I1_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_4_I0_LUT4_O_I1 I3=R10_LUT4_I3_47_O_LUT4_I2_O O=L10_LUT4_I3_26_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_26_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_46_O_LUT4_I2_2_O O=L10_LUT4_I3_26_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_1_O I1=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R10_LUT4_I3_46_O_LUT4_I2_O I3=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_26_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I1_1_I2_LUT4_O_I3 I3=L10_LUT4_I3_26_I2_LUT4_O_I3 O=L10_LUT4_I3_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I2 I3=L10_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_26_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=L10_LUT4_I3_2_I0_LUT4_O_I0 I1=L10_LUT4_I3_2_I0_LUT4_O_I1 I2=L10_LUT4_I3_2_I0_LUT4_O_I2 I3=L10_LUT4_I3_2_I0_LUT4_O_I3 O=L10_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I1=L10_LUT4_I3_2_I2_LUT4_O_I0 I2=R10_LUT4_I3_29_O I3=R10_LUT4_I3_28_O O=L10_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_O I1=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_28_O_LUT4_I2_1_O I3=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_25_O I1=R10_LUT4_I3_24_O I2=R10_LUT4_I3_27_O I3=R10_LUT4_I3_26_O O=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_27_O I1=R10_LUT4_I3_24_O I2=R10_LUT4_I3_25_O I3=R10_LUT4_I3_26_O O=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_28_O_LUT4_I2_O O=L10_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1 I3=R10_LUT4_I3_28_O_LUT4_I2_1_O O=L10_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_O I1=L10_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 I2=R10_LUT4_I3_28_O_LUT4_I2_1_O I3=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_2_O I1=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_29_O_LUT4_I2_O I3=L10_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_2_I1_LUT4_O_I1 I2=L10_LUT4_I3_2_I1_LUT4_O_I2 I3=L10_LUT4_I3_2_I1_LUT4_O_I3 O=L10_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_O I1=L10_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_29_O_LUT4_I2_O O=L10_LUT4_I3_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_27_O I1=R10_LUT4_I3_26_O I2=R10_LUT4_I3_24_O I3=R10_LUT4_I3_25_O O=L10_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_27_O I1=R10_LUT4_I3_25_O I2=R10_LUT4_I3_24_O I3=R10_LUT4_I3_26_O O=L10_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_1_O I1=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_28_O_LUT4_I2_2_O I3=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_27_O I1=R10_LUT4_I3_25_O I2=R10_LUT4_I3_26_O I3=R10_LUT4_I3_24_O O=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_27_O I1=R10_LUT4_I3_26_O I2=R10_LUT4_I3_25_O I3=R10_LUT4_I3_24_O O=L10_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_29_O_LUT4_I2_O O=L10_LUT4_I3_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_28_O_LUT4_I2_O O=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_1_O I1=L10_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_28_O_LUT4_I2_2_O I3=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_27_O I1=R10_LUT4_I3_26_O I2=R10_LUT4_I3_25_O I3=R10_LUT4_I3_24_O O=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_27_O I1=R10_LUT4_I3_26_O I2=R10_LUT4_I3_25_O I3=R10_LUT4_I3_24_O O=L10_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L10_LUT4_I3_2_I2_LUT4_O_I0 I1=R10_LUT4_I3_28_O_LUT4_I2_1_O I2=L10_LUT4_I3_2_I2_LUT4_O_I2 I3=L10_LUT4_I3_2_I2_LUT4_O_I3 O=L10_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R10_LUT4_I3_27_O I1=R10_LUT4_I3_26_O I2=R10_LUT4_I3_25_O I3=R10_LUT4_I3_24_O O=L10_LUT4_I3_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_12_I1_LUT4_O_I2 I3=L10_LUT4_I3_21_I1_LUT4_O_I2 O=L10_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_28_O_LUT4_I2_O O=L10_LUT4_I3_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_28_O_LUT4_I2_2_O I1=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_29_O_LUT4_I2_O I3=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_25_O I1=R10_LUT4_I3_26_O I2=R10_LUT4_I3_27_O I3=R10_LUT4_I3_24_O O=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_24_O I1=R10_LUT4_I3_26_O I2=R10_LUT4_I3_25_O I3=R10_LUT4_I3_27_O O=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_26_O I1=R10_LUT4_I3_25_O I2=R10_LUT4_I3_24_O I3=R10_LUT4_I3_27_O O=L10_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L10_LUT4_I3_3_I0 I1=L10_LUT4_I3_3_I1 I2=L10_LUT4_I3_3_I2 I3=L10(17) O=R11_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L10_LUT4_I3_7_I0_LUT4_O_I0 I1=L10_LUT4_I3_3_I0_LUT4_O_I1 I2=L10_LUT4_I3_3_I0_LUT4_O_I2 I3=L10_LUT4_I3_3_I0_LUT4_O_I3 O=L10_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 I1=L10_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_41_O I3=R10_LUT4_I3_40_O O=L10_LUT4_I3_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_40_O_LUT4_I2_1_O O=L10_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_41_O_LUT4_I2_O I1=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I3 I2=L10_LUT4_I3_24_I0_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_40_O_LUT4_I2_2_O O=L10_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_40_O_LUT4_I2_2_O I3=L10_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_39_O I1=R10_LUT4_I3_36_O I2=R10_LUT4_I3_37_O I3=R10_LUT4_I3_38_O O=L10_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_3_I1_LUT4_O_I2 I3=L10_LUT4_I3_3_I1_LUT4_O_I3 O=L10_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_41_O_LUT4_I2_O I1=L10_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_40_O_LUT4_I2_2_O I3=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_39_O I1=R10_LUT4_I3_37_O I2=R10_LUT4_I3_38_O I3=R10_LUT4_I3_36_O O=L10_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_40_O_LUT4_I2_1_O O=L10_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_40_O_LUT4_I2_O I3=L10_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3 I3=R10_LUT4_I3_40_O_LUT4_I2_1_O O=L10_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_41_O_LUT4_I2_O I1=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I2=L10_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 I3=R10_LUT4_I3_40_O_LUT4_I2_2_O O=L10_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_3_I2_LUT4_O_I2 I3=L10_LUT4_I3_7_I1_LUT4_O_I3 O=L10_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_1_O I1=L10_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_15_I1_LUT4_O_I1 O=L10_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3 I3=R10_LUT4_I3_40_O_LUT4_I2_O O=L10_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L10_LUT4_I3_4_I0 I1=L10_LUT4_I3_4_I1 I2=L10_LUT4_I3_4_I2 I3=L10(22) O=R11_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_4_I1_LUT4_O_I1 I3=L10_LUT4_I3_4_I0 O=L10_LUT4_I3_26_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_O I1=L10_LUT4_I3_4_I0_LUT4_O_I1 I2=L10_LUT4_I3_4_I0_LUT4_O_I2 I3=L10_LUT4_I3_4_I0_LUT4_O_I3 O=L10_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R10_LUT4_I3_43_O I1=R10_LUT4_I3_44_O I2=R10_LUT4_I3_45_O I3=R10_LUT4_I3_42_O O=L10_LUT4_I3_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_1_O I1=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_46_O_LUT4_I2_O I3=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_45_O I1=R10_LUT4_I3_43_O I2=R10_LUT4_I3_44_O I3=R10_LUT4_I3_42_O O=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_44_O I1=R10_LUT4_I3_45_O I2=R10_LUT4_I3_43_O I3=R10_LUT4_I3_42_O O=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_46_O_LUT4_I2_2_O I3=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_43_O I1=R10_LUT4_I3_42_O I2=R10_LUT4_I3_45_O I3=R10_LUT4_I3_44_O O=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_4_I2_LUT4_I2_I1 I3=R10_LUT4_I3_47_O_LUT4_I2_O O=L10_LUT4_I3_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_2_O I1=L10_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_46_O_LUT4_I2_1_O O=L10_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_45_O I1=R10_LUT4_I3_44_O I2=R10_LUT4_I3_42_O I3=R10_LUT4_I3_43_O O=L10_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L10_LUT4_I3_4_I1_LUT4_O_I0 I1=L10_LUT4_I3_4_I1_LUT4_O_I1 I2=L10_LUT4_I1_1_I3_LUT4_O_I3 I3=L10_LUT4_I3_4_I1_LUT4_O_I3 O=L10_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=L10_LUT4_I1_1_I2_LUT4_O_I2 I1=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1 I2=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I2 I3=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3 O=L10_LUT4_I3_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_2_O I1=L10_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I2 I3=R10_LUT4_I3_46_O_LUT4_I2_1_O O=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_46_O_LUT4_I2_O I3=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_4_I0_LUT4_O_I1 I3=R10_LUT4_I3_46_O_LUT4_I2_1_O O=L10_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I2 I3=R10_LUT4_I3_46_O_LUT4_I2_2_O O=L10_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_46_O_LUT4_I2_O I3=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_O I1=L10_LUT4_I3_4_I2_LUT4_I2_I1 I2=L10_LUT4_I3_4_I2 I3=L10_LUT4_I3_4_I2_LUT4_I2_I3 O=L10_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R10_LUT4_I3_45_O I1=R10_LUT4_I3_44_O I2=R10_LUT4_I3_43_O I3=R10_LUT4_I3_42_O O=L10_LUT4_I3_4_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I1 I2=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I2 I3=R10_LUT4_I3_47_O_LUT4_I2_O O=L10_LUT4_I3_4_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_2_O I1=L10_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_46_O_LUT4_I2_1_O I3=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_45_O I1=R10_LUT4_I3_44_O I2=R10_LUT4_I3_43_O I3=R10_LUT4_I3_42_O O=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_44_O I1=R10_LUT4_I3_43_O I2=R10_LUT4_I3_42_O I3=R10_LUT4_I3_45_O O=L10_LUT4_I3_4_I2_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_4_I2_LUT4_O_I2 I3=L10_LUT4_I3_4_I2_LUT4_O_I3 O=L10_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_46_O_LUT4_I2_2_O I1=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_46_O_LUT4_I2_O O=L10_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_45_O I1=R10_LUT4_I3_42_O I2=R10_LUT4_I3_43_O I3=R10_LUT4_I3_44_O O=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_44_O I1=R10_LUT4_I3_43_O I2=R10_LUT4_I3_45_O I3=R10_LUT4_I3_42_O O=L10_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_47_O_LUT4_I2_O I1=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_46_O_LUT4_I2_1_O I3=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_42_O I1=R10_LUT4_I3_44_O I2=R10_LUT4_I3_43_O I3=R10_LUT4_I3_45_O O=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_45_O I1=R10_LUT4_I3_44_O I2=R10_LUT4_I3_43_O I3=R10_LUT4_I3_42_O O=L10_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L10_LUT4_I3_5_I0 I1=L10_LUT4_I3_5_I1 I2=L10_LUT4_I3_5_I2 I3=L10(24) O=R11_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L10_LUT4_I3_5_I0_LUT4_O_I0 I1=R10_LUT4_I3_34_O I2=R10_LUT4_I3_35_O I3=L10_LUT4_I3_5_I0_LUT4_O_I3 O=L10_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_34_O_LUT4_I2_2_O I3=L10_LUT4_I3_5_I0_LUT4_O_I0 O=L10_LUT4_I3_5_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_34_O_LUT4_I2_1_O I3=L10_LUT4_I3_5_I0_LUT4_O_I0 O=L10_LUT4_I3_5_I0_LUT4_O_I0_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_35_O_LUT4_I2_O I1=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_25_I1_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_5_I0_LUT4_O_I0_LUT4_I3_O O=L10_LUT4_I3_25_I1_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R10_LUT4_I3_31_O I1=R10_LUT4_I3_30_O I2=R10_LUT4_I3_33_O I3=R10_LUT4_I3_32_O O=L10_LUT4_I3_5_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_1_O I1=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_34_O_LUT4_I2_2_O O=L10_LUT4_I3_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_32_O I1=R10_LUT4_I3_31_O I2=R10_LUT4_I3_30_O I3=R10_LUT4_I3_33_O O=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_33_O I1=R10_LUT4_I3_31_O I2=R10_LUT4_I3_32_O I3=R10_LUT4_I3_30_O O=L10_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_5_I1_LUT4_O_I1 I2=L10_LUT4_I3_5_I1_LUT4_O_I2 I3=L10_LUT4_I3_5_I1_LUT4_O_I3 O=L10_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_5_I2_LUT4_O_I2 I3=R10_LUT4_I3_34_O_LUT4_I2_2_O O=L10_LUT4_I3_5_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_25_I1_LUT4_O_I3_LUT4_O_I0 I3=R10_LUT4_I3_34_O_LUT4_I2_O O=L10_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_1_O I1=L10_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_35_O_LUT4_I2_O I3=L10_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_1_I2_LUT4_O_I3 I3=R10_LUT4_I3_34_O_LUT4_I2_O O=L10_LUT4_I3_5_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L10_LUT4_I3_5_I2_LUT4_I2_I0 I1=L10_LUT4_I3_5_I1_LUT4_O_I3 I2=L10_LUT4_I3_5_I2 I3=L10_LUT4_I3_25_I1_LUT4_O_I1 O=L10_LUT4_I3_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_5_I2_LUT4_O_I1 I2=L10_LUT4_I3_5_I2_LUT4_O_I2 I3=R10_LUT4_I3_34_O_LUT4_I2_1_O O=L10_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_35_O_LUT4_I2_O O=L10_LUT4_I3_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_O I1=L10_LUT4_I3_25_I1_LUT4_O_I2_LUT4_O_I2 I2=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_34_O_LUT4_I2_2_O O=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_32_O I1=R10_LUT4_I3_31_O I2=R10_LUT4_I3_33_O I3=R10_LUT4_I3_30_O O=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_34_O_LUT4_I2_1_O I1=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_34_O_LUT4_I2_2_O I3=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2 O=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_33_O I1=R10_LUT4_I3_30_O I2=R10_LUT4_I3_31_O I3=R10_LUT4_I3_32_O O=L10_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_33_O I1=R10_LUT4_I3_32_O I2=R10_LUT4_I3_31_O I3=R10_LUT4_I3_30_O O=L10_LUT4_I3_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_6_I0 I1=L10_LUT4_I3_6_I1 I2=L10_LUT4_I3_6_I2 I3=L10(27) O=R11_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L10_LUT4_I3_6_I0 I1=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I2=L10_LUT4_I3_6_I1_LUT4_O_I3 I3=L10_LUT4_I3_6_I1_LUT4_O_I1 O=L10_LUT4_I3_6_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_6_I1_LUT4_O_I3 I1=L10_LUT4_I3_6_I0 I2=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L10_LUT4_I3_6_I0_LUT4_I1_I3 O=L10_LUT4_I3_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_6_I0_LUT4_I1_I3_LUT4_O_I2 I3=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O O=L10_LUT4_I3_6_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_6_I0_LUT4_O_I2 I3=L10_LUT4_I3_6_I0_LUT4_O_I3 O=L10_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_16_O_LUT4_I2_O I3=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 O=L10_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_13_O I1=R10_LUT4_I3_14_O I2=R10_LUT4_I3_15_O I3=R10_LUT4_I3_12_O O=L10_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_17_O_LUT4_I2_O I1=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0 O=L10_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0 I2=R10_LUT4_I3_16_O_LUT4_I2_O I3=L10_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_17_O_LUT4_I2_O I1=L10_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_6_I1_LUT4_O_I0 I1=L10_LUT4_I3_6_I1_LUT4_O_I1 I2=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L10_LUT4_I3_6_I1_LUT4_O_I3 O=L10_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2 I3=L10_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3 O=L10_LUT4_I3_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_16_O_LUT4_I2_O O=L10_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_17_O_LUT4_I2_O I1=L10_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 O=L10_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0 I1=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_16_O_LUT4_I2_O I3=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R10_LUT4_I3_12_O I1=R10_LUT4_I3_14_O I2=R10_LUT4_I3_13_O I3=R10_LUT4_I3_15_O O=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_14_O I1=R10_LUT4_I3_13_O I2=R10_LUT4_I3_15_O I3=R10_LUT4_I3_12_O O=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L10_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1 I1=R10_LUT4_I3_16_O_LUT4_I2_2_O I2=R10_LUT4_I3_17_O_LUT4_I2_O I3=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 O=L10_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I1=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_16_O_LUT4_I2_2_O I3=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R10_LUT4_I3_13_O I1=R10_LUT4_I3_12_O I2=R10_LUT4_I3_15_O I3=R10_LUT4_I3_14_O O=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_14_O I1=R10_LUT4_I3_13_O I2=R10_LUT4_I3_12_O I3=R10_LUT4_I3_15_O O=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L10_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=R10_LUT4_I3_16_O_LUT4_I2_O I2=R10_LUT4_I3_16_O_LUT4_I2_1_O I3=L10_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L10_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_6_I2_LUT4_O_I0 I1=L10_LUT4_I3_6_I2_LUT4_O_I1 I2=L10_LUT4_I3_6_I2_LUT4_O_I2 I3=L10_LUT4_I3_6_I2_LUT4_O_I3 O=L10_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_13_I2_LUT4_O_I3 I1=R10_LUT4_I3_16_O_LUT4_I2_O I2=L10_LUT4_I3_13_I1_LUT4_O_I0 I3=L10_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3 O=L10_LUT4_I3_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_16_O_LUT4_I2_1_O O=L10_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I2=L10_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_16_O_LUT4_I2_O O=L10_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_14_O I1=R10_LUT4_I3_15_O I2=R10_LUT4_I3_13_O I3=R10_LUT4_I3_12_O O=L10_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L10_LUT4_I3_13_I2_LUT4_O_I3_LUT4_I1_I3 I1=R10_LUT4_I3_16_O_LUT4_I2_2_O I2=R10_LUT4_I3_17_O_LUT4_I2_O I3=L10_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_6_I2_LUT4_O_I2 I1=L10_LUT4_I3_6_I2_LUT4_O_I3 I2=L10_LUT4_I3_23_I2_LUT4_O_I2 I3=L10_LUT4_I3_23_I2_LUT4_O_I1 O=L10_LUT4_I3_13_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_O I1=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_16_O_LUT4_I2_2_O O=L10_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_15_O I1=R10_LUT4_I3_14_O I2=R10_LUT4_I3_13_O I3=R10_LUT4_I3_12_O O=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_15_O I1=R10_LUT4_I3_14_O I2=R10_LUT4_I3_12_O I3=R10_LUT4_I3_13_O O=L10_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_16_O_LUT4_I2_1_O I1=L10_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_17_O_LUT4_I2_O I3=L10_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_15_O I1=R10_LUT4_I3_13_O I2=R10_LUT4_I3_12_O I3=R10_LUT4_I3_14_O O=L10_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_15_O I1=R10_LUT4_I3_14_O I2=R10_LUT4_I3_13_O I3=R10_LUT4_I3_12_O O=L10_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L10_LUT4_I3_7_I0 I1=L10_LUT4_I3_7_I1 I2=L10_LUT4_I3_7_I2 I3=L10(31) O=R11_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L10_LUT4_I3_7_I0_LUT4_O_I0 I1=L10_LUT4_I3_7_I0_LUT4_O_I1 I2=L10_LUT4_I3_7_I0_LUT4_O_I2 I3=L10_LUT4_I3_3_I1_LUT4_O_I3 O=L10_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L10_LUT4_I3_3_I1_LUT4_O_I3 I1=L10_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1 I2=L10_LUT4_I3_3_I1_LUT4_O_I2 I3=L10_LUT4_I3_24_I2_LUT4_O_I2 O=L10_LUT4_I3_7_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_41_O_LUT4_I2_O I3=L10_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=L10_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_40_O_LUT4_I2_2_O O=L10_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_39_O I1=R10_LUT4_I3_38_O I2=R10_LUT4_I3_37_O I3=R10_LUT4_I3_36_O O=L10_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2 I1=L10_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_40_O I3=R10_LUT4_I3_41_O O=L10_LUT4_I3_7_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R10_LUT4_I3_39_O I1=R10_LUT4_I3_38_O I2=R10_LUT4_I3_36_O I3=R10_LUT4_I3_37_O O=L10_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_40_O_LUT4_I2_1_O O=L10_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_38_O I1=R10_LUT4_I3_39_O I2=R10_LUT4_I3_37_O I3=R10_LUT4_I3_36_O O=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_39_O I1=R10_LUT4_I3_37_O I2=R10_LUT4_I3_36_O I3=R10_LUT4_I3_38_O O=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_7_I1_LUT4_O_I1 I2=L10_LUT4_I3_7_I1_LUT4_O_I2 I3=L10_LUT4_I3_7_I1_LUT4_O_I3 O=L10_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_40_O_LUT4_I2_2_O O=L10_LUT4_I3_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_41_O_LUT4_I2_O I1=L10_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_40_O_LUT4_I2_2_O O=L10_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_39_O I1=R10_LUT4_I3_38_O I2=R10_LUT4_I3_37_O I3=R10_LUT4_I3_36_O O=L10_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_1_O I1=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_41_O_LUT4_I2_O O=L10_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_38_O I1=R10_LUT4_I3_36_O I2=R10_LUT4_I3_37_O I3=R10_LUT4_I3_39_O O=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_38_O I1=R10_LUT4_I3_37_O I2=R10_LUT4_I3_39_O I3=R10_LUT4_I3_36_O O=L10_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_2_O I1=L10_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_24_I1_LUT4_O_I1 I3=L10_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R10_LUT4_I3_39_O I1=R10_LUT4_I3_38_O I2=R10_LUT4_I3_37_O I3=R10_LUT4_I3_36_O O=L10_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_40_O_LUT4_I2_1_O I3=L10_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_41_O_LUT4_I2_O I3=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_7_I2 I2=L10_LUT4_I3_3_I2_LUT4_O_I2 I3=L10_LUT4_I3_24_I1_LUT4_O_I3 O=L10_LUT4_I3_24_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_7_I2_LUT4_O_I2 I3=L10_LUT4_I3_7_I2_LUT4_O_I3 O=L10_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_1_O I1=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_41_O_LUT4_I2_O O=L10_LUT4_I3_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_39_O I1=R10_LUT4_I3_38_O I2=R10_LUT4_I3_37_O I3=R10_LUT4_I3_36_O O=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_24_I0_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_40_O_LUT4_I2_1_O I3=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2 O=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_39_O I1=R10_LUT4_I3_38_O I2=R10_LUT4_I3_37_O I3=R10_LUT4_I3_36_O O=L10_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R10_LUT4_I3_40_O_LUT4_I2_O I1=L10_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I2=R10_LUT4_I3_40_O_LUT4_I2_2_O I3=L10_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 O=L10_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_8_I0 I1=L10_LUT4_I3_8_I1 I2=L10_LUT4_I3_8_I2 I3=L10(25) O=R11_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L10_LUT4_I3_8_I0_LUT4_O_I0 I1=L10_LUT4_I3_8_I0_LUT4_O_I1 I2=L10_LUT4_I3_8_I0_LUT4_O_I2 I3=L10_LUT4_I3_8_I0_LUT4_O_I3 O=L10_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I0_LUT4_O_I0_LUT4_O_I1 I2=L10_LUT4_I3_8_I0_LUT4_O_I0_LUT4_O_I2 I3=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2 O=L10_LUT4_I3_8_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_O_LUT4_I3_O I3=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_8_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_2_O I1=L10_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I2 I2=R10_LUT4_I3_O_LUT4_I2_1_O I3=L10_LUT4_I3_8_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_8_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_3_O I1=R10_LUT4_I3_2_O I2=R10_LUT4_I3_5_O I3=R10_LUT4_I3_4_O O=L10_LUT4_I3_8_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_18_I1_LUT4_O_I2 I3=L10_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_8_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I3_O I1=L10_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 I3=R10_LUT4_I3_O_LUT4_I2_2_O O=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_5_O I1=R10_LUT4_I3_3_O I2=R10_LUT4_I3_2_O I3=R10_LUT4_I3_4_O O=L10_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=R10_LUT4_I3_2_O I2=L10_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_O_LUT4_I3_O O=L10_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=R10_LUT4_I3_O_LUT4_I2_1_O I2=R10_LUT4_I3_O_LUT4_I2_2_O I3=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_I1 O=L10_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_1_I1 I3=R10_LUT4_I3_O_LUT4_I3_O O=L10_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_O O=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_O_LUT4_I3_O I3=L10_LUT4_I3_18_I2_LUT4_O_I0 O=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I1 I2=L10_LUT4_I3_8_I1_LUT4_I1_I2 I3=R10_LUT4_I3_O_LUT4_I2_O O=L10_LUT4_I3_8_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_5_O I1=R10_LUT4_I3_4_O I2=R10_LUT4_I3_3_O I3=R10_LUT4_I3_2_O O=L10_LUT4_I3_8_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I1_LUT4_O_I1 I2=L10_LUT4_I3_8_I1_LUT4_O_I2 I3=R10_LUT4_I3_O_LUT4_I3_O O=L10_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_2_O I1=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I2=R10_LUT4_I3_O_LUT4_I2_1_O I3=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_5_O I1=R10_LUT4_I3_4_O I2=R10_LUT4_I3_2_O I3=R10_LUT4_I3_3_O O=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_4_O I1=R10_LUT4_I3_3_O I2=R10_LUT4_I3_2_O I3=R10_LUT4_I3_5_O O=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_I1 I2=L10_LUT4_I3_8_I1_LUT4_O_I2 I3=R10_LUT4_I3_O_LUT4_I2_1_O O=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_1_I1 I2=L10_LUT4_I3_8_I1_LUT4_O_I2 I3=R10_LUT4_I3_O_LUT4_I2_2_O O=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_5_O I1=R10_LUT4_I3_2_O I2=R10_LUT4_I3_3_O I3=R10_LUT4_I3_4_O O=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_1_O I2=L10_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R10_LUT4_I3_O_LUT4_I2_1_O O=L10_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_4_O I1=R10_LUT4_I3_2_O I2=R10_LUT4_I3_3_O I3=R10_LUT4_I3_5_O O=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R10_LUT4_I3_5_O I1=R10_LUT4_I3_4_O I2=R10_LUT4_I3_3_O I3=R10_LUT4_I3_2_O O=L10_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I2_LUT4_O_I1 I2=L10_LUT4_I3_18_I2 I3=L10_LUT4_I3_8_I2_LUT4_O_I3 O=L10_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I3_O I1=L10_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_O_LUT4_I2_2_O O=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_3_O I1=R10_LUT4_I3_4_O I2=R10_LUT4_I3_5_O I3=R10_LUT4_I3_2_O O=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R10_LUT4_I3_O_LUT4_I2_O I1=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_O_LUT4_I2_1_O I3=L10_LUT4_I3_8_I1_LUT4_O_I2_LUT4_I2_1_I1 O=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_5_O I1=R10_LUT4_I3_4_O I2=R10_LUT4_I3_3_O I3=R10_LUT4_I3_2_O O=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_O_LUT4_I2_O I3=L10_LUT4_I3_18_I2_LUT4_O_I0 O=L10_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_8_I1_LUT4_I1_I2 I3=R10_LUT4_I3_O_LUT4_I3_O O=L10_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L10_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=R10_LUT4_I3_O_LUT4_I2_2_O I2=R10_LUT4_I3_O_LUT4_I2_1_O I3=L10_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_9_I0 I1=L10_LUT4_I3_I0 I2=L10_LUT4_I3_9_I2 I3=L10(28) O=R11_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_9_I0_LUT4_O_I2 I3=L10_LUT4_I3_17_I1 O=L10_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_I2_LUT4_O_I2 O=L10_LUT4_I3_9_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_23_O_LUT4_I2_O I1=L10_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_22_O_LUT4_I2_1_O I3=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1 I2=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R10_LUT4_I3_23_O_LUT4_I2_O O=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_2_O I1=L10_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I3 I2=R10_LUT4_I3_22_O_LUT4_I2_1_O I3=L10_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=L10_LUT4_I3_17_I1_LUT4_O_I0 I3=R10_LUT4_I3_22_O_LUT4_I2_O O=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_21_O I1=R10_LUT4_I3_20_O I2=R10_LUT4_I3_19_O I3=R10_LUT4_I3_18_O O=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I2=L10_LUT4_I3_20_I2_LUT4_I3_I1_LUT4_O_I3 I3=R10_LUT4_I3_22_O_LUT4_I2_2_O O=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_9_I2_LUT4_O_I1 I2=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O I3=L10_LUT4_I3_I0_LUT4_O_I2 O=L10_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_22_O_LUT4_I2_O O=L10_LUT4_I3_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_22_O_LUT4_I2_1_O O=L10_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_23_O_LUT4_I2_O I1=L10_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_22_O_LUT4_I2_2_O O=L10_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_19_O I1=R10_LUT4_I3_20_O I2=R10_LUT4_I3_21_O I3=R10_LUT4_I3_18_O O=L10_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I1=L10_LUT4_I3_I0_LUT4_O_I1 I2=L10_LUT4_I3_I0_LUT4_O_I2 I3=L10_LUT4_I3_I0_LUT4_O_I3 O=L10_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_9_I2_LUT4_O_I1 O=L10_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=L10_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_23_O_LUT4_I2_O I1=L10_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_22_O_LUT4_I2_1_O I3=L10_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 O=L10_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R10_LUT4_I3_22_O_LUT4_I2_2_O I3=L10_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L10_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=L10_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L10_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I3 I3=R10_LUT4_I3_23_O_LUT4_I2_O O=L10_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_2_O I1=L10_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=L10_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_22_O_LUT4_I2_1_O O=L10_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O I1=L10_LUT4_I3_I1_LUT4_O_I1 I2=L10_LUT4_I3_I0_LUT4_O_I1 I3=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=L10_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L10_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=L10_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R10_LUT4_I3_22_O_LUT4_I2_1_O I3=L10_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3 O=L10_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_20_O I1=R10_LUT4_I3_19_O I2=R10_LUT4_I3_18_O I3=R10_LUT4_I3_21_O O=L10_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_23_O_LUT4_I2_O I1=L10_LUT4_I3_20_I2_LUT4_I3_I2_LUT4_O_I3 I2=L10_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_22_O_LUT4_I2_2_O O=L10_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L10_LUT4_I3_I2_LUT4_O_I0 I1=L10_LUT4_I3_I2_LUT4_O_I1 I2=L10_LUT4_I3_I2_LUT4_O_I2 I3=L10_LUT4_I3_I2_LUT4_O_I3 O=L10_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L10_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I1=L10_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=R10_LUT4_I3_22_O I3=R10_LUT4_I3_23_O O=L10_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R10_LUT4_I3_21_O I1=R10_LUT4_I3_19_O I2=R10_LUT4_I3_20_O I3=R10_LUT4_I3_18_O O=L10_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L10_LUT4_I3_17_I1_LUT4_O_I0 I1=R10_LUT4_I3_22_O_LUT4_I2_1_O I2=L10_LUT4_I3_20_I0_LUT4_O_I3 I3=L10_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3 O=L10_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_23_O_LUT4_I2_O O=L10_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=L10_LUT4_I3_20_I2_LUT4_I3_I2_LUT4_O_I3 I3=R10_LUT4_I3_22_O_LUT4_I2_2_O O=L10_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_18_O I1=R10_LUT4_I3_20_O I2=R10_LUT4_I3_19_O I3=R10_LUT4_I3_21_O O=L10_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I2=L10_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=R10_LUT4_I3_22_O_LUT4_I2_2_O O=L10_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L10_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3 I3=R10_LUT4_I3_22_O_LUT4_I2_O O=L10_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R10_LUT4_I3_23_O_LUT4_I2_O I1=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=R10_LUT4_I3_22_O_LUT4_I2_1_O I3=L10_LUT4_I3_20_I2_LUT4_I3_I1_LUT4_O_I3 O=L10_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_21_O I1=R10_LUT4_I3_20_O I2=R10_LUT4_I3_19_O I3=R10_LUT4_I3_18_O O=L10_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R10_LUT4_I3_22_O_LUT4_I2_2_O O=L10_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_21_O I1=R10_LUT4_I3_19_O I2=R10_LUT4_I3_18_O I3=R10_LUT4_I3_20_O O=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R10_LUT4_I3_23_O_LUT4_I2_O I1=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I2=L10_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1 I3=R10_LUT4_I3_22_O_LUT4_I2_1_O O=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1 I2=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=L10_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R10_LUT4_I3_22_O_LUT4_I2_O I1=L10_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I2=L10_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R10_LUT4_I3_22_O_LUT4_I2_2_O O=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R10_LUT4_I3_21_O I1=R10_LUT4_I3_20_O I2=R10_LUT4_I3_19_O I3=R10_LUT4_I3_18_O O=L10_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=L10(1) D=R9(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(2) D=R9(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(11) D=R9(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(12) D=R9(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(13) D=R9(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(14) D=R9(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(15) D=R9(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(16) D=R9(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(17) D=R9(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(18) D=R9(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(19) D=R9(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(20) D=R9(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(3) D=R9(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(21) D=R9(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(22) D=R9(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(23) D=R9(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(24) D=R9(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(25) D=R9(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(26) D=R9(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(27) D=R9(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(28) D=R9(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(29) D=R9(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(30) D=R9(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(4) D=R9(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(31) D=R9(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(32) D=R9(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(5) D=R9(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(6) D=R9(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(7) D=R9(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(8) D=R9(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(9) D=R9(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L10(10) D=R9(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:173.1-174.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L11(10) I2=L11_LUT4_I1_I2 I3=L11_LUT4_I1_I3 O=R12_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L11(1) I2=L11_LUT4_I1_1_I2 I3=L11_LUT4_I1_1_I3 O=R12_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O I2=L11_LUT4_I1_1_I2_LUT4_O_I2 I3=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O O=L11_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_22_I2_LUT4_O_I2 I3=R11_LUT4_I3_11_O_LUT4_I2_O O=L11_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_10_O_LUT4_I2_1_O O=L11_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_10_O_LUT4_I2_2_O I3=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 O=L11_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_8_O I1=R11_LUT4_I3_9_O I2=R11_LUT4_I3_7_O I3=R11_LUT4_I3_6_O O=L11_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L11_LUT4_I1_1_I3_LUT4_O_I0 I1=L11_LUT4_I1_1_I3_LUT4_O_I1 I2=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O I3=L11_LUT4_I3_22_I1 O=L11_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L11_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I3 O=L11_LUT4_I1_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R11_LUT4_I3_10_O_LUT4_I2_1_O I3=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 O=L11_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_2_O I1=L11_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_11_O_LUT4_I2_O I3=L11_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_8_O I1=R11_LUT4_I3_6_O I2=R11_LUT4_I3_7_O I3=R11_LUT4_I3_9_O O=L11_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_1_O I1=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R11_LUT4_I3_11_O_LUT4_I2_O I3=L11_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 O=L11_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I3=R11_LUT4_I3_10_O_LUT4_I2_2_O O=L11_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_7_O I1=R11_LUT4_I3_6_O I2=R11_LUT4_I3_9_O I3=R11_LUT4_I3_8_O O=L11_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L11(24) I2=L11_LUT4_I1_2_I2 I3=L11_LUT4_I1_2_I3 O=R12_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=L11_LUT4_I1_2_I2_LUT4_O_I0 I1=L11_LUT4_I1_2_I2_LUT4_O_I1 I2=L11_LUT4_I1_2_I2_LUT4_O_I2 I3=L11_LUT4_I3_15_I2 O=L11_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I1 I2=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2 I3=L11_LUT4_I3_1_I0_LUT4_I3_O O=L11_LUT4_I1_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_35_O_LUT4_I2_O I1=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_34_O_LUT4_I2_O I3=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_32_O I1=R11_LUT4_I3_33_O I2=R11_LUT4_I3_31_O I3=R11_LUT4_I3_30_O O=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_32_O I1=R11_LUT4_I3_31_O I2=R11_LUT4_I3_30_O I3=R11_LUT4_I3_33_O O=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_34_O_LUT4_I2_O O=L11_LUT4_I1_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_34_O_LUT4_I2_1_O O=L11_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_33_O I1=R11_LUT4_I3_32_O I2=R11_LUT4_I3_31_O I3=R11_LUT4_I3_30_O O=L11_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R11_LUT4_I3_35_O_LUT4_I2_O I1=R11_LUT4_I3_34_O_LUT4_I2_2_O I2=L11_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I2=R11_LUT4_I3_35_O_LUT4_I2_O I3=L11_LUT4_I3_1_I0_LUT4_I3_I2_LUT4_O_I1 O=L11_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_33_O I1=R11_LUT4_I3_32_O I2=R11_LUT4_I3_31_O I3=R11_LUT4_I3_30_O O=L11_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_35_O_LUT4_I2_O I3=L11_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_2_I3_LUT4_O_I1 I2=L11_LUT4_I1_2_I3_LUT4_O_I2 I3=L11_LUT4_I1_2_I3_LUT4_O_I3 O=L11_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I1_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L11_LUT4_I3_1_I0_LUT4_I3_I2_LUT4_O_I1 I1=R11_LUT4_I3_34_O_LUT4_I2_1_O I2=R11_LUT4_I3_34_O_LUT4_I2_O I3=L11_LUT4_I3_1_I2_LUT4_O_I2 O=L11_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_35_O_LUT4_I2_O I3=L11_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2 O=L11_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_34_O_LUT4_I2_1_O O=L11_LUT4_I1_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_34_O_LUT4_I2_2_O O=L11_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L11_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1 I1=R11_LUT4_I3_34_O_LUT4_I2_O I2=L11_LUT4_I1_2_I3_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I1_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L11_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 I1=L11_LUT4_I3_1_I0_LUT4_I3_I2_LUT4_O_I3 I2=R11_LUT4_I3_35_O I3=R11_LUT4_I3_34_O O=L11_LUT4_I1_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001100110101
+.subckt LUT4 I0=K1(1) I1=L11(31) I2=L11_LUT4_I1_3_I2 I3=L11_LUT4_I1_3_I3 O=R12_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=L11_LUT4_I1_3_I2_LUT4_O_I0 I1=L11_LUT4_I1_3_I2_LUT4_O_I1 I2=L11_LUT4_I1_3_I2_LUT4_O_I2 I3=L11_LUT4_I1_3_I2_LUT4_O_I3 O=L11_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L11_LUT4_I1_3_I2_LUT4_O_I3 I1=L11_LUT4_I1_3_I2_LUT4_O_I2 I2=L11_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2 I3=L11_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I3 O=L11_LUT4_I1_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_1_O I1=L11_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R11_LUT4_I3_40_O_LUT4_I2_2_O O=L11_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_39_O I1=R11_LUT4_I3_38_O I2=R11_LUT4_I3_36_O I3=R11_LUT4_I3_37_O O=L11_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_41_O_LUT4_I2_O I3=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=L11_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I1_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=R11_LUT4_I3_40_O_LUT4_I2_2_O I2=R11_LUT4_I3_40_O_LUT4_I2_1_O I3=L11_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 O=L11_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2 O=L11_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_1_O I1=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R11_LUT4_I3_41_O_LUT4_I2_O O=L11_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R11_LUT4_I3_40_O_LUT4_I2_2_O O=L11_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_2_O I1=L11_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 I2=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_11_I1_LUT4_O_I1 O=L11_LUT4_I1_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R11_LUT4_I3_40_O_LUT4_I2_1_O O=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_41_O_LUT4_I2_O I3=L11_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_39_O I1=R11_LUT4_I3_37_O I2=R11_LUT4_I3_38_O I3=R11_LUT4_I3_36_O O=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_39_O I1=R11_LUT4_I3_38_O I2=R11_LUT4_I3_37_O I3=R11_LUT4_I3_36_O O=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_40_O_LUT4_I2_O O=L11_LUT4_I1_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_40_O_LUT4_I2_1_O I3=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=R11_LUT4_I3_40_O_LUT4_I2_2_O I2=R11_LUT4_I3_41_O_LUT4_I2_O I3=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_39_O I1=R11_LUT4_I3_38_O I2=R11_LUT4_I3_37_O I3=R11_LUT4_I3_36_O O=L11_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I3_LUT4_O_I1 I2=L11_LUT4_I1_3_I3_LUT4_O_I2 I3=L11_LUT4_I1_3_I3_LUT4_O_I3 O=L11_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R11_LUT4_I3_40_O_LUT4_I2_O O=L11_LUT4_I1_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R11_LUT4_I3_40_O_LUT4_I2_1_O O=L11_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_41_O_LUT4_I2_O I1=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R11_LUT4_I3_40_O_LUT4_I2_2_O O=L11_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I1_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_40_O_LUT4_I2_2_O I3=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_38_O I1=R11_LUT4_I3_39_O I2=R11_LUT4_I3_37_O I3=R11_LUT4_I3_36_O O=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_39_O I1=R11_LUT4_I3_37_O I2=R11_LUT4_I3_36_O I3=R11_LUT4_I3_38_O O=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_1_O I1=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_41_O_LUT4_I2_O I3=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_39_O I1=R11_LUT4_I3_38_O I2=R11_LUT4_I3_37_O I3=R11_LUT4_I3_36_O O=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R11_LUT4_I3_39_O I1=R11_LUT4_I3_38_O I2=R11_LUT4_I3_37_O I3=R11_LUT4_I3_36_O O=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L11_LUT4_I1_3_I3_LUT4_O_I1 I1=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_20_I2_LUT4_O_I2 I3=L11_LUT4_I3_20_I2_LUT4_O_I1 O=L11_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_41_O_LUT4_I2_O I3=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_40_O_LUT4_I2_2_O O=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I3 I2=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_40_O_LUT4_I2_1_O O=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_39_O I1=R11_LUT4_I3_38_O I2=R11_LUT4_I3_37_O I3=R11_LUT4_I3_36_O O=L11_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O I1=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L11_LUT4_I1_I2_LUT4_O_I2 I3=L11_LUT4_I1_I2_LUT4_O_I3 O=L11_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O I1=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L11_LUT4_I1_I2_LUT4_O_I2 I3=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3 O=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 I2=R11_LUT4_I3_10_O_LUT4_I2_2_O I3=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_11_O_LUT4_I2_O I3=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 O=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_22_I2_LUT4_O_I2 I3=R11_LUT4_I3_10_O_LUT4_I2_O O=L11_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_10_O_LUT4_I2_1_O O=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_2_O I1=L11_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R11_LUT4_I3_11_O_LUT4_I2_O I3=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_8_O I1=R11_LUT4_I3_7_O I2=R11_LUT4_I3_6_O I3=R11_LUT4_I3_9_O O=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_10_O_LUT4_I2_2_O O=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_7_O I1=R11_LUT4_I3_8_O I2=R11_LUT4_I3_9_O I3=R11_LUT4_I3_6_O O=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_1_O I1=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_11_O_LUT4_I2_O I3=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_9_O I1=R11_LUT4_I3_6_O I2=R11_LUT4_I3_7_O I3=R11_LUT4_I3_8_O O=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L11_LUT4_I1_I3_LUT4_O_I1 I2=L11_LUT4_I1_I3_LUT4_O_I2 I3=L11_LUT4_I1_I3_LUT4_O_I3 O=L11_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I1=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_11_O I3=R11_LUT4_I3_10_O O=L11_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R11_LUT4_I3_9_O I1=R11_LUT4_I3_8_O I2=R11_LUT4_I3_7_O I3=R11_LUT4_I3_6_O O=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_9_O I1=R11_LUT4_I3_8_O I2=R11_LUT4_I3_7_O I3=R11_LUT4_I3_6_O O=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I1_1_I2_LUT4_O_I2 I1=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I1_I2_LUT4_O_I3 O=L11_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_22_I2_LUT4_O_I2 I3=R11_LUT4_I3_10_O_LUT4_I2_2_O O=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_10_O_LUT4_I2_1_O O=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I2=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_11_O_LUT4_I2_O O=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R11_LUT4_I3_10_O_LUT4_I2_1_O I3=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_2_O I1=L11_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I3=R11_LUT4_I3_11_O_LUT4_I2_O O=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O I1=L11_LUT4_I3_22_I1_LUT4_O_I3 I2=L11_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I1_1_I3_LUT4_O_I0 O=L11_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R11_LUT4_I3_11_O_LUT4_I2_O I3=L11_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_9_O I1=R11_LUT4_I3_7_O I2=R11_LUT4_I3_8_O I3=R11_LUT4_I3_6_O O=L11_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11(14) I3=L11_LUT4_I2_I3 O=R12_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11(17) I3=L11_LUT4_I2_1_I3 O=R12_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L11_LUT4_I1_3_I3_LUT4_O_I3 I1=L11_LUT4_I2_1_I3_LUT4_O_I1 I2=L11_LUT4_I2_1_I3_LUT4_O_I2 I3=L11_LUT4_I2_1_I3_LUT4_O_I3 O=L11_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_11_I2_LUT4_O_I2 O=L11_LUT4_I2_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_41_O_LUT4_I2_O I3=L11_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_38_O I1=R11_LUT4_I3_37_O I2=R11_LUT4_I3_39_O I3=R11_LUT4_I3_36_O O=L11_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_1_O I1=L11_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_40_O_LUT4_I2_2_O O=L11_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I1_3_I3_LUT4_O_I2 I2=L11_LUT4_I3_20_I2_LUT4_O_I2 I3=L11_LUT4_I1_3_I3_LUT4_O_I1 O=L11_LUT4_I2_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L11_LUT4_I1_3_I2_LUT4_O_I2 I1=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=L11_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I1 O=L11_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R11_LUT4_I3_41_O_LUT4_I2_O I3=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L11_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11(32) I3=L11_LUT4_I2_2_I3 O=R12_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L11_LUT4_I2_2_I3_LUT4_O_I0 I1=L11_LUT4_I3_12_I1 I2=L11_LUT4_I2_2_I3_LUT4_O_I2 I3=L11_LUT4_I2_2_I3_LUT4_O_I3 O=L11_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_4_I0_LUT4_O_I2 I2=L11_LUT4_I3_2_I0_LUT4_O_I1 I3=L11_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3 O=L11_LUT4_I2_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_47_O_LUT4_I2_O I3=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I0 O=L11_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_46_O_LUT4_I2_O O=L11_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I2=R11_LUT4_I3_46_O_LUT4_I2_1_O I3=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I2_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_O I1=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_47_O_LUT4_I2_O I3=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1 O=L11_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3 I2=L11_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_46_O_LUT4_I2_1_O O=L11_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I2_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I2 I2=L11_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_47_O_LUT4_I2_O O=L11_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_O I1=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_46_O_LUT4_I2_1_O I3=L11_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I2_I3_LUT4_O_I0 I1=L11_LUT4_I3_21_I1 I2=L11_LUT4_I2_I3_LUT4_O_I2 I3=L11_LUT4_I2_I3_LUT4_O_I3 O=L11_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=L11_LUT4_I3_21_I1 I1=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1 I2=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L11_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_4_O_LUT4_I2_O O=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_5_O_LUT4_I2_O O=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_2_O I1=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_4_O_LUT4_I2_1_O I3=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_3_O I1=R11_LUT4_I3_2_O I2=R11_LUT4_I3_1_O I3=R11_LUT4_I3_O O=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I3 I2=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_5_O_LUT4_I2_O O=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_2_O I1=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_4_O_LUT4_I2_1_O I3=L11_LUT4_I3_21_I2_LUT4_I1_I0_LUT4_O_I2 O=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_3_O I1=R11_LUT4_I3_2_O I2=R11_LUT4_I3_1_O I3=R11_LUT4_I3_O O=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0 I1=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_10_I1_LUT4_O_I2 O=L11_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R11_LUT4_I3_5_O_LUT4_I2_O I3=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 O=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I3 I3=R11_LUT4_I3_4_O_LUT4_I2_1_O O=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 I2=R11_LUT4_I3_4_O_LUT4_I2_2_O I3=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 I3=R11_LUT4_I3_5_O_LUT4_I2_O O=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_2_O I1=L11_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_4_O_LUT4_I2_1_O I3=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_5_O_LUT4_I2_O I1=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I1 I2=R11_LUT4_I3_4_O_LUT4_I2_1_O I3=L11_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=R11_LUT4_I3_4_O_LUT4_I2_2_O I3=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 I1=R11_LUT4_I3_4_O_LUT4_I2_2_O I2=L11_LUT4_I3_7_I2_LUT4_O_I1 I3=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R11_LUT4_I3_3_O I1=R11_LUT4_I3_2_O I2=R11_LUT4_I3_1_O I3=R11_LUT4_I3_O O=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_4_O_LUT4_I2_1_O O=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_5_O_LUT4_I2_O O=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_O I1=R11_LUT4_I3_2_O I2=R11_LUT4_I3_1_O I3=R11_LUT4_I3_3_O O=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L11_LUT4_I3_I0 I1=L11_LUT4_I3_I1 I2=L11_LUT4_I3_I2 I3=L11(2) O=R12_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L11_LUT4_I3_1_I0 I1=L11_LUT4_I3_1_I1 I2=L11_LUT4_I3_1_I2 I3=L11(6) O=R12_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L11_LUT4_I3_7_I0 I1=L11_LUT4_I3_10_I1 I2=L11_LUT4_I3_10_I2 I3=L11(8) O=R12_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_10_I1_LUT4_O_I2 I3=L11_LUT4_I3_10_I1_LUT4_O_I3 O=L11_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_10_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_4_O_LUT4_I2_1_O O=L11_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_5_O_LUT4_I2_O I1=L11_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 I3=R11_LUT4_I3_4_O_LUT4_I2_2_O O=L11_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_2_O I1=R11_LUT4_I3_O I2=R11_LUT4_I3_1_O I3=R11_LUT4_I3_3_O O=L11_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2 O=L11_LUT4_I3_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_5_O_LUT4_I2_O I3=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_2_O I1=R11_LUT4_I3_1_O I2=R11_LUT4_I3_O I3=R11_LUT4_I3_3_O O=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_2_O I1=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R11_LUT4_I3_4_O_LUT4_I2_1_O I3=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_1_O I1=R11_LUT4_I3_O I2=R11_LUT4_I3_3_O I3=R11_LUT4_I3_2_O O=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_7_I2_LUT4_O_I1 I2=L11_LUT4_I3_21_I2 I3=L11_LUT4_I3_7_I2_LUT4_O_I2 O=L11_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L11_LUT4_I3_20_I0 I1=L11_LUT4_I3_11_I1 I2=L11_LUT4_I3_11_I2 I3=L11(9) O=R12_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_11_I1_LUT4_O_I1 I2=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=L11_LUT4_I1_3_I2_LUT4_O_I0 O=L11_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_11_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_40_O_LUT4_I2_1_O I3=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_41_O_LUT4_I2_O I1=L11_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_40_O_LUT4_I2_2_O I3=L11_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_20_I2_LUT4_O_I1 I2=L11_LUT4_I3_11_I2_LUT4_O_I2 I3=L11_LUT4_I1_3_I3_LUT4_O_I1 O=L11_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_41_O_LUT4_I2_O I1=L11_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 I2=L11_LUT4_I1_3_I3_LUT4_O_I2 I3=L11_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R11_LUT4_I3_40_O_LUT4_I2_O O=L11_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_1_O I1=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_40_O_LUT4_I2_2_O I3=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_12_I0 I1=L11_LUT4_I3_12_I1 I2=L11_LUT4_I3_12_I2 I3=L11(12) O=R12_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L11_LUT4_I3_12_I0_LUT4_O_I0 I1=L11_LUT4_I3_4_I1 I2=L11_LUT4_I3_12_I0_LUT4_O_I2 I3=L11_LUT4_I3_2_I2 O=L11_LUT4_I3_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3 I2=L11_LUT4_I3_4_I0_LUT4_O_I2 I3=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_12_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_1_O I1=L11_LUT4_I3_2_I2_LUT4_O_I2 I2=L11_LUT4_I3_2_I0_LUT4_O_I2 I3=L11_LUT4_I3_12_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_12_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_12_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_47_O_LUT4_I2_O O=L11_LUT4_I3_12_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I0 I2=R11_LUT4_I3_46_O_LUT4_I2_O I3=L11_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 O=L11_LUT4_I3_12_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_12_I1_LUT4_O_I2 I3=L11_LUT4_I3_4_I1_LUT4_O_I3 O=L11_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I0 I1=R11_LUT4_I3_46_O_LUT4_I2_1_O I2=R11_LUT4_I3_46_O_LUT4_I2_O I3=L11_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_43_O I1=R11_LUT4_I3_42_O I2=R11_LUT4_I3_45_O I3=R11_LUT4_I3_44_O O=L11_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_12_I2_LUT4_O_I1 I2=L11_LUT4_I3_12_I2_LUT4_O_I2 I3=L11_LUT4_I2_2_I3_LUT4_O_I3 O=L11_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_O I1=L11_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_46_O_LUT4_I2_1_O O=L11_LUT4_I3_12_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_43_O I1=R11_LUT4_I3_44_O I2=R11_LUT4_I3_45_O I3=R11_LUT4_I3_42_O O=L11_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_47_O_LUT4_I2_O I3=L11_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_44_O I1=R11_LUT4_I3_42_O I2=R11_LUT4_I3_43_O I3=R11_LUT4_I3_45_O O=L11_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I3_13_I0 I1=L11_LUT4_I3_13_I1 I2=L11_LUT4_I3_13_I2 I3=L11(13) O=R12_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=L11_LUT4_I3_I0_LUT4_O_I2 I1=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I2=L11_LUT4_I3_I0_LUT4_O_I1 I3=L11_LUT4_I3_13_I0_LUT4_O_I3 O=L11_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_I1_LUT4_O_I1 I2=L11_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L11_LUT4_I3_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L11_LUT4_I3_13_I2_LUT4_O_I3 I1=R11_LUT4_I3_22_O_LUT4_I2_2_O I2=L11_LUT4_I3_I2_LUT4_O_I2 I3=L11_LUT4_I3_13_I1_LUT4_O_I3 O=L11_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_22_O_LUT4_I2_1_O O=L11_LUT4_I3_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 O=L11_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_21_O I1=R11_LUT4_I3_18_O I2=R11_LUT4_I3_19_O I3=R11_LUT4_I3_20_O O=L11_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_13_I2_LUT4_O_I1 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_13_I2_LUT4_O_I3 O=L11_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_22_O_LUT4_I2_1_O O=L11_LUT4_I3_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1 I2=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_22_O_LUT4_I2_2_O O=L11_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_21_O I1=R11_LUT4_I3_20_O I2=R11_LUT4_I3_19_O I3=R11_LUT4_I3_18_O O=L11_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_21_O I1=R11_LUT4_I3_20_O I2=R11_LUT4_I3_19_O I3=R11_LUT4_I3_18_O O=L11_LUT4_I3_13_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L11_LUT4_I3_14_I0 I1=L11_LUT4_I3_14_I1 I2=L11_LUT4_I3_14_I2 I3=L11(15) O=R12_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_9_I0_LUT4_O_I3 I3=L11_LUT4_I3_9_I0_LUT4_O_I0 O=L11_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_14_I1_LUT4_O_I2 I3=L11_LUT4_I3_9_I1_LUT4_O_I0 O=L11_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_14_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L11_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 I1=R11_LUT4_I3_16_O_LUT4_I2_2_O I2=R11_LUT4_I3_16_O_LUT4_I2_1_O I3=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R11_LUT4_I3_17_O_LUT4_I2_O I3=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_9_I2_LUT4_O_I2 I1=L11_LUT4_I3_23_I2 I2=L11_LUT4_I3_19_I2_LUT4_O_I2 I3=L11_LUT4_I3_14_I2_LUT4_O_I3 O=L11_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I2 I2=R11_LUT4_I3_16_O_LUT4_I2_1_O I3=L11_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_15_O I1=R11_LUT4_I3_14_O I2=R11_LUT4_I3_13_O I3=R11_LUT4_I3_12_O O=L11_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R11_LUT4_I3_17_O_LUT4_I2_O I1=L11_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_16_O_LUT4_I2_2_O I3=L11_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_15_I0 I1=L11_LUT4_I3_24_I2 I2=L11_LUT4_I3_15_I2 I3=L11(16) O=R12_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L11_LUT4_I1_2_I2_LUT4_O_I1 I1=L11_LUT4_I3_1_I1_LUT4_O_I2 I2=L11_LUT4_I3_1_I2 I3=L11_LUT4_I3_1_I1_LUT4_O_I3 O=L11_LUT4_I3_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_O I1=R11_LUT4_I3_34_O_LUT4_I2_1_O I2=L11_LUT4_I3_15_I2_LUT4_O_I2 I3=L11_LUT4_I3_15_I2_LUT4_O_I3 O=L11_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I3_1_I2_LUT4_O_I2 I2=R11_LUT4_I3_34_O_LUT4_I2_1_O I3=L11_LUT4_I3_15_I2_LUT4_O_I2 O=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_33_O I1=R11_LUT4_I3_32_O I2=R11_LUT4_I3_31_O I3=R11_LUT4_I3_30_O O=L11_LUT4_I3_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_1_O I1=L11_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_34_O_LUT4_I2_O I3=L11_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_15_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_33_O I1=R11_LUT4_I3_31_O I2=R11_LUT4_I3_30_O I3=R11_LUT4_I3_32_O O=L11_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L11_LUT4_I3_16_I0 I1=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I2=L11_LUT4_I3_16_I2 I3=L11(18) O=R12_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_16_I0_LUT4_O_I1 I2=L11_LUT4_I3_13_I1 I3=L11_LUT4_I3_5_I0_LUT4_O_I3 O=L11_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_16_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_2_O I1=L11_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 I2=L11_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_23_O_LUT4_I2_O O=L11_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I2=R11_LUT4_I3_22_O_LUT4_I2_1_O I3=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_16_I2_LUT4_I3_I1 I2=L11_LUT4_I3_16_I2_LUT4_I3_I2 I3=L11_LUT4_I3_16_I2 O=L11_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3 O=L11_LUT4_I3_16_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_21_O I1=R11_LUT4_I3_20_O I2=R11_LUT4_I3_18_O I3=R11_LUT4_I3_19_O O=L11_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_1_O I1=L11_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1 I2=L11_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 I3=R11_LUT4_I3_22_O_LUT4_I2_2_O O=L11_LUT4_I3_16_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_20_O I1=R11_LUT4_I3_18_O I2=R11_LUT4_I3_19_O I3=R11_LUT4_I3_21_O O=L11_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_16_I2_LUT4_O_I1 I2=L11_LUT4_I3_16_I2_LUT4_O_I2 I3=L11_LUT4_I3_I1_LUT4_O_I1 O=L11_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_1_O I1=L11_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_22_O_LUT4_I2_2_O I3=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_16_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_20_O I1=R11_LUT4_I3_19_O I2=R11_LUT4_I3_21_O I3=R11_LUT4_I3_18_O O=L11_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_19_O I1=R11_LUT4_I3_18_O I2=R11_LUT4_I3_21_O I3=R11_LUT4_I3_20_O O=L11_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_20_O I1=R11_LUT4_I3_21_O I2=R11_LUT4_I3_19_O I3=R11_LUT4_I3_18_O O=L11_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L11_LUT4_I3_8_I0 I1=L11_LUT4_I3_17_I1 I2=L11_LUT4_I3_17_I2 I3=L11(19) O=R12_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_6_I2_LUT4_O_I3 I2=L11_LUT4_I3_17_I1_LUT4_O_I2 I3=L11_LUT4_I3_8_I0_LUT4_O_I3 O=L11_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_17_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_1_O I1=L11_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_2_O I3=L11_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_O I1=L11_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=R11_LUT4_I3_29_O_LUT4_I2_O I3=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_17_I2_LUT4_O_I0 I1=L11_LUT4_I3_8_I2_LUT4_O_I0 I2=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I3=L11_LUT4_I3_3_I2_LUT4_O_I3 O=L11_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_2_O I1=L11_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I2=L11_LUT4_I3_8_I2_LUT4_O_I1 I3=L11_LUT4_I3_17_I2_LUT4_O_I0_LUT4_O_I3 O=L11_LUT4_I3_17_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_17_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_28_O_LUT4_I2_O O=L11_LUT4_I3_17_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_1_O I1=L11_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_29_O_LUT4_I2_O I3=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_17_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L11_LUT4_I3_18_I2 I3=L11(20) O=R12_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L11_LUT4_I3_22_I0_LUT4_O_I2 I1=L11_LUT4_I3_22_I2 I2=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O I3=L11_LUT4_I1_1_I3_LUT4_O_I1 O=L11_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_9_I0 I1=L11_LUT4_I3_19_I1 I2=L11_LUT4_I3_19_I2 I3=L11(21) O=R12_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_14_I1_LUT4_O_I2 I3=L11_LUT4_I3_9_I0_LUT4_O_I0 O=L11_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_19_I2_LUT4_O_I2 I3=L11_LUT4_I3_23_I0_LUT4_O_I2 O=L11_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_17_O_LUT4_I2_O I1=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2 I2=L11_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_16_O_LUT4_I2_1_O O=L11_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_16_O_LUT4_I2_2_O I3=L11_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_1_I0_LUT4_I3_I1 I2=L11_LUT4_I3_1_I0_LUT4_I3_I2 I3=L11_LUT4_I3_1_I0 O=L11_LUT4_I3_1_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_35_O_LUT4_I2_O I1=L11_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_34_O_LUT4_I2_O O=L11_LUT4_I3_1_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I3_1_I0_LUT4_I3_I2_LUT4_O_I1 I2=R11_LUT4_I3_34_O_LUT4_I2_1_O I3=L11_LUT4_I3_1_I0_LUT4_I3_I2_LUT4_O_I3 O=L11_LUT4_I3_1_I0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_31_O I1=R11_LUT4_I3_32_O I2=R11_LUT4_I3_33_O I3=R11_LUT4_I3_30_O O=L11_LUT4_I3_1_I0_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_31_O I1=R11_LUT4_I3_30_O I2=R11_LUT4_I3_33_O I3=R11_LUT4_I3_32_O O=L11_LUT4_I3_1_I0_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_1_I0_LUT4_O_I2 I3=L11_LUT4_I3_1_I0_LUT4_O_I3 O=L11_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_35_O_LUT4_I2_O I1=L11_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_34_O_LUT4_I2_O I3=L11_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_32_O I1=R11_LUT4_I3_30_O I2=R11_LUT4_I3_31_O I3=R11_LUT4_I3_33_O O=L11_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_32_O I1=R11_LUT4_I3_31_O I2=R11_LUT4_I3_33_O I3=R11_LUT4_I3_30_O O=L11_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_34_O_LUT4_I2_1_O I3=L11_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_33_O I1=R11_LUT4_I3_32_O I2=R11_LUT4_I3_31_O I3=R11_LUT4_I3_30_O O=L11_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_33_O I1=R11_LUT4_I3_30_O I2=R11_LUT4_I3_31_O I3=R11_LUT4_I3_32_O O=L11_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I3_1_I1_LUT4_O_I0 I1=L11_LUT4_I1_2_I2_LUT4_O_I1 I2=L11_LUT4_I3_1_I1_LUT4_O_I2 I3=L11_LUT4_I3_1_I1_LUT4_O_I3 O=L11_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=L11_LUT4_I1_2_I3_LUT4_O_I2 I1=L11_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1 I2=L11_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I2 I3=L11_LUT4_I1_2_I3_LUT4_O_I3 O=L11_LUT4_I3_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L11_LUT4_I3_1_I0_LUT4_I3_I2_LUT4_O_I3 I1=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2 I3=L11_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 I1=L11_LUT4_I3_1_I2_LUT4_O_I2 I2=R11_LUT4_I3_35_O I3=R11_LUT4_I3_34_O O=L11_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_1_I0_LUT4_I3_O O=L11_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_35_O_LUT4_I2_O I1=L11_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 I2=L11_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_34_O_LUT4_I2_O O=L11_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_34_O_LUT4_I2_1_O I3=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_35_O_LUT4_I2_O I1=R11_LUT4_I3_34_O_LUT4_I2_2_O I2=L11_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1 I3=L11_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_35_O_LUT4_I2_O O=L11_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_33_O I1=R11_LUT4_I3_32_O I2=R11_LUT4_I3_31_O I3=R11_LUT4_I3_30_O O=L11_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_1_I2_LUT4_O_I1 I2=L11_LUT4_I3_1_I2_LUT4_O_I2 I3=R11_LUT4_I3_34_O_LUT4_I2_1_O O=L11_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_34_O_LUT4_I2_2_O O=L11_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_35_O_LUT4_I2_O I1=L11_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I2=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_34_O_LUT4_I2_O O=L11_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_33_O I1=R11_LUT4_I3_31_O I2=R11_LUT4_I3_32_O I3=R11_LUT4_I3_30_O O=L11_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_30_O I1=R11_LUT4_I3_32_O I2=R11_LUT4_I3_31_O I3=R11_LUT4_I3_33_O O=L11_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L11_LUT4_I3_2_I0 I1=L11_LUT4_I3_2_I1 I2=L11_LUT4_I3_2_I2 I3=L11(7) O=R12_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L11_LUT4_I3_20_I0 I1=L11_LUT4_I3_20_I1 I2=L11_LUT4_I3_20_I2 I3=L11(23) O=R12_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L11_LUT4_I1_3_I3_LUT4_O_I3 I1=L11_LUT4_I2_1_I3_LUT4_O_I1 I2=L11_LUT4_I3_20_I0_LUT4_O_I2 I3=L11_LUT4_I3_20_I0_LUT4_O_I3 O=L11_LUT4_I3_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_40_O_LUT4_I2_1_O I3=L11_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_20_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_38_O I1=R11_LUT4_I3_37_O I2=R11_LUT4_I3_36_O I3=R11_LUT4_I3_39_O O=L11_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_37_O I1=R11_LUT4_I3_36_O I2=R11_LUT4_I3_39_O I3=R11_LUT4_I3_38_O O=L11_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_41_O_LUT4_I2_O I1=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_40_O_LUT4_I2_2_O I3=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_20_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_37_O I1=R11_LUT4_I3_38_O I2=R11_LUT4_I3_39_O I3=R11_LUT4_I3_36_O O=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_36_O I1=R11_LUT4_I3_38_O I2=R11_LUT4_I3_37_O I3=R11_LUT4_I3_39_O O=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L11_LUT4_I1_3_I2_LUT4_O_I1 I1=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=L11_LUT4_I1_3_I2_LUT4_O_I0 I3=L11_LUT4_I1_3_I2_LUT4_O_I3 O=L11_LUT4_I3_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_20_I2_LUT4_O_I1 I2=L11_LUT4_I3_20_I2_LUT4_O_I2 I3=L11_LUT4_I2_1_I3_LUT4_O_I1 O=L11_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_20_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3 I2=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I3 I3=R11_LUT4_I3_41_O_LUT4_I2_O O=L11_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_1_O I1=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R11_LUT4_I3_40_O_LUT4_I2_2_O I3=L11_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_1_O I1=L11_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_41_O_LUT4_I2_O I3=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_41_O_LUT4_I2_O I1=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_40_O_LUT4_I2_2_O I3=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I2 I3=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=L11_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_40_O_LUT4_I2_1_O O=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_39_O I1=R11_LUT4_I3_36_O I2=R11_LUT4_I3_37_O I3=R11_LUT4_I3_38_O O=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_40_O_LUT4_I2_O I1=L11_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_40_O_LUT4_I2_2_O I3=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_38_O I1=R11_LUT4_I3_36_O I2=R11_LUT4_I3_37_O I3=R11_LUT4_I3_39_O O=L11_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I3_21_I0 I1=L11_LUT4_I3_21_I1 I2=L11_LUT4_I3_21_I2 I3=L11(25) O=R12_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L11_LUT4_I3_7_I1_LUT4_O_I3 I1=L11_LUT4_I3_21_I0_LUT4_O_I1 I2=L11_LUT4_I2_I3_LUT4_O_I0 I3=L11_LUT4_I3_7_I0_LUT4_O_I2 O=L11_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_10_I1_LUT4_O_I3 I3=L11_LUT4_I3_7_I1_LUT4_O_I2 O=L11_LUT4_I3_21_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_21_I1_LUT4_O_I1 I2=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 I3=R11_LUT4_I3_4_O_LUT4_I2_O O=L11_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_5_O_LUT4_I2_O O=L11_LUT4_I3_21_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_2_O I1=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_4_O_LUT4_I2_1_O I3=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I1 O=L11_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_21_I2_LUT4_I1_I0 I1=L11_LUT4_I3_21_I2 I2=L11_LUT4_I3_7_I2_LUT4_O_I2 I3=L11_LUT4_I3_21_I2_LUT4_I1_I3 O=L11_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R11_LUT4_I3_4_O_LUT4_I2_2_O I2=L11_LUT4_I3_21_I2_LUT4_I1_I0_LUT4_O_I2 I3=L11_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_21_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=R11_LUT4_I3_3_O I1=R11_LUT4_I3_1_O I2=R11_LUT4_I3_2_O I3=R11_LUT4_I3_O O=L11_LUT4_I3_21_I2_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I1 I2=R11_LUT4_I3_5_O_LUT4_I2_O I3=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I3 O=L11_LUT4_I3_21_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_2_O I1=R11_LUT4_I3_1_O I2=R11_LUT4_I3_3_O I3=R11_LUT4_I3_O O=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_2_O I1=R11_LUT4_I3_3_O I2=R11_LUT4_I3_1_O I3=R11_LUT4_I3_O O=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_21_I2_LUT4_O_I2 I3=L11_LUT4_I3_21_I2_LUT4_O_I3 O=L11_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_5_O_LUT4_I2_O I1=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_4_O_LUT4_I2_2_O I3=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_3_O I1=R11_LUT4_I3_2_O I2=R11_LUT4_I3_O I3=R11_LUT4_I3_1_O O=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_1_O I1=R11_LUT4_I3_2_O I2=R11_LUT4_I3_3_O I3=R11_LUT4_I3_O O=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_4_O_LUT4_I2_1_O I3=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_21_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_3_O I1=R11_LUT4_I3_2_O I2=R11_LUT4_I3_1_O I3=R11_LUT4_I3_O O=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_3_O I1=R11_LUT4_I3_O I2=R11_LUT4_I3_1_O I3=R11_LUT4_I3_2_O O=L11_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I3_22_I0 I1=L11_LUT4_I3_22_I1 I2=L11_LUT4_I3_22_I2 I3=L11(26) O=R12_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L11_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L11_LUT4_I1_I3_LUT4_O_I2 I2=L11_LUT4_I3_22_I0_LUT4_O_I2 I3=L11_LUT4_I3_22_I0_LUT4_O_I3 O=L11_LUT4_I3_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I1_1_I2_LUT4_O_I2 O=L11_LUT4_I3_22_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O O=L11_LUT4_I3_22_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L11_LUT4_I3_22_I1_LUT4_O_I0 I1=L11_LUT4_I3_22_I1_LUT4_O_I1 I2=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O I3=L11_LUT4_I3_22_I1_LUT4_O_I3 O=L11_LUT4_I3_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 I1=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I2=R11_LUT4_I3_11_O I3=R11_LUT4_I3_10_O O=L11_LUT4_I3_22_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R11_LUT4_I3_9_O I1=R11_LUT4_I3_8_O I2=R11_LUT4_I3_7_O I3=R11_LUT4_I3_6_O O=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_9_O I1=R11_LUT4_I3_8_O I2=R11_LUT4_I3_6_O I3=R11_LUT4_I3_7_O O=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0 I1=R11_LUT4_I3_11_O_LUT4_I2_O I2=R11_LUT4_I3_10_O_LUT4_I2_1_O I3=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_22_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_10_O_LUT4_I2_2_O I3=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0 O=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_I1 I2=R11_LUT4_I3_10_O_LUT4_I2_1_O I3=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0 O=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_2_O I1=L11_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_11_O_LUT4_I2_O I3=L11_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O I2=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 I3=R11_LUT4_I3_10_O_LUT4_I2_O O=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_9_O I1=R11_LUT4_I3_8_O I2=R11_LUT4_I3_7_O I3=R11_LUT4_I3_6_O O=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_1_O I1=L11_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I2=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 I3=R11_LUT4_I3_11_O_LUT4_I2_O O=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_6_O I1=R11_LUT4_I3_8_O I2=R11_LUT4_I3_7_O I3=R11_LUT4_I3_9_O O=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_22_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_O I1=L11_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 I2=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R11_LUT4_I3_10_O_LUT4_I2_1_O O=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_1_O I1=L11_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_10_O_LUT4_I2_2_O I3=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=L11_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_10_O_LUT4_I2_O O=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I2=R11_LUT4_I3_11_O_LUT4_I2_O I3=L11_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 O=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_8_O I1=R11_LUT4_I3_7_O I2=R11_LUT4_I3_9_O I3=R11_LUT4_I3_6_O O=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_2_O I1=L11_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I2=L11_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_11_O_LUT4_I2_O O=L11_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_22_I2_LUT4_O_I1 I2=L11_LUT4_I3_22_I2_LUT4_O_I2 I3=R11_LUT4_I3_10_O_LUT4_I2_1_O O=L11_LUT4_I3_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_10_O_LUT4_I2_O O=L11_LUT4_I3_22_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_10_O_LUT4_I2_2_O I1=L11_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=L11_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I3=R11_LUT4_I3_11_O_LUT4_I2_O O=L11_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_9_O I1=R11_LUT4_I3_7_O I2=R11_LUT4_I3_6_O I3=R11_LUT4_I3_8_O O=L11_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_9_O I1=R11_LUT4_I3_8_O I2=R11_LUT4_I3_7_O I3=R11_LUT4_I3_6_O O=L11_LUT4_I3_22_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_23_I0 I1=L11_LUT4_I3_23_I1 I2=L11_LUT4_I3_23_I2 I3=L11(27) O=R12_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_23_I0_LUT4_O_I2 I3=L11_LUT4_I3_23_I0_LUT4_O_I3 O=L11_LUT4_I3_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_1_O I1=L11_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3 I2=L11_LUT4_I3_14_I2_LUT4_O_I3 I3=L11_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_23_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2 I3=R11_LUT4_I3_16_O_LUT4_I2_2_O O=L11_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I0 I2=R11_LUT4_I3_17_O_LUT4_I2_O I3=L11_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_23_I0_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 I3=R11_LUT4_I3_16_O_LUT4_I2_O O=L11_LUT4_I3_23_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I0 I3=R11_LUT4_I3_17_O_LUT4_I2_O O=L11_LUT4_I3_23_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_2_O I1=L11_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I2 I2=R11_LUT4_I3_16_O_LUT4_I2_1_O I3=L11_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_9_I0_LUT4_O_I2 I2=L11_LUT4_I3_23_I1_LUT4_O_I2 I3=L11_LUT4_I3_23_I1_LUT4_O_I3 O=L11_LUT4_I3_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_23_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_16_O_LUT4_I2_2_O O=L11_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_17_O_LUT4_I2_O I1=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_16_O_LUT4_I2_1_O O=L11_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_14_I1_LUT4_O_I2 I2=L11_LUT4_I3_23_I1_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_23_I1_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_23_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_16_O_LUT4_I2_1_O O=L11_LUT4_I3_23_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_16_O I3=R11_LUT4_I3_17_O O=L11_LUT4_I3_23_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_23_I2_LUT4_O_I2 I3=L11_LUT4_I3_23_I2_LUT4_O_I3 O=L11_LUT4_I3_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_2_O I1=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2 I3=R11_LUT4_I3_16_O_LUT4_I2_1_O O=L11_LUT4_I3_23_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_15_O I1=R11_LUT4_I3_14_O I2=R11_LUT4_I3_12_O I3=R11_LUT4_I3_13_O O=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_13_O I1=R11_LUT4_I3_12_O I2=R11_LUT4_I3_15_O I3=R11_LUT4_I3_14_O O=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_17_O_LUT4_I2_O O=L11_LUT4_I3_23_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_12_O I1=R11_LUT4_I3_14_O I2=R11_LUT4_I3_13_O I3=R11_LUT4_I3_15_O O=L11_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_14_O I1=R11_LUT4_I3_13_O I2=R11_LUT4_I3_12_O I3=R11_LUT4_I3_15_O O=L11_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L11_LUT4_I3_24_I0 I1=L11_LUT4_I3_24_I1 I2=L11_LUT4_I3_24_I2 I3=L11(30) O=R12_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_24_I0_LUT4_O_I1 I2=L11_LUT4_I3_24_I0_LUT4_O_I2 I3=L11_LUT4_I1_2_I2_LUT4_O_I0 O=L11_LUT4_I3_24_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I3_24_I0_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_34_O_LUT4_I2_1_O O=L11_LUT4_I3_24_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_35_O_LUT4_I2_O I1=L11_LUT4_I3_24_I0_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3 I3=R11_LUT4_I3_34_O_LUT4_I2_O O=L11_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_33_O I1=R11_LUT4_I3_32_O I2=R11_LUT4_I3_30_O I3=R11_LUT4_I3_31_O O=L11_LUT4_I3_24_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L11_LUT4_I3_1_I0_LUT4_I3_I2_LUT4_O_I1 I1=R11_LUT4_I3_34_O_LUT4_I2_O I2=R11_LUT4_I3_35_O_LUT4_I2_O I3=L11_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_24_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_2_I2_LUT4_O_I2 I3=L11_LUT4_I3_1_I1_LUT4_O_I3 O=L11_LUT4_I3_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_2_I3_LUT4_O_I1 I3=L11_LUT4_I3_24_I2_LUT4_O_I3 O=L11_LUT4_I3_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I1 I3=L11_LUT4_I3_24_I2_LUT4_O_I3 O=L11_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_35_O_LUT4_I2_O I1=R11_LUT4_I3_34_O_LUT4_I2_2_O I2=L11_LUT4_I3_24_I0_LUT4_O_I1_LUT4_O_I1 I3=L11_LUT4_I3_24_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_24_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R11_LUT4_I3_34_O_LUT4_I2_2_O I1=L11_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3 I2=R11_LUT4_I3_35_O_LUT4_I2_O I3=L11_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_24_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_2_I0_LUT4_O_I0 I1=L11_LUT4_I3_2_I0_LUT4_O_I1 I2=L11_LUT4_I3_2_I0_LUT4_O_I2 I3=L11_LUT4_I3_2_I0_LUT4_O_I3 O=L11_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I1=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I0 I2=R11_LUT4_I3_46_O I3=R11_LUT4_I3_47_O O=L11_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I0 I2=R11_LUT4_I3_46_O_LUT4_I2_O I3=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I0 O=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_1_O I1=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_47_O_LUT4_I2_O I3=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I1 O=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I0 I1=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_46_O_LUT4_I2_2_O I3=R11_LUT4_I3_46_O_LUT4_I2_O O=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=R11_LUT4_I3_45_O I1=R11_LUT4_I3_44_O I2=R11_LUT4_I3_43_O I3=R11_LUT4_I3_42_O O=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_47_O_LUT4_I2_O I3=L11_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_O I1=L11_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_46_O_LUT4_I2_1_O I3=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1 O=L11_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_46_O_LUT4_I2_1_O O=L11_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_44_O I1=R11_LUT4_I3_45_O I2=R11_LUT4_I3_43_O I3=R11_LUT4_I3_42_O O=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_45_O I1=R11_LUT4_I3_42_O I2=R11_LUT4_I3_43_O I3=R11_LUT4_I3_44_O O=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I3_4_I1_LUT4_O_I1 I1=L11_LUT4_I3_12_I2 I2=L11_LUT4_I3_4_I1_LUT4_O_I3 I3=L11_LUT4_I3_2_I1_LUT4_O_I3 O=L11_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_1_O I1=L11_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 I2=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_47_O_LUT4_I2_O O=L11_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_46_O_LUT4_I2_O O=L11_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_2_I2_LUT4_O_I1 I2=L11_LUT4_I3_2_I2_LUT4_O_I2 I3=R11_LUT4_I3_46_O_LUT4_I2_2_O O=L11_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_46_O_LUT4_I2_O O=L11_LUT4_I3_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_1_O I1=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I1 I2=R11_LUT4_I3_47_O_LUT4_I2_O I3=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 O=L11_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_45_O I1=R11_LUT4_I3_43_O I2=R11_LUT4_I3_42_O I3=R11_LUT4_I3_44_O O=L11_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_45_O I1=R11_LUT4_I3_44_O I2=R11_LUT4_I3_43_O I3=R11_LUT4_I3_42_O O=L11_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_3_I0 I1=L11_LUT4_I3_3_I1 I2=L11_LUT4_I3_3_I2 I3=L11(11) O=R12_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L11_LUT4_I3_3_I0_LUT4_O_I0 I1=L11_LUT4_I3_3_I0_LUT4_O_I1 I2=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I3=L11_LUT4_I3_8_I2_LUT4_O_I1 O=L11_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_3_I1_LUT4_O_I0 I1=L11_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I2=R11_LUT4_I3_28_O I3=R11_LUT4_I3_29_O O=L11_LUT4_I3_3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R11_LUT4_I3_25_O I1=R11_LUT4_I3_24_O I2=R11_LUT4_I3_27_O I3=R11_LUT4_I3_26_O O=L11_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_1_O I1=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_2_O I3=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_27_O I1=R11_LUT4_I3_24_O I2=R11_LUT4_I3_25_O I3=R11_LUT4_I3_26_O O=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_26_O I1=R11_LUT4_I3_25_O I2=R11_LUT4_I3_24_O I3=R11_LUT4_I3_27_O O=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L11_LUT4_I3_3_I1_LUT4_O_I0 I1=R11_LUT4_I3_28_O_LUT4_I2_1_O I2=L11_LUT4_I3_3_I1_LUT4_O_I2 I3=L11_LUT4_I3_3_I1_LUT4_O_I3 O=L11_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R11_LUT4_I3_27_O I1=R11_LUT4_I3_26_O I2=R11_LUT4_I3_25_O I3=R11_LUT4_I3_24_O O=L11_LUT4_I3_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_8_I1_LUT4_O_I2 I3=L11_LUT4_I3_17_I1_LUT4_O_I2 O=L11_LUT4_I3_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3 I3=R11_LUT4_I3_28_O_LUT4_I2_O O=L11_LUT4_I3_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_29_O_LUT4_I2_O I1=L11_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_2_O I3=L11_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_3_I2_LUT4_O_I1 I2=L11_LUT4_I3_3_I2_LUT4_O_I2 I3=L11_LUT4_I3_3_I2_LUT4_O_I3 O=L11_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_O I1=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_29_O_LUT4_I2_O O=L11_LUT4_I3_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_1_O I1=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_29_O_LUT4_I2_O O=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_27_O I1=R11_LUT4_I3_26_O I2=R11_LUT4_I3_24_O I3=R11_LUT4_I3_25_O O=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_27_O I1=R11_LUT4_I3_25_O I2=R11_LUT4_I3_24_O I3=R11_LUT4_I3_26_O O=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_1_O I1=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_2_O I3=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_27_O I1=R11_LUT4_I3_25_O I2=R11_LUT4_I3_26_O I3=R11_LUT4_I3_24_O O=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_27_O I1=R11_LUT4_I3_26_O I2=R11_LUT4_I3_25_O I3=R11_LUT4_I3_24_O O=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_29_O_LUT4_I2_O O=L11_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_28_O_LUT4_I2_O O=L11_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_1_O I1=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_2_O I3=L11_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_27_O I1=R11_LUT4_I3_26_O I2=R11_LUT4_I3_25_O I3=R11_LUT4_I3_24_O O=L11_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L11_LUT4_I3_4_I0 I1=L11_LUT4_I3_4_I1 I2=L11_LUT4_I3_4_I2 I3=L11(22) O=R12_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=L11_LUT4_I3_4_I0_LUT4_O_I0 I1=L11_LUT4_I3_4_I0_LUT4_O_I1 I2=L11_LUT4_I3_4_I0_LUT4_O_I2 I3=L11_LUT4_I3_2_I2 O=L11_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I0 I1=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I1 I2=R11_LUT4_I3_46_O_LUT4_I2_2_O I3=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2 O=L11_LUT4_I3_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R11_LUT4_I3_45_O I1=R11_LUT4_I3_44_O I2=R11_LUT4_I3_43_O I3=R11_LUT4_I3_42_O O=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_45_O I1=R11_LUT4_I3_44_O I2=R11_LUT4_I3_43_O I3=R11_LUT4_I3_42_O O=L11_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I0 I1=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_46_O_LUT4_I2_O I3=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R11_LUT4_I3_45_O I1=R11_LUT4_I3_44_O I2=R11_LUT4_I3_42_O I3=R11_LUT4_I3_43_O O=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_45_O I1=R11_LUT4_I3_43_O I2=R11_LUT4_I3_44_O I3=R11_LUT4_I3_42_O O=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_1_O I1=L11_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_47_O_LUT4_I2_O I3=L11_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I2 O=L11_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_O I1=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_47_O_LUT4_I2_O I3=L11_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_42_O I1=R11_LUT4_I3_44_O I2=R11_LUT4_I3_43_O I3=R11_LUT4_I3_45_O O=L11_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 I2=R11_LUT4_I3_46_O_LUT4_I2_1_O I3=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_4_I1_LUT4_O_I1 I2=L11_LUT4_I3_12_I2 I3=L11_LUT4_I3_4_I1_LUT4_O_I3 O=L11_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_2_I1_LUT4_O_I3 I3=L11_LUT4_I2_2_I3_LUT4_O_I2 O=L11_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R11_LUT4_I3_44_O I1=R11_LUT4_I3_43_O I2=R11_LUT4_I3_45_O I3=R11_LUT4_I3_42_O O=L11_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_1_O I1=L11_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I2 I2=L11_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_47_O_LUT4_I2_O O=L11_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_4_I2_LUT4_O_I2 I3=L11_LUT4_I2_2_I3_LUT4_O_I3 O=L11_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_4_I2_LUT4_O_I2 I2=L11_LUT4_I3_2_I2_LUT4_O_I2 I3=R11_LUT4_I3_46_O_LUT4_I2_O O=L11_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_46_O_LUT4_I2_2_O I1=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_47_O_LUT4_I2_O I3=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_45_O I1=R11_LUT4_I3_44_O I2=R11_LUT4_I3_43_O I3=R11_LUT4_I3_42_O O=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_44_O I1=R11_LUT4_I3_43_O I2=R11_LUT4_I3_42_O I3=R11_LUT4_I3_45_O O=L11_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L11_LUT4_I3_5_I0 I1=L11_LUT4_I3_I0 I2=L11_LUT4_I3_5_I2 I3=L11(28) O=R12_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_13_I2 I2=L11_LUT4_I3_I2_LUT4_O_I2 I3=L11_LUT4_I3_5_I0_LUT4_O_I3 O=L11_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_I2_LUT4_O_I1 O=L11_LUT4_I3_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 I2=L11_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3 I3=R11_LUT4_I3_22_O_LUT4_I2_2_O O=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_1_O I1=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 O=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_2_O I1=L11_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=L11_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R11_LUT4_I3_22_O_LUT4_I2_1_O O=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I2=L11_LUT4_I3_13_I2_LUT4_O_I3 I3=R11_LUT4_I3_22_O_LUT4_I2_O O=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_21_O I1=R11_LUT4_I3_20_O I2=R11_LUT4_I3_19_O I3=R11_LUT4_I3_18_O O=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_5_I2_LUT4_O_I1 I2=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L11_LUT4_I3_I0_LUT4_O_I2 O=L11_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_22_O_LUT4_I2_O O=L11_LUT4_I3_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_22_O_LUT4_I2_1_O O=L11_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L11_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=R11_LUT4_I3_22_O_LUT4_I2_2_O I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_19_O I1=R11_LUT4_I3_20_O I2=R11_LUT4_I3_21_O I3=R11_LUT4_I3_18_O O=L11_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L11_LUT4_I3_6_I0 I1=L11_LUT4_I3_8_I0 I2=L11_LUT4_I3_6_I2 I3=L11(29) O=R12_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_6_I0_LUT4_O_I1 I2=L11_LUT4_I3_6_I0_LUT4_O_I2 I3=L11_LUT4_I3_3_I2 O=L11_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_29_O_LUT4_I2_O I1=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I1 I3=R11_LUT4_I3_28_O_LUT4_I2_2_O O=L11_LUT4_I3_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I3=R11_LUT4_I3_28_O_LUT4_I2_2_O O=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=L11_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_28_O_LUT4_I2_O O=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_27_O I1=R11_LUT4_I3_26_O I2=R11_LUT4_I3_25_O I3=R11_LUT4_I3_24_O O=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I3=L11_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I2=R11_LUT4_I3_28_O_LUT4_I2_1_O I3=R11_LUT4_I3_28_O_LUT4_I2_O O=L11_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_3_I1_LUT4_O_I2 I3=L11_LUT4_I3_6_I2_LUT4_O_I3 O=L11_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_3_I1_LUT4_O_I0 I3=R11_LUT4_I3_28_O_LUT4_I2_O O=L11_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_1_O I3=L11_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_29_O_LUT4_I2_O I1=L11_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_2_O I3=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_26_O I1=R11_LUT4_I3_25_O I2=R11_LUT4_I3_27_O I3=R11_LUT4_I3_24_O O=L11_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I3_7_I0 I1=L11_LUT4_I3_7_I1 I2=L11_LUT4_I3_7_I2 I3=L11(3) O=R12_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_I3_LUT4_O_I3 I2=L11_LUT4_I3_7_I0_LUT4_O_I2 I3=L11_LUT4_I2_I3_LUT4_O_I0 O=L11_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_7_I1_LUT4_O_I2 I3=L11_LUT4_I3_7_I1_LUT4_O_I3 O=L11_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2 O=L11_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_5_O_LUT4_I2_O I3=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=L11_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_3_O I1=R11_LUT4_I3_1_O I2=R11_LUT4_I3_O I3=R11_LUT4_I3_2_O O=L11_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_2_O I1=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I3 I2=R11_LUT4_I3_4_O_LUT4_I2_1_O I3=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L11_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0 O=L11_LUT4_I3_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_5_O_LUT4_I2_O I1=L11_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R11_LUT4_I3_4_O_LUT4_I2_2_O O=L11_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_4_O_LUT4_I2_1_O O=L11_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_7_I2_LUT4_O_I1 I2=L11_LUT4_I3_7_I2_LUT4_O_I2 I3=L11_LUT4_I3_7_I2_LUT4_O_I3 O=L11_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_5_O_LUT4_I2_O I1=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_21_I2_LUT4_I1_I3_LUT4_O_I1 I3=R11_LUT4_I3_4_O_LUT4_I2_2_O O=L11_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_21_I2_LUT4_I1_I0_LUT4_O_I2 I2=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_4_O_LUT4_I2_1_O O=L11_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_4_O_LUT4_I2_2_O I3=L11_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_4_O_LUT4_I2_1_O I3=L11_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 O=L11_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_4_O_LUT4_I2_O I1=L11_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 I2=R11_LUT4_I3_5_O_LUT4_I2_O I3=L11_LUT4_I3_21_I2_LUT4_I1_I0_LUT4_O_I2 O=L11_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_3_O I1=R11_LUT4_I3_2_O I2=R11_LUT4_I3_1_O I3=R11_LUT4_I3_O O=L11_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 I2=L11_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L11_LUT4_I3_21_I1 O=L11_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L11_LUT4_I3_8_I0 I1=L11_LUT4_I3_8_I1 I2=L11_LUT4_I3_8_I2 I3=L11(4) O=R12_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_8_I0_LUT4_O_I1 I2=L11_LUT4_I3_3_I1 I3=L11_LUT4_I3_8_I0_LUT4_O_I3 O=L11_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_8_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_O I1=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_1_O I3=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_26_O I1=R11_LUT4_I3_24_O I2=R11_LUT4_I3_25_O I3=R11_LUT4_I3_27_O O=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_27_O I1=R11_LUT4_I3_26_O I2=R11_LUT4_I3_25_O I3=R11_LUT4_I3_24_O O=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L11_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=R11_LUT4_I3_28_O_LUT4_I2_2_O I2=R11_LUT4_I3_29_O_LUT4_I2_O I3=L11_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 O=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_6_I2_LUT4_O_I3 I1=L11_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_8_I1_LUT4_O_I1 O=L11_LUT4_I3_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I1=L11_LUT4_I3_3_I1_LUT4_O_I0 I2=R11_LUT4_I3_29_O I3=R11_LUT4_I3_28_O O=L11_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_O I1=L11_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_29_O_LUT4_I2_O O=L11_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_24_O I1=R11_LUT4_I3_26_O I2=R11_LUT4_I3_25_O I3=R11_LUT4_I3_27_O O=L11_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_8_I1_LUT4_O_I1 I2=L11_LUT4_I3_8_I1_LUT4_O_I2 I3=L11_LUT4_I3_8_I0_LUT4_O_I1 O=L11_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_1_O I1=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3 I2=L11_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I3=R11_LUT4_I3_28_O_LUT4_I2_2_O O=L11_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_O I1=L11_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_29_O_LUT4_I2_O I3=L11_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_25_O I1=R11_LUT4_I3_26_O I2=R11_LUT4_I3_27_O I3=R11_LUT4_I3_24_O O=L11_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_O I1=L11_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_2_O I3=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 O=L11_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_26_O I1=R11_LUT4_I3_27_O I2=R11_LUT4_I3_25_O I3=R11_LUT4_I3_24_O O=L11_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_1_O I1=L11_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_29_O_LUT4_I2_O I3=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_8_I2_LUT4_O_I0 I1=L11_LUT4_I3_8_I2_LUT4_O_I1 I2=L11_LUT4_I3_8_I2_LUT4_O_I2 I3=L11_LUT4_I3_8_I2_LUT4_O_I3 O=L11_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=L11_LUT4_I3_6_I0_LUT4_O_I1 I3=L11_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_8_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_O I1=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_28_O_LUT4_I2_1_O I3=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_29_O_LUT4_I2_O I1=L11_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_28_O_LUT4_I2_2_O O=L11_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_29_O_LUT4_I2_O I1=L11_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_28_O_LUT4_I2_2_O O=L11_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_28_O_LUT4_I2_O I1=L11_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3 I2=L11_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I3=R11_LUT4_I3_28_O_LUT4_I2_1_O O=L11_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_9_I0 I1=L11_LUT4_I3_9_I1 I2=L11_LUT4_I3_9_I2 I3=L11(5) O=R12_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L11_LUT4_I3_9_I0_LUT4_O_I0 I1=L11_LUT4_I3_9_I0_LUT4_O_I1 I2=L11_LUT4_I3_9_I0_LUT4_O_I2 I3=L11_LUT4_I3_9_I0_LUT4_O_I3 O=L11_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_23_I1_LUT4_O_I2 I2=L11_LUT4_I3_9_I1_LUT4_O_I1 I3=L11_LUT4_I3_23_I1_LUT4_O_I3 O=L11_LUT4_I3_9_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L11_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I0 I1=L11_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_9_I1_LUT4_O_I3 I3=L11_LUT4_I3_9_I1_LUT4_O_I2 O=L11_LUT4_I3_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 I1=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_16_O I3=R11_LUT4_I3_17_O O=L11_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=L11_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_16_O_LUT4_I2_1_O O=L11_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_14_O I1=R11_LUT4_I3_13_O I2=R11_LUT4_I3_15_O I3=R11_LUT4_I3_12_O O=L11_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_9_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 I2=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R11_LUT4_I3_16_O_LUT4_I2_1_O O=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_15_O I1=R11_LUT4_I3_12_O I2=R11_LUT4_I3_13_O I3=R11_LUT4_I3_14_O O=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_17_O_LUT4_I2_O I1=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_16_O_LUT4_I2_2_O I3=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_15_O I1=R11_LUT4_I3_14_O I2=R11_LUT4_I3_13_O I3=R11_LUT4_I3_12_O O=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_15_O I1=R11_LUT4_I3_14_O I2=R11_LUT4_I3_13_O I3=R11_LUT4_I3_12_O O=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_16_O_LUT4_I2_2_O I3=L11_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_14_O I1=R11_LUT4_I3_15_O I2=R11_LUT4_I3_13_O I3=R11_LUT4_I3_12_O O=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_17_O_LUT4_I2_O I1=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_16_O_LUT4_I2_1_O O=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_15_O I1=R11_LUT4_I3_13_O I2=R11_LUT4_I3_14_O I3=R11_LUT4_I3_12_O O=L11_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L11_LUT4_I3_9_I1_LUT4_O_I0 I1=L11_LUT4_I3_9_I1_LUT4_O_I1 I2=L11_LUT4_I3_9_I1_LUT4_O_I2 I3=L11_LUT4_I3_9_I1_LUT4_O_I3 O=L11_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_9_I0_LUT4_O_I1 I3=L11_LUT4_I3_23_I1_LUT4_O_I3 O=L11_LUT4_I3_9_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_16_O_LUT4_I2_1_O I3=L11_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_16_O_LUT4_I2_O O=L11_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_17_O_LUT4_I2_O I1=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L11_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1 I3=R11_LUT4_I3_16_O_LUT4_I2_2_O O=L11_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_15_O I1=R11_LUT4_I3_14_O I2=R11_LUT4_I3_13_O I3=R11_LUT4_I3_12_O O=L11_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L11_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I0 I1=R11_LUT4_I3_16_O_LUT4_I2_1_O I2=R11_LUT4_I3_16_O_LUT4_I2_2_O I3=L11_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_14_O I1=R11_LUT4_I3_12_O I2=R11_LUT4_I3_13_O I3=R11_LUT4_I3_15_O O=L11_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R11_LUT4_I3_15_O I1=R11_LUT4_I3_14_O I2=R11_LUT4_I3_13_O I3=R11_LUT4_I3_12_O O=L11_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_17_O_LUT4_I2_O I3=L11_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_13_O I1=R11_LUT4_I3_14_O I2=R11_LUT4_I3_15_O I3=R11_LUT4_I3_12_O O=L11_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_15_O I1=R11_LUT4_I3_13_O I2=R11_LUT4_I3_12_O I3=R11_LUT4_I3_14_O O=L11_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_9_I2_LUT4_O_I2 I3=L11_LUT4_I3_9_I2_LUT4_O_I3 O=L11_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3 I3=R11_LUT4_I3_17_O_LUT4_I2_O O=L11_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R11_LUT4_I3_16_O_LUT4_I2_1_O I3=L11_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I2 O=L11_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2 I2=R11_LUT4_I3_16_O_LUT4_I2_2_O I3=L11_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I0 O=L11_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_23_I0_LUT4_O_I3 I1=L11_LUT4_I3_14_I2_LUT4_O_I3 I2=L11_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R11_LUT4_I3_17_O_LUT4_I2_O I1=L11_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R11_LUT4_I3_16_O_LUT4_I2_1_O I3=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_16_O_LUT4_I2_O I1=L11_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_16_O_LUT4_I2_2_O I3=L11_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L11_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I1=L11_LUT4_I3_I0_LUT4_O_I1 I2=L11_LUT4_I3_I0_LUT4_O_I2 I3=L11_LUT4_I3_I0_LUT4_O_I3 O=L11_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_5_I2_LUT4_O_I1 O=L11_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=L11_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_1_O I1=L11_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=L11_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1 I3=R11_LUT4_I3_23_O_LUT4_I2_O O=L11_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R11_LUT4_I3_22_O_LUT4_I2_2_O I3=L11_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=L11_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R11_LUT4_I3_22_O_LUT4_I2_1_O I3=L11_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L11_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_2_O I1=L11_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 O=L11_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I1=L11_LUT4_I3_I1_LUT4_O_I1 I2=L11_LUT4_I3_I0_LUT4_O_I1 I3=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L11_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L11_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=L11_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L11_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_22_O_LUT4_I2_1_O I3=L11_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_20_O I1=R11_LUT4_I3_19_O I2=R11_LUT4_I3_18_O I3=R11_LUT4_I3_21_O O=L11_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_2_O I1=L11_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1 O=L11_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L11_LUT4_I3_I2_LUT4_O_I0 I1=L11_LUT4_I3_I2_LUT4_O_I1 I2=L11_LUT4_I3_I2_LUT4_O_I2 I3=L11_LUT4_I3_I2_LUT4_O_I3 O=L11_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I1=L11_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=R11_LUT4_I3_22_O I3=R11_LUT4_I3_23_O O=L11_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R11_LUT4_I3_21_O I1=R11_LUT4_I3_19_O I2=R11_LUT4_I3_20_O I3=R11_LUT4_I3_18_O O=L11_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_22_O_LUT4_I2_2_O O=L11_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3 I3=R11_LUT4_I3_22_O_LUT4_I2_1_O O=L11_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_21_O I1=R11_LUT4_I3_20_O I2=R11_LUT4_I3_19_O I3=R11_LUT4_I3_18_O O=L11_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L11_LUT4_I3_13_I2_LUT4_O_I3 I1=R11_LUT4_I3_22_O_LUT4_I2_1_O I2=L11_LUT4_I3_16_I0_LUT4_O_I1 I3=L11_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=L11_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R11_LUT4_I3_23_O_LUT4_I2_O I3=L11_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L11_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=L11_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1 I3=R11_LUT4_I3_22_O_LUT4_I2_2_O O=L11_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_18_O I1=R11_LUT4_I3_20_O I2=R11_LUT4_I3_19_O I3=R11_LUT4_I3_21_O O=L11_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_22_O_LUT4_I2_2_O O=L11_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_21_O I1=R11_LUT4_I3_19_O I2=R11_LUT4_I3_18_O I3=R11_LUT4_I3_20_O O=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_1_O I1=L11_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1 I2=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R11_LUT4_I3_23_O_LUT4_I2_O O=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1 I2=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=L11_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R11_LUT4_I3_22_O_LUT4_I2_O I1=L11_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 I2=L11_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R11_LUT4_I3_22_O_LUT4_I2_2_O O=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R11_LUT4_I3_21_O I1=R11_LUT4_I3_20_O I2=R11_LUT4_I3_19_O I3=R11_LUT4_I3_18_O O=L11_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=L11(1) D=R10(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(2) D=R10(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(11) D=R10(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(12) D=R10(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(13) D=R10(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(14) D=R10(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(15) D=R10(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(16) D=R10(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(17) D=R10(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(18) D=R10(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(19) D=R10(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(20) D=R10(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(3) D=R10(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(21) D=R10(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(22) D=R10(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(23) D=R10(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(24) D=R10(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(25) D=R10(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(26) D=R10(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(27) D=R10(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(28) D=R10(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(29) D=R10(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(30) D=R10(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(4) D=R10(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(31) D=R10(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(32) D=R10(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(5) D=R10(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(6) D=R10(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(7) D=R10(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(8) D=R10(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(9) D=R10(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L11(10) D=R10(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:179.1-180.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L12(10) I2=L12_LUT4_I1_I2 I3=L12_LUT4_I1_I3 O=R13_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L12(12) I2=L12_LUT4_I1_1_I2 I3=L12_LUT4_I1_1_I3 O=R13_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_6_I1 I2=L12_LUT4_I3_6_I0_LUT4_O_I3 I3=L12_LUT4_I3_3_I1 O=L12_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L12_LUT4_I1_1_I3_LUT4_O_I0 I1=L12_LUT4_I3_3_I2 I2=L12_LUT4_I3_3_I0_LUT4_O_I1 I3=L12_LUT4_I1_1_I3_LUT4_O_I3 O=L12_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_11_I2_LUT4_O_I1 I2=L12_LUT4_I3_6_I2_LUT4_O_I3 I3=L12_LUT4_I3_6_I2_LUT4_O_I2 O=L12_LUT4_I1_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=L12(29) I2=L12_LUT4_I1_2_I2 I3=L12_LUT4_I1_2_I3 O=R13_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L12_LUT4_I1_2_I2_LUT4_O_I0 I1=L12_LUT4_I1_2_I2_LUT4_O_I1 I2=L12_LUT4_I1_5_I3_LUT4_O_I3 I3=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O O=L12_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L12_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I0 I1=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2 I2=R12_LUT4_I3_28_O I3=R12_LUT4_I3_29_O O=L12_LUT4_I1_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R12_LUT4_I3_27_O I1=R12_LUT4_I3_25_O I2=R12_LUT4_I3_26_O I3=R12_LUT4_I3_24_O O=L12_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_2_I3_LUT4_O_I1 I2=L12_LUT4_I1_2_I3_LUT4_O_I2 I3=L12_LUT4_I1_2_I3_LUT4_O_I3 O=L12_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I1_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_28_O_LUT4_I2_2_O I1=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I0 I3=R12_LUT4_I3_28_O_LUT4_I2_1_O O=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_26_O I1=R12_LUT4_I3_25_O I2=R12_LUT4_I3_27_O I3=R12_LUT4_I3_24_O O=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_27_O I1=R12_LUT4_I3_26_O I2=R12_LUT4_I3_25_O I3=R12_LUT4_I3_24_O O=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_27_O I1=R12_LUT4_I3_26_O I2=R12_LUT4_I3_25_O I3=R12_LUT4_I3_24_O O=L12_LUT4_I1_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L12(1) I2=L12_LUT4_I1_3_I2 I3=L12_LUT4_I1_3_I3 O=R13_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=L12_LUT4_I1_3_I2_LUT4_O_I2 I3=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O O=L12_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_20_I2_LUT4_O_I2 I3=R12_LUT4_I3_11_O_LUT4_I2_O O=L12_LUT4_I1_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_10_O_LUT4_I2_O O=L12_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_1_O I1=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R12_LUT4_I3_10_O_LUT4_I2_2_O I3=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 O=L12_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I1_3_I3_LUT4_O_I0 I1=L12_LUT4_I1_3_I3_LUT4_O_I1 I2=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L12_LUT4_I3_20_I1 O=L12_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2 I3=L12_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3 O=L12_LUT4_I1_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_2_O I1=L12_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_11_O_LUT4_I2_O I3=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_8_O I1=R12_LUT4_I3_7_O I2=R12_LUT4_I3_9_O I3=R12_LUT4_I3_6_O O=L12_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R12_LUT4_I3_10_O_LUT4_I2_1_O I3=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I1_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_1_O I1=L12_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I2=R12_LUT4_I3_11_O_LUT4_I2_O I3=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_9_O I1=R12_LUT4_I3_7_O I2=R12_LUT4_I3_6_O I3=R12_LUT4_I3_8_O O=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1 I3=R12_LUT4_I3_10_O_LUT4_I2_2_O O=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_7_O I1=R12_LUT4_I3_6_O I2=R12_LUT4_I3_9_O I3=R12_LUT4_I3_8_O O=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L12(13) I2=L12_LUT4_I1_4_I2 I3=L12_LUT4_I1_4_I3 O=R13_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=L12_LUT4_I3_8_I0 I1=L12_LUT4_I1_4_I2_LUT4_O_I1 I2=L12_LUT4_I1_4_I2_LUT4_O_I2 I3=L12_LUT4_I1_4_I2_LUT4_O_I3 O=L12_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_22_O_LUT4_I2_1_O O=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_21_O I1=R12_LUT4_I3_19_O I2=R12_LUT4_I3_20_O I3=R12_LUT4_I3_18_O O=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_2_O I1=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_23_O_LUT4_I2_O O=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_20_O I1=R12_LUT4_I3_19_O I2=R12_LUT4_I3_21_O I3=R12_LUT4_I3_18_O O=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_23_O_LUT4_I2_O I3=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 O=L12_LUT4_I1_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I1 I1=R12_LUT4_I3_23_O_LUT4_I2_O I2=R12_LUT4_I3_22_O_LUT4_I2_2_O I3=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_16_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_1_O I1=L12_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_22_O_LUT4_I2_2_O I3=L12_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_21_O I1=R12_LUT4_I3_20_O I2=R12_LUT4_I3_19_O I3=R12_LUT4_I3_18_O O=L12_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_1_O I1=L12_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_22_O_LUT4_I2_2_O I3=L12_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I1_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_21_O I1=R12_LUT4_I3_20_O I2=R12_LUT4_I3_18_O I3=R12_LUT4_I3_19_O O=L12_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_4_I3_LUT4_O_I1 I2=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=L12_LUT4_I1_6_I3_LUT4_O_I3 O=L12_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O O=L12_LUT4_I1_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_22_O_LUT4_I2_2_O O=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_21_O I1=R12_LUT4_I3_19_O I2=R12_LUT4_I3_18_O I3=R12_LUT4_I3_20_O O=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_1_O I1=L12_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_23_O_LUT4_I2_O I3=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_21_O I1=R12_LUT4_I3_18_O I2=R12_LUT4_I3_19_O I3=R12_LUT4_I3_20_O O=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L12(19) I2=L12_LUT4_I1_5_I2 I3=L12_LUT4_I1_5_I3 O=R13_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_1_I1_LUT4_O_I3 I2=L12_LUT4_I1_5_I2_LUT4_O_I2 I3=L12_LUT4_I1_5_I2_LUT4_O_I3 O=L12_LUT4_I1_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I1_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I3 I1=L12_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R12_LUT4_I3_28_O_LUT4_I2_2_O I3=L12_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 I1=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0 I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_I1_LUT4_O_I1 I2=L12_LUT4_I3_I1_LUT4_O_I2 I3=L12_LUT4_I3_I1_LUT4_O_I0 O=L12_LUT4_I1_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I1_2_I3 I3=L12_LUT4_I1_5_I3_LUT4_O_I3 O=L12_LUT4_I1_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L12_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I0 I1=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I2=L12_LUT4_I3_1_I2_LUT4_O_I2 I3=L12_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I1_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I0 I1=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_29_O I3=R12_LUT4_I3_28_O O=L12_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I3 I1=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12(28) I2=L12_LUT4_I1_6_I2 I3=L12_LUT4_I1_6_I3 O=R13_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I2=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=L12_LUT4_I1_6_I2_LUT4_O_I3 O=L12_LUT4_I1_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_22_O_LUT4_I2_2_O O=L12_LUT4_I1_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_22_O_LUT4_I2_1_O O=L12_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_23_O_LUT4_I2_O I3=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_18_O I1=R12_LUT4_I3_20_O I2=R12_LUT4_I3_19_O I3=R12_LUT4_I3_21_O O=L12_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L12_LUT4_I1_6_I3_LUT4_O_I0 I1=L12_LUT4_I1_6_I3_LUT4_O_I1 I2=L12_LUT4_I1_6_I3_LUT4_O_I2 I3=L12_LUT4_I1_6_I3_LUT4_O_I3 O=L12_LUT4_I1_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_8_I2_LUT4_O_I2 I1=L12_LUT4_I1_4_I2_LUT4_O_I1 I2=L12_LUT4_I3_16_I1_LUT4_O_I2 I3=L12_LUT4_I3_16_I1_LUT4_O_I1 O=L12_LUT4_I1_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R12_LUT4_I3_23_O_LUT4_I2_O I1=L12_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2 I2=L12_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I3_16_I2_LUT4_O_I3 O=L12_LUT4_I1_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0 I3=R12_LUT4_I3_22_O_LUT4_I2_O O=L12_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=L12_LUT4_I1_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_1_O I1=L12_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_22_O_LUT4_I2_2_O I3=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_21_O I1=R12_LUT4_I3_20_O I2=R12_LUT4_I3_19_O I3=R12_LUT4_I3_18_O O=L12_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 I2=R12_LUT4_I3_23_O_LUT4_I2_O I3=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_16_I0_LUT4_O_I2 I2=L12_LUT4_I1_6_I2_LUT4_O_I3 I3=L12_LUT4_I1_4_I3_LUT4_O_I1 O=L12_LUT4_I1_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I1=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L12_LUT4_I1_I2_LUT4_O_I2 I3=L12_LUT4_I1_I2_LUT4_O_I3 O=L12_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I1=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L12_LUT4_I1_I2_LUT4_O_I2 I3=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3 O=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0 I2=R12_LUT4_I3_10_O_LUT4_I2_2_O I3=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1 I3=R12_LUT4_I3_11_O_LUT4_I2_O O=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_20_I2_LUT4_O_I2 I3=R12_LUT4_I3_10_O_LUT4_I2_O O=L12_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_10_O_LUT4_I2_2_O O=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_1_O I1=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_11_O_LUT4_I2_O O=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_8_O I1=R12_LUT4_I3_9_O I2=R12_LUT4_I3_7_O I3=R12_LUT4_I3_6_O O=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_10_O_LUT4_I2_2_O I3=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_6_O I1=R12_LUT4_I3_8_O I2=R12_LUT4_I3_7_O I3=R12_LUT4_I3_9_O O=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_8_O I1=R12_LUT4_I3_7_O I2=R12_LUT4_I3_6_O I3=R12_LUT4_I3_9_O O=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_1_O I1=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_11_O_LUT4_I2_O I3=L12_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 O=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L12_LUT4_I1_I3_LUT4_O_I1 I2=L12_LUT4_I1_I3_LUT4_O_I2 I3=L12_LUT4_I1_I3_LUT4_O_I3 O=L12_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I1=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_11_O I3=R12_LUT4_I3_10_O O=L12_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R12_LUT4_I3_9_O I1=R12_LUT4_I3_8_O I2=R12_LUT4_I3_6_O I3=R12_LUT4_I3_7_O O=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_9_O I1=R12_LUT4_I3_8_O I2=R12_LUT4_I3_7_O I3=R12_LUT4_I3_6_O O=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I1_3_I2_LUT4_O_I2 I1=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I1_I2_LUT4_O_I3 O=L12_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_20_I2_LUT4_O_I2 I3=R12_LUT4_I3_10_O_LUT4_I2_2_O O=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_11_O_LUT4_I2_O O=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I2=L12_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_10_O_LUT4_I2_1_O O=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_10_O_LUT4_I2_1_O I3=L12_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_2_O I1=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I3=R12_LUT4_I3_11_O_LUT4_I2_O O=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_20_I1_LUT4_O_I3 I2=L12_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I1_3_I3_LUT4_O_I0 O=L12_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I2=R12_LUT4_I3_11_O_LUT4_I2_O I3=L12_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_9_O I1=R12_LUT4_I3_6_O I2=R12_LUT4_I3_7_O I3=R12_LUT4_I3_8_O O=L12_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12(6) I3=L12_LUT4_I2_I3 O=R13_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12(15) I3=L12_LUT4_I2_1_I3 O=R13_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L12_LUT4_I2_1_I3_LUT4_O_I0 I1=L12_LUT4_I3_4_I0_LUT4_I0_O I2=L12_LUT4_I2_1_I3_LUT4_O_I2 I3=L12_LUT4_I2_1_I3_LUT4_O_I3 O=L12_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L12_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3 O=L12_LUT4_I2_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_16_O_LUT4_I2_O I3=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_17_O_LUT4_I2_O I1=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_4_I0_LUT4_O_I3 I3=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O O=L12_LUT4_I2_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12(24) I3=L12_LUT4_I2_2_I3 O=R13_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L12_LUT4_I2_2_I3_LUT4_O_I0 I1=L12_LUT4_I2_2_I3_LUT4_O_I1 I2=L12_LUT4_I2_2_I3_LUT4_O_I2 I3=L12_LUT4_I2_2_I3_LUT4_O_I3 O=L12_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I0 I1=R12_LUT4_I3_34_O_LUT4_I2_O I2=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2 I3=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I2_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R12_LUT4_I3_33_O I1=R12_LUT4_I3_30_O I2=R12_LUT4_I3_31_O I3=R12_LUT4_I3_32_O O=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_35_O I3=R12_LUT4_I3_34_O O=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001100110101
+.subckt LUT4 I0=R12_LUT4_I3_33_O I1=R12_LUT4_I3_32_O I2=R12_LUT4_I3_31_O I3=R12_LUT4_I3_30_O O=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_33_O I1=R12_LUT4_I3_32_O I2=R12_LUT4_I3_31_O I3=R12_LUT4_I3_30_O O=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_34_O_LUT4_I2_1_O O=L12_LUT4_I2_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_34_O_LUT4_I2_2_O O=L12_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_33_O I1=R12_LUT4_I3_32_O I2=R12_LUT4_I3_31_O I3=R12_LUT4_I3_30_O O=L12_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I2_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 I1=R12_LUT4_I3_34_O_LUT4_I2_O I2=R12_LUT4_I3_34_O_LUT4_I2_1_O I3=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_32_O I1=R12_LUT4_I3_33_O I2=R12_LUT4_I3_31_O I3=R12_LUT4_I3_30_O O=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_35_O_LUT4_I2_O I3=L12_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I2 O=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_33_O I1=R12_LUT4_I3_32_O I2=R12_LUT4_I3_30_O I3=R12_LUT4_I3_31_O O=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_15_I0_LUT4_O_I1 I2=L12_LUT4_I3_15_I0_LUT4_O_I0 I3=L12_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I2_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L12_LUT4_I3_15_I0 I1=L12_LUT4_I2_I3_LUT4_O_I1 I2=L12_LUT4_I2_I3_LUT4_O_I2 I3=L12_LUT4_I2_I3_LUT4_O_I3 O=L12_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=L12_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I0 I1=L12_LUT4_I3_21_I0_LUT4_O_I2 I2=L12_LUT4_I2_2_I3_LUT4_O_I1 I3=L12_LUT4_I2_2_I3_LUT4_O_I0 O=L12_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_34_O_LUT4_I2_1_O I3=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_34_O_LUT4_I2_O I3=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_30_O I1=R12_LUT4_I3_32_O I2=R12_LUT4_I3_31_O I3=R12_LUT4_I3_33_O O=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_33_O I1=R12_LUT4_I3_32_O I2=R12_LUT4_I3_31_O I3=R12_LUT4_I3_30_O O=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_34_O_LUT4_I2_O I3=L12_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_32_O I1=R12_LUT4_I3_30_O I2=R12_LUT4_I3_31_O I3=R12_LUT4_I3_33_O O=L12_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_1_O I1=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I0 I2=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I0 I3=R12_LUT4_I3_35_O_LUT4_I2_O O=L12_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_I0 I1=L12_LUT4_I3_I1 I2=L12_LUT4_I3_I2 I3=L12(4) O=R13_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L12_LUT4_I3_1_I0 I1=L12_LUT4_I3_1_I1 I2=L12_LUT4_I3_1_I2 I3=L12(11) O=R13_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L12_LUT4_I3_10_I0 I1=L12_LUT4_I3_10_I1 I2=L12_LUT4_I3_10_I2 I3=L12(5) O=R13_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L12_LUT4_I2_1_I3_LUT4_O_I0 I1=L12_LUT4_I3_4_I1_LUT4_O_I0 I2=L12_LUT4_I3_4_I0_LUT4_I0_O I3=L12_LUT4_I3_10_I0_LUT4_O_I3 O=L12_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=L12_LUT4_I3_10_I1_LUT4_O_I0 I1=L12_LUT4_I3_4_I2_LUT4_O_I1 I2=L12_LUT4_I3_10_I1_LUT4_O_I2 I3=L12_LUT4_I3_10_I1_LUT4_O_I3 O=L12_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_10_I1_LUT4_O_I0_LUT4_O_I1 I2=L12_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 I3=R12_LUT4_I3_16_O_LUT4_I2_1_O O=L12_LUT4_I3_10_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_10_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_16_O_LUT4_I2_O O=L12_LUT4_I3_10_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_17_O_LUT4_I2_O I1=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_10_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_16_O_LUT4_I2_O I3=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_10_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_15_O I1=R12_LUT4_I3_13_O I2=R12_LUT4_I3_14_O I3=R12_LUT4_I3_12_O O=L12_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_17_O_LUT4_I2_O I1=L12_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_16_O_LUT4_I2_2_O O=L12_LUT4_I3_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_14_O I1=R12_LUT4_I3_12_O I2=R12_LUT4_I3_13_O I3=R12_LUT4_I3_15_O O=L12_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_10_I2_LUT4_I2_I1 I2=L12_LUT4_I3_10_I2 I3=L12_LUT4_I3_10_I1_LUT4_O_I0 O=L12_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_10_I2_LUT4_O_I1 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_10_I2_LUT4_O_I3 O=L12_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_16_O_LUT4_I2_O O=L12_LUT4_I3_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3 I2=R12_LUT4_I3_17_O_LUT4_I2_O I3=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_10_I2_LUT4_O_I3 I2=R12_LUT4_I3_16_O_LUT4_I2_O I3=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3 O=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_15_O I1=R12_LUT4_I3_12_O I2=R12_LUT4_I3_13_O I3=R12_LUT4_I3_14_O O=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O I1=L12_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2 I2=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2 I3=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3 O=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I2=R12_LUT4_I3_16_O_LUT4_I2_O I3=L12_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 O=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_17_O_LUT4_I2_O I1=L12_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_15_O I1=R12_LUT4_I3_14_O I2=R12_LUT4_I3_13_O I3=R12_LUT4_I3_12_O O=L12_LUT4_I3_10_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I3_11_I0 I1=L12_LUT4_I3_11_I1 I2=L12_LUT4_I3_11_I2 I3=L12(7) O=R13_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_3_I2_LUT4_O_I2 I2=L12_LUT4_I3_6_I0_LUT4_O_I2 I3=L12_LUT4_I3_3_I0_LUT4_O_I1 O=L12_LUT4_I3_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=L12_LUT4_I3_6_I2_LUT4_O_I2 I1=L12_LUT4_I3_11_I1 I2=L12_LUT4_I3_11_I1_LUT4_I1_I2 I3=L12_LUT4_I3_11_I1_LUT4_I1_I3 O=L12_LUT4_I3_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_11_I1_LUT4_I1_I2_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_O O=L12_LUT4_I3_11_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_44_O I1=R12_LUT4_I3_43_O I2=R12_LUT4_I3_42_O I3=R12_LUT4_I3_45_O O=L12_LUT4_I3_11_I1_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L12_LUT4_I3_11_I1_LUT4_I1_I3_LUT4_O_I0 I1=R12_LUT4_I3_46_O_LUT4_I2_1_O I2=R12_LUT4_I3_46_O_LUT4_I2_2_O I3=L12_LUT4_I3_11_I1_LUT4_I1_I3_LUT4_O_I3 O=L12_LUT4_I3_11_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_43_O I1=R12_LUT4_I3_42_O I2=R12_LUT4_I3_45_O I3=R12_LUT4_I3_44_O O=L12_LUT4_I3_11_I1_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_45_O I1=R12_LUT4_I3_44_O I2=R12_LUT4_I3_43_O I3=R12_LUT4_I3_42_O O=L12_LUT4_I3_11_I1_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_11_I1 I3=L12_LUT4_I3_6_I2_LUT4_O_I1 O=L12_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_11_I1_LUT4_O_I1 I2=L12_LUT4_I3_6_I1_LUT4_O_I1 I3=R12_LUT4_I3_46_O_LUT4_I2_2_O O=L12_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_O O=L12_LUT4_I3_11_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_11_I1_LUT4_I1_I3_LUT4_O_I3 I2=L12_LUT4_I3_11_I1_LUT4_I1_I2_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_1_O O=L12_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_44_O I1=R12_LUT4_I3_42_O I2=R12_LUT4_I3_43_O I3=R12_LUT4_I3_45_O O=L12_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_6_I2_LUT4_O_I3 I1=L12_LUT4_I3_11_I2_LUT4_O_I1 I2=L12_LUT4_I3_11_I2_LUT4_O_I2 I3=L12_LUT4_I3_11_I2_LUT4_O_I3 O=L12_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_11_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_46_O_LUT4_I2_O I3=L12_LUT4_I3_11_I1_LUT4_I1_I3_LUT4_O_I3 O=L12_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_1_O I1=L12_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I0 I2=R12_LUT4_I3_46_O_LUT4_I2_2_O I3=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 I2=L12_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_O O=L12_LUT4_I3_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_45_O I1=R12_LUT4_I3_42_O I2=R12_LUT4_I3_43_O I3=R12_LUT4_I3_44_O O=L12_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_1_O I1=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_2_O O=L12_LUT4_I3_11_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_42_O I1=R12_LUT4_I3_44_O I2=R12_LUT4_I3_43_O I3=R12_LUT4_I3_45_O O=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_45_O I1=R12_LUT4_I3_44_O I2=R12_LUT4_I3_43_O I3=R12_LUT4_I3_42_O O=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L12_LUT4_I3_12_I0 I1=L12_LUT4_I3_12_I1 I2=L12_LUT4_I3_12_I2 I3=L12(8) O=R13_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L12_LUT4_I3_9_I0_LUT4_O_I3 I1=L12_LUT4_I3_9_I0_LUT4_O_I2 I2=L12_LUT4_I3_12_I0_LUT4_O_I2 I3=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_I2_O O=L12_LUT4_I3_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_14_I1_LUT4_O_I1 I3=L12_LUT4_I3_7_I0_LUT4_O_I0 O=L12_LUT4_I3_12_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_12_I1_LUT4_O_I1 I2=L12_LUT4_I3_12_I1_LUT4_O_I2 I3=L12_LUT4_I3_12_I1_LUT4_O_I3 O=L12_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L12_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I0 I1=R12_LUT4_I3_O_LUT4_I2_2_O I2=L12_LUT4_I3_12_I1_LUT4_O_I1 I3=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_I2_I3 O=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I3=R12_LUT4_I3_O_LUT4_I3_O O=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R12_LUT4_I3_O_LUT4_I2_2_O O=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I3_O I1=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I2_1_O I3=L12_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 O=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 I2=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_O_LUT4_I3_O O=L12_LUT4_I3_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I0 I1=L12_LUT4_I3_7_I1_LUT4_I1_I2 I2=R12_LUT4_I3_1_O I3=R12_LUT4_I3_O O=L12_LUT4_I3_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R12_LUT4_I3_5_O I1=R12_LUT4_I3_4_O I2=R12_LUT4_I3_3_O I3=R12_LUT4_I3_2_O O=L12_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_12_I2_LUT4_I3_I2 I3=L12_LUT4_I3_12_I2 O=L12_LUT4_I3_9_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I3_O I1=L12_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_7_I1_LUT4_I1_I2 I3=L12_LUT4_I3_12_I2_LUT4_I3_I2_LUT4_O_I3 O=L12_LUT4_I3_12_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I2_2_O I3=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_12_I2_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_12_I2_LUT4_O_I2 I3=L12_LUT4_I3_12_I2_LUT4_O_I3 O=L12_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I3_O I1=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_O_LUT4_I2_2_O O=L12_LUT4_I3_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I2_1_O I3=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_5_O I1=R12_LUT4_I3_4_O I2=R12_LUT4_I3_3_O I3=R12_LUT4_I3_2_O O=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_5_O I1=R12_LUT4_I3_2_O I2=R12_LUT4_I3_3_O I3=R12_LUT4_I3_4_O O=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_19_I0 I1=L12_LUT4_I3_13_I1 I2=L12_LUT4_I3_13_I2 I3=L12(9) O=R13_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=L12_LUT4_I3_19_I1_LUT4_O_I2 I1=L12_LUT4_I3_19_I1_LUT4_O_I1 I2=L12_LUT4_I3_13_I1_LUT4_O_I2 I3=L12_LUT4_I3_13_I1_LUT4_O_I3 O=L12_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R12_LUT4_I3_41_O_LUT4_I2_O I1=L12_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_13_I1_LUT4_O_I2 I3=L12_LUT4_I3_13_I1_LUT4_O_I3 O=L12_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_40_O_LUT4_I2_1_O O=L12_LUT4_I3_13_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_39_O I1=R12_LUT4_I3_37_O I2=R12_LUT4_I3_38_O I3=R12_LUT4_I3_36_O O=L12_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_41_O_LUT4_I2_O I1=L12_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3 I2=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_40_O_LUT4_I2_2_O O=L12_LUT4_I3_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_19_I2_LUT4_O_I2 I3=L12_LUT4_I3_2_I1_LUT4_O_I3 O=L12_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L12_LUT4_I3_14_I0 I1=L12_LUT4_I3_14_I1 I2=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_I2_O I3=L12(14) O=R13_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_7_I2_LUT4_O_I3 I3=L12_LUT4_I3_9_I0_LUT4_O_I3 O=L12_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_14_I1_LUT4_O_I1 I2=L12_LUT4_I3_14_I1_LUT4_O_I2 I3=L12_LUT4_I3_7_I0_LUT4_O_I2 O=L12_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_14_I1_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I3_14_I1_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_14_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 I3=R12_LUT4_I3_O_LUT4_I2_2_O O=L12_LUT4_I3_14_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I3_O I1=L12_LUT4_I3_7_I1_LUT4_O_I2_LUT4_I2_I1 I2=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I3=R12_LUT4_I3_O_LUT4_I2_1_O O=L12_LUT4_I3_14_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_14_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 I2=R12_LUT4_I3_O_LUT4_I2_1_O I3=L12_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I3_O I1=L12_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I2_2_O I3=L12_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_4_O I1=R12_LUT4_I3_3_O I2=R12_LUT4_I3_5_O I3=R12_LUT4_I3_2_O O=L12_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_15_I0 I1=L12_LUT4_I3_21_I2 I2=L12_LUT4_I3_15_I2 I3=L12(16) O=R13_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L12_LUT4_I3_15_I0_LUT4_O_I0 I1=L12_LUT4_I3_15_I0_LUT4_O_I1 I2=L12_LUT4_I3_15_I0_LUT4_O_I2 I3=L12_LUT4_I2_I3_LUT4_O_I2 O=L12_LUT4_I3_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_15_I0_LUT4_O_I0_LUT4_O_I1 I2=L12_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_34_O_LUT4_I2_O O=L12_LUT4_I3_15_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_15_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_34_O_LUT4_I2_1_O O=L12_LUT4_I3_15_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I2_I3_LUT4_O_I3 I3=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I0 O=L12_LUT4_I3_15_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_15_I0_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_15_I0_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_21_I2_LUT4_O_I2 O=L12_LUT4_I3_15_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I0 I2=R12_LUT4_I3_35_O_LUT4_I2_O I3=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=L12_LUT4_I3_15_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_1_O I1=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R12_LUT4_I3_34_O_LUT4_I2_O I3=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_15_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_15_I2_LUT4_O_I2 I3=L12_LUT4_I3_21_I1 O=L12_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_15_I2_LUT4_O_I2 I2=L12_LUT4_I3_21_I2_LUT4_O_I3 I3=L12_LUT4_I3_21_I0_LUT4_O_I2 O=L12_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_O I1=R12_LUT4_I3_34_O_LUT4_I2_1_O I2=L12_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R12_LUT4_I3_33_O I1=R12_LUT4_I3_32_O I2=R12_LUT4_I3_31_O I3=R12_LUT4_I3_30_O O=L12_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_1_O I1=L12_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R12_LUT4_I3_34_O_LUT4_I2_O I3=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=L12_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_16_I0 I1=L12_LUT4_I3_16_I1 I2=L12_LUT4_I3_16_I2 I3=L12(18) O=R13_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I2=L12_LUT4_I3_16_I0_LUT4_O_I2 I3=L12_LUT4_I3_16_I0_LUT4_O_I3 O=L12_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_16_I0_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_22_O_LUT4_I2_O O=L12_LUT4_I3_16_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_16_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_22_O_LUT4_I2_1_O O=L12_LUT4_I3_16_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I0 I1=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_16_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_22_O_LUT4_I2_2_O O=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_1_O I1=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_23_O_LUT4_I2_O O=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I1 I2=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I3=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_22_O_LUT4_I2_2_O I3=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2 O=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_22_O_LUT4_I2_1_O I3=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_2_O I1=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_23_O_LUT4_I2_O I3=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_16_I1_LUT4_O_I1 I2=L12_LUT4_I3_16_I1_LUT4_O_I2 I3=L12_LUT4_I3_8_I2_LUT4_O_I2 O=L12_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 I2=R12_LUT4_I3_22_O_LUT4_I2_1_O I3=L12_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0 O=L12_LUT4_I3_16_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_2_O I1=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_23_O_LUT4_I2_O O=L12_LUT4_I3_16_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_23_O_LUT4_I2_O O=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I3_I2 I3=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O O=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_1_O I1=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R12_LUT4_I3_22_O_LUT4_I2_2_O O=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_20_O I1=R12_LUT4_I3_19_O I2=R12_LUT4_I3_18_O I3=R12_LUT4_I3_21_O O=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_19_O I1=R12_LUT4_I3_18_O I2=R12_LUT4_I3_21_O I3=R12_LUT4_I3_20_O O=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_8_I1 I3=L12_LUT4_I3_16_I2_LUT4_O_I3 O=L12_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_16_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_1_O I1=L12_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 I2=R12_LUT4_I3_22_O_LUT4_I2_2_O I3=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=L12_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R12_LUT4_I3_23_O_LUT4_I2_O O=L12_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L12_LUT4_I3_17_I2 I3=L12(20) O=R13_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L12_LUT4_I3_20_I0_LUT4_O_I2 I1=L12_LUT4_I3_20_I2 I2=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L12_LUT4_I1_3_I3_LUT4_O_I1 O=L12_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I3_18_I0 I1=L12_LUT4_I3_18_I1 I2=L12_LUT4_I3_18_I2 I3=L12(21) O=R13_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_4_I1_LUT4_O_I0 I2=L12_LUT4_I2_1_I3_LUT4_O_I0 I3=L12_LUT4_I3_4_I0_LUT4_I0_O O=L12_LUT4_I3_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_4_I0_LUT4_O_I2 I2=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L12_LUT4_I3_4_I0_LUT4_I0_O O=L12_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_18_I2_LUT4_O_I1 I2=L12_LUT4_I3_18_I2_LUT4_O_I2 I3=L12_LUT4_I3_4_I2_LUT4_O_I0 O=L12_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_O I1=L12_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_18_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_17_O_LUT4_I2_O I3=L12_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_18_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_17_O_LUT4_I2_O I1=L12_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_15_O I1=R12_LUT4_I3_14_O I2=R12_LUT4_I3_13_O I3=R12_LUT4_I3_12_O O=L12_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3 I1=R12_LUT4_I3_17_O_LUT4_I2_O I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_15_O I1=R12_LUT4_I3_14_O I2=R12_LUT4_I3_13_O I3=R12_LUT4_I3_12_O O=L12_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L12_LUT4_I3_19_I0 I1=L12_LUT4_I3_19_I1 I2=L12_LUT4_I3_19_I2 I3=L12(23) O=R13_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L12_LUT4_I3_5_I0_LUT4_O_I0 I1=L12_LUT4_I3_2_I0_LUT4_O_I2 I2=L12_LUT4_I3_19_I0_LUT4_O_I2 I3=L12_LUT4_I3_19_I0_LUT4_O_I3 O=L12_LUT4_I3_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_1_O I1=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_41_O_LUT4_I2_O I3=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_19_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_36_O I1=R12_LUT4_I3_38_O I2=R12_LUT4_I3_37_O I3=R12_LUT4_I3_39_O O=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_37_O I1=R12_LUT4_I3_38_O I2=R12_LUT4_I3_39_O I3=R12_LUT4_I3_36_O O=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_40_O_LUT4_I2_2_O I3=L12_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_19_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_38_O I1=R12_LUT4_I3_37_O I2=R12_LUT4_I3_36_O I3=R12_LUT4_I3_39_O O=L12_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_37_O I1=R12_LUT4_I3_36_O I2=R12_LUT4_I3_39_O I3=R12_LUT4_I3_38_O O=L12_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_5_I1 I1=L12_LUT4_I3_19_I1_LUT4_O_I1 I2=L12_LUT4_I3_19_I1_LUT4_O_I2 I3=L12_LUT4_I3_19_I1_LUT4_O_I3 O=L12_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_19_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 I2=R12_LUT4_I3_40_O_LUT4_I2_2_O I3=L12_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_1_O I1=L12_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 I2=R12_LUT4_I3_41_O_LUT4_I2_O I3=L12_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_40_O_LUT4_I2_2_O I3=L12_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_19_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I3=R12_LUT4_I3_40_O_LUT4_I2_O O=L12_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_1_O I1=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0 I3=R12_LUT4_I3_41_O_LUT4_I2_O O=L12_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_39_O I1=R12_LUT4_I3_38_O I2=R12_LUT4_I3_37_O I3=R12_LUT4_I3_36_O O=L12_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_2_I0_LUT4_O_I2 I2=L12_LUT4_I3_19_I2_LUT4_O_I2 I3=L12_LUT4_I3_2_I1_LUT4_O_I2 O=L12_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3 I2=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_40_O_LUT4_I2_1_O O=L12_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_41_O_LUT4_I2_O I1=L12_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_40_O_LUT4_I2_2_O O=L12_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_1_I0_LUT4_O_I0 I1=L12_LUT4_I1_5_I2_LUT4_O_I2 I2=L12_LUT4_I3_I1_LUT4_O_I1 I3=L12_LUT4_I3_1_I0_LUT4_O_I3 O=L12_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I2 I1=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_28_O I3=R12_LUT4_I3_29_O O=L12_LUT4_I3_1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R12_LUT4_I3_28_O_LUT4_I2_2_O I1=L12_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I3_I0_LUT4_O_I1 O=L12_LUT4_I3_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_27_O I1=R12_LUT4_I3_26_O I2=R12_LUT4_I3_25_O I3=R12_LUT4_I3_24_O O=L12_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L12_LUT4_I3_I2_LUT4_O_I2 I1=L12_LUT4_I3_1_I1_LUT4_I2_I1 I2=L12_LUT4_I3_1_I1 I3=L12_LUT4_I3_I1_LUT4_O_I0 O=L12_LUT4_I1_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R12_LUT4_I3_28_O_LUT4_I2_2_O I1=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_1_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_1_I1_LUT4_O_I1 I2=L12_LUT4_I3_1_I1_LUT4_O_I2 I3=L12_LUT4_I3_1_I1_LUT4_O_I3 O=L12_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I3 I1=L12_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_I0_LUT4_O_I0 I3=R12_LUT4_I3_28_O_LUT4_I2_1_O O=L12_LUT4_I3_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_26_O I1=R12_LUT4_I3_25_O I2=R12_LUT4_I3_24_O I3=R12_LUT4_I3_27_O O=L12_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 I1=L12_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_28_O_LUT4_I2_2_O I3=L12_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 I1=L12_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_28_O_LUT4_I2_2_O I3=L12_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_27_O I1=R12_LUT4_I3_26_O I2=R12_LUT4_I3_24_O I3=R12_LUT4_I3_25_O O=L12_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_28_O_LUT4_I2_2_O I1=L12_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I3 I1=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_1_I2_LUT4_O_I0 I1=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I2=L12_LUT4_I3_1_I2_LUT4_O_I2 I3=L12_LUT4_I3_1_I2_LUT4_O_I3 O=L12_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0 I1=L12_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I0 I2=R12_LUT4_I3_29_O I3=R12_LUT4_I3_28_O O=L12_LUT4_I3_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0 I3=L12_LUT4_I1_2_I3_LUT4_O_I3 O=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2 O=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_25_O I1=R12_LUT4_I3_26_O I2=R12_LUT4_I3_27_O I3=R12_LUT4_I3_24_O O=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I1_2_I3_LUT4_O_I2 O=L12_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_28_O_LUT4_I2_2_O I3=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2 O=L12_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I3 I1=L12_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 I1=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_28_O_LUT4_I2_1_O O=L12_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_27_O I1=R12_LUT4_I3_25_O I2=R12_LUT4_I3_24_O I3=R12_LUT4_I3_26_O O=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_27_O I1=R12_LUT4_I3_26_O I2=R12_LUT4_I3_25_O I3=R12_LUT4_I3_24_O O=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_2_I0 I1=L12_LUT4_I3_2_I1 I2=L12_LUT4_I3_2_I2 I3=L12(17) O=R13_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L12_LUT4_I3_20_I0 I1=L12_LUT4_I3_20_I1 I2=L12_LUT4_I3_20_I2 I3=L12(26) O=R13_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L12_LUT4_I1_I3_LUT4_O_I2 I2=L12_LUT4_I3_20_I0_LUT4_O_I2 I3=L12_LUT4_I3_20_I0_LUT4_O_I3 O=L12_LUT4_I3_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I1_3_I2_LUT4_O_I2 O=L12_LUT4_I3_20_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=L12_LUT4_I3_20_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L12_LUT4_I3_20_I1_LUT4_O_I0 I1=L12_LUT4_I3_20_I1_LUT4_O_I1 I2=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L12_LUT4_I3_20_I1_LUT4_O_I3 O=L12_LUT4_I3_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0 I1=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1 I2=R12_LUT4_I3_11_O I3=R12_LUT4_I3_10_O O=L12_LUT4_I3_20_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R12_LUT4_I3_9_O I1=R12_LUT4_I3_8_O I2=R12_LUT4_I3_7_O I3=R12_LUT4_I3_6_O O=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1 I2=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1 I3=R12_LUT4_I3_10_O_LUT4_I2_1_O O=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_2_O I1=L12_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R12_LUT4_I3_11_O_LUT4_I2_O I3=L12_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0 I3=R12_LUT4_I3_10_O_LUT4_I2_O O=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_10_O_LUT4_I2_2_O I3=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1 O=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_9_O I1=R12_LUT4_I3_8_O I2=R12_LUT4_I3_7_O I3=R12_LUT4_I3_6_O O=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_10_O_LUT4_I2_1_O I3=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_20_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_9_O I1=R12_LUT4_I3_8_O I2=R12_LUT4_I3_7_O I3=R12_LUT4_I3_6_O O=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_1_O I1=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3 I3=R12_LUT4_I3_11_O_LUT4_I2_O O=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_7_O I1=R12_LUT4_I3_8_O I2=R12_LUT4_I3_9_O I3=R12_LUT4_I3_6_O O=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3 I2=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_10_O_LUT4_I2_1_O O=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_1_O I1=L12_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R12_LUT4_I3_10_O_LUT4_I2_2_O I3=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_10_O_LUT4_I2_O O=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I2=R12_LUT4_I3_11_O_LUT4_I2_O I3=L12_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0 O=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_8_O I1=R12_LUT4_I3_6_O I2=R12_LUT4_I3_7_O I3=R12_LUT4_I3_9_O O=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_2_O I1=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_11_O_LUT4_I2_O O=L12_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_20_I2_LUT4_O_I1 I2=L12_LUT4_I3_20_I2_LUT4_O_I2 I3=R12_LUT4_I3_10_O_LUT4_I2_1_O O=L12_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_10_O_LUT4_I2_2_O O=L12_LUT4_I3_20_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_10_O_LUT4_I2_O I1=L12_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I3=R12_LUT4_I3_11_O_LUT4_I2_O O=L12_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_9_O I1=R12_LUT4_I3_7_O I2=R12_LUT4_I3_8_O I3=R12_LUT4_I3_6_O O=L12_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_9_O I1=R12_LUT4_I3_8_O I2=R12_LUT4_I3_7_O I3=R12_LUT4_I3_6_O O=L12_LUT4_I3_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I3_21_I0 I1=L12_LUT4_I3_21_I1 I2=L12_LUT4_I3_21_I2 I3=L12(30) O=R13_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_21_I0_LUT4_O_I2 I3=L12_LUT4_I3_21_I0_LUT4_O_I3 O=L12_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_21_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_34_O_LUT4_I2_1_O O=L12_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_35_O_LUT4_I2_O I1=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R12_LUT4_I3_34_O_LUT4_I2_O O=L12_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I0 I1=L12_LUT4_I2_I3_LUT4_O_I3 I2=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_21_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R12_LUT4_I3_34_O_LUT4_I2_1_O I3=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I0 I3=R12_LUT4_I3_35_O_LUT4_I2_O O=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_1_O I1=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I0 I2=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_34_O_LUT4_I2_O O=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I2_2_I3_LUT4_O_I2 I2=L12_LUT4_I3_21_I1_LUT4_O_I2 I3=L12_LUT4_I2_2_I3_LUT4_O_I1 O=L12_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 I1=R12_LUT4_I3_35_O_LUT4_I2_O I2=L12_LUT4_I3_21_I1_LUT4_O_I2 I3=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_I2_I3 O=L12_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1 I2=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_34_O_LUT4_I2_O O=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=R12_LUT4_I3_34_O_LUT4_I2_2_O O=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I0 I1=R12_LUT4_I3_34_O_LUT4_I2_2_O I2=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_21_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=R12_LUT4_I3_33_O I1=R12_LUT4_I3_31_O I2=R12_LUT4_I3_32_O I3=R12_LUT4_I3_30_O O=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R12_LUT4_I3_35_O_LUT4_I2_O O=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_35_O_LUT4_I2_O I1=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I0 I3=R12_LUT4_I3_34_O_LUT4_I2_O O=L12_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_33_O I1=R12_LUT4_I3_31_O I2=R12_LUT4_I3_30_O I3=R12_LUT4_I3_32_O O=L12_LUT4_I3_21_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_21_I2_LUT4_O_I2 I3=L12_LUT4_I3_21_I2_LUT4_O_I3 O=L12_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_35_O_LUT4_I2_O I1=R12_LUT4_I3_34_O_LUT4_I2_2_O I2=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R12_LUT4_I3_35_O_LUT4_I2_O I1=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_34_O_LUT4_I2_O I3=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=L12_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_31_O I1=R12_LUT4_I3_32_O I2=R12_LUT4_I3_33_O I3=R12_LUT4_I3_30_O O=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_35_O_LUT4_I2_O O=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_32_O I1=R12_LUT4_I3_31_O I2=R12_LUT4_I3_33_O I3=R12_LUT4_I3_30_O O=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_35_O_LUT4_I2_O I1=R12_LUT4_I3_34_O_LUT4_I2_2_O I2=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_21_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I2 I2=L12_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_35_O_LUT4_I2_O O=L12_LUT4_I3_15_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_35_O_LUT4_I2_O I3=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I2 O=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_31_O I1=R12_LUT4_I3_30_O I2=R12_LUT4_I3_33_O I3=R12_LUT4_I3_32_O O=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_34_O_LUT4_I2_2_O I1=L12_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R12_LUT4_I3_35_O_LUT4_I2_O I3=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_32_O I1=R12_LUT4_I3_31_O I2=R12_LUT4_I3_30_O I3=R12_LUT4_I3_33_O O=L12_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L12_LUT4_I3_5_I0_LUT4_O_I0 I1=L12_LUT4_I3_2_I0_LUT4_O_I1 I2=L12_LUT4_I3_2_I0_LUT4_O_I2 I3=L12_LUT4_I3_2_I0_LUT4_O_I3 O=L12_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L12_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I1=L12_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_41_O I3=R12_LUT4_I3_40_O O=L12_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I2=R12_LUT4_I3_41_O_LUT4_I2_O I3=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_1_O I1=L12_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3 I2=L12_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I1 I3=R12_LUT4_I3_40_O_LUT4_I2_2_O O=L12_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_41_O_LUT4_I2_O I1=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_40_O_LUT4_I2_2_O I3=L12_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_39_O I1=R12_LUT4_I3_36_O I2=R12_LUT4_I3_37_O I3=R12_LUT4_I3_38_O O=L12_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_2_I1_LUT4_O_I2 I3=L12_LUT4_I3_2_I1_LUT4_O_I3 O=L12_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_1_O I1=L12_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_41_O_LUT4_I2_O I3=L12_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_40_O_LUT4_I2_2_O O=L12_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_40_O_LUT4_I2_O I3=L12_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_40_O_LUT4_I2_1_O O=L12_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_41_O_LUT4_I2_O I1=L12_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 I2=R12_LUT4_I3_40_O_LUT4_I2_2_O I3=L12_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0 O=L12_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_2_I2_LUT4_O_I2 I3=L12_LUT4_I3_5_I1_LUT4_O_I3 O=L12_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_2_O I1=L12_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 I2=L12_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 I2=R12_LUT4_I3_40_O_LUT4_I2_1_O I3=L12_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_3_I0 I1=L12_LUT4_I3_3_I1 I2=L12_LUT4_I3_3_I2 I3=L12(22) O=R13_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L12_LUT4_I3_6_I1 I1=L12_LUT4_I3_3_I0_LUT4_O_I1 I2=L12_LUT4_I3_3_I0_LUT4_O_I2 I3=L12_LUT4_I3_6_I1_LUT4_O_I3 O=L12_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L12_LUT4_I3_3_I1 I1=L12_LUT4_I3_6_I0_LUT4_O_I3 I2=L12_LUT4_I3_6_I0_LUT4_O_I2 I3=L12_LUT4_I3_6_I0_LUT4_O_I0 O=L12_LUT4_I3_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_3_I1_LUT4_O_I1 I2=L12_LUT4_I3_3_I2_LUT4_O_I1 I3=R12_LUT4_I3_46_O_LUT4_I2_O O=L12_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_1_O O=L12_LUT4_I3_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_46_O_LUT4_I2_2_O I3=L12_LUT4_I3_11_I1_LUT4_I1_I2_LUT4_O_I2 O=L12_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_1_O I1=L12_LUT4_I3_3_I2_LUT4_O_I1 I2=L12_LUT4_I3_3_I2_LUT4_O_I2 I3=L12_LUT4_I3_3_I2_LUT4_O_I3 O=L12_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R12_LUT4_I3_43_O I1=R12_LUT4_I3_44_O I2=R12_LUT4_I3_45_O I3=R12_LUT4_I3_42_O O=L12_LUT4_I3_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_2_O I1=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_46_O_LUT4_I2_O I3=L12_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I2 O=L12_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_11_I1_LUT4_I1_I3_LUT4_O_I0 I2=R12_LUT4_I3_46_O_LUT4_I2_1_O I3=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 O=L12_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_6_I1_LUT4_O_I1 I3=R12_LUT4_I3_47_O_LUT4_I2_O O=L12_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_2_O I1=L12_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I0 I2=R12_LUT4_I3_46_O_LUT4_I2_O I3=L12_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_4_I0 I1=L12_LUT4_I3_4_I1 I2=L12_LUT4_I3_4_I2 I3=L12(27) O=R13_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L12_LUT4_I3_4_I0 I1=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I2=L12_LUT4_I3_4_I1_LUT4_O_I3 I3=L12_LUT4_I3_4_I1_LUT4_O_I1 O=L12_LUT4_I3_4_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I3_4_I1_LUT4_O_I3 I1=L12_LUT4_I3_4_I0 I2=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L12_LUT4_I3_4_I0_LUT4_I1_I3 O=L12_LUT4_I3_10_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2 I3=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O O=L12_LUT4_I3_4_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_4_I0_LUT4_O_I2 I3=L12_LUT4_I3_4_I0_LUT4_O_I3 O=L12_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I3=R12_LUT4_I3_16_O_LUT4_I2_O O=L12_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_13_O I1=R12_LUT4_I3_14_O I2=R12_LUT4_I3_15_O I3=R12_LUT4_I3_12_O O=L12_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_17_O_LUT4_I2_O I1=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 O=L12_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I2=R12_LUT4_I3_16_O_LUT4_I2_O I3=L12_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_17_O_LUT4_I2_O I1=L12_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_4_I1_LUT4_O_I0 I1=L12_LUT4_I3_4_I1_LUT4_O_I1 I2=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L12_LUT4_I3_4_I1_LUT4_O_I3 O=L12_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I2 I3=L12_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3 O=L12_LUT4_I3_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I3=R12_LUT4_I3_16_O_LUT4_I2_2_O O=L12_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_O I1=L12_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_17_O_LUT4_I2_O O=L12_LUT4_I3_4_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I1=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_16_O_LUT4_I2_O I3=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R12_LUT4_I3_12_O I1=R12_LUT4_I3_14_O I2=R12_LUT4_I3_13_O I3=R12_LUT4_I3_15_O O=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_14_O I1=R12_LUT4_I3_13_O I2=R12_LUT4_I3_15_O I3=R12_LUT4_I3_12_O O=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1 I1=R12_LUT4_I3_16_O_LUT4_I2_2_O I2=R12_LUT4_I3_17_O_LUT4_I2_O I3=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I1=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R12_LUT4_I3_13_O I1=R12_LUT4_I3_12_O I2=R12_LUT4_I3_15_O I3=R12_LUT4_I3_14_O O=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_14_O I1=R12_LUT4_I3_13_O I2=R12_LUT4_I3_12_O I3=R12_LUT4_I3_15_O O=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L12_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=R12_LUT4_I3_16_O_LUT4_I2_O I2=R12_LUT4_I3_16_O_LUT4_I2_1_O I3=L12_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_4_I2_LUT4_O_I0 I1=L12_LUT4_I3_4_I2_LUT4_O_I1 I2=L12_LUT4_I3_4_I2_LUT4_O_I2 I3=L12_LUT4_I3_4_I2_LUT4_O_I3 O=L12_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I3_10_I2_LUT4_O_I3 I1=R12_LUT4_I3_16_O_LUT4_I2_O I2=L12_LUT4_I3_10_I1_LUT4_O_I0 I3=L12_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I3 O=L12_LUT4_I3_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_16_O_LUT4_I2_1_O O=L12_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_16_O_LUT4_I2_2_O I3=L12_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3 O=L12_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_O I1=L12_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_17_O_LUT4_I2_O I3=L12_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_14_O I1=R12_LUT4_I3_15_O I2=R12_LUT4_I3_13_O I3=R12_LUT4_I3_12_O O=L12_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L12_LUT4_I3_4_I2_LUT4_O_I2 I1=L12_LUT4_I3_4_I2_LUT4_O_I3 I2=L12_LUT4_I3_18_I2_LUT4_O_I2 I3=L12_LUT4_I3_18_I2_LUT4_O_I1 O=L12_LUT4_I3_10_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_O I1=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_16_O_LUT4_I2_2_O O=L12_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_15_O I1=R12_LUT4_I3_14_O I2=R12_LUT4_I3_13_O I3=R12_LUT4_I3_12_O O=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_15_O I1=R12_LUT4_I3_14_O I2=R12_LUT4_I3_12_O I3=R12_LUT4_I3_13_O O=L12_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_16_O_LUT4_I2_1_O I1=L12_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_17_O_LUT4_I2_O I3=L12_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_15_O I1=R12_LUT4_I3_13_O I2=R12_LUT4_I3_12_O I3=R12_LUT4_I3_14_O O=L12_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_15_O I1=R12_LUT4_I3_14_O I2=R12_LUT4_I3_13_O I3=R12_LUT4_I3_12_O O=L12_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L12_LUT4_I3_5_I0 I1=L12_LUT4_I3_5_I1 I2=L12_LUT4_I3_5_I2 I3=L12(31) O=R13_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L12_LUT4_I3_5_I0_LUT4_O_I0 I1=L12_LUT4_I3_5_I0_LUT4_O_I1 I2=L12_LUT4_I3_5_I0_LUT4_O_I2 I3=L12_LUT4_I3_2_I1_LUT4_O_I3 O=L12_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L12_LUT4_I3_2_I1_LUT4_O_I3 I1=L12_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I1 I2=L12_LUT4_I3_2_I1_LUT4_O_I2 I3=L12_LUT4_I3_19_I2_LUT4_O_I2 O=L12_LUT4_I3_5_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_40_O_LUT4_I2_1_O I3=L12_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3 I3=R12_LUT4_I3_40_O_LUT4_I2_O O=L12_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L12_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0 I1=L12_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_41_O I3=R12_LUT4_I3_40_O O=L12_LUT4_I3_5_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R12_LUT4_I3_39_O I1=R12_LUT4_I3_38_O I2=R12_LUT4_I3_36_O I3=R12_LUT4_I3_37_O O=L12_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_40_O_LUT4_I2_2_O O=L12_LUT4_I3_5_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_38_O I1=R12_LUT4_I3_39_O I2=R12_LUT4_I3_37_O I3=R12_LUT4_I3_36_O O=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_41_O_LUT4_I2_O I1=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2 I2=L12_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_40_O_LUT4_I2_2_O O=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_39_O I1=R12_LUT4_I3_38_O I2=R12_LUT4_I3_37_O I3=R12_LUT4_I3_36_O O=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_5_I1_LUT4_O_I1 I2=L12_LUT4_I3_5_I1_LUT4_O_I2 I3=L12_LUT4_I3_5_I1_LUT4_O_I3 O=L12_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_41_O_LUT4_I2_O O=L12_LUT4_I3_5_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_39_O I1=R12_LUT4_I3_38_O I2=R12_LUT4_I3_37_O I3=R12_LUT4_I3_36_O O=L12_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_38_O I1=R12_LUT4_I3_36_O I2=R12_LUT4_I3_37_O I3=R12_LUT4_I3_39_O O=L12_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_1_O I1=L12_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_40_O_LUT4_I2_2_O I3=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_38_O I1=R12_LUT4_I3_37_O I2=R12_LUT4_I3_39_O I3=R12_LUT4_I3_36_O O=L12_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_2_O I1=L12_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_19_I1_LUT4_O_I1 I3=L12_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_5_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R12_LUT4_I3_39_O I1=R12_LUT4_I3_38_O I2=R12_LUT4_I3_37_O I3=R12_LUT4_I3_36_O O=L12_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_41_O_LUT4_I2_O I3=L12_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0 I2=R12_LUT4_I3_40_O_LUT4_I2_1_O I3=L12_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_5_I2 I2=L12_LUT4_I3_2_I2_LUT4_O_I2 I3=L12_LUT4_I3_19_I1_LUT4_O_I3 O=L12_LUT4_I3_19_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_5_I2_LUT4_O_I2 I3=L12_LUT4_I3_5_I2_LUT4_O_I3 O=L12_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_O I1=L12_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_40_O_LUT4_I2_2_O I3=L12_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 O=L12_LUT4_I3_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_39_O I1=R12_LUT4_I3_37_O I2=R12_LUT4_I3_36_O I3=R12_LUT4_I3_38_O O=L12_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_40_O_LUT4_I2_1_O I1=L12_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_41_O_LUT4_I2_O I3=L12_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_39_O I1=R12_LUT4_I3_38_O I2=R12_LUT4_I3_37_O I3=R12_LUT4_I3_36_O O=L12_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_6_I0 I1=L12_LUT4_I3_6_I1 I2=L12_LUT4_I3_6_I2 I3=L12(32) O=R13_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L12_LUT4_I3_6_I0_LUT4_O_I0 I1=L12_LUT4_I3_3_I1 I2=L12_LUT4_I3_6_I0_LUT4_O_I2 I3=L12_LUT4_I3_6_I0_LUT4_O_I3 O=L12_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 I1=R12_LUT4_I3_47_O_LUT4_I2_O I2=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2 I3=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I3 O=L12_LUT4_I3_6_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R12_LUT4_I3_44_O I1=R12_LUT4_I3_45_O I2=R12_LUT4_I3_43_O I3=R12_LUT4_I3_42_O O=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_2_O I1=L12_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_46_O_LUT4_I2_O I3=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2 O=L12_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_45_O I1=R12_LUT4_I3_44_O I2=R12_LUT4_I3_43_O I3=R12_LUT4_I3_42_O O=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_11_I1_LUT4_I1_I3_LUT4_O_I0 I1=R12_LUT4_I3_46_O_LUT4_I2_O I2=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_1_O O=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_45_O I1=R12_LUT4_I3_44_O I2=R12_LUT4_I3_43_O I3=R12_LUT4_I3_42_O O=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_1_O I1=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2 I2=R12_LUT4_I3_46_O_LUT4_I2_O I3=L12_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_46_O_LUT4_I2_2_O I3=L12_LUT4_I3_11_I1_LUT4_I1_I3_LUT4_O_I0 O=L12_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_44_O I1=R12_LUT4_I3_43_O I2=R12_LUT4_I3_45_O I3=R12_LUT4_I3_42_O O=L12_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_3_I2_LUT4_O_I1 I3=R12_LUT4_I3_47_O_LUT4_I2_O O=L12_LUT4_I3_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_1_O O=L12_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_1_O I1=L12_LUT4_I3_6_I1_LUT4_O_I1 I2=L12_LUT4_I3_6_I1_LUT4_O_I2 I3=L12_LUT4_I3_6_I1_LUT4_O_I3 O=L12_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R12_LUT4_I3_45_O I1=R12_LUT4_I3_44_O I2=R12_LUT4_I3_43_O I3=R12_LUT4_I3_42_O O=L12_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_2_O O=L12_LUT4_I3_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_11_I1_LUT4_I1_I2_LUT4_O_I2 I2=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_O O=L12_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_45_O I1=R12_LUT4_I3_43_O I2=R12_LUT4_I3_44_O I3=R12_LUT4_I3_42_O O=L12_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R12_LUT4_I3_46_O_LUT4_I2_1_O O=L12_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_2_O I1=L12_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_46_O_LUT4_I2_O I3=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=L12_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_6_I2_LUT4_O_I1 I2=L12_LUT4_I3_6_I2_LUT4_O_I2 I3=L12_LUT4_I3_6_I2_LUT4_O_I3 O=L12_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_3_I2_LUT4_O_I1 I3=R12_LUT4_I3_46_O_LUT4_I2_2_O O=L12_LUT4_I3_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_46_O_LUT4_I2_1_O O=L12_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_46_O_LUT4_I2_O I3=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_11_I2_LUT4_O_I1 O=L12_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_47_O_LUT4_I2_O I1=L12_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I2 I2=R12_LUT4_I3_46_O_LUT4_I2_2_O I3=L12_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 O=L12_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_46_O_LUT4_I2_1_O I1=L12_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 I2=R12_LUT4_I3_46_O_LUT4_I2_O I3=L12_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 O=L12_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I0 I1=L12_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_46_O_LUT4_I2_1_O I3=R12_LUT4_I3_46_O_LUT4_I2_2_O O=L12_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=R12_LUT4_I3_45_O I1=R12_LUT4_I3_44_O I2=R12_LUT4_I3_42_O I3=R12_LUT4_I3_43_O O=L12_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_45_O I1=R12_LUT4_I3_43_O I2=R12_LUT4_I3_42_O I3=R12_LUT4_I3_44_O O=L12_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L12_LUT4_I3_7_I0 I1=L12_LUT4_I3_7_I1 I2=L12_LUT4_I3_7_I2 I3=L12(25) O=R13_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L12_LUT4_I3_7_I0_LUT4_O_I0 I1=L12_LUT4_I3_7_I0_LUT4_O_I1 I2=L12_LUT4_I3_7_I0_LUT4_O_I2 I3=L12_LUT4_I3_7_I0_LUT4_O_I3 O=L12_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1 I2=L12_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2 I3=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2 O=L12_LUT4_I3_7_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I3_O I3=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_2_O I1=L12_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I2_1_O I3=L12_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_3_O I1=R12_LUT4_I3_2_O I2=R12_LUT4_I3_5_O I3=R12_LUT4_I3_4_O O=L12_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_14_I1_LUT4_O_I2 I3=L12_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_7_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I3_O I1=L12_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 I3=R12_LUT4_I3_O_LUT4_I2_2_O O=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_5_O I1=R12_LUT4_I3_3_O I2=R12_LUT4_I3_2_O I3=R12_LUT4_I3_4_O O=L12_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=R12_LUT4_I3_2_O I2=L12_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R12_LUT4_I3_O_LUT4_I3_O O=L12_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I1=R12_LUT4_I3_O_LUT4_I2_1_O I2=R12_LUT4_I3_O_LUT4_I2_2_O I3=L12_LUT4_I3_7_I1_LUT4_O_I2_LUT4_I2_I1 O=L12_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 I3=R12_LUT4_I3_O_LUT4_I3_O O=L12_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_2_O I1=R12_LUT4_I3_4_O I2=R12_LUT4_I3_3_O I3=R12_LUT4_I3_5_O O=L12_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2 I3=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_7_I1_LUT4_O_I2_LUT4_I2_O O=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I3_O I3=L12_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I0 O=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_7_I1 I2=L12_LUT4_I3_7_I1_LUT4_I1_I2 I3=R12_LUT4_I3_O_LUT4_I2_O O=L12_LUT4_I3_7_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_5_O I1=R12_LUT4_I3_4_O I2=R12_LUT4_I3_3_O I3=R12_LUT4_I3_2_O O=L12_LUT4_I3_7_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_7_I1_LUT4_O_I1 I2=L12_LUT4_I3_7_I1_LUT4_O_I2 I3=R12_LUT4_I3_O_LUT4_I3_O O=L12_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_2_O I1=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I2_1_O I3=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_5_O I1=R12_LUT4_I3_4_O I2=R12_LUT4_I3_2_O I3=R12_LUT4_I3_3_O O=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_4_O I1=R12_LUT4_I3_3_O I2=R12_LUT4_I3_2_O I3=R12_LUT4_I3_5_O O=L12_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_7_I1_LUT4_O_I2_LUT4_I2_I1 I2=L12_LUT4_I3_7_I1_LUT4_O_I2 I3=R12_LUT4_I3_O_LUT4_I2_1_O O=L12_LUT4_I3_7_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 I2=L12_LUT4_I3_7_I1_LUT4_O_I2 I3=R12_LUT4_I3_O_LUT4_I2_2_O O=L12_LUT4_I3_7_I1_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_7_I1_LUT4_O_I2_LUT4_I2_1_O I2=L12_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I3=R12_LUT4_I3_O_LUT4_I2_1_O O=L12_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_4_O I1=R12_LUT4_I3_2_O I2=R12_LUT4_I3_3_O I3=R12_LUT4_I3_5_O O=L12_LUT4_I3_7_I1_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_5_O I1=R12_LUT4_I3_4_O I2=R12_LUT4_I3_3_O I3=R12_LUT4_I3_2_O O=L12_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_12_I2 I2=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_I2_O I3=L12_LUT4_I3_7_I2_LUT4_O_I3 O=L12_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I2_O I3=L12_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I0 O=L12_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_7_I1_LUT4_I1_I2 I3=R12_LUT4_I3_O_LUT4_I3_O O=L12_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L12_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I1=R12_LUT4_I3_O_LUT4_I2_2_O I2=R12_LUT4_I3_O_LUT4_I2_1_O I3=L12_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I3_8_I0 I1=L12_LUT4_I3_8_I1 I2=L12_LUT4_I3_8_I2 I3=L12(2) O=R13_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L12_LUT4_I1_6_I3_LUT4_O_I1 I1=L12_LUT4_I3_8_I1 I2=L12_LUT4_I1_4_I2_LUT4_O_I2 I3=L12_LUT4_I1_4_I2_LUT4_O_I3 O=L12_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_8_I1_LUT4_O_I2 I3=L12_LUT4_I3_8_I1_LUT4_O_I3 O=L12_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_O I1=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_22_O_LUT4_I2_1_O I3=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_20_O I1=R12_LUT4_I3_21_O I2=R12_LUT4_I3_19_O I3=R12_LUT4_I3_18_O O=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_21_O I1=R12_LUT4_I3_20_O I2=R12_LUT4_I3_19_O I3=R12_LUT4_I3_18_O O=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L12_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0 I1=R12_LUT4_I3_22_O_LUT4_I2_2_O I2=R12_LUT4_I3_23_O_LUT4_I2_O I3=L12_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_21_O I1=R12_LUT4_I3_20_O I2=R12_LUT4_I3_19_O I3=R12_LUT4_I3_18_O O=L12_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_20_O I1=R12_LUT4_I3_18_O I2=R12_LUT4_I3_19_O I3=R12_LUT4_I3_21_O O=L12_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I2=L12_LUT4_I3_8_I2_LUT4_O_I2 I3=L12_LUT4_I1_6_I3_LUT4_O_I2 O=L12_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I2=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 I3=R12_LUT4_I3_22_O_LUT4_I2_O O=L12_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_22_O_LUT4_I2_1_O O=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_2_O I1=L12_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 I2=R12_LUT4_I3_23_O_LUT4_I2_O I3=L12_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_22_O_LUT4_I2_1_O I1=L12_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_23_O_LUT4_I2_O O=L12_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_19_O I1=R12_LUT4_I3_20_O I2=R12_LUT4_I3_21_O I3=R12_LUT4_I3_18_O O=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_21_O I1=R12_LUT4_I3_20_O I2=R12_LUT4_I3_19_O I3=R12_LUT4_I3_18_O O=L12_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L12_LUT4_I3_9_I0 I1=L12_LUT4_I3_9_I1 I2=L12_LUT4_I3_9_I2 I3=L12(3) O=R13_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_12_I1_LUT4_O_I1_LUT4_I2_O I2=L12_LUT4_I3_9_I0_LUT4_O_I2 I3=L12_LUT4_I3_9_I0_LUT4_O_I3 O=L12_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L12_LUT4_I3_7_I2_LUT4_O_I3 I1=L12_LUT4_I3_7_I1_LUT4_I1_O I2=L12_LUT4_I3_9_I2_LUT4_O_I2 I3=L12_LUT4_I3_9_I2_LUT4_O_I3 O=L12_LUT4_I3_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_7_I0_LUT4_O_I3 I2=L12_LUT4_I3_7_I0_LUT4_O_I1 I3=L12_LUT4_I3_7_I0_LUT4_O_I2 O=L12_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=L12_LUT4_I3_12_I1 I1=L12_LUT4_I3_7_I2_LUT4_O_I3 I2=L12_LUT4_I3_9_I2_LUT4_O_I2 I3=L12_LUT4_I3_9_I2_LUT4_O_I3 O=L12_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_2_O I1=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I2_1_O I3=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_O_LUT4_I2_1_O I3=L12_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_5_O I1=R12_LUT4_I3_4_O I2=R12_LUT4_I3_3_O I3=R12_LUT4_I3_2_O O=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R12_LUT4_I3_5_O I1=R12_LUT4_I3_3_O I2=R12_LUT4_I3_4_O I3=R12_LUT4_I3_2_O O=L12_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_O_LUT4_I2_O I1=L12_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 I3=R12_LUT4_I3_O_LUT4_I3_O O=L12_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_4_O I1=R12_LUT4_I3_5_O I2=R12_LUT4_I3_3_O I3=R12_LUT4_I3_2_O O=L12_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R12_LUT4_I3_3_O I1=R12_LUT4_I3_4_O I2=R12_LUT4_I3_5_O I3=R12_LUT4_I3_2_O O=L12_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L12_LUT4_I3_I0_LUT4_O_I0 I1=L12_LUT4_I3_I0_LUT4_O_I1 I2=R12_LUT4_I3_29_O I3=R12_LUT4_I3_28_O O=L12_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R12_LUT4_I3_27_O I1=R12_LUT4_I3_24_O I2=R12_LUT4_I3_25_O I3=R12_LUT4_I3_26_O O=L12_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_26_O I1=R12_LUT4_I3_24_O I2=R12_LUT4_I3_25_O I3=R12_LUT4_I3_27_O O=L12_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L12_LUT4_I3_I1_LUT4_O_I0 I1=L12_LUT4_I3_I1_LUT4_O_I1 I2=L12_LUT4_I3_I1_LUT4_O_I2 I3=L12_LUT4_I3_I1_LUT4_O_I3 O=L12_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=R12_LUT4_I3_28_O_LUT4_I2_2_O I1=L12_LUT4_I3_I0_LUT4_O_I1 I2=L12_LUT4_I1_5_I2_LUT4_O_I2 I3=L12_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I3 O=L12_LUT4_I3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L12_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 I1=L12_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_28_O I3=R12_LUT4_I3_29_O O=L12_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=L12_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I3 I1=L12_LUT4_I3_I0_LUT4_O_I1 I2=L12_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1 I3=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_28_O_LUT4_I2_2_O I1=L12_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 O=L12_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L12_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2 I3=L12_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 O=L12_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 I1=L12_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=L12_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_28_O_LUT4_I2_2_O O=L12_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I3 I1=L12_LUT4_I3_I0_LUT4_O_I0 I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_26_O I1=R12_LUT4_I3_27_O I2=R12_LUT4_I3_25_O I3=R12_LUT4_I3_24_O O=L12_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I3 I1=L12_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=R12_LUT4_I3_28_O_LUT4_I2_1_O I3=L12_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=L12_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_25_O I1=R12_LUT4_I3_24_O I2=R12_LUT4_I3_27_O I3=R12_LUT4_I3_26_O O=L12_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R12_LUT4_I3_27_O I1=R12_LUT4_I3_26_O I2=R12_LUT4_I3_25_O I3=R12_LUT4_I3_24_O O=L12_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L12_LUT4_I3_1_I2 I1=L12_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I2=L12_LUT4_I3_I2_LUT4_O_I2 I3=L12_LUT4_I1_2_I3 O=L12_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I2=R12_LUT4_I3_28_O_LUT4_I2_2_O I3=L12_LUT4_I1_2_I3_LUT4_O_I2 O=L12_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L12_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L12_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R12_LUT4_I3_28_O_LUT4_I2_1_O O=L12_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L12_LUT4_I1_2_I3_LUT4_O_I3 I1=L12_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L12_LUT4_I3_I0_LUT4_O_I0 I3=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L12_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R12_LUT4_I3_24_O I1=R12_LUT4_I3_26_O I2=R12_LUT4_I3_25_O I3=R12_LUT4_I3_27_O O=L12_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt ff CQZ=L12(1) D=R11(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(2) D=R11(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(11) D=R11(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(12) D=R11(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(13) D=R11(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(14) D=R11(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(15) D=R11(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(16) D=R11(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(17) D=R11(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(18) D=R11(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(19) D=R11(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(20) D=R11(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(3) D=R11(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(21) D=R11(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(22) D=R11(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(23) D=R11(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(24) D=R11(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(25) D=R11(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(26) D=R11(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(27) D=R11(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(28) D=R11(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(29) D=R11(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(30) D=R11(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(4) D=R11(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(31) D=R11(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(32) D=R11(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(5) D=R11(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(6) D=R11(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(7) D=R11(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(8) D=R11(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(9) D=R11(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L12(10) D=R11(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:185.1-186.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L13(1) I2=L13_LUT4_I1_I2 I3=L13_LUT4_I1_I3 O=R14_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=L13(4) I2=L13_LUT4_I1_1_I2 I3=L13_LUT4_I1_1_I3 O=R14_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L13_LUT4_I2_1_I3_LUT4_O_I3 I1=L13_LUT4_I1_1_I2_LUT4_O_I1 I2=L13_LUT4_I1_1_I2_LUT4_O_I2 I3=L13_LUT4_I1_1_I2_LUT4_O_I3 O=L13_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_29_O_LUT4_I2_O O=L13_LUT4_I1_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I1=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_29_O I3=R13_LUT4_I3_28_O O=L13_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=R13_LUT4_I3_27_O I1=R13_LUT4_I3_26_O I2=R13_LUT4_I3_25_O I3=R13_LUT4_I3_24_O O=L13_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R13_LUT4_I3_29_O_LUT4_I2_O I1=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_28_O_LUT4_I2_2_O O=L13_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_26_O I1=R13_LUT4_I3_24_O I2=R13_LUT4_I3_25_O I3=R13_LUT4_I3_27_O O=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_27_O I1=R13_LUT4_I3_24_O I2=R13_LUT4_I3_25_O I3=R13_LUT4_I3_26_O O=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_O I1=L13_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2 I2=L13_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_28_O_LUT4_I2_1_O O=L13_LUT4_I1_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_25_O I1=R13_LUT4_I3_24_O I2=R13_LUT4_I3_27_O I3=R13_LUT4_I3_26_O O=L13_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_1_I3_LUT4_O_I1 I2=L13_LUT4_I1_1_I3_LUT4_O_I2 I3=L13_LUT4_I1_1_I3_LUT4_O_I3 O=L13_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_28_O_LUT4_I2_2_O O=L13_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_28_O_LUT4_I2_O O=L13_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_1_O I1=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R13_LUT4_I3_29_O_LUT4_I2_O I3=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_24_O I1=R13_LUT4_I3_26_O I2=R13_LUT4_I3_25_O I3=R13_LUT4_I3_27_O O=L13_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_28_O_LUT4_I2_1_O O=L13_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_29_O_LUT4_I2_O I3=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I0 O=L13_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_O I1=L13_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R13_LUT4_I3_28_O_LUT4_I2_2_O I3=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_27_O I1=R13_LUT4_I3_26_O I2=R13_LUT4_I3_25_O I3=R13_LUT4_I3_24_O O=L13_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I0 I1=R13_LUT4_I3_28_O_LUT4_I2_2_O I2=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_27_O I1=R13_LUT4_I3_26_O I2=R13_LUT4_I3_25_O I3=R13_LUT4_I3_24_O O=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_1_O I1=L13_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=L13_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_29_O_LUT4_I2_O O=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_O I1=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R13_LUT4_I3_28_O_LUT4_I2_2_O I3=L13_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_28_O_LUT4_I2_O O=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_1_O I1=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_29_O_LUT4_I2_O I3=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_27_O I1=R13_LUT4_I3_26_O I2=R13_LUT4_I3_25_O I3=R13_LUT4_I3_24_O O=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L13(14) I2=L13_LUT4_I1_2_I2 I3=L13_LUT4_I1_2_I3 O=R14_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L13_LUT4_I1_2_I2_LUT4_O_I0 I1=R13_LUT4_I3_5_O_LUT4_I2_O I2=L13_LUT4_I1_2_I2_LUT4_O_I2 I3=L13_LUT4_I1_2_I2_LUT4_O_I3 O=L13_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_3_O I1=R13_LUT4_I3_2_O I2=R13_LUT4_I3_1_O I3=R13_LUT4_I3_O O=L13_LUT4_I1_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_1_O I1=L13_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2 I2=L13_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_5_O_LUT4_I2_O O=L13_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_2_O I1=R13_LUT4_I3_1_O I2=R13_LUT4_I3_3_O I3=R13_LUT4_I3_O O=L13_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_4_O_LUT4_I2_2_O O=L13_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_4_O_LUT4_I2_O O=L13_LUT4_I1_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_1_O I1=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_4_O_LUT4_I2_2_O I3=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_3_O I1=R13_LUT4_I3_2_O I2=R13_LUT4_I3_1_O I3=R13_LUT4_I3_O O=L13_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_2_I3_LUT4_O_I1 I2=L13_LUT4_I1_2_I3_LUT4_O_I2 I3=L13_LUT4_I2_3_I3_LUT4_O_I0 O=L13_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_7_I1_LUT4_O_I0 I2=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 I3=L13_LUT4_I3_7_I1_LUT4_O_I3 O=L13_LUT4_I1_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I1_2_I2_LUT4_O_I0 I3=R13_LUT4_I3_4_O_LUT4_I2_O O=L13_LUT4_I1_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I3 I3=R13_LUT4_I3_4_O_LUT4_I2_1_O O=L13_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_5_O_LUT4_I2_O I1=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_4_O_LUT4_I2_2_O O=L13_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13(18) I2=L13_LUT4_I1_3_I2 I3=L13_LUT4_I1_3_I3 O=R14_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=L13_LUT4_I1_3_I2_LUT4_O_I0 I1=L13_LUT4_I1_3_I2_LUT4_O_I1 I2=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_I2_O I3=L13_LUT4_I1_3_I2_LUT4_O_I3 O=L13_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I1 I2=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2 I3=L13_LUT4_I3_10_I0_LUT4_O_I2 O=L13_LUT4_I1_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_1_O I1=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_23_O_LUT4_I2_O I3=L13_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_21_O I1=R13_LUT4_I3_20_O I2=R13_LUT4_I3_19_O I3=R13_LUT4_I3_18_O O=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_O I1=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_22_O_LUT4_I2_2_O I3=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_21_O I1=R13_LUT4_I3_20_O I2=R13_LUT4_I3_19_O I3=R13_LUT4_I3_18_O O=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I1_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_O I1=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_22_O_LUT4_I2_1_O I3=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_23_O_LUT4_I2_O I1=L13_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_22_O_LUT4_I2_2_O I3=L13_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 I1=R13_LUT4_I3_22_O_LUT4_I2_2_O I2=L13_LUT4_I1_3_I2_LUT4_O_I3 I3=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_I2_I3 O=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I1 I2=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_22_O_LUT4_I2_O O=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_22_O_LUT4_I2_O O=L13_LUT4_I1_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_3_I2_LUT4_O_I0 I3=R13_LUT4_I3_22_O_LUT4_I2_1_O O=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_23_O_LUT4_I2_O I1=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I2=R13_LUT4_I3_22_O_LUT4_I2_2_O I3=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1 O=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_21_O I1=R13_LUT4_I3_20_O I2=R13_LUT4_I3_19_O I3=R13_LUT4_I3_18_O O=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I1_LUT4_O_I3 I2=L13_LUT4_I3_10_I1 I3=L13_LUT4_I1_3_I3_LUT4_O_I3 O=L13_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_3_I2_LUT4_O_I2 O=L13_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_O I1=L13_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_22_O_LUT4_I2_1_O I3=L13_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_23_O_LUT4_I2_O I1=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_22_O_LUT4_I2_2_O I3=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_21_O I1=R13_LUT4_I3_18_O I2=R13_LUT4_I3_19_O I3=R13_LUT4_I3_20_O O=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_20_O I1=R13_LUT4_I3_19_O I2=R13_LUT4_I3_18_O I3=R13_LUT4_I3_21_O O=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L13(23) I2=L13_LUT4_I1_4_I2 I3=L13_LUT4_I1_4_I3 O=R14_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_4_I2_LUT4_O_I1 I2=L13_LUT4_I1_4_I2_LUT4_O_I2 I3=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O O=L13_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_1_O I1=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I3 I2=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_41_O_LUT4_I2_O O=L13_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_40_O_LUT4_I2_2_O O=L13_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_37_O I1=R13_LUT4_I3_38_O I2=R13_LUT4_I3_39_O I3=R13_LUT4_I3_36_O O=L13_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_40_O_LUT4_I2_1_O O=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3 I1=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2 I2=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I2 I3=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3 O=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_1_O I1=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_41_O_LUT4_I2_O I3=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I1=R13_LUT4_I3_41_O_LUT4_I2_O I2=R13_LUT4_I3_40_O_LUT4_I2_2_O I3=L13_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I1_4_I3_LUT4_O_I0 I1=L13_LUT4_I1_4_I3_LUT4_O_I1 I2=L13_LUT4_I1_4_I3_LUT4_O_I2 I3=L13_LUT4_I1_4_I3_LUT4_O_I3 O=L13_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=L13_LUT4_I3_2_I2_LUT4_O_I2 I1=L13_LUT4_I3_2_I2_LUT4_O_I1 I2=L13_LUT4_I3_2_I2_LUT4_O_I3 I3=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O O=L13_LUT4_I1_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_1_I0_LUT4_O_I2 I3=R13_LUT4_I3_40_O_LUT4_I2_O O=L13_LUT4_I1_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_40_O_LUT4_I2_1_O I3=L13_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L13_LUT4_I3_2_I0_LUT4_O_I1 I1=R13_LUT4_I3_40_O_LUT4_I2_2_O I2=R13_LUT4_I3_41_O_LUT4_I2_O I3=L13_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_8_I2_LUT4_O_I1 I1=L13_LUT4_I1_4_I2_LUT4_O_I1 I2=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=L13_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I1_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_41_O_LUT4_I2_O O=L13_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_1_O I1=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 I2=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_40_O_LUT4_I2_2_O O=L13_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13(27) I2=L13_LUT4_I1_5_I2 I3=L13_LUT4_I1_5_I3 O=R14_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_5_I2_LUT4_O_I1 I2=L13_LUT4_I1_5_I2_LUT4_O_I2 I3=L13_LUT4_I1_5_I2_LUT4_O_I3 O=L13_LUT4_I1_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I0 I1=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I1_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R13_LUT4_I3_16_O_LUT4_I2_1_O I2=R13_LUT4_I3_16_O_LUT4_I2_O I3=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_13_O I1=R13_LUT4_I3_12_O I2=R13_LUT4_I3_15_O I3=R13_LUT4_I3_14_O O=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R13_LUT4_I3_17_O_LUT4_I2_O I2=R13_LUT4_I3_16_O_LUT4_I2_2_O I3=L13_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_17_O_LUT4_I2_O I1=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_16_O_LUT4_I2_2_O I3=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_15_O I1=R13_LUT4_I3_14_O I2=R13_LUT4_I3_13_O I3=R13_LUT4_I3_12_O O=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_15_O I1=R13_LUT4_I3_13_O I2=R13_LUT4_I3_14_O I3=R13_LUT4_I3_12_O O=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_16_O_LUT4_I2_O O=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_15_O I1=R13_LUT4_I3_12_O I2=R13_LUT4_I3_13_O I3=R13_LUT4_I3_14_O O=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_16_O_LUT4_I2_2_O O=L13_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_O I1=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R13_LUT4_I3_17_O_LUT4_I2_O O=L13_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_I3_I1 I2=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_I3_I2 I3=L13_LUT4_I1_5_I2_LUT4_O_I3 O=L13_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_16_O_LUT4_I2_O I3=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R13_LUT4_I3_16_O_LUT4_I2_2_O I2=R13_LUT4_I3_17_O_LUT4_I2_O I3=L13_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I1_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R13_LUT4_I3_16_O_LUT4_I2_O I2=R13_LUT4_I3_16_O_LUT4_I2_1_O I3=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_15_O I1=R13_LUT4_I3_13_O I2=R13_LUT4_I3_12_O I3=R13_LUT4_I3_14_O O=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_17_O_LUT4_I2_O I1=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_16_O_LUT4_I2_2_O O=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_14_O I1=R13_LUT4_I3_13_O I2=R13_LUT4_I3_15_O I3=R13_LUT4_I3_12_O O=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_5_I3_LUT4_O_I1 I2=L13_LUT4_I1_5_I3_LUT4_O_I2 I3=L13_LUT4_I3_14_I1 O=L13_LUT4_I1_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I1_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2 I2=L13_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_16_O_LUT4_I2_O O=L13_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_15_O I1=R13_LUT4_I3_14_O I2=R13_LUT4_I3_13_O I3=R13_LUT4_I3_12_O O=L13_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_17_O_LUT4_I2_O I1=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R13_LUT4_I3_16_O_LUT4_I2_2_O I3=L13_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 O=L13_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_16_O_LUT4_I2_1_O O=L13_LUT4_I1_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_16_O_LUT4_I2_O O=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_17_O_LUT4_I2_O I1=L13_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3 I2=L13_LUT4_I3_14_I1_LUT4_O_I1_LUT4_I3_I1 I3=R13_LUT4_I3_16_O_LUT4_I2_2_O O=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_15_O I1=R13_LUT4_I3_14_O I2=R13_LUT4_I3_12_O I3=R13_LUT4_I3_13_O O=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_13_O I1=R13_LUT4_I3_14_O I2=R13_LUT4_I3_15_O I3=R13_LUT4_I3_12_O O=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L13(30) I2=L13_LUT4_I1_6_I2 I3=L13_LUT4_I1_6_I3 O=R14_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_6_I2_LUT4_O_I2 I3=L13_LUT4_I3_16_I0 O=L13_LUT4_I1_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2 I2=L13_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I3=L13_LUT4_I1_6_I2_LUT4_O_I2 O=L13_LUT4_I3_16_I2_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_35_O_LUT4_I2_O I1=R13_LUT4_I3_34_O_LUT4_I2_2_O I2=L13_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=L13_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2 I1=R13_LUT4_I3_35_O_LUT4_I2_O I2=L13_LUT4_I3_16_I0_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_34_O_LUT4_I2_1_O O=L13_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2 I1=R13_LUT4_I3_34_O_LUT4_I2_2_O I2=R13_LUT4_I3_34_O_LUT4_I2_1_O I3=L13_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_30_O I1=R13_LUT4_I3_32_O I2=R13_LUT4_I3_31_O I3=R13_LUT4_I3_33_O O=L13_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_2_O I1=L13_LUT4_I3_16_I2_LUT4_I0_I3_LUT4_O_I1 I2=R13_LUT4_I3_35_O_LUT4_I2_O I3=L13_LUT4_I3_16_I0_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_11_I1 I1=L13_LUT4_I1_6_I3_LUT4_O_I1 I2=L13_LUT4_I1_6_I3_LUT4_O_I2 I3=L13_LUT4_I1_6_I3_LUT4_O_I3 O=L13_LUT4_I1_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_34_O_LUT4_I2_2_O O=L13_LUT4_I1_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_11_I2_LUT4_O_I2_LUT4_I3_O I2=L13_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=R13_LUT4_I3_34_O_LUT4_I2_1_O O=L13_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_31_O I1=R13_LUT4_I3_32_O I2=R13_LUT4_I3_33_O I3=R13_LUT4_I3_30_O O=L13_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I1_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_2_O I1=L13_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2 I2=R13_LUT4_I3_34_O_LUT4_I2_O I3=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I1_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_35_O_LUT4_I2_O I1=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I0 I2=L13_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_34_O_LUT4_I2_1_O O=L13_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_2_O I1=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3 I2=R13_LUT4_I3_34_O_LUT4_I2_O I3=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1 O=L13_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_I2_LUT4_O_I1 I2=L13_LUT4_I1_I2_LUT4_O_I2 I3=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_I0_O O=L13_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I0 I2=R13_LUT4_I3_10_O_LUT4_I2_2_O I3=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_9_O I1=R13_LUT4_I3_7_O I2=R13_LUT4_I3_8_O I3=R13_LUT4_I3_6_O O=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_1_O I1=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I0 I3=R13_LUT4_I3_11_O_LUT4_I2_O O=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_1_O I1=L13_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I2=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_11_O_LUT4_I2_O O=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R13_LUT4_I3_10_O_LUT4_I2_O O=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_10_O_LUT4_I2_2_O O=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_9_O I1=R13_LUT4_I3_8_O I2=R13_LUT4_I3_7_O I3=R13_LUT4_I3_6_O O=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_10_O_LUT4_I2_2_O I3=L13_LUT4_I3_17_I2_LUT4_O_I3 O=L13_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_10_O_LUT4_I2_1_O O=L13_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I0 I2=R13_LUT4_I3_11_O_LUT4_I2_O I3=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_7_O I1=R13_LUT4_I3_8_O I2=R13_LUT4_I3_9_O I3=R13_LUT4_I3_6_O O=L13_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L13_LUT4_I1_I3_LUT4_O_I0 I1=L13_LUT4_I1_I3_LUT4_O_I1 I2=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I3=L13_LUT4_I3_17_I1 O=L13_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2 I3=L13_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3 O=L13_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=R13_LUT4_I3_11_O_LUT4_I2_O I3=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_1_O I1=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R13_LUT4_I3_10_O_LUT4_I2_2_O I3=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_1_O I1=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I0 I2=R13_LUT4_I3_10_O_LUT4_I2_2_O I3=L13_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_11_O_LUT4_I2_O O=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_9_O I1=R13_LUT4_I3_8_O I2=R13_LUT4_I3_7_O I3=R13_LUT4_I3_6_O O=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_9_O I1=R13_LUT4_I3_7_O I2=R13_LUT4_I3_6_O I3=R13_LUT4_I3_8_O O=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13(6) I3=L13_LUT4_I2_I3 O=R14_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13(11) I3=L13_LUT4_I2_1_I3 O=R14_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L13_LUT4_I2_4_I3_LUT4_O_I1 I1=L13_LUT4_I2_1_I3_LUT4_O_I1 I2=L13_LUT4_I2_1_I3_LUT4_O_I2 I3=L13_LUT4_I2_1_I3_LUT4_O_I3 O=L13_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_12_I2_LUT4_O_I1 O=L13_LUT4_I2_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_O I1=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_28_O_LUT4_I2_2_O I3=L13_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2 O=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_1_O I1=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_29_O_LUT4_I2_O O=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_26_O I1=R13_LUT4_I3_25_O I2=R13_LUT4_I3_24_O I3=R13_LUT4_I3_27_O O=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_29_O_LUT4_I2_O I1=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_28_O_LUT4_I2_2_O I3=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I2_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_27_O I1=R13_LUT4_I3_26_O I2=R13_LUT4_I3_24_O I3=R13_LUT4_I3_25_O O=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_29_O_LUT4_I2_O O=L13_LUT4_I2_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_28_O_LUT4_I2_O O=L13_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_1_O I1=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R13_LUT4_I3_28_O_LUT4_I2_2_O I3=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=L13_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_12_I2_LUT4_O_I2 O=L13_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_O I1=L13_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2 I2=R13_LUT4_I3_28_O_LUT4_I2_1_O I3=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_29_O_LUT4_I2_O I1=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_28_O_LUT4_I2_2_O O=L13_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_27_O I1=R13_LUT4_I3_25_O I2=R13_LUT4_I3_24_O I3=R13_LUT4_I3_26_O O=L13_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13(15) I3=L13_LUT4_I2_2_I3 O=R14_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_2_I3_LUT4_O_I1 I2=L13_LUT4_I2_2_I3_LUT4_O_I2 I3=L13_LUT4_I3_5_I0_LUT4_O_I3 O=L13_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2 I2=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I0 I3=L13_LUT4_I3_5_I1_LUT4_O_I2 O=L13_LUT4_I2_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13(25) I3=L13_LUT4_I2_3_I3 O=R14_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L13_LUT4_I2_3_I3_LUT4_O_I0 I1=L13_LUT4_I2_3_I3_LUT4_O_I1 I2=L13_LUT4_I2_3_I3_LUT4_O_I2 I3=L13_LUT4_I2_3_I3_LUT4_O_I3 O=L13_LUT4_I2_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110111
+.subckt LUT4 I0=L13_LUT4_I1_2_I3_LUT4_O_I2 I1=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I1 I2=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2 I3=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I3 O=L13_LUT4_I2_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I3 I3=R13_LUT4_I3_4_O_LUT4_I2_O O=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_5_O_LUT4_I2_O O=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_1_O I1=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_4_O_LUT4_I2_2_O I3=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_1_O I1=R13_LUT4_I3_2_O I2=R13_LUT4_I3_3_O I3=R13_LUT4_I3_O O=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_3_O I1=R13_LUT4_I3_1_O I2=R13_LUT4_I3_2_O I3=R13_LUT4_I3_O O=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_5_O_LUT4_I2_O I3=L13_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2 O=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_2_O I1=R13_LUT4_I3_3_O I2=R13_LUT4_I3_1_O I3=R13_LUT4_I3_O O=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_3_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_7_I2_LUT4_O_I2 I3=L13_LUT4_I3_7_I2_LUT4_O_I3 O=L13_LUT4_I2_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_5_O_LUT4_I2_O I1=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L13_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I3 I3=L13_LUT4_I2_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I2_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_4_O_LUT4_I2_1_O I3=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I2_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_7_I2_LUT4_O_I2 I3=L13_LUT4_I1_2_I3_LUT4_O_I2 O=L13_LUT4_I2_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_4_I1_LUT4_O_I3 I3=L13_LUT4_I3_7_I1_LUT4_O_I2 O=L13_LUT4_I2_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13(29) I3=L13_LUT4_I2_4_I3 O=R14_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L13_LUT4_I2_4_I3_LUT4_O_I0 I1=L13_LUT4_I2_4_I3_LUT4_O_I1 I2=L13_LUT4_I2_4_I3_LUT4_O_I2 I3=L13_LUT4_I2_4_I3_LUT4_O_I3 O=L13_LUT4_I2_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_12_I2_LUT4_O_I2 I2=L13_LUT4_I1_1_I2_LUT4_O_I1 I3=L13_LUT4_I2_1_I3_LUT4_O_I1 O=L13_LUT4_I2_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_1_I3_LUT4_O_I3 I3=L13_LUT4_I2_4_I3_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I2_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I0 I3=R13_LUT4_I3_28_O_LUT4_I2_O O=L13_LUT4_I2_4_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_28_O_LUT4_I2_1_O I3=L13_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=L13_LUT4_I2_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L13_LUT4_I1_1_I3_LUT4_O_I2 I1=L13_LUT4_I1_1_I3_LUT4_O_I1 I2=L13_LUT4_I3_12_I1_LUT4_O_I1 I3=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I2_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=L13_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=R13_LUT4_I3_28_O_LUT4_I2_1_O I2=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100001101
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_28_O_LUT4_I2_O O=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_27_O I1=R13_LUT4_I3_26_O I2=R13_LUT4_I3_25_O I3=R13_LUT4_I3_24_O O=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L13_LUT4_I2_4_I3_LUT4_O_I1_LUT4_O_I3 I1=L13_LUT4_I1_1_I3_LUT4_O_I2 I2=L13_LUT4_I2_1_I3_LUT4_O_I2 I3=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2 O=L13_LUT4_I2_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L13_LUT4_I2_I3_LUT4_O_I0 I1=L13_LUT4_I2_I3_LUT4_O_I1 I2=L13_LUT4_I2_I3_LUT4_O_I2 I3=L13_LUT4_I2_I3_LUT4_O_I3 O=L13_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=L13_LUT4_I3_11_I1_LUT4_O_I3 I1=L13_LUT4_I1_6_I3_LUT4_O_I1 I2=L13_LUT4_I3_11_I1_LUT4_O_I2 I3=L13_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L13_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L13_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=L13_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2 I2=R13_LUT4_I3_34_O_LUT4_I2_O I3=L13_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R13_LUT4_I3_33_O I1=R13_LUT4_I3_32_O I2=R13_LUT4_I3_31_O I3=R13_LUT4_I3_30_O O=L13_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_2_O I1=L13_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3 I2=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_34_O_LUT4_I2_1_O O=L13_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_1_O I1=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_11_I1_LUT4_O_I1 I3=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_32_O I1=R13_LUT4_I3_31_O I2=R13_LUT4_I3_33_O I3=R13_LUT4_I3_30_O O=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_1_O I1=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3 I3=R13_LUT4_I3_34_O_LUT4_I2_O O=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=R13_LUT4_I3_33_O I1=R13_LUT4_I3_31_O I2=R13_LUT4_I3_32_O I3=R13_LUT4_I3_30_O O=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_6_I3_LUT4_O_I3 I3=L13_LUT4_I3_16_I0_LUT4_O_I3 O=L13_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_35_O_LUT4_I2_O I1=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I0 I3=R13_LUT4_I3_34_O_LUT4_I2_O O=L13_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_I0_O I1=L13_LUT4_I3_I1 I2=L13_LUT4_I3_I2 I3=L13(10) O=R14_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=L13_LUT4_I3_1_I0 I1=L13_LUT4_I3_1_I1 I2=L13_LUT4_I3_1_I2 I3=L13(17) O=R14_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L13_LUT4_I3_10_I0 I1=L13_LUT4_I3_10_I1 I2=L13_LUT4_I3_10_I2 I3=L13(13) O=R14_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_I2_O I2=L13_LUT4_I3_10_I0_LUT4_O_I2 I3=L13_LUT4_I3_3_I0_LUT4_O_I1 O=L13_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_10_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_O I1=L13_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=R13_LUT4_I3_22_O_LUT4_I2_1_O O=L13_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_23_O_LUT4_I2_O I1=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I3 I2=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_22_O_LUT4_I2_2_O O=L13_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_3_I1_LUT4_O_I3 I1=L13_LUT4_I3_10_I1_LUT4_O_I1 I2=L13_LUT4_I3_3_I1_LUT4_O_I2 I3=L13_LUT4_I3_3_I1_LUT4_O_I1 O=L13_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_10_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_O I1=L13_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 I3=R13_LUT4_I3_23_O_LUT4_I2_O O=L13_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_1_O I1=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_22_O_LUT4_I2_2_O O=L13_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_10_I2_LUT4_O_I2 I3=L13_LUT4_I3_10_I2_LUT4_O_I3 O=L13_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_O I1=L13_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_22_O_LUT4_I2_2_O O=L13_LUT4_I3_10_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_19_O I1=R13_LUT4_I3_18_O I2=R13_LUT4_I3_21_O I3=R13_LUT4_I3_20_O O=L13_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_21_O I1=R13_LUT4_I3_19_O I2=R13_LUT4_I3_18_O I3=R13_LUT4_I3_20_O O=L13_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_1_O I1=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I3 I2=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_23_O_LUT4_I2_O O=L13_LUT4_I3_10_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_11_I0 I1=L13_LUT4_I3_11_I1 I2=L13_LUT4_I3_11_I2 I3=L13(16) O=R14_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_6_I3_LUT4_O_I3 I2=L13_LUT4_I1_6_I2 I3=L13_LUT4_I2_I3_LUT4_O_I2 O=L13_LUT4_I3_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_11_I1_LUT4_O_I1 I2=L13_LUT4_I3_11_I1_LUT4_O_I2 I3=L13_LUT4_I3_11_I1_LUT4_O_I3 O=L13_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_11_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_2_O I1=L13_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=L13_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_34_O_LUT4_I2_O O=L13_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I0 I1=R13_LUT4_I3_34_O_LUT4_I2_2_O I2=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=R13_LUT4_I3_31_O I1=R13_LUT4_I3_30_O I2=R13_LUT4_I3_33_O I3=R13_LUT4_I3_32_O O=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=R13_LUT4_I3_35_O_LUT4_I2_O O=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_32_O I1=R13_LUT4_I3_31_O I2=R13_LUT4_I3_30_O I3=R13_LUT4_I3_33_O O=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_16_I2_LUT4_O_I2 I3=R13_LUT4_I3_34_O_LUT4_I2_O O=L13_LUT4_I3_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3 I3=R13_LUT4_I3_35_O_LUT4_I2_O O=L13_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_11_I2 I2=L13_LUT4_I1_6_I3_LUT4_O_I2 I3=L13_LUT4_I1_6_I3_LUT4_O_I1 O=L13_LUT4_I3_16_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_1_O I1=R13_LUT4_I3_34_O_LUT4_I2_O I2=L13_LUT4_I3_11_I2_LUT4_O_I2 I3=L13_LUT4_I3_11_I2_LUT4_O_I3 O=L13_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R13_LUT4_I3_35_O_LUT4_I2_O I1=L13_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I3 I2=R13_LUT4_I3_34_O_LUT4_I2_O I3=L13_LUT4_I3_11_I2_LUT4_O_I2 O=L13_LUT4_I3_11_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_33_O I1=R13_LUT4_I3_32_O I2=R13_LUT4_I3_31_O I3=R13_LUT4_I3_30_O O=L13_LUT4_I3_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_O I1=L13_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_34_O_LUT4_I2_1_O I3=L13_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_11_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_2_O I1=L13_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I0 I3=R13_LUT4_I3_34_O_LUT4_I2_1_O O=L13_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_33_O I1=R13_LUT4_I3_32_O I2=R13_LUT4_I3_31_O I3=R13_LUT4_I3_30_O O=L13_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_33_O I1=R13_LUT4_I3_31_O I2=R13_LUT4_I3_30_O I3=R13_LUT4_I3_32_O O=L13_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L13_LUT4_I3_12_I0 I1=L13_LUT4_I3_12_I1 I2=L13_LUT4_I3_12_I2 I3=L13(19) O=R14_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I2_4_I3_LUT4_O_I2 I3=L13_LUT4_I2_4_I3_LUT4_O_I1 O=L13_LUT4_I3_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_12_I1_LUT4_O_I1 I2=L13_LUT4_I1_1_I3_LUT4_O_I1 I3=L13_LUT4_I3_12_I1_LUT4_O_I3 O=L13_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_28_O_LUT4_I2_1_O I3=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I0 O=L13_LUT4_I3_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_29_O_LUT4_I2_O O=L13_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_O I1=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_28_O_LUT4_I2_2_O I3=L13_LUT4_I2_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_27_O I1=R13_LUT4_I3_25_O I2=R13_LUT4_I3_26_O I3=R13_LUT4_I3_24_O O=L13_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I2_1_I3_LUT4_O_I2 O=L13_LUT4_I3_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_12_I2_LUT4_O_I1 I2=L13_LUT4_I3_12_I2_LUT4_O_I2 I3=L13_LUT4_I3_12_I2_LUT4_O_I3 O=L13_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_12_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_1_O I1=L13_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_28_O_LUT4_I2_2_O I3=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_26_O I1=R13_LUT4_I3_27_O I2=R13_LUT4_I3_25_O I3=R13_LUT4_I3_24_O O=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_O I1=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_29_O_LUT4_I2_O I3=L13_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_26_O I1=R13_LUT4_I3_25_O I2=R13_LUT4_I3_27_O I3=R13_LUT4_I3_24_O O=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_O I1=L13_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_28_O_LUT4_I2_2_O I3=L13_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=R13_LUT4_I3_29_O_LUT4_I2_O I2=R13_LUT4_I3_28_O_LUT4_I2_1_O I3=L13_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_25_O I1=R13_LUT4_I3_26_O I2=R13_LUT4_I3_27_O I3=R13_LUT4_I3_24_O O=L13_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L13_LUT4_I2_1_I3_LUT4_O_I3 I1=L13_LUT4_I1_1_I2_LUT4_O_I1 I2=L13_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_O I1=L13_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R13_LUT4_I3_29_O_LUT4_I2_O I3=L13_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2 O=L13_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_28_O_LUT4_I2_1_O I1=L13_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I2=L13_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_28_O_LUT4_I2_2_O O=L13_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_13_I0 I1=L13_LUT4_I3_13_I1 I2=L13_LUT4_I3_13_I2 I3=L13(20) O=R14_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_13_I0_LUT4_O_I2 I3=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_I0_O O=L13_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_13_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R13_LUT4_I3_10_O_LUT4_I2_2_O I3=L13_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I0 O=L13_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_1_O I1=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I0 I2=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_11_O_LUT4_I2_O O=L13_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_13_I1_LUT4_O_I2 I3=L13_LUT4_I1_I2_LUT4_O_I2 O=L13_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_13_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_11_O_LUT4_I2_O I3=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_1_O I1=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_10_O_LUT4_I2_2_O I3=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_I3_LUT4_O_I1 I2=L13_LUT4_I3_17_I2 I3=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O O=L13_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L13_LUT4_I3_14_I0 I1=L13_LUT4_I3_14_I1 I2=L13_LUT4_I3_14_I2 I3=L13(21) O=R14_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L13_LUT4_I3_5_I0_LUT4_O_I2 I1=L13_LUT4_I1_5_I2_LUT4_O_I2 I2=L13_LUT4_I3_5_I0_LUT4_O_I3 I3=L13_LUT4_I3_14_I0_LUT4_O_I3 O=L13_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L13_LUT4_I3_5_I1_LUT4_O_I3 I1=L13_LUT4_I1_5_I2_LUT4_O_I3 I2=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1 I3=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_14_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_2_O I1=L13_LUT4_I3_14_I1_LUT4_O_I1 I2=L13_LUT4_I3_14_I1_LUT4_O_I2 I3=L13_LUT4_I3_14_I1_LUT4_O_I3 O=L13_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I3_14_I1_LUT4_O_I1_LUT4_I3_I1 I2=R13_LUT4_I3_16_O_LUT4_I2_O I3=L13_LUT4_I3_14_I1_LUT4_O_I1 O=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_12_O I1=R13_LUT4_I3_14_O I2=R13_LUT4_I3_13_O I3=R13_LUT4_I3_15_O O=L13_LUT4_I3_14_I1_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_15_O I1=R13_LUT4_I3_14_O I2=R13_LUT4_I3_13_O I3=R13_LUT4_I3_12_O O=L13_LUT4_I3_14_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_14_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R13_LUT4_I3_16_O_LUT4_I2_O I3=L13_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_17_O_LUT4_I2_O I1=L13_LUT4_I3_14_I1_LUT4_O_I1_LUT4_I3_I1 I2=R13_LUT4_I3_16_O_LUT4_I2_2_O I3=L13_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_16_O_LUT4_I2_O O=L13_LUT4_I3_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3 I2=L13_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_17_O_LUT4_I2_O O=L13_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_14_O I1=R13_LUT4_I3_12_O I2=R13_LUT4_I3_13_O I3=R13_LUT4_I3_15_O O=L13_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L13_LUT4_I3_5_I2_LUT4_O_I2 I1=L13_LUT4_I3_14_I1_LUT4_O_I2 I2=L13_LUT4_I1_5_I3_LUT4_O_I1 I3=L13_LUT4_I3_14_I2 O=L13_LUT4_I2_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_14_I2_LUT4_O_I2 I3=L13_LUT4_I3_14_I2_LUT4_O_I3 O=L13_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_17_O_LUT4_I2_O I1=L13_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I2=L13_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_16_O_LUT4_I2_2_O O=L13_LUT4_I3_14_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_14_O I1=R13_LUT4_I3_15_O I2=R13_LUT4_I3_13_O I3=R13_LUT4_I3_12_O O=L13_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_16_O_LUT4_I2_O O=L13_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_15_O I1=R13_LUT4_I3_14_O I2=R13_LUT4_I3_13_O I3=R13_LUT4_I3_12_O O=L13_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L13_LUT4_I3_6_I1_LUT4_O_I0_LUT4_I1_O I1=L13_LUT4_I3_15_I1 I2=L13_LUT4_I3_15_I2 I3=L13(22) O=R14_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_15_I1_LUT4_O_I1 I2=L13_LUT4_I3_9_I1_LUT4_O_I1 I3=L13_LUT4_I3_15_I1_LUT4_O_I3 O=L13_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2 O=L13_LUT4_I3_15_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R13_LUT4_I3_46_O_LUT4_I2_1_O I3=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 O=L13_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_2_O I1=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R13_LUT4_I3_47_O_LUT4_I2_O I3=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L13_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_15_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_1_O I1=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_47_O_LUT4_I2_O O=L13_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_46_O_LUT4_I2_2_O O=L13_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_15_I2_LUT4_O_I1 I2=L13_LUT4_I3_19_I1_LUT4_O_I1 I3=L13_LUT4_I3_9_I2_LUT4_O_I3 O=L13_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_15_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_47_O_LUT4_I2_O O=L13_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_46_O_LUT4_I2_1_O I3=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_16_I0 I1=L13_LUT4_I3_16_I1 I2=L13_LUT4_I3_16_I2 I3=L13(24) O=R14_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_16_I0_LUT4_O_I1 I2=L13_LUT4_I3_16_I0_LUT4_O_I2 I3=L13_LUT4_I3_16_I0_LUT4_O_I3 O=L13_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R13_LUT4_I3_35_O_LUT4_I2_O I1=L13_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_34_O_LUT4_I2_1_O I3=L13_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_16_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_32_O I1=R13_LUT4_I3_30_O I2=R13_LUT4_I3_31_O I3=R13_LUT4_I3_33_O O=L13_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_32_O I1=R13_LUT4_I3_33_O I2=R13_LUT4_I3_31_O I3=R13_LUT4_I3_30_O O=L13_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_2_O I1=L13_LUT4_I3_16_I0_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_34_O_LUT4_I2_O O=L13_LUT4_I3_16_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_33_O I1=R13_LUT4_I3_30_O I2=R13_LUT4_I3_31_O I3=R13_LUT4_I3_32_O O=L13_LUT4_I3_16_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L13_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I0 I1=L13_LUT4_I3_16_I0_LUT4_O_I1 I2=L13_LUT4_I3_16_I0_LUT4_O_I2 I3=L13_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_16_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_34_O_LUT4_I2_2_O O=L13_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_2_O I1=L13_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I3 I2=L13_LUT4_I3_16_I2_LUT4_I0_I3_LUT4_O_I1 I3=R13_LUT4_I3_35_O_LUT4_I2_O O=L13_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I2_I3_LUT4_O_I1 I1=L13_LUT4_I3_11_I1_LUT4_O_I3 I2=L13_LUT4_I3_11_I1_LUT4_O_I1 I3=L13_LUT4_I3_16_I1_LUT4_O_I3 O=L13_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=L13_LUT4_I3_16_I2 I1=L13_LUT4_I3_16_I2_LUT4_I0_I1 I2=L13_LUT4_I3_16_I0_LUT4_O_I3 I3=L13_LUT4_I3_16_I2_LUT4_I0_I3 O=L13_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L13_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1 I1=L13_LUT4_I3_16_I2_LUT4_I0_I3_LUT4_O_I1 I2=R13_LUT4_I3_34_O_LUT4_I2_1_O I3=L13_LUT4_I3_16_I2_LUT4_I0_I3_LUT4_O_I3 O=L13_LUT4_I3_16_I2_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R13_LUT4_I3_33_O I1=R13_LUT4_I3_32_O I2=R13_LUT4_I3_30_O I3=R13_LUT4_I3_31_O O=L13_LUT4_I3_16_I2_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_35_O_LUT4_I2_O I1=L13_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3 I2=L13_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I3 I3=R13_LUT4_I3_34_O_LUT4_I2_O O=L13_LUT4_I3_16_I2_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_16_I2_LUT4_O_I1 I2=L13_LUT4_I3_16_I2_LUT4_O_I2 I3=R13_LUT4_I3_34_O_LUT4_I2_1_O O=L13_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_35_O_LUT4_I2_O O=L13_LUT4_I3_16_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_34_O_LUT4_I2_2_O I1=L13_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_34_O_LUT4_I2_O I3=L13_LUT4_I3_16_I0_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_33_O I1=R13_LUT4_I3_32_O I2=R13_LUT4_I3_31_O I3=R13_LUT4_I3_30_O O=L13_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_35_O_LUT4_I2_O I1=L13_LUT4_I3_16_I2_LUT4_O_I2 I2=R13_LUT4_I3_34_O_LUT4_I2_1_O I3=L13_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_33_O I1=R13_LUT4_I3_32_O I2=R13_LUT4_I3_31_O I3=R13_LUT4_I3_30_O O=L13_LUT4_I3_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L13_LUT4_I3_17_I0 I1=L13_LUT4_I3_17_I1 I2=L13_LUT4_I3_17_I2 I3=L13(26) O=R14_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_I0_O I1=L13_LUT4_I3_I1_LUT4_O_I2 I2=L13_LUT4_I3_13_I1 I3=L13_LUT4_I3_I2_LUT4_O_I2 O=L13_LUT4_I3_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_17_I1_LUT4_O_I1 I2=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I3=L13_LUT4_I3_17_I1_LUT4_O_I3 O=L13_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L13_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I0 I1=R13_LUT4_I3_11_O_LUT4_I2_O I2=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I3=L13_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_17_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R13_LUT4_I3_6_O I1=R13_LUT4_I3_8_O I2=R13_LUT4_I3_7_O I3=R13_LUT4_I3_9_O O=L13_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_10_O_LUT4_I2_2_O O=L13_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I2 I2=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_10_O_LUT4_I2_O O=L13_LUT4_I3_17_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_17_I2_LUT4_O_I1 I2=R13_LUT4_I3_10_O_LUT4_I2_1_O I3=L13_LUT4_I3_17_I2_LUT4_O_I3 O=L13_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_10_O_LUT4_I2_O O=L13_LUT4_I3_17_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_2_O I1=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_11_O_LUT4_I2_O I3=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I0 O=L13_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_9_O I1=R13_LUT4_I3_8_O I2=R13_LUT4_I3_6_O I3=R13_LUT4_I3_7_O O=L13_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_9_O I1=R13_LUT4_I3_8_O I2=R13_LUT4_I3_7_O I3=R13_LUT4_I3_6_O O=L13_LUT4_I3_17_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L13_LUT4_I3_18_I0 I1=L13_LUT4_I3_18_I1 I2=L13_LUT4_I3_18_I2 I3=L13(28) O=R14_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_3_I0_LUT4_O_I0 I3=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_I2_O O=L13_LUT4_I3_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_10_I2 I2=L13_LUT4_I1_3_I3_LUT4_O_I3 I3=L13_LUT4_I3_3_I1 O=L13_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_3_I2_LUT4_O_I1 I3=L13_LUT4_I1_3_I2_LUT4_O_I3 O=L13_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L13_LUT4_I3_6_I1_LUT4_O_I0_LUT4_I1_O I1=L13_LUT4_I3_19_I1 I2=L13_LUT4_I3_19_I2 I3=L13(32) O=R14_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_19_I1_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I3 I3=L13_LUT4_I3_19_I1_LUT4_O_I3 O=L13_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_1_O I1=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I2=L13_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_19_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R13_LUT4_I3_47_O_LUT4_I2_O I3=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_6_I1_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I2 I3=L13_LUT4_I3_9_I2_LUT4_O_I3 O=L13_LUT4_I3_19_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_6_I2_LUT4_O_I2 I3=L13_LUT4_I3_9_I1_LUT4_O_I0 O=L13_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_1_O I1=R13_LUT4_I3_41_O_LUT4_I2_O I2=L13_LUT4_I3_1_I0_LUT4_O_I2 I3=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O O=L13_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R13_LUT4_I3_39_O I1=R13_LUT4_I3_38_O I2=R13_LUT4_I3_37_O I3=R13_LUT4_I3_36_O O=L13_LUT4_I3_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I1=L13_LUT4_I3_1_I1_LUT4_O_I1 I2=L13_LUT4_I3_1_I1_LUT4_O_I2 I3=L13_LUT4_I3_8_I1_LUT4_O_I2 O=L13_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_40_O_LUT4_I2_2_O I3=L13_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I3_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_2_I0_LUT4_O_I1 I2=R13_LUT4_I3_41_O_LUT4_I2_O I3=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_40_O_LUT4_I2_O O=L13_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_1_O I1=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_40_O_LUT4_I2_2_O I3=L13_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_2_I1_LUT4_O_I3 I2=L13_LUT4_I3_1_I2 I3=L13_LUT4_I1_4_I3_LUT4_O_I2 O=L13_LUT4_I1_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_41_O_LUT4_I2_O I1=L13_LUT4_I3_1_I2_LUT4_O_I1 I2=L13_LUT4_I3_1_I2_LUT4_O_I2 I3=L13_LUT4_I3_1_I2_LUT4_O_I3 O=L13_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_1_O I1=L13_LUT4_I3_1_I2_LUT4_O_I1 I2=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3 I3=R13_LUT4_I3_40_O_LUT4_I2_2_O O=L13_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_39_O I1=R13_LUT4_I3_38_O I2=R13_LUT4_I3_36_O I3=R13_LUT4_I3_37_O O=L13_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_2_O I1=L13_LUT4_I3_1_I0_LUT4_O_I2 I2=L13_LUT4_I3_8_I0_LUT4_O_I2 I3=L13_LUT4_I3_8_I0_LUT4_O_I3 O=L13_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_40_O_LUT4_I2_1_O I3=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_39_O I1=R13_LUT4_I3_37_O I2=R13_LUT4_I3_38_O I3=R13_LUT4_I3_36_O O=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_39_O I1=R13_LUT4_I3_38_O I2=R13_LUT4_I3_37_O I3=R13_LUT4_I3_36_O O=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L13_LUT4_I3_2_I0 I1=L13_LUT4_I3_2_I1 I2=L13_LUT4_I3_2_I2 I3=L13(31) O=R14_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L13_LUT4_I3_2_I0_LUT4_O_I0 I1=L13_LUT4_I3_2_I0_LUT4_O_I1 I2=R13_LUT4_I3_41_O I3=R13_LUT4_I3_40_O O=L13_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R13_LUT4_I3_39_O I1=R13_LUT4_I3_37_O I2=R13_LUT4_I3_36_O I3=R13_LUT4_I3_38_O O=L13_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_39_O I1=R13_LUT4_I3_38_O I2=R13_LUT4_I3_37_O I3=R13_LUT4_I3_36_O O=L13_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L13_LUT4_I1_4_I2_LUT4_O_I1 I1=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I2=L13_LUT4_I3_2_I1_LUT4_O_I2 I3=L13_LUT4_I3_2_I1_LUT4_O_I3 O=L13_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_40_O_LUT4_I2_1_O O=L13_LUT4_I3_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_38_O I1=R13_LUT4_I3_39_O I2=R13_LUT4_I3_37_O I3=R13_LUT4_I3_36_O O=L13_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_39_O I1=R13_LUT4_I3_38_O I2=R13_LUT4_I3_37_O I3=R13_LUT4_I3_36_O O=L13_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_2_I0_LUT4_O_I0 I2=R13_LUT4_I3_41_O_LUT4_I2_O I3=L13_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_2_I2_LUT4_O_I1 I2=L13_LUT4_I3_2_I2_LUT4_O_I2 I3=L13_LUT4_I3_2_I2_LUT4_O_I3 O=L13_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_41_O_LUT4_I2_O I1=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_40_O_LUT4_I2_2_O I3=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_38_O I1=R13_LUT4_I3_36_O I2=R13_LUT4_I3_37_O I3=R13_LUT4_I3_39_O O=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_38_O I1=R13_LUT4_I3_37_O I2=R13_LUT4_I3_39_O I3=R13_LUT4_I3_36_O O=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_1_I2_LUT4_O_I1 I2=L13_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_40_O_LUT4_I2_1_O O=L13_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_1_O I1=L13_LUT4_I3_1_I0_LUT4_O_I2 I2=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I3=L13_LUT4_I3_1_I1_LUT4_O_I1 O=L13_LUT4_I3_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L13_LUT4_I3_3_I0 I1=L13_LUT4_I3_3_I1 I2=L13_LUT4_I3_3_I2 I3=L13(2) O=R14_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L13_LUT4_I3_3_I0_LUT4_O_I0 I1=L13_LUT4_I3_3_I0_LUT4_O_I1 I2=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_I2_O I3=L13_LUT4_I3_3_I0_LUT4_O_I3 O=L13_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I2=L13_LUT4_I1_3_I2_LUT4_O_I1 I3=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I3 O=L13_LUT4_I3_3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=R13_LUT4_I3_22_O_LUT4_I2_1_O I2=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1 I3=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R13_LUT4_I3_21_O I1=R13_LUT4_I3_20_O I2=R13_LUT4_I3_18_O I3=R13_LUT4_I3_19_O O=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_23_O_LUT4_I2_O I1=L13_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_22_O_LUT4_I2_2_O I3=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_22_O_LUT4_I2_1_O I3=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 O=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_3_I2_LUT4_O_I0 I3=R13_LUT4_I3_22_O_LUT4_I2_O O=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_23_O_LUT4_I2_O I1=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_22_O_LUT4_I2_2_O I3=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_3_I2_LUT4_O_I0 I3=L13_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_1_O I1=L13_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_23_O_LUT4_I2_O I3=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I3 I2=R13_LUT4_I3_22_O I3=R13_LUT4_I3_23_O O=L13_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_10_I0_LUT4_O_I2 I3=L13_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I3 O=L13_LUT4_I3_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I1_LUT4_O_I1 I2=L13_LUT4_I3_3_I1_LUT4_O_I2 I3=L13_LUT4_I3_3_I1_LUT4_O_I3 O=L13_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_23_O_LUT4_I2_O I1=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_22_O_LUT4_I2_2_O I3=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_20_O I1=R13_LUT4_I3_21_O I2=R13_LUT4_I3_19_O I3=R13_LUT4_I3_18_O O=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_20_O I1=R13_LUT4_I3_18_O I2=R13_LUT4_I3_19_O I3=R13_LUT4_I3_21_O O=L13_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_O I1=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_22_O_LUT4_I2_1_O I3=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_19_O I1=R13_LUT4_I3_20_O I2=R13_LUT4_I3_21_O I3=R13_LUT4_I3_18_O O=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_21_O I1=R13_LUT4_I3_19_O I2=R13_LUT4_I3_20_O I3=R13_LUT4_I3_18_O O=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_23_O_LUT4_I2_O I3=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 O=L13_LUT4_I3_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_22_O_LUT4_I2_2_O O=L13_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_O I1=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L13_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_22_O_LUT4_I2_1_O O=L13_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_20_O I1=R13_LUT4_I3_19_O I2=R13_LUT4_I3_21_O I3=R13_LUT4_I3_18_O O=L13_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L13_LUT4_I3_3_I2_LUT4_O_I0 I1=R13_LUT4_I3_23_O_LUT4_I2_O I2=L13_LUT4_I3_3_I2_LUT4_O_I2 I3=L13_LUT4_I3_3_I2_LUT4_O_I3 O=L13_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_21_O I1=R13_LUT4_I3_20_O I2=R13_LUT4_I3_19_O I3=R13_LUT4_I3_18_O O=L13_LUT4_I3_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_22_O_LUT4_I2_2_O I3=L13_LUT4_I3_3_I2_LUT4_O_I0 O=L13_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_22_O_LUT4_I2_1_O O=L13_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_O I1=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=R13_LUT4_I3_23_O_LUT4_I2_O O=L13_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_18_O I1=R13_LUT4_I3_20_O I2=R13_LUT4_I3_19_O I3=R13_LUT4_I3_21_O O=L13_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 I3=R13_LUT4_I3_22_O_LUT4_I2_O O=L13_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_1_O I1=L13_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L13_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_22_O_LUT4_I2_2_O O=L13_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_22_O_LUT4_I2_1_O I1=L13_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_23_O_LUT4_I2_O O=L13_LUT4_I1_3_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_21_O I1=R13_LUT4_I3_20_O I2=R13_LUT4_I3_19_O I3=R13_LUT4_I3_18_O O=L13_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L13_LUT4_I3_7_I0 I1=L13_LUT4_I3_4_I1 I2=L13_LUT4_I3_4_I2 I3=L13(3) O=R14_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_7_I1_LUT4_O_I1 I3=L13_LUT4_I3_4_I1_LUT4_O_I3 O=L13_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_1_O I1=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=L13_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_4_O_LUT4_I2_2_O O=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_5_O_LUT4_I2_O O=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_3_O I1=R13_LUT4_I3_1_O I2=R13_LUT4_I3_O I3=R13_LUT4_I3_2_O O=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_1_O I1=L13_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_4_O_LUT4_I2_2_O I3=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_5_O_LUT4_I2_O I3=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_2_I2_LUT4_O_I2 I2=L13_LUT4_I3_7_I2_LUT4_O_I3 I3=L13_LUT4_I3_4_I2_LUT4_O_I3 O=L13_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I3 I2=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2 I3=L13_LUT4_I1_2_I3_LUT4_O_I2 O=L13_LUT4_I3_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L13_LUT4_I3_5_I0 I1=L13_LUT4_I3_5_I1 I2=L13_LUT4_I3_5_I2 I3=L13(5) O=R14_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_5_I2_LUT4_O_I2 I2=L13_LUT4_I3_5_I0_LUT4_O_I2 I3=L13_LUT4_I3_5_I0_LUT4_O_I3 O=L13_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_5_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R13_LUT4_I3_16_O_LUT4_I2_O O=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_16_O_LUT4_I2_2_O O=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_5_I2_LUT4_O_I1 I2=L13_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_5_I1_LUT4_O_I3 O=L13_LUT4_I3_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_5_I1_LUT4_O_I1 I2=L13_LUT4_I3_5_I1_LUT4_O_I2 I3=L13_LUT4_I3_5_I1_LUT4_O_I3 O=L13_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_5_I1_LUT4_O_I1 I2=R13_LUT4_I3_17_O_LUT4_I2_O I3=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_17_O_LUT4_I2_O I1=L13_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_16_O_LUT4_I2_2_O I3=L13_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_5_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_14_O I1=R13_LUT4_I3_13_O I2=R13_LUT4_I3_12_O I3=R13_LUT4_I3_15_O O=L13_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_15_O I1=R13_LUT4_I3_14_O I2=R13_LUT4_I3_13_O I3=R13_LUT4_I3_12_O O=L13_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2 I2=L13_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3 I3=L13_LUT4_I1_5_I2_LUT4_O_I1 O=L13_LUT4_I3_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_16_O_LUT4_I2_2_O I3=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I3_5_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_14_I1_LUT4_O_I1_LUT4_I3_I1 I3=R13_LUT4_I3_16_O_LUT4_I2_O O=L13_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R13_LUT4_I3_17_O_LUT4_I2_O I3=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_5_I2_LUT4_O_I2 I3=L13_LUT4_I3_5_I2_LUT4_O_I3 O=L13_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_14_I1_LUT4_O_I1 I3=R13_LUT4_I3_17_O_LUT4_I2_O O=L13_LUT4_I3_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3 I3=R13_LUT4_I3_16_O_LUT4_I2_O O=L13_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I2=L13_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_16_O_LUT4_I2_2_O O=L13_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I1_5_I3_LUT4_O_I2 I1=L13_LUT4_I3_14_I1_LUT4_O_I2 I2=L13_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_O I1=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_17_O_LUT4_I2_O O=L13_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_16_O_LUT4_I2_1_O I1=L13_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_16_O_LUT4_I2_2_O I3=L13_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_6_I1_LUT4_O_I0_LUT4_I1_O I1=L13_LUT4_I3_6_I1 I2=L13_LUT4_I3_6_I2 I3=L13(7) O=R14_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L13_LUT4_I3_6_I1_LUT4_O_I0 I1=L13_LUT4_I3_6_I1_LUT4_O_I1 I2=L13_LUT4_I3_6_I1_LUT4_O_I2 I3=L13_LUT4_I3_6_I1_LUT4_O_I3 O=L13_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L13_LUT4_I3_19_I1_LUT4_O_I3 I1=L13_LUT4_I3_6_I1_LUT4_O_I0 I2=L13_LUT4_I3_6_I1_LUT4_O_I0_LUT4_I1_I2 I3=L13_LUT4_I3_6_I1_LUT4_O_I0_LUT4_I1_I3 O=L13_LUT4_I3_6_I1_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R13_LUT4_I3_46_O_LUT4_I2_1_O I3=L13_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I3_6_I1_LUT4_O_I0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_9_I2_LUT4_O_I1 I3=L13_LUT4_I3_19_I1_LUT4_O_I1 O=L13_LUT4_I3_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_1_O I1=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R13_LUT4_I3_47_O_LUT4_I2_O I3=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_44_O I1=R13_LUT4_I3_43_O I2=R13_LUT4_I3_42_O I3=R13_LUT4_I3_45_O O=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I2=R13_LUT4_I3_46_O_LUT4_I2_2_O I3=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_45_O I1=R13_LUT4_I3_43_O I2=R13_LUT4_I3_44_O I3=R13_LUT4_I3_42_O O=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_2_O I1=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_6_I1_LUT4_O_I2 I3=L13_LUT4_I3_6_I1_LUT4_O_I3 O=L13_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_46_O_LUT4_I2_1_O O=L13_LUT4_I3_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_45_O I1=R13_LUT4_I3_44_O I2=R13_LUT4_I3_43_O I3=R13_LUT4_I3_42_O O=L13_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I1=R13_LUT4_I3_47_O_LUT4_I2_O I2=R13_LUT4_I3_46_O_LUT4_I2_2_O I3=L13_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I2 O=L13_LUT4_I3_6_I1_LUT4_O_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_45_O I1=R13_LUT4_I3_44_O I2=R13_LUT4_I3_43_O I3=R13_LUT4_I3_42_O O=L13_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I1=R13_LUT4_I3_46_O_LUT4_I2_2_O I2=R13_LUT4_I3_47_O_LUT4_I2_O I3=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_43_O I1=R13_LUT4_I3_42_O I2=R13_LUT4_I3_45_O I3=R13_LUT4_I3_44_O O=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_44_O I1=R13_LUT4_I3_43_O I2=R13_LUT4_I3_45_O I3=R13_LUT4_I3_42_O O=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_6_I2_LUT4_O_I1 I2=L13_LUT4_I3_6_I2_LUT4_O_I2 I3=L13_LUT4_I3_9_I1_LUT4_O_I3 O=L13_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_9_I1_LUT4_O_I1 I3=L13_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R13_LUT4_I3_46_O_LUT4_I2_O I3=R13_LUT4_I3_46_O_LUT4_I2_1_O O=L13_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_46_O_LUT4_I2_O O=L13_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_47_O_LUT4_I2_O O=L13_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_2_O I1=L13_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_46_O_LUT4_I2_1_O I3=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_7_I0 I1=L13_LUT4_I3_7_I1 I2=L13_LUT4_I3_7_I2 I3=L13(8) O=R14_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_2_I2 I2=L13_LUT4_I2_3_I3_LUT4_O_I1 I3=L13_LUT4_I2_3_I3_LUT4_O_I0 O=L13_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L13_LUT4_I3_7_I1_LUT4_O_I0 I1=L13_LUT4_I3_7_I1_LUT4_O_I1 I2=L13_LUT4_I3_7_I1_LUT4_O_I2 I3=L13_LUT4_I3_7_I1_LUT4_O_I3 O=L13_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2 I3=L13_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I3 O=L13_LUT4_I3_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=L13_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_4_O_LUT4_I2_1_O O=L13_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_2_O I1=R13_LUT4_I3_O I2=R13_LUT4_I3_1_O I3=R13_LUT4_I3_3_O O=L13_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_5_O_LUT4_I2_O I1=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_4_O_LUT4_I2_2_O O=L13_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2 I1=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_4_O_LUT4_I2_2_O O=L13_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_1_O I1=L13_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_5_O_LUT4_I2_O O=L13_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_1_O I1=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_5_O_LUT4_I2_O I3=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_2_O I1=R13_LUT4_I3_1_O I2=R13_LUT4_I3_O I3=R13_LUT4_I3_3_O O=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_O I1=R13_LUT4_I3_2_O I2=R13_LUT4_I3_1_O I3=R13_LUT4_I3_3_O O=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_4_O_LUT4_I2_2_O I3=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_1_O I1=R13_LUT4_I3_O I2=R13_LUT4_I3_3_O I3=R13_LUT4_I3_2_O O=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R13_LUT4_I3_4_O_LUT4_I2_1_O O=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_5_O_LUT4_I2_O I1=L13_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=R13_LUT4_I3_4_O_LUT4_I2_2_O I3=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_5_O_LUT4_I2_O O=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_1_O I1=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=R13_LUT4_I3_4_O_LUT4_I2_2_O I3=L13_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_3_O I1=R13_LUT4_I3_2_O I2=R13_LUT4_I3_1_O I3=R13_LUT4_I3_O O=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L13_LUT4_I1_2_I2_LUT4_O_I0 I1=R13_LUT4_I3_4_O_LUT4_I2_1_O I2=R13_LUT4_I3_4_O_LUT4_I2_2_O I3=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I1_2_I2_LUT4_O_I2 I2=L13_LUT4_I3_7_I2_LUT4_O_I2 I3=L13_LUT4_I3_7_I2_LUT4_O_I3 O=L13_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_1_O I1=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_5_O_LUT4_I2_O O=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_3_O I1=R13_LUT4_I3_2_O I2=R13_LUT4_I3_O I3=R13_LUT4_I3_1_O O=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_4_O_LUT4_I2_2_O I3=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_3_O I1=R13_LUT4_I3_2_O I2=R13_LUT4_I3_1_O I3=R13_LUT4_I3_O O=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_3_O I1=R13_LUT4_I3_O I2=R13_LUT4_I3_1_O I3=R13_LUT4_I3_2_O O=L13_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_5_O_LUT4_I2_O I3=L13_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_4_O_LUT4_I2_2_O I3=L13_LUT4_I1_2_I2_LUT4_O_I0 O=L13_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_4_O_LUT4_I2_O I1=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_4_O_LUT4_I2_1_O I3=L13_LUT4_I2_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_3_O I1=R13_LUT4_I3_2_O I2=R13_LUT4_I3_1_O I3=R13_LUT4_I3_O O=L13_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L13_LUT4_I3_8_I0 I1=L13_LUT4_I3_8_I1 I2=L13_LUT4_I3_8_I2 I3=L13(9) O=R14_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=L13_LUT4_I1_4_I3_LUT4_O_I1 I1=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I2=L13_LUT4_I3_8_I0_LUT4_O_I2 I3=L13_LUT4_I3_8_I0_LUT4_O_I3 O=L13_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_41_O_LUT4_I2_O I3=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_41_O_LUT4_I2_O I1=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_40_O_LUT4_I2_2_O I3=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_I2 I3=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O O=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3 I2=L13_LUT4_I3_2_I0_LUT4_O_I0 I3=R13_LUT4_I3_40_O_LUT4_I2_1_O O=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_39_O I1=R13_LUT4_I3_36_O I2=R13_LUT4_I3_37_O I3=R13_LUT4_I3_38_O O=L13_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_1_O I1=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_40_O_LUT4_I2_2_O I3=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_36_O I1=R13_LUT4_I3_38_O I2=R13_LUT4_I3_37_O I3=R13_LUT4_I3_39_O O=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_37_O I1=R13_LUT4_I3_36_O I2=R13_LUT4_I3_39_O I3=R13_LUT4_I3_38_O O=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_8_I1_LUT4_O_I2 I3=L13_LUT4_I1_4_I3_LUT4_O_I3 O=L13_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I3 I2=R13_LUT4_I3_41_O_LUT4_I2_O I3=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_1_O I1=L13_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_40_O_LUT4_I2_2_O O=L13_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_40_O_LUT4_I2_O I1=L13_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 I2=L13_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_40_O_LUT4_I2_2_O O=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_38_O I1=R13_LUT4_I3_37_O I2=R13_LUT4_I3_36_O I3=R13_LUT4_I3_39_O O=L13_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_8_I2_LUT4_O_I1 I2=L13_LUT4_I1_4_I2_LUT4_O_I2 I3=L13_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O O=L13_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_40_O_LUT4_I2_O O=L13_LUT4_I3_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_2_I0_LUT4_O_I1 I3=R13_LUT4_I3_40_O_LUT4_I2_1_O O=L13_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_41_O_LUT4_I2_O I1=L13_LUT4_I3_2_I0_LUT4_O_I0 I2=L13_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_40_O_LUT4_I2_2_O O=L13_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_39_O I1=R13_LUT4_I3_38_O I2=R13_LUT4_I3_37_O I3=R13_LUT4_I3_36_O O=L13_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L13_LUT4_I3_6_I1_LUT4_O_I0_LUT4_I1_O I1=L13_LUT4_I3_9_I1 I2=L13_LUT4_I3_9_I2 I3=L13(12) O=R14_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=L13_LUT4_I3_9_I1_LUT4_O_I0 I1=L13_LUT4_I3_9_I1_LUT4_O_I1 I2=L13_LUT4_I3_9_I1_LUT4_O_I2 I3=L13_LUT4_I3_9_I1_LUT4_O_I3 O=L13_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101100001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_15_I1_LUT4_O_I3 I3=L13_LUT4_I3_6_I2_LUT4_O_I1 O=L13_LUT4_I3_9_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_47_O_LUT4_I2_O I3=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_44_O I1=R13_LUT4_I3_42_O I2=R13_LUT4_I3_43_O I3=R13_LUT4_I3_45_O O=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R13_LUT4_I3_47_O_LUT4_I2_O O=L13_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_45_O I1=R13_LUT4_I3_44_O I2=R13_LUT4_I3_43_O I3=R13_LUT4_I3_42_O O=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_46_O_LUT4_I2_1_O O=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_42_O I1=R13_LUT4_I3_44_O I2=R13_LUT4_I3_43_O I3=R13_LUT4_I3_45_O O=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_45_O I1=R13_LUT4_I3_44_O I2=R13_LUT4_I3_42_O I3=R13_LUT4_I3_43_O O=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2 I3=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3 O=L13_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R13_LUT4_I3_46_O_LUT4_I2_1_O I3=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_44_O I1=R13_LUT4_I3_45_O I2=R13_LUT4_I3_43_O I3=R13_LUT4_I3_42_O O=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_2_O I1=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R13_LUT4_I3_47_O_LUT4_I2_O O=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_45_O I1=R13_LUT4_I3_42_O I2=R13_LUT4_I3_43_O I3=R13_LUT4_I3_44_O O=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_9_I1_LUT4_O_I2 I2=L13_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2 I3=L13_LUT4_I3_6_I2_LUT4_O_I2 O=L13_LUT4_I3_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1 I3=R13_LUT4_I3_46_O_LUT4_I2_O O=L13_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_46_O_LUT4_I2_1_O O=L13_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_9_I2_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I2 I3=L13_LUT4_I3_9_I2_LUT4_O_I3 O=L13_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_1_O I1=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_15_I2_LUT4_O_I1 I3=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_45_O I1=R13_LUT4_I3_44_O I2=R13_LUT4_I3_43_O I3=R13_LUT4_I3_42_O O=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_46_O_LUT4_I2_2_O O=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 I2=R13_LUT4_I3_47_O_LUT4_I2_O I3=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_45_O I1=R13_LUT4_I3_43_O I2=R13_LUT4_I3_42_O I3=R13_LUT4_I3_44_O O=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_46_O_LUT4_I2_2_O O=L13_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_47_O_LUT4_I2_O I3=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_O I1=L13_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R13_LUT4_I3_46_O_LUT4_I2_1_O I3=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_45_O I1=R13_LUT4_I3_44_O I2=R13_LUT4_I3_43_O I3=R13_LUT4_I3_42_O O=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_43_O I1=R13_LUT4_I3_44_O I2=R13_LUT4_I3_45_O I3=R13_LUT4_I3_42_O O=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_47_O_LUT4_I2_O O=L13_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R13_LUT4_I3_46_O_LUT4_I2_O O=L13_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_46_O_LUT4_I2_2_O I1=L13_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 I2=R13_LUT4_I3_46_O_LUT4_I2_1_O I3=L13_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L13_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L13_LUT4_I3_I1_LUT4_O_I0 I1=L13_LUT4_I3_I1_LUT4_O_I1 I2=L13_LUT4_I3_I1_LUT4_O_I2 I3=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O O=L13_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I0 I1=R13_LUT4_I3_10_O_LUT4_I2_2_O I2=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I2 I3=L13_LUT4_I1_I3_LUT4_O_I0 O=L13_LUT4_I3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R13_LUT4_I3_8_O I1=R13_LUT4_I3_6_O I2=R13_LUT4_I3_7_O I3=R13_LUT4_I3_9_O O=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R13_LUT4_I3_10_O_LUT4_I2_1_O O=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_2_O I1=L13_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R13_LUT4_I3_11_O_LUT4_I2_O I3=L13_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_8_O I1=R13_LUT4_I3_7_O I2=R13_LUT4_I3_9_O I3=R13_LUT4_I3_6_O O=L13_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I0 I1=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_10_O_LUT4_I2_O I3=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R13_LUT4_I3_9_O I1=R13_LUT4_I3_6_O I2=R13_LUT4_I3_7_O I3=R13_LUT4_I3_8_O O=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R13_LUT4_I3_9_O I1=R13_LUT4_I3_8_O I2=R13_LUT4_I3_7_O I3=R13_LUT4_I3_6_O O=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_1_O I1=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R13_LUT4_I3_11_O_LUT4_I2_O O=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_8_O I1=R13_LUT4_I3_7_O I2=R13_LUT4_I3_6_O I3=R13_LUT4_I3_9_O O=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L13_LUT4_I1_I2_LUT4_O_I2 I1=L13_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I2=L13_LUT4_I3_13_I1_LUT4_O_I2 I3=L13_LUT4_I3_I2_LUT4_O_I1 O=L13_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R13_LUT4_I3_11_O_LUT4_I2_O I3=L13_LUT4_I3_17_I2_LUT4_O_I3 O=L13_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R13_LUT4_I3_10_O_LUT4_I2_1_O O=L13_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_10_O_LUT4_I2_2_O I3=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_I2_LUT4_O_I1 I2=L13_LUT4_I3_I2_LUT4_O_I2 I3=L13_LUT4_I3_I2_LUT4_O_I3 O=L13_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3 O=L13_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=R13_LUT4_I3_11_O_LUT4_I2_O I2=R13_LUT4_I3_10_O_LUT4_I2_2_O I3=L13_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I0 O=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_10_O_LUT4_I2_1_O I3=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_8_O I1=R13_LUT4_I3_9_O I2=R13_LUT4_I3_7_O I3=R13_LUT4_I3_6_O O=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R13_LUT4_I3_7_O I1=R13_LUT4_I3_6_O I2=R13_LUT4_I3_9_O I3=R13_LUT4_I3_8_O O=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L13_LUT4_I1_I2_LUT4_O_I1 I3=L13_LUT4_I3_13_I0_LUT4_O_I2 O=L13_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L13_LUT4_I3_I2_LUT4_O_I3 I1=L13_LUT4_I3_I2_LUT4_O_I2 I2=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_I0_I2 I3=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_I0_I3 O=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_2_O I1=L13_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R13_LUT4_I3_11_O_LUT4_I2_O I3=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_O I1=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=L13_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I0 I3=R13_LUT4_I3_10_O_LUT4_I2_1_O O=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L13_LUT4_I3_17_I2_LUT4_O_I3 I3=R13_LUT4_I3_10_O_LUT4_I2_O O=L13_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R13_LUT4_I3_10_O_LUT4_I2_1_O O=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R13_LUT4_I3_10_O_LUT4_I2_2_O I1=L13_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R13_LUT4_I3_11_O_LUT4_I2_O I3=L13_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R13_LUT4_I3_9_O I1=R13_LUT4_I3_8_O I2=R13_LUT4_I3_7_O I3=R13_LUT4_I3_6_O O=L13_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=L13(1) D=R12(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(2) D=R12(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(11) D=R12(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(12) D=R12(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(13) D=R12(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(14) D=R12(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(15) D=R12(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(16) D=R12(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(17) D=R12(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(18) D=R12(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(19) D=R12(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(20) D=R12(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(3) D=R12(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(21) D=R12(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(22) D=R12(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(23) D=R12(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(24) D=R12(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(25) D=R12(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(26) D=R12(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(27) D=R12(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(28) D=R12(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(29) D=R12(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(30) D=R12(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(4) D=R12(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(31) D=R12(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(32) D=R12(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(5) D=R12(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(6) D=R12(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(7) D=R12(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(8) D=R12(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(9) D=R12(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L13(10) D=R12(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:191.1-192.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(1) D=R13(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(2) D=R13(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(11) D=R13(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(12) D=R13(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(13) D=R13(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(14) D=R13(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(15) D=R13(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(16) D=R13(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(17) D=R13(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(18) D=R13(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(19) D=R13(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(20) D=R13(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(3) D=R13(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(21) D=R13(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(22) D=R13(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(23) D=R13(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(24) D=R13(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(25) D=R13(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(26) D=R13(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(27) D=R13(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(28) D=R13(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(29) D=R13(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(30) D=R13(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(4) D=R13(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(31) D=R13(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(32) D=R13(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(5) D=R13(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(6) D=R13(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(7) D=R13(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(8) D=R13(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(9) D=R13(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L14(10) D=R13(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:197.1-198.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L1(10) I2=L1_LUT4_I1_I2 I3=L1_LUT4_I1_I3 O=R2_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L1(11) I2=L1_LUT4_I1_1_I2 I3=L1_LUT4_I1_1_I3 O=R2_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L1_LUT4_I1_1_I2_LUT4_O_I0 I1=R1_LUT4_I3_28_O_LUT4_I2_2_O I2=L1_LUT4_I1_1_I2_LUT4_O_I2 I3=L1_LUT4_I1_1_I2_LUT4_O_I3 O=L1_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R1_LUT4_I3_27_O I1=R1_LUT4_I3_26_O I2=R1_LUT4_I3_25_O I3=R1_LUT4_I3_24_O O=L1_LUT4_I1_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_17_I1_LUT4_O_I2 O=L1_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_29_O_LUT4_I2_O I1=L1_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I0 I2=R1_LUT4_I3_28_O_LUT4_I2_2_O I3=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_27_O I1=R1_LUT4_I3_26_O I2=R1_LUT4_I3_24_O I3=R1_LUT4_I3_25_O O=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_28_O_LUT4_I2_1_O I3=L1_LUT4_I1_1_I2_LUT4_O_I0 O=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_25_O I1=R1_LUT4_I3_26_O I2=R1_LUT4_I3_27_O I3=R1_LUT4_I3_24_O O=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_28_O_LUT4_I2_1_O I3=L1_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I1_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I0 I2=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_29_O_LUT4_I2_O O=L1_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_27_O I1=R1_LUT4_I3_26_O I2=R1_LUT4_I3_25_O I3=R1_LUT4_I3_24_O O=L1_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I1_1_I3_LUT4_O_I0 I1=L1_LUT4_I1_1_I3_LUT4_O_I1 I2=L1_LUT4_I1_1_I3_LUT4_O_I2 I3=L1_LUT4_I1_1_I3_LUT4_O_I3 O=L1_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I0 I1=L1_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3 I2=R1_LUT4_I3_29_O I3=R1_LUT4_I3_28_O O=L1_LUT4_I1_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R1_LUT4_I3_27_O I1=R1_LUT4_I3_26_O I2=R1_LUT4_I3_25_O I3=R1_LUT4_I3_24_O O=L1_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_28_O_LUT4_I2_1_O I3=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_27_O I1=R1_LUT4_I3_26_O I2=R1_LUT4_I3_25_O I3=R1_LUT4_I3_24_O O=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_26_O I1=R1_LUT4_I3_24_O I2=R1_LUT4_I3_25_O I3=R1_LUT4_I3_27_O O=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_17_I2_LUT4_O_I2 I1=L1_LUT4_I3_17_I2_LUT4_O_I1 I2=L1_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_2_O I1=L1_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_28_O_LUT4_I2_1_O O=L1_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R1_LUT4_I3_29_O_LUT4_I2_O O=L1_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_26_O I1=R1_LUT4_I3_25_O I2=R1_LUT4_I3_24_O I3=R1_LUT4_I3_27_O O=L1_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_29_O_LUT4_I2_O I1=L1_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_28_O_LUT4_I2_1_O I3=L1_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 I2=R1_LUT4_I3_28_O_LUT4_I2_2_O I3=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1(1) I2=L1_LUT4_I1_2_I2 I3=L1_LUT4_I1_2_I3 O=R2_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O I2=L1_LUT4_I1_2_I2_LUT4_O_I2 I3=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O O=L1_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_22_I2_LUT4_O_I2 I3=R1_LUT4_I3_11_O_LUT4_I2_O O=L1_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=R1_LUT4_I3_10_O_LUT4_I2_O O=L1_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_1_O I1=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R1_LUT4_I3_10_O_LUT4_I2_2_O I3=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 O=L1_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I1_2_I3_LUT4_O_I0 I1=L1_LUT4_I1_2_I3_LUT4_O_I1 I2=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O I3=L1_LUT4_I3_22_I1 O=L1_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2 I3=L1_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3 O=L1_LUT4_I1_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_O I1=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_11_O_LUT4_I2_O I3=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_1_O I1=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I2=L1_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_10_O_LUT4_I2_2_O O=L1_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_8_O I1=R1_LUT4_I3_6_O I2=R1_LUT4_I3_7_O I3=R1_LUT4_I3_9_O O=L1_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I1_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_1_O I1=L1_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I2=R1_LUT4_I3_11_O_LUT4_I2_O I3=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_9_O I1=R1_LUT4_I3_7_O I2=R1_LUT4_I3_6_O I3=R1_LUT4_I3_8_O O=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_O I1=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I3=R1_LUT4_I3_10_O_LUT4_I2_2_O O=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_7_O I1=R1_LUT4_I3_6_O I2=R1_LUT4_I3_9_O I3=R1_LUT4_I3_8_O O=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O I1=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L1_LUT4_I1_I2_LUT4_O_I2 I3=L1_LUT4_I1_I2_LUT4_O_I3 O=L1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O I1=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L1_LUT4_I1_I2_LUT4_O_I2 I3=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3 O=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 I2=R1_LUT4_I3_10_O_LUT4_I2_2_O I3=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_O I1=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I3=R1_LUT4_I3_11_O_LUT4_I2_O O=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_22_I2_LUT4_O_I2 I3=R1_LUT4_I3_10_O_LUT4_I2_O O=L1_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_10_O_LUT4_I2_2_O O=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_1_O I1=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R1_LUT4_I3_11_O_LUT4_I2_O O=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_8_O I1=R1_LUT4_I3_9_O I2=R1_LUT4_I3_7_O I3=R1_LUT4_I3_6_O O=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_2_O I1=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_11_O_LUT4_I2_O I3=L1_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 O=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_8_O I1=R1_LUT4_I3_7_O I2=R1_LUT4_I3_6_O I3=R1_LUT4_I3_9_O O=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_O I1=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_10_O_LUT4_I2_1_O I3=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 O=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_7_O I1=R1_LUT4_I3_8_O I2=R1_LUT4_I3_9_O I3=R1_LUT4_I3_6_O O=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L1_LUT4_I1_I3_LUT4_O_I1 I2=L1_LUT4_I1_I3_LUT4_O_I2 I3=L1_LUT4_I1_I3_LUT4_O_I3 O=L1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I1=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_11_O I3=R1_LUT4_I3_10_O O=L1_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R1_LUT4_I3_9_O I1=R1_LUT4_I3_8_O I2=R1_LUT4_I3_7_O I3=R1_LUT4_I3_6_O O=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_9_O I1=R1_LUT4_I3_8_O I2=R1_LUT4_I3_7_O I3=R1_LUT4_I3_6_O O=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I1_2_I2_LUT4_O_I2 I1=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I1_I2_LUT4_O_I3 O=L1_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_22_I2_LUT4_O_I2 I3=R1_LUT4_I3_10_O_LUT4_I2_2_O O=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I3=R1_LUT4_I3_10_O_LUT4_I2_O O=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_1_O I1=L1_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R1_LUT4_I3_11_O_LUT4_I2_O I3=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_O I1=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_10_O_LUT4_I2_1_O I3=L1_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_2_O I1=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I3=R1_LUT4_I3_11_O_LUT4_I2_O O=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I3_22_I1_LUT4_O_I3 I2=L1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I1_2_I3_LUT4_O_I0 O=L1_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_O I1=L1_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I2=R1_LUT4_I3_11_O_LUT4_I2_O I3=L1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_9_O I1=R1_LUT4_I3_7_O I2=R1_LUT4_I3_8_O I3=R1_LUT4_I3_6_O O=L1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1(15) I3=L1_LUT4_I2_I3 O=R2_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1(18) I3=L1_LUT4_I2_1_I3 O=R2_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L1_LUT4_I2_1_I3_LUT4_O_I0 I1=L1_LUT4_I2_1_I3_LUT4_O_I1 I2=L1_LUT4_I2_1_I3_LUT4_O_I2 I3=L1_LUT4_I2_1_I3_LUT4_O_I3 O=L1_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_23_I2_LUT4_O_I2 I3=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L1_LUT4_I2_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_I2_LUT4_O_I1 O=L1_LUT4_I2_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_23_O_LUT4_I2_O I3=L1_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_1_O I1=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R1_LUT4_I3_22_O_LUT4_I2_O I3=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_I1_LUT4_O_I2 O=L1_LUT4_I2_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_23_O_LUT4_I2_O I1=L1_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 I3=R1_LUT4_I3_22_O_LUT4_I2_O O=L1_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_22_O_LUT4_I2_1_O I3=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L1_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_21_O I1=R1_LUT4_I3_18_O I2=R1_LUT4_I3_19_O I3=R1_LUT4_I3_20_O O=L1_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_I2_LUT4_O_I3 O=L1_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I0 I2=R1_LUT4_I3_22_O_LUT4_I2_O I3=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1 O=L1_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2 I1=R1_LUT4_I3_23_O_LUT4_I2_O I2=R1_LUT4_I3_22_O_LUT4_I2_1_O I3=L1_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1(25) I3=L1_LUT4_I2_2_I3 O=R2_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L1_LUT4_I2_2_I3_LUT4_O_I0 I1=L1_LUT4_I2_2_I3_LUT4_O_I1 I2=L1_LUT4_I2_2_I3_LUT4_O_I2 I3=L1_LUT4_I2_2_I3_LUT4_O_I3 O=L1_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110111
+.subckt LUT4 I0=L1_LUT4_I3_15_I0_LUT4_O_I2 I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1 I2=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2 I3=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3 O=L1_LUT4_I2_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I3_O I1=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_O_LUT4_I2_2_O I3=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R1_LUT4_I3_O_LUT4_I2_1_O I3=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I2_1_O O=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_3_O I1=R1_LUT4_I3_4_O I2=R1_LUT4_I3_5_O I3=R1_LUT4_I3_2_O O=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_4_O I1=R1_LUT4_I3_5_O I2=R1_LUT4_I3_3_O I3=R1_LUT4_I3_2_O O=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I3_O I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I2_2_O I3=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_4_O I1=R1_LUT4_I3_3_O I2=R1_LUT4_I3_2_O I3=R1_LUT4_I3_5_O O=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_4_O I1=R1_LUT4_I3_2_O I2=R1_LUT4_I3_3_O I3=R1_LUT4_I3_5_O O=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_12_I2_LUT4_O_I2 I3=L1_LUT4_I3_8_I2_LUT4_O_I2 O=L1_LUT4_I2_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_1_O I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R1_LUT4_I3_2_O I1=R1_LUT4_I3_4_O I2=R1_LUT4_I3_3_O I3=R1_LUT4_I3_5_O O=L1_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_O_LUT4_I3_O I3=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_12_I2_LUT4_O_I2 I3=L1_LUT4_I3_15_I0_LUT4_O_I2 O=L1_LUT4_I2_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_8_I1_LUT4_O_I3 I2=L1_LUT4_I3_12_I1_LUT4_O_I1 I3=L1_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I2_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I2_O O=L1_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I2_2_O I3=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L1_LUT4_I2_I3_LUT4_O_I0 I1=L1_LUT4_I3_5_I0_LUT4_I0_O I2=L1_LUT4_I2_I3_LUT4_O_I2 I3=L1_LUT4_I2_I3_LUT4_O_I3 O=L1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L1_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L1_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R1_LUT4_I3_16_O_LUT4_I2_O I3=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 O=L1_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_17_O_LUT4_I2_O I1=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I0 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_5_I0_LUT4_O_I3 I3=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O O=L1_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L1_LUT4_I3_I0 I1=L1_LUT4_I3_I1 I2=L1_LUT4_I3_I2 I3=L1(2) O=R2_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L1_LUT4_I3_1_I0 I1=L1_LUT4_I3_1_I1 I2=L1_LUT4_I3_1_I2 I3=L1(5) O=R2_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L1_LUT4_I3_10_I0 I1=L1_LUT4_I3_10_I1 I2=L1_LUT4_I3_10_I2 I3=L1(6) O=R2_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_16_I0_LUT4_O_I3 I2=L1_LUT4_I3_16_I0_LUT4_O_I2 I3=L1_LUT4_I3_10_I0_LUT4_O_I3 O=L1_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_10_I1_LUT4_I2_I1 I2=L1_LUT4_I3_10_I1 I3=L1_LUT4_I3_4_I2_LUT4_O_I2 O=L1_LUT4_I3_16_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_2_O I1=R1_LUT4_I3_35_O_LUT4_I2_O I2=L1_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 I3=L1_LUT4_I3_10_I1_LUT4_I2_I1_LUT4_O_I3 O=L1_LUT4_I3_10_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R1_LUT4_I3_35_O_LUT4_I2_O I1=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R1_LUT4_I3_34_O_LUT4_I2_2_O I3=L1_LUT4_I3_10_I2_LUT4_I3_I1_LUT4_O_I3 O=L1_LUT4_I3_10_I1_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_10_I1_LUT4_O_I1 I2=R1_LUT4_I3_34_O_LUT4_I2_O I3=L1_LUT4_I3_6_I0_LUT4_O_I2 O=L1_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_34_O_LUT4_I2_1_O O=L1_LUT4_I3_10_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_35_O_LUT4_I2_O I1=L1_LUT4_I3_10_I2_LUT4_I3_I1_LUT4_O_I3 I2=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_34_O_LUT4_I2_2_O O=L1_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_31_O I1=R1_LUT4_I3_32_O I2=R1_LUT4_I3_33_O I3=R1_LUT4_I3_30_O O=L1_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_10_I2_LUT4_I3_I1 I2=L1_LUT4_I3_10_I2_LUT4_I3_I2 I3=L1_LUT4_I3_10_I2 O=L1_LUT4_I3_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_35_O_LUT4_I2_O I1=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3 I2=R1_LUT4_I3_34_O_LUT4_I2_1_O I3=L1_LUT4_I3_10_I2_LUT4_I3_I1_LUT4_O_I3 O=L1_LUT4_I3_10_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_32_O I1=R1_LUT4_I3_30_O I2=R1_LUT4_I3_31_O I3=R1_LUT4_I3_33_O O=L1_LUT4_I3_10_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_2_O I1=L1_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_34_O_LUT4_I2_O I3=L1_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_10_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_10_I2_LUT4_O_I2 I3=L1_LUT4_I3_10_I2_LUT4_O_I3 O=L1_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_2_O I1=L1_LUT4_I3_6_I1_LUT4_O_I0 I2=R1_LUT4_I3_34_O_LUT4_I2_1_O I3=L1_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 O=L1_LUT4_I3_10_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_35_O_LUT4_I2_O I1=L1_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_34_O_LUT4_I2_O I3=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1 O=L1_LUT4_I3_10_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_32_O I1=R1_LUT4_I3_33_O I2=R1_LUT4_I3_31_O I3=R1_LUT4_I3_30_O O=L1_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L1_LUT4_I3_11_I0 I1=L1_LUT4_I3_11_I1 I2=L1_LUT4_I3_11_I2 I3=L1(7) O=R2_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_11_I0_LUT4_O_I1 I2=L1_LUT4_I3_11_I0_LUT4_O_I2 I3=L1_LUT4_I3_25_I0_LUT4_O_I2 O=L1_LUT4_I3_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_11_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_25_I2_LUT4_O_I0_LUT4_O_I1 I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_45_O I1=R1_LUT4_I3_43_O I2=R1_LUT4_I3_44_O I3=R1_LUT4_I3_42_O O=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_O I1=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_46_O_LUT4_I2_1_O I3=L1_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_42_O I1=R1_LUT4_I3_44_O I2=R1_LUT4_I3_43_O I3=R1_LUT4_I3_45_O O=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_11_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L1_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I1=R1_LUT4_I3_47_O_LUT4_I2_O I2=R1_LUT4_I3_46_O_LUT4_I2_1_O I3=L1_LUT4_I3_25_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_46_O_LUT4_I2_O I3=L1_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L1_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_44_O I1=R1_LUT4_I3_43_O I2=R1_LUT4_I3_45_O I3=R1_LUT4_I3_42_O O=L1_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_11_I1_LUT4_O_I1 I2=L1_LUT4_I3_11_I1_LUT4_O_I2 I3=L1_LUT4_I3_20_I1_LUT4_O_I3 O=L1_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_O I1=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I3 I2=R1_LUT4_I3_46_O_LUT4_I2_1_O I3=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_11_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_45_O I1=R1_LUT4_I3_44_O I2=R1_LUT4_I3_43_O I3=R1_LUT4_I3_42_O O=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_45_O I1=R1_LUT4_I3_44_O I2=R1_LUT4_I3_43_O I3=R1_LUT4_I3_42_O O=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_11_I2_LUT4_O_I2 I3=L1_LUT4_I3_11_I2_LUT4_O_I3 O=L1_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_O I1=L1_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I0 I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_45_O I1=R1_LUT4_I3_44_O I2=R1_LUT4_I3_43_O I3=R1_LUT4_I3_42_O O=L1_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I3 I2=R1_LUT4_I3_46_O_LUT4_I2_1_O I3=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I0 I1=L1_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_46_O_LUT4_I2_2_O I3=R1_LUT4_I3_46_O_LUT4_I2_O O=L1_LUT4_I3_11_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I0 I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_25_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_25_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_45_O I1=R1_LUT4_I3_44_O I2=R1_LUT4_I3_42_O I3=R1_LUT4_I3_43_O O=L1_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_45_O I1=R1_LUT4_I3_44_O I2=R1_LUT4_I3_43_O I3=R1_LUT4_I3_42_O O=L1_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L1_LUT4_I3_8_I0 I1=L1_LUT4_I3_12_I1 I2=L1_LUT4_I3_12_I2 I3=L1(8) O=R2_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L1_LUT4_I3_15_I1_LUT4_O_I1 I1=L1_LUT4_I3_12_I1_LUT4_O_I1 I2=L1_LUT4_I3_8_I1_LUT4_O_I2 I3=L1_LUT4_I3_15_I1_LUT4_O_I3 O=L1_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I3_O O=L1_LUT4_I3_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I2_O O=L1_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_2_O I1=L1_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_O_LUT4_I2_1_O O=L1_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_5_O I1=R1_LUT4_I3_4_O I2=R1_LUT4_I3_3_O I3=R1_LUT4_I3_2_O O=L1_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_8_I2_LUT4_O_I1 I2=L1_LUT4_I3_12_I2_LUT4_O_I2 I3=L1_LUT4_I3_8_I2_LUT4_O_I2 O=L1_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_2_O I1=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I2_1_O O=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_5_O I1=R1_LUT4_I3_2_O I2=R1_LUT4_I3_3_O I3=R1_LUT4_I3_4_O O=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_5_O I1=R1_LUT4_I3_3_O I2=R1_LUT4_I3_2_O I3=R1_LUT4_I3_4_O O=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I3_O I3=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_3_O I1=R1_LUT4_I3_2_O I2=R1_LUT4_I3_5_O I3=R1_LUT4_I3_4_O O=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_21_I0 I1=L1_LUT4_I3_13_I1 I2=L1_LUT4_I3_13_I2 I3=L1(9) O=R2_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_13_I1_LUT4_O_I1 I2=L1_LUT4_I3_21_I1_LUT4_O_I1 I3=L1_LUT4_I3_21_I1_LUT4_O_I2 O=L1_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_13_I1_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_13_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_13_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_2_O I1=L1_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_40_O_LUT4_I2_1_O I3=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_13_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_41_O_LUT4_I2_O I3=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_13_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_21_I2_LUT4_O_I2 I3=L1_LUT4_I3_3_I1_LUT4_O_I3 O=L1_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L1_LUT4_I3_25_I0 I1=L1_LUT4_I3_14_I1 I2=L1_LUT4_I3_14_I2 I3=L1(12) O=R2_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_20_I1_LUT4_O_I3 I2=L1_LUT4_I3_11_I2_LUT4_O_I2 I3=L1_LUT4_I3_25_I2 O=L1_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_14_I2_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I3 I3=L1_LUT4_I3_25_I0_LUT4_O_I3 O=L1_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_46_O_LUT4_I2_1_O O=L1_LUT4_I3_14_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_47_O_LUT4_I2_O O=L1_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_25_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R1_LUT4_I3_46_O_LUT4_I2_O O=L1_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_45_O I1=R1_LUT4_I3_42_O I2=R1_LUT4_I3_43_O I3=R1_LUT4_I3_44_O O=L1_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_15_I0 I1=L1_LUT4_I3_15_I1 I2=L1_LUT4_I3_15_I2 I3=L1(14) O=R2_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_15_I0_LUT4_O_I2 I3=L1_LUT4_I2_2_I3_LUT4_O_I0 O=L1_LUT4_I3_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_15_I0_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_15_I2_LUT4_O_I0 I3=R1_LUT4_I3_O_LUT4_I2_O O=L1_LUT4_I3_15_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_15_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R1_LUT4_I3_O_LUT4_I3_O O=L1_LUT4_I3_15_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L1_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=R1_LUT4_I3_O_LUT4_I2_2_O I2=R1_LUT4_I3_O_LUT4_I2_1_O I3=L1_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L1_LUT4_I3_15_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_15_I1_LUT4_O_I1 I2=L1_LUT4_I3_15_I1_LUT4_O_I2 I3=L1_LUT4_I3_15_I1_LUT4_O_I3 O=L1_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_15_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I2_2_O O=L1_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I3_O I1=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I2_1_O I3=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=L1_LUT4_I3_15_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_15_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I2_1_O I3=L1_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L1_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I3_O I1=L1_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I2_2_O I3=L1_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_5_O I1=R1_LUT4_I3_4_O I2=R1_LUT4_I3_3_O I3=R1_LUT4_I3_2_O O=L1_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 I3=L1_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_15_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L1_LUT4_I3_15_I2_LUT4_O_I0 I1=R1_LUT4_I3_O_LUT4_I3_O I2=L1_LUT4_I3_8_I2_LUT4_O_I1 I3=L1_LUT4_I3_15_I2_LUT4_O_I3 O=L1_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R1_LUT4_I3_5_O I1=R1_LUT4_I3_4_O I2=R1_LUT4_I3_3_O I3=R1_LUT4_I3_2_O O=L1_LUT4_I3_15_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I2_2_O O=L1_LUT4_I3_15_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I2_1_O I3=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_16_I0 I1=L1_LUT4_I3_16_I1 I2=L1_LUT4_I3_16_I2 I3=L1(16) O=R2_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_6_I2_LUT4_O_I1 I2=L1_LUT4_I3_16_I0_LUT4_O_I2 I3=L1_LUT4_I3_16_I0_LUT4_O_I3 O=L1_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_4_I2_LUT4_O_I1 O=L1_LUT4_I3_16_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_1_O I1=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L1_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_34_O_LUT4_I2_O O=L1_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_35_O_LUT4_I2_O I1=L1_LUT4_I3_6_I1_LUT4_O_I0 I2=R1_LUT4_I3_34_O_LUT4_I2_2_O I3=L1_LUT4_I3_4_I0_LUT4_O_I0 O=L1_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_16_I1_LUT4_O_I1 I2=L1_LUT4_I3_16_I1_LUT4_O_I2 I3=L1_LUT4_I3_16_I1_LUT4_O_I3 O=L1_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_35_O_LUT4_I2_O I1=L1_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_34_O_LUT4_I2_O I3=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3 O=L1_LUT4_I3_16_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_33_O I1=R1_LUT4_I3_31_O I2=R1_LUT4_I3_30_O I3=R1_LUT4_I3_32_O O=L1_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_2_O I1=L1_LUT4_I3_6_I0_LUT4_O_I2 I2=L1_LUT4_I3_16_I1_LUT4_O_I2 I3=L1_LUT4_I3_16_I1_LUT4_O_I2_LUT4_I2_I3 O=L1_LUT4_I3_4_I1_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=L1_LUT4_I3_4_I0_LUT4_O_I0 I3=R1_LUT4_I3_35_O_LUT4_I2_O O=L1_LUT4_I3_16_I1_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_2_O I1=R1_LUT4_I3_35_O_LUT4_I2_O I2=L1_LUT4_I3_6_I1_LUT4_O_I1 I3=L1_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_16_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R1_LUT4_I3_35_O_LUT4_I2_O I1=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1 I2=R1_LUT4_I3_34_O_LUT4_I2_2_O I3=L1_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I1 O=L1_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_4_I1_LUT4_O_I3 I1=L1_LUT4_I3_6_I0_LUT4_O_I2 I2=R1_LUT4_I3_35_O I3=R1_LUT4_I3_34_O O=L1_LUT4_I3_16_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_O I1=R1_LUT4_I3_34_O_LUT4_I2_1_O I2=L1_LUT4_I3_16_I2_LUT4_O_I2 I3=L1_LUT4_I3_16_I2_LUT4_O_I3 O=L1_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R1_LUT4_I3_33_O I1=R1_LUT4_I3_32_O I2=R1_LUT4_I3_31_O I3=R1_LUT4_I3_30_O O=L1_LUT4_I3_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_1_O I1=L1_LUT4_I3_4_I0_LUT4_O_I0 I2=L1_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_34_O_LUT4_I2_O O=L1_LUT4_I3_16_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_9_I0 I1=L1_LUT4_I3_17_I1 I2=L1_LUT4_I3_17_I2 I3=L1(19) O=R2_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_17_I1_LUT4_O_I1 I2=L1_LUT4_I3_17_I1_LUT4_O_I2 I3=L1_LUT4_I3_9_I0_LUT4_O_I3 O=L1_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3 I3=R1_LUT4_I3_28_O_LUT4_I2_O O=L1_LUT4_I3_17_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I1_1_I2_LUT4_O_I0 I3=R1_LUT4_I3_29_O_LUT4_I2_O O=L1_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_2_O I1=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_28_O_LUT4_I2_1_O O=L1_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_17_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_29_O_LUT4_I2_O I1=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I3=R1_LUT4_I3_28_O_LUT4_I2_1_O O=L1_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R1_LUT4_I3_28_O_LUT4_I2_2_O I3=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_17_I2_LUT4_O_I1 I2=L1_LUT4_I3_17_I2_LUT4_O_I2 I3=L1_LUT4_I3_9_I2_LUT4_O_I0 O=L1_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_17_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_28_O_LUT4_I2_1_O I3=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_29_O_LUT4_I2_O I1=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_28_O_LUT4_I2_2_O O=L1_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_28_O_LUT4_I2_2_O I3=L1_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 O=L1_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_29_O_LUT4_I2_O I1=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_28_O_LUT4_I2_1_O I3=L1_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L1_LUT4_I3_18_I2 I3=L1(20) O=R2_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L1_LUT4_I3_22_I0_LUT4_O_I2 I1=L1_LUT4_I3_22_I2 I2=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O I3=L1_LUT4_I1_2_I3_LUT4_O_I1 O=L1_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I3_19_I0 I1=L1_LUT4_I3_19_I1 I2=L1_LUT4_I3_19_I2 I3=L1(21) O=R2_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_1_I0_LUT4_O_I1 I2=L1_LUT4_I2_I3_LUT4_O_I0 I3=L1_LUT4_I3_5_I0_LUT4_I0_O O=L1_LUT4_I3_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_5_I0_LUT4_O_I2 I2=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L1_LUT4_I3_5_I0_LUT4_I0_O O=L1_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=L1_LUT4_I3_19_I2_LUT4_O_I2 I3=L1_LUT4_I3_5_I2_LUT4_O_I2 O=L1_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_16_O_LUT4_I2_O O=L1_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_16_O_LUT4_I2_1_O O=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_17_O_LUT4_I2_O I1=L1_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=R1_LUT4_I3_16_O_LUT4_I2_2_O O=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2 I3=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_15_O I1=R1_LUT4_I3_14_O I2=R1_LUT4_I3_13_O I3=R1_LUT4_I3_12_O O=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L1_LUT4_I2_I3_LUT4_O_I0 I1=L1_LUT4_I3_1_I0_LUT4_O_I1 I2=L1_LUT4_I3_5_I0_LUT4_I0_O I3=L1_LUT4_I3_1_I0_LUT4_O_I3 O=L1_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I0 I3=R1_LUT4_I3_16_O_LUT4_I2_2_O O=L1_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_O I1=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_17_O_LUT4_I2_O O=L1_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_15_O I1=R1_LUT4_I3_14_O I2=R1_LUT4_I3_13_O I3=R1_LUT4_I3_12_O O=L1_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L1_LUT4_I3_1_I1_LUT4_O_I0 I1=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=L1_LUT4_I3_5_I2_LUT4_O_I1 I3=L1_LUT4_I3_1_I1_LUT4_O_I3 O=L1_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I1=L1_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R1_LUT4_I3_17_O I3=R1_LUT4_I3_16_O O=L1_LUT4_I3_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R1_LUT4_I3_14_O I1=R1_LUT4_I3_12_O I2=R1_LUT4_I3_13_O I3=R1_LUT4_I3_15_O O=L1_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_17_O_LUT4_I2_O I3=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_15_O I1=R1_LUT4_I3_13_O I2=R1_LUT4_I3_14_O I3=R1_LUT4_I3_12_O O=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_15_O I1=R1_LUT4_I3_13_O I2=R1_LUT4_I3_12_O I3=R1_LUT4_I3_14_O O=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L1_LUT4_I3_1_I2 I1=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=L1_LUT4_I3_1_I2_LUT4_I0_I2 I3=L1_LUT4_I3_19_I2_LUT4_O_I2 O=L1_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_1_I2_LUT4_I0_I2_LUT4_O_I1 I2=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_17_O_LUT4_I2_O O=L1_LUT4_I3_1_I2_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_1_I2_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=R1_LUT4_I3_16_O_LUT4_I2_O O=L1_LUT4_I3_1_I2_LUT4_I0_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 O=L1_LUT4_I3_1_I2_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_1_I2_LUT4_O_I1 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_1_I2_LUT4_O_I3 O=L1_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_16_O_LUT4_I2_O O=L1_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_I3 I2=R1_LUT4_I3_17_O_LUT4_I2_O I3=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_15_O I1=R1_LUT4_I3_14_O I2=R1_LUT4_I3_13_O I3=R1_LUT4_I3_12_O O=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_15_O I1=R1_LUT4_I3_14_O I2=R1_LUT4_I3_12_O I3=R1_LUT4_I3_13_O O=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_1_I2_LUT4_O_I3 I2=R1_LUT4_I3_16_O_LUT4_I2_O I3=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_I3 O=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_15_O I1=R1_LUT4_I3_12_O I2=R1_LUT4_I3_13_O I3=R1_LUT4_I3_14_O O=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O I1=L1_LUT4_I3_5_I0_LUT4_I1_I3_LUT4_O_I2 I2=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2 I3=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3 O=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_O I1=L1_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1 I2=L1_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_16_O_LUT4_I2_2_O O=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I0 I2=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I3=R1_LUT4_I3_17_O_LUT4_I2_O O=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_15_O I1=R1_LUT4_I3_14_O I2=R1_LUT4_I3_13_O I3=R1_LUT4_I3_12_O O=L1_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I3_2_I0 I1=L1_LUT4_I3_2_I1 I2=L1_LUT4_I3_2_I2 I3=L1(13) O=R2_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000111
+.subckt LUT4 I0=L1_LUT4_I3_25_I0 I1=L1_LUT4_I3_20_I1 I2=L1_LUT4_I3_20_I2 I3=L1(22) O=R2_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_20_I1_LUT4_O_I2 I3=L1_LUT4_I3_20_I1_LUT4_O_I3 O=L1_LUT4_I3_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L1_LUT4_I3_11_I2_LUT4_O_I2 I1=L1_LUT4_I3_25_I2_LUT4_O_I2 I2=L1_LUT4_I3_20_I1_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_20_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_20_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L1_LUT4_I3_20_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I1=R1_LUT4_I3_46_O_LUT4_I2_1_O I2=R1_LUT4_I3_46_O_LUT4_I2_O I3=L1_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_20_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_46_O_LUT4_I2_2_O O=L1_LUT4_I3_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_46_O_LUT4_I2_O O=L1_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_1_O I1=L1_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_25_I0_LUT4_O_I3 I1=L1_LUT4_I3_25_I0_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I2 I3=L1_LUT4_I3_20_I2_LUT4_O_I3 O=L1_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_46_O_LUT4_I2_O O=L1_LUT4_I3_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_46_O_LUT4_I2_1_O O=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_47_O_LUT4_I2_O O=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_44_O I1=R1_LUT4_I3_43_O I2=R1_LUT4_I3_42_O I3=R1_LUT4_I3_45_O O=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_45_O I1=R1_LUT4_I3_44_O I2=R1_LUT4_I3_43_O I3=R1_LUT4_I3_42_O O=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_47_O_LUT4_I2_O O=L1_LUT4_I3_20_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_46_O_LUT4_I2_2_O O=L1_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_O I1=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_46_O_LUT4_I2_1_O I3=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_43_O I1=R1_LUT4_I3_44_O I2=R1_LUT4_I3_45_O I3=R1_LUT4_I3_42_O O=L1_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L1_LUT4_I3_21_I0 I1=L1_LUT4_I3_21_I1 I2=L1_LUT4_I3_21_I2 I3=L1(23) O=R2_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L1_LUT4_I3_7_I0_LUT4_O_I0 I1=L1_LUT4_I3_3_I0_LUT4_O_I2 I2=L1_LUT4_I3_21_I0_LUT4_O_I2 I3=L1_LUT4_I3_21_I0_LUT4_O_I3 O=L1_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_40_O_LUT4_I2_2_O O=L1_LUT4_I3_21_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_38_O I1=R1_LUT4_I3_37_O I2=R1_LUT4_I3_36_O I3=R1_LUT4_I3_39_O O=L1_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_37_O I1=R1_LUT4_I3_38_O I2=R1_LUT4_I3_39_O I3=R1_LUT4_I3_36_O O=L1_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_41_O_LUT4_I2_O I1=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_1_O I3=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_21_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_36_O I1=R1_LUT4_I3_38_O I2=R1_LUT4_I3_37_O I3=R1_LUT4_I3_39_O O=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_37_O I1=R1_LUT4_I3_36_O I2=R1_LUT4_I3_39_O I3=R1_LUT4_I3_38_O O=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_7_I1 I1=L1_LUT4_I3_21_I1_LUT4_O_I1 I2=L1_LUT4_I3_21_I1_LUT4_O_I2 I3=L1_LUT4_I3_21_I1_LUT4_O_I3 O=L1_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_21_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_1_O I3=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_41_O_LUT4_I2_O I1=L1_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_2_O I3=L1_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_1_O I3=L1_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0 O=L1_LUT4_I3_21_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_40_O_LUT4_I2_O O=L1_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_41_O_LUT4_I2_O I1=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_40_O_LUT4_I2_2_O I3=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_3_I0_LUT4_O_I2 I2=L1_LUT4_I3_21_I2_LUT4_O_I2 I3=L1_LUT4_I3_3_I1_LUT4_O_I2 O=L1_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_41_O_LUT4_I2_O I1=L1_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I1 I3=R1_LUT4_I3_40_O_LUT4_I2_2_O O=L1_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I3 I2=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I3=R1_LUT4_I3_40_O_LUT4_I2_1_O O=L1_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_22_I0 I1=L1_LUT4_I3_22_I1 I2=L1_LUT4_I3_22_I2 I3=L1(26) O=R2_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L1_LUT4_I1_I3_LUT4_O_I2 I2=L1_LUT4_I3_22_I0_LUT4_O_I2 I3=L1_LUT4_I3_22_I0_LUT4_O_I3 O=L1_LUT4_I3_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I1_2_I2_LUT4_O_I2 O=L1_LUT4_I3_22_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O O=L1_LUT4_I3_22_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L1_LUT4_I3_22_I1_LUT4_O_I0 I1=L1_LUT4_I3_22_I1_LUT4_O_I1 I2=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O I3=L1_LUT4_I3_22_I1_LUT4_O_I3 O=L1_LUT4_I3_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 I1=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I2=R1_LUT4_I3_11_O I3=R1_LUT4_I3_10_O O=L1_LUT4_I3_22_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R1_LUT4_I3_9_O I1=R1_LUT4_I3_8_O I2=R1_LUT4_I3_7_O I3=R1_LUT4_I3_6_O O=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_9_O I1=R1_LUT4_I3_8_O I2=R1_LUT4_I3_6_O I3=R1_LUT4_I3_7_O O=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0 I1=R1_LUT4_I3_11_O_LUT4_I2_O I2=R1_LUT4_I3_10_O_LUT4_I2_1_O I3=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_22_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_O I1=L1_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R1_LUT4_I3_10_O_LUT4_I2_2_O I3=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0 O=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_I1 I2=R1_LUT4_I3_10_O_LUT4_I2_1_O I3=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0 O=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_2_O I1=L1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_11_O_LUT4_I2_O I3=L1_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O I2=R1_LUT4_I3_10_O_LUT4_I2_O I3=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 O=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_9_O I1=R1_LUT4_I3_8_O I2=R1_LUT4_I3_7_O I3=R1_LUT4_I3_6_O O=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_1_O I1=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 I3=R1_LUT4_I3_11_O_LUT4_I2_O O=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_6_O I1=R1_LUT4_I3_8_O I2=R1_LUT4_I3_7_O I3=R1_LUT4_I3_9_O O=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_22_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_O I1=L1_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 I2=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_10_O_LUT4_I2_1_O O=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_1_O I1=L1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_10_O_LUT4_I2_2_O I3=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_10_O_LUT4_I2_O O=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I2=R1_LUT4_I3_11_O_LUT4_I2_O I3=L1_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 O=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_8_O I1=R1_LUT4_I3_7_O I2=R1_LUT4_I3_9_O I3=R1_LUT4_I3_6_O O=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_2_O I1=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L1_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_11_O_LUT4_I2_O O=L1_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_22_I2_LUT4_O_I1 I2=L1_LUT4_I3_22_I2_LUT4_O_I2 I3=R1_LUT4_I3_10_O_LUT4_I2_1_O O=L1_LUT4_I3_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_10_O_LUT4_I2_2_O O=L1_LUT4_I3_22_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_10_O_LUT4_I2_O I1=L1_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L1_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I3=R1_LUT4_I3_11_O_LUT4_I2_O O=L1_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_9_O I1=R1_LUT4_I3_6_O I2=R1_LUT4_I3_7_O I3=R1_LUT4_I3_8_O O=L1_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_9_O I1=R1_LUT4_I3_8_O I2=R1_LUT4_I3_7_O I3=R1_LUT4_I3_6_O O=L1_LUT4_I3_22_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I3_I0 I1=L1_LUT4_I3_23_I1 I2=L1_LUT4_I3_23_I2 I3=L1(28) O=R2_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_I2_LUT4_O_I3 I2=L1_LUT4_I2_1_I3_LUT4_O_I1 I3=L1_LUT4_I3_2_I2 O=L1_LUT4_I3_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=L1_LUT4_I2_1_I3_LUT4_O_I2 I1=L1_LUT4_I3_2_I0_LUT4_O_I2 I2=L1_LUT4_I3_23_I2_LUT4_O_I2 I3=L1_LUT4_I3_23_I2_LUT4_O_I3 O=L1_LUT4_I3_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_23_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_23_O_LUT4_I2_O I3=L1_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_1_O I1=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I2=L1_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I0 I3=R1_LUT4_I3_22_O_LUT4_I2_O O=L1_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_23_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I3 I2=L1_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_22_O_LUT4_I2_1_O O=L1_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_23_O_LUT4_I2_O I1=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_22_O_LUT4_I2_O O=L1_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_9_I0 I1=L1_LUT4_I3_24_I1 I2=L1_LUT4_I3_24_I2 I3=L1(29) O=R2_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_24_I1_LUT4_O_I2 I3=L1_LUT4_I1_1_I3_LUT4_O_I2 O=L1_LUT4_I3_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_24_I1_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_29_O_LUT4_I2_O O=L1_LUT4_I3_24_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 I1=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R1_LUT4_I3_29_O I3=R1_LUT4_I3_28_O O=L1_LUT4_I3_24_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I1_1_I2_LUT4_O_I2 I3=L1_LUT4_I3_17_I1_LUT4_O_I1 O=L1_LUT4_I3_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L1_LUT4_I3_25_I0 I1=L1_LUT4_I3_25_I1 I2=L1_LUT4_I3_25_I2 I3=L1(32) O=R2_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_25_I0_LUT4_O_I1 I2=L1_LUT4_I3_25_I0_LUT4_O_I2 I3=L1_LUT4_I3_25_I0_LUT4_O_I3 O=L1_LUT4_I3_25_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_1_O I1=L1_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2 I2=L1_LUT4_I3_11_I0_LUT4_O_I1 I3=L1_LUT4_I3_25_I0_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_25_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_25_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_46_O_LUT4_I2_O O=L1_LUT4_I3_25_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L1_LUT4_I3_20_I2_LUT4_O_I3 I1=L1_LUT4_I3_14_I2_LUT4_O_I1 I2=L1_LUT4_I3_11_I0_LUT4_O_I2 I3=L1_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_25_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=L1_LUT4_I3_25_I2_LUT4_O_I0_LUT4_O_I1 I3=R1_LUT4_I3_46_O_LUT4_I2_O O=L1_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_1_O I1=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_11_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_25_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_25_I0_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_25_I0_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_20_I2_LUT4_O_I2 O=L1_LUT4_I3_25_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_46_O_LUT4_I2_O I3=L1_LUT4_I3_25_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_25_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_43_O I1=R1_LUT4_I3_42_O I2=R1_LUT4_I3_45_O I3=R1_LUT4_I3_44_O O=L1_LUT4_I3_25_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I3 I1=R1_LUT4_I3_46_O_LUT4_I2_1_O I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_25_I2_LUT4_O_I0_LUT4_O_I1 O=L1_LUT4_I3_25_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_11_I0_LUT4_O_I2 I2=L1_LUT4_I3_14_I2_LUT4_O_I1 I3=L1_LUT4_I3_25_I0_LUT4_O_I1 O=L1_LUT4_I3_25_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L1_LUT4_I3_25_I2_LUT4_O_I0 I1=L1_LUT4_I3_11_I2 I2=L1_LUT4_I3_25_I2_LUT4_O_I2 I3=L1_LUT4_I3_25_I2_LUT4_O_I3 O=L1_LUT4_I3_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I2 I1=L1_LUT4_I3_25_I2_LUT4_O_I0_LUT4_O_I1 I2=R1_LUT4_I3_47_O I3=R1_LUT4_I3_46_O O=L1_LUT4_I3_25_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R1_LUT4_I3_45_O I1=R1_LUT4_I3_43_O I2=R1_LUT4_I3_42_O I3=R1_LUT4_I3_44_O O=L1_LUT4_I3_25_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_25_I2_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_25_I2_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_25_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_O I1=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_11_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_25_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_2_O I1=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_46_O_LUT4_I2_1_O I3=L1_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_25_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_46_O_LUT4_I2_O I1=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_47_O_LUT4_I2_O I3=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_25_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_44_O I1=R1_LUT4_I3_42_O I2=R1_LUT4_I3_43_O I3=R1_LUT4_I3_45_O O=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_44_O I1=R1_LUT4_I3_45_O I2=R1_LUT4_I3_43_O I3=R1_LUT4_I3_42_O O=L1_LUT4_I3_25_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L1_LUT4_I3_2_I0_LUT4_O_I0 I1=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L1_LUT4_I3_2_I0_LUT4_O_I2 I3=L1_LUT4_I3_2_I0_LUT4_O_I3 O=L1_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_I1_LUT4_O_I2 I2=L1_LUT4_I3_23_I2_LUT4_O_I3 I3=L1_LUT4_I2_1_I3_LUT4_O_I2 O=L1_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L1_LUT4_I3_2_I1_LUT4_O_I2 I1=R1_LUT4_I3_23_O_LUT4_I2_O I2=R1_LUT4_I3_22_O_LUT4_I2_O I3=L1_LUT4_I3_2_I1_LUT4_O_I1 O=L1_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I0 I2=L1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_22_O_LUT4_I2_1_O O=L1_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I0 I1=R1_LUT4_I3_22_O_LUT4_I2_O I2=R1_LUT4_I3_23_O_LUT4_I2_O I3=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_21_O I1=R1_LUT4_I3_20_O I2=R1_LUT4_I3_19_O I3=R1_LUT4_I3_18_O O=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_21_O I1=R1_LUT4_I3_20_O I2=R1_LUT4_I3_19_O I3=R1_LUT4_I3_18_O O=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_2_I0_LUT4_O_I3 I2=L1_LUT4_I3_2_I1 I3=L1_LUT4_I3_2_I0_LUT4_O_I2 O=L1_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_2_I1_LUT4_O_I1 I2=L1_LUT4_I3_2_I1_LUT4_O_I2 I3=R1_LUT4_I3_22_O_LUT4_I2_1_O O=L1_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_21_O I1=R1_LUT4_I3_20_O I2=R1_LUT4_I3_19_O I3=R1_LUT4_I3_18_O O=L1_LUT4_I3_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R1_LUT4_I3_21_O I1=R1_LUT4_I3_20_O I2=R1_LUT4_I3_18_O I3=R1_LUT4_I3_19_O O=L1_LUT4_I3_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L1_LUT4_I3_2_I2_LUT4_O_I0 I1=L1_LUT4_I3_2_I2_LUT4_O_I1 I2=L1_LUT4_I2_1_I3_LUT4_O_I3 I3=L1_LUT4_I3_2_I2_LUT4_O_I3 O=L1_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L1_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I0 I1=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I2=R1_LUT4_I3_22_O I3=R1_LUT4_I3_23_O O=L1_LUT4_I3_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R1_LUT4_I3_19_O I1=R1_LUT4_I3_20_O I2=R1_LUT4_I3_21_O I3=R1_LUT4_I3_18_O O=L1_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_23_O_LUT4_I2_O I3=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I0 O=L1_LUT4_I3_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_22_O_LUT4_I2_2_O O=L1_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_1_O I1=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=R1_LUT4_I3_22_O_LUT4_I2_O O=L1_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_1_O I1=L1_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_22_O_LUT4_I2_O I3=L1_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_21_O I1=R1_LUT4_I3_19_O I2=R1_LUT4_I3_18_O I3=R1_LUT4_I3_20_O O=L1_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_20_O I1=R1_LUT4_I3_18_O I2=R1_LUT4_I3_19_O I3=R1_LUT4_I3_21_O O=L1_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_3_I0 I1=L1_LUT4_I3_3_I1 I2=L1_LUT4_I3_3_I2 I3=L1(17) O=R2_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L1_LUT4_I3_7_I0_LUT4_O_I0 I1=L1_LUT4_I3_3_I0_LUT4_O_I1 I2=L1_LUT4_I3_3_I0_LUT4_O_I2 I3=L1_LUT4_I3_3_I0_LUT4_O_I3 O=L1_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L1_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I1=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 I2=R1_LUT4_I3_41_O I3=R1_LUT4_I3_40_O O=L1_LUT4_I3_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_40_O_LUT4_I2_1_O I3=L1_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_41_O_LUT4_I2_O I1=L1_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_40_O_LUT4_I2_2_O I3=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_1_O I3=L1_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_39_O I1=R1_LUT4_I3_37_O I2=R1_LUT4_I3_38_O I3=R1_LUT4_I3_36_O O=L1_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_3_I1_LUT4_O_I2 I3=L1_LUT4_I3_3_I1_LUT4_O_I3 O=L1_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_2_O I1=L1_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_40_O_LUT4_I2_1_O O=L1_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_39_O I1=R1_LUT4_I3_36_O I2=R1_LUT4_I3_37_O I3=R1_LUT4_I3_38_O O=L1_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_41_O_LUT4_I2_O I3=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 O=L1_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_O I3=L1_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0 O=L1_LUT4_I3_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3 I3=R1_LUT4_I3_41_O_LUT4_I2_O O=L1_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_2_O I1=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_1_O I3=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_3_I2_LUT4_O_I2 I3=L1_LUT4_I3_7_I1_LUT4_O_I3 O=L1_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_41_O_LUT4_I2_O I1=L1_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_13_I1_LUT4_O_I1 O=L1_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R1_LUT4_I3_39_O I1=R1_LUT4_I3_38_O I2=R1_LUT4_I3_37_O I3=R1_LUT4_I3_36_O O=L1_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I3=R1_LUT4_I3_40_O_LUT4_I2_1_O O=L1_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L1_LUT4_I3_4_I0 I1=L1_LUT4_I3_4_I1 I2=L1_LUT4_I3_4_I2 I3=L1(24) O=R2_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L1_LUT4_I3_4_I0_LUT4_O_I0 I1=R1_LUT4_I3_34_O_LUT4_I2_O I2=L1_LUT4_I3_4_I0_LUT4_O_I2 I3=L1_LUT4_I3_4_I0_LUT4_O_I3 O=L1_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R1_LUT4_I3_33_O I1=R1_LUT4_I3_32_O I2=R1_LUT4_I3_30_O I3=R1_LUT4_I3_31_O O=L1_LUT4_I3_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_2_O I1=R1_LUT4_I3_35_O_LUT4_I2_O I2=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R1_LUT4_I3_32_O I1=R1_LUT4_I3_31_O I2=R1_LUT4_I3_33_O I3=R1_LUT4_I3_30_O O=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_35_O_LUT4_I2_O I1=L1_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2 I2=R1_LUT4_I3_34_O_LUT4_I2_2_O I3=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_32_O I1=R1_LUT4_I3_31_O I2=R1_LUT4_I3_30_O I3=R1_LUT4_I3_33_O O=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L1_LUT4_I3_6_I1_LUT4_O_I0 I1=L1_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_35_O I3=R1_LUT4_I3_34_O O=L1_LUT4_I3_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100111111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 I3=R1_LUT4_I3_34_O_LUT4_I2_1_O O=L1_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=R1_LUT4_I3_33_O I1=R1_LUT4_I3_30_O I2=R1_LUT4_I3_31_O I3=R1_LUT4_I3_32_O O=L1_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_4_I1_LUT4_I2_I0 I1=L1_LUT4_I3_6_I0 I2=L1_LUT4_I3_4_I1 I3=L1_LUT4_I3_16_I1_LUT4_O_I1 O=L1_LUT4_I3_10_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_4_I1_LUT4_O_I1 I2=R1_LUT4_I3_34_O_LUT4_I2_O I3=L1_LUT4_I3_4_I1_LUT4_O_I3 O=L1_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_35_O_LUT4_I2_O O=L1_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_31_O I1=R1_LUT4_I3_30_O I2=R1_LUT4_I3_33_O I3=R1_LUT4_I3_32_O O=L1_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_33_O I1=R1_LUT4_I3_32_O I2=R1_LUT4_I3_31_O I3=R1_LUT4_I3_30_O O=L1_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I3_6_I0 I1=L1_LUT4_I3_4_I2_LUT4_O_I1 I2=L1_LUT4_I3_4_I2_LUT4_O_I2 I3=L1_LUT4_I3_16_I2 O=L1_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_4_I1_LUT4_O_I3 I3=R1_LUT4_I3_34_O_LUT4_I2_1_O O=L1_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_35_O_LUT4_I2_O O=L1_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_2_O I1=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3 I2=R1_LUT4_I3_34_O_LUT4_I2_O I3=L1_LUT4_I3_10_I2_LUT4_I3_I1_LUT4_O_I3 O=L1_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_5_I0 I1=L1_LUT4_I3_5_I1 I2=L1_LUT4_I3_5_I2 I3=L1(27) O=R2_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L1_LUT4_I3_5_I0 I1=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I2=L1_LUT4_I3_5_I1_LUT4_O_I3 I3=L1_LUT4_I3_5_I1_LUT4_O_I1 O=L1_LUT4_I3_5_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I3_5_I1_LUT4_O_I3 I1=L1_LUT4_I3_5_I0 I2=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L1_LUT4_I3_5_I0_LUT4_I1_I3 O=L1_LUT4_I3_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_5_I0_LUT4_I1_I3_LUT4_O_I2 I3=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O O=L1_LUT4_I3_5_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_17_O_LUT4_I2_O I1=L1_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L1_LUT4_I3_5_I0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_5_I0_LUT4_O_I2 I3=L1_LUT4_I3_5_I0_LUT4_O_I3 O=L1_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_5_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_16_O_LUT4_I2_O I3=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I0 O=L1_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_13_O I1=R1_LUT4_I3_14_O I2=R1_LUT4_I3_15_O I3=R1_LUT4_I3_12_O O=L1_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_17_O_LUT4_I2_O I1=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I0 O=L1_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I0 I2=R1_LUT4_I3_16_O_LUT4_I2_O I3=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_17_O_LUT4_I2_O I1=L1_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 O=L1_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_1_I0_LUT4_O_I1 I1=L1_LUT4_I3_5_I1_LUT4_O_I1 I2=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L1_LUT4_I3_5_I1_LUT4_O_I3 O=L1_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I0 I1=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_16_O_LUT4_I2_O I3=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_5_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R1_LUT4_I3_12_O I1=R1_LUT4_I3_14_O I2=R1_LUT4_I3_13_O I3=R1_LUT4_I3_15_O O=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_14_O I1=R1_LUT4_I3_13_O I2=R1_LUT4_I3_15_O I3=R1_LUT4_I3_12_O O=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I1=R1_LUT4_I3_16_O_LUT4_I2_2_O I2=R1_LUT4_I3_17_O_LUT4_I2_O I3=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I0 I1=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_5_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R1_LUT4_I3_13_O I1=R1_LUT4_I3_12_O I2=R1_LUT4_I3_15_O I3=R1_LUT4_I3_14_O O=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_14_O I1=R1_LUT4_I3_13_O I2=R1_LUT4_I3_12_O I3=R1_LUT4_I3_15_O O=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L1_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=R1_LUT4_I3_16_O_LUT4_I2_O I2=R1_LUT4_I3_16_O_LUT4_I2_1_O I3=L1_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_5_I2_LUT4_O_I1 I2=L1_LUT4_I3_5_I2_LUT4_O_I2 I3=L1_LUT4_I3_5_I2_LUT4_O_I3 O=L1_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_O I1=L1_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_17_O_LUT4_I2_O I3=L1_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_14_O I1=R1_LUT4_I3_15_O I2=R1_LUT4_I3_13_O I3=R1_LUT4_I3_12_O O=L1_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_I3 O=L1_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_16_O_LUT4_I2_O I3=L1_LUT4_I3_1_I2_LUT4_O_I3 O=L1_LUT4_I3_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_17_O_LUT4_I2_O I3=L1_LUT4_I3_1_I2_LUT4_O_I3_LUT4_I1_I3 O=L1_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_1_O I1=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=R1_LUT4_I3_16_O_LUT4_I2_2_O I3=L1_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_16_O_LUT4_I2_O I1=L1_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=L1_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_17_O_LUT4_I2_O O=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_15_O I1=R1_LUT4_I3_14_O I2=R1_LUT4_I3_13_O I3=R1_LUT4_I3_12_O O=L1_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=L1_LUT4_I3_1_I2_LUT4_I0_I2 O=L1_LUT4_I3_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L1_LUT4_I3_6_I0 I1=L1_LUT4_I3_6_I1 I2=L1_LUT4_I3_6_I2 I3=L1(30) O=R2_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_6_I0_LUT4_O_I1 I2=L1_LUT4_I3_6_I0_LUT4_O_I2 I3=R1_LUT4_I3_35_O_LUT4_I2_O O=L1_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_16_I2_LUT4_O_I2 I3=R1_LUT4_I3_34_O_LUT4_I2_O O=L1_LUT4_I3_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_2_O I1=L1_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2 I2=R1_LUT4_I3_34_O_LUT4_I2_1_O I3=L1_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I1 O=L1_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_33_O I1=R1_LUT4_I3_32_O I2=R1_LUT4_I3_31_O I3=R1_LUT4_I3_30_O O=L1_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L1_LUT4_I3_6_I1_LUT4_O_I0 I1=L1_LUT4_I3_6_I1_LUT4_O_I1 I2=R1_LUT4_I3_34_O I3=R1_LUT4_I3_35_O O=L1_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R1_LUT4_I3_33_O I1=R1_LUT4_I3_31_O I2=R1_LUT4_I3_32_O I3=R1_LUT4_I3_30_O O=L1_LUT4_I3_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_6_I1_LUT4_O_I1 I1=R1_LUT4_I3_34_O_LUT4_I2_2_O I2=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1 I3=R1_LUT4_I3_34_O_LUT4_I2_1_O O=L1_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_33_O I1=R1_LUT4_I3_32_O I2=R1_LUT4_I3_31_O I3=R1_LUT4_I3_30_O O=L1_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L1_LUT4_I3_6_I2_LUT4_O_I0 I1=L1_LUT4_I3_6_I2_LUT4_O_I1 I2=L1_LUT4_I3_4_I2_LUT4_O_I1 I3=L1_LUT4_I3_16_I1 O=L1_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R1_LUT4_I3_34_O_LUT4_I2_2_O I1=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1 I2=R1_LUT4_I3_34_O_LUT4_I2_1_O I3=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3 O=L1_LUT4_I3_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_33_O I1=R1_LUT4_I3_32_O I2=R1_LUT4_I3_31_O I3=R1_LUT4_I3_30_O O=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_30_O I1=R1_LUT4_I3_32_O I2=R1_LUT4_I3_31_O I3=R1_LUT4_I3_33_O O=L1_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_10_I1_LUT4_I2_I1 I3=L1_LUT4_I3_4_I0_LUT4_O_I2 O=L1_LUT4_I3_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L1_LUT4_I3_7_I0 I1=L1_LUT4_I3_7_I1 I2=L1_LUT4_I3_7_I2 I3=L1(31) O=R2_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L1_LUT4_I3_7_I0_LUT4_O_I0 I1=L1_LUT4_I3_7_I0_LUT4_O_I1 I2=L1_LUT4_I3_7_I0_LUT4_O_I2 I3=L1_LUT4_I3_3_I1_LUT4_O_I3 O=L1_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L1_LUT4_I3_3_I1_LUT4_O_I3 I1=L1_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1 I2=L1_LUT4_I3_3_I1_LUT4_O_I2 I3=L1_LUT4_I3_21_I2_LUT4_O_I2 O=L1_LUT4_I3_7_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_2_O I3=L1_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0 O=L1_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L1_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 I1=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 I2=R1_LUT4_I3_40_O I3=R1_LUT4_I3_41_O O=L1_LUT4_I3_7_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=R1_LUT4_I3_41_O_LUT4_I2_O I1=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_2_O I3=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_39_O I1=R1_LUT4_I3_37_O I2=R1_LUT4_I3_36_O I3=R1_LUT4_I3_38_O O=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_39_O I1=R1_LUT4_I3_38_O I2=R1_LUT4_I3_37_O I3=R1_LUT4_I3_36_O O=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_7_I1_LUT4_O_I1 I2=L1_LUT4_I3_7_I1_LUT4_O_I2 I3=L1_LUT4_I3_7_I1_LUT4_O_I3 O=L1_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_2_O I1=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_1_O I3=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_38_O I1=R1_LUT4_I3_36_O I2=R1_LUT4_I3_37_O I3=R1_LUT4_I3_39_O O=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_38_O I1=R1_LUT4_I3_39_O I2=R1_LUT4_I3_37_O I3=R1_LUT4_I3_36_O O=L1_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_41_O_LUT4_I2_O O=L1_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3 I2=R1_LUT4_I3_40_O_LUT4_I2_2_O I3=L1_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_39_O I1=R1_LUT4_I3_38_O I2=R1_LUT4_I3_36_O I3=R1_LUT4_I3_37_O O=L1_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_38_O I1=R1_LUT4_I3_37_O I2=R1_LUT4_I3_39_O I3=R1_LUT4_I3_36_O O=L1_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0 I1=R1_LUT4_I3_41_O_LUT4_I2_O I2=L1_LUT4_I3_21_I1_LUT4_O_I1 I3=L1_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R1_LUT4_I3_39_O I1=R1_LUT4_I3_38_O I2=R1_LUT4_I3_37_O I3=R1_LUT4_I3_36_O O=L1_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_40_O_LUT4_I2_1_O O=L1_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3 I2=R1_LUT4_I3_40_O_LUT4_I2_2_O I3=L1_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_7_I2 I2=L1_LUT4_I3_3_I2_LUT4_O_I2 I3=L1_LUT4_I3_21_I1_LUT4_O_I3 O=L1_LUT4_I3_21_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_7_I2_LUT4_O_I2 I3=L1_LUT4_I3_7_I2_LUT4_O_I3 O=L1_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_2_O I3=L1_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1 I2=L1_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 I3=R1_LUT4_I3_41_O_LUT4_I2_O O=L1_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_40_O_LUT4_I2_O I1=L1_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_40_O_LUT4_I2_1_O O=L1_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_39_O I1=R1_LUT4_I3_38_O I2=R1_LUT4_I3_37_O I3=R1_LUT4_I3_36_O O=L1_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R1_LUT4_I3_41_O_LUT4_I2_O I1=L1_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I2=R1_LUT4_I3_40_O_LUT4_I2_1_O I3=L1_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_39_O I1=R1_LUT4_I3_38_O I2=R1_LUT4_I3_37_O I3=R1_LUT4_I3_36_O O=L1_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_8_I0 I1=L1_LUT4_I3_8_I1 I2=L1_LUT4_I3_8_I2 I3=L1(3) O=R2_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_15_I2 I2=L1_LUT4_I2_2_I3_LUT4_O_I1 I3=L1_LUT4_I2_2_I3_LUT4_O_I0 O=L1_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_8_I1_LUT4_O_I2 I3=L1_LUT4_I3_8_I1_LUT4_O_I3 O=L1_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I2_1_O I3=L1_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I3_O I1=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_O_LUT4_I2_1_O O=L1_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_5_O I1=R1_LUT4_I3_3_O I2=R1_LUT4_I3_4_O I3=R1_LUT4_I3_2_O O=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I3_O I1=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I2_2_O O=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_5_O I1=R1_LUT4_I3_4_O I2=R1_LUT4_I3_3_O I3=R1_LUT4_I3_2_O O=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_5_O I1=R1_LUT4_I3_4_O I2=R1_LUT4_I3_3_O I3=R1_LUT4_I3_2_O O=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L1_LUT4_I3_15_I2_LUT4_O_I0 I1=R1_LUT4_I3_O_LUT4_I2_1_O I2=R1_LUT4_I3_O_LUT4_I3_O I3=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_O_LUT4_I2_2_O O=L1_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_15_I1_LUT4_O_I2 O=L1_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I3_O I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I2_2_O I3=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I2_1_O O=L1_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_5_O I1=R1_LUT4_I3_4_O I2=R1_LUT4_I3_2_O I3=R1_LUT4_I3_3_O O=L1_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_8_I2_LUT4_O_I1 I2=L1_LUT4_I3_8_I2_LUT4_O_I2 I3=L1_LUT4_I3_8_I2_LUT4_O_I3 O=L1_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=L1_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I3_O O=L1_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_4_O I1=R1_LUT4_I3_3_O I2=R1_LUT4_I3_5_O I3=R1_LUT4_I3_2_O O=L1_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_2_O I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_O_LUT4_I2_1_O I3=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L1_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_O_LUT4_I2_2_O I3=L1_LUT4_I3_15_I2_LUT4_O_I0 O=L1_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=R1_LUT4_I3_O_LUT4_I2_1_O O=L1_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_O_LUT4_I2_O I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=L1_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_O_LUT4_I3_O O=L1_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3 I2=L1_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2 I3=L1_LUT4_I3_15_I0_LUT4_O_I2 O=L1_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L1_LUT4_I3_9_I0 I1=L1_LUT4_I3_9_I1 I2=L1_LUT4_I3_9_I2 I3=L1(4) O=R2_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_9_I0_LUT4_O_I1 I2=L1_LUT4_I1_1_I2 I3=L1_LUT4_I3_9_I0_LUT4_O_I3 O=L1_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_28_O_LUT4_I2_1_O I3=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_26_O I1=R1_LUT4_I3_25_O I2=R1_LUT4_I3_27_O I3=R1_LUT4_I3_24_O O=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_27_O I1=R1_LUT4_I3_25_O I2=R1_LUT4_I3_24_O I3=R1_LUT4_I3_26_O O=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R1_LUT4_I3_29_O_LUT4_I2_O I1=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_28_O_LUT4_I2_2_O O=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_27_O I1=R1_LUT4_I3_25_O I2=R1_LUT4_I3_26_O I3=R1_LUT4_I3_24_O O=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L1_LUT4_I3_17_I1_LUT4_O_I1 I1=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_9_I1_LUT4_O_I1 O=L1_LUT4_I3_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L1_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3 I1=L1_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_29_O I3=R1_LUT4_I3_28_O O=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_28_O_LUT4_I2_1_O I3=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_26_O I1=R1_LUT4_I3_27_O I2=R1_LUT4_I3_25_O I3=R1_LUT4_I3_24_O O=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_24_O I1=R1_LUT4_I3_26_O I2=R1_LUT4_I3_25_O I3=R1_LUT4_I3_27_O O=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_9_I1_LUT4_O_I1 I2=L1_LUT4_I3_9_I1_LUT4_O_I2 I3=L1_LUT4_I3_9_I0_LUT4_O_I1 O=L1_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I1_1_I2_LUT4_O_I0 I3=R1_LUT4_I3_28_O_LUT4_I2_O O=L1_LUT4_I3_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I0 I3=R1_LUT4_I3_28_O_LUT4_I2_1_O O=L1_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_29_O_LUT4_I2_O I1=L1_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R1_LUT4_I3_28_O_LUT4_I2_2_O I3=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 O=L1_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I3=L1_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 O=L1_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L1_LUT4_I3_9_I2_LUT4_O_I0 I1=L1_LUT4_I3_9_I2_LUT4_O_I1 I2=L1_LUT4_I3_9_I2_LUT4_O_I2 I3=L1_LUT4_I3_9_I2_LUT4_O_I3 O=L1_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=L1_LUT4_I3_24_I1_LUT4_O_I2 I1=L1_LUT4_I3_17_I2_LUT4_O_I2 I2=L1_LUT4_I3_9_I2_LUT4_O_I1 I3=L1_LUT4_I1_1_I3_LUT4_O_I3 O=L1_LUT4_I3_9_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I2 I3=L1_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3 O=L1_LUT4_I3_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I2=R1_LUT4_I3_28_O_LUT4_I2_2_O I3=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_29_O_LUT4_I2_O I1=L1_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_28_O_LUT4_I2_1_O O=L1_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_29_O_LUT4_I2_O I1=L1_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 I2=L1_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_28_O_LUT4_I2_2_O O=L1_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_27_O I1=R1_LUT4_I3_24_O I2=R1_LUT4_I3_25_O I3=R1_LUT4_I3_26_O O=L1_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_28_O_LUT4_I2_O I1=L1_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L1_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 I3=R1_LUT4_I3_28_O_LUT4_I2_1_O O=L1_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_25_O I1=R1_LUT4_I3_24_O I2=R1_LUT4_I3_27_O I3=R1_LUT4_I3_26_O O=L1_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_27_O I1=R1_LUT4_I3_26_O I2=R1_LUT4_I3_25_O I3=R1_LUT4_I3_24_O O=L1_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L1_LUT4_I3_I0_LUT4_O_I0 I1=L1_LUT4_I3_I0_LUT4_O_I1 I2=L1_LUT4_I3_I0_LUT4_O_I2 I3=L1_LUT4_I3_23_I2 O=L1_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L1_LUT4_I3_I1_LUT4_O_I1 O=L1_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_1_O I1=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_23_O_LUT4_I2_O O=L1_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_21_O I1=R1_LUT4_I3_19_O I2=R1_LUT4_I3_20_O I3=R1_LUT4_I3_18_O O=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_19_O I1=R1_LUT4_I3_18_O I2=R1_LUT4_I3_21_O I3=R1_LUT4_I3_20_O O=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_2_I1_LUT4_O_I2 I2=L1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2 I3=R1_LUT4_I3_22_O_LUT4_I2_O O=L1_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_20_O I1=R1_LUT4_I3_21_O I2=R1_LUT4_I3_19_O I3=R1_LUT4_I3_18_O O=L1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_I1_LUT4_O_I1 I2=L1_LUT4_I3_I1_LUT4_O_I2 I3=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2 I3=L1_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 O=L1_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R1_LUT4_I3_22_O_LUT4_I2_O I3=L1_LUT4_I3_2_I1_LUT4_O_I2 O=L1_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_18_O I1=R1_LUT4_I3_20_O I2=R1_LUT4_I3_19_O I3=R1_LUT4_I3_21_O O=L1_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_1_O I1=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 I2=R1_LUT4_I3_23_O_LUT4_I2_O I3=L1_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_I2_LUT4_O_I1 I2=L1_LUT4_I3_I2_LUT4_O_I2 I3=L1_LUT4_I3_I2_LUT4_O_I3 O=L1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_2_I1_LUT4_O_I1 I3=R1_LUT4_I3_22_O_LUT4_I2_1_O O=L1_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R1_LUT4_I3_22_O_LUT4_I2_2_O O=L1_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_23_O_LUT4_I2_O I1=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=L1_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_22_O_LUT4_I2_O O=L1_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0 I1=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_2_I2_LUT4_O_I1 I3=L1_LUT4_I2_1_I3_LUT4_O_I3 O=L1_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=L1_LUT4_I3_2_I1_LUT4_O_I1 I2=R1_LUT4_I3_22_O I3=R1_LUT4_I3_23_O O=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 I2=R1_LUT4_I3_23_O_LUT4_I2_O I3=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=L1_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R1_LUT4_I3_22_O_LUT4_I2_O O=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O I2=R1_LUT4_I3_22_O_LUT4_I2_1_O I3=L1_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I0 O=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R1_LUT4_I3_21_O I1=R1_LUT4_I3_20_O I2=R1_LUT4_I3_19_O I3=R1_LUT4_I3_18_O O=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1 I2=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R1_LUT4_I3_22_O_LUT4_I2_O O=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_21_O I1=R1_LUT4_I3_20_O I2=R1_LUT4_I3_19_O I3=R1_LUT4_I3_18_O O=L1_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_2_O I1=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L1_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1 I3=R1_LUT4_I3_23_O_LUT4_I2_O O=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_20_O I1=R1_LUT4_I3_19_O I2=R1_LUT4_I3_21_O I3=R1_LUT4_I3_18_O O=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R1_LUT4_I3_22_O_LUT4_I2_1_O I1=L1_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I0 I2=R1_LUT4_I3_22_O_LUT4_I2_O I3=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R1_LUT4_I3_20_O I1=R1_LUT4_I3_19_O I2=R1_LUT4_I3_18_O I3=R1_LUT4_I3_21_O O=L1_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=L1(1) D=R0(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(2) D=R0(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(11) D=R0(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(12) D=R0(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(13) D=R0(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(14) D=R0(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(15) D=R0(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(16) D=R0(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(17) D=R0(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(18) D=R0(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(19) D=R0(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(20) D=R0(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(3) D=R0(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(21) D=R0(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(22) D=R0(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(23) D=R0(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(24) D=R0(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(25) D=R0(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(26) D=R0(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(27) D=R0(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(28) D=R0(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(29) D=R0(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(30) D=R0(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(4) D=R0(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(31) D=R0(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(32) D=R0(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(5) D=R0(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(6) D=R0(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(7) D=R0(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(8) D=R0(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(9) D=R0(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L1(10) D=R0(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:116.1-117.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L2(10) I2=L2_LUT4_I1_I2 I3=L2_LUT4_I1_I3 O=R3_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L2(11) I2=L2_LUT4_I1_1_I2 I3=L2_LUT4_I1_1_I3 O=R3_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L2_LUT4_I1_1_I2_LUT4_O_I0 I1=R2_LUT4_I3_28_O_LUT4_I2_2_O I2=L2_LUT4_I1_1_I2_LUT4_O_I2 I3=L2_LUT4_I1_1_I2_LUT4_O_I3 O=L2_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R2_LUT4_I3_27_O I1=R2_LUT4_I3_26_O I2=R2_LUT4_I3_25_O I3=R2_LUT4_I3_24_O O=L2_LUT4_I1_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_17_I1_LUT4_O_I2 O=L2_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_24_O I1=R2_LUT4_I3_26_O I2=R2_LUT4_I3_25_O I3=R2_LUT4_I3_27_O O=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_27_O I1=R2_LUT4_I3_26_O I2=R2_LUT4_I3_25_O I3=R2_LUT4_I3_24_O O=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_1_O I1=L2_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I1 I2=R2_LUT4_I3_28_O_LUT4_I2_2_O I3=L2_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2 O=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2 O=L2_LUT4_I1_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I1 I2=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_28_O_LUT4_I2_1_O O=L2_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I1_1_I3_LUT4_O_I0 I1=L2_LUT4_I1_1_I3_LUT4_O_I1 I2=L2_LUT4_I1_1_I3_LUT4_O_I2 I3=L2_LUT4_I3_9_I2_LUT4_O_I1 O=L2_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I1_1_I2_LUT4_O_I0 I1=L2_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I1 I2=R2_LUT4_I3_29_O I3=R2_LUT4_I3_28_O O=L2_LUT4_I1_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R2_LUT4_I3_27_O I1=R2_LUT4_I3_26_O I2=R2_LUT4_I3_24_O I3=R2_LUT4_I3_25_O O=L2_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_28_O_LUT4_I2_2_O I3=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_27_O I1=R2_LUT4_I3_26_O I2=R2_LUT4_I3_25_O I3=R2_LUT4_I3_24_O O=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_26_O I1=R2_LUT4_I3_25_O I2=R2_LUT4_I3_27_O I3=R2_LUT4_I3_24_O O=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L2_LUT4_I3_9_I2_LUT4_O_I2 I1=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_29_O_LUT4_I2_O O=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_1_O I1=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_28_O_LUT4_I2_2_O O=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_25_O I1=R2_LUT4_I3_24_O I2=R2_LUT4_I3_27_O I3=R2_LUT4_I3_26_O O=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_1_O I1=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R2_LUT4_I3_28_O_LUT4_I2_2_O O=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_27_O I1=R2_LUT4_I3_25_O I2=R2_LUT4_I3_26_O I3=R2_LUT4_I3_24_O O=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L2(1) I2=L2_LUT4_I1_2_I2 I3=L2_LUT4_I1_2_I3 O=R3_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=L2_LUT4_I1_2_I2_LUT4_O_I0 I1=L2_LUT4_I1_2_I2_LUT4_O_I1 I2=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O I3=L2_LUT4_I3_22_I1 O=L2_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2 I3=L2_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I3 O=L2_LUT4_I1_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_11_O_LUT4_I2_O I3=L2_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_8_O I1=R2_LUT4_I3_6_O I2=R2_LUT4_I3_7_O I3=R2_LUT4_I3_9_O O=L2_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_1_O I1=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_2_O O=L2_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I1_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_11_O_LUT4_I2_O O=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_7_O I1=R2_LUT4_I3_6_O I2=R2_LUT4_I3_9_O I3=R2_LUT4_I3_8_O O=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_9_O I1=R2_LUT4_I3_8_O I2=R2_LUT4_I3_6_O I3=R2_LUT4_I3_7_O O=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_1_O I1=L2_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I2=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_10_O_LUT4_I2_2_O O=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L2_LUT4_I1_2_I3_LUT4_O_I2 I3=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_O O=L2_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_22_I2_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_1_O O=L2_LUT4_I1_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0 I3=R2_LUT4_I3_10_O_LUT4_I2_O O=L2_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_2_O I1=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R2_LUT4_I3_11_O_LUT4_I2_O I3=L2_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=L2_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2(21) I2=L2_LUT4_I1_3_I2 I3=L2_LUT4_I1_3_I3 O=R3_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_3_I2_LUT4_O_I1 I2=L2_LUT4_I1_3_I2_LUT4_O_I2 I3=L2_LUT4_I3_5_I2_LUT4_O_I0 O=L2_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_O I1=L2_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I1_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_17_O_LUT4_I2_O I3=L2_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I1_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_17_O_LUT4_I2_O I1=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_15_O I1=R2_LUT4_I3_14_O I2=R2_LUT4_I3_13_O I3=R2_LUT4_I3_12_O O=L2_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_15_O I1=R2_LUT4_I3_14_O I2=R2_LUT4_I3_13_O I3=R2_LUT4_I3_12_O O=L2_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_3_I3_LUT4_O_I1 I2=L2_LUT4_I2_1_I3_LUT4_O_I0 I3=L2_LUT4_I1_3_I3_LUT4_O_I3 O=L2_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I1_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I3 I2=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R2_LUT4_I3_16_O_LUT4_I2_2_O O=L2_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_O I1=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_17_O_LUT4_I2_O O=L2_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3 I3=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O O=L2_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=L2(30) I2=L2_LUT4_I1_4_I2 I3=L2_LUT4_I1_4_I3 O=R3_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_4_I2_LUT4_O_I1 I2=L2_LUT4_I1_4_I2_LUT4_O_I2 I3=R2_LUT4_I3_34_O_LUT4_I2_2_O O=L2_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_34_O_LUT4_I2_O I3=L2_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_32_O I1=R2_LUT4_I3_31_O I2=R2_LUT4_I3_30_O I3=R2_LUT4_I3_33_O O=L2_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_32_O I1=R2_LUT4_I3_33_O I2=R2_LUT4_I3_31_O I3=R2_LUT4_I3_30_O O=L2_LUT4_I1_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I3_15_I1 I1=L2_LUT4_I1_4_I3_LUT4_O_I1 I2=L2_LUT4_I1_4_I3_LUT4_O_I2 I3=L2_LUT4_I1_4_I3_LUT4_O_I3 O=L2_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_1_I2_LUT4_O_I2 O=L2_LUT4_I1_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_2_O I1=L2_LUT4_I3_15_I0_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_35_O_LUT4_I2_O I3=L2_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2 O=L2_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_1_O I1=L2_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I2 I2=L2_LUT4_I3_20_I2_LUT4_O_I2_LUT4_I2_I1 I3=R2_LUT4_I3_34_O_LUT4_I2_O O=L2_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_15_I0_LUT4_O_I1 I3=L2_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I1_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I2 I1=R2_LUT4_I3_34_O_LUT4_I2_2_O I2=R2_LUT4_I3_35_O_LUT4_I2_O I3=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L2_LUT4_I1_I2_LUT4_O_I1 I2=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L2_LUT4_I1_I2_LUT4_O_I3 O=L2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L2_LUT4_I1_I2_LUT4_O_I1 I2=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_I2 I3=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_I2_LUT4_O_I1 I2=R2_LUT4_I3_10_O_LUT4_I2_2_O I3=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_1_O O=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I2=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_11_O_LUT4_I2_O O=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_22_I2_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_O O=L2_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_11_O_LUT4_I2_O O=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_1_O I1=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_2_O O=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_8_O I1=R2_LUT4_I3_9_O I2=R2_LUT4_I3_7_O I3=R2_LUT4_I3_6_O O=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_1_O I1=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_11_O_LUT4_I2_O O=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_9_O I1=R2_LUT4_I3_6_O I2=R2_LUT4_I3_7_O I3=R2_LUT4_I3_8_O O=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_8_O I1=R2_LUT4_I3_7_O I2=R2_LUT4_I3_6_O I3=R2_LUT4_I3_9_O O=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_10_O_LUT4_I2_2_O I3=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 O=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_7_O I1=R2_LUT4_I3_8_O I2=R2_LUT4_I3_9_O I3=R2_LUT4_I3_6_O O=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I1_I3_LUT4_O_I0 I1=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_O I2=L2_LUT4_I1_I3_LUT4_O_I2 I3=L2_LUT4_I1_I3_LUT4_O_I3 O=L2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0 I1=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I2=R2_LUT4_I3_11_O I3=R2_LUT4_I3_10_O O=L2_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R2_LUT4_I3_9_O I1=R2_LUT4_I3_7_O I2=R2_LUT4_I3_8_O I3=R2_LUT4_I3_6_O O=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_9_O I1=R2_LUT4_I3_8_O I2=R2_LUT4_I3_7_O I3=R2_LUT4_I3_6_O O=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L2_LUT4_I1_2_I3_LUT4_O_I2 I1=L2_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_18_I1_LUT4_O_I2 I3=L2_LUT4_I1_I2_LUT4_O_I3 O=L2_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_22_I2_LUT4_O_I2 I3=R2_LUT4_I3_11_O_LUT4_I2_O O=L2_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_O O=L2_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_1_O I1=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_10_O_LUT4_I2_2_O I3=L2_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O I1=L2_LUT4_I3_22_I1_LUT4_O_I1 I2=L2_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I1_2_I2_LUT4_O_I0 O=L2_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_2_O O=L2_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_9_O I1=R2_LUT4_I3_8_O I2=R2_LUT4_I3_7_O I3=R2_LUT4_I3_6_O O=L2_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2(14) I3=L2_LUT4_I2_I3 O=R3_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2(15) I3=L2_LUT4_I2_1_I3 O=R3_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L2_LUT4_I2_1_I3_LUT4_O_I0 I1=L2_LUT4_I2_1_I3_LUT4_O_I1 I2=L2_LUT4_I2_1_I3_LUT4_O_I2 I3=L2_LUT4_I2_1_I3_LUT4_O_I3 O=L2_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L2_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3 O=L2_LUT4_I2_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_16_O_LUT4_I2_O I3=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_17_O_LUT4_I2_O I1=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_5_I0_LUT4_O_I0 I1=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I2=L2_LUT4_I3_5_I0_LUT4_O_I3 I3=L2_LUT4_I3_5_I0_LUT4_O_I1 O=L2_LUT4_I2_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2 I3=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O O=L2_LUT4_I2_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2(32) I3=L2_LUT4_I2_2_I3 O=R3_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L2_LUT4_I2_2_I3_LUT4_O_I0 I1=L2_LUT4_I3_13_I1 I2=L2_LUT4_I2_2_I3_LUT4_O_I2 I3=L2_LUT4_I2_2_I3_LUT4_O_I3 O=L2_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1 I2=L2_LUT4_I3_2_I0_LUT4_O_I1 I3=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3 O=L2_LUT4_I2_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0 I1=R2_LUT4_I3_46_O_LUT4_I2_1_O I2=R2_LUT4_I3_46_O_LUT4_I2_2_O I3=L2_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I0 I2=R2_LUT4_I3_46_O_LUT4_I2_O I3=L2_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_46_O_LUT4_I2_O I3=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1 O=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_46_O_LUT4_I2_1_O O=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_46_O_LUT4_I2_2_O I3=L2_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I2_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_2_O I1=L2_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3 I2=L2_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_46_O_LUT4_I2_1_O O=L2_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_46_O_LUT4_I2_O I3=L2_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_45_O I1=R2_LUT4_I3_44_O I2=R2_LUT4_I3_43_O I3=R2_LUT4_I3_42_O O=L2_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I2_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I0 I3=R2_LUT4_I3_46_O_LUT4_I2_1_O O=L2_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_2_O I1=L2_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0 I2=L2_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I3=R2_LUT4_I3_46_O_LUT4_I2_O O=L2_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I2_I3_LUT4_O_I0 I1=L2_LUT4_I3_21_I1 I2=L2_LUT4_I2_I3_LUT4_O_I2 I3=L2_LUT4_I2_I3_LUT4_O_I3 O=L2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=L2_LUT4_I3_21_I1 I1=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1 I2=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L2_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_4_O_LUT4_I2_O O=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R2_LUT4_I3_4_O_LUT4_I2_1_O O=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_5_O_LUT4_I2_O I1=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 I3=R2_LUT4_I3_4_O_LUT4_I2_2_O O=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_2_O I1=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_4_O_LUT4_I2_1_O I3=L2_LUT4_I3_21_I2_LUT4_I2_I1_LUT4_O_I2 O=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_3_O I1=R2_LUT4_I3_2_O I2=R2_LUT4_I3_1_O I3=R2_LUT4_I3_O O=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_5_O_LUT4_I2_O O=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_2_O I1=R2_LUT4_I3_3_O I2=R2_LUT4_I3_1_O I3=R2_LUT4_I3_O O=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0 I1=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_11_I1_LUT4_O_I2 O=L2_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R2_LUT4_I3_5_O_LUT4_I2_O I3=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 O=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_4_O_LUT4_I2_1_O O=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_4_O_LUT4_I2_2_O I3=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_2_O I1=L2_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_4_O_LUT4_I2_1_O I3=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_5_O_LUT4_I2_O O=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_4_O_LUT4_I2_1_O I3=L2_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_5_O_LUT4_I2_O I1=L2_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_4_O_LUT4_I2_2_O I3=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 I1=R2_LUT4_I3_4_O_LUT4_I2_2_O I2=L2_LUT4_I3_8_I2_LUT4_O_I1 I3=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R2_LUT4_I3_3_O I1=R2_LUT4_I3_2_O I2=R2_LUT4_I3_1_O I3=R2_LUT4_I3_O O=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R2_LUT4_I3_4_O_LUT4_I2_1_O O=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_5_O_LUT4_I2_O O=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_O I1=R2_LUT4_I3_2_O I2=R2_LUT4_I3_1_O I3=R2_LUT4_I3_3_O O=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I3_I0 I1=L2_LUT4_I3_I1 I2=L2_LUT4_I3_I2 I3=L2(2) O=R3_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L2_LUT4_I3_1_I0 I1=L2_LUT4_I3_1_I1 I2=L2_LUT4_I3_1_I2 I3=L2(6) O=R3_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=L2_LUT4_I3_10_I0 I1=L2_LUT4_I3_10_I1 I2=L2_LUT4_I3_10_I2 I3=L2(5) O=R3_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L2_LUT4_I2_1_I3_LUT4_O_I0 I1=L2_LUT4_I1_3_I3_LUT4_O_I1 I2=L2_LUT4_I2_1_I3_LUT4_O_I1 I3=L2_LUT4_I3_10_I0_LUT4_O_I3 O=L2_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=L2_LUT4_I3_5_I0_LUT4_O_I3 I1=L2_LUT4_I3_5_I0_LUT4_O_I0 I2=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L2_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_10_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O O=L2_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L2_LUT4_I3_10_I1_LUT4_O_I0 I1=L2_LUT4_I3_5_I2_LUT4_O_I1 I2=L2_LUT4_I3_10_I1_LUT4_O_I2 I3=L2_LUT4_I3_10_I1_LUT4_O_I3 O=L2_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_10_I1_LUT4_O_I0_LUT4_O_I1 I2=L2_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 I3=R2_LUT4_I3_16_O_LUT4_I2_1_O O=L2_LUT4_I3_10_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_10_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_16_O_LUT4_I2_O O=L2_LUT4_I3_10_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_17_O_LUT4_I2_O I1=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I3_10_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_17_O_LUT4_I2_O I1=L2_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_16_O_LUT4_I2_2_O O=L2_LUT4_I3_10_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_14_O I1=R2_LUT4_I3_12_O I2=R2_LUT4_I3_13_O I3=R2_LUT4_I3_15_O O=L2_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_16_O_LUT4_I2_O I3=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_15_O I1=R2_LUT4_I3_13_O I2=R2_LUT4_I3_14_O I3=R2_LUT4_I3_12_O O=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_14_O I1=R2_LUT4_I3_13_O I2=R2_LUT4_I3_12_O I3=R2_LUT4_I3_15_O O=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_10_I2_LUT4_I3_I1 I2=L2_LUT4_I3_10_I1_LUT4_O_I0 I3=L2_LUT4_I3_10_I2 O=L2_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111100
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_10_I2_LUT4_O_I1 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I3_10_I2_LUT4_O_I3 O=L2_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_16_O_LUT4_I2_O O=L2_LUT4_I3_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3 I2=R2_LUT4_I3_17_O_LUT4_I2_O I3=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_10_I2_LUT4_O_I3 I2=R2_LUT4_I3_16_O_LUT4_I2_O I3=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3 O=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_15_O I1=R2_LUT4_I3_12_O I2=R2_LUT4_I3_13_O I3=R2_LUT4_I3_14_O O=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O I1=L2_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2 I3=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3 O=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R2_LUT4_I3_16_O_LUT4_I2_O I3=L2_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2 O=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_17_O_LUT4_I2_O I1=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_15_O I1=R2_LUT4_I3_14_O I2=R2_LUT4_I3_13_O I3=R2_LUT4_I3_12_O O=L2_LUT4_I3_10_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I3_8_I0 I1=L2_LUT4_I3_11_I1 I2=L2_LUT4_I3_11_I2 I3=L2(8) O=R3_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_11_I1_LUT4_O_I2 I3=L2_LUT4_I3_11_I1_LUT4_O_I3 O=L2_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_4_O_LUT4_I2_2_O O=L2_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_5_O_LUT4_I2_O I1=L2_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 I3=R2_LUT4_I3_4_O_LUT4_I2_1_O O=L2_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_2_O I1=R2_LUT4_I3_O I2=R2_LUT4_I3_1_O I3=R2_LUT4_I3_3_O O=L2_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2 O=L2_LUT4_I3_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 I2=R2_LUT4_I3_5_O_LUT4_I2_O I3=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_2_O I1=R2_LUT4_I3_1_O I2=R2_LUT4_I3_O I3=R2_LUT4_I3_3_O O=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_2_O I1=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R2_LUT4_I3_4_O_LUT4_I2_1_O I3=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_1_O I1=R2_LUT4_I3_O I2=R2_LUT4_I3_3_O I3=R2_LUT4_I3_2_O O=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_8_I2_LUT4_O_I1 I2=L2_LUT4_I3_21_I2 I3=L2_LUT4_I3_8_I2_LUT4_O_I2 O=L2_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L2_LUT4_I3_12_I0 I1=L2_LUT4_I3_12_I1 I2=L2_LUT4_I3_12_I2 I3=L2(9) O=R3_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_12_I0_LUT4_O_I1 I2=L2_LUT4_I3_19_I1_LUT4_O_I1 I3=L2_LUT4_I3_19_I1_LUT4_O_I2 O=L2_LUT4_I3_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_12_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R2_LUT4_I3_36_O_LUT4_I2_1_O I3=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I2 O=L2_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_2_O I1=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_37_O_LUT4_I2_O I3=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_I2_O I1=L2_LUT4_I3_3_I0_LUT4_O_I3 I2=L2_LUT4_I3_19_I0_LUT4_O_I2 I3=L2_LUT4_I3_19_I0_LUT4_O_I1 O=L2_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_19_I2_LUT4_O_I2 I3=L2_LUT4_I3_3_I1_LUT4_O_I3 O=L2_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L2_LUT4_I3_13_I0 I1=L2_LUT4_I3_13_I1 I2=L2_LUT4_I3_13_I2 I3=L2(12) O=R3_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L2_LUT4_I3_13_I0_LUT4_O_I0 I1=L2_LUT4_I3_4_I1_LUT4_O_I3 I2=L2_LUT4_I3_2_I2 I3=L2_LUT4_I3_13_I0_LUT4_O_I3 O=L2_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1 I1=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I3 I2=L2_LUT4_I3_2_I0_LUT4_O_I1 I3=L2_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 O=L2_LUT4_I3_13_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_2_I2_LUT4_O_I2 I2=L2_LUT4_I3_2_I0_LUT4_O_I2 I3=L2_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_46_O_LUT4_I2_2_O O=L2_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_O I1=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I2=L2_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I3=R2_LUT4_I3_46_O_LUT4_I2_1_O O=L2_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_13_I1_LUT4_O_I2 I3=L2_LUT4_I3_2_I1_LUT4_O_I2 O=L2_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1 I2=R2_LUT4_I3_46_O_LUT4_I2_O I3=L2_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_13_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_45_O I1=R2_LUT4_I3_44_O I2=R2_LUT4_I3_43_O I3=R2_LUT4_I3_42_O O=L2_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_2_I1_LUT4_O_I0 I2=L2_LUT4_I3_13_I2 I3=L2_LUT4_I3_2_I1_LUT4_O_I2 O=L2_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_13_I2_LUT4_O_I1 I2=L2_LUT4_I3_13_I2_LUT4_O_I2 I3=L2_LUT4_I2_2_I3_LUT4_O_I3 O=L2_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_46_O_LUT4_I2_O I3=L2_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_44_O I1=R2_LUT4_I3_45_O I2=R2_LUT4_I3_43_O I3=R2_LUT4_I3_42_O O=L2_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_45_O I1=R2_LUT4_I3_43_O I2=R2_LUT4_I3_44_O I3=R2_LUT4_I3_42_O O=L2_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_2_O I1=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I2=L2_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_46_O_LUT4_I2_1_O O=L2_LUT4_I3_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_14_I0 I1=L2_LUT4_I3_14_I1 I2=L2_LUT4_I3_14_I2 I3=L2(13) O=R3_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=L2_LUT4_I3_I0_LUT4_O_I2 I1=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O I2=L2_LUT4_I3_I0_LUT4_O_I1 I3=L2_LUT4_I3_14_I0_LUT4_O_I3 O=L2_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_I1_LUT4_O_I1 I2=L2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L2_LUT4_I3_14_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L2_LUT4_I3_14_I2_LUT4_O_I3 I1=R2_LUT4_I3_22_O_LUT4_I2_2_O I2=L2_LUT4_I3_I2_LUT4_O_I2 I3=L2_LUT4_I3_14_I1_LUT4_O_I3 O=L2_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I3=R2_LUT4_I3_22_O_LUT4_I2_1_O O=L2_LUT4_I3_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 O=L2_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_21_O I1=R2_LUT4_I3_18_O I2=R2_LUT4_I3_19_O I3=R2_LUT4_I3_20_O O=L2_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_14_I2_LUT4_O_I1 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_14_I2_LUT4_O_I3 O=L2_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_22_O_LUT4_I2_1_O O=L2_LUT4_I3_14_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1 I2=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=R2_LUT4_I3_22_O_LUT4_I2_2_O O=L2_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_21_O I1=R2_LUT4_I3_20_O I2=R2_LUT4_I3_19_O I3=R2_LUT4_I3_18_O O=L2_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_21_O I1=R2_LUT4_I3_20_O I2=R2_LUT4_I3_19_O I3=R2_LUT4_I3_18_O O=L2_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I3_15_I0 I1=L2_LUT4_I3_15_I1 I2=L2_LUT4_I3_15_I2 I3=L2(16) O=R3_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_15_I0_LUT4_O_I1 I2=L2_LUT4_I3_1_I1_LUT4_O_I1 I3=L2_LUT4_I3_1_I1_LUT4_O_I3 O=L2_LUT4_I3_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_1_O I1=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I2 I2=R2_LUT4_I3_34_O_LUT4_I2_O I3=L2_LUT4_I3_15_I0_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_15_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_30_O I1=R2_LUT4_I3_32_O I2=R2_LUT4_I3_31_O I3=R2_LUT4_I3_33_O O=L2_LUT4_I3_15_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_15_I1_LUT4_O_I2 I3=L2_LUT4_I3_1_I0_LUT4_O_I2 O=L2_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_15_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_1_O I1=L2_LUT4_I3_15_I0_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_34_O_LUT4_I2_O I3=L2_LUT4_I1_4_I2_LUT4_O_I2 O=L2_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_2_O I1=L2_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_35_O_LUT4_I2_O I3=L2_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_O I1=R2_LUT4_I3_34_O_LUT4_I2_1_O I2=L2_LUT4_I3_15_I2_LUT4_O_I2 I3=L2_LUT4_I3_15_I2_LUT4_O_I3 O=L2_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R2_LUT4_I3_35_O_LUT4_I2_O I1=L2_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_34_O_LUT4_I2_1_O I3=L2_LUT4_I3_15_I2_LUT4_O_I2 O=L2_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_33_O I1=R2_LUT4_I3_32_O I2=R2_LUT4_I3_31_O I3=R2_LUT4_I3_30_O O=L2_LUT4_I3_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_1_O I1=L2_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_34_O_LUT4_I2_O I3=L2_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_15_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_31_O I1=R2_LUT4_I3_30_O I2=R2_LUT4_I3_33_O I3=R2_LUT4_I3_32_O O=L2_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_33_O I1=R2_LUT4_I3_32_O I2=R2_LUT4_I3_30_O I3=R2_LUT4_I3_31_O O=L2_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L2_LUT4_I3_16_I0 I1=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O I2=L2_LUT4_I3_16_I2 I3=L2(18) O=R3_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_16_I0_LUT4_O_I1 I2=L2_LUT4_I3_14_I1 I3=L2_LUT4_I3_7_I0_LUT4_O_I3 O=L2_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_16_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_1_O I1=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_22_O_LUT4_I2_2_O I3=L2_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 O=L2_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I2=L2_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_23_O_LUT4_I2_O O=L2_LUT4_I3_16_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_16_I2_LUT4_I3_I1 I2=L2_LUT4_I3_16_I2_LUT4_I3_I2 I3=L2_LUT4_I3_16_I2 O=L2_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3 O=L2_LUT4_I3_16_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_21_O I1=R2_LUT4_I3_20_O I2=R2_LUT4_I3_18_O I3=R2_LUT4_I3_19_O O=L2_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_1_O I1=L2_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1 I2=L2_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 I3=R2_LUT4_I3_22_O_LUT4_I2_2_O O=L2_LUT4_I3_16_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_20_O I1=R2_LUT4_I3_18_O I2=R2_LUT4_I3_19_O I3=R2_LUT4_I3_21_O O=L2_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_16_I2_LUT4_O_I1 I2=L2_LUT4_I3_16_I2_LUT4_O_I2 I3=L2_LUT4_I3_I1_LUT4_O_I1 O=L2_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_1_O I1=L2_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_22_O_LUT4_I2_2_O I3=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I3_16_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_20_O I1=R2_LUT4_I3_19_O I2=R2_LUT4_I3_21_O I3=R2_LUT4_I3_18_O O=L2_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_19_O I1=R2_LUT4_I3_18_O I2=R2_LUT4_I3_21_O I3=R2_LUT4_I3_20_O O=L2_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_20_O I1=R2_LUT4_I3_21_O I2=R2_LUT4_I3_19_O I3=R2_LUT4_I3_18_O O=L2_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I3_9_I0 I1=L2_LUT4_I3_17_I1 I2=L2_LUT4_I3_17_I2 I3=L2(19) O=R3_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_17_I1_LUT4_O_I1 I2=L2_LUT4_I3_17_I1_LUT4_O_I2 I3=L2_LUT4_I3_9_I0_LUT4_O_I3 O=L2_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I1_1_I2_LUT4_O_I0 I3=R2_LUT4_I3_28_O_LUT4_I2_O O=L2_LUT4_I3_17_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_28_O_LUT4_I2_1_O O=L2_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_2_O I1=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_17_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_1_O I1=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_28_O_LUT4_I2_2_O I3=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_17_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_9_I2_LUT4_O_I1 I2=L2_LUT4_I3_23_I1_LUT4_O_I2 I3=L2_LUT4_I3_17_I2_LUT4_O_I3 O=L2_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_17_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_1_O I1=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_28_O_LUT4_I2_2_O O=L2_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_18_I0 I1=L2_LUT4_I3_18_I1 I2=L2_LUT4_I3_18_I2 I3=L2(20) O=R3_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_O O=L2_LUT4_I3_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_18_I1_LUT4_O_I2 I3=L2_LUT4_I1_2_I3_LUT4_O_I2 O=L2_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_18_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_10_O_LUT4_I2_2_O I3=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I1 I1=R2_LUT4_I3_10_O_LUT4_I2_1_O I2=R2_LUT4_I3_11_O_LUT4_I2_O I3=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I3=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I3 O=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0 I3=R2_LUT4_I3_10_O_LUT4_I2_2_O O=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_8_O I1=R2_LUT4_I3_7_O I2=R2_LUT4_I3_9_O I3=R2_LUT4_I3_6_O O=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_1_O I1=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I2=R2_LUT4_I3_11_O_LUT4_I2_O I3=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_2_I2_LUT4_O_I1 I2=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O I3=L2_LUT4_I3_22_I2 O=L2_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L2_LUT4_I3_19_I0 I1=L2_LUT4_I3_19_I1 I2=L2_LUT4_I3_19_I2 I3=L2(23) O=R3_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_19_I0_LUT4_O_I1 I2=L2_LUT4_I3_19_I0_LUT4_O_I2 I3=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_I2_O O=L2_LUT4_I3_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_1_O I1=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_37_O_LUT4_I2_O O=L2_LUT4_I3_19_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_39_O I1=R2_LUT4_I3_38_O I2=R2_LUT4_I3_41_O I3=R2_LUT4_I3_40_O O=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_38_O I1=R2_LUT4_I3_40_O I2=R2_LUT4_I3_39_O I3=R2_LUT4_I3_41_O O=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_36_O_LUT4_I2_2_O O=L2_LUT4_I3_19_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_40_O I1=R2_LUT4_I3_39_O I2=R2_LUT4_I3_38_O I3=R2_LUT4_I3_41_O O=L2_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_39_O I1=R2_LUT4_I3_40_O I2=R2_LUT4_I3_41_O I3=R2_LUT4_I3_38_O O=L2_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I3_6_I1 I1=L2_LUT4_I3_19_I1_LUT4_O_I1 I2=L2_LUT4_I3_19_I1_LUT4_O_I2 I3=L2_LUT4_I3_19_I1_LUT4_O_I3 O=L2_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_19_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I2=L2_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I0 I3=R2_LUT4_I3_36_O_LUT4_I2_2_O O=L2_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_1_O I1=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_37_O_LUT4_I2_O I3=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_36_O_LUT4_I2_1_O I3=L2_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_19_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_36_O_LUT4_I2_O O=L2_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L2_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I1=R2_LUT4_I3_37_O_LUT4_I2_O I2=R2_LUT4_I3_36_O_LUT4_I2_2_O I3=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_41_O I1=R2_LUT4_I3_40_O I2=R2_LUT4_I3_39_O I3=R2_LUT4_I3_38_O O=L2_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_19_I2_LUT4_O_I2 I3=L2_LUT4_I3_3_I1_LUT4_O_I2 O=L2_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_1_O I1=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_37_O_LUT4_I2_O I3=L2_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_36_O_LUT4_I2_2_O O=L2_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_1_I0_LUT4_O_I0 I1=L2_LUT4_I1_4_I2 I2=L2_LUT4_I3_1_I0_LUT4_O_I2 I3=L2_LUT4_I3_1_I0_LUT4_O_I3 O=L2_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L2_LUT4_I1_4_I2_LUT4_O_I2 I1=R2_LUT4_I3_35_O_LUT4_I2_O I2=L2_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I2 I3=L2_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I3 O=L2_LUT4_I3_1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L2_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3 I1=L2_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_34_O_LUT4_I2_1_O I3=L2_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_34_O_LUT4_I2_2_O O=L2_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_35_O_LUT4_I2_O I1=R2_LUT4_I3_34_O_LUT4_I2_2_O I2=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I2 I1=R2_LUT4_I3_35_O_LUT4_I2_O I2=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_34_O_LUT4_I2_O O=L2_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_33_O I1=R2_LUT4_I3_32_O I2=R2_LUT4_I3_31_O I3=R2_LUT4_I3_30_O O=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_2_O I1=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_35_O_LUT4_I2_O I3=L2_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_33_O I1=R2_LUT4_I3_32_O I2=R2_LUT4_I3_31_O I3=R2_LUT4_I3_30_O O=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_35_O_LUT4_I2_O I1=R2_LUT4_I3_34_O_LUT4_I2_2_O I2=L2_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_2_O I1=L2_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 I2=R2_LUT4_I3_34_O_LUT4_I2_1_O I3=L2_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I2 O=L2_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=R2_LUT4_I3_32_O I1=R2_LUT4_I3_30_O I2=R2_LUT4_I3_31_O I3=R2_LUT4_I3_33_O O=L2_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_1_O I1=L2_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 I2=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_34_O_LUT4_I2_O O=L2_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_1_I1_LUT4_O_I1 I2=L2_LUT4_I3_1_I1_LUT4_O_I2 I3=L2_LUT4_I3_1_I1_LUT4_O_I3 O=L2_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I0 I1=R2_LUT4_I3_34_O_LUT4_I2_O I2=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R2_LUT4_I3_33_O I1=R2_LUT4_I3_31_O I2=R2_LUT4_I3_30_O I3=R2_LUT4_I3_32_O O=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_32_O I1=R2_LUT4_I3_31_O I2=R2_LUT4_I3_33_O I3=R2_LUT4_I3_30_O O=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_35_O_LUT4_I2_O I1=L2_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 I2=L2_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_34_O_LUT4_I2_1_O O=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_35_O_LUT4_I2_O I1=R2_LUT4_I3_34_O_LUT4_I2_2_O I2=L2_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R2_LUT4_I3_33_O I1=R2_LUT4_I3_32_O I2=R2_LUT4_I3_31_O I3=R2_LUT4_I3_30_O O=L2_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_2_O I1=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I0 I2=R2_LUT4_I3_35_O_LUT4_I2_O I3=L2_LUT4_I3_20_I2_LUT4_O_I2_LUT4_I2_I1 O=L2_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_1_I2_LUT4_O_I3 I2=L2_LUT4_I3_20_I1_LUT4_O_I2 I3=L2_LUT4_I1_4_I3_LUT4_O_I2 O=L2_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I1_4_I3_LUT4_O_I3 I2=L2_LUT4_I3_1_I2_LUT4_O_I2 I3=L2_LUT4_I3_1_I2_LUT4_O_I3 O=L2_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_35_O_LUT4_I2_O I1=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I2 I2=R2_LUT4_I3_34_O_LUT4_I2_1_O I3=L2_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_2_O I1=L2_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_34_O_LUT4_I2_O I3=L2_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I1_4_I2_LUT4_O_I2 I3=R2_LUT4_I3_34_O_LUT4_I2_1_O O=L2_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_20_I2_LUT4_O_I2_LUT4_I2_O I2=L2_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_34_O_LUT4_I2_O O=L2_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L2_LUT4_I3_2_I0 I1=L2_LUT4_I3_2_I1 I2=L2_LUT4_I3_2_I2 I3=L2(7) O=R3_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L2_LUT4_I3_20_I0 I1=L2_LUT4_I3_20_I1 I2=L2_LUT4_I3_20_I2 I3=L2(24) O=R3_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_15_I1_LUT4_O_I2 I2=L2_LUT4_I3_20_I0_LUT4_O_I2 I3=L2_LUT4_I3_1_I0_LUT4_O_I3 O=L2_LUT4_I3_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I3 I2=R2_LUT4_I3_34_O_LUT4_I2_1_O I3=L2_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_20_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_33_O I1=R2_LUT4_I3_32_O I2=R2_LUT4_I3_31_O I3=R2_LUT4_I3_30_O O=L2_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I1_4_I3_LUT4_O_I2 I1=L2_LUT4_I1_4_I2 I2=L2_LUT4_I3_20_I1_LUT4_O_I2 I3=L2_LUT4_I3_15_I2 O=L2_LUT4_I3_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_20_I1_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_34_O_LUT4_I2_O I3=L2_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_20_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_1_I1_LUT4_O_I2 I3=L2_LUT4_I3_20_I2 O=L2_LUT4_I1_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_35_O_LUT4_I2_O I1=R2_LUT4_I3_34_O_LUT4_I2_2_O I2=L2_LUT4_I3_20_I2_LUT4_O_I2 I3=L2_LUT4_I3_20_I2_LUT4_O_I3 O=L2_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_2_O I1=L2_LUT4_I3_20_I2_LUT4_O_I2_LUT4_I2_I1 I2=L2_LUT4_I3_20_I2_LUT4_O_I2 I3=R2_LUT4_I3_35_O_LUT4_I2_O O=L2_LUT4_I3_20_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_20_I2_LUT4_O_I2_LUT4_I2_1_I1 I2=L2_LUT4_I3_20_I2_LUT4_O_I2 I3=R2_LUT4_I3_34_O_LUT4_I2_2_O O=L2_LUT4_I3_20_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_35_O_LUT4_I2_O I1=L2_LUT4_I3_15_I0_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_34_O_LUT4_I2_1_O I3=L2_LUT4_I3_20_I2_LUT4_O_I2_LUT4_I2_I1 O=L2_LUT4_I3_20_I2_LUT4_O_I2_LUT4_I2_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_33_O I1=R2_LUT4_I3_30_O I2=R2_LUT4_I3_31_O I3=R2_LUT4_I3_32_O O=L2_LUT4_I3_20_I2_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_33_O I1=R2_LUT4_I3_31_O I2=R2_LUT4_I3_32_O I3=R2_LUT4_I3_30_O O=L2_LUT4_I3_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_34_O_LUT4_I2_2_O I1=L2_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I0 I3=R2_LUT4_I3_35_O_LUT4_I2_O O=L2_LUT4_I3_20_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_31_O I1=R2_LUT4_I3_32_O I2=R2_LUT4_I3_33_O I3=R2_LUT4_I3_30_O O=L2_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I3_21_I0 I1=L2_LUT4_I3_21_I1 I2=L2_LUT4_I3_21_I2 I3=L2(25) O=R3_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L2_LUT4_I3_8_I1_LUT4_O_I3 I1=L2_LUT4_I3_21_I0_LUT4_O_I1 I2=L2_LUT4_I2_I3_LUT4_O_I0 I3=L2_LUT4_I3_8_I0_LUT4_O_I2 O=L2_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_11_I1_LUT4_O_I3 I3=L2_LUT4_I3_8_I1_LUT4_O_I2 O=L2_LUT4_I3_21_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_21_I1_LUT4_O_I1 I2=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 I3=R2_LUT4_I3_4_O_LUT4_I2_O O=L2_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_5_O_LUT4_I2_O O=L2_LUT4_I3_21_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_2_O I1=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_4_O_LUT4_I2_1_O I3=L2_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L2_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_21_I2_LUT4_I2_I1 I2=L2_LUT4_I3_21_I2 I3=L2_LUT4_I3_8_I2_LUT4_O_I2 O=L2_LUT4_I3_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L2_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 I1=R2_LUT4_I3_4_O_LUT4_I2_2_O I2=L2_LUT4_I3_21_I2_LUT4_I2_I1_LUT4_O_I2 I3=L2_LUT4_I3_21_I2_LUT4_I2_I1_LUT4_O_I3 O=L2_LUT4_I3_21_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R2_LUT4_I3_3_O I1=R2_LUT4_I3_1_O I2=R2_LUT4_I3_2_O I3=R2_LUT4_I3_O O=L2_LUT4_I3_21_I2_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_5_O_LUT4_I2_O I3=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I3_21_I2_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_21_I2_LUT4_O_I2 I3=L2_LUT4_I3_21_I2_LUT4_O_I3 O=L2_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_2_O I1=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_4_O_LUT4_I2_1_O I3=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_1_O I1=R2_LUT4_I3_2_O I2=R2_LUT4_I3_3_O I3=R2_LUT4_I3_O O=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_3_O I1=R2_LUT4_I3_O I2=R2_LUT4_I3_1_O I3=R2_LUT4_I3_2_O O=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_5_O_LUT4_I2_O I3=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_21_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_3_O I1=R2_LUT4_I3_2_O I2=R2_LUT4_I3_1_O I3=R2_LUT4_I3_O O=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_3_O I1=R2_LUT4_I3_2_O I2=R2_LUT4_I3_O I3=R2_LUT4_I3_1_O O=L2_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L2_LUT4_I3_22_I0 I1=L2_LUT4_I3_22_I1 I2=L2_LUT4_I3_22_I2 I3=L2(26) O=R3_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_I1_O I1=L2_LUT4_I1_I3_LUT4_O_I2 I2=L2_LUT4_I3_22_I0_LUT4_O_I2 I3=L2_LUT4_I3_18_I1 O=L2_LUT4_I3_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L2_LUT4_I3_22_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_22_I1_LUT4_O_I1 I2=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O I3=L2_LUT4_I3_22_I1_LUT4_O_I3 O=L2_LUT4_I3_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_22_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0 I2=L2_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_10_O_LUT4_I2_2_O O=L2_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_1_O I1=L2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R2_LUT4_I3_11_O_LUT4_I2_O I3=L2_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 O=L2_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0 I1=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_11_O_LUT4_I2_O I3=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_22_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_1_O I1=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0 I2=R2_LUT4_I3_10_O_LUT4_I2_2_O I3=L2_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_6_O I1=R2_LUT4_I3_8_O I2=R2_LUT4_I3_7_O I3=R2_LUT4_I3_9_O O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_9_O I1=R2_LUT4_I3_8_O I2=R2_LUT4_I3_7_O I3=R2_LUT4_I3_6_O O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_1_O O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_2_O I1=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R2_LUT4_I3_11_O_LUT4_I2_O I3=L2_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0 O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=L2_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_10_O_LUT4_I2_1_O O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O I2=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_10_O_LUT4_I2_O O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_O I1=L2_LUT4_I1_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R2_LUT4_I3_11_O_LUT4_I2_O O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_9_O I1=R2_LUT4_I3_8_O I2=R2_LUT4_I3_7_O I3=R2_LUT4_I3_6_O O=L2_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_22_I2_LUT4_O_I1 I2=L2_LUT4_I3_22_I2_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_2_O O=L2_LUT4_I3_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_10_O_LUT4_I2_O O=L2_LUT4_I3_22_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_10_O_LUT4_I2_1_O I1=L2_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_11_O_LUT4_I2_O I3=L2_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_9_O I1=R2_LUT4_I3_7_O I2=R2_LUT4_I3_6_O I3=R2_LUT4_I3_8_O O=L2_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_9_O I1=R2_LUT4_I3_8_O I2=R2_LUT4_I3_7_O I3=R2_LUT4_I3_6_O O=L2_LUT4_I3_22_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I3_9_I0 I1=L2_LUT4_I3_23_I1 I2=L2_LUT4_I3_23_I2 I3=L2(29) O=R3_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_23_I1_LUT4_O_I2 I3=L2_LUT4_I1_1_I3_LUT4_O_I2 O=L2_LUT4_I3_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 I3=R2_LUT4_I3_29_O_LUT4_I2_O O=L2_LUT4_I3_23_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_29_O I3=R2_LUT4_I3_28_O O=L2_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I1_1_I2_LUT4_O_I2 I3=L2_LUT4_I3_17_I1_LUT4_O_I1 O=L2_LUT4_I3_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L2_LUT4_I3_2_I0_LUT4_O_I0 I1=L2_LUT4_I3_2_I0_LUT4_O_I1 I2=L2_LUT4_I3_2_I0_LUT4_O_I2 I3=L2_LUT4_I3_2_I0_LUT4_O_I3 O=L2_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I0 I1=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1 I2=R2_LUT4_I3_47_O I3=R2_LUT4_I3_46_O O=L2_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=R2_LUT4_I3_43_O I1=R2_LUT4_I3_44_O I2=R2_LUT4_I3_45_O I3=R2_LUT4_I3_42_O O=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_42_O I1=R2_LUT4_I3_44_O I2=R2_LUT4_I3_43_O I3=R2_LUT4_I3_45_O O=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0 I2=R2_LUT4_I3_46_O_LUT4_I2_2_O I3=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1 O=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_O I1=L2_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I2 I2=R2_LUT4_I3_46_O_LUT4_I2_1_O I3=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_45_O I1=R2_LUT4_I3_43_O I2=R2_LUT4_I3_42_O I3=R2_LUT4_I3_44_O O=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=L2_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_46_O_LUT4_I2_2_O I3=R2_LUT4_I3_46_O_LUT4_I2_1_O O=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_2_O I1=L2_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 I2=L2_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_46_O_LUT4_I2_1_O O=L2_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 I2=L2_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_46_O_LUT4_I2_O O=L2_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_46_O_LUT4_I2_O I3=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0 O=L2_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_45_O I1=R2_LUT4_I3_42_O I2=R2_LUT4_I3_43_O I3=R2_LUT4_I3_44_O O=L2_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L2_LUT4_I3_2_I1_LUT4_O_I0 I1=L2_LUT4_I3_13_I2 I2=L2_LUT4_I3_2_I1_LUT4_O_I2 I3=L2_LUT4_I3_2_I1_LUT4_O_I3 O=L2_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_2_I1_LUT4_O_I3 I3=L2_LUT4_I2_2_I3_LUT4_O_I2 O=L2_LUT4_I3_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_2_O I1=L2_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R2_LUT4_I3_44_O I1=R2_LUT4_I3_43_O I2=R2_LUT4_I3_45_O I3=R2_LUT4_I3_42_O O=L2_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0 I2=L2_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I0 I3=R2_LUT4_I3_46_O_LUT4_I2_O O=L2_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_2_O I1=L2_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 I2=L2_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 I3=R2_LUT4_I3_46_O_LUT4_I2_O O=L2_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_47_O_LUT4_I2_O I1=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_46_O_LUT4_I2_1_O I3=L2_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_2_I2_LUT4_O_I1 I2=L2_LUT4_I3_2_I2_LUT4_O_I2 I3=R2_LUT4_I3_46_O_LUT4_I2_2_O O=L2_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_47_O_LUT4_I2_O O=L2_LUT4_I3_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_O I1=L2_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_46_O_LUT4_I2_1_O I3=L2_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0 O=L2_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_45_O I1=R2_LUT4_I3_44_O I2=R2_LUT4_I3_43_O I3=R2_LUT4_I3_42_O O=L2_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R2_LUT4_I3_45_O I1=R2_LUT4_I3_44_O I2=R2_LUT4_I3_43_O I3=R2_LUT4_I3_42_O O=L2_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I3_3_I0 I1=L2_LUT4_I3_3_I1 I2=L2_LUT4_I3_3_I2 I3=L2(17) O=R3_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_I2_O I1=L2_LUT4_I3_3_I0_LUT4_O_I1 I2=L2_LUT4_I3_3_I0_LUT4_O_I2 I3=L2_LUT4_I3_3_I0_LUT4_O_I3 O=L2_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L2_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I0 I1=L2_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_37_O I3=R2_LUT4_I3_36_O O=L2_LUT4_I3_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R2_LUT4_I3_41_O I1=R2_LUT4_I3_39_O I2=R2_LUT4_I3_40_O I3=R2_LUT4_I3_38_O O=L2_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_37_O_LUT4_I2_O I3=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_36_O_LUT4_I2_1_O I3=L2_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_2_O I1=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_37_O_LUT4_I2_O O=L2_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_3_I1_LUT4_O_I2 I3=L2_LUT4_I3_3_I1_LUT4_O_I3 O=L2_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L2_LUT4_I3_3_I1_LUT4_O_I3 I1=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_I2_I1 I2=L2_LUT4_I3_3_I1_LUT4_O_I2 I3=L2_LUT4_I3_19_I2_LUT4_O_I2 O=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=R2_LUT4_I3_36_O_LUT4_I2_2_O I3=L2_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_1_O I1=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 I2=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I3=R2_LUT4_I3_37_O_LUT4_I2_O O=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_36_O_LUT4_I2_2_O I3=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_41_O I1=R2_LUT4_I3_38_O I2=R2_LUT4_I3_39_O I3=R2_LUT4_I3_40_O O=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 I3=R2_LUT4_I3_36_O_LUT4_I2_O O=L2_LUT4_I3_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_36_O_LUT4_I2_1_O I3=L2_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 I1=R2_LUT4_I3_36_O_LUT4_I2_2_O I2=R2_LUT4_I3_37_O_LUT4_I2_O I3=L2_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I0 O=L2_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_3_I2_LUT4_O_I2 I3=L2_LUT4_I3_6_I1_LUT4_O_I3 O=L2_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_37_O_LUT4_I2_O I1=L2_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_12_I0_LUT4_O_I1 O=L2_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_36_O_LUT4_I2_1_O O=L2_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L2_LUT4_I3_4_I0 I1=L2_LUT4_I3_4_I1 I2=L2_LUT4_I3_4_I2 I3=L2(22) O=R3_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_4_I0_LUT4_O_I1 I2=L2_LUT4_I3_4_I0_LUT4_O_I2 I3=L2_LUT4_I3_4_I0_LUT4_O_I3 O=L2_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_46_O_LUT4_I2_2_O I1=L2_LUT4_I3_2_I2_LUT4_O_I1_LUT4_O_I2 I2=R2_LUT4_I3_46_O_LUT4_I2_1_O I3=L2_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_44_O I1=R2_LUT4_I3_42_O I2=R2_LUT4_I3_43_O I3=R2_LUT4_I3_45_O O=L2_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1 O=L2_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L2_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0 I1=L2_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_47_O I3=R2_LUT4_I3_46_O O=L2_LUT4_I3_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R2_LUT4_I3_45_O I1=R2_LUT4_I3_44_O I2=R2_LUT4_I3_42_O I3=R2_LUT4_I3_43_O O=L2_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_44_O I1=R2_LUT4_I3_43_O I2=R2_LUT4_I3_42_O I3=R2_LUT4_I3_45_O O=L2_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_2_I2 I3=L2_LUT4_I3_4_I1_LUT4_O_I3 O=L2_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_4_I2_LUT4_O_I2 I3=L2_LUT4_I2_2_I3_LUT4_O_I3 O=L2_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_4_I2_LUT4_O_I2 I2=L2_LUT4_I3_2_I2_LUT4_O_I2 I3=R2_LUT4_I3_46_O_LUT4_I2_1_O O=L2_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0 I1=R2_LUT4_I3_46_O_LUT4_I2_2_O I2=R2_LUT4_I3_46_O_LUT4_I2_1_O I3=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_43_O I1=R2_LUT4_I3_42_O I2=R2_LUT4_I3_45_O I3=R2_LUT4_I3_44_O O=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_45_O I1=R2_LUT4_I3_44_O I2=R2_LUT4_I3_43_O I3=R2_LUT4_I3_42_O O=L2_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L2_LUT4_I3_5_I0 I1=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I2=L2_LUT4_I3_5_I2 I3=L2(27) O=R3_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=L2_LUT4_I3_5_I0_LUT4_O_I0 I1=L2_LUT4_I3_5_I0_LUT4_O_I1 I2=L2_LUT4_I1_3_I3_LUT4_O_I1 I3=L2_LUT4_I3_5_I0_LUT4_O_I3 O=L2_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2 I3=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3 O=L2_LUT4_I3_5_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0 I2=R2_LUT4_I3_16_O_LUT4_I2_O I3=L2_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 O=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_17_O_LUT4_I2_O I1=L2_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R2_LUT4_I3_16_O_LUT4_I2_O O=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_17_O_LUT4_I2_O I1=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0 O=L2_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0 I1=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_16_O_LUT4_I2_O I3=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_5_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R2_LUT4_I3_12_O I1=R2_LUT4_I3_14_O I2=R2_LUT4_I3_13_O I3=R2_LUT4_I3_15_O O=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_14_O I1=R2_LUT4_I3_13_O I2=R2_LUT4_I3_15_O I3=R2_LUT4_I3_12_O O=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1 I1=R2_LUT4_I3_16_O_LUT4_I2_2_O I2=R2_LUT4_I3_17_O_LUT4_I2_O I3=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_5_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_O I1=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_13_O I1=R2_LUT4_I3_14_O I2=R2_LUT4_I3_15_O I3=R2_LUT4_I3_12_O O=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_17_O_LUT4_I2_O I3=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_14_O I1=R2_LUT4_I3_15_O I2=R2_LUT4_I3_13_O I3=R2_LUT4_I3_12_O O=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_13_O I1=R2_LUT4_I3_12_O I2=R2_LUT4_I3_15_O I3=R2_LUT4_I3_14_O O=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L2_LUT4_I3_5_I2_LUT4_O_I0 I1=L2_LUT4_I3_5_I2_LUT4_O_I1 I2=L2_LUT4_I3_5_I2_LUT4_O_I2 I3=L2_LUT4_I3_5_I2_LUT4_O_I3 O=L2_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I3_10_I2_LUT4_O_I3 I1=R2_LUT4_I3_16_O_LUT4_I2_O I2=L2_LUT4_I3_10_I1_LUT4_O_I0 I3=L2_LUT4_I3_5_I2_LUT4_O_I0_LUT4_O_I3 O=L2_LUT4_I3_5_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_16_O_LUT4_I2_2_O O=L2_LUT4_I3_5_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_17_O_LUT4_I2_O I3=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3 O=L2_LUT4_I3_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I2=R2_LUT4_I3_16_O_LUT4_I2_2_O I3=L2_LUT4_I3_10_I2_LUT4_O_I3_LUT4_I1_I3 O=L2_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_O I1=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_17_O_LUT4_I2_O I3=L2_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_5_I2_LUT4_O_I2 I1=L2_LUT4_I3_5_I2_LUT4_O_I3 I2=L2_LUT4_I1_3_I2_LUT4_O_I2 I3=L2_LUT4_I1_3_I2_LUT4_O_I1 O=L2_LUT4_I3_10_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_O I1=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_16_O_LUT4_I2_2_O O=L2_LUT4_I3_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_15_O I1=R2_LUT4_I3_14_O I2=R2_LUT4_I3_13_O I3=R2_LUT4_I3_12_O O=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_15_O I1=R2_LUT4_I3_14_O I2=R2_LUT4_I3_12_O I3=R2_LUT4_I3_13_O O=L2_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_16_O_LUT4_I2_1_O I1=L2_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_17_O_LUT4_I2_O I3=L2_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_15_O I1=R2_LUT4_I3_13_O I2=R2_LUT4_I3_12_O I3=R2_LUT4_I3_14_O O=L2_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_15_O I1=R2_LUT4_I3_14_O I2=R2_LUT4_I3_13_O I3=R2_LUT4_I3_12_O O=L2_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I3_6_I0 I1=L2_LUT4_I3_6_I1 I2=L2_LUT4_I3_6_I2 I3=L2(31) O=R3_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L2_LUT4_I3_3_I1_LUT4_O_I2_LUT4_I2_O I1=L2_LUT4_I3_6_I0_LUT4_O_I1 I2=L2_LUT4_I3_6_I0_LUT4_O_I2 I3=L2_LUT4_I3_3_I1_LUT4_O_I3 O=L2_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L2_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 I1=L2_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_37_O I3=R2_LUT4_I3_36_O O=L2_LUT4_I3_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R2_LUT4_I3_41_O I1=R2_LUT4_I3_40_O I2=R2_LUT4_I3_39_O I3=R2_LUT4_I3_38_O O=L2_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_37_O_LUT4_I2_O I3=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_40_O I1=R2_LUT4_I3_41_O I2=R2_LUT4_I3_39_O I3=R2_LUT4_I3_38_O O=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_41_O I1=R2_LUT4_I3_39_O I2=R2_LUT4_I3_38_O I3=R2_LUT4_I3_40_O O=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_6_I1_LUT4_O_I1 I2=L2_LUT4_I3_6_I1_LUT4_O_I2 I3=L2_LUT4_I3_6_I1_LUT4_O_I3 O=L2_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_2_O I1=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_37_O_LUT4_I2_O I3=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_40_O I1=R2_LUT4_I3_38_O I2=R2_LUT4_I3_39_O I3=R2_LUT4_I3_41_O O=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_40_O I1=R2_LUT4_I3_39_O I2=R2_LUT4_I3_41_O I3=R2_LUT4_I3_38_O O=L2_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_36_O_LUT4_I2_1_O O=L2_LUT4_I3_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I0 I2=R2_LUT4_I3_36_O_LUT4_I2_2_O I3=L2_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_41_O I1=R2_LUT4_I3_40_O I2=R2_LUT4_I3_38_O I3=R2_LUT4_I3_39_O O=L2_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_1_O I1=L2_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_19_I1_LUT4_O_I1 I3=L2_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R2_LUT4_I3_41_O I1=R2_LUT4_I3_40_O I2=R2_LUT4_I3_39_O I3=R2_LUT4_I3_38_O O=L2_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_37_O_LUT4_I2_O I3=L2_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_36_O_LUT4_I2_2_O I3=L2_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 O=L2_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_6_I2 I2=L2_LUT4_I3_3_I2_LUT4_O_I2 I3=L2_LUT4_I3_19_I1_LUT4_O_I3 O=L2_LUT4_I3_19_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_6_I2_LUT4_O_I2 I3=L2_LUT4_I3_6_I2_LUT4_O_I3 O=L2_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_1_O I1=L2_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_37_O_LUT4_I2_O O=L2_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_41_O I1=R2_LUT4_I3_40_O I2=R2_LUT4_I3_39_O I3=R2_LUT4_I3_38_O O=L2_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_36_O_LUT4_I2_2_O I3=L2_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I2=L2_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 I3=R2_LUT4_I3_37_O_LUT4_I2_O O=L2_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_36_O_LUT4_I2_O I1=L2_LUT4_I3_19_I0_LUT4_O_I1_LUT4_O_I2 I2=L2_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_36_O_LUT4_I2_1_O O=L2_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_41_O I1=R2_LUT4_I3_40_O I2=R2_LUT4_I3_39_O I3=R2_LUT4_I3_38_O O=L2_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L2_LUT4_I3_7_I0 I1=L2_LUT4_I3_I0 I2=L2_LUT4_I3_7_I2 I3=L2(28) O=R3_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_14_I2 I2=L2_LUT4_I3_I2_LUT4_O_I2 I3=L2_LUT4_I3_7_I0_LUT4_O_I3 O=L2_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_I2_LUT4_O_I1 O=L2_LUT4_I3_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_1_O I1=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_2_O I1=L2_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I2=L2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R2_LUT4_I3_22_O_LUT4_I2_1_O O=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I2=L2_LUT4_I3_14_I2_LUT4_O_I3 I3=R2_LUT4_I3_22_O_LUT4_I2_O O=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_21_O I1=R2_LUT4_I3_20_O I2=R2_LUT4_I3_19_O I3=R2_LUT4_I3_18_O O=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I2=L2_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3 I3=R2_LUT4_I3_22_O_LUT4_I2_2_O O=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_7_I2_LUT4_O_I1 I2=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L2_LUT4_I3_I0_LUT4_O_I2 O=L2_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_22_O_LUT4_I2_O O=L2_LUT4_I3_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_22_O_LUT4_I2_1_O O=L2_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=R2_LUT4_I3_22_O_LUT4_I2_2_O I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_19_O I1=R2_LUT4_I3_20_O I2=R2_LUT4_I3_21_O I3=R2_LUT4_I3_18_O O=L2_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L2_LUT4_I3_8_I0 I1=L2_LUT4_I3_8_I1 I2=L2_LUT4_I3_8_I2 I3=L2(3) O=R3_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_I3_LUT4_O_I3 I2=L2_LUT4_I3_8_I0_LUT4_O_I2 I3=L2_LUT4_I2_I3_LUT4_O_I0 O=L2_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_8_I1_LUT4_O_I2 I3=L2_LUT4_I3_8_I1_LUT4_O_I3 O=L2_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2 O=L2_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_2_O I1=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_4_O_LUT4_I2_1_O O=L2_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_5_O_LUT4_I2_O I3=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=L2_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_3_O I1=R2_LUT4_I3_1_O I2=R2_LUT4_I3_O I3=R2_LUT4_I3_2_O O=L2_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0 O=L2_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_5_O_LUT4_I2_O I1=L2_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R2_LUT4_I3_4_O_LUT4_I2_2_O O=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R2_LUT4_I3_4_O_LUT4_I2_1_O O=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_3_O I1=R2_LUT4_I3_2_O I2=R2_LUT4_I3_1_O I3=R2_LUT4_I3_O O=L2_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_8_I2_LUT4_O_I1 I2=L2_LUT4_I3_8_I2_LUT4_O_I2 I3=L2_LUT4_I3_8_I2_LUT4_O_I3 O=L2_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_5_O_LUT4_I2_O I1=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R2_LUT4_I3_4_O_LUT4_I2_2_O O=L2_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_2_O I1=R2_LUT4_I3_1_O I2=R2_LUT4_I3_3_O I3=R2_LUT4_I3_O O=L2_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_21_I2_LUT4_I2_I1_LUT4_O_I2 I2=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_4_O_LUT4_I2_1_O O=L2_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_4_O_LUT4_I2_2_O I3=L2_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_4_O_LUT4_I2_1_O I3=L2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 O=L2_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_4_O_LUT4_I2_O I1=L2_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_5_O_LUT4_I2_O I3=L2_LUT4_I3_21_I2_LUT4_I2_I1_LUT4_O_I2 O=L2_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_3_O I1=R2_LUT4_I3_2_O I2=R2_LUT4_I3_1_O I3=R2_LUT4_I3_O O=L2_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 I2=L2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L2_LUT4_I3_21_I1 O=L2_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L2_LUT4_I3_9_I0 I1=L2_LUT4_I3_9_I1 I2=L2_LUT4_I3_9_I2 I3=L2(4) O=R3_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_9_I0_LUT4_O_I1 I2=L2_LUT4_I1_1_I2 I3=L2_LUT4_I3_9_I0_LUT4_O_I3 O=L2_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_2_O I1=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_27_O I1=R2_LUT4_I3_25_O I2=R2_LUT4_I3_24_O I3=R2_LUT4_I3_26_O O=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_27_O I1=R2_LUT4_I3_24_O I2=R2_LUT4_I3_25_O I3=R2_LUT4_I3_26_O O=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_28_O_LUT4_I2_1_O I3=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_26_O I1=R2_LUT4_I3_24_O I2=R2_LUT4_I3_25_O I3=R2_LUT4_I3_27_O O=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L2_LUT4_I3_17_I1_LUT4_O_I1 I1=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_9_I1_LUT4_O_I1 O=L2_LUT4_I3_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=L2_LUT4_I1_1_I2_LUT4_O_I0 I2=R2_LUT4_I3_29_O I3=R2_LUT4_I3_28_O O=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_28_O_LUT4_I2_2_O I3=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_26_O I1=R2_LUT4_I3_27_O I2=R2_LUT4_I3_25_O I3=R2_LUT4_I3_24_O O=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_25_O I1=R2_LUT4_I3_26_O I2=R2_LUT4_I3_27_O I3=R2_LUT4_I3_24_O O=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_9_I1_LUT4_O_I1 I2=L2_LUT4_I3_9_I1_LUT4_O_I2 I3=L2_LUT4_I3_9_I0_LUT4_O_I1 O=L2_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_28_O_LUT4_I2_O O=L2_LUT4_I3_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I1 I3=R2_LUT4_I3_28_O_LUT4_I2_2_O O=L2_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_1_O I1=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 O=L2_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_27_O I1=R2_LUT4_I3_26_O I2=R2_LUT4_I3_25_O I3=R2_LUT4_I3_24_O O=L2_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I3=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 O=L2_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_9_I2_LUT4_O_I1 I2=L2_LUT4_I3_9_I2_LUT4_O_I2 I3=L2_LUT4_I3_9_I2_LUT4_O_I3 O=L2_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_1_O I1=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R2_LUT4_I3_28_O_LUT4_I2_2_O I3=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R2_LUT4_I3_29_O_LUT4_I2_O I3=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_27_O I1=R2_LUT4_I3_26_O I2=R2_LUT4_I3_25_O I3=R2_LUT4_I3_24_O O=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_1_O I1=L2_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R2_LUT4_I3_28_O_LUT4_I2_2_O I3=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_26_O I1=R2_LUT4_I3_25_O I2=R2_LUT4_I3_24_O I3=R2_LUT4_I3_27_O O=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_23_I1_LUT4_O_I2 O=L2_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_O I1=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=L2_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R2_LUT4_I3_28_O_LUT4_I2_2_O O=L2_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_28_O_LUT4_I2_1_O I1=L2_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 I2=L2_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R2_LUT4_I3_29_O_LUT4_I2_O O=L2_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O I1=L2_LUT4_I3_I0_LUT4_O_I1 I2=L2_LUT4_I3_I0_LUT4_O_I2 I3=L2_LUT4_I3_I0_LUT4_O_I3 O=L2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_7_I2_LUT4_O_I1 O=L2_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=L2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_1_O I1=L2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=L2_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1 I3=R2_LUT4_I3_23_O_LUT4_I2_O O=L2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R2_LUT4_I3_22_O_LUT4_I2_2_O I3=L2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=L2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R2_LUT4_I3_22_O_LUT4_I2_1_O I3=L2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_2_O I1=L2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2 O=L2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O I1=L2_LUT4_I3_I1_LUT4_O_I1 I2=L2_LUT4_I3_I0_LUT4_O_I1 I3=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=L2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L2_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_22_O_LUT4_I2_1_O I3=L2_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_20_O I1=R2_LUT4_I3_19_O I2=R2_LUT4_I3_18_O I3=R2_LUT4_I3_21_O O=L2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_2_O I1=L2_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1 O=L2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L2_LUT4_I3_I2_LUT4_O_I0 I1=L2_LUT4_I3_I2_LUT4_O_I1 I2=L2_LUT4_I3_I2_LUT4_O_I2 I3=L2_LUT4_I3_I2_LUT4_O_I3 O=L2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I1=L2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=R2_LUT4_I3_22_O I3=R2_LUT4_I3_23_O O=L2_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R2_LUT4_I3_21_O I1=R2_LUT4_I3_19_O I2=R2_LUT4_I3_20_O I3=R2_LUT4_I3_18_O O=L2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_22_O_LUT4_I2_2_O O=L2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_16_I2_LUT4_I3_I1_LUT4_O_I3 I3=R2_LUT4_I3_22_O_LUT4_I2_1_O O=L2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_21_O I1=R2_LUT4_I3_20_O I2=R2_LUT4_I3_19_O I3=R2_LUT4_I3_18_O O=L2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L2_LUT4_I3_14_I2_LUT4_O_I3 I1=R2_LUT4_I3_22_O_LUT4_I2_1_O I2=L2_LUT4_I3_16_I0_LUT4_O_I1 I3=L2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=L2_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R2_LUT4_I3_23_O_LUT4_I2_O I3=L2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=L2_LUT4_I3_16_I2_LUT4_I3_I2_LUT4_O_I1 I3=R2_LUT4_I3_22_O_LUT4_I2_2_O O=L2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_18_O I1=R2_LUT4_I3_20_O I2=R2_LUT4_I3_19_O I3=R2_LUT4_I3_21_O O=L2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R2_LUT4_I3_22_O_LUT4_I2_2_O O=L2_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_21_O I1=R2_LUT4_I3_19_O I2=R2_LUT4_I3_18_O I3=R2_LUT4_I3_20_O O=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_1_O I1=L2_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1 I2=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R2_LUT4_I3_23_O_LUT4_I2_O O=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_I2 I3=L2_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R2_LUT4_I3_22_O_LUT4_I2_O I1=L2_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 I2=L2_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R2_LUT4_I3_22_O_LUT4_I2_2_O O=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R2_LUT4_I3_21_O I1=R2_LUT4_I3_20_O I2=R2_LUT4_I3_19_O I3=R2_LUT4_I3_18_O O=L2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=L2(1) D=R1(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(2) D=R1(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(11) D=R1(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(12) D=R1(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(13) D=R1(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(14) D=R1(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(15) D=R1(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(16) D=R1(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(17) D=R1(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(18) D=R1(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(19) D=R1(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(20) D=R1(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(3) D=R1(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(21) D=R1(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(22) D=R1(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(23) D=R1(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(24) D=R1(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(25) D=R1(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(26) D=R1(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(27) D=R1(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(28) D=R1(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(29) D=R1(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(30) D=R1(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(4) D=R1(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(31) D=R1(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(32) D=R1(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(5) D=R1(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(6) D=R1(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(7) D=R1(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(8) D=R1(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(9) D=R1(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L2(10) D=R1(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:124.1-125.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L3(10) I2=L3_LUT4_I1_I2 I3=L3_LUT4_I1_I3 O=R4_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L3(1) I2=L3_LUT4_I1_1_I2 I3=L3_LUT4_I1_1_I3 O=R4_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I2_O I1=L3_LUT4_I1_1_I2_LUT4_O_I1 I2=L3_LUT4_I1_1_I2_LUT4_O_I2 I3=L3_LUT4_I3_22_I1 O=L3_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I1_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I3=R3_LUT4_I3_10_O_LUT4_I2_2_O O=L3_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_7_O I1=R3_LUT4_I3_6_O I2=R3_LUT4_I3_9_O I3=R3_LUT4_I3_8_O O=L3_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_1_O I1=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_11_O_LUT4_I2_O I3=L3_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 O=L3_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R3_LUT4_I3_11_O_LUT4_I2_O I3=L3_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_1_O I1=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I2=R3_LUT4_I3_10_O_LUT4_I2_2_O I3=L3_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_8_O I1=R3_LUT4_I3_6_O I2=R3_LUT4_I3_7_O I3=R3_LUT4_I3_9_O O=L3_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O I2=L3_LUT4_I1_1_I3_LUT4_O_I2 I3=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O O=L3_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_22_I2_LUT4_O_I2 I3=R3_LUT4_I3_11_O_LUT4_I2_O O=L3_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_10_O_LUT4_I2_2_O O=L3_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_10_O_LUT4_I2_1_O I3=L3_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=L3_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3(8) I2=L3_LUT4_I1_2_I2 I3=L3_LUT4_I1_2_I3 O=R4_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_2_I2_LUT4_O_I1 I2=L3_LUT4_I3_5_I2 I3=L3_LUT4_I1_2_I2_LUT4_O_I3 O=L3_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I1_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_5_O_LUT4_I2_O I1=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_4_O_LUT4_I2_2_O O=L3_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_4_O_LUT4_I2_1_O O=L3_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_4_O_LUT4_I2_2_O I3=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I0 O=L3_LUT4_I1_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_4_O_LUT4_I2_1_O I3=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_5_O_LUT4_I2_O I3=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I1_2_I3_LUT4_O_I0 I1=L3_LUT4_I2_I3_LUT4_O_I2 I2=L3_LUT4_I1_2_I3_LUT4_O_I2 I3=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=L3_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L3_LUT4_I3_15_I2_LUT4_O_I3 I1=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1 I2=L3_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_15_I2_LUT4_O_I1 O=L3_LUT4_I1_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_2_I2_LUT4_O_I1 I3=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 O=L3_LUT4_I1_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L3(11) I2=L3_LUT4_I1_3_I2 I3=L3_LUT4_I1_3_I3 O=R4_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L3_LUT4_I3_7_I2 I1=L3_LUT4_I1_3_I2_LUT4_O_I1 I2=L3_LUT4_I1_3_I2_LUT4_O_I2 I3=L3_LUT4_I1_3_I2_LUT4_O_I3 O=L3_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_18_I2_LUT4_O_I1 O=L3_LUT4_I1_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_29_O_LUT4_I2_O I1=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=L3_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_28_O_LUT4_I2_1_O O=L3_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_2_O I3=L3_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_26_O I1=R3_LUT4_I3_25_O I2=R3_LUT4_I3_24_O I3=R3_LUT4_I3_27_O O=L3_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_2_O I1=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_I2_I1 I2=L3_LUT4_I1_3_I2_LUT4_O_I2 I3=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_I2_I3 O=L3_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R3_LUT4_I3_26_O I1=R3_LUT4_I3_24_O I2=R3_LUT4_I3_25_O I3=R3_LUT4_I3_27_O O=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I1_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_2_O I3=L3_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_24_O I1=R3_LUT4_I3_26_O I2=R3_LUT4_I3_25_O I3=R3_LUT4_I3_27_O O=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_29_O_LUT4_I2_O I1=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_1_O I3=L3_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I1_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_29_O_LUT4_I2_O I1=L3_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_1_O I3=L3_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_I2_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_2_O I3=L3_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_27_O I1=R3_LUT4_I3_25_O I2=R3_LUT4_I3_24_O I3=R3_LUT4_I3_26_O O=L3_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_3_I3_LUT4_O_I2 I3=L3_LUT4_I1_3_I3_LUT4_O_I3 O=L3_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_1_O I3=L3_LUT4_I3_7_I2_LUT4_O_I3 O=L3_LUT4_I1_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_2_O I3=L3_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2 O=L3_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2 I2=L3_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_29_O_LUT4_I2_O O=L3_LUT4_I1_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_18_I1_LUT4_O_I2 O=L3_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_29_O_LUT4_I2_O I1=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2 I2=R3_LUT4_I3_28_O_LUT4_I2_2_O I3=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_27_O I1=R3_LUT4_I3_26_O I2=R3_LUT4_I3_24_O I3=R3_LUT4_I3_25_O O=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_1_O I3=L3_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2 O=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_25_O I1=R3_LUT4_I3_26_O I2=R3_LUT4_I3_27_O I3=R3_LUT4_I3_24_O O=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L3(12) I2=L3_LUT4_I1_4_I2 I3=L3_LUT4_I1_4_I3 O=R4_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_4_I2_LUT4_O_I1 I2=L3_LUT4_I3_3_I2_LUT4_O_I2 I3=L3_LUT4_I1_4_I2_LUT4_O_I3 O=L3_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_O I1=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R3_LUT4_I3_43_O I1=R3_LUT4_I3_44_O I2=R3_LUT4_I3_45_O I3=R3_LUT4_I3_42_O O=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_46_O_LUT4_I2_1_O O=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_2_O I1=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_47_O_LUT4_I2_O I3=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_44_O I1=R3_LUT4_I3_43_O I2=R3_LUT4_I3_45_O I3=R3_LUT4_I3_42_O O=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_45_O I1=R3_LUT4_I3_44_O I2=R3_LUT4_I3_43_O I3=R3_LUT4_I3_42_O O=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_3_I2_LUT4_O_I1 O=L3_LUT4_I1_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_1_O I1=L3_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I2 I2=L3_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_46_O_LUT4_I2_O O=L3_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_2_O I1=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2 I2=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_47_O_LUT4_I2_O O=L3_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I1_4_I3_LUT4_O_I0 I1=L3_LUT4_I1_4_I3_LUT4_O_I1 I2=L3_LUT4_I1_4_I3_LUT4_O_I2 I3=L3_LUT4_I3_12_I1_LUT4_O_I0_LUT4_I2_O O=L3_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2 I3=L3_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I3 O=L3_LUT4_I1_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_2_O I1=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_47_O_LUT4_I2_O I3=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_1_O I1=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R3_LUT4_I3_46_O_LUT4_I2_O I3=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_12_I2_LUT4_O_I3 I2=L3_LUT4_I3_24_I2_LUT4_O_I3 I3=L3_LUT4_I3_3_I1_LUT4_O_I3 O=L3_LUT4_I1_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_4_I3_LUT4_O_I0 I2=L3_LUT4_I3_3_I1_LUT4_O_I1 I3=L3_LUT4_I3_24_I2_LUT4_O_I1 O=L3_LUT4_I1_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O I1=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I2=L3_LUT4_I1_I2_LUT4_O_I2 I3=L3_LUT4_I1_I2_LUT4_O_I3 O=L3_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O I1=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I2=L3_LUT4_I1_I2_LUT4_O_I2 I3=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3 O=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1 I2=R3_LUT4_I3_10_O_LUT4_I2_1_O I3=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 O=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I3=R3_LUT4_I3_10_O_LUT4_I2_O O=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_11_O_LUT4_I2_O I1=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I2=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_10_O_LUT4_I2_2_O O=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_22_I2_LUT4_O_I2 I3=R3_LUT4_I3_10_O_LUT4_I2_O O=L3_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_10_O_LUT4_I2_1_O O=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_11_O_LUT4_I2_O I1=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R3_LUT4_I3_10_O_LUT4_I2_2_O O=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_8_O I1=R3_LUT4_I3_7_O I2=R3_LUT4_I3_6_O I3=R3_LUT4_I3_9_O O=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_11_O_LUT4_I2_O I1=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_10_O_LUT4_I2_2_O O=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_9_O I1=R3_LUT4_I3_6_O I2=R3_LUT4_I3_7_O I3=R3_LUT4_I3_8_O O=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_10_O_LUT4_I2_1_O I3=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 O=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_7_O I1=R3_LUT4_I3_8_O I2=R3_LUT4_I3_9_O I3=R3_LUT4_I3_6_O O=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L3_LUT4_I1_I3_LUT4_O_I1 I2=L3_LUT4_I1_I3_LUT4_O_I2 I3=L3_LUT4_I1_I3_LUT4_O_I3 O=L3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I1=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_11_O I3=R3_LUT4_I3_10_O O=L3_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R3_LUT4_I3_9_O I1=R3_LUT4_I3_8_O I2=R3_LUT4_I3_7_O I3=R3_LUT4_I3_6_O O=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_9_O I1=R3_LUT4_I3_7_O I2=R3_LUT4_I3_8_O I3=R3_LUT4_I3_6_O O=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L3_LUT4_I1_1_I3_LUT4_O_I2 I1=L3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_19_I1_LUT4_O_I2 I3=L3_LUT4_I1_I2_LUT4_O_I3 O=L3_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_22_I2_LUT4_O_I2 I3=R3_LUT4_I3_10_O_LUT4_I2_2_O O=L3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R3_LUT4_I3_10_O_LUT4_I2_1_O O=L3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_11_O_LUT4_I2_O O=L3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I2_O I1=L3_LUT4_I3_22_I1_LUT4_O_I3 I2=L3_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I1_1_I2_LUT4_O_I2 O=L3_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_10_O_LUT4_I2_1_O O=L3_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_9_O I1=R3_LUT4_I3_8_O I2=R3_LUT4_I3_7_O I3=R3_LUT4_I3_6_O O=L3_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3(3) I3=L3_LUT4_I2_I3 O=R4_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3(15) I3=L3_LUT4_I2_1_I3 O=R4_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L3_LUT4_I2_1_I3_LUT4_O_I0 I1=L3_LUT4_I3_6_I0_LUT4_I0_O I2=L3_LUT4_I2_1_I3_LUT4_O_I2 I3=L3_LUT4_I2_1_I3_LUT4_O_I3 O=L3_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L3_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3 O=L3_LUT4_I2_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_16_O_LUT4_I2_O I3=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_17_O_LUT4_I2_O I1=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_6_I0_LUT4_O_I3 I3=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O O=L3_LUT4_I2_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L3_LUT4_I2_I3_LUT4_O_I0 I1=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=L3_LUT4_I2_I3_LUT4_O_I2 I3=L3_LUT4_I2_I3_LUT4_O_I3 O=L3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1 I2=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L3_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2 I1=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_5_O_LUT4_I2_O O=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_4_O_LUT4_I2_1_O O=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_4_O_LUT4_I2_2_O I3=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3 I3=R3_LUT4_I3_4_O_LUT4_I2_1_O O=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_5_O_LUT4_I2_O O=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_3_O I1=R3_LUT4_I3_2_O I2=R3_LUT4_I3_1_O I3=R3_LUT4_I3_O O=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_5_I1 I1=L3_LUT4_I1_2_I2_LUT4_O_I3 I2=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_5_I1 I1=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I1 I2=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I0 I3=R3_LUT4_I3_4_O_LUT4_I2_O O=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_5_O_LUT4_I2_O I1=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_4_O_LUT4_I2_2_O I3=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_3_O I1=R3_LUT4_I3_2_O I2=R3_LUT4_I3_1_O I3=R3_LUT4_I3_O O=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_4_O_LUT4_I2_1_O I3=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_2_O I1=R3_LUT4_I3_3_O I2=R3_LUT4_I3_1_O I3=R3_LUT4_I3_O O=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L3_LUT4_I3_I0 I1=L3_LUT4_I3_I1 I2=L3_LUT4_I3_I2 I3=L3(2) O=R4_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L3_LUT4_I3_1_I0 I1=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I2=L3_LUT4_I3_1_I2 I3=L3(6) O=R4_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L3_LUT4_I3_18_I0 I1=L3_LUT4_I3_10_I1 I2=L3_LUT4_I3_10_I2 I3=L3(4) O=R4_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L3_LUT4_I3_7_I1_LUT4_O_I3 I1=L3_LUT4_I3_10_I1_LUT4_O_I1 I2=L3_LUT4_I3_18_I0_LUT4_O_I3 I3=L3_LUT4_I3_10_I1_LUT4_O_I3 O=L3_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1 I3=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2 O=L3_LUT4_I3_10_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_7_I1_LUT4_O_I0 I3=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L3_LUT4_I3_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L3_LUT4_I3_18_I2_LUT4_O_I3 I1=L3_LUT4_I3_10_I2_LUT4_O_I1 I2=L3_LUT4_I3_10_I2_LUT4_O_I2 I3=L3_LUT4_I3_10_I2_LUT4_O_I3 O=L3_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_28_O_LUT4_I2_2_O I3=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_29_O_LUT4_I2_O I1=L3_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_28_O_LUT4_I2_1_O O=L3_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_29_O_LUT4_I2_O I1=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_I2_I1 I2=L3_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_28_O_LUT4_I2_2_O O=L3_LUT4_I3_10_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_27_O I1=R3_LUT4_I3_24_O I2=R3_LUT4_I3_25_O I3=R3_LUT4_I3_26_O O=L3_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_1_O I3=L3_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_10_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_25_O I1=R3_LUT4_I3_24_O I2=R3_LUT4_I3_27_O I3=R3_LUT4_I3_26_O O=L3_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L3_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3 I1=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=R3_LUT4_I3_28_O I3=R3_LUT4_I3_29_O O=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=R3_LUT4_I3_27_O I1=R3_LUT4_I3_26_O I2=R3_LUT4_I3_25_O I3=R3_LUT4_I3_24_O O=L3_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L3_LUT4_I3_11_I0 I1=L3_LUT4_I3_11_I1 I2=L3_LUT4_I3_11_I2 I3=L3(5) O=R4_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L3_LUT4_I2_1_I3_LUT4_O_I0 I1=L3_LUT4_I3_6_I1_LUT4_O_I0 I2=L3_LUT4_I3_6_I0_LUT4_I0_O I3=L3_LUT4_I3_11_I0_LUT4_O_I3 O=L3_LUT4_I3_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=L3_LUT4_I3_11_I1_LUT4_O_I0 I1=L3_LUT4_I3_6_I2_LUT4_O_I1 I2=L3_LUT4_I3_11_I1_LUT4_O_I2 I3=L3_LUT4_I3_11_I1_LUT4_O_I3 O=L3_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_11_I1_LUT4_O_I0_LUT4_O_I1 I2=L3_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_16_O_LUT4_I2_1_O O=L3_LUT4_I3_11_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_11_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_16_O_LUT4_I2_O O=L3_LUT4_I3_11_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_17_O_LUT4_I2_O I1=L3_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L3_LUT4_I3_11_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_O I1=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_16_O_LUT4_I2_2_O O=L3_LUT4_I3_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_14_O I1=R3_LUT4_I3_12_O I2=R3_LUT4_I3_13_O I3=R3_LUT4_I3_15_O O=L3_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_17_O_LUT4_I2_O I3=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_15_O I1=R3_LUT4_I3_13_O I2=R3_LUT4_I3_14_O I3=R3_LUT4_I3_12_O O=L3_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_11_I2_LUT4_I2_I1 I2=L3_LUT4_I3_11_I2 I3=L3_LUT4_I3_11_I1_LUT4_O_I0 O=L3_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_11_I2_LUT4_O_I1 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_11_I2_LUT4_O_I3 O=L3_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_16_O_LUT4_I2_O O=L3_LUT4_I3_11_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_I3 I2=R3_LUT4_I3_17_O_LUT4_I2_O I3=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_11_I2_LUT4_O_I3 I2=R3_LUT4_I3_16_O_LUT4_I2_O I3=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_I3 O=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_15_O I1=R3_LUT4_I3_12_O I2=R3_LUT4_I3_13_O I3=R3_LUT4_I3_14_O O=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O I1=L3_LUT4_I3_6_I0_LUT4_I1_I3_LUT4_O_I2 I2=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2 I3=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3 O=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_O I1=L3_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2 I2=L3_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_17_O_LUT4_I2_O O=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I2=L3_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_16_O_LUT4_I2_2_O O=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_15_O I1=R3_LUT4_I3_14_O I2=R3_LUT4_I3_13_O I3=R3_LUT4_I3_12_O O=L3_LUT4_I3_11_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_12_I1_LUT4_O_I0_LUT4_I2_O I1=L3_LUT4_I3_12_I1 I2=L3_LUT4_I3_12_I2 I3=L3(7) O=R4_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L3_LUT4_I3_12_I1_LUT4_O_I0 I1=L3_LUT4_I3_12_I1_LUT4_O_I1 I2=L3_LUT4_I3_12_I1_LUT4_O_I2 I3=L3_LUT4_I3_12_I1_LUT4_O_I3 O=L3_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_12_I1_LUT4_O_I0_LUT4_I2_I1 I2=L3_LUT4_I3_12_I1_LUT4_O_I0 I3=L3_LUT4_I3_24_I1_LUT4_O_I3 O=L3_LUT4_I3_12_I1_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L3_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 I1=L3_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I2=L3_LUT4_I3_3_I2_LUT4_O_I1 I3=L3_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2 O=L3_LUT4_I3_12_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L3_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I0 I1=R3_LUT4_I3_47_O_LUT4_I2_O I2=R3_LUT4_I3_46_O_LUT4_I2_O I3=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_2_O I1=L3_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1 I2=R3_LUT4_I3_46_O_LUT4_I2_1_O I3=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_O I1=L3_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I2 I2=L3_LUT4_I3_12_I1_LUT4_O_I2 I3=L3_LUT4_I3_12_I1_LUT4_O_I3 O=L3_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_1_O I1=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_47_O_LUT4_I2_O O=L3_LUT4_I3_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=R3_LUT4_I3_46_O_LUT4_I2_O I2=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I1 I3=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3 O=L3_LUT4_I3_12_I1_LUT4_O_I0_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=L3_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1 I1=R3_LUT4_I3_47_O_LUT4_I2_O I2=R3_LUT4_I3_46_O_LUT4_I2_1_O I3=L3_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_44_O I1=R3_LUT4_I3_45_O I2=R3_LUT4_I3_43_O I3=R3_LUT4_I3_42_O O=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_45_O I1=R3_LUT4_I3_43_O I2=R3_LUT4_I3_44_O I3=R3_LUT4_I3_42_O O=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_2_O I1=L3_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_46_O_LUT4_I2_O I3=L3_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1 O=L3_LUT4_I3_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_45_O I1=R3_LUT4_I3_44_O I2=R3_LUT4_I3_43_O I3=R3_LUT4_I3_42_O O=L3_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L3_LUT4_I1_4_I3_LUT4_O_I2 I1=L3_LUT4_I3_24_I2_LUT4_O_I1 I2=L3_LUT4_I3_24_I2_LUT4_O_I3 I3=L3_LUT4_I3_12_I2_LUT4_O_I3 O=L3_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_47_O_LUT4_I2_O I1=L3_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I0 I2=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_46_O_LUT4_I2_O O=L3_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_2_O I1=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L3_LUT4_I3_24_I2_LUT4_O_I3_LUT4_O_I0 I3=R3_LUT4_I3_46_O_LUT4_I2_1_O O=L3_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_13_I0 I1=L3_LUT4_I3_13_I1 I2=L3_LUT4_I3_13_I2 I3=L3(9) O=R4_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=L3_LUT4_I3_21_I1_LUT4_O_I2 I1=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I2=L3_LUT4_I3_13_I0_LUT4_O_I2 I3=L3_LUT4_I3_13_I0_LUT4_O_I3 O=L3_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R3_LUT4_I3_37_O_LUT4_I2_O I1=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 I2=L3_LUT4_I3_13_I0_LUT4_O_I2 I3=L3_LUT4_I3_13_I0_LUT4_O_I3 O=L3_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_36_O_LUT4_I2_2_O I3=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2 O=L3_LUT4_I3_13_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3 I1=R3_LUT4_I3_36_O_LUT4_I2_2_O I2=R3_LUT4_I3_37_O_LUT4_I2_O I3=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_I2 I3=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O O=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 I2=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_36_O_LUT4_I2_1_O O=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_41_O I1=R3_LUT4_I3_38_O I2=R3_LUT4_I3_39_O I3=R3_LUT4_I3_40_O O=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_1_O I1=L3_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_37_O_LUT4_I2_O I3=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_40_O I1=R3_LUT4_I3_39_O I2=R3_LUT4_I3_41_O I3=R3_LUT4_I3_38_O O=L3_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_I2_O I1=L3_LUT4_I3_2_I0_LUT4_O_I3 I2=L3_LUT4_I3_21_I0_LUT4_O_I2 I3=L3_LUT4_I3_21_I0_LUT4_O_I1 O=L3_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_21_I2_LUT4_O_I2 I3=L3_LUT4_I3_2_I1_LUT4_O_I3 O=L3_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L3_LUT4_I3_14_I0 I1=L3_LUT4_I3_14_I1 I2=L3_LUT4_I3_14_I2 I3=L3(13) O=R4_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=L3_LUT4_I3_I0_LUT4_O_I2 I1=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I2=L3_LUT4_I3_I0_LUT4_O_I1 I3=L3_LUT4_I3_14_I0_LUT4_O_I3 O=L3_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_I1_LUT4_O_I1 I2=L3_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L3_LUT4_I3_14_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L3_LUT4_I3_14_I2_LUT4_O_I3 I1=R3_LUT4_I3_22_O_LUT4_I2_2_O I2=L3_LUT4_I3_I2_LUT4_O_I2 I3=L3_LUT4_I3_14_I1_LUT4_O_I3 O=L3_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I3=R3_LUT4_I3_22_O_LUT4_I2_1_O O=L3_LUT4_I3_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I3 I2=R3_LUT4_I3_22_O_LUT4_I2_O I3=L3_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_14_I2_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_14_I2_LUT4_O_I3 O=L3_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_22_O_LUT4_I2_2_O O=L3_LUT4_I3_14_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I1 I2=L3_LUT4_I3_17_I2_LUT4_I3_I2_LUT4_O_I1 I3=R3_LUT4_I3_22_O_LUT4_I2_O O=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_22_O_LUT4_I2_2_O I1=L3_LUT4_I3_17_I2_LUT4_I3_I2_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2 O=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I2=L3_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R3_LUT4_I3_22_O_LUT4_I2_O O=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I2=L3_LUT4_I3_14_I2_LUT4_O_I3 I3=R3_LUT4_I3_23_O_LUT4_I2_O O=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_21_O I1=R3_LUT4_I3_20_O I2=R3_LUT4_I3_19_O I3=R3_LUT4_I3_18_O O=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_21_O I1=R3_LUT4_I3_20_O I2=R3_LUT4_I3_19_O I3=R3_LUT4_I3_18_O O=L3_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=L3_LUT4_I3_5_I1 I2=L3_LUT4_I3_15_I2 I3=L3(14) O=R4_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L3_LUT4_I1_2_I3_LUT4_O_I2 I1=L3_LUT4_I3_15_I2_LUT4_O_I1 I2=L3_LUT4_I3_15_I2_LUT4_O_I2 I3=L3_LUT4_I3_15_I2_LUT4_O_I3 O=L3_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_15_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 I2=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_4_O_LUT4_I2_1_O O=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=R3_LUT4_I3_5_O_LUT4_I2_O I2=R3_LUT4_I3_4_O_LUT4_I2_2_O I3=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_5_O_LUT4_I2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R3_LUT4_I3_4_O_LUT4_I2_1_O I3=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_4_O_LUT4_I2_2_O O=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_3_O I1=R3_LUT4_I3_2_O I2=R3_LUT4_I3_1_O I3=R3_LUT4_I3_O O=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_5_O_LUT4_I2_O I1=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 I2=R3_LUT4_I3_4_O_LUT4_I2_1_O I3=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3 I2=R3_LUT4_I3_4_O_LUT4_I2_2_O I3=L3_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_I3_I1 I2=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_I3_I2 I3=L3_LUT4_I3_15_I2_LUT4_O_I2 O=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R3_LUT4_I3_5_O_LUT4_I2_O I3=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3 O=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_O I1=R3_LUT4_I3_2_O I2=R3_LUT4_I3_1_O I3=R3_LUT4_I3_3_O O=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_2_O I1=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_4_O_LUT4_I2_1_O O=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_4_O_LUT4_I2_1_O I3=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_1_O I1=R3_LUT4_I3_O I2=R3_LUT4_I3_3_O I3=R3_LUT4_I3_2_O O=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_3_O I1=R3_LUT4_I3_1_O I2=R3_LUT4_I3_O I3=R3_LUT4_I3_2_O O=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_5_O_LUT4_I2_O O=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_2_O I1=R3_LUT4_I3_1_O I2=R3_LUT4_I3_O I3=R3_LUT4_I3_3_O O=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_15_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_5_O_LUT4_I2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_4_O_LUT4_I2_1_O O=L3_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_2_O I1=R3_LUT4_I3_O I2=R3_LUT4_I3_1_O I3=R3_LUT4_I3_3_O O=L3_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 I3=R3_LUT4_I3_4_O_LUT4_I2_2_O O=L3_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_16_I0 I1=L3_LUT4_I3_23_I1 I2=L3_LUT4_I3_16_I2 I3=L3(16) O=R4_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_23_I2 I2=L3_LUT4_I3_1_I0_LUT4_O_I2 I3=L3_LUT4_I3_16_I0_LUT4_O_I3 O=L3_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_1_O I1=R3_LUT4_I3_34_O_LUT4_I2_O I2=L3_LUT4_I3_16_I2_LUT4_O_I2 I3=L3_LUT4_I3_16_I2_LUT4_O_I3 O=L3_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_2_O I1=L3_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I3 I2=R3_LUT4_I3_34_O_LUT4_I2_1_O I3=L3_LUT4_I3_16_I2_LUT4_O_I2 O=L3_LUT4_I3_16_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_33_O I1=R3_LUT4_I3_32_O I2=R3_LUT4_I3_31_O I3=R3_LUT4_I3_30_O O=L3_LUT4_I3_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_O I1=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 I2=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_34_O_LUT4_I2_1_O O=L3_LUT4_I3_16_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_17_I0 I1=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I2=L3_LUT4_I3_17_I2 I3=L3(18) O=R4_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_17_I0_LUT4_O_I1 I2=L3_LUT4_I3_14_I1 I3=L3_LUT4_I3_9_I0_LUT4_O_I3 O=L3_LUT4_I3_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_17_I0_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_17_I0_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_17_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_22_O_LUT4_I2_2_O I1=L3_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_22_O_LUT4_I2_1_O O=L3_LUT4_I3_17_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I2=R3_LUT4_I3_22_O_LUT4_I2_O I3=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_17_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_17_I2_LUT4_I3_I1 I2=L3_LUT4_I3_17_I2_LUT4_I3_I2 I3=L3_LUT4_I3_17_I2 O=L3_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_22_O_LUT4_I2_O I1=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I3 O=L3_LUT4_I3_17_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_20_O I1=R3_LUT4_I3_18_O I2=R3_LUT4_I3_19_O I3=R3_LUT4_I3_21_O O=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_21_O I1=R3_LUT4_I3_20_O I2=R3_LUT4_I3_18_O I3=R3_LUT4_I3_19_O O=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_17_I2_LUT4_I3_I2_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_2_O I3=L3_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_17_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_21_O I1=R3_LUT4_I3_20_O I2=R3_LUT4_I3_19_O I3=R3_LUT4_I3_18_O O=L3_LUT4_I3_17_I2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_17_I2_LUT4_O_I1 I2=L3_LUT4_I3_17_I2_LUT4_O_I2 I3=L3_LUT4_I3_I1_LUT4_O_I1 O=L3_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_22_O_LUT4_I2_O I1=L3_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_2_O I3=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_17_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_20_O I1=R3_LUT4_I3_19_O I2=R3_LUT4_I3_21_O I3=R3_LUT4_I3_18_O O=L3_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_19_O I1=R3_LUT4_I3_18_O I2=R3_LUT4_I3_21_O I3=R3_LUT4_I3_20_O O=L3_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I3 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_20_O I1=R3_LUT4_I3_21_O I2=R3_LUT4_I3_19_O I3=R3_LUT4_I3_18_O O=L3_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L3_LUT4_I3_18_I0 I1=L3_LUT4_I3_18_I1 I2=L3_LUT4_I3_18_I2 I3=L3(19) O=R4_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I1_LUT4_O_I3 I2=L3_LUT4_I1_3_I3 I3=L3_LUT4_I3_18_I0_LUT4_O_I3 O=L3_LUT4_I3_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L3_LUT4_I3_18_I1_LUT4_O_I2 I3=L3_LUT4_I3_18_I0_LUT4_O_I3 O=L3_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_18_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_2_O I1=L3_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R3_LUT4_I3_28_O_LUT4_I2_1_O O=L3_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_29_O_LUT4_I2_O I3=L3_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_18_I2_LUT4_O_I1 I2=L3_LUT4_I1_3_I2_LUT4_O_I2 I3=L3_LUT4_I3_18_I2_LUT4_O_I3 O=L3_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_18_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_2_O I1=L3_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_1_O I3=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0 O=L3_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_26_O I1=R3_LUT4_I3_27_O I2=R3_LUT4_I3_25_O I3=R3_LUT4_I3_24_O O=L3_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_29_O_LUT4_I2_O O=L3_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_3_I2_LUT4_O_I3 I2=L3_LUT4_I3_10_I2_LUT4_O_I1 I3=L3_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_18_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L3_LUT4_I3_19_I0 I1=L3_LUT4_I3_19_I1 I2=L3_LUT4_I3_19_I2 I3=L3(20) O=R4_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I3=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O O=L3_LUT4_I3_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_19_I1_LUT4_O_I2 I3=L3_LUT4_I1_1_I3_LUT4_O_I2 O=L3_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_19_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_10_O_LUT4_I2_1_O I3=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_10_O_LUT4_I2_2_O O=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I3=R3_LUT4_I3_10_O_LUT4_I2_1_O O=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=R3_LUT4_I3_11_O_LUT4_I2_O I3=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 O=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_8_O I1=R3_LUT4_I3_7_O I2=R3_LUT4_I3_9_O I3=R3_LUT4_I3_6_O O=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_11_O_LUT4_I2_O I1=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I2=R3_LUT4_I3_10_O_LUT4_I2_2_O I3=L3_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_1_I2_LUT4_O_I1 I2=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I2_O I3=L3_LUT4_I3_22_I2 O=L3_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L3_LUT4_I3_1_I0_LUT4_O_I0 I1=L3_LUT4_I3_1_I0_LUT4_O_I1 I2=L3_LUT4_I3_1_I0_LUT4_O_I2 I3=L3_LUT4_I3_4_I0_LUT4_O_I0_LUT4_I3_1_O_LUT4_I3_O O=L3_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_4_I1_LUT4_O_I2 I3=R3_LUT4_I3_34_O_LUT4_I2_O O=L3_LUT4_I3_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_34_O_LUT4_I2_1_O O=L3_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_23_I1_LUT4_O_I3_LUT4_O_I0 I2=R3_LUT4_I3_34_O_LUT4_I2_2_O I3=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_32_O I1=R3_LUT4_I3_30_O I2=R3_LUT4_I3_31_O I3=R3_LUT4_I3_33_O O=L3_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L3_LUT4_I3_1_I2_LUT4_O_I3 I1=R3_LUT4_I3_34_O_LUT4_I2_1_O I2=L3_LUT4_I3_23_I2_LUT4_O_I2 I3=L3_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_34_O_LUT4_I2_O O=L3_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 I2=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_34_O_LUT4_I2_2_O O=L3_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_1_I0_LUT4_O_I1 I1=L3_LUT4_I3_1_I2 I2=L3_LUT4_I3_4_I0_LUT4_O_I0_LUT4_I3_1_O_LUT4_I3_O I3=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=L3_LUT4_I3_16_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_1_I2_LUT4_O_I1 I2=R3_LUT4_I3_34_O_LUT4_I2_O I3=L3_LUT4_I3_1_I2_LUT4_O_I3 O=L3_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_34_O_LUT4_I2_1_O I3=L3_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_34_O_LUT4_I2_2_O O=L3_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_31_O I1=R3_LUT4_I3_32_O I2=R3_LUT4_I3_33_O I3=R3_LUT4_I3_30_O O=L3_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_33_O I1=R3_LUT4_I3_32_O I2=R3_LUT4_I3_31_O I3=R3_LUT4_I3_30_O O=L3_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L3_LUT4_I3_2_I0 I1=L3_LUT4_I3_2_I1 I2=L3_LUT4_I3_2_I2 I3=L3(17) O=R4_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L3_LUT4_I3_20_I0 I1=L3_LUT4_I3_20_I1 I2=L3_LUT4_I3_20_I2 I3=L3(21) O=R4_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_6_I1_LUT4_O_I0 I2=L3_LUT4_I2_1_I3_LUT4_O_I0 I3=L3_LUT4_I3_6_I0_LUT4_I0_O O=L3_LUT4_I3_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_6_I0_LUT4_O_I2 I2=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L3_LUT4_I3_6_I0_LUT4_I0_O O=L3_LUT4_I3_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_20_I2_LUT4_O_I1 I2=L3_LUT4_I3_20_I2_LUT4_O_I2 I3=L3_LUT4_I3_6_I2_LUT4_O_I0 O=L3_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_O I1=L3_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_20_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_17_O_LUT4_I2_O I3=L3_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_17_O_LUT4_I2_O I1=L3_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_6_I0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_15_O I1=R3_LUT4_I3_14_O I2=R3_LUT4_I3_13_O I3=R3_LUT4_I3_12_O O=L3_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_15_O I1=R3_LUT4_I3_14_O I2=R3_LUT4_I3_13_O I3=R3_LUT4_I3_12_O O=L3_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L3_LUT4_I3_21_I0 I1=L3_LUT4_I3_21_I1 I2=L3_LUT4_I3_21_I2 I3=L3(23) O=R4_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_21_I0_LUT4_O_I1 I2=L3_LUT4_I3_21_I0_LUT4_O_I2 I3=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_I2_O O=L3_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_36_O_LUT4_I2_1_O O=L3_LUT4_I3_21_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_40_O I1=R3_LUT4_I3_39_O I2=R3_LUT4_I3_38_O I3=R3_LUT4_I3_41_O O=L3_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_39_O I1=R3_LUT4_I3_40_O I2=R3_LUT4_I3_41_O I3=R3_LUT4_I3_38_O O=L3_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_2_O I1=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_37_O_LUT4_I2_O O=L3_LUT4_I3_21_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_39_O I1=R3_LUT4_I3_38_O I2=R3_LUT4_I3_41_O I3=R3_LUT4_I3_40_O O=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_38_O I1=R3_LUT4_I3_40_O I2=R3_LUT4_I3_39_O I3=R3_LUT4_I3_41_O O=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L3_LUT4_I3_8_I1 I1=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I2=L3_LUT4_I3_21_I1_LUT4_O_I2 I3=L3_LUT4_I3_21_I1_LUT4_O_I3 O=L3_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_36_O_LUT4_I2_2_O I3=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I0 O=L3_LUT4_I3_21_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 I3=R3_LUT4_I3_36_O_LUT4_I2_O O=L3_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_1_O I1=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_37_O_LUT4_I2_O I3=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_21_I2_LUT4_O_I2 I3=L3_LUT4_I3_2_I1_LUT4_O_I2 O=L3_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_1_O I1=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_37_O_LUT4_I2_O I3=L3_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_36_O_LUT4_I2_2_O O=L3_LUT4_I3_21_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_22_I0 I1=L3_LUT4_I3_22_I1 I2=L3_LUT4_I3_22_I2 I3=L3(26) O=R4_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L3_LUT4_I1_I2_LUT4_O_I2_LUT4_I2_O I1=L3_LUT4_I1_I3_LUT4_O_I2 I2=L3_LUT4_I3_19_I1 I3=L3_LUT4_I3_22_I0_LUT4_O_I3 O=L3_LUT4_I3_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I3=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O O=L3_LUT4_I3_22_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L3_LUT4_I3_22_I1_LUT4_O_I0 I1=L3_LUT4_I3_22_I1_LUT4_O_I1 I2=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I2_O I3=L3_LUT4_I3_22_I1_LUT4_O_I3 O=L3_LUT4_I3_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 I1=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1 I2=R3_LUT4_I3_11_O I3=R3_LUT4_I3_10_O O=L3_LUT4_I3_22_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R3_LUT4_I3_9_O I1=R3_LUT4_I3_8_O I2=R3_LUT4_I3_7_O I3=R3_LUT4_I3_6_O O=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_9_O I1=R3_LUT4_I3_8_O I2=R3_LUT4_I3_6_O I3=R3_LUT4_I3_7_O O=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0 I1=R3_LUT4_I3_11_O_LUT4_I2_O I2=R3_LUT4_I3_10_O_LUT4_I2_1_O I3=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_22_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0 I3=R3_LUT4_I3_10_O_LUT4_I2_2_O O=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I3=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1 I2=R3_LUT4_I3_10_O_LUT4_I2_1_O I3=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0 O=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_11_O_LUT4_I2_O I1=L3_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R3_LUT4_I3_10_O_LUT4_I2_2_O I3=L3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I2=L3_LUT4_I3_22_I1_LUT4_O_I0_LUT4_O_I0 I3=R3_LUT4_I3_10_O_LUT4_I2_O O=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_9_O I1=R3_LUT4_I3_8_O I2=R3_LUT4_I3_7_O I3=R3_LUT4_I3_6_O O=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_1_O I1=L3_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I2=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 I3=R3_LUT4_I3_11_O_LUT4_I2_O O=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_6_O I1=R3_LUT4_I3_8_O I2=R3_LUT4_I3_7_O I3=R3_LUT4_I3_9_O O=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_22_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_1_O I1=L3_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_10_O_LUT4_I2_2_O I3=L3_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 O=L3_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_10_O_LUT4_I2_O I1=L3_LUT4_I3_22_I1_LUT4_O_I1_LUT4_O_I3 I2=L3_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R3_LUT4_I3_11_O_LUT4_I2_O O=L3_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_8_O I1=R3_LUT4_I3_9_O I2=R3_LUT4_I3_7_O I3=R3_LUT4_I3_6_O O=L3_LUT4_I3_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_22_I2_LUT4_O_I1 I2=L3_LUT4_I3_22_I2_LUT4_O_I2 I3=R3_LUT4_I3_10_O_LUT4_I2_1_O O=L3_LUT4_I3_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_10_O_LUT4_I2_O O=L3_LUT4_I3_22_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_11_O_LUT4_I2_O I1=L3_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_10_O_LUT4_I2_2_O I3=L3_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_9_O I1=R3_LUT4_I3_7_O I2=R3_LUT4_I3_6_O I3=R3_LUT4_I3_8_O O=L3_LUT4_I3_22_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_9_O I1=R3_LUT4_I3_8_O I2=R3_LUT4_I3_7_O I3=R3_LUT4_I3_6_O O=L3_LUT4_I3_22_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_23_I0 I1=L3_LUT4_I3_23_I1 I2=L3_LUT4_I3_23_I2 I3=L3(30) O=R4_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_23_I0_LUT4_O_I2 I3=L3_LUT4_I3_4_I2_LUT4_O_I1 O=L3_LUT4_I3_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L3_LUT4_I3_4_I0_LUT4_O_I0_LUT4_I3_1_O_LUT4_I3_O I1=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I2=L3_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_23_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I0 I2=R3_LUT4_I3_34_O_LUT4_I2_2_O I3=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I3 O=L3_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_O I1=L3_LUT4_I3_23_I1_LUT4_O_I3_LUT4_O_I0 I2=R3_LUT4_I3_34_O_LUT4_I2_1_O I3=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_23_I1_LUT4_O_I0 I1=L3_LUT4_I3_4_I1 I2=L3_LUT4_I3_23_I1_LUT4_O_I2 I3=L3_LUT4_I3_23_I1_LUT4_O_I3 O=L3_LUT4_I3_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_I3_I2 I3=L3_LUT4_I3_23_I1_LUT4_O_I0 O=L3_LUT4_I3_4_I1_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I0 I1=R3_LUT4_I3_34_O_LUT4_I2_2_O I2=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I2 I3=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I3 O=L3_LUT4_I3_23_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=R3_LUT4_I3_32_O I1=R3_LUT4_I3_31_O I2=R3_LUT4_I3_33_O I3=R3_LUT4_I3_30_O O=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_35_O_LUT4_I2_O O=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_33_O I1=R3_LUT4_I3_32_O I2=R3_LUT4_I3_31_O I3=R3_LUT4_I3_30_O O=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_4_I1_LUT4_O_I2 I2=R3_LUT4_I3_34_O_LUT4_I2_2_O I3=L3_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_23_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_33_O I1=R3_LUT4_I3_31_O I2=R3_LUT4_I3_30_O I3=R3_LUT4_I3_32_O O=L3_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L3_LUT4_I3_23_I1_LUT4_O_I3_LUT4_O_I0 I1=L3_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I3 I2=R3_LUT4_I3_35_O I3=R3_LUT4_I3_34_O O=L3_LUT4_I3_23_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=R3_LUT4_I3_30_O I1=R3_LUT4_I3_32_O I2=R3_LUT4_I3_31_O I3=R3_LUT4_I3_33_O O=L3_LUT4_I3_23_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_23_I2_LUT4_O_I2 I3=L3_LUT4_I3_4_I2_LUT4_O_I2 O=L3_LUT4_I3_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_2_O I1=R3_LUT4_I3_35_O_LUT4_I2_O I2=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_23_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_2_O I1=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_34_O_LUT4_I2_1_O I3=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I0 O=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_34_O_LUT4_I2_O I3=L3_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_32_O I1=R3_LUT4_I3_33_O I2=R3_LUT4_I3_31_O I3=R3_LUT4_I3_30_O O=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R3_LUT4_I3_34_O_LUT4_I2_2_O I3=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_12_I1_LUT4_O_I0_LUT4_I2_O I1=L3_LUT4_I3_24_I1 I2=L3_LUT4_I3_24_I2 I3=L3(32) O=R4_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_3_I2_LUT4_O_I3 I2=L3_LUT4_I3_3_I2_LUT4_O_I2 I3=L3_LUT4_I3_24_I1_LUT4_O_I3 O=L3_LUT4_I3_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I1_4_I2_LUT4_O_I1 I2=L3_LUT4_I3_3_I2_LUT4_O_I2 I3=L3_LUT4_I3_12_I1_LUT4_O_I1 O=L3_LUT4_I3_24_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_24_I2_LUT4_O_I1 I2=L3_LUT4_I3_3_I1_LUT4_O_I3 I3=L3_LUT4_I3_24_I2_LUT4_O_I3 O=L3_LUT4_I3_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_24_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1 I3=R3_LUT4_I3_46_O_LUT4_I2_2_O O=L3_LUT4_I3_24_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_24_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=R3_LUT4_I3_46_O_LUT4_I2_1_O O=L3_LUT4_I3_24_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_47_O_LUT4_I2_O I1=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L3_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_46_O_LUT4_I2_O O=L3_LUT4_I3_24_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_24_I2_LUT4_O_I3_LUT4_O_I0 I1=L3_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I0 I2=R3_LUT4_I3_46_O_LUT4_I2_2_O I3=R3_LUT4_I3_46_O_LUT4_I2_1_O O=L3_LUT4_I3_24_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_2_O I1=L3_LUT4_I3_24_I2_LUT4_O_I3_LUT4_O_I0 I2=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_47_O_LUT4_I2_O O=L3_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_45_O I1=R3_LUT4_I3_44_O I2=R3_LUT4_I3_42_O I3=R3_LUT4_I3_43_O O=L3_LUT4_I3_24_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_I2_O I1=L3_LUT4_I3_2_I0_LUT4_O_I1 I2=L3_LUT4_I3_2_I0_LUT4_O_I2 I3=L3_LUT4_I3_2_I0_LUT4_O_I3 O=L3_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 I1=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_37_O I3=R3_LUT4_I3_36_O O=L3_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_36_O_LUT4_I2_2_O O=L3_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_40_O I1=R3_LUT4_I3_38_O I2=R3_LUT4_I3_39_O I3=R3_LUT4_I3_41_O O=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_41_O I1=R3_LUT4_I3_39_O I2=R3_LUT4_I3_40_O I3=R3_LUT4_I3_38_O O=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_2_O I1=L3_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_37_O_LUT4_I2_O O=L3_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_36_O_LUT4_I2_1_O I3=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_2_I1_LUT4_O_I2 I3=L3_LUT4_I3_2_I1_LUT4_O_I3 O=L3_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L3_LUT4_I3_2_I1_LUT4_O_I3 I1=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_I2_I1 I2=L3_LUT4_I3_2_I1_LUT4_O_I2 I3=L3_LUT4_I3_21_I2_LUT4_O_I2 O=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=R3_LUT4_I3_36_O_LUT4_I2_1_O I3=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I0 O=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_1_O I1=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_36_O_LUT4_I2_2_O O=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2 I2=R3_LUT4_I3_37_O_LUT4_I2_O I3=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I0 I3=R3_LUT4_I3_36_O_LUT4_I2_O O=L3_LUT4_I3_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_36_O_LUT4_I2_1_O I3=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I1 I1=R3_LUT4_I3_36_O_LUT4_I2_2_O I2=R3_LUT4_I3_37_O_LUT4_I2_O I3=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 O=L3_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_2_I2_LUT4_O_I0 I1=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I2=L3_LUT4_I3_2_I2_LUT4_O_I2 I3=L3_LUT4_I3_8_I1_LUT4_O_I1 O=L3_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_1_O I1=L3_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I2 I3=L3_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I3 O=L3_LUT4_I3_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_36_O_LUT4_I2_2_O I3=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_2_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_36_O_LUT4_I2_1_O I3=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_41_O I1=R3_LUT4_I3_40_O I2=R3_LUT4_I3_39_O I3=R3_LUT4_I3_38_O O=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_41_O I1=R3_LUT4_I3_40_O I2=R3_LUT4_I3_39_O I3=R3_LUT4_I3_38_O O=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L3_LUT4_I3_12_I1_LUT4_O_I0_LUT4_I2_O I1=L3_LUT4_I3_3_I1 I2=L3_LUT4_I3_3_I2 I3=L3(22) O=R4_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=L3_LUT4_I3_3_I1_LUT4_O_I0 I1=L3_LUT4_I3_3_I1_LUT4_O_I1 I2=L3_LUT4_I3_3_I1_LUT4_O_I2 I3=L3_LUT4_I3_3_I1_LUT4_O_I3 O=L3_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L3_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I0 I1=L3_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1 I2=R3_LUT4_I3_47_O I3=R3_LUT4_I3_46_O O=L3_LUT4_I3_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=R3_LUT4_I3_47_O_LUT4_I2_O I1=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_46_O_LUT4_I2_O I3=L3_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I0 O=L3_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_45_O I1=R3_LUT4_I3_44_O I2=R3_LUT4_I3_43_O I3=R3_LUT4_I3_42_O O=L3_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R3_LUT4_I3_43_O I1=R3_LUT4_I3_42_O I2=R3_LUT4_I3_45_O I3=R3_LUT4_I3_44_O O=L3_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_46_O_LUT4_I2_2_O O=L3_LUT4_I3_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_46_O_LUT4_I2_1_O O=L3_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_45_O I1=R3_LUT4_I3_44_O I2=R3_LUT4_I3_43_O I3=R3_LUT4_I3_42_O O=L3_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I0 I1=R3_LUT4_I3_46_O_LUT4_I2_O I2=R3_LUT4_I3_47_O_LUT4_I2_O I3=L3_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_45_O I1=R3_LUT4_I3_43_O I2=R3_LUT4_I3_42_O I3=R3_LUT4_I3_44_O O=L3_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_44_O I1=R3_LUT4_I3_43_O I2=R3_LUT4_I3_42_O I3=R3_LUT4_I3_45_O O=L3_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_12_I2_LUT4_O_I3 O=L3_LUT4_I3_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_2_O I1=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_46_O_LUT4_I2_1_O O=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_44_O I1=R3_LUT4_I3_42_O I2=R3_LUT4_I3_43_O I3=R3_LUT4_I3_45_O O=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_47_O_LUT4_I2_O I1=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_46_O_LUT4_I2_O O=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_45_O I1=R3_LUT4_I3_44_O I2=R3_LUT4_I3_43_O I3=R3_LUT4_I3_42_O O=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_3_I2_LUT4_O_I1 I2=L3_LUT4_I3_3_I2_LUT4_O_I2 I3=L3_LUT4_I3_3_I2_LUT4_O_I3 O=L3_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_1_O I1=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_46_O_LUT4_I2_O I3=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_42_O I1=R3_LUT4_I3_44_O I2=R3_LUT4_I3_43_O I3=R3_LUT4_I3_45_O O=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_2_O I1=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_47_O_LUT4_I2_O O=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_45_O I1=R3_LUT4_I3_42_O I2=R3_LUT4_I3_43_O I3=R3_LUT4_I3_44_O O=L3_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_47_O_LUT4_I2_O I1=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_46_O_LUT4_I2_2_O O=L3_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_46_O_LUT4_I2_1_O I1=L3_LUT4_I3_3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_46_O_LUT4_I2_O I3=L3_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2 O=L3_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1 I3=R3_LUT4_I3_46_O_LUT4_I2_1_O O=L3_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L3_LUT4_I3_4_I0 I1=L3_LUT4_I3_4_I1 I2=L3_LUT4_I3_4_I2 I3=L3(24) O=R4_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L3_LUT4_I3_4_I0_LUT4_O_I0 I1=R3_LUT4_I3_34_O I2=R3_LUT4_I3_35_O I3=L3_LUT4_I3_4_I0_LUT4_O_I3 O=L3_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I3 I2=R3_LUT4_I3_34_O_LUT4_I2_O I3=L3_LUT4_I3_4_I0_LUT4_O_I0 O=L3_LUT4_I3_4_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_2_O I1=L3_LUT4_I3_23_I1_LUT4_O_I3_LUT4_O_I0 I2=R3_LUT4_I3_34_O_LUT4_I2_1_O I3=L3_LUT4_I3_4_I0_LUT4_O_I0 O=L3_LUT4_I3_4_I0_LUT4_O_I0_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O I3=L3_LUT4_I3_4_I0_LUT4_O_I0_LUT4_I3_1_O O=L3_LUT4_I3_4_I0_LUT4_O_I0_LUT4_I3_1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_2_O I1=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 I2=L3_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3 I3=L3_LUT4_I3_4_I0_LUT4_O_I0_LUT4_I3_O O=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R3_LUT4_I3_31_O I1=R3_LUT4_I3_30_O I2=R3_LUT4_I3_33_O I3=R3_LUT4_I3_32_O O=L3_LUT4_I3_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_O I1=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_34_O_LUT4_I2_1_O I3=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_33_O I1=R3_LUT4_I3_31_O I2=R3_LUT4_I3_32_O I3=R3_LUT4_I3_30_O O=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_32_O I1=R3_LUT4_I3_31_O I2=R3_LUT4_I3_30_O I3=R3_LUT4_I3_33_O O=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L3_LUT4_I3_4_I1_LUT4_I2_I0 I1=L3_LUT4_I3_4_I2_LUT4_O_I1 I2=L3_LUT4_I3_4_I1 I3=L3_LUT4_I3_23_I1_LUT4_O_I2 O=L3_LUT4_I3_1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_4_I1_LUT4_O_I1 I2=L3_LUT4_I3_4_I1_LUT4_O_I2 I3=R3_LUT4_I3_34_O_LUT4_I2_1_O O=L3_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_34_O_LUT4_I2_2_O O=L3_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I3 I2=L3_LUT4_I3_23_I1_LUT4_O_I0_LUT4_O_I0 I3=R3_LUT4_I3_34_O_LUT4_I2_O O=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_35_O_LUT4_I2_O I1=L3_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_34_O_LUT4_I2_O I3=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2 O=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_33_O I1=R3_LUT4_I3_30_O I2=R3_LUT4_I3_31_O I3=R3_LUT4_I3_32_O O=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_33_O I1=R3_LUT4_I3_32_O I2=R3_LUT4_I3_31_O I3=R3_LUT4_I3_30_O O=L3_LUT4_I3_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_4_I2_LUT4_O_I0 I1=L3_LUT4_I3_4_I2_LUT4_O_I1 I2=L3_LUT4_I3_4_I2_LUT4_O_I2 I3=L3_LUT4_I3_16_I2 O=L3_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I2=L3_LUT4_I3_4_I0_LUT4_O_I0_LUT4_I3_1_O_LUT4_I3_O I3=L3_LUT4_I3_1_I0_LUT4_O_I1 O=L3_LUT4_I3_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_1_I2_LUT4_O_I3 I3=R3_LUT4_I3_35_O_LUT4_I2_O O=L3_LUT4_I3_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_16_I2_LUT4_O_I2_LUT4_I3_O I2=R3_LUT4_I3_34_O_LUT4_I2_O I3=L3_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_34_O_LUT4_I2_2_O I3=L3_LUT4_I3_1_I2_LUT4_O_I3 O=L3_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_34_O_LUT4_I2_2_O I1=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_35_O_LUT4_I2_O O=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=R3_LUT4_I3_33_O I1=R3_LUT4_I3_32_O I2=R3_LUT4_I3_31_O I3=R3_LUT4_I3_30_O O=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_33_O I1=R3_LUT4_I3_32_O I2=R3_LUT4_I3_30_O I3=R3_LUT4_I3_31_O O=L3_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L3_LUT4_I3_5_I0 I1=L3_LUT4_I3_5_I1 I2=L3_LUT4_I3_5_I2 I3=L3(25) O=R4_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=L3_LUT4_I1_2_I2_LUT4_O_I3 I2=L3_LUT4_I3_5_I0_LUT4_O_I2 I3=L3_LUT4_I3_5_I0_LUT4_O_I3 O=L3_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I0 I1=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_4_O_LUT4_I2_2_O I3=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_5_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R3_LUT4_I3_3_O I1=R3_LUT4_I3_2_O I2=R3_LUT4_I3_1_O I3=R3_LUT4_I3_O O=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_3_O I1=R3_LUT4_I3_1_O I2=R3_LUT4_I3_2_O I3=R3_LUT4_I3_O O=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_5_O_LUT4_I2_O I3=L3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_2_O I1=R3_LUT4_I3_1_O I2=R3_LUT4_I3_3_O I3=R3_LUT4_I3_O O=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L3_LUT4_I3_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_4_O_LUT4_I2_2_O I3=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3 O=L3_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_5_O_LUT4_I2_O I1=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_4_O_LUT4_I2_1_O I3=L3_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_5_I1_LUT4_O_I1 I2=L3_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_4_O_LUT4_I2_O O=L3_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I0 I3=R3_LUT4_I3_5_O_LUT4_I2_O O=L3_LUT4_I3_5_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_2_O I1=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_5_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_4_O_LUT4_I2_1_O O=L3_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_5_I0_LUT4_O_I2 I2=L3_LUT4_I3_5_I2 I3=L3_LUT4_I1_2_I2_LUT4_O_I3 O=L3_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_5_I2_LUT4_O_I2 I3=L3_LUT4_I3_5_I2_LUT4_O_I3 O=L3_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_5_O_LUT4_I2_O I1=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_4_O_LUT4_I2_2_O O=L3_LUT4_I3_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_3_O I1=R3_LUT4_I3_2_O I2=R3_LUT4_I3_O I3=R3_LUT4_I3_1_O O=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_1_O I1=R3_LUT4_I3_2_O I2=R3_LUT4_I3_3_O I3=R3_LUT4_I3_O O=L3_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_4_O_LUT4_I2_O I1=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_4_O_LUT4_I2_1_O I3=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_3_O I1=R3_LUT4_I3_2_O I2=R3_LUT4_I3_1_O I3=R3_LUT4_I3_O O=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_3_O I1=R3_LUT4_I3_O I2=R3_LUT4_I3_1_O I3=R3_LUT4_I3_2_O O=L3_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L3_LUT4_I3_6_I0 I1=L3_LUT4_I3_6_I1 I2=L3_LUT4_I3_6_I2 I3=L3(27) O=R4_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L3_LUT4_I3_6_I0 I1=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I2=L3_LUT4_I3_6_I1_LUT4_O_I3 I3=L3_LUT4_I3_6_I1_LUT4_O_I1 O=L3_LUT4_I3_6_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_6_I1_LUT4_O_I3 I1=L3_LUT4_I3_6_I0 I2=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L3_LUT4_I3_6_I0_LUT4_I1_I3 O=L3_LUT4_I3_11_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_6_I0_LUT4_I1_I3_LUT4_O_I2 I3=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O O=L3_LUT4_I3_6_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_6_I0_LUT4_O_I2 I3=L3_LUT4_I3_6_I0_LUT4_O_I3 O=L3_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_O I1=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0 O=L3_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_17_O_LUT4_I2_O I3=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_13_O I1=R3_LUT4_I3_14_O I2=R3_LUT4_I3_15_O I3=R3_LUT4_I3_12_O O=L3_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0 I2=R3_LUT4_I3_16_O_LUT4_I2_O I3=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_17_O_LUT4_I2_O I1=L3_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_6_I1_LUT4_O_I0 I1=L3_LUT4_I3_6_I1_LUT4_O_I1 I2=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L3_LUT4_I3_6_I1_LUT4_O_I3 O=L3_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2 I3=L3_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3 O=L3_LUT4_I3_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_16_O_LUT4_I2_O O=L3_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_17_O_LUT4_I2_O I1=L3_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 O=L3_LUT4_I3_6_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0 I1=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_16_O_LUT4_I2_O I3=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R3_LUT4_I3_12_O I1=R3_LUT4_I3_14_O I2=R3_LUT4_I3_13_O I3=R3_LUT4_I3_15_O O=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_14_O I1=R3_LUT4_I3_13_O I2=R3_LUT4_I3_15_O I3=R3_LUT4_I3_12_O O=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L3_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1 I1=R3_LUT4_I3_16_O_LUT4_I2_2_O I2=R3_LUT4_I3_17_O_LUT4_I2_O I3=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I1=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R3_LUT4_I3_13_O I1=R3_LUT4_I3_12_O I2=R3_LUT4_I3_15_O I3=R3_LUT4_I3_14_O O=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_14_O I1=R3_LUT4_I3_13_O I2=R3_LUT4_I3_12_O I3=R3_LUT4_I3_15_O O=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L3_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=R3_LUT4_I3_16_O_LUT4_I2_O I2=R3_LUT4_I3_16_O_LUT4_I2_1_O I3=L3_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L3_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_6_I2_LUT4_O_I0 I1=L3_LUT4_I3_6_I2_LUT4_O_I1 I2=L3_LUT4_I3_6_I2_LUT4_O_I2 I3=L3_LUT4_I3_6_I2_LUT4_O_I3 O=L3_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_11_I2_LUT4_O_I3 I1=R3_LUT4_I3_16_O_LUT4_I2_O I2=L3_LUT4_I3_11_I1_LUT4_O_I0 I3=L3_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3 O=L3_LUT4_I3_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_16_O_LUT4_I2_2_O O=L3_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 I2=R3_LUT4_I3_17_O_LUT4_I2_O I3=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_I3 O=L3_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 I2=L3_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_16_O_LUT4_I2_O O=L3_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_14_O I1=R3_LUT4_I3_15_O I2=R3_LUT4_I3_13_O I3=R3_LUT4_I3_12_O O=L3_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L3_LUT4_I3_11_I2_LUT4_O_I3_LUT4_I1_I3 I1=R3_LUT4_I3_16_O_LUT4_I2_2_O I2=R3_LUT4_I3_17_O_LUT4_I2_O I3=L3_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L3_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_6_I2_LUT4_O_I2 I1=L3_LUT4_I3_6_I2_LUT4_O_I3 I2=L3_LUT4_I3_20_I2_LUT4_O_I2 I3=L3_LUT4_I3_20_I2_LUT4_O_I1 O=L3_LUT4_I3_11_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R3_LUT4_I3_17_O_LUT4_I2_O I1=L3_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_16_O_LUT4_I2_2_O I3=L3_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_15_O I1=R3_LUT4_I3_14_O I2=R3_LUT4_I3_13_O I3=R3_LUT4_I3_12_O O=L3_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_15_O I1=R3_LUT4_I3_14_O I2=R3_LUT4_I3_12_O I3=R3_LUT4_I3_13_O O=L3_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_16_O_LUT4_I2_1_O I1=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_16_O_LUT4_I2_O I3=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_15_O I1=R3_LUT4_I3_13_O I2=R3_LUT4_I3_12_O I3=R3_LUT4_I3_14_O O=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_15_O I1=R3_LUT4_I3_14_O I2=R3_LUT4_I3_13_O I3=R3_LUT4_I3_12_O O=L3_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L3_LUT4_I3_7_I1 I2=L3_LUT4_I3_7_I2 I3=L3(29) O=R4_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L3_LUT4_I3_7_I1_LUT4_O_I0 I1=L3_LUT4_I3_7_I1_LUT4_O_I1 I2=L3_LUT4_I3_7_I1_LUT4_O_I2 I3=L3_LUT4_I3_7_I1_LUT4_O_I3 O=L3_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_2_O I3=L3_LUT4_I3_7_I2_LUT4_O_I3 O=L3_LUT4_I3_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2 I3=R3_LUT4_I3_29_O_LUT4_I2_O O=L3_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_28_O_LUT4_I2_1_O O=L3_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_28_O_LUT4_I2_O O=L3_LUT4_I3_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_28_O_LUT4_I2_1_O O=L3_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_29_O_LUT4_I2_O I1=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_2_O I3=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_27_O I1=R3_LUT4_I3_26_O I2=R3_LUT4_I3_25_O I3=R3_LUT4_I3_24_O O=L3_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=L3_LUT4_I1_3_I2_LUT4_O_I1 I3=L3_LUT4_I1_3_I3_LUT4_O_I2 O=L3_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0 I1=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_O I3=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_2_O I1=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0 I2=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_28_O_LUT4_I2_1_O O=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I2=L3_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_29_O_LUT4_I2_O O=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_O I2=L3_LUT4_I3_7_I2_LUT4_O_I3 I3=R3_LUT4_I3_28_O_LUT4_I2_O O=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_26_O I1=R3_LUT4_I3_25_O I2=R3_LUT4_I3_27_O I3=R3_LUT4_I3_24_O O=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_27_O I1=R3_LUT4_I3_25_O I2=R3_LUT4_I3_26_O I3=R3_LUT4_I3_24_O O=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=R3_LUT4_I3_28_O_LUT4_I2_1_O I2=L3_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=L3_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L3_LUT4_I3_7_I1_LUT4_O_I0 I2=L3_LUT4_I3_7_I2 I3=L3_LUT4_I3_7_I1_LUT4_O_I1 O=L3_LUT4_I3_18_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I2_LUT4_O_I1 I2=R3_LUT4_I3_29_O_LUT4_I2_O I3=L3_LUT4_I3_7_I2_LUT4_O_I3 O=L3_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_28_O_LUT4_I2_2_O O=L3_LUT4_I3_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_28_O_LUT4_I2_O I1=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_28_O_LUT4_I2_1_O I3=L3_LUT4_I1_3_I2_LUT4_O_I2_LUT4_I2_I1 O=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_27_O I1=R3_LUT4_I3_26_O I2=R3_LUT4_I3_25_O I3=R3_LUT4_I3_24_O O=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_27_O I1=R3_LUT4_I3_26_O I2=R3_LUT4_I3_25_O I3=R3_LUT4_I3_24_O O=L3_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_27_O I1=R3_LUT4_I3_26_O I2=R3_LUT4_I3_25_O I3=R3_LUT4_I3_24_O O=L3_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_8_I0 I1=L3_LUT4_I3_8_I1 I2=L3_LUT4_I3_8_I2 I3=L3(31) O=R4_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L3_LUT4_I3_2_I1_LUT4_O_I2_LUT4_I2_O I1=L3_LUT4_I3_8_I0_LUT4_O_I1 I2=L3_LUT4_I3_8_I0_LUT4_O_I2 I3=L3_LUT4_I3_2_I1_LUT4_O_I3 O=L3_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L3_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 I1=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_37_O I3=R3_LUT4_I3_36_O O=L3_LUT4_I3_8_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_37_O_LUT4_I2_O I3=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_40_O I1=R3_LUT4_I3_41_O I2=R3_LUT4_I3_39_O I3=R3_LUT4_I3_38_O O=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_41_O I1=R3_LUT4_I3_39_O I2=R3_LUT4_I3_38_O I3=R3_LUT4_I3_40_O O=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_8_I1_LUT4_O_I1 I2=L3_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I3=L3_LUT4_I3_8_I1_LUT4_O_I3 O=L3_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I0 I1=R3_LUT4_I3_37_O_LUT4_I2_O I2=R3_LUT4_I3_36_O_LUT4_I2_2_O I3=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_41_O I1=R3_LUT4_I3_40_O I2=R3_LUT4_I3_39_O I3=R3_LUT4_I3_38_O O=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R3_LUT4_I3_41_O I1=R3_LUT4_I3_40_O I2=R3_LUT4_I3_39_O I3=R3_LUT4_I3_38_O O=L3_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_2_I2_LUT4_O_I2 O=L3_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_1_O I1=L3_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_36_O_LUT4_I2_2_O I3=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1 I3=R3_LUT4_I3_37_O_LUT4_I2_O O=L3_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_8_I2 I2=L3_LUT4_I3_2_I2_LUT4_O_I0 I3=L3_LUT4_I3_21_I1_LUT4_O_I3 O=L3_LUT4_I3_21_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_8_I2_LUT4_O_I2 I3=L3_LUT4_I3_8_I2_LUT4_O_I3 O=L3_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3 I2=R3_LUT4_I3_36_O_LUT4_I2_1_O I3=L3_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1 I2=L3_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_37_O_LUT4_I2_O O=L3_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_O I1=L3_LUT4_I3_21_I0_LUT4_O_I2_LUT4_O_I2 I2=L3_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_36_O_LUT4_I2_2_O O=L3_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_41_O I1=R3_LUT4_I3_40_O I2=R3_LUT4_I3_39_O I3=R3_LUT4_I3_38_O O=L3_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R3_LUT4_I3_36_O_LUT4_I2_2_O I1=L3_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 I3=R3_LUT4_I3_37_O_LUT4_I2_O O=L3_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_41_O I1=R3_LUT4_I3_40_O I2=R3_LUT4_I3_38_O I3=R3_LUT4_I3_39_O O=L3_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L3_LUT4_I3_9_I0 I1=L3_LUT4_I3_I0 I2=L3_LUT4_I3_9_I2 I3=L3(28) O=R4_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_14_I2 I2=L3_LUT4_I3_I2_LUT4_O_I2 I3=L3_LUT4_I3_9_I0_LUT4_O_I3 O=L3_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_I2_LUT4_O_I1 O=L3_LUT4_I3_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I3 I3=R3_LUT4_I3_22_O_LUT4_I2_2_O O=L3_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_21_O I1=R3_LUT4_I3_18_O I2=R3_LUT4_I3_19_O I3=R3_LUT4_I3_20_O O=L3_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R3_LUT4_I3_22_O_LUT4_I2_O I1=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 O=L3_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_9_I2_LUT4_O_I1 I2=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L3_LUT4_I3_I0_LUT4_O_I2 O=L3_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_23_O_LUT4_I2_O O=L3_LUT4_I3_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_22_O_LUT4_I2_O O=L3_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L3_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=R3_LUT4_I3_22_O_LUT4_I2_2_O I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_19_O I1=R3_LUT4_I3_20_O I2=R3_LUT4_I3_21_O I3=R3_LUT4_I3_18_O O=L3_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I1=L3_LUT4_I3_I0_LUT4_O_I1 I2=L3_LUT4_I3_I0_LUT4_O_I2 I3=L3_LUT4_I3_I0_LUT4_O_I3 O=L3_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_9_I2_LUT4_O_I1 O=L3_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=L3_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_22_O_LUT4_I2_O I1=L3_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=L3_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1 I3=R3_LUT4_I3_22_O_LUT4_I2_1_O O=L3_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R3_LUT4_I3_22_O_LUT4_I2_2_O I3=L3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=L3_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_22_O_LUT4_I2_2_O I1=L3_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_17_I2_LUT4_I3_I2_LUT4_O_I1 O=L3_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R3_LUT4_I3_22_O_LUT4_I2_O I3=L3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L3_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I1=L3_LUT4_I3_I1_LUT4_O_I1 I2=L3_LUT4_I3_I0_LUT4_O_I1 I3=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L3_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=L3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L3_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_O I3=L3_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_20_O I1=R3_LUT4_I3_19_O I2=R3_LUT4_I3_18_O I3=R3_LUT4_I3_21_O O=L3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_22_O_LUT4_I2_2_O I1=L3_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I1 O=L3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L3_LUT4_I3_I2_LUT4_O_I0 I1=L3_LUT4_I3_I2_LUT4_O_I1 I2=L3_LUT4_I3_I2_LUT4_O_I2 I3=L3_LUT4_I3_I2_LUT4_O_I3 O=L3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I1=L3_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=R3_LUT4_I3_23_O I3=R3_LUT4_I3_22_O O=L3_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R3_LUT4_I3_21_O I1=R3_LUT4_I3_19_O I2=R3_LUT4_I3_20_O I3=R3_LUT4_I3_18_O O=L3_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R3_LUT4_I3_22_O_LUT4_I2_2_O O=L3_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I3 I3=R3_LUT4_I3_22_O_LUT4_I2_O O=L3_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_21_O I1=R3_LUT4_I3_20_O I2=R3_LUT4_I3_19_O I3=R3_LUT4_I3_18_O O=L3_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L3_LUT4_I3_14_I2_LUT4_O_I3 I1=R3_LUT4_I3_22_O_LUT4_I2_O I2=L3_LUT4_I3_17_I0_LUT4_O_I1 I3=L3_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=L3_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L3_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=L3_LUT4_I3_17_I2_LUT4_I3_I1_LUT4_O_I1 I3=R3_LUT4_I3_22_O_LUT4_I2_2_O O=L3_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_18_O I1=R3_LUT4_I3_20_O I2=R3_LUT4_I3_19_O I3=R3_LUT4_I3_21_O O=L3_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R3_LUT4_I3_22_O_LUT4_I2_2_O O=L3_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_21_O I1=R3_LUT4_I3_19_O I2=R3_LUT4_I3_18_O I3=R3_LUT4_I3_20_O O=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R3_LUT4_I3_22_O_LUT4_I2_O I1=L3_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_1_O I3=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 O=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1 I2=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=L3_LUT4_I3_14_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R3_LUT4_I3_23_O_LUT4_I2_O I1=L3_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 I2=R3_LUT4_I3_22_O_LUT4_I2_2_O I3=L3_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R3_LUT4_I3_21_O I1=R3_LUT4_I3_20_O I2=R3_LUT4_I3_19_O I3=R3_LUT4_I3_18_O O=L3_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=L3(1) D=R2(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(2) D=R2(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(11) D=R2(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(12) D=R2(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(13) D=R2(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(14) D=R2(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(15) D=R2(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(16) D=R2(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(17) D=R2(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(18) D=R2(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(19) D=R2(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(20) D=R2(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(3) D=R2(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(21) D=R2(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(22) D=R2(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(23) D=R2(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(24) D=R2(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(25) D=R2(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(26) D=R2(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(27) D=R2(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(28) D=R2(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(29) D=R2(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(30) D=R2(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(4) D=R2(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(31) D=R2(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(32) D=R2(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(5) D=R2(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(6) D=R2(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(7) D=R2(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(8) D=R2(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(9) D=R2(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L3(10) D=R2(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:131.1-132.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L4(2) I2=L4_LUT4_I1_I2 I3=L4_LUT4_I1_I3 O=R5_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L4(10) I2=L4_LUT4_I1_1_I2 I3=L4_LUT4_I1_1_I3 O=R5_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I1_O_LUT4_I1_O I1=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L4_LUT4_I1_1_I2_LUT4_O_I2 I3=L4_LUT4_I1_1_I2_LUT4_O_I3 O=L4_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I1_O_LUT4_I1_O I1=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L4_LUT4_I1_1_I2_LUT4_O_I2 I3=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3 O=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I0 I2=R4_LUT4_I3_6_O_LUT4_I2_1_O I3=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I1 I3=R4_LUT4_I3_7_O_LUT4_I2_O O=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_17_I2_LUT4_O_I2 I3=R4_LUT4_I3_6_O_LUT4_I2_O O=L4_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_6_O_LUT4_I2_1_O O=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_7_O_LUT4_I2_O I1=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_6_O_LUT4_I2_2_O I3=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_10_O I1=R4_LUT4_I3_11_O I2=R4_LUT4_I3_9_O I3=R4_LUT4_I3_8_O O=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_6_O_LUT4_I2_1_O I3=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_9_O I1=R4_LUT4_I3_10_O I2=R4_LUT4_I3_11_O I3=R4_LUT4_I3_8_O O=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_10_O I1=R4_LUT4_I3_9_O I2=R4_LUT4_I3_8_O I3=R4_LUT4_I3_11_O O=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_7_O_LUT4_I2_O I1=L4_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I2=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I3=R4_LUT4_I3_6_O_LUT4_I2_2_O O=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O I1=L4_LUT4_I1_1_I3_LUT4_O_I1 I2=L4_LUT4_I1_1_I3_LUT4_O_I2 I3=L4_LUT4_I1_1_I3_LUT4_O_I3 O=L4_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I1=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_7_O I3=R4_LUT4_I3_6_O O=L4_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R4_LUT4_I3_11_O I1=R4_LUT4_I3_10_O I2=R4_LUT4_I3_9_O I3=R4_LUT4_I3_8_O O=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_11_O I1=R4_LUT4_I3_10_O I2=R4_LUT4_I3_9_O I3=R4_LUT4_I3_8_O O=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I1_3_I2_LUT4_O_I2 I1=L4_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_13_I1_LUT4_O_I2 I3=L4_LUT4_I1_1_I2_LUT4_O_I3 O=L4_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_17_I2_LUT4_O_I2 I3=R4_LUT4_I3_6_O_LUT4_I2_1_O O=L4_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_6_O_LUT4_I2_2_O I3=L4_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I2=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=R4_LUT4_I3_7_O_LUT4_I2_O O=L4_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I1=L4_LUT4_I3_17_I1_LUT4_O_I3 I2=L4_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I1_3_I3_LUT4_O_I0 O=L4_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I2=L4_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_7_O_LUT4_I2_O O=L4_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4(12) I2=L4_LUT4_I1_2_I2 I3=L4_LUT4_I1_2_I3 O=R5_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_5_I1 I2=L4_LUT4_I3_5_I0_LUT4_O_I3 I3=L4_LUT4_I3_3_I1 O=L4_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L4_LUT4_I1_2_I3_LUT4_O_I0 I1=L4_LUT4_I3_3_I2 I2=L4_LUT4_I3_6_I0_LUT4_O_I3 I3=L4_LUT4_I1_2_I3_LUT4_O_I3 O=L4_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_6_I2_LUT4_O_I1 I2=L4_LUT4_I3_5_I2_LUT4_O_I3 I3=L4_LUT4_I3_5_I2_LUT4_O_I2 O=L4_LUT4_I1_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=L4(1) I2=L4_LUT4_I1_3_I2 I3=L4_LUT4_I1_3_I3 O=R5_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I1_O_LUT4_I1_O I2=L4_LUT4_I1_3_I2_LUT4_O_I2 I3=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O O=L4_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_17_I2_LUT4_O_I2 I3=R4_LUT4_I3_7_O_LUT4_I2_O O=L4_LUT4_I1_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_6_O_LUT4_I2_O O=L4_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_2_O I1=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_6_O_LUT4_I2_1_O I3=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 O=L4_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_11_O I1=R4_LUT4_I3_9_O I2=R4_LUT4_I3_10_O I3=R4_LUT4_I3_8_O O=L4_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I1_3_I3_LUT4_O_I0 I1=L4_LUT4_I1_3_I3_LUT4_O_I1 I2=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I3=L4_LUT4_I3_17_I1 O=L4_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2 I3=L4_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3 O=L4_LUT4_I1_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_7_O_LUT4_I2_O I1=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_6_O_LUT4_I2_1_O I3=L4_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_10_O I1=R4_LUT4_I3_8_O I2=R4_LUT4_I3_9_O I3=R4_LUT4_I3_11_O O=L4_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_6_O_LUT4_I2_2_O I3=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I1 O=L4_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I1_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_7_O_LUT4_I2_O I1=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_6_O_LUT4_I2_2_O O=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_11_O I1=R4_LUT4_I3_9_O I2=R4_LUT4_I3_8_O I3=R4_LUT4_I3_10_O O=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I1 I3=R4_LUT4_I3_6_O_LUT4_I2_1_O O=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_9_O I1=R4_LUT4_I3_8_O I2=R4_LUT4_I3_11_O I3=R4_LUT4_I3_10_O O=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L4(3) I2=L4_LUT4_I1_4_I2 I3=L4_LUT4_I1_4_I3 O=R5_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_4_I2_LUT4_O_I1 I2=L4_LUT4_I1_5_I2_LUT4_O_I3 I3=L4_LUT4_I1_4_I2_LUT4_O_I3 O=L4_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_5_O_LUT4_I2_O I1=L4_LUT4_I3_10_I0_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=L4_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I2 I2=R4_LUT4_I3_4_O_LUT4_I2_O I3=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_5_O_LUT4_I2_O O=L4_LUT4_I1_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_10_I2_LUT4_O_I1 I3=R4_LUT4_I3_4_O_LUT4_I2_O O=L4_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_1_O I1=R4_LUT4_I3_2_O I2=R4_LUT4_I3_3_O I3=R4_LUT4_I3_O O=L4_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L4_LUT4_I2_I3_LUT4_O_I2 I1=L4_LUT4_I1_5_I3_LUT4_O_I1 I2=L4_LUT4_I3_10_I2 I3=L4_LUT4_I1_4_I3_LUT4_O_I3 O=L4_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I0 I1=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I3_10_I2_LUT4_O_I1 I2=R4_LUT4_I3_5_O_LUT4_I2_O I3=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_3_O I1=R4_LUT4_I3_2_O I2=R4_LUT4_I3_1_O I3=R4_LUT4_I3_O O=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=R4_LUT4_I3_4_O_LUT4_I2_2_O I2=R4_LUT4_I3_4_O_LUT4_I2_O I3=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_5_O_LUT4_I2_O I1=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_4_O_LUT4_I2_O I3=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_3_O I1=R4_LUT4_I3_O I2=R4_LUT4_I3_1_O I3=R4_LUT4_I3_2_O O=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L4(25) I2=L4_LUT4_I1_5_I2 I3=L4_LUT4_I1_5_I3 O=R5_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_10_I0 I2=L4_LUT4_I1_5_I2_LUT4_O_I2 I3=L4_LUT4_I1_5_I2_LUT4_O_I3 O=L4_LUT4_I1_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_3_O I1=R4_LUT4_I3_1_O I2=R4_LUT4_I3_O I3=R4_LUT4_I3_2_O O=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=R4_LUT4_I3_4_O_LUT4_I2_O I2=R4_LUT4_I3_5_O_LUT4_I2_O I3=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_1_O I1=R4_LUT4_I3_O I2=R4_LUT4_I3_3_O I3=R4_LUT4_I3_2_O O=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_10_I0_LUT4_O_I2 I1=L4_LUT4_I3_10_I0_LUT4_O_I1 I2=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R4_LUT4_I3_5_O_LUT4_I2_O I1=L4_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I2 I2=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_4_O_LUT4_I2_O O=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_2_O I1=R4_LUT4_I3_1_O I2=R4_LUT4_I3_3_O I3=R4_LUT4_I3_O O=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_2_O I1=R4_LUT4_I3_3_O I2=R4_LUT4_I3_1_O I3=R4_LUT4_I3_O O=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_3_O I1=R4_LUT4_I3_2_O I2=R4_LUT4_I3_1_O I3=R4_LUT4_I3_O O=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_5_I3_LUT4_O_I1 I2=L4_LUT4_I1_5_I3_LUT4_O_I2 I3=L4_LUT4_I2_I3_LUT4_O_I2 O=L4_LUT4_I1_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_10_I1_LUT4_O_I2 O=L4_LUT4_I1_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_4_O_LUT4_I2_O I3=L4_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I2 O=L4_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_5_O_LUT4_I2_O I1=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_2_O I1=R4_LUT4_I3_1_O I2=R4_LUT4_I3_O I3=R4_LUT4_I3_3_O O=L4_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_4_O_LUT4_I2_O O=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_3_O I1=R4_LUT4_I3_2_O I2=R4_LUT4_I3_O I3=R4_LUT4_I3_1_O O=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_2_O I1=R4_LUT4_I3_O I2=R4_LUT4_I3_1_O I3=R4_LUT4_I3_3_O O=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_5_O_LUT4_I2_O I1=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_O I1=R4_LUT4_I3_2_O I2=R4_LUT4_I3_1_O I3=R4_LUT4_I3_3_O O=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_O I1=L4_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=R4_LUT4_I3_5_O_LUT4_I2_O I3=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4(30) I2=L4_LUT4_I1_6_I2 I3=L4_LUT4_I1_6_I3 O=R5_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_6_I2_LUT4_O_I2 I3=L4_LUT4_I3_16_I0 O=L4_LUT4_I1_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=R4_LUT4_I3_35_O_LUT4_I2_O I1=R4_LUT4_I3_34_O_LUT4_I2_1_O I2=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2 I1=R4_LUT4_I3_35_O_LUT4_I2_O I2=L4_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_34_O_LUT4_I2_2_O O=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_30_O I1=R4_LUT4_I3_32_O I2=R4_LUT4_I3_31_O I3=R4_LUT4_I3_33_O O=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_1_O I1=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_35_O_LUT4_I2_O I3=L4_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_33_O I1=R4_LUT4_I3_32_O I2=R4_LUT4_I3_30_O I3=R4_LUT4_I3_31_O O=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_6_I3_LUT4_O_I1 I2=L4_LUT4_I1_6_I3_LUT4_O_I2 I3=L4_LUT4_I1_6_I3_LUT4_O_I3 O=L4_LUT4_I1_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I0 I1=L4_LUT4_I3_2_I2_LUT4_O_I2 I2=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I1_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_1_O I1=L4_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_34_O_LUT4_I2_O I3=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_1_O I1=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_34_O_LUT4_I2_O I3=L4_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_35_O_LUT4_I2_O I1=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I0 I2=L4_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_34_O_LUT4_I2_2_O O=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_34_O_LUT4_I2_1_O O=L4_LUT4_I1_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I0 I3=R4_LUT4_I3_34_O_LUT4_I2_2_O O=L4_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_31_O I1=R4_LUT4_I3_32_O I2=R4_LUT4_I3_33_O I3=R4_LUT4_I3_30_O O=L4_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L4_LUT4_I3_2_I0_LUT4_O_I2 I1=L4_LUT4_I3_2_I0_LUT4_O_I0 I2=L4_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=L4_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2 I1=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I0 I2=R4_LUT4_I3_35_O I3=R4_LUT4_I3_34_O O=L4_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=L4_LUT4_I1_I2_LUT4_O_I0 I1=L4_LUT4_I1_I2_LUT4_O_I1 I2=R4_LUT4_I3_22_O I3=R4_LUT4_I3_23_O O=L4_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R4_LUT4_I3_21_O I1=R4_LUT4_I3_20_O I2=R4_LUT4_I3_19_O I3=R4_LUT4_I3_18_O O=L4_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R4_LUT4_I3_19_O I1=R4_LUT4_I3_18_O I2=R4_LUT4_I3_21_O I3=R4_LUT4_I3_20_O O=L4_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I1_I3_LUT4_O_I0 I1=L4_LUT4_I1_I3_LUT4_O_I1 I2=L4_LUT4_I1_I3_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I3 O=L4_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I2=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I0 I2=R4_LUT4_I3_23_O_LUT4_I2_O I3=L4_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_1_O I1=L4_LUT4_I3_9_I2_LUT4_I1_I3_LUT4_O_I1 I2=R4_LUT4_I3_22_O_LUT4_I2_O I3=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_1_O I1=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_9_I2_LUT4_I1_I3_LUT4_O_I1 I3=R4_LUT4_I3_22_O_LUT4_I2_O O=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_23_O_LUT4_I2_O I3=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=R4_LUT4_I3_22_O_LUT4_I2_2_O I2=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R4_LUT4_I3_21_O I1=R4_LUT4_I3_20_O I2=R4_LUT4_I3_18_O I3=R4_LUT4_I3_19_O O=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_20_O I1=R4_LUT4_I3_21_O I2=R4_LUT4_I3_19_O I3=R4_LUT4_I3_18_O O=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L4_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I0 I1=R4_LUT4_I3_23_O_LUT4_I2_O I2=R4_LUT4_I3_22_O_LUT4_I2_1_O I3=L4_LUT4_I1_I2_LUT4_O_I1 O=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_1_O I1=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 I3=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R4_LUT4_I3_18_O I1=R4_LUT4_I3_20_O I2=R4_LUT4_I3_19_O I3=R4_LUT4_I3_21_O O=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_9_I2_LUT4_I1_I3_LUT4_O_I1 I3=R4_LUT4_I3_22_O_LUT4_I2_2_O O=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 I1=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=R4_LUT4_I3_22_O_LUT4_I2_O I3=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_21_O I1=R4_LUT4_I3_20_O I2=R4_LUT4_I3_19_O I3=R4_LUT4_I3_18_O O=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_1_O I1=L4_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_23_O_LUT4_I2_O I3=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3 I2=L4_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I0 I3=R4_LUT4_I3_22_O_LUT4_I2_1_O O=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I1=L4_LUT4_I3_9_I1_LUT4_O_I1 I2=L4_LUT4_I3_9_I2_LUT4_I1_I0 I3=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_22_O_LUT4_I2_1_O O=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_20_O I1=R4_LUT4_I3_19_O I2=R4_LUT4_I3_18_O I3=R4_LUT4_I3_21_O O=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_23_O_LUT4_I2_O I1=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R4_LUT4_I3_22_O_LUT4_I2_O I3=L4_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_21_O I1=R4_LUT4_I3_20_O I2=R4_LUT4_I3_19_O I3=R4_LUT4_I3_18_O O=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4(8) I3=L4_LUT4_I2_I3 O=R5_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4(15) I3=L4_LUT4_I2_1_I3 O=R5_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L4_LUT4_I2_1_I3_LUT4_O_I0 I1=L4_LUT4_I3_4_I0_LUT4_I0_O I2=L4_LUT4_I2_1_I3_LUT4_O_I2 I3=L4_LUT4_I2_1_I3_LUT4_O_I3 O=L4_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L4_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3 O=L4_LUT4_I2_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_1_O I1=L4_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_O I3=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L4_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_17_O_LUT4_I2_O I1=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_4_I0_LUT4_O_I3 I3=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O O=L4_LUT4_I2_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4(17) I3=L4_LUT4_I2_2_I3 O=R5_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I2_2_I3_LUT4_O_I1 I2=L4_LUT4_I2_2_I3_LUT4_O_I2 I3=L4_LUT4_I3_7_I1_LUT4_O_I0 O=L4_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I2 I1=R4_LUT4_I3_41_O_LUT4_I2_O I2=L4_LUT4_I3_7_I2_LUT4_O_I1 I3=L4_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I2_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_40_O_LUT4_I2_O O=L4_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_19_I2_LUT4_I1_I2 I3=L4_LUT4_I3_19_I1_LUT4_O_I3 O=L4_LUT4_I2_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4(18) I3=L4_LUT4_I2_3_I3 O=R5_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L4_LUT4_I2_3_I3_LUT4_O_I0 I1=L4_LUT4_I3_9_I1 I2=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L4_LUT4_I2_3_I3_LUT4_O_I3 O=L4_LUT4_I2_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_9_I2_LUT4_I1_I3 I2=L4_LUT4_I3_9_I2_LUT4_I1_I2 I3=L4_LUT4_I3_9_I2_LUT4_I1_I0 O=L4_LUT4_I2_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3 I3=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I2_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4(28) I3=L4_LUT4_I2_4_I3 O=R5_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L4_LUT4_I2_4_I3_LUT4_O_I0 I1=L4_LUT4_I2_4_I3_LUT4_O_I1 I2=L4_LUT4_I2_4_I3_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I1 O=L4_LUT4_I2_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I2_4_I3_LUT4_O_I0_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I2_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I2_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I2_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I2_4_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_1_O I1=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_22_O_LUT4_I2_O I3=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I2_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I1_I2_LUT4_O_I0 I2=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=R4_LUT4_I3_23_O_LUT4_I2_O O=L4_LUT4_I2_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_9_I1_LUT4_O_I1 I3=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L4_LUT4_I2_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L4_LUT4_I2_I3_LUT4_O_I0 I1=L4_LUT4_I3_10_I2 I2=L4_LUT4_I2_I3_LUT4_O_I2 I3=L4_LUT4_I2_I3_LUT4_O_I3 O=L4_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=L4_LUT4_I3_10_I1_LUT4_O_I1 I1=L4_LUT4_I1_4_I3_LUT4_O_I3 I2=L4_LUT4_I1_5_I3_LUT4_O_I2 I3=L4_LUT4_I3_10_I1_LUT4_O_I3 O=L4_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L4_LUT4_I3_10_I0_LUT4_O_I3 I1=L4_LUT4_I1_4_I2_LUT4_O_I3 I2=L4_LUT4_I1_5_I2_LUT4_O_I2 I3=L4_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_2_O I1=L4_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2 I2=L4_LUT4_I3_10_I0_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=L4_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_5_O_LUT4_I2_O O=L4_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_4_I2_LUT4_O_I1 I2=L4_LUT4_I1_5_I2_LUT4_O_I2 I3=L4_LUT4_I1_4_I2_LUT4_O_I3 O=L4_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L4_LUT4_I3_I0 I1=L4_LUT4_I3_I1 I2=L4_LUT4_I3_I2 I3=L4(4) O=R5_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L4_LUT4_I3_1_I0 I1=L4_LUT4_I3_1_I1 I2=L4_LUT4_I3_1_I2 I3=L4(5) O=R5_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L4_LUT4_I3_10_I0 I1=L4_LUT4_I3_10_I1 I2=L4_LUT4_I3_10_I2 I3=L4(14) O=R5_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_10_I0_LUT4_O_I1 I2=L4_LUT4_I3_10_I0_LUT4_O_I2 I3=L4_LUT4_I3_10_I0_LUT4_O_I3 O=L4_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2 I2=L4_LUT4_I3_10_I0_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_4_O_LUT4_I2_O O=L4_LUT4_I3_10_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_3_O I1=R4_LUT4_I3_2_O I2=R4_LUT4_I3_1_O I3=R4_LUT4_I3_O O=L4_LUT4_I3_10_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_5_O_LUT4_I2_O I1=L4_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I3_10_I2_LUT4_O_I1 O=L4_LUT4_I3_10_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_3_O I1=R4_LUT4_I3_1_O I2=R4_LUT4_I3_2_O I3=R4_LUT4_I3_O O=L4_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_2_O I1=L4_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2 I2=L4_LUT4_I1_5_I2_LUT4_O_I3 I3=L4_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_10_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_5_O_LUT4_I2_O O=L4_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R4_LUT4_I3_4_O_LUT4_I2_O O=L4_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_10_I1_LUT4_O_I1 I2=L4_LUT4_I3_10_I1_LUT4_O_I2 I3=L4_LUT4_I3_10_I1_LUT4_O_I3 O=L4_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_10_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R4_LUT4_I3_4_O_LUT4_I2_O I3=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=R4_LUT4_I3_5_O_LUT4_I2_O I2=R4_LUT4_I3_4_O_LUT4_I2_2_O I3=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_10_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I3_10_I0_LUT4_O_I1_LUT4_O_I2 I2=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R4_LUT4_I3_4_O_LUT4_I2_2_O O=L4_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_5_O_LUT4_I2_O I1=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_4_O_LUT4_I2_O I3=L4_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I0 I3=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_5_O_LUT4_I2_O I1=L4_LUT4_I3_10_I2_LUT4_O_I1 I2=L4_LUT4_I1_4_I2_LUT4_O_I1 I3=L4_LUT4_I3_10_I2_LUT4_O_I3 O=L4_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R4_LUT4_I3_3_O I1=R4_LUT4_I3_2_O I2=R4_LUT4_I3_1_O I3=R4_LUT4_I3_O O=L4_LUT4_I3_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_4_O_LUT4_I2_2_O O=L4_LUT4_I3_10_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_4_O_LUT4_I2_1_O I1=L4_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_4_O_LUT4_I2_O I3=L4_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_3_O I1=R4_LUT4_I3_2_O I2=R4_LUT4_I3_1_O I3=R4_LUT4_I3_O O=L4_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L4_LUT4_I3_2_I1 I1=L4_LUT4_I1_6_I2 I2=L4_LUT4_I3_11_I2 I3=L4(16) O=R5_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_11_I2_LUT4_O_I2 I3=L4_LUT4_I1_6_I3_LUT4_O_I3 O=L4_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_2_O I1=R4_LUT4_I3_34_O_LUT4_I2_O I2=L4_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R4_LUT4_I3_35_O_LUT4_I2_O I1=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I0 I2=R4_LUT4_I3_34_O_LUT4_I2_O I3=L4_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 O=L4_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_33_O I1=R4_LUT4_I3_32_O I2=R4_LUT4_I3_31_O I3=R4_LUT4_I3_30_O O=L4_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_O I1=L4_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_34_O_LUT4_I2_2_O I3=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 O=L4_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_I0 I1=L4_LUT4_I3_12_I1 I2=L4_LUT4_I3_12_I2 I3=L4(19) O=R5_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_12_I1_LUT4_O_I1 I2=L4_LUT4_I3_12_I1_LUT4_O_I2 I3=L4_LUT4_I3_I0_LUT4_O_I3 O=L4_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_8_I0_LUT4_O_I0 I3=R4_LUT4_I3_28_O_LUT4_I2_O O=L4_LUT4_I3_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 I3=R4_LUT4_I3_28_O_LUT4_I2_1_O O=L4_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_28_O_LUT4_I2_2_O I3=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_1_O I1=L4_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 I2=R4_LUT4_I3_29_O_LUT4_I2_O I3=L4_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_I2_LUT4_O_I0 I1=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O I2=L4_LUT4_I3_12_I2_LUT4_O_I2 I3=L4_LUT4_I3_8_I1_LUT4_O_I2 O=L4_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 I2=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_28_O_LUT4_I2_1_O O=L4_LUT4_I3_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_13_I0 I1=L4_LUT4_I3_13_I1 I2=L4_LUT4_I3_13_I2 I3=L4(20) O=R5_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O O=L4_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_13_I1_LUT4_O_I2 I3=L4_LUT4_I1_3_I2_LUT4_O_I2 O=L4_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_13_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_6_O_LUT4_I2_2_O I3=L4_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_2_O I1=L4_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_6_O_LUT4_I2_1_O I3=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_6_O_LUT4_I2_O O=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I2=R4_LUT4_I3_7_O_LUT4_I2_O I3=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I0 O=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_10_O I1=R4_LUT4_I3_9_O I2=R4_LUT4_I3_11_O I3=R4_LUT4_I3_8_O O=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_7_O_LUT4_I2_O I1=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_6_O_LUT4_I2_1_O I3=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I1_3_I3_LUT4_O_I1 I2=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I3=L4_LUT4_I3_17_I2 O=L4_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L4_LUT4_I3_14_I0 I1=L4_LUT4_I3_14_I1 I2=L4_LUT4_I3_14_I2 I3=L4(21) O=R5_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_1_I0_LUT4_O_I1 I2=L4_LUT4_I2_1_I3_LUT4_O_I0 I3=L4_LUT4_I3_4_I0_LUT4_I0_O O=L4_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_4_I0_LUT4_O_I2 I2=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O I3=L4_LUT4_I3_4_I0_LUT4_I0_O O=L4_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_4_I2_LUT4_O_I2 I2=L4_LUT4_I3_14_I2_LUT4_O_I2 I3=L4_LUT4_I3_14_I2_LUT4_O_I3 O=L4_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I2 I3=R4_LUT4_I3_16_O_LUT4_I2_O O=L4_LUT4_I3_14_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_16_O_LUT4_I2_1_O O=L4_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_O I3=L4_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3 I3=R4_LUT4_I3_16_O_LUT4_I2_1_O O=L4_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L4_LUT4_I3_15_I0 I1=L4_LUT4_I3_15_I1 I2=L4_LUT4_I3_15_I2 I3=L4(23) O=R5_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L4_LUT4_I3_19_I1 I1=L4_LUT4_I3_7_I0_LUT4_O_I2 I2=L4_LUT4_I3_7_I0_LUT4_O_I3 I3=L4_LUT4_I3_15_I0_LUT4_O_I3 O=L4_LUT4_I3_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_15_I0_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_40_O_LUT4_I2_O O=L4_LUT4_I3_15_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_15_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_40_O_LUT4_I2_2_O I3=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I2 O=L4_LUT4_I3_15_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R4_LUT4_I3_41_O_LUT4_I2_O I3=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_15_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_7_I1_LUT4_O_I3 I2=L4_LUT4_I3_7_I1_LUT4_O_I2 I3=L4_LUT4_I3_7_I1_LUT4_O_I1 O=L4_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_7_I2_LUT4_O_I1 I3=L4_LUT4_I3_15_I2_LUT4_O_I3 O=L4_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_15_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_40_O_LUT4_I2_2_O O=L4_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_41_O_LUT4_I2_O O=L4_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_16_I0 I1=L4_LUT4_I3_16_I1 I2=L4_LUT4_I3_16_I2 I3=L4(24) O=R5_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_16_I0_LUT4_O_I2 I3=L4_LUT4_I3_16_I0_LUT4_O_I3 O=L4_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=R4_LUT4_I3_35_O_LUT4_I2_O I1=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_34_O_LUT4_I2_2_O I3=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I0 O=L4_LUT4_I3_16_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I0 I1=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_34_O_LUT4_I2_1_O O=L4_LUT4_I3_16_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=R4_LUT4_I3_32_O I1=R4_LUT4_I3_33_O I2=R4_LUT4_I3_31_O I3=R4_LUT4_I3_30_O O=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_32_O I1=R4_LUT4_I3_30_O I2=R4_LUT4_I3_31_O I3=R4_LUT4_I3_33_O O=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_35_O_LUT4_I2_O O=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_16_I1_LUT4_O_I1 I2=L4_LUT4_I3_2_I0_LUT4_O_I0 I3=L4_LUT4_I3_16_I1_LUT4_O_I3 O=L4_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_34_O_LUT4_I2_2_O O=L4_LUT4_I3_16_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_2_O I1=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 I3=R4_LUT4_I3_34_O_LUT4_I2_O O=L4_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=R4_LUT4_I3_32_O I1=R4_LUT4_I3_31_O I2=R4_LUT4_I3_33_O I3=R4_LUT4_I3_30_O O=L4_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_11_I2_LUT4_O_I2 I2=L4_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I0 I3=L4_LUT4_I1_6_I3_LUT4_O_I2 O=L4_LUT4_I3_16_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_16_I2_LUT4_O_I1 I2=L4_LUT4_I3_16_I2_LUT4_O_I2 I3=R4_LUT4_I3_34_O_LUT4_I2_2_O O=L4_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_35_O_LUT4_I2_O O=L4_LUT4_I3_16_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_1_O I1=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_34_O_LUT4_I2_O I3=L4_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_33_O I1=R4_LUT4_I3_32_O I2=R4_LUT4_I3_31_O I3=R4_LUT4_I3_30_O O=L4_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_35_O_LUT4_I2_O I1=L4_LUT4_I3_16_I2_LUT4_O_I2 I2=R4_LUT4_I3_34_O_LUT4_I2_2_O I3=L4_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2 O=L4_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_33_O I1=R4_LUT4_I3_32_O I2=R4_LUT4_I3_31_O I3=R4_LUT4_I3_30_O O=L4_LUT4_I3_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I3_17_I0 I1=L4_LUT4_I3_17_I1 I2=L4_LUT4_I3_17_I2 I3=L4(26) O=R5_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O I1=L4_LUT4_I1_1_I3_LUT4_O_I2 I2=L4_LUT4_I3_13_I1 I3=L4_LUT4_I3_17_I0_LUT4_O_I3 O=L4_LUT4_I3_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I1_O_LUT4_I1_O O=L4_LUT4_I3_17_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L4_LUT4_I3_17_I1_LUT4_O_I0 I1=L4_LUT4_I3_17_I1_LUT4_O_I1 I2=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I3=L4_LUT4_I3_17_I1_LUT4_O_I3 O=L4_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I0 I1=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I1 I2=R4_LUT4_I3_7_O I3=R4_LUT4_I3_6_O O=L4_LUT4_I3_17_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R4_LUT4_I3_11_O I1=R4_LUT4_I3_10_O I2=R4_LUT4_I3_9_O I3=R4_LUT4_I3_8_O O=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_11_O I1=R4_LUT4_I3_10_O I2=R4_LUT4_I3_8_O I3=R4_LUT4_I3_9_O O=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_7_O_LUT4_I2_O I1=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_6_O_LUT4_I2_2_O I3=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_17_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1 I1=R4_LUT4_I3_6_O_LUT4_I2_2_O I2=R4_LUT4_I3_6_O_LUT4_I2_1_O I3=L4_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I2=L4_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=R4_LUT4_I3_7_O_LUT4_I2_O O=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I1_O I2=R4_LUT4_I3_6_O_LUT4_I2_O I3=L4_LUT4_I3_17_I1_LUT4_O_I0_LUT4_O_I0 O=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_11_O I1=R4_LUT4_I3_10_O I2=R4_LUT4_I3_9_O I3=R4_LUT4_I3_8_O O=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R4_LUT4_I3_7_O_LUT4_I2_O I1=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3 I2=R4_LUT4_I3_6_O_LUT4_I2_1_O I3=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1 O=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I3_I2 I3=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O O=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_6_O_LUT4_I2_2_O I3=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_8_O I1=R4_LUT4_I3_10_O I2=R4_LUT4_I3_9_O I3=R4_LUT4_I3_11_O O=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_17_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I3 I2=L4_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_6_O_LUT4_I2_2_O O=L4_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_7_O_LUT4_I2_O I1=L4_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_6_O_LUT4_I2_1_O I3=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_17_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_17_I2_LUT4_O_I1 I2=L4_LUT4_I3_17_I2_LUT4_O_I2 I3=R4_LUT4_I3_6_O_LUT4_I2_2_O O=L4_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_6_O_LUT4_I2_1_O O=L4_LUT4_I3_17_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_6_O_LUT4_I2_O I1=L4_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I3=R4_LUT4_I3_7_O_LUT4_I2_O O=L4_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_11_O I1=R4_LUT4_I3_8_O I2=R4_LUT4_I3_9_O I3=R4_LUT4_I3_10_O O=L4_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_11_O I1=R4_LUT4_I3_10_O I2=R4_LUT4_I3_9_O I3=R4_LUT4_I3_8_O O=L4_LUT4_I3_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I3_I0 I1=L4_LUT4_I3_18_I1 I2=L4_LUT4_I3_18_I2 I3=L4(29) O=R5_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L4_LUT4_I3_8_I1 I1=L4_LUT4_I3_18_I1_LUT4_O_I1 I2=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O I3=L4_LUT4_I3_18_I1_LUT4_O_I3 O=L4_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_28_O_LUT4_I2_1_O O=L4_LUT4_I3_18_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I0 I1=L4_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_28_O I3=R4_LUT4_I3_29_O O=L4_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=L4_LUT4_I3_I2_LUT4_O_I2 I1=L4_LUT4_I3_8_I2_LUT4_O_I2 I2=L4_LUT4_I3_I2_LUT4_O_I1 I3=L4_LUT4_I3_8_I2_LUT4_O_I3 O=L4_LUT4_I3_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_8_I0_LUT4_O_I2 I3=L4_LUT4_I3_12_I1_LUT4_O_I1 O=L4_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L4_LUT4_I3_19_I0 I1=L4_LUT4_I3_19_I1 I2=L4_LUT4_I3_19_I2 I3=L4(31) O=R5_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_7_I2_LUT4_O_I3 I2=L4_LUT4_I3_19_I0_LUT4_O_I2 I3=L4_LUT4_I3_7_I1_LUT4_O_I1 O=L4_LUT4_I3_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_19_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I3 I2=L4_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 I3=R4_LUT4_I3_40_O_LUT4_I2_2_O O=L4_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_41_O_LUT4_I2_O I3=L4_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_39_O I1=R4_LUT4_I3_38_O I2=R4_LUT4_I3_37_O I3=R4_LUT4_I3_36_O O=L4_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_19_I1_LUT4_O_I1 I2=L4_LUT4_I3_19_I1_LUT4_O_I2 I3=L4_LUT4_I3_19_I1_LUT4_O_I3 O=L4_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_40_O_LUT4_I2_1_O O=L4_LUT4_I3_19_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_41_O_LUT4_I2_O I1=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_40_O_LUT4_I2_2_O O=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_39_O I1=R4_LUT4_I3_38_O I2=R4_LUT4_I3_36_O I3=R4_LUT4_I3_37_O O=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_38_O I1=R4_LUT4_I3_37_O I2=R4_LUT4_I3_39_O I3=R4_LUT4_I3_36_O O=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_41_O_LUT4_I2_O I1=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_40_O_LUT4_I2_2_O I3=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_19_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_38_O I1=R4_LUT4_I3_36_O I2=R4_LUT4_I3_37_O I3=R4_LUT4_I3_39_O O=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_38_O I1=R4_LUT4_I3_39_O I2=R4_LUT4_I3_37_O I3=R4_LUT4_I3_36_O O=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I2 I1=R4_LUT4_I3_40_O_LUT4_I2_1_O I2=L4_LUT4_I3_7_I0_LUT4_O_I2 I3=L4_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_19_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_40_O_LUT4_I2_2_O O=L4_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R4_LUT4_I3_41_O_LUT4_I2_O I3=L4_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_19_I2 I2=L4_LUT4_I3_19_I2_LUT4_I1_I2 I3=L4_LUT4_I3_15_I0_LUT4_O_I3 O=L4_LUT4_I3_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_19_I2_LUT4_O_I2 I3=L4_LUT4_I3_19_I2_LUT4_O_I3 O=L4_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_41_O_LUT4_I2_O I3=L4_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_39_O I1=R4_LUT4_I3_37_O I2=R4_LUT4_I3_36_O I3=R4_LUT4_I3_38_O O=L4_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 I2=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_40_O_LUT4_I2_2_O O=L4_LUT4_I2_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_39_O I1=R4_LUT4_I3_38_O I2=R4_LUT4_I3_37_O I3=R4_LUT4_I3_36_O O=L4_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_40_O_LUT4_I2_2_O I3=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I1 O=L4_LUT4_I3_19_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_39_O I1=R4_LUT4_I3_38_O I2=R4_LUT4_I3_37_O I3=R4_LUT4_I3_36_O O=L4_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I2_1_I3_LUT4_O_I0 I1=L4_LUT4_I3_1_I0_LUT4_O_I1 I2=L4_LUT4_I3_4_I0_LUT4_I0_O I3=L4_LUT4_I3_1_I0_LUT4_O_I3 O=L4_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_O I1=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 O=L4_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_1_O I1=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_17_O_LUT4_I2_O O=L4_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_15_O I1=R4_LUT4_I3_14_O I2=R4_LUT4_I3_13_O I3=R4_LUT4_I3_12_O O=L4_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L4_LUT4_I3_1_I1_LUT4_O_I0 I1=L4_LUT4_I3_1_I1_LUT4_O_I1 I2=L4_LUT4_I3_1_I1_LUT4_O_I2 I3=L4_LUT4_I3_1_I1_LUT4_O_I3 O=L4_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I1=L4_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R4_LUT4_I3_17_O I3=R4_LUT4_I3_16_O O=L4_LUT4_I3_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R4_LUT4_I3_14_O I1=R4_LUT4_I3_12_O I2=R4_LUT4_I3_13_O I3=R4_LUT4_I3_15_O O=L4_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_1_O I1=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3 I3=R4_LUT4_I3_16_O_LUT4_I2_O O=L4_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_1_I2_LUT4_O_I1 I1=R4_LUT4_I3_16_O_LUT4_I2_2_O I2=R4_LUT4_I3_17_O_LUT4_I2_O I3=L4_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_1_O I1=L4_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I2 I2=R4_LUT4_I3_16_O_LUT4_I2_O I3=L4_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_17_O_LUT4_I2_O I1=L4_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 I2=L4_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3 I3=R4_LUT4_I3_16_O_LUT4_I2_2_O O=L4_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_1_I2_LUT4_O_I1 I1=R4_LUT4_I3_17_O_LUT4_I2_O I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_15_O I1=R4_LUT4_I3_14_O I2=R4_LUT4_I3_13_O I3=R4_LUT4_I3_12_O O=L4_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_1_O I1=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_17_O_LUT4_I2_O I3=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_15_O I1=R4_LUT4_I3_13_O I2=R4_LUT4_I3_14_O I3=R4_LUT4_I3_12_O O=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_15_O I1=R4_LUT4_I3_13_O I2=R4_LUT4_I3_12_O I3=R4_LUT4_I3_14_O O=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L4_LUT4_I3_4_I2_LUT4_O_I0 I1=L4_LUT4_I3_1_I2 I2=L4_LUT4_I3_1_I1_LUT4_O_I2 I3=L4_LUT4_I3_14_I2_LUT4_O_I2 O=L4_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_1_O I1=L4_LUT4_I3_1_I2_LUT4_O_I1 I2=L4_LUT4_I3_1_I2_LUT4_O_I2 I3=L4_LUT4_I3_1_I2_LUT4_O_I3 O=L4_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R4_LUT4_I3_15_O I1=R4_LUT4_I3_12_O I2=R4_LUT4_I3_13_O I3=R4_LUT4_I3_14_O O=L4_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_4_I2_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L4_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 I1=R4_LUT4_I3_16_O_LUT4_I2_1_O I2=R4_LUT4_I3_16_O_LUT4_I2_O I3=L4_LUT4_I3_1_I2_LUT4_O_I1 O=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_15_O I1=R4_LUT4_I3_14_O I2=R4_LUT4_I3_13_O I3=R4_LUT4_I3_12_O O=L4_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R4_LUT4_I3_17_O_LUT4_I2_O I1=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_15_O I1=R4_LUT4_I3_14_O I2=R4_LUT4_I3_12_O I3=R4_LUT4_I3_13_O O=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_14_O I1=R4_LUT4_I3_15_O I2=R4_LUT4_I3_13_O I3=R4_LUT4_I3_12_O O=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L4_LUT4_I3_2_I0 I1=L4_LUT4_I3_2_I1 I2=L4_LUT4_I3_2_I2 I3=L4(6) O=R5_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=L4_LUT4_I3_2_I0_LUT4_O_I0 I1=L4_LUT4_I3_2_I0_LUT4_O_I1 I2=L4_LUT4_I3_2_I0_LUT4_O_I2 I3=L4_LUT4_I1_6_I3_LUT4_O_I2 O=L4_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1 I2=L4_LUT4_I3_16_I2_LUT4_O_I2 I3=R4_LUT4_I3_34_O_LUT4_I2_O O=L4_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_34_O_LUT4_I2_1_O O=L4_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_33_O I1=R4_LUT4_I3_32_O I2=R4_LUT4_I3_31_O I3=R4_LUT4_I3_30_O O=L4_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I0 I1=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_34_O_LUT4_I2_1_O I3=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R4_LUT4_I3_33_O I1=R4_LUT4_I3_32_O I2=R4_LUT4_I3_31_O I3=R4_LUT4_I3_30_O O=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_33_O I1=R4_LUT4_I3_31_O I2=R4_LUT4_I3_30_O I3=R4_LUT4_I3_32_O O=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_2_O I1=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_35_O_LUT4_I2_O I3=L4_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2 O=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_33_O I1=R4_LUT4_I3_31_O I2=R4_LUT4_I3_32_O I3=R4_LUT4_I3_30_O O=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I0 I1=R4_LUT4_I3_34_O_LUT4_I2_1_O I2=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=R4_LUT4_I3_31_O I1=R4_LUT4_I3_30_O I2=R4_LUT4_I3_33_O I3=R4_LUT4_I3_32_O O=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I0 I3=R4_LUT4_I3_35_O_LUT4_I2_O O=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_35_O_LUT4_I2_O I1=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 I2=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I0 I3=R4_LUT4_I3_34_O_LUT4_I2_2_O O=L4_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_32_O I1=R4_LUT4_I3_31_O I2=R4_LUT4_I3_30_O I3=R4_LUT4_I3_33_O O=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_16_I2 I2=L4_LUT4_I3_2_I1_LUT4_O_I2 I3=L4_LUT4_I3_2_I1_LUT4_O_I3 O=L4_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_16_I0_LUT4_O_I2 I2=L4_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_16_I0_LUT4_O_I3 O=L4_LUT4_I3_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_1_O I1=L4_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_34_O_LUT4_I2_O O=L4_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_33_O I1=R4_LUT4_I3_30_O I2=R4_LUT4_I3_31_O I3=R4_LUT4_I3_32_O O=L4_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I0 I1=L4_LUT4_I1_6_I2_LUT4_O_I2 I2=L4_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R4_LUT4_I3_34_O_LUT4_I2_1_O I1=L4_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_35_O_LUT4_I2_O I3=L4_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I1 O=L4_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=R4_LUT4_I3_34_O_LUT4_I2_2_O I2=L4_LUT4_I3_16_I0_LUT4_O_I3_LUT4_O_I0 I3=R4_LUT4_I3_34_O_LUT4_I2_O O=L4_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_2_I2_LUT4_O_I2 I3=L4_LUT4_I3_2_I1_LUT4_O_I2 O=L4_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_2_I2_LUT4_O_I2 I3=L4_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I0 O=L4_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L4_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2 I1=R4_LUT4_I3_34_O_LUT4_I2_1_O I2=R4_LUT4_I3_34_O_LUT4_I2_2_O I3=L4_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_35_O_LUT4_I2_O I1=L4_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 I2=L4_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I0 I3=R4_LUT4_I3_34_O_LUT4_I2_O O=L4_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_3_I0 I1=L4_LUT4_I3_3_I1 I2=L4_LUT4_I3_3_I2 I3=L4(22) O=R5_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L4_LUT4_I3_5_I1 I1=L4_LUT4_I3_6_I0_LUT4_O_I3 I2=L4_LUT4_I3_3_I0_LUT4_O_I2 I3=L4_LUT4_I3_5_I1_LUT4_O_I3 O=L4_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_3_I1_LUT4_O_I1 I2=L4_LUT4_I3_3_I2_LUT4_O_I1 I3=R4_LUT4_I3_46_O_LUT4_I2_O O=L4_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_46_O_LUT4_I2_1_O O=L4_LUT4_I3_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2 I2=R4_LUT4_I3_46_O_LUT4_I2_2_O I3=L4_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_1_O I1=L4_LUT4_I3_3_I2_LUT4_O_I1 I2=L4_LUT4_I3_3_I2_LUT4_O_I2 I3=L4_LUT4_I3_3_I2_LUT4_O_I3 O=L4_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R4_LUT4_I3_43_O I1=R4_LUT4_I3_44_O I2=R4_LUT4_I3_45_O I3=R4_LUT4_I3_42_O O=L4_LUT4_I3_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_2_O I1=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2 O=L4_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_6_I1_LUT4_I3_I1_LUT4_O_I0 I2=R4_LUT4_I3_46_O_LUT4_I2_1_O I3=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I0 O=L4_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_5_I1_LUT4_O_I1 I3=R4_LUT4_I3_47_O_LUT4_I2_O O=L4_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_2_O I1=L4_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I0 I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_4_I0 I1=L4_LUT4_I3_4_I1 I2=L4_LUT4_I3_4_I2 I3=L4(27) O=R5_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L4_LUT4_I3_4_I0 I1=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O I2=L4_LUT4_I3_4_I1_LUT4_O_I3 I3=L4_LUT4_I3_4_I1_LUT4_O_I1 O=L4_LUT4_I3_4_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I3_4_I1_LUT4_O_I3 I1=L4_LUT4_I3_4_I0 I2=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O I3=L4_LUT4_I3_4_I0_LUT4_I1_I3 O=L4_LUT4_I3_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2 I3=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3 O=L4_LUT4_I3_4_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_17_O_LUT4_I2_O I1=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3 I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3 I1=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2 I2=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_I2 I3=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_I3 O=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R4_LUT4_I3_17_O_LUT4_I2_O I1=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_1_O I1=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I2=R4_LUT4_I3_16_O_LUT4_I2_O I3=L4_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1 O=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_4_I0_LUT4_O_I2 I3=L4_LUT4_I3_4_I0_LUT4_O_I3 O=L4_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_1_O I1=L4_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_O I3=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 O=L4_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_13_O I1=R4_LUT4_I3_14_O I2=R4_LUT4_I3_15_O I3=R4_LUT4_I3_12_O O=L4_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_17_O_LUT4_I2_O I1=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 O=L4_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_1_O I1=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I2=R4_LUT4_I3_16_O_LUT4_I2_O I3=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_17_O_LUT4_I2_O I1=L4_LUT4_I3_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L4_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_1_I0_LUT4_O_I1 I1=L4_LUT4_I3_4_I1_LUT4_O_I1 I2=L4_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O I3=L4_LUT4_I3_4_I1_LUT4_O_I3 O=L4_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I1=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_O I3=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R4_LUT4_I3_12_O I1=R4_LUT4_I3_14_O I2=R4_LUT4_I3_13_O I3=R4_LUT4_I3_15_O O=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_14_O I1=R4_LUT4_I3_13_O I2=R4_LUT4_I3_15_O I3=R4_LUT4_I3_12_O O=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I1=R4_LUT4_I3_16_O_LUT4_I2_2_O I2=R4_LUT4_I3_17_O_LUT4_I2_O I3=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I1=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_16_O_LUT4_I2_2_O I3=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R4_LUT4_I3_13_O I1=R4_LUT4_I3_12_O I2=R4_LUT4_I3_15_O I3=R4_LUT4_I3_14_O O=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_14_O I1=R4_LUT4_I3_13_O I2=R4_LUT4_I3_12_O I3=R4_LUT4_I3_15_O O=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L4_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=R4_LUT4_I3_16_O_LUT4_I2_O I2=R4_LUT4_I3_16_O_LUT4_I2_1_O I3=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_4_I2_LUT4_O_I0 I1=L4_LUT4_I3_4_I2_LUT4_O_I1 I2=L4_LUT4_I3_4_I2_LUT4_O_I2 I3=L4_LUT4_I3_4_I2_LUT4_O_I3 O=L4_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1 I2=L4_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I2 I3=R4_LUT4_I3_17_O_LUT4_I2_O O=L4_LUT4_I3_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I1=R4_LUT4_I3_16_O_LUT4_I2_1_O I2=L4_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100001101
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3 I3=R4_LUT4_I3_16_O_LUT4_I2_O O=L4_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_15_O I1=R4_LUT4_I3_14_O I2=R4_LUT4_I3_13_O I3=R4_LUT4_I3_12_O O=L4_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_16_O_LUT4_I2_O I1=L4_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_17_O_LUT4_I2_O I3=L4_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_15_O I1=R4_LUT4_I3_14_O I2=R4_LUT4_I3_13_O I3=R4_LUT4_I3_12_O O=L4_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_1_I1_LUT4_O_I2 I3=L4_LUT4_I3_1_I2_LUT4_O_I3 O=L4_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_1_I1_LUT4_O_I1 I3=L4_LUT4_I3_14_I2_LUT4_O_I3 O=L4_LUT4_I3_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L4_LUT4_I3_5_I0 I1=L4_LUT4_I3_5_I1 I2=L4_LUT4_I3_5_I2 I3=L4(32) O=R5_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L4_LUT4_I3_5_I0_LUT4_O_I0 I1=L4_LUT4_I3_3_I1 I2=L4_LUT4_I3_6_I0_LUT4_O_I2 I3=L4_LUT4_I3_5_I0_LUT4_O_I3 O=L4_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I0 I1=R4_LUT4_I3_47_O_LUT4_I2_O I2=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2 I3=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3 O=L4_LUT4_I3_5_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R4_LUT4_I3_44_O I1=R4_LUT4_I3_45_O I2=R4_LUT4_I3_43_O I3=R4_LUT4_I3_42_O O=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_2_O I1=L4_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2 O=L4_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_45_O I1=R4_LUT4_I3_44_O I2=R4_LUT4_I3_43_O I3=R4_LUT4_I3_42_O O=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_6_I1_LUT4_I3_I1_LUT4_O_I0 I1=R4_LUT4_I3_46_O_LUT4_I2_O I2=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_46_O_LUT4_I2_1_O O=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_45_O I1=R4_LUT4_I3_44_O I2=R4_LUT4_I3_43_O I3=R4_LUT4_I3_42_O O=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_3_I2_LUT4_O_I1 I3=R4_LUT4_I3_47_O_LUT4_I2_O O=L4_LUT4_I3_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_46_O_LUT4_I2_1_O O=L4_LUT4_I3_5_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_1_O I1=L4_LUT4_I3_5_I1_LUT4_O_I1 I2=L4_LUT4_I3_5_I1_LUT4_O_I2 I3=L4_LUT4_I3_5_I1_LUT4_O_I3 O=L4_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R4_LUT4_I3_45_O I1=R4_LUT4_I3_44_O I2=R4_LUT4_I3_43_O I3=R4_LUT4_I3_42_O O=L4_LUT4_I3_5_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_46_O_LUT4_I2_2_O O=L4_LUT4_I3_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I2=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_46_O_LUT4_I2_O O=L4_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_45_O I1=R4_LUT4_I3_43_O I2=R4_LUT4_I3_44_O I3=R4_LUT4_I3_42_O O=L4_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_5_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 I2=L4_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_46_O_LUT4_I2_1_O O=L4_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_2_O I1=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=L4_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_5_I2_LUT4_O_I1 I2=L4_LUT4_I3_5_I2_LUT4_O_I2 I3=L4_LUT4_I3_5_I2_LUT4_O_I3 O=L4_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_3_I2_LUT4_O_I1 I3=R4_LUT4_I3_46_O_LUT4_I2_2_O O=L4_LUT4_I3_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_46_O_LUT4_I2_1_O O=L4_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 O=L4_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_6_I2_LUT4_O_I1 O=L4_LUT4_I3_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_46_O_LUT4_I2_2_O I3=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_1_O I1=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I0 O=L4_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I0 I1=L4_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_46_O_LUT4_I2_1_O I3=R4_LUT4_I3_46_O_LUT4_I2_2_O O=L4_LUT4_I3_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=R4_LUT4_I3_45_O I1=R4_LUT4_I3_44_O I2=R4_LUT4_I3_42_O I3=R4_LUT4_I3_43_O O=L4_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_45_O I1=R4_LUT4_I3_43_O I2=R4_LUT4_I3_42_O I3=R4_LUT4_I3_44_O O=L4_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L4_LUT4_I3_6_I0 I1=L4_LUT4_I3_6_I1 I2=L4_LUT4_I3_6_I2 I3=L4(7) O=R5_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_3_I2_LUT4_O_I2 I2=L4_LUT4_I3_6_I0_LUT4_O_I2 I3=L4_LUT4_I3_6_I0_LUT4_O_I3 O=L4_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_1_O I1=L4_LUT4_I3_5_I0_LUT4_O_I0_LUT4_O_I2 I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_46_O_LUT4_I2_2_O I3=L4_LUT4_I3_6_I1_LUT4_I3_I1_LUT4_O_I0 O=L4_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_44_O I1=R4_LUT4_I3_43_O I2=R4_LUT4_I3_45_O I3=R4_LUT4_I3_42_O O=L4_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_3_I1 I1=L4_LUT4_I3_5_I0_LUT4_O_I3 I2=L4_LUT4_I3_6_I0_LUT4_O_I2 I3=L4_LUT4_I3_5_I0_LUT4_O_I0 O=L4_LUT4_I3_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_6_I1 I3=L4_LUT4_I3_5_I2_LUT4_O_I1 O=L4_LUT4_I1_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L4_LUT4_I3_5_I2_LUT4_O_I2 I1=L4_LUT4_I3_6_I1_LUT4_I3_I1 I2=L4_LUT4_I3_6_I1_LUT4_I3_I2 I3=L4_LUT4_I3_6_I1 O=L4_LUT4_I3_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L4_LUT4_I3_6_I1_LUT4_I3_I1_LUT4_O_I0 I1=R4_LUT4_I3_46_O_LUT4_I2_1_O I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I3_6_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_43_O I1=R4_LUT4_I3_42_O I2=R4_LUT4_I3_45_O I3=R4_LUT4_I3_44_O O=L4_LUT4_I3_6_I1_LUT4_I3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_46_O_LUT4_I2_2_O I3=L4_LUT4_I3_6_I1_LUT4_I3_I2_LUT4_O_I3 O=L4_LUT4_I3_6_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_45_O I1=R4_LUT4_I3_44_O I2=R4_LUT4_I3_43_O I3=R4_LUT4_I3_42_O O=L4_LUT4_I3_6_I1_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_6_I1_LUT4_O_I1 I2=L4_LUT4_I3_5_I1_LUT4_O_I1 I3=R4_LUT4_I3_46_O_LUT4_I2_2_O O=L4_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_46_O_LUT4_I2_1_O O=L4_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_6_I1_LUT4_I3_I2_LUT4_O_I3 I2=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_46_O_LUT4_I2_O O=L4_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_44_O I1=R4_LUT4_I3_43_O I2=R4_LUT4_I3_42_O I3=R4_LUT4_I3_45_O O=L4_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L4_LUT4_I3_5_I2_LUT4_O_I3 I1=L4_LUT4_I3_6_I2_LUT4_O_I1 I2=L4_LUT4_I3_6_I2_LUT4_O_I2 I3=L4_LUT4_I3_6_I2_LUT4_O_I3 O=L4_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_6_I1_LUT4_I3_I2_LUT4_O_I3 O=L4_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_1_O I1=L4_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I0 I2=R4_LUT4_I3_46_O_LUT4_I2_2_O I3=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 O=L4_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_46_O_LUT4_I2_2_O I1=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_46_O_LUT4_I2_O I3=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_45_O I1=R4_LUT4_I3_44_O I2=R4_LUT4_I3_43_O I3=R4_LUT4_I3_42_O O=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_45_O I1=R4_LUT4_I3_42_O I2=R4_LUT4_I3_43_O I3=R4_LUT4_I3_44_O O=L4_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_47_O_LUT4_I2_O I1=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_46_O_LUT4_I2_1_O O=L4_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_44_O I1=R4_LUT4_I3_42_O I2=R4_LUT4_I3_43_O I3=R4_LUT4_I3_45_O O=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_42_O I1=R4_LUT4_I3_44_O I2=R4_LUT4_I3_43_O I3=R4_LUT4_I3_45_O O=L4_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L4_LUT4_I3_7_I0 I1=L4_LUT4_I3_7_I1 I2=L4_LUT4_I3_7_I2 I3=L4(9) O=R5_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_7_I0_LUT4_O_I1 I2=L4_LUT4_I3_7_I0_LUT4_O_I2 I3=L4_LUT4_I3_7_I0_LUT4_O_I3 O=L4_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_7_I0_LUT4_O_I1_LUT4_I3_I2 I3=L4_LUT4_I3_7_I0_LUT4_O_I1 O=L4_LUT4_I3_19_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_40_O_LUT4_I2_O O=L4_LUT4_I3_7_I0_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_7_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_40_O_LUT4_I2_2_O I3=L4_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 O=L4_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 I2=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_41_O_LUT4_I2_O O=L4_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_40_O_LUT4_I2_2_O I3=L4_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_41_O_LUT4_I2_O I3=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_39_O I1=R4_LUT4_I3_36_O I2=R4_LUT4_I3_37_O I3=R4_LUT4_I3_38_O O=L4_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_7_I1_LUT4_O_I0 I1=L4_LUT4_I3_7_I1_LUT4_O_I1 I2=L4_LUT4_I3_7_I1_LUT4_O_I2 I3=L4_LUT4_I3_7_I1_LUT4_O_I3 O=L4_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L4_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I0 I1=L4_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1 I2=L4_LUT4_I3_7_I2_LUT4_O_I2 I3=L4_LUT4_I3_19_I0_LUT4_O_I2 O=L4_LUT4_I3_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=R4_LUT4_I3_41_O_LUT4_I2_O I1=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 I2=L4_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_40_O_LUT4_I2_2_O O=L4_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_40_O_LUT4_I2_1_O I3=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_15_I2_LUT4_O_I3 I2=L4_LUT4_I2_2_I3_LUT4_O_I1 I3=L4_LUT4_I3_7_I2_LUT4_O_I3 O=L4_LUT4_I3_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_40_O_LUT4_I2_1_O O=L4_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_38_O I1=R4_LUT4_I3_37_O I2=R4_LUT4_I3_36_O I3=R4_LUT4_I3_39_O O=L4_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_36_O I1=R4_LUT4_I3_38_O I2=R4_LUT4_I3_37_O I3=R4_LUT4_I3_39_O O=L4_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_41_O_LUT4_I2_O I1=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_40_O_LUT4_I2_2_O I3=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_37_O I1=R4_LUT4_I3_38_O I2=R4_LUT4_I3_39_O I3=R4_LUT4_I3_36_O O=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_37_O I1=R4_LUT4_I3_36_O I2=R4_LUT4_I3_39_O I3=R4_LUT4_I3_38_O O=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_7_I2_LUT4_O_I1 I2=L4_LUT4_I3_7_I2_LUT4_O_I2 I3=L4_LUT4_I3_7_I2_LUT4_O_I3 O=L4_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_O I1=L4_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 I2=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_40_O_LUT4_I2_2_O O=L4_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_41_O_LUT4_I2_O O=L4_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_41_O_LUT4_I2_O I1=L4_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_19_I0_LUT4_O_I2 I3=L4_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R4_LUT4_I3_39_O I1=R4_LUT4_I3_38_O I2=R4_LUT4_I3_37_O I3=R4_LUT4_I3_36_O O=L4_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_40_O_LUT4_I2_O O=L4_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_40_O_LUT4_I2_1_O I1=L4_LUT4_I3_19_I1_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_40_O_LUT4_I2_2_O I3=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_40_O_LUT4_I2_O O=L4_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_40_O_LUT4_I2_1_O O=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_41_O_LUT4_I2_O I1=L4_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_40_O_LUT4_I2_2_O I3=L4_LUT4_I3_19_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_39_O I1=R4_LUT4_I3_37_O I2=R4_LUT4_I3_38_O I3=R4_LUT4_I3_36_O O=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_39_O I1=R4_LUT4_I3_38_O I2=R4_LUT4_I3_37_O I3=R4_LUT4_I3_36_O O=L4_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I3_8_I0 I1=L4_LUT4_I3_8_I1 I2=L4_LUT4_I3_8_I2 I3=L4(11) O=R5_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L4_LUT4_I3_8_I0_LUT4_O_I0 I1=R4_LUT4_I3_28_O_LUT4_I2_2_O I2=L4_LUT4_I3_8_I0_LUT4_O_I2 I3=L4_LUT4_I3_8_I0_LUT4_O_I3 O=L4_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R4_LUT4_I3_27_O I1=R4_LUT4_I3_26_O I2=R4_LUT4_I3_25_O I3=R4_LUT4_I3_24_O O=L4_LUT4_I3_8_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_I1_LUT4_O_I2 I3=L4_LUT4_I3_12_I1_LUT4_O_I2 O=L4_LUT4_I3_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_29_O_LUT4_I2_O I3=L4_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_28_O_LUT4_I2_1_O O=L4_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_24_O I1=R4_LUT4_I3_26_O I2=R4_LUT4_I3_25_O I3=R4_LUT4_I3_27_O O=L4_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_8_I1_LUT4_O_I1 I2=L4_LUT4_I3_8_I1_LUT4_O_I2 I3=L4_LUT4_I3_8_I1_LUT4_O_I3 O=L4_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_1_O I1=L4_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_28_O_LUT4_I2_2_O O=L4_LUT4_I3_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_27_O I1=R4_LUT4_I3_25_O I2=R4_LUT4_I3_24_O I3=R4_LUT4_I3_26_O O=L4_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_29_O_LUT4_I2_O I1=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_28_O_LUT4_I2_2_O I3=L4_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_29_O_LUT4_I2_O I1=L4_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 I2=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_28_O_LUT4_I2_2_O O=L4_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_26_O I1=R4_LUT4_I3_25_O I2=R4_LUT4_I3_27_O I3=R4_LUT4_I3_24_O O=L4_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I1=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_29_O_LUT4_I2_O I3=L4_LUT4_I3_12_I2_LUT4_O_I2 O=L4_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=L4_LUT4_I3_8_I2_LUT4_O_I0 I1=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O I2=L4_LUT4_I3_8_I2_LUT4_O_I2 I3=L4_LUT4_I3_8_I2_LUT4_O_I3 O=L4_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I1 I2=R4_LUT4_I3_28_O_LUT4_I2_1_O I3=L4_LUT4_I3_8_I0_LUT4_O_I0 O=L4_LUT4_I3_8_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R4_LUT4_I3_28_O_LUT4_I2_O O=L4_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_29_O_LUT4_I2_O I1=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_28_O_LUT4_I2_2_O I3=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I0 O=L4_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_1_O I1=L4_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I3=R4_LUT4_I3_28_O_LUT4_I2_2_O O=L4_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_1_O I1=L4_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_28_O_LUT4_I2_2_O I3=L4_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_27_O I1=R4_LUT4_I3_26_O I2=R4_LUT4_I3_25_O I3=R4_LUT4_I3_24_O O=L4_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I0 I2=R4_LUT4_I3_29_O_LUT4_I2_O I3=L4_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_27_O I1=R4_LUT4_I3_26_O I2=R4_LUT4_I3_24_O I3=R4_LUT4_I3_25_O O=L4_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L4_LUT4_I3_9_I0 I1=L4_LUT4_I3_9_I1 I2=L4_LUT4_I3_9_I2 I3=L4(13) O=R5_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_9_I0_LUT4_O_I1 I2=L4_LUT4_I1_I3_LUT4_O_I2 I3=L4_LUT4_I1_I3_LUT4_O_I0 O=L4_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I2_4_I3_LUT4_O_I0_LUT4_O_I2 I3=L4_LUT4_I3_9_I0_LUT4_O_I1 O=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_23_O_LUT4_I2_O I1=L4_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_22_O_LUT4_I2_O I3=L4_LUT4_I1_I2_LUT4_O_I0 O=L4_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_20_O I1=R4_LUT4_I3_18_O I2=R4_LUT4_I3_19_O I3=R4_LUT4_I3_21_O O=L4_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_22_O_LUT4_I2_1_O I3=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=L4_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I1=L4_LUT4_I3_9_I1_LUT4_O_I1 I2=L4_LUT4_I3_9_I1_LUT4_O_I2 I3=L4_LUT4_I3_9_I1_LUT4_O_I3 O=L4_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3 I1=R4_LUT4_I3_22_O_LUT4_I2_O I2=R4_LUT4_I3_23_O_LUT4_I2_O I3=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I1_I2_LUT4_O_I1 I2=R4_LUT4_I3_22_O_LUT4_I2_1_O I3=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 O=L4_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_22_O_LUT4_I2_1_O I3=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_21_O I1=R4_LUT4_I3_20_O I2=R4_LUT4_I3_19_O I3=R4_LUT4_I3_18_O O=L4_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_23_O_LUT4_I2_O I1=L4_LUT4_I1_I2_LUT4_O_I1 I2=R4_LUT4_I3_22_O_LUT4_I2_O I3=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R4_LUT4_I3_22_O_LUT4_I2_1_O I3=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_22_O_LUT4_I2_O O=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O I2=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_23_O_LUT4_I2_O O=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_20_O I1=R4_LUT4_I3_19_O I2=R4_LUT4_I3_21_O I3=R4_LUT4_I3_18_O O=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L4_LUT4_I3_9_I2_LUT4_I1_I0 I1=L4_LUT4_I3_9_I2 I2=L4_LUT4_I3_9_I2_LUT4_I1_I2 I3=L4_LUT4_I3_9_I2_LUT4_I1_I3 O=L4_LUT4_I2_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_9_I2_LUT4_I1_I0_LUT4_O_I1 I2=L4_LUT4_I1_I2_LUT4_O_I0 I3=R4_LUT4_I3_22_O_LUT4_I2_1_O O=L4_LUT4_I3_9_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_9_I2_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1 I3=R4_LUT4_I3_22_O_LUT4_I2_O O=L4_LUT4_I3_9_I2_LUT4_I1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L4_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_23_O_LUT4_I2_O O=L4_LUT4_I3_9_I2_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 I2=R4_LUT4_I3_22_O_LUT4_I2_1_O I3=L4_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_9_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_23_O_LUT4_I2_O I1=L4_LUT4_I3_9_I2_LUT4_I1_I3_LUT4_O_I1 I2=R4_LUT4_I3_22_O_LUT4_I2_O I3=L4_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 O=L4_LUT4_I3_9_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_21_O I1=R4_LUT4_I3_18_O I2=R4_LUT4_I3_19_O I3=R4_LUT4_I3_20_O O=L4_LUT4_I3_9_I2_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_9_I2_LUT4_O_I2 I3=L4_LUT4_I3_9_I2_LUT4_O_I3 O=L4_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L4_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I0 I1=R4_LUT4_I3_22_O_LUT4_I2_O I2=L4_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_22_O_LUT4_I2_1_O O=L4_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_21_O I1=R4_LUT4_I3_19_O I2=R4_LUT4_I3_20_O I3=R4_LUT4_I3_18_O O=L4_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_23_O_LUT4_I2_O I1=L4_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I2=R4_LUT4_I3_22_O_LUT4_I2_O I3=L4_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L4_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_21_O I1=R4_LUT4_I3_19_O I2=R4_LUT4_I3_18_O I3=R4_LUT4_I3_20_O O=L4_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_22_O_LUT4_I2_2_O I1=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_23_O_LUT4_I2_O I3=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_21_O I1=R4_LUT4_I3_20_O I2=R4_LUT4_I3_19_O I3=R4_LUT4_I3_18_O O=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_19_O I1=R4_LUT4_I3_20_O I2=R4_LUT4_I3_21_O I3=R4_LUT4_I3_18_O O=L4_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_I0_LUT4_O_I1 I2=L4_LUT4_I3_8_I0 I3=L4_LUT4_I3_I0_LUT4_O_I3 O=L4_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_1_O I1=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R4_LUT4_I3_29_O_LUT4_I2_O O=L4_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_28_O_LUT4_I2_2_O I3=L4_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_12_I1_LUT4_O_I1 I1=L4_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=L4_LUT4_I3_I1_LUT4_O_I1 O=L4_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I1=L4_LUT4_I3_8_I0_LUT4_O_I0 I2=R4_LUT4_I3_28_O I3=R4_LUT4_I3_29_O O=L4_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=R4_LUT4_I3_28_O_LUT4_I2_1_O I3=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_I1_LUT4_O_I1 I2=L4_LUT4_I3_I1_LUT4_O_I2 I3=L4_LUT4_I3_I0_LUT4_O_I1 O=L4_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L4_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 I2=R4_LUT4_I3_28_O_LUT4_I2_2_O I3=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_26_O I1=R4_LUT4_I3_25_O I2=R4_LUT4_I3_24_O I3=R4_LUT4_I3_27_O O=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_1_O I1=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R4_LUT4_I3_29_O_LUT4_I2_O I3=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_26_O I1=R4_LUT4_I3_24_O I2=R4_LUT4_I3_25_O I3=R4_LUT4_I3_27_O O=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_25_O I1=R4_LUT4_I3_24_O I2=R4_LUT4_I3_27_O I3=R4_LUT4_I3_26_O O=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L4_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2 I3=L4_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 O=L4_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R4_LUT4_I3_29_O_LUT4_I2_O I3=L4_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 O=L4_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_26_O I1=R4_LUT4_I3_27_O I2=R4_LUT4_I3_25_O I3=R4_LUT4_I3_24_O O=L4_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_1_O I1=L4_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R4_LUT4_I3_28_O_LUT4_I2_2_O I3=L4_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 O=L4_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L4_LUT4_I3_I2_LUT4_O_I0 I1=L4_LUT4_I3_I2_LUT4_O_I1 I2=L4_LUT4_I3_I2_LUT4_O_I2 I3=L4_LUT4_I3_I2_LUT4_O_I3 O=L4_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_18_I1_LUT4_O_I1 I2=L4_LUT4_I3_18_I1_LUT4_O_I3 I3=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O O=L4_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_1_O I1=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R4_LUT4_I3_28_O_LUT4_I2_2_O O=L4_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_27_O I1=R4_LUT4_I3_26_O I2=R4_LUT4_I3_25_O I3=R4_LUT4_I3_24_O O=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_25_O I1=R4_LUT4_I3_26_O I2=R4_LUT4_I3_27_O I3=R4_LUT4_I3_24_O O=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I2=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_29_O_LUT4_I2_O O=L4_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R4_LUT4_I3_27_O I1=R4_LUT4_I3_24_O I2=R4_LUT4_I3_25_O I3=R4_LUT4_I3_26_O O=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_27_O I1=R4_LUT4_I3_26_O I2=R4_LUT4_I3_25_O I3=R4_LUT4_I3_24_O O=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I0 I1=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_28_O_LUT4_I2_2_O O=L4_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101000100
+.subckt LUT4 I0=R4_LUT4_I3_27_O I1=R4_LUT4_I3_25_O I2=R4_LUT4_I3_26_O I3=R4_LUT4_I3_24_O O=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R4_LUT4_I3_28_O_LUT4_I2_O I1=L4_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=R4_LUT4_I3_29_O_LUT4_I2_O I3=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 O=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R4_LUT4_I3_29_O_LUT4_I2_O O=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=L4_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=R4_LUT4_I3_28_O_LUT4_I2_O O=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R4_LUT4_I3_27_O I1=R4_LUT4_I3_26_O I2=R4_LUT4_I3_25_O I3=R4_LUT4_I3_24_O O=L4_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=L4(1) D=R3(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(2) D=R3(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(11) D=R3(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(12) D=R3(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(13) D=R3(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(14) D=R3(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(15) D=R3(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(16) D=R3(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(17) D=R3(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(18) D=R3(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(19) D=R3(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(20) D=R3(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(3) D=R3(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(21) D=R3(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(22) D=R3(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(23) D=R3(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(24) D=R3(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(25) D=R3(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(26) D=R3(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(27) D=R3(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(28) D=R3(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(29) D=R3(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(30) D=R3(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(4) D=R3(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(31) D=R3(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(32) D=R3(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(5) D=R3(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(6) D=R3(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(7) D=R3(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(8) D=R3(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(9) D=R3(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L4(10) D=R3(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:137.1-138.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L5(3) I2=L5_LUT4_I1_I2 I3=L5_LUT4_I1_I3 O=R6_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L5(10) I2=L5_LUT4_I1_1_I2 I3=L5_LUT4_I1_1_I3 O=R6_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I1=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I2=L5_LUT4_I1_1_I2_LUT4_O_I2 I3=L5_LUT4_I1_1_I2_LUT4_O_I3 O=L5_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I1=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I2=L5_LUT4_I1_1_I2_LUT4_O_I2 I3=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3 O=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I0 I2=R5_LUT4_I3_10_O_LUT4_I2_2_O I3=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I2=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_11_O_LUT4_I2_O O=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_19_I2_LUT4_O_I2 I3=R5_LUT4_I3_10_O_LUT4_I2_O O=L5_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_10_O_LUT4_I2_1_O O=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_11_O_LUT4_I2_O I1=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_10_O_LUT4_I2_2_O O=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_8_O I1=R5_LUT4_I3_7_O I2=R5_LUT4_I3_6_O I3=R5_LUT4_I3_9_O O=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I1_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_10_O_LUT4_I2_2_O O=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_7_O I1=R5_LUT4_I3_8_O I2=R5_LUT4_I3_9_O I3=R5_LUT4_I3_6_O O=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_11_O_LUT4_I2_O I1=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I3=R5_LUT4_I3_10_O_LUT4_I2_1_O O=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_9_O I1=R5_LUT4_I3_6_O I2=R5_LUT4_I3_7_O I3=R5_LUT4_I3_8_O O=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O I1=L5_LUT4_I1_1_I3_LUT4_O_I1 I2=L5_LUT4_I1_1_I3_LUT4_O_I2 I3=L5_LUT4_I1_1_I3_LUT4_O_I3 O=L5_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I1=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_11_O I3=R5_LUT4_I3_10_O O=L5_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R5_LUT4_I3_9_O I1=R5_LUT4_I3_8_O I2=R5_LUT4_I3_7_O I3=R5_LUT4_I3_6_O O=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_9_O I1=R5_LUT4_I3_7_O I2=R5_LUT4_I3_8_O I3=R5_LUT4_I3_6_O O=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I1_4_I3_LUT4_O_I2 I1=L5_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_16_I1_LUT4_O_I2 I3=L5_LUT4_I1_1_I2_LUT4_O_I3 O=L5_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_19_I2_LUT4_O_I2 I3=R5_LUT4_I3_10_O_LUT4_I2_2_O O=L5_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_10_O_LUT4_I2_1_O I3=L5_LUT4_I1_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=L5_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_11_O_LUT4_I2_O O=L5_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I1=L5_LUT4_I3_19_I1_LUT4_O_I1 I2=L5_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I1_4_I2_LUT4_O_I0 O=L5_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_10_O_LUT4_I2_1_O O=L5_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_9_O I1=R5_LUT4_I3_8_O I2=R5_LUT4_I3_7_O I3=R5_LUT4_I3_6_O O=L5_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L5(12) I2=L5_LUT4_I1_2_I2 I3=L5_LUT4_I1_2_I3 O=R6_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_7_I1 I2=L5_LUT4_I3_7_I0_LUT4_O_I3 I3=L5_LUT4_I3_2_I1 O=L5_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L5_LUT4_I1_2_I3_LUT4_O_I0 I1=L5_LUT4_I3_2_I2 I2=L5_LUT4_I3_2_I0_LUT4_O_I1 I3=L5_LUT4_I1_2_I3_LUT4_O_I3 O=L5_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_11_I2_LUT4_O_I1 I2=L5_LUT4_I3_7_I2_LUT4_O_I3 I3=L5_LUT4_I3_7_I2_LUT4_O_I1 O=L5_LUT4_I1_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=L5(17) I2=L5_LUT4_I1_3_I2 I3=L5_LUT4_I1_3_I3 O=R6_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=L5_LUT4_I1_3_I2_LUT4_O_I0 I1=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I2=L5_LUT4_I1_3_I2_LUT4_O_I2 I3=L5_LUT4_I3_6_I1_LUT4_O_I1 O=L5_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_2_O I1=L5_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2 I3=L5_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I3 O=L5_LUT4_I1_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R5_LUT4_I3_41_O_LUT4_I2_O I1=L5_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 I2=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3 I3=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2 O=L5_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_40_O_LUT4_I2_1_O I3=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I1_3_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_40_O_LUT4_I2_2_O I3=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I1_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_39_O I1=R5_LUT4_I3_38_O I2=R5_LUT4_I3_37_O I3=R5_LUT4_I3_36_O O=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_39_O I1=R5_LUT4_I3_38_O I2=R5_LUT4_I3_37_O I3=R5_LUT4_I3_36_O O=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I1_3_I3_LUT4_O_I0 I1=L5_LUT4_I1_3_I3_LUT4_O_I1 I2=L5_LUT4_I1_8_I2_LUT4_O_I3 I3=L5_LUT4_I1_3_I3_LUT4_O_I3 O=L5_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 I1=L5_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I1 I2=R5_LUT4_I3_41_O I3=R5_LUT4_I3_40_O O=L5_LUT4_I1_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R5_LUT4_I3_38_O I1=R5_LUT4_I3_36_O I2=R5_LUT4_I3_37_O I3=R5_LUT4_I3_39_O O=L5_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I0 I1=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I1_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R5_LUT4_I3_40_O_LUT4_I2_2_O I3=L5_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2 O=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_36_O I1=R5_LUT4_I3_38_O I2=R5_LUT4_I3_37_O I3=R5_LUT4_I3_39_O O=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_1_O I1=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_41_O_LUT4_I2_O I3=L5_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 O=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_37_O I1=R5_LUT4_I3_38_O I2=R5_LUT4_I3_39_O I3=R5_LUT4_I3_36_O O=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_2_O I1=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R5_LUT4_I3_41_O_LUT4_I2_O I3=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_38_O I1=R5_LUT4_I3_37_O I2=R5_LUT4_I3_36_O I3=R5_LUT4_I3_39_O O=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I1 I3=R5_LUT4_I3_40_O_LUT4_I2_1_O O=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_37_O I1=R5_LUT4_I3_36_O I2=R5_LUT4_I3_39_O I3=R5_LUT4_I3_38_O O=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_1_O I1=L5_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_41_O_LUT4_I2_O I3=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_39_O I1=R5_LUT4_I3_37_O I2=R5_LUT4_I3_38_O I3=R5_LUT4_I3_36_O O=L5_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L5(1) I2=L5_LUT4_I1_4_I2 I3=L5_LUT4_I1_4_I3 O=R6_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=L5_LUT4_I1_4_I2_LUT4_O_I0 I1=L5_LUT4_I1_4_I2_LUT4_O_I1 I2=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I3=L5_LUT4_I3_19_I1 O=L5_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_4_I2_LUT4_O_I0_LUT4_O_I2 I3=L5_LUT4_I1_4_I2_LUT4_O_I0_LUT4_O_I3 O=L5_LUT4_I1_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L5_LUT4_I1_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=R5_LUT4_I3_10_O_LUT4_I2_2_O I2=R5_LUT4_I3_10_O_LUT4_I2_1_O I3=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=L5_LUT4_I1_4_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_8_O I1=R5_LUT4_I3_6_O I2=R5_LUT4_I3_7_O I3=R5_LUT4_I3_9_O O=L5_LUT4_I1_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R5_LUT4_I3_11_O_LUT4_I2_O I3=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I1_4_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_10_O_LUT4_I2_2_O O=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_7_O I1=R5_LUT4_I3_6_O I2=R5_LUT4_I3_9_O I3=R5_LUT4_I3_8_O O=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_9_O I1=R5_LUT4_I3_8_O I2=R5_LUT4_I3_6_O I3=R5_LUT4_I3_7_O O=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_11_O_LUT4_I2_O I1=L5_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2 I2=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_10_O_LUT4_I2_1_O O=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I2=L5_LUT4_I1_4_I3_LUT4_O_I2 I3=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O O=L5_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_19_I2_LUT4_O_I2 I3=R5_LUT4_I3_11_O_LUT4_I2_O O=L5_LUT4_I1_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I3=R5_LUT4_I3_10_O_LUT4_I2_O O=L5_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_2_O I1=L5_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=L5_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_10_O_LUT4_I2_1_O O=L5_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5(8) I2=L5_LUT4_I1_5_I2 I3=L5_LUT4_I1_5_I3 O=R6_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_7_I2_LUT4_O_I2 I2=L5_LUT4_I3_3_I2 I3=L5_LUT4_I1_5_I2_LUT4_O_I3 O=L5_LUT4_I1_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_4_O_LUT4_I2_2_O I3=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 O=L5_LUT4_I1_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_4_O_LUT4_I2_1_O I3=L5_LUT4_I1_7_I2_LUT4_O_I0 O=L5_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I2=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=R5_LUT4_I3_5_O_LUT4_I2_O O=L5_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I1_5_I3_LUT4_O_I0 I1=L5_LUT4_I1_I2_LUT4_O_I1 I2=L5_LUT4_I1_7_I3_LUT4_O_I3 I3=L5_LUT4_I1_7_I2 O=L5_LUT4_I1_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1 I1=L5_LUT4_I1_7_I2_LUT4_I2_I1 I2=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I1_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L5(9) I2=L5_LUT4_I1_6_I2 I3=L5_LUT4_I1_6_I3 O=R6_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_8_I2_LUT4_O_I0 I3=L5_LUT4_I1_8_I2_LUT4_O_I2 O=L5_LUT4_I1_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I1=L5_LUT4_I1_8_I3_LUT4_O_I1 I2=L5_LUT4_I1_6_I3_LUT4_O_I2 I3=L5_LUT4_I1_8_I3_LUT4_O_I3 O=L5_LUT4_I1_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I1_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_2_O I1=L5_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R5_LUT4_I3_41_O_LUT4_I2_O I3=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_40_O_LUT4_I2_1_O I3=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_1_O I1=L5_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_40_O_LUT4_I2_2_O O=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3 O=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_41_O_LUT4_I2_O I3=L5_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I1 O=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_2_O I1=L5_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_41_O_LUT4_I2_O I3=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_I2 I3=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 I2=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3 I3=R5_LUT4_I3_40_O_LUT4_I2_1_O O=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_39_O I1=R5_LUT4_I3_36_O I2=R5_LUT4_I3_37_O I3=R5_LUT4_I3_38_O O=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L5(14) I2=L5_LUT4_I1_7_I2 I3=L5_LUT4_I1_7_I3 O=R6_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_7_I2_LUT4_I2_I1 I2=L5_LUT4_I1_7_I2 I3=L5_LUT4_I1_7_I2_LUT4_I2_I3 O=L5_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I0 I1=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I1 I2=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I2 I3=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I3 O=L5_LUT4_I1_7_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I1_7_I2_LUT4_O_I0 I1=R5_LUT4_I3_5_O_LUT4_I2_O I2=R5_LUT4_I3_4_O_LUT4_I2_2_O I3=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3 O=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_3_O I1=R5_LUT4_I3_2_O I2=R5_LUT4_I3_1_O I3=R5_LUT4_I3_O O=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 I2=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=R5_LUT4_I3_4_O_LUT4_I2_1_O O=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_5_O_LUT4_I2_O I1=L5_LUT4_I1_7_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_4_O_LUT4_I2_2_O O=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3 I3=R5_LUT4_I3_4_O_LUT4_I2_1_O O=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_2_O I1=R5_LUT4_I3_O I2=R5_LUT4_I3_1_O I3=R5_LUT4_I3_3_O O=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_7_I2_LUT4_I2_I3_LUT4_O_I1 I2=L5_LUT4_I1_7_I2_LUT4_I2_I3_LUT4_O_I2 I3=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2 O=L5_LUT4_I1_7_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I1_7_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_5_O_LUT4_I2_O I3=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I1_7_I2_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_3_O I1=R5_LUT4_I3_1_O I2=R5_LUT4_I3_O I3=R5_LUT4_I3_2_O O=L5_LUT4_I1_7_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_2_O I1=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_4_O_LUT4_I2_1_O O=L5_LUT4_I1_7_I2_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I1_7_I2_LUT4_O_I0 I1=R5_LUT4_I3_4_O_LUT4_I2_2_O I2=L5_LUT4_I1_7_I2_LUT4_O_I2 I3=L5_LUT4_I1_7_I2_LUT4_O_I3 O=L5_LUT4_I1_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R5_LUT4_I3_3_O I1=R5_LUT4_I3_2_O I2=R5_LUT4_I3_1_O I3=R5_LUT4_I3_O O=L5_LUT4_I1_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I1_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_5_O_LUT4_I2_O I1=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I2 I2=L5_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0 I3=R5_LUT4_I3_4_O_LUT4_I2_2_O O=L5_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=R5_LUT4_I3_4_O_LUT4_I2_1_O I3=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 O=L5_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_4_O_LUT4_I2_O O=L5_LUT4_I1_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_5_O_LUT4_I2_O I1=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_4_O_LUT4_I2_1_O I3=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_O I1=R5_LUT4_I3_2_O I2=R5_LUT4_I3_1_O I3=R5_LUT4_I3_3_O O=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_3_O I1=R5_LUT4_I3_2_O I2=R5_LUT4_I3_1_O I3=R5_LUT4_I3_O O=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_7_I3_LUT4_O_I1 I2=L5_LUT4_I1_I3 I3=L5_LUT4_I1_7_I3_LUT4_O_I3 O=L5_LUT4_I1_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I1_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R5_LUT4_I3_5_O_LUT4_I2_O I3=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_2_O I1=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 I2=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R5_LUT4_I3_4_O_LUT4_I2_1_O O=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=R5_LUT4_I3_4_O_LUT4_I2_1_O I3=L5_LUT4_I1_7_I2_LUT4_I2_I3_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_5_O_LUT4_I2_O I1=L5_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0 I2=R5_LUT4_I3_4_O_LUT4_I2_2_O I3=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_1_O I1=R5_LUT4_I3_O I2=R5_LUT4_I3_3_O I3=R5_LUT4_I3_2_O O=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I1 I2=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I0 I3=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L5_LUT4_I1_I3 I1=L5_LUT4_I1_I2_LUT4_O_I0 I2=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0 I3=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I1_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L5(23) I2=L5_LUT4_I1_8_I2 I3=L5_LUT4_I1_8_I3 O=R6_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=L5_LUT4_I1_8_I2_LUT4_O_I0 I1=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I2=L5_LUT4_I1_8_I2_LUT4_O_I2 I3=L5_LUT4_I1_8_I2_LUT4_O_I3 O=L5_LUT4_I1_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=L5_LUT4_I3_6_I0_LUT4_O_I3 I1=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I2=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I0 I3=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I1_8_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_3_I3_LUT4_O_I1 I3=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O O=L5_LUT4_I1_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_8_I2_LUT4_O_I3_LUT4_I3_I1 I2=L5_LUT4_I1_8_I2_LUT4_O_I3_LUT4_I3_I2 I3=L5_LUT4_I1_8_I2_LUT4_O_I3 O=L5_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_1_O I1=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=R5_LUT4_I3_41_O_LUT4_I2_O O=L5_LUT4_I1_8_I2_LUT4_O_I3_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R5_LUT4_I3_40_O_LUT4_I2_2_O O=L5_LUT4_I1_8_I2_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I1_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R5_LUT4_I3_41_O_LUT4_I2_O O=L5_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_1_O I1=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R5_LUT4_I3_40_O_LUT4_I2_2_O I3=L5_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I1_8_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I1_8_I3_LUT4_O_I0 I1=L5_LUT4_I1_8_I3_LUT4_O_I1 I2=L5_LUT4_I1_8_I3_LUT4_O_I2 I3=L5_LUT4_I1_8_I3_LUT4_O_I3 O=L5_LUT4_I1_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_8_I3_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 I3=R5_LUT4_I3_40_O_LUT4_I2_O O=L5_LUT4_I1_8_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_40_O_LUT4_I2_1_O I3=L5_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2 O=L5_LUT4_I1_8_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I1=R5_LUT4_I3_41_O_LUT4_I2_O I2=R5_LUT4_I3_40_O_LUT4_I2_2_O I3=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I1_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_6_I0_LUT4_O_I3 I1=L5_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I3=L5_LUT4_I1_3_I3_LUT4_O_I1 O=L5_LUT4_I1_8_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I1_I2_LUT4_O_I0 I1=L5_LUT4_I1_I2_LUT4_O_I1 I2=L5_LUT4_I1_I2_LUT4_O_I2 I3=L5_LUT4_I1_I2_LUT4_O_I3 O=L5_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I2=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R5_LUT4_I3_4_O_LUT4_I2_O O=L5_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_4_O_LUT4_I2_1_O O=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_5_O_LUT4_I2_O I1=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3 I2=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R5_LUT4_I3_4_O_LUT4_I2_2_O O=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_2_O I1=R5_LUT4_I3_1_O I2=R5_LUT4_I3_O I3=R5_LUT4_I3_3_O O=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_3_O I1=R5_LUT4_I3_2_O I2=R5_LUT4_I3_1_O I3=R5_LUT4_I3_O O=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0 I1=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I1_5_I2_LUT4_O_I3 I3=L5_LUT4_I1_7_I2_LUT4_O_I2 O=L5_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_2_O I1=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I2 I2=R5_LUT4_I3_4_O_LUT4_I2_1_O I3=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_3_O I1=R5_LUT4_I3_1_O I2=R5_LUT4_I3_2_O I3=R5_LUT4_I3_O O=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_5_O_LUT4_I2_O O=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_2_O I1=R5_LUT4_I3_3_O I2=R5_LUT4_I3_1_O I3=R5_LUT4_I3_O O=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_I3_LUT4_O_I1 I2=L5_LUT4_I1_7_I2_LUT4_O_I0 I3=R5_LUT4_I3_4_O_LUT4_I2_O O=L5_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R5_LUT4_I3_5_O_LUT4_I2_O O=L5_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_2_O I1=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0 I3=R5_LUT4_I3_4_O_LUT4_I2_1_O O=L5_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5(15) I3=L5_LUT4_I2_I3 O=R6_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5(28) I3=L5_LUT4_I2_1_I3 O=R6_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L5_LUT4_I2_1_I3_LUT4_O_I0 I1=L5_LUT4_I2_1_I3_LUT4_O_I1 I2=L5_LUT4_I3_13_I1 I3=L5_LUT4_I3_I0_LUT4_O_I1 O=L5_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000001111111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_I2_LUT4_I1_O O=L5_LUT4_I2_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 I2=L5_LUT4_I3_I2_LUT4_O_I2 I3=R5_LUT4_I3_22_O_LUT4_I2_2_O O=L5_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_1_O I1=L5_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=R5_LUT4_I3_23_O_LUT4_I2_O I3=L5_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=L5_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5(30) I3=L5_LUT4_I2_2_I3 O=R6_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_I3_O I1=L5_LUT4_I3_14_I1 I2=L5_LUT4_I2_2_I3_LUT4_O_I2 I3=L5_LUT4_I2_2_I3_LUT4_O_I3 O=L5_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_35_O_LUT4_I2_O O=L5_LUT4_I2_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_31_O I1=R5_LUT4_I3_32_O I2=R5_LUT4_I3_33_O I3=R5_LUT4_I3_30_O O=L5_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I2_I3_LUT4_O_I0 I1=L5_LUT4_I3_4_I0_LUT4_I0_O I2=L5_LUT4_I2_I3_LUT4_O_I2 I3=L5_LUT4_I2_I3_LUT4_O_I3 O=L5_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L5_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L5_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2 I2=R5_LUT4_I3_16_O_LUT4_I2_O I3=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_4_I0_LUT4_O_I3 I3=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O O=L5_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L5_LUT4_I3_I0 I1=L5_LUT4_I3_I1 I2=L5_LUT4_I3_I2 I3=L5(2) O=R6_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L5_LUT4_I3_1_I0 I1=L5_LUT4_I3_1_I1 I2=L5_LUT4_I3_1_I2 I3=L5(18) O=R6_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=L5_LUT4_I3_10_I0 I1=L5_LUT4_I3_10_I1 I2=L5_LUT4_I3_10_I2 I3=L5(6) O=R6_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_14_I0_LUT4_O_I2 I3=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_I3_O O=L5_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L5_LUT4_I3_18_I1_LUT4_O_I0 I1=L5_LUT4_I3_10_I1_LUT4_O_I1 I2=L5_LUT4_I2_2_I3_LUT4_O_I2 I3=L5_LUT4_I3_18_I1_LUT4_O_I1 O=L5_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I2=L5_LUT4_I3_14_I1_LUT4_O_I3 I3=L5_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_10_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_34_O_LUT4_I2_O O=L5_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_18_I2_LUT4_O_I2_LUT4_I1_I2 I2=L5_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I3 I3=R5_LUT4_I3_35_O_LUT4_I2_O O=L5_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_10_I2_LUT4_O_I1 I2=L5_LUT4_I3_10_I2_LUT4_O_I2 I3=L5_LUT4_I3_18_I0_LUT4_O_I3 O=L5_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_I3_I1 I2=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_I3_I2 I3=L5_LUT4_I3_10_I2_LUT4_O_I1 O=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L5_LUT4_I3_18_I0_LUT4_O_I2_LUT4_O_I1 I1=R5_LUT4_I3_34_O_LUT4_I2_O I2=R5_LUT4_I3_34_O_LUT4_I2_2_O I3=L5_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_18_I2_LUT4_I3_I2_LUT4_O_I2 I1=R5_LUT4_I3_34_O_LUT4_I2_1_O I2=R5_LUT4_I3_35_O_LUT4_I2_O I3=L5_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_2_O I1=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_34_O_LUT4_I2_O I3=L5_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_31_O I1=R5_LUT4_I3_30_O I2=R5_LUT4_I3_33_O I3=R5_LUT4_I3_32_O O=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I3_18_I2_LUT4_I3_I2_LUT4_O_I2 I1=R5_LUT4_I3_35_O_LUT4_I2_O I2=R5_LUT4_I3_34_O_LUT4_I2_1_O I3=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_33_O I1=R5_LUT4_I3_31_O I2=R5_LUT4_I3_32_O I3=R5_LUT4_I3_30_O O=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_10_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_34_O_LUT4_I2_2_O I3=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_35_O_LUT4_I2_O I1=L5_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I2=R5_LUT4_I3_34_O_LUT4_I2_O I3=L5_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_32_O I1=R5_LUT4_I3_33_O I2=R5_LUT4_I3_31_O I3=R5_LUT4_I3_30_O O=L5_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I3_11_I0 I1=L5_LUT4_I3_11_I1 I2=L5_LUT4_I3_11_I2 I3=L5(7) O=R6_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_2_I2_LUT4_O_I2 I2=L5_LUT4_I3_7_I0_LUT4_O_I2 I3=L5_LUT4_I3_2_I0_LUT4_O_I1 O=L5_LUT4_I3_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_11_I1 I3=L5_LUT4_I3_7_I2_LUT4_O_I2 O=L5_LUT4_I1_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L5_LUT4_I3_11_I1_LUT4_I3_I0 I1=L5_LUT4_I3_11_I1_LUT4_I3_I1 I2=L5_LUT4_I3_7_I2_LUT4_O_I1 I3=L5_LUT4_I3_11_I1 O=L5_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111110000
+.subckt LUT4 I0=L5_LUT4_I3_11_I1_LUT4_I3_I0_LUT4_O_I0 I1=R5_LUT4_I3_42_O_LUT4_I2_1_O I2=R5_LUT4_I3_42_O_LUT4_I2_O I3=L5_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 O=L5_LUT4_I3_11_I1_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_46_O I1=R5_LUT4_I3_44_O I2=R5_LUT4_I3_45_O I3=R5_LUT4_I3_47_O O=L5_LUT4_I3_11_I1_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_11_I1_LUT4_I3_I1_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_2_O I3=L5_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_11_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_47_O I1=R5_LUT4_I3_46_O I2=R5_LUT4_I3_44_O I3=R5_LUT4_I3_45_O O=L5_LUT4_I3_11_I1_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_11_I1_LUT4_O_I1 I2=L5_LUT4_I3_2_I2_LUT4_O_I1 I3=R5_LUT4_I3_42_O_LUT4_I2_O O=L5_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_42_O_LUT4_I2_2_O O=L5_LUT4_I3_11_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_11_I1_LUT4_I3_I1_LUT4_O_I1 I3=R5_LUT4_I3_42_O_LUT4_I2_1_O O=L5_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_47_O I1=R5_LUT4_I3_46_O I2=R5_LUT4_I3_45_O I3=R5_LUT4_I3_44_O O=L5_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L5_LUT4_I3_7_I2_LUT4_O_I3 I1=L5_LUT4_I3_11_I2_LUT4_O_I1 I2=L5_LUT4_I3_11_I2_LUT4_O_I2 I3=L5_LUT4_I3_11_I2_LUT4_O_I3 O=L5_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_11_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 I2=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_42_O_LUT4_I2_2_O O=L5_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_1_O I1=L5_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I0 I2=R5_LUT4_I3_42_O_LUT4_I2_O I3=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_2_O I1=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_42_O_LUT4_I2_O O=L5_LUT4_I3_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_47_O I1=R5_LUT4_I3_46_O I2=R5_LUT4_I3_45_O I3=R5_LUT4_I3_44_O O=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_45_O I1=R5_LUT4_I3_46_O I2=R5_LUT4_I3_47_O I3=R5_LUT4_I3_44_O O=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_1_O I3=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_11_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_46_O I1=R5_LUT4_I3_45_O I2=R5_LUT4_I3_47_O I3=R5_LUT4_I3_44_O O=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_46_O I1=R5_LUT4_I3_47_O I2=R5_LUT4_I3_45_O I3=R5_LUT4_I3_44_O O=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I3_12_I0 I1=L5_LUT4_I3_12_I1 I2=L5_LUT4_I3_12_I2 I3=L5(11) O=R6_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_12_I0_LUT4_O_I2 I3=L5_LUT4_I3_12_I0_LUT4_O_I3 O=L5_LUT4_I3_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_12_I0_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_28_O_LUT4_I2_1_O I3=L5_LUT4_I3_5_I2_LUT4_O_I3 O=L5_LUT4_I3_12_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_12_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_12_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2 I2=L5_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3 I3=R5_LUT4_I3_29_O_LUT4_I2_O O=L5_LUT4_I3_12_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_8_I1_LUT4_O_I1 I3=L5_LUT4_I3_15_I1_LUT4_O_I2 O=L5_LUT4_I3_12_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_15_I2_LUT4_O_I1 I2=L5_LUT4_I3_12_I1_LUT4_O_I2 I3=L5_LUT4_I3_5_I2 O=L5_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_1_O I1=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_29_O_LUT4_I2_O O=L5_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_12_I2_LUT4_O_I0_LUT4_O_I1 O=L5_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_12_I2 I2=L5_LUT4_I3_12_I0_LUT4_O_I2 I3=L5_LUT4_I3_12_I2_LUT4_I1_I3 O=L5_LUT4_I3_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3 I3=L5_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I3 O=L5_LUT4_I3_12_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L5_LUT4_I3_12_I2_LUT4_O_I0 I1=L5_LUT4_I3_12_I2_LUT4_O_I1 I2=L5_LUT4_I3_12_I2_LUT4_O_I2 I3=L5_LUT4_I3_12_I2_LUT4_O_I3 O=L5_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_12_I2_LUT4_O_I0_LUT4_O_I1 I2=L5_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_29_O_LUT4_I2_O O=L5_LUT4_I3_12_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_27_O I1=R5_LUT4_I3_26_O I2=R5_LUT4_I3_25_O I3=R5_LUT4_I3_24_O O=L5_LUT4_I3_12_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_1_O I1=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0 I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_12_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_24_O I1=R5_LUT4_I3_26_O I2=R5_LUT4_I3_25_O I3=R5_LUT4_I3_27_O O=L5_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_1_O I1=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_29_O_LUT4_I2_O I3=L5_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_27_O I1=R5_LUT4_I3_26_O I2=R5_LUT4_I3_24_O I3=R5_LUT4_I3_25_O O=L5_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_27_O I1=R5_LUT4_I3_25_O I2=R5_LUT4_I3_24_O I3=R5_LUT4_I3_26_O O=L5_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L5_LUT4_I3_13_I0 I1=L5_LUT4_I3_13_I1 I2=L5_LUT4_I3_13_I2 I3=L5(13) O=R6_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_13_I0_LUT4_O_I1 I2=L5_LUT4_I3_I0_LUT4_O_I0 I3=L5_LUT4_I3_I0_LUT4_O_I2 O=L5_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_13_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_1_I1_LUT4_I3_I1_LUT4_O_I1 I2=R5_LUT4_I3_22_O_LUT4_I2_2_O I3=L5_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_1_O I1=L5_LUT4_I3_I1_LUT4_O_I2 I2=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0 I3=R5_LUT4_I3_23_O_LUT4_I2_O O=L5_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_1_I1_LUT4_O_I2 I1=R5_LUT4_I3_23_O_LUT4_I2_O I2=L5_LUT4_I3_I0_LUT4_O_I3 I3=L5_LUT4_I3_13_I1_LUT4_O_I3 O=L5_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_22_O_LUT4_I2_1_O O=L5_LUT4_I3_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I1 I2=L5_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=R5_LUT4_I3_22_O_LUT4_I2_2_O O=L5_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_21_O I1=R5_LUT4_I3_20_O I2=R5_LUT4_I3_19_O I3=R5_LUT4_I3_18_O O=L5_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_13_I2_LUT4_O_I1 I2=R5_LUT4_I3_22_O_LUT4_I2_2_O I3=L5_LUT4_I3_1_I1_LUT4_O_I2 O=L5_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_22_O_LUT4_I2_1_O O=L5_LUT4_I3_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_I2_LUT4_O_I2 I2=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_23_O_LUT4_I2_O O=L5_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_21_O I1=R5_LUT4_I3_19_O I2=R5_LUT4_I3_20_O I3=R5_LUT4_I3_18_O O=L5_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I3_14_I0 I1=L5_LUT4_I3_14_I1 I2=L5_LUT4_I3_14_I2 I3=L5(16) O=R6_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_I3_O I1=L5_LUT4_I3_18_I0_LUT4_O_I3 I2=L5_LUT4_I3_14_I0_LUT4_O_I2 I3=L5_LUT4_I2_2_I3_LUT4_O_I3 O=L5_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_14_I1_LUT4_O_I2 I3=L5_LUT4_I3_14_I1_LUT4_O_I3 O=L5_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_14_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L5_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I1=R5_LUT4_I3_34_O_LUT4_I2_O I2=R5_LUT4_I3_34_O_LUT4_I2_2_O I3=L5_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_35_O_LUT4_I2_O I1=R5_LUT4_I3_34_O_LUT4_I2_1_O I2=L5_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I2=R5_LUT4_I3_34_O_LUT4_I2_O I3=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_18_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_33_O I1=R5_LUT4_I3_31_O I2=R5_LUT4_I3_30_O I3=R5_LUT4_I3_32_O O=L5_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_18_I2_LUT4_O_I2_LUT4_I1_I2 I2=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R5_LUT4_I3_35_O_LUT4_I2_O O=L5_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_14_I2 I2=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_I3_O I3=L5_LUT4_I2_2_I3_LUT4_O_I2 O=L5_LUT4_I3_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_O I1=R5_LUT4_I3_34_O_LUT4_I2_2_O I2=L5_LUT4_I3_14_I2_LUT4_O_I2 I3=L5_LUT4_I3_14_I2_LUT4_O_I3 O=L5_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_14_I2_LUT4_O_I2_LUT4_I2_I1 I2=L5_LUT4_I3_14_I2_LUT4_O_I2 I3=R5_LUT4_I3_34_O_LUT4_I2_2_O O=L5_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_18_I0_LUT4_O_I1_LUT4_O_I2 I2=R5_LUT4_I3_34_O_LUT4_I2_O I3=L5_LUT4_I3_18_I2_LUT4_O_I2_LUT4_I1_I2 O=L5_LUT4_I3_14_I2_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_33_O I1=R5_LUT4_I3_32_O I2=R5_LUT4_I3_31_O I3=R5_LUT4_I3_30_O O=L5_LUT4_I3_14_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_2_O I1=L5_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_34_O_LUT4_I2_O I3=L5_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_33_O I1=R5_LUT4_I3_32_O I2=R5_LUT4_I3_31_O I3=R5_LUT4_I3_30_O O=L5_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_32_O I1=R5_LUT4_I3_31_O I2=R5_LUT4_I3_30_O I3=R5_LUT4_I3_33_O O=L5_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L5_LUT4_I3_8_I0 I1=L5_LUT4_I3_15_I1 I2=L5_LUT4_I3_15_I2 I3=L5(19) O=R6_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L5_LUT4_I3_15_I1_LUT4_O_I2 I3=L5_LUT4_I3_8_I0_LUT4_O_I3 O=L5_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_15_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_1_O I1=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_29_O_LUT4_I2_O I3=L5_LUT4_I3_12_I2_LUT4_O_I0_LUT4_O_I1 O=L5_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_8_I2_LUT4_O_I0 I1=L5_LUT4_I3_15_I2_LUT4_O_I1 I2=L5_LUT4_I3_12_I2_LUT4_O_I0 I3=L5_LUT4_I3_12_I2_LUT4_O_I1 O=L5_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_15_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_2_O I1=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O O=L5_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_1_O I1=L5_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R5_LUT4_I3_29_O_LUT4_I2_O O=L5_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2 O=L5_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_16_I0 I1=L5_LUT4_I3_16_I1 I2=L5_LUT4_I3_16_I2 I3=L5(20) O=R6_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I3=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O O=L5_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_16_I1_LUT4_O_I2 I3=L5_LUT4_I1_4_I3_LUT4_O_I2 O=L5_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_16_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_10_O_LUT4_I2_1_O I3=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R5_LUT4_I3_10_O_LUT4_I2_2_O O=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=R5_LUT4_I3_10_O_LUT4_I2_1_O I3=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=R5_LUT4_I3_11_O_LUT4_I2_O I3=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I0 O=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_8_O I1=R5_LUT4_I3_7_O I2=R5_LUT4_I3_9_O I3=R5_LUT4_I3_6_O O=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_11_O_LUT4_I2_O I1=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I2=R5_LUT4_I3_10_O_LUT4_I2_2_O I3=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I1_4_I2_LUT4_O_I1 I2=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I3=L5_LUT4_I3_19_I2 O=L5_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L5_LUT4_I3_17_I0 I1=L5_LUT4_I3_17_I1 I2=L5_LUT4_I3_17_I2 I3=L5(21) O=R6_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_9_I0_LUT4_O_I1 I2=L5_LUT4_I2_I3_LUT4_O_I0 I3=L5_LUT4_I3_4_I0_LUT4_I0_O O=L5_LUT4_I3_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_4_I0_LUT4_O_I2 I2=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L5_LUT4_I3_4_I0_LUT4_I0_O O=L5_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_17_I2_LUT4_O_I1 I2=L5_LUT4_I3_17_I2_LUT4_O_I2 I3=L5_LUT4_I3_4_I2_LUT4_O_I0 O=L5_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_17_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_15_O I1=R5_LUT4_I3_14_O I2=R5_LUT4_I3_13_O I3=R5_LUT4_I3_12_O O=L5_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_16_O_LUT4_I2_O I3=L5_LUT4_I3_9_I1_LUT4_O_I0_LUT4_O_I2 O=L5_LUT4_I3_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_15_O I1=R5_LUT4_I3_14_O I2=R5_LUT4_I3_12_O I3=R5_LUT4_I3_13_O O=L5_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L5_LUT4_I3_18_I0 I1=L5_LUT4_I3_18_I1 I2=L5_LUT4_I3_18_I2 I3=L5(24) O=R6_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_10_I2_LUT4_O_I2 I2=L5_LUT4_I3_18_I2_LUT4_I3_I2 I3=L5_LUT4_I3_18_I0 O=L5_LUT4_I2_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_18_I0_LUT4_O_I1 I2=L5_LUT4_I3_18_I0_LUT4_O_I2 I3=L5_LUT4_I3_18_I0_LUT4_O_I3 O=L5_LUT4_I3_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_18_I0_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_18_I0_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_34_O_LUT4_I2_O O=L5_LUT4_I3_18_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_33_O I1=R5_LUT4_I3_30_O I2=R5_LUT4_I3_31_O I3=R5_LUT4_I3_32_O O=L5_LUT4_I3_18_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_33_O I1=R5_LUT4_I3_32_O I2=R5_LUT4_I3_31_O I3=R5_LUT4_I3_30_O O=L5_LUT4_I3_18_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_35_O_LUT4_I2_O I1=L5_LUT4_I3_18_I0_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_34_O_LUT4_I2_2_O O=L5_LUT4_I3_18_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_32_O I1=R5_LUT4_I3_30_O I2=R5_LUT4_I3_31_O I3=R5_LUT4_I3_33_O O=L5_LUT4_I3_18_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I0 I1=L5_LUT4_I3_18_I0_LUT4_O_I2 I2=L5_LUT4_I3_18_I0_LUT4_O_I1 I3=L5_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_18_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_18_I0_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_35_O_LUT4_I2_O O=L5_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_18_I2_LUT4_I3_I1_LUT4_O_I1 I2=R5_LUT4_I3_35_O_LUT4_I2_O I3=L5_LUT4_I3_18_I0_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=L5_LUT4_I3_18_I1_LUT4_O_I0 I1=L5_LUT4_I3_18_I1_LUT4_O_I1 I2=L5_LUT4_I3_14_I1_LUT4_O_I2 I3=L5_LUT4_I3_18_I1_LUT4_O_I3 O=L5_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_18_I1_LUT4_O_I0_LUT4_O_I1 I2=L5_LUT4_I3_18_I2_LUT4_O_I2 I3=R5_LUT4_I3_34_O_LUT4_I2_2_O O=L5_LUT4_I3_18_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_18_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_35_O_LUT4_I2_O O=L5_LUT4_I3_18_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_2_O I1=L5_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I3 I2=L5_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3 I3=L5_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_18_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_2_O I1=L5_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R5_LUT4_I3_34_O_LUT4_I2_O O=L5_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=R5_LUT4_I3_32_O I1=R5_LUT4_I3_31_O I2=R5_LUT4_I3_33_O I3=R5_LUT4_I3_30_O O=L5_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_18_I2_LUT4_I3_I1 I2=L5_LUT4_I3_18_I2_LUT4_I3_I2 I3=L5_LUT4_I3_18_I2 O=L5_LUT4_I3_14_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L5_LUT4_I3_18_I0_LUT4_O_I1_LUT4_O_I2 I1=L5_LUT4_I3_18_I2_LUT4_I3_I1_LUT4_O_I1 I2=R5_LUT4_I3_34_O_LUT4_I2_2_O I3=L5_LUT4_I3_18_I2_LUT4_I3_I1_LUT4_O_I3 O=L5_LUT4_I3_18_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R5_LUT4_I3_33_O I1=R5_LUT4_I3_32_O I2=R5_LUT4_I3_30_O I3=R5_LUT4_I3_31_O O=L5_LUT4_I3_18_I2_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I3 I2=L5_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R5_LUT4_I3_35_O_LUT4_I2_O O=L5_LUT4_I3_18_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_35_O_LUT4_I2_O I1=R5_LUT4_I3_34_O_LUT4_I2_1_O I2=L5_LUT4_I3_18_I2_LUT4_I3_I2_LUT4_O_I2 I3=L5_LUT4_I3_18_I2_LUT4_I3_I2_LUT4_O_I3 O=L5_LUT4_I3_18_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R5_LUT4_I3_30_O I1=R5_LUT4_I3_32_O I2=R5_LUT4_I3_31_O I3=R5_LUT4_I3_33_O O=L5_LUT4_I3_18_I2_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_18_I0_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_35_O_LUT4_I2_O I3=L5_LUT4_I3_18_I2_LUT4_I3_I1_LUT4_O_I1 O=L5_LUT4_I3_18_I2_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_18_I2_LUT4_O_I1 I2=L5_LUT4_I3_18_I2_LUT4_O_I2 I3=R5_LUT4_I3_34_O_LUT4_I2_O O=L5_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_34_O_LUT4_I2_2_O I3=L5_LUT4_I3_18_I0_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_18_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L5_LUT4_I3_18_I0_LUT4_O_I1_LUT4_O_I1 I3=R5_LUT4_I3_35_O_LUT4_I2_O O=L5_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_34_O_LUT4_I2_1_O I1=L5_LUT4_I3_18_I2_LUT4_O_I2 I2=L5_LUT4_I3_18_I2_LUT4_O_I2_LUT4_I1_I2 I3=R5_LUT4_I3_35_O_LUT4_I2_O O=L5_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_33_O I1=R5_LUT4_I3_32_O I2=R5_LUT4_I3_31_O I3=R5_LUT4_I3_30_O O=L5_LUT4_I3_18_I2_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_33_O I1=R5_LUT4_I3_32_O I2=R5_LUT4_I3_31_O I3=R5_LUT4_I3_30_O O=L5_LUT4_I3_18_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_19_I0 I1=L5_LUT4_I3_19_I1 I2=L5_LUT4_I3_19_I2 I3=L5(26) O=R6_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L5_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O I1=L5_LUT4_I1_1_I3_LUT4_O_I2 I2=L5_LUT4_I3_16_I1 I3=L5_LUT4_I3_19_I0_LUT4_O_I3 O=L5_LUT4_I3_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O I3=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O O=L5_LUT4_I3_19_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_19_I1_LUT4_O_I1 I2=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I3=L5_LUT4_I3_19_I1_LUT4_O_I3 O=L5_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_19_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2 I2=L5_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R5_LUT4_I3_10_O_LUT4_I2_1_O O=L5_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_11_O_LUT4_I2_O I1=L5_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_10_O_LUT4_I2_2_O I3=L5_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2 O=L5_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_8_O I1=R5_LUT4_I3_9_O I2=R5_LUT4_I3_7_O I3=R5_LUT4_I3_6_O O=L5_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I0 I1=R5_LUT4_I3_10_O_LUT4_I2_2_O I2=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_19_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R5_LUT4_I3_9_O I1=R5_LUT4_I3_8_O I2=R5_LUT4_I3_7_O I3=R5_LUT4_I3_6_O O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I1_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I2=R5_LUT4_I3_11_O_LUT4_I2_O I3=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2 O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_6_O I1=R5_LUT4_I3_8_O I2=R5_LUT4_I3_7_O I3=R5_LUT4_I3_9_O O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_O I1=L5_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_11_O_LUT4_I2_O O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_2_O I1=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R5_LUT4_I3_10_O_LUT4_I2_1_O I3=L5_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2 O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_10_O_LUT4_I2_2_O I1=L5_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_10_O_LUT4_I2_1_O O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=L5_LUT4_I1_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=R5_LUT4_I3_11_O_LUT4_I2_O O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O I2=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I0 I3=R5_LUT4_I3_10_O_LUT4_I2_O O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_9_O I1=R5_LUT4_I3_8_O I2=R5_LUT4_I3_7_O I3=R5_LUT4_I3_6_O O=L5_LUT4_I3_19_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_19_I2_LUT4_O_I1 I2=L5_LUT4_I3_19_I2_LUT4_O_I2 I3=R5_LUT4_I3_10_O_LUT4_I2_1_O O=L5_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_10_O_LUT4_I2_O O=L5_LUT4_I3_19_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_11_O_LUT4_I2_O I1=L5_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=R5_LUT4_I3_10_O_LUT4_I2_2_O I3=L5_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_9_O I1=R5_LUT4_I3_7_O I2=R5_LUT4_I3_6_O I3=R5_LUT4_I3_8_O O=L5_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_9_O I1=R5_LUT4_I3_8_O I2=R5_LUT4_I3_7_O I3=R5_LUT4_I3_6_O O=L5_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_13_I2 I1=L5_LUT4_I2_1_I3_LUT4_O_I1 I2=L5_LUT4_I3_I0_LUT4_O_I3 I3=L5_LUT4_I3_1_I0_LUT4_O_I3 O=L5_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=R5_LUT4_I3_23_O_LUT4_I2_O I3=L5_LUT4_I3_1_I1_LUT4_I3_I1_LUT4_O_I1 O=L5_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_1_O I1=L5_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=R5_LUT4_I3_22_O_LUT4_I2_2_O I3=L5_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 O=L5_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_1_I1 I1=L5_LUT4_I3_1_I2_LUT4_O_I1 I2=L5_LUT4_I3_1_I1_LUT4_I0_I2 I3=L5_LUT4_I3_1_I1_LUT4_I0_I3 O=L5_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_1_I1_LUT4_I3_I2 I1=L5_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I3 I2=L5_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_1_I1_LUT4_I3_I1 O=L5_LUT4_I3_1_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0 I1=R5_LUT4_I3_22_O_LUT4_I2_O I2=L5_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1 I3=L5_LUT4_I3_1_I1_LUT4_I0_I3_LUT4_O_I3 O=L5_LUT4_I3_1_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_2_O I1=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I2=R5_LUT4_I3_23_O_LUT4_I2_O I3=L5_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 O=L5_LUT4_I3_1_I1_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_1_I1_LUT4_I3_I1 I2=L5_LUT4_I3_1_I1_LUT4_I3_I2 I3=L5_LUT4_I3_1_I1 O=L5_LUT4_I2_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_1_O I1=L5_LUT4_I3_1_I1_LUT4_I3_I1_LUT4_O_I1 I2=R5_LUT4_I3_23_O_LUT4_I2_O I3=L5_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_1_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_18_O I1=R5_LUT4_I3_20_O I2=R5_LUT4_I3_19_O I3=R5_LUT4_I3_21_O O=L5_LUT4_I3_1_I1_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_I1_LUT4_O_I2 I2=R5_LUT4_I3_22_O_LUT4_I2_2_O I3=L5_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0 O=L5_LUT4_I3_1_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_1_I1_LUT4_O_I1 I2=L5_LUT4_I3_1_I1_LUT4_O_I2 I3=R5_LUT4_I3_22_O_LUT4_I2_O O=L5_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0 I3=R5_LUT4_I3_22_O_LUT4_I2_1_O O=L5_LUT4_I3_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_2_O I1=L5_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 I2=R5_LUT4_I3_23_O_LUT4_I2_O I3=L5_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_21_O I1=R5_LUT4_I3_20_O I2=R5_LUT4_I3_18_O I3=R5_LUT4_I3_19_O O=L5_LUT4_I3_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_21_O I1=R5_LUT4_I3_20_O I2=R5_LUT4_I3_19_O I3=R5_LUT4_I3_18_O O=L5_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I3_1_I2_LUT4_O_I0 I1=L5_LUT4_I3_1_I2_LUT4_O_I1 I2=L5_LUT4_I3_1_I2_LUT4_O_I2 I3=L5_LUT4_I3_1_I2_LUT4_O_I3 O=L5_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0 I1=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I1 I2=R5_LUT4_I3_22_O I3=R5_LUT4_I3_23_O O=L5_LUT4_I3_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R5_LUT4_I3_19_O I1=R5_LUT4_I3_18_O I2=R5_LUT4_I3_21_O I3=R5_LUT4_I3_20_O O=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_20_O I1=R5_LUT4_I3_19_O I2=R5_LUT4_I3_21_O I3=R5_LUT4_I3_18_O O=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=L5_LUT4_I3_1_I1_LUT4_I3_I1_LUT4_O_I1 I3=R5_LUT4_I3_22_O_LUT4_I2_2_O O=L5_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_1_O I1=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0 I2=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_23_O_LUT4_I2_O O=L5_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_22_O_LUT4_I2_1_O I3=L5_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_20_O I1=R5_LUT4_I3_19_O I2=R5_LUT4_I3_18_O I3=R5_LUT4_I3_21_O O=L5_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I0 I2=R5_LUT4_I3_23_O_LUT4_I2_O I3=L5_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_1_O I1=L5_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=R5_LUT4_I3_22_O_LUT4_I2_2_O I3=L5_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 O=L5_LUT4_I3_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_2_I0 I1=L5_LUT4_I3_2_I1 I2=L5_LUT4_I3_2_I2 I3=L5(22) O=R6_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L5_LUT4_I3_2_I0_LUT4_O_I0 I1=L5_LUT4_I3_2_I0_LUT4_O_I1 I2=L5_LUT4_I3_7_I1 I3=L5_LUT4_I3_7_I1_LUT4_O_I3 O=L5_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=L5_LUT4_I3_2_I1 I1=L5_LUT4_I3_7_I0_LUT4_O_I3 I2=L5_LUT4_I3_7_I0_LUT4_O_I2 I3=L5_LUT4_I3_7_I0_LUT4_O_I0 O=L5_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_2_I1_LUT4_O_I1 I2=L5_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_43_O_LUT4_I2_O O=L5_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_11_I1_LUT4_I3_I1_LUT4_O_I1 I3=R5_LUT4_I3_42_O_LUT4_I2_O O=L5_LUT4_I3_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L5_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3 I1=R5_LUT4_I3_42_O_LUT4_I2_2_O I2=R5_LUT4_I3_42_O_LUT4_I2_1_O I3=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 O=L5_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_2_O I1=L5_LUT4_I3_2_I2_LUT4_O_I1 I2=L5_LUT4_I3_2_I2_LUT4_O_I2 I3=L5_LUT4_I3_2_I2_LUT4_O_I3 O=L5_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R5_LUT4_I3_47_O I1=R5_LUT4_I3_46_O I2=R5_LUT4_I3_45_O I3=R5_LUT4_I3_44_O O=L5_LUT4_I3_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_1_O I1=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=R5_LUT4_I3_42_O_LUT4_I2_O I3=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3 I2=R5_LUT4_I3_42_O_LUT4_I2_2_O I3=L5_LUT4_I3_11_I1_LUT4_I3_I0_LUT4_O_I0 O=L5_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_42_O_LUT4_I2_1_O O=L5_LUT4_I3_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I0 I3=R5_LUT4_I3_42_O_LUT4_I2_O O=L5_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_3_I0 I1=L5_LUT4_I1_I3 I2=L5_LUT4_I3_3_I2 I3=L5(25) O=R6_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L5_LUT4_I1_7_I3_LUT4_O_I3 I1=L5_LUT4_I1_5_I2_LUT4_O_I3 I2=L5_LUT4_I3_3_I0_LUT4_O_I2 I3=L5_LUT4_I3_3_I0_LUT4_O_I3 O=L5_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L5_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0 I1=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I2=R5_LUT4_I3_4_O_LUT4_I2_O I3=L5_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R5_LUT4_I3_2_O I1=R5_LUT4_I3_1_O I2=R5_LUT4_I3_3_O I3=R5_LUT4_I3_O O=L5_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_5_O_LUT4_I2_O I1=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=R5_LUT4_I3_4_O_LUT4_I2_2_O O=L5_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I1_7_I2_LUT4_I2_I3 O=L5_LUT4_I3_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_4_O_LUT4_I2_1_O I3=L5_LUT4_I1_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_5_O_LUT4_I2_O I1=L5_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=R5_LUT4_I3_4_O_LUT4_I2_2_O I3=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_5_O_LUT4_I2_O I1=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 I2=R5_LUT4_I3_4_O_LUT4_I2_1_O I3=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I1_7_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=R5_LUT4_I3_4_O_LUT4_I2_2_O I3=L5_LUT4_I1_7_I2_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_3_I0_LUT4_O_I2 I2=L5_LUT4_I3_3_I2 I3=L5_LUT4_I1_5_I2_LUT4_O_I3 O=L5_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_3_I2_LUT4_O_I2 I3=L5_LUT4_I3_3_I2_LUT4_O_I3 O=L5_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_5_O_LUT4_I2_O I1=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_4_O_LUT4_I2_2_O O=L5_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_3_O I1=R5_LUT4_I3_2_O I2=R5_LUT4_I3_O I3=R5_LUT4_I3_1_O O=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_1_O I1=R5_LUT4_I3_2_O I2=R5_LUT4_I3_3_O I3=R5_LUT4_I3_O O=L5_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_4_O_LUT4_I2_O I1=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_4_O_LUT4_I2_1_O I3=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_3_O I1=R5_LUT4_I3_2_O I2=R5_LUT4_I3_1_O I3=R5_LUT4_I3_O O=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_3_O I1=R5_LUT4_I3_O I2=R5_LUT4_I3_1_O I3=R5_LUT4_I3_2_O O=L5_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I3_4_I0 I1=L5_LUT4_I3_4_I1 I2=L5_LUT4_I3_4_I2 I3=L5(27) O=R6_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L5_LUT4_I3_4_I0 I1=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I2=L5_LUT4_I3_4_I1_LUT4_O_I3 I3=L5_LUT4_I3_4_I1_LUT4_O_I1 O=L5_LUT4_I3_4_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_4_I1_LUT4_O_I3 I1=L5_LUT4_I3_4_I0 I2=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L5_LUT4_I3_4_I0_LUT4_I1_I3 O=L5_LUT4_I3_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2 I3=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O O=L5_LUT4_I3_4_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_4_I0_LUT4_O_I2 I3=L5_LUT4_I3_4_I0_LUT4_O_I3 O=L5_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I3=R5_LUT4_I3_16_O_LUT4_I2_O O=L5_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_12_O I1=R5_LUT4_I3_14_O I2=R5_LUT4_I3_13_O I3=R5_LUT4_I3_15_O O=L5_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 O=L5_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I2=R5_LUT4_I3_16_O_LUT4_I2_O I3=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_9_I0_LUT4_O_I1 I1=L5_LUT4_I3_4_I1_LUT4_O_I1 I2=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I3=L5_LUT4_I3_4_I1_LUT4_O_I3 O=L5_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I1=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_16_O_LUT4_I2_O I3=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R5_LUT4_I3_13_O I1=R5_LUT4_I3_14_O I2=R5_LUT4_I3_15_O I3=R5_LUT4_I3_12_O O=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_14_O I1=R5_LUT4_I3_12_O I2=R5_LUT4_I3_13_O I3=R5_LUT4_I3_15_O O=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1 I1=R5_LUT4_I3_16_O_LUT4_I2_2_O I2=R5_LUT4_I3_17_O_LUT4_I2_O I3=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I1=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R5_LUT4_I3_13_O I1=R5_LUT4_I3_12_O I2=R5_LUT4_I3_15_O I3=R5_LUT4_I3_14_O O=L5_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=R5_LUT4_I3_16_O_LUT4_I2_O I2=R5_LUT4_I3_16_O_LUT4_I2_1_O I3=L5_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L5_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_4_I2_LUT4_O_I0 I1=L5_LUT4_I3_4_I2_LUT4_O_I1 I2=L5_LUT4_I3_4_I2_LUT4_O_I2 I3=L5_LUT4_I3_4_I2_LUT4_O_I3 O=L5_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_9_I2_LUT4_O_I3 I1=R5_LUT4_I3_16_O_LUT4_I2_O I2=L5_LUT4_I3_9_I1_LUT4_O_I0 I3=L5_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I3 O=L5_LUT4_I3_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 I3=R5_LUT4_I3_16_O_LUT4_I2_2_O O=L5_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I2=R5_LUT4_I3_17_O_LUT4_I2_O I3=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_I3 O=L5_LUT4_I3_4_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_I3 I1=R5_LUT4_I3_16_O_LUT4_I2_2_O I2=R5_LUT4_I3_17_O_LUT4_I2_O I3=L5_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 I2=L5_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_16_O_LUT4_I2_O O=L5_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_14_O I1=R5_LUT4_I3_15_O I2=R5_LUT4_I3_13_O I3=R5_LUT4_I3_12_O O=L5_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I3_4_I2_LUT4_O_I2 I1=L5_LUT4_I3_4_I2_LUT4_O_I3 I2=L5_LUT4_I3_17_I2_LUT4_O_I2 I3=L5_LUT4_I3_17_I2_LUT4_O_I1 O=L5_LUT4_I3_9_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_16_O_LUT4_I2_O I3=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_15_O I1=R5_LUT4_I3_13_O I2=R5_LUT4_I3_12_O I3=R5_LUT4_I3_14_O O=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_15_O I1=R5_LUT4_I3_14_O I2=R5_LUT4_I3_13_O I3=R5_LUT4_I3_12_O O=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_9_I1_LUT4_O_I0_LUT4_O_I2 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_15_O I1=R5_LUT4_I3_14_O I2=R5_LUT4_I3_13_O I3=R5_LUT4_I3_12_O O=L5_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I1=L5_LUT4_I3_5_I1 I2=L5_LUT4_I3_5_I2 I3=L5(29) O=R6_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L5_LUT4_I3_5_I1_LUT4_O_I0 I1=L5_LUT4_I3_5_I1_LUT4_O_I1 I2=L5_LUT4_I3_5_I1_LUT4_O_I2 I3=L5_LUT4_I3_8_I0_LUT4_O_I1 O=L5_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_5_I1_LUT4_O_I0_LUT4_O_I1 I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_5_I2_LUT4_O_I3 O=L5_LUT4_I3_5_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_5_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_28_O_LUT4_I2_1_O O=L5_LUT4_I3_5_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3 I2=R5_LUT4_I3_29_O_LUT4_I2_O I3=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 O=L5_LUT4_I3_5_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_5_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I1 I1=R5_LUT4_I3_29_O_LUT4_I2_O I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_28_O_LUT4_I2_1_O I3=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2 O=L5_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_25_O I1=R5_LUT4_I3_26_O I2=R5_LUT4_I3_27_O I3=R5_LUT4_I3_24_O O=L5_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I1=L5_LUT4_I3_5_I1_LUT4_O_I0 I2=L5_LUT4_I3_5_I2 I3=L5_LUT4_I3_5_I1_LUT4_O_I1 O=L5_LUT4_I3_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_5_I2_LUT4_O_I1 I2=R5_LUT4_I3_29_O_LUT4_I2_O I3=L5_LUT4_I3_5_I2_LUT4_O_I3 O=L5_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_28_O_LUT4_I2_2_O O=L5_LUT4_I3_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_28_O_LUT4_I2_1_O I3=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_25_O I1=R5_LUT4_I3_24_O I2=R5_LUT4_I3_27_O I3=R5_LUT4_I3_26_O O=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_26_O I1=R5_LUT4_I3_25_O I2=R5_LUT4_I3_24_O I3=R5_LUT4_I3_27_O O=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_27_O I1=R5_LUT4_I3_26_O I2=R5_LUT4_I3_25_O I3=R5_LUT4_I3_24_O O=L5_LUT4_I3_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_6_I0 I1=L5_LUT4_I3_6_I1 I2=L5_LUT4_I3_6_I2 I3=L5(31) O=R6_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L5_LUT4_I3_6_I0_LUT4_O_I0 I1=L5_LUT4_I3_6_I0_LUT4_O_I1 I2=L5_LUT4_I1_8_I2_LUT4_O_I2 I3=L5_LUT4_I3_6_I0_LUT4_O_I3 O=L5_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L5_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 I1=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_41_O I3=R5_LUT4_I3_40_O O=L5_LUT4_I3_6_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_41_O_LUT4_I2_O I3=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_38_O I1=R5_LUT4_I3_39_O I2=R5_LUT4_I3_37_O I3=R5_LUT4_I3_36_O O=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_39_O I1=R5_LUT4_I3_37_O I2=R5_LUT4_I3_36_O I3=R5_LUT4_I3_38_O O=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_40_O_LUT4_I2_O O=L5_LUT4_I3_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_40_O_LUT4_I2_1_O I3=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_2_O I1=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3 I2=R5_LUT4_I3_41_O_LUT4_I2_O I3=L5_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_39_O I1=R5_LUT4_I3_38_O I2=R5_LUT4_I3_37_O I3=R5_LUT4_I3_36_O O=L5_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I3=L5_LUT4_I3_6_I1 O=L5_LUT4_I1_8_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_6_I1_LUT4_O_I1 I2=L5_LUT4_I1_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I3=L5_LUT4_I3_6_I1_LUT4_O_I3 O=L5_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L5_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2 I1=R5_LUT4_I3_41_O_LUT4_I2_O I2=R5_LUT4_I3_40_O_LUT4_I2_1_O I3=L5_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_39_O I1=R5_LUT4_I3_38_O I2=R5_LUT4_I3_37_O I3=R5_LUT4_I3_36_O O=L5_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I1_3_I2_LUT4_O_I2 O=L5_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_1_O I1=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I1 I3=R5_LUT4_I3_40_O_LUT4_I2_2_O O=L5_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_41_O_LUT4_I2_O O=L5_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_38_O I1=R5_LUT4_I3_37_O I2=R5_LUT4_I3_39_O I3=R5_LUT4_I3_36_O O=L5_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_6_I2 I2=L5_LUT4_I1_3_I2_LUT4_O_I0 I3=L5_LUT4_I1_8_I3_LUT4_O_I2 O=L5_LUT4_I1_8_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_6_I2_LUT4_O_I2 I3=L5_LUT4_I3_6_I2_LUT4_O_I3 O=L5_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_O I1=L5_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3 I2=R5_LUT4_I3_41_O_LUT4_I2_O I3=L5_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_40_O_LUT4_I2_1_O I1=L5_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_40_O_LUT4_I2_2_O O=L5_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_39_O I1=R5_LUT4_I3_38_O I2=R5_LUT4_I3_36_O I3=R5_LUT4_I3_37_O O=L5_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_39_O I1=R5_LUT4_I3_38_O I2=R5_LUT4_I3_37_O I3=R5_LUT4_I3_36_O O=L5_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L5_LUT4_I3_7_I0 I1=L5_LUT4_I3_7_I1 I2=L5_LUT4_I3_7_I2 I3=L5(32) O=R6_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L5_LUT4_I3_7_I0_LUT4_O_I0 I1=L5_LUT4_I3_2_I1 I2=L5_LUT4_I3_7_I0_LUT4_O_I2 I3=L5_LUT4_I3_7_I0_LUT4_O_I3 O=L5_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2 I3=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3 O=L5_LUT4_I3_7_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_1_O I1=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_O I3=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_47_O I1=R5_LUT4_I3_45_O I2=R5_LUT4_I3_44_O I3=R5_LUT4_I3_46_O O=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_11_I1_LUT4_I3_I0_LUT4_O_I0 I2=R5_LUT4_I3_42_O_LUT4_I2_2_O I3=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_47_O I1=R5_LUT4_I3_46_O I2=R5_LUT4_I3_45_O I3=R5_LUT4_I3_44_O O=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I3=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_42_O_LUT4_I2_1_O O=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_47_O I1=R5_LUT4_I3_45_O I2=R5_LUT4_I3_46_O I3=R5_LUT4_I3_44_O O=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_2_O I1=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_O I3=L5_LUT4_I3_11_I1_LUT4_I3_I0_LUT4_O_I0 O=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_47_O I1=R5_LUT4_I3_44_O I2=R5_LUT4_I3_45_O I3=R5_LUT4_I3_46_O O=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_42_O_LUT4_I2_2_O O=L5_LUT4_I3_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_1_O I3=L5_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_42_O_LUT4_I2_O O=L5_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_44_O I1=R5_LUT4_I3_46_O I2=R5_LUT4_I3_45_O I3=R5_LUT4_I3_47_O O=L5_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_1_O I1=L5_LUT4_I3_2_I2_LUT4_O_I1 I2=L5_LUT4_I3_7_I1_LUT4_O_I2 I3=L5_LUT4_I3_7_I1_LUT4_O_I3 O=L5_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_O I3=L5_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 I2=R5_LUT4_I3_42_O_LUT4_I2_2_O I3=L5_LUT4_I3_11_I1_LUT4_I3_I1_LUT4_O_I1 O=L5_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_45_O I1=R5_LUT4_I3_44_O I2=R5_LUT4_I3_47_O I3=R5_LUT4_I3_46_O O=L5_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_2_O I1=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3 I2=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_42_O_LUT4_I2_O O=L5_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_1_O I3=L5_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_7_I2_LUT4_O_I1 I2=L5_LUT4_I3_7_I2_LUT4_O_I2 I3=L5_LUT4_I3_7_I2_LUT4_O_I3 O=L5_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_11_I2_LUT4_O_I1 O=L5_LUT4_I3_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_43_O_LUT4_I2_O I1=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=R5_LUT4_I3_42_O_LUT4_I2_2_O I3=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I2 O=L5_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_1_O I1=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_O I3=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_42_O_LUT4_I2_O O=L5_LUT4_I3_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_11_I2_LUT4_O_I3_LUT4_O_I3 I3=R5_LUT4_I3_43_O_LUT4_I2_O O=L5_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_42_O_LUT4_I2_2_O I1=L5_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_1_O I3=L5_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I0 I1=L5_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_42_O_LUT4_I2_1_O I3=R5_LUT4_I3_42_O_LUT4_I2_O O=L5_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=R5_LUT4_I3_47_O I1=R5_LUT4_I3_46_O I2=R5_LUT4_I3_45_O I3=R5_LUT4_I3_44_O O=L5_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_46_O I1=R5_LUT4_I3_45_O I2=R5_LUT4_I3_44_O I3=R5_LUT4_I3_47_O O=L5_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L5_LUT4_I3_8_I0 I1=L5_LUT4_I3_8_I1 I2=L5_LUT4_I3_8_I2 I3=L5(4) O=R6_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_8_I0_LUT4_O_I1 I2=L5_LUT4_I3_12_I0 I3=L5_LUT4_I3_8_I0_LUT4_O_I3 O=L5_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0 I1=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I1 I2=R5_LUT4_I3_28_O_LUT4_I2_O I3=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_8_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R5_LUT4_I3_29_O_LUT4_I2_O I1=L5_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0 O=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I2=R5_LUT4_I3_28_O_LUT4_I2_1_O I3=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O I2=L5_LUT4_I3_5_I2_LUT4_O_I3 I3=R5_LUT4_I3_28_O_LUT4_I2_O O=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_26_O I1=R5_LUT4_I3_24_O I2=R5_LUT4_I3_25_O I3=R5_LUT4_I3_27_O O=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_26_O I1=R5_LUT4_I3_25_O I2=R5_LUT4_I3_27_O I3=R5_LUT4_I3_24_O O=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=R5_LUT4_I3_28_O_LUT4_I2_1_O I2=L5_LUT4_I3_12_I2_LUT4_O_I0_LUT4_O_I1 I3=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=L5_LUT4_I3_8_I0_LUT4_O_I1 I1=L5_LUT4_I3_8_I1_LUT4_O_I1 I2=L5_LUT4_I3_8_I0_LUT4_O_I3 I3=L5_LUT4_I3_8_I1_LUT4_O_I3 O=L5_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_28_O_LUT4_I2_1_O O=L5_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_26_O I1=R5_LUT4_I3_27_O I2=R5_LUT4_I3_25_O I3=R5_LUT4_I3_24_O O=L5_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_29_O_LUT4_I2_O I1=L5_LUT4_I3_5_I2_LUT4_O_I1_LUT4_O_I2 I2=R5_LUT4_I3_28_O_LUT4_I2_2_O I3=L5_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_5_I1_LUT4_O_I0 I3=L5_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L5_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L5_LUT4_I3_8_I2_LUT4_O_I0 I1=L5_LUT4_I3_8_I2_LUT4_O_I1 I2=L5_LUT4_I3_8_I2_LUT4_O_I2 I3=L5_LUT4_I3_8_I2_LUT4_O_I3 O=L5_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_12_I1_LUT4_O_I2 I2=L5_LUT4_I3_8_I2_LUT4_O_I1 I3=L5_LUT4_I3_12_I2_LUT4_I1_I3 O=L5_LUT4_I3_8_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_28_O_LUT4_I2_2_O O=L5_LUT4_I3_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_28_O_LUT4_I2_O O=L5_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_1_O I1=L5_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I3 I2=R5_LUT4_I3_29_O_LUT4_I2_O I3=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 O=L5_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_27_O I1=R5_LUT4_I3_26_O I2=R5_LUT4_I3_25_O I3=R5_LUT4_I3_24_O O=L5_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_29_O_LUT4_I2_O I1=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_28_O_LUT4_I2_2_O O=L5_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_27_O I1=R5_LUT4_I3_24_O I2=R5_LUT4_I3_25_O I3=R5_LUT4_I3_26_O O=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_27_O I1=R5_LUT4_I3_25_O I2=R5_LUT4_I3_26_O I3=R5_LUT4_I3_24_O O=L5_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_28_O_LUT4_I2_O I1=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_28_O_LUT4_I2_1_O O=L5_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_27_O I1=R5_LUT4_I3_26_O I2=R5_LUT4_I3_25_O I3=R5_LUT4_I3_24_O O=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2 I1=L5_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 I2=R5_LUT4_I3_28_O I3=R5_LUT4_I3_29_O O=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=R5_LUT4_I3_27_O I1=R5_LUT4_I3_26_O I2=R5_LUT4_I3_25_O I3=R5_LUT4_I3_24_O O=L5_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L5_LUT4_I3_9_I0 I1=L5_LUT4_I3_9_I1 I2=L5_LUT4_I3_9_I2 I3=L5(5) O=R6_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L5_LUT4_I2_I3_LUT4_O_I0 I1=L5_LUT4_I3_9_I0_LUT4_O_I1 I2=L5_LUT4_I3_4_I0_LUT4_I0_O I3=L5_LUT4_I3_9_I0_LUT4_O_I3 O=L5_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2 I3=L5_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3 O=L5_LUT4_I3_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 I2=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1 I3=R5_LUT4_I3_16_O_LUT4_I2_O O=L5_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 O=L5_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L5_LUT4_I3_9_I1_LUT4_O_I0 I1=L5_LUT4_I3_4_I2_LUT4_O_I1 I2=L5_LUT4_I3_9_I1_LUT4_O_I2 I3=L5_LUT4_I3_9_I1_LUT4_O_I3 O=L5_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_9_I1_LUT4_O_I0_LUT4_O_I1 I2=L5_LUT4_I3_9_I1_LUT4_O_I0_LUT4_O_I2 I3=R5_LUT4_I3_16_O_LUT4_I2_1_O O=L5_LUT4_I3_9_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_9_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_17_I2_LUT4_O_I1_LUT4_O_I1 I3=R5_LUT4_I3_16_O_LUT4_I2_O O=L5_LUT4_I3_9_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L5_LUT4_I3_9_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_15_O I1=R5_LUT4_I3_14_O I2=R5_LUT4_I3_13_O I3=R5_LUT4_I3_12_O O=L5_LUT4_I3_9_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=L5_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_16_O_LUT4_I2_2_O O=L5_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_14_O I1=R5_LUT4_I3_13_O I2=R5_LUT4_I3_15_O I3=R5_LUT4_I3_12_O O=L5_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_16_O_LUT4_I2_O I3=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_15_O I1=R5_LUT4_I3_12_O I2=R5_LUT4_I3_13_O I3=R5_LUT4_I3_14_O O=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R5_LUT4_I3_14_O I1=R5_LUT4_I3_13_O I2=R5_LUT4_I3_12_O I3=R5_LUT4_I3_15_O O=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_9_I2_LUT4_I3_I1 I2=L5_LUT4_I3_9_I1_LUT4_O_I0 I3=L5_LUT4_I3_9_I2 O=L5_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111100
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_9_I2_LUT4_O_I1 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_9_I2_LUT4_O_I3 O=L5_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_4_I2_LUT4_O_I3_LUT4_O_I3 I3=R5_LUT4_I3_16_O_LUT4_I2_O O=L5_LUT4_I3_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_I3 I2=R5_LUT4_I3_17_O_LUT4_I2_O I3=L5_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L5_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_9_I2_LUT4_O_I3 I2=R5_LUT4_I3_16_O_LUT4_I2_O I3=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_I3 O=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_15_O I1=R5_LUT4_I3_13_O I2=R5_LUT4_I3_14_O I3=R5_LUT4_I3_12_O O=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O I1=L5_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2 I2=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2 I3=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3 O=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R5_LUT4_I3_16_O_LUT4_I2_1_O I1=L5_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I2=R5_LUT4_I3_16_O_LUT4_I2_O I3=L5_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2 O=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_17_O_LUT4_I2_O I1=L5_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1 I2=R5_LUT4_I3_16_O_LUT4_I2_2_O I3=L5_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L5_LUT4_I3_9_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_15_O I1=R5_LUT4_I3_14_O I2=R5_LUT4_I3_13_O I3=R5_LUT4_I3_12_O O=L5_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L5_LUT4_I3_I0_LUT4_O_I0 I1=L5_LUT4_I3_I0_LUT4_O_I1 I2=L5_LUT4_I3_I0_LUT4_O_I2 I3=L5_LUT4_I3_I0_LUT4_O_I3 O=L5_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1 I2=L5_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2 I3=L5_LUT4_I3_1_I2_LUT4_O_I3 O=L5_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 I2=R5_LUT4_I3_23_O_LUT4_I2_O I3=L5_LUT4_I3_I2_LUT4_O_I2 O=L5_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_1_O I1=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I1 I2=L5_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R5_LUT4_I3_22_O_LUT4_I2_2_O O=L5_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_20_O I1=R5_LUT4_I3_18_O I2=R5_LUT4_I3_19_O I3=R5_LUT4_I3_21_O O=L5_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L5_LUT4_I3_1_I1_LUT4_I0_I2 I3=L5_LUT4_I3_1_I2_LUT4_O_I1 O=L5_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L5_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0 I1=R5_LUT4_I3_23_O_LUT4_I2_O I2=L5_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=L5_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L5_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R5_LUT4_I3_19_O I1=R5_LUT4_I3_20_O I2=R5_LUT4_I3_21_O I3=R5_LUT4_I3_18_O O=L5_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L5_LUT4_I3_1_I1_LUT4_O_I2 I1=R5_LUT4_I3_22_O_LUT4_I2_1_O I2=L5_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I3 I3=L5_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I2 O=L5_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I2=R5_LUT4_I3_22_O_LUT4_I2_2_O I3=L5_LUT4_I3_1_I2_LUT4_O_I0_LUT4_O_I1 O=L5_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_23_O_LUT4_I2_O I1=R5_LUT4_I3_22_O_LUT4_I2_2_O I2=L5_LUT4_I3_I1_LUT4_O_I2 I3=L5_LUT4_I3_I1_LUT4_O_I3 O=L5_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R5_LUT4_I3_21_O I1=R5_LUT4_I3_20_O I2=R5_LUT4_I3_19_O I3=R5_LUT4_I3_18_O O=L5_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I3=R5_LUT4_I3_22_O_LUT4_I2_1_O O=L5_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_22_O_LUT4_I2_2_O O=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_21_O I1=R5_LUT4_I3_20_O I2=R5_LUT4_I3_19_O I3=R5_LUT4_I3_18_O O=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R5_LUT4_I3_21_O I1=R5_LUT4_I3_18_O I2=R5_LUT4_I3_19_O I3=R5_LUT4_I3_20_O O=L5_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_I2 I2=L5_LUT4_I3_I1_LUT4_O_I2 I3=R5_LUT4_I3_22_O_LUT4_I2_2_O O=L5_LUT4_I3_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L5_LUT4_I3_I2_LUT4_O_I1 I2=L5_LUT4_I3_I2_LUT4_O_I2 I3=R5_LUT4_I3_22_O_LUT4_I2_1_O O=L5_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R5_LUT4_I3_22_O_LUT4_I2_O I1=L5_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=L5_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R5_LUT4_I3_23_O_LUT4_I2_O O=L5_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R5_LUT4_I3_20_O I1=R5_LUT4_I3_21_O I2=R5_LUT4_I3_19_O I3=R5_LUT4_I3_18_O O=L5_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R5_LUT4_I3_21_O I1=R5_LUT4_I3_19_O I2=R5_LUT4_I3_18_O I3=R5_LUT4_I3_20_O O=L5_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R5_LUT4_I3_21_O I1=R5_LUT4_I3_20_O I2=R5_LUT4_I3_19_O I3=R5_LUT4_I3_18_O O=L5_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=L5(1) D=R4(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(2) D=R4(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(11) D=R4(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(12) D=R4(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(13) D=R4(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(14) D=R4(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(15) D=R4(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(16) D=R4(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(17) D=R4(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(18) D=R4(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(19) D=R4(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(20) D=R4(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(3) D=R4(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(21) D=R4(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(22) D=R4(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(23) D=R4(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(24) D=R4(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(25) D=R4(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(26) D=R4(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(27) D=R4(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(28) D=R4(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(29) D=R4(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(30) D=R4(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(4) D=R4(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(31) D=R4(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(32) D=R4(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(5) D=R4(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(6) D=R4(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(7) D=R4(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(8) D=R4(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(9) D=R4(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L5(10) D=R4(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:143.1-144.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L6(2) I2=L6_LUT4_I1_I2 I3=L6_LUT4_I1_I3 O=R7_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L6(10) I2=L6_LUT4_I1_1_I2 I3=L6_LUT4_I1_1_I3 O=R7_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I1=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I1_1_I2_LUT4_O_I2 I3=L6_LUT4_I1_1_I2_LUT4_O_I3 O=L6_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I1=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I1_1_I2_LUT4_O_I2 I3=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3 O=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I0 I2=R6_LUT4_I3_10_O_LUT4_I2_2_O I3=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1 I3=R6_LUT4_I3_11_O_LUT4_I2_O O=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_21_I2_LUT4_O_I2 I3=R6_LUT4_I3_10_O_LUT4_I2_O O=L6_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_10_O_LUT4_I2_2_O O=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_1_O I1=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_11_O_LUT4_I2_O O=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_8_O I1=R6_LUT4_I3_9_O I2=R6_LUT4_I3_7_O I3=R6_LUT4_I3_6_O O=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_10_O_LUT4_I2_2_O I3=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_6_O I1=R6_LUT4_I3_8_O I2=R6_LUT4_I3_7_O I3=R6_LUT4_I3_9_O O=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_8_O I1=R6_LUT4_I3_7_O I2=R6_LUT4_I3_6_O I3=R6_LUT4_I3_9_O O=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_1_O I1=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_11_O_LUT4_I2_O I3=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_9_O I1=R6_LUT4_I3_7_O I2=R6_LUT4_I3_8_O I3=R6_LUT4_I3_6_O O=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O I1=L6_LUT4_I1_1_I3_LUT4_O_I1 I2=L6_LUT4_I1_1_I3_LUT4_O_I2 I3=L6_LUT4_I1_1_I3_LUT4_O_I3 O=L6_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I1=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_11_O I3=R6_LUT4_I3_10_O O=L6_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R6_LUT4_I3_9_O I1=R6_LUT4_I3_8_O I2=R6_LUT4_I3_6_O I3=R6_LUT4_I3_7_O O=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_9_O I1=R6_LUT4_I3_8_O I2=R6_LUT4_I3_7_O I3=R6_LUT4_I3_6_O O=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I1_2_I2_LUT4_O_I2 I1=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I1_1_I2_LUT4_O_I3 O=L6_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_21_I2_LUT4_O_I2 I3=R6_LUT4_I3_10_O_LUT4_I2_2_O O=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I3=R6_LUT4_I3_10_O_LUT4_I2_O O=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_1_O I1=L6_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_11_O_LUT4_I2_O I3=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_1_O I1=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_11_O_LUT4_I2_O I3=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 O=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_10_O_LUT4_I2_2_O I3=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_21_I1_LUT4_O_I3 I2=L6_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I1_2_I3_LUT4_O_I0 O=L6_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R6_LUT4_I3_11_O_LUT4_I2_O I3=L6_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L6_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6(1) I2=L6_LUT4_I1_2_I2 I3=L6_LUT4_I1_2_I3 O=R7_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=L6_LUT4_I1_2_I2_LUT4_O_I2 I3=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O O=L6_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_21_I2_LUT4_O_I2 I3=R6_LUT4_I3_11_O_LUT4_I2_O O=L6_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_10_O_LUT4_I2_O O=L6_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_1_O I1=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R6_LUT4_I3_10_O_LUT4_I2_2_O I3=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 O=L6_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_9_O I1=R6_LUT4_I3_6_O I2=R6_LUT4_I3_7_O I3=R6_LUT4_I3_8_O O=L6_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I1_2_I3_LUT4_O_I0 I1=L6_LUT4_I1_2_I3_LUT4_O_I1 I2=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L6_LUT4_I3_21_I1 O=L6_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2 I3=L6_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3 O=L6_LUT4_I1_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_2_O I1=L6_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_11_O_LUT4_I2_O I3=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_8_O I1=R6_LUT4_I3_7_O I2=R6_LUT4_I3_9_O I3=R6_LUT4_I3_6_O O=L6_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_10_O_LUT4_I2_1_O I3=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1 O=L6_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I1_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_1_O I1=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R6_LUT4_I3_11_O_LUT4_I2_O I3=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_9_O I1=R6_LUT4_I3_7_O I2=R6_LUT4_I3_6_O I3=R6_LUT4_I3_8_O O=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1 I3=R6_LUT4_I3_10_O_LUT4_I2_2_O O=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_7_O I1=R6_LUT4_I3_6_O I2=R6_LUT4_I3_9_O I3=R6_LUT4_I3_8_O O=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L6(5) I2=L6_LUT4_I1_3_I2 I3=L6_LUT4_I1_3_I3 O=R7_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=L6_LUT4_I1_5_I2_LUT4_O_I1 I1=L6_LUT4_I1_3_I2_LUT4_O_I1 I2=L6_LUT4_I1_3_I2_LUT4_O_I2 I3=L6_LUT4_I1_3_I2_LUT4_O_I3 O=L6_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I1_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=R6_LUT4_I3_16_O_LUT4_I2_2_O I2=R6_LUT4_I3_16_O_LUT4_I2_1_O I3=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_14_O I1=R6_LUT4_I3_15_O I2=R6_LUT4_I3_13_O I3=R6_LUT4_I3_12_O O=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_O I3=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_15_O I1=R6_LUT4_I3_12_O I2=R6_LUT4_I3_13_O I3=R6_LUT4_I3_14_O O=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_1_O I3=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_14_O I1=R6_LUT4_I3_12_O I2=R6_LUT4_I3_13_O I3=R6_LUT4_I3_15_O O=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_14_O I1=R6_LUT4_I3_13_O I2=R6_LUT4_I3_12_O I3=R6_LUT4_I3_15_O O=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_2_O I3=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_15_O I1=R6_LUT4_I3_13_O I2=R6_LUT4_I3_12_O I3=R6_LUT4_I3_14_O O=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_15_O I1=R6_LUT4_I3_13_O I2=R6_LUT4_I3_14_O I3=R6_LUT4_I3_12_O O=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I1_3_I3_LUT4_O_I0 I1=L6_LUT4_I1_5_I3_LUT4_O_I1 I2=L6_LUT4_I3_22_I1_LUT4_O_I2_LUT4_I1_O I3=L6_LUT4_I1_3_I3_LUT4_O_I3 O=L6_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2 I3=L6_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3 O=L6_LUT4_I1_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_O I1=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_16_O_LUT4_I2_1_O I3=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 I3=R6_LUT4_I3_16_O_LUT4_I2_2_O O=L6_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_15_O I1=R6_LUT4_I3_14_O I2=R6_LUT4_I3_13_O I3=R6_LUT4_I3_12_O O=L6_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L6_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I0 I1=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_I2_O I2=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_16_O_LUT4_I2_O I3=L6_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=L6_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_1_O I1=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_2_O I3=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=L6_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L6(11) I2=L6_LUT4_I1_4_I2 I3=L6_LUT4_I1_4_I3 O=R7_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L6_LUT4_I3_3_I2 I1=L6_LUT4_I1_4_I2_LUT4_O_I1 I2=L6_LUT4_I1_4_I2_LUT4_O_I2 I3=L6_LUT4_I1_4_I2_LUT4_O_I3 O=L6_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_16_I2_LUT4_O_I1 O=L6_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R6_LUT4_I3_29_O_LUT4_I2_O O=L6_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_26_O I1=R6_LUT4_I3_25_O I2=R6_LUT4_I3_24_O I3=R6_LUT4_I3_27_O O=L6_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_2_O I1=L6_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I3=R6_LUT4_I3_28_O_LUT4_I2_1_O O=L6_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_2_O I1=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I1_4_I2_LUT4_O_I2 I3=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_I2_I3 O=L6_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_28_O_LUT4_I2_2_O I3=L6_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_24_O I1=R6_LUT4_I3_26_O I2=R6_LUT4_I3_25_O I3=R6_LUT4_I3_27_O O=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_29_O_LUT4_I2_O I1=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_28_O_LUT4_I2_1_O I3=L6_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_29_O_LUT4_I2_O I1=L6_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_28_O_LUT4_I2_1_O O=L6_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_28_O_LUT4_I2_2_O I3=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I2 O=L6_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_4_I3_LUT4_O_I2 I3=L6_LUT4_I1_4_I3_LUT4_O_I3 O=L6_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_28_O_LUT4_I2_1_O I3=L6_LUT4_I3_3_I2_LUT4_O_I3 O=L6_LUT4_I1_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_28_O_LUT4_I2_2_O I3=L6_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I2 O=L6_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I2=L6_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_29_O_LUT4_I2_O O=L6_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_16_I1_LUT4_O_I2 O=L6_LUT4_I1_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_29_O_LUT4_I2_O I1=L6_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I2=R6_LUT4_I3_28_O_LUT4_I2_2_O I3=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_27_O I1=R6_LUT4_I3_26_O I2=R6_LUT4_I3_24_O I3=R6_LUT4_I3_25_O O=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_28_O_LUT4_I2_1_O I3=L6_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I2 O=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_25_O I1=R6_LUT4_I3_26_O I2=R6_LUT4_I3_27_O I3=R6_LUT4_I3_24_O O=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L6(15) I2=L6_LUT4_I1_5_I2 I3=L6_LUT4_I1_5_I3 O=R7_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_5_I2_LUT4_O_I1 I2=L6_LUT4_I1_5_I2_LUT4_O_I2 I3=L6_LUT4_I1_5_I2_LUT4_O_I3 O=L6_LUT4_I1_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_O I1=L6_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_22_I0_LUT4_O_I2 I3=L6_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I1_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_2_O I1=L6_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_16_O_LUT4_I2_1_O O=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_15_O I1=R6_LUT4_I3_14_O I2=R6_LUT4_I3_13_O I3=R6_LUT4_I3_12_O O=L6_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_1_O I3=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=L6_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I3_22_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=R6_LUT4_I3_16_O_LUT4_I2_2_O I3=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_1_O I3=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 O=L6_LUT4_I1_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_16_O_LUT4_I2_2_O O=L6_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I3_22_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=L6_LUT4_I3_22_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_16_O_LUT4_I2_O O=L6_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 I3=R6_LUT4_I3_17_O_LUT4_I2_O O=L6_LUT4_I1_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_16_O_LUT4_I2_O O=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_1_O I3=L6_LUT4_I3_22_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_15_O I1=R6_LUT4_I3_14_O I2=R6_LUT4_I3_12_O I3=R6_LUT4_I3_13_O O=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_15_O I1=R6_LUT4_I3_14_O I2=R6_LUT4_I3_13_O I3=R6_LUT4_I3_12_O O=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L6_LUT4_I3_22_I1_LUT4_O_I2_LUT4_I1_O I1=L6_LUT4_I1_5_I3_LUT4_O_I1 I2=L6_LUT4_I1_5_I3_LUT4_O_I2 I3=L6_LUT4_I1_5_I3_LUT4_O_I3 O=L6_LUT4_I1_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I1_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_1_O I3=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_16_O_LUT4_I2_O O=L6_LUT4_I1_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_I2_O O=L6_LUT4_I1_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_16_O_LUT4_I2_O I3=L6_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_O I1=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_2_O I3=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_16_O_LUT4_I2_1_O O=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_5_I3_LUT4_O_I3 I3=L6_LUT4_I3_18_I1_LUT4_O_I2 O=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_2_O I1=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_1_O I3=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_13_O I1=R6_LUT4_I3_14_O I2=R6_LUT4_I3_15_O I3=R6_LUT4_I3_12_O O=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_13_O I1=R6_LUT4_I3_12_O I2=R6_LUT4_I3_15_O I3=R6_LUT4_I3_14_O O=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_O I3=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_14_O I1=R6_LUT4_I3_13_O I2=R6_LUT4_I3_15_O I3=R6_LUT4_I3_12_O O=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_12_O I1=R6_LUT4_I3_14_O I2=R6_LUT4_I3_13_O I3=R6_LUT4_I3_15_O O=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L6_LUT4_I1_I2_LUT4_O_I0 I1=L6_LUT4_I1_I2_LUT4_O_I1 I2=R6_LUT4_I3_22_O I3=R6_LUT4_I3_23_O O=L6_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R6_LUT4_I3_21_O I1=R6_LUT4_I3_20_O I2=R6_LUT4_I3_19_O I3=R6_LUT4_I3_18_O O=L6_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R6_LUT4_I3_21_O I1=R6_LUT4_I3_18_O I2=R6_LUT4_I3_19_O I3=R6_LUT4_I3_20_O O=L6_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I1_I3_LUT4_O_I0 I1=L6_LUT4_I2_I3_LUT4_O_I3 I2=L6_LUT4_I1_I3_LUT4_O_I2 I3=L6_LUT4_I1_I3_LUT4_O_I3 O=L6_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L6_LUT4_I3_12_I1_LUT4_O_I1 I2=L6_LUT4_I3_12_I2_LUT4_I1_I0 I3=L6_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_2_O I1=L6_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_22_O_LUT4_I2_1_O I3=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 O=L6_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_21_O I1=R6_LUT4_I3_20_O I2=R6_LUT4_I3_19_O I3=R6_LUT4_I3_18_O O=L6_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6(28) I3=L6_LUT4_I2_I3 O=R7_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L6_LUT4_I2_I3_LUT4_O_I0 I1=L6_LUT4_I2_I3_LUT4_O_I1 I2=L6_LUT4_I2_I3_LUT4_O_I2 I3=L6_LUT4_I2_I3_LUT4_O_I3 O=L6_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L6_LUT4_I3_15_I1_LUT4_O_I2 O=L6_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_2_O I1=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I2 I2=R6_LUT4_I3_22_O_LUT4_I2_O I3=L6_LUT4_I3_15_I1_LUT4_O_I1 O=L6_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I0 I2=R6_LUT4_I3_22_O_LUT4_I2_1_O I3=L6_LUT4_I1_I2_LUT4_O_I0 O=L6_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_12_I1_LUT4_O_I1 I3=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L6_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L6_LUT4_I3_I0 I1=L6_LUT4_I3_I1 I2=L6_LUT4_I3_I2 I3=L6(17) O=R7_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L6_LUT4_I3_1_I0 I1=L6_LUT4_I3_1_I1 I2=L6_LUT4_I3_1_I2 I3=L6(24) O=R7_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L6_LUT4_I3_20_I0 I1=L6_LUT4_I3_10_I1 I2=L6_LUT4_I3_10_I2 I3=L6(9) O=R7_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_10_I1_LUT4_O_I1 I2=L6_LUT4_I3_20_I1_LUT4_O_I1 I3=L6_LUT4_I3_20_I1_LUT4_O_I2 O=L6_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_10_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_40_O_LUT4_I2_2_O I3=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_1_O I1=L6_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I2 I2=L6_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_41_O_LUT4_I2_O O=L6_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_20_I2_LUT4_O_I2 I3=L6_LUT4_I3_I1_LUT4_O_I3 O=L6_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L6_LUT4_I3_24_I0 I1=L6_LUT4_I3_11_I1 I2=L6_LUT4_I3_11_I2 I3=L6(12) O=R7_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L6_LUT4_I3_24_I2 I1=L6_LUT4_I3_8_I1_LUT4_O_I2 I2=L6_LUT4_I3_8_I1_LUT4_O_I1 I3=L6_LUT4_I3_8_I2_LUT4_O_I2 O=L6_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_11_I2_LUT4_O_I1 I2=L6_LUT4_I3_19_I2_LUT4_O_I3 I3=L6_LUT4_I3_24_I0_LUT4_O_I3 O=L6_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I0_LUT4_O_I2 I3=R6_LUT4_I3_46_O_LUT4_I2_1_O O=L6_LUT4_I3_11_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R6_LUT4_I3_46_O_LUT4_I2_2_O O=L6_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_O I1=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_47_O_LUT4_I2_O I3=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_12_I0 I1=L6_LUT4_I3_12_I1 I2=L6_LUT4_I3_12_I2 I3=L6(13) O=R7_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_12_I0_LUT4_O_I1 I2=L6_LUT4_I1_I3_LUT4_O_I2 I3=L6_LUT4_I1_I3_LUT4_O_I0 O=L6_LUT4_I3_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L6_LUT4_I3_12_I0_LUT4_O_I1 O=L6_LUT4_I3_15_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_12_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I2 I2=R6_LUT4_I3_22_O_LUT4_I2_O I3=L6_LUT4_I1_I2_LUT4_O_I0 O=L6_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_2_O I1=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I0 I2=L6_LUT4_I3_15_I1_LUT4_O_I1 I3=R6_LUT4_I3_22_O_LUT4_I2_1_O O=L6_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L6_LUT4_I3_12_I1_LUT4_O_I1 I2=L6_LUT4_I3_12_I1_LUT4_O_I2 I3=L6_LUT4_I3_12_I1_LUT4_O_I3 O=L6_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I2 I2=R6_LUT4_I3_22_O_LUT4_I2_O I3=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_2_O I1=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I1_I2_LUT4_O_I1 I3=R6_LUT4_I3_22_O_LUT4_I2_1_O O=L6_LUT4_I3_12_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_2_O I1=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_22_O_LUT4_I2_1_O I3=L6_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_21_O I1=R6_LUT4_I3_20_O I2=R6_LUT4_I3_19_O I3=R6_LUT4_I3_18_O O=L6_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I1_I2_LUT4_O_I1 I2=R6_LUT4_I3_22_O_LUT4_I2_O I3=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_2_O I1=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_22_O_LUT4_I2_1_O O=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 I3=R6_LUT4_I3_22_O_LUT4_I2_O O=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I3_15_I1_LUT4_O_I1 I3=R6_LUT4_I3_23_O_LUT4_I2_O O=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_21_O I1=R6_LUT4_I3_19_O I2=R6_LUT4_I3_20_O I3=R6_LUT4_I3_18_O O=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_12_I2_LUT4_I1_I0 I1=L6_LUT4_I3_12_I2 I2=L6_LUT4_I3_12_I2_LUT4_I1_I2 I3=L6_LUT4_I3_12_I2_LUT4_I1_I3 O=L6_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_12_I2_LUT4_I1_I0_LUT4_O_I1 I2=L6_LUT4_I1_I2_LUT4_O_I0 I3=R6_LUT4_I3_22_O_LUT4_I2_2_O O=L6_LUT4_I3_12_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=L6_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 I3=R6_LUT4_I3_22_O_LUT4_I2_O O=L6_LUT4_I3_12_I2_LUT4_I1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_2_O I1=L6_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_22_O_LUT4_I2_1_O O=L6_LUT4_I3_12_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2 I2=R6_LUT4_I3_22_O_LUT4_I2_O I3=L6_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I0 O=L6_LUT4_I3_12_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_12_I2_LUT4_O_I2 I3=L6_LUT4_I3_12_I2_LUT4_O_I3 O=L6_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L6_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I0 I1=R6_LUT4_I3_22_O_LUT4_I2_2_O I2=L6_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2 I3=R6_LUT4_I3_22_O_LUT4_I2_O O=L6_LUT4_I3_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_21_O I1=R6_LUT4_I3_20_O I2=R6_LUT4_I3_18_O I3=R6_LUT4_I3_19_O O=L6_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_21_O I1=R6_LUT4_I3_20_O I2=R6_LUT4_I3_19_O I3=R6_LUT4_I3_18_O O=L6_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_22_O_LUT4_I2_1_O I3=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_21_O I1=R6_LUT4_I3_20_O I2=R6_LUT4_I3_19_O I3=R6_LUT4_I3_18_O O=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_20_O I1=R6_LUT4_I3_19_O I2=R6_LUT4_I3_21_O I3=R6_LUT4_I3_18_O O=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_I2_O I1=L6_LUT4_I3_2_I1 I2=L6_LUT4_I3_13_I2 I3=L6(14) O=R7_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L6_LUT4_I3_9_I0_LUT4_O_I3 I1=L6_LUT4_I3_13_I2_LUT4_O_I1 I2=L6_LUT4_I3_13_I2_LUT4_O_I2 I3=L6_LUT4_I3_13_I2_LUT4_O_I3 O=L6_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_O_LUT4_I2_2_O O=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_9_I1_LUT4_O_I2_LUT4_I2_I0 I1=R6_LUT4_I3_O_LUT4_I3_O I2=R6_LUT4_I3_O_LUT4_I2_1_O I3=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I3_O I1=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_O_LUT4_I2_2_O O=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_5_O I1=R6_LUT4_I3_4_O I2=R6_LUT4_I3_3_O I3=R6_LUT4_I3_2_O O=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_O_LUT4_I2_2_O O=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I3_O I1=L6_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_O_LUT4_I2_1_O I3=L6_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_I3_I1 I2=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_I3_I2 I3=L6_LUT4_I3_13_I2_LUT4_O_I2 O=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_O_LUT4_I3_O I3=L6_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_2_O I1=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_O_LUT4_I2_1_O O=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_O_LUT4_I2_2_O I3=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_4_O I1=R6_LUT4_I3_3_O I2=R6_LUT4_I3_2_O I3=R6_LUT4_I3_5_O O=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_5_O I1=R6_LUT4_I3_3_O I2=R6_LUT4_I3_2_O I3=R6_LUT4_I3_4_O O=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I3_O I1=L6_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 I2=R6_LUT4_I3_O_LUT4_I2_1_O I3=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_3_O I1=R6_LUT4_I3_2_O I2=R6_LUT4_I3_5_O I3=R6_LUT4_I3_4_O O=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_13_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I3_O I1=L6_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 I3=R6_LUT4_I3_O_LUT4_I2_2_O O=L6_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_4_O I1=R6_LUT4_I3_2_O I2=R6_LUT4_I3_3_O I3=R6_LUT4_I3_5_O O=L6_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_O_LUT4_I2_1_O O=L6_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_14_I0 I1=L6_LUT4_I3_23_I2 I2=L6_LUT4_I3_14_I2 I3=L6(16) O=R7_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_7_I0_LUT4_O_I3 I2=L6_LUT4_I3_7_I0_LUT4_O_I2 I3=L6_LUT4_I3_23_I0 O=L6_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_O I1=R6_LUT4_I3_34_O_LUT4_I2_2_O I2=L6_LUT4_I3_14_I2_LUT4_O_I2 I3=L6_LUT4_I3_14_I2_LUT4_O_I3 O=L6_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_2_O I1=L6_LUT4_I3_14_I2_LUT4_O_I2 I2=R6_LUT4_I3_34_O_LUT4_I2_O I3=L6_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_14_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_14_I2_LUT4_O_I2_LUT4_I1_O I2=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I0 I3=R6_LUT4_I3_35_O_LUT4_I2_O O=L6_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_33_O I1=R6_LUT4_I3_32_O I2=R6_LUT4_I3_31_O I3=R6_LUT4_I3_30_O O=L6_LUT4_I3_14_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_2_O I1=L6_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_34_O_LUT4_I2_O I3=L6_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I0 O=L6_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_15_I0 I1=L6_LUT4_I3_15_I1 I2=L6_LUT4_I3_15_I2 I3=L6(18) O=R7_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I3_12_I1 I3=L6_LUT4_I3_15_I0_LUT4_O_I3 O=L6_LUT4_I3_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_12_I2_LUT4_I1_I3 I2=L6_LUT4_I3_12_I2_LUT4_I1_I2 I3=L6_LUT4_I3_12_I2_LUT4_I1_I0 O=L6_LUT4_I3_15_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L6_LUT4_I3_15_I1 I1=L6_LUT4_I3_15_I2_LUT4_O_I3 I2=L6_LUT4_I3_15_I1_LUT4_I3_I2 I3=L6_LUT4_I3_15_I1_LUT4_O_I2 O=L6_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_15_I1_LUT4_I3_I1 I2=L6_LUT4_I3_15_I1_LUT4_I3_I2 I3=L6_LUT4_I3_15_I1 O=L6_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I0 I1=R6_LUT4_I3_22_O_LUT4_I2_1_O I2=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I2 I3=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I3 O=L6_LUT4_I3_15_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R6_LUT4_I3_20_O I1=R6_LUT4_I3_19_O I2=R6_LUT4_I3_18_O I3=R6_LUT4_I3_21_O O=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_19_O I1=R6_LUT4_I3_20_O I2=R6_LUT4_I3_21_O I3=R6_LUT4_I3_18_O O=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2 I2=R6_LUT4_I3_22_O_LUT4_I2_2_O I3=L6_LUT4_I1_I2_LUT4_O_I1 O=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_2_O I1=L6_LUT4_I3_15_I1_LUT4_O_I1 I2=L6_LUT4_I3_15_I1_LUT4_O_I2 I3=L6_LUT4_I3_15_I1_LUT4_O_I3 O=L6_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R6_LUT4_I3_18_O I1=R6_LUT4_I3_20_O I2=R6_LUT4_I3_19_O I3=R6_LUT4_I3_21_O O=L6_LUT4_I3_15_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_15_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_1_O I1=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_22_O_LUT4_I2_O I3=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I2 O=L6_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I0 I2=L6_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2 I3=R6_LUT4_I3_22_O_LUT4_I2_2_O O=L6_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I2 I3=R6_LUT4_I3_22_O_LUT4_I2_O O=L6_LUT4_I3_15_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_22_O_LUT4_I2_1_O O=L6_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_19_O I1=R6_LUT4_I3_18_O I2=R6_LUT4_I3_21_O I3=R6_LUT4_I3_20_O O=L6_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_15_I2_LUT4_I3_I1 I2=L6_LUT4_I3_15_I2_LUT4_I3_I2 I3=L6_LUT4_I3_15_I2 O=L6_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_12_I1_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_22_O_LUT4_I2_O O=L6_LUT4_I3_15_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_12_I2_LUT4_O_I2_LUT4_O_I2 I1=R6_LUT4_I3_22_O_LUT4_I2_1_O I2=R6_LUT4_I3_22_O_LUT4_I2_2_O I3=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2 O=L6_LUT4_I3_15_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_15_I2_LUT4_O_I1 I2=L6_LUT4_I3_15_I2_LUT4_O_I2 I3=L6_LUT4_I3_15_I2_LUT4_O_I3 O=L6_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_2_O I1=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_22_O_LUT4_I2_O O=L6_LUT4_I3_15_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_21_O I1=R6_LUT4_I3_19_O I2=R6_LUT4_I3_18_O I3=R6_LUT4_I3_20_O O=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_20_O I1=R6_LUT4_I3_18_O I2=R6_LUT4_I3_19_O I3=R6_LUT4_I3_21_O O=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I2 I3=R6_LUT4_I3_22_O_LUT4_I2_1_O O=L6_LUT4_I3_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_22_O_LUT4_I2_1_O I3=L6_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_20_O I1=R6_LUT4_I3_21_O I2=R6_LUT4_I3_19_O I3=R6_LUT4_I3_18_O O=L6_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_15_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_22_O_LUT4_I2_1_O I1=L6_LUT4_I3_15_I1_LUT4_I3_I1_LUT4_O_I0 I2=R6_LUT4_I3_22_O_LUT4_I2_O I3=L6_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_23_O_LUT4_I2_O I1=L6_LUT4_I3_12_I2_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I3_15_I1_LUT4_O_I3_LUT4_O_I2 I3=R6_LUT4_I3_22_O_LUT4_I2_2_O O=L6_LUT4_I3_15_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_6_I0 I1=L6_LUT4_I3_16_I1 I2=L6_LUT4_I3_16_I2 I3=L6(19) O=R7_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I3_16_I1_LUT4_O_I2 I3=L6_LUT4_I3_6_I0_LUT4_O_I3 O=L6_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_16_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_2_O I1=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I0 I3=R6_LUT4_I3_28_O_LUT4_I2_1_O O=L6_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R6_LUT4_I3_29_O_LUT4_I2_O I3=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I2 O=L6_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_16_I2_LUT4_O_I1 I2=L6_LUT4_I1_4_I2_LUT4_O_I2 I3=L6_LUT4_I3_6_I2_LUT4_O_I0 O=L6_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_16_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I2 I2=L6_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_28_O_LUT4_I2_2_O O=L6_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_29_O_LUT4_I2_O I1=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_28_O_LUT4_I2_1_O I3=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L6_LUT4_I3_16_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O I1=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I3_17_I2 I3=L6(20) O=R7_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L6_LUT4_I3_21_I0_LUT4_O_I2 I1=L6_LUT4_I3_21_I2 I2=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L6_LUT4_I1_2_I3_LUT4_O_I1 O=L6_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L6_LUT4_I3_18_I0 I1=L6_LUT4_I3_18_I1 I2=L6_LUT4_I3_18_I2 I3=L6(21) O=R7_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_5_I3_LUT4_O_I1 I2=L6_LUT4_I1_3_I3_LUT4_O_I0 I3=L6_LUT4_I3_22_I1_LUT4_O_I2_LUT4_I1_O O=L6_LUT4_I3_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_5_I3_LUT4_O_I2 I2=L6_LUT4_I3_18_I1_LUT4_O_I2 I3=L6_LUT4_I3_22_I1_LUT4_O_I2_LUT4_I1_O O=L6_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_18_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_2_O I1=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R6_LUT4_I3_16_O_LUT4_I2_1_O I3=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_O I3=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_5_I2_LUT4_O_I2 I2=L6_LUT4_I3_22_I2_LUT4_O_I3 I3=L6_LUT4_I3_22_I0_LUT4_O_I2 O=L6_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L6_LUT4_I3_24_I0 I1=L6_LUT4_I3_19_I1 I2=L6_LUT4_I3_19_I2 I3=L6(22) O=R7_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L6_LUT4_I3_19_I1_LUT4_O_I0 I1=L6_LUT4_I3_8_I1_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I0 I3=L6_LUT4_I3_8_I1_LUT4_O_I2 O=L6_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L6_LUT4_I3_8_I2_LUT4_O_I2 I1=L6_LUT4_I3_24_I2_LUT4_O_I1 I2=L6_LUT4_I3_19_I1_LUT4_O_I0_LUT4_O_I2 I3=L6_LUT4_I3_19_I1_LUT4_O_I0_LUT4_O_I3 O=L6_LUT4_I3_19_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L6_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I1=R6_LUT4_I3_46_O_LUT4_I2_1_O I2=R6_LUT4_I3_47_O_LUT4_I2_O I3=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_19_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_46_O_LUT4_I2_O I3=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_19_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_24_I0_LUT4_O_I3 I1=L6_LUT4_I3_24_I0_LUT4_O_I1 I2=L6_LUT4_I3_19_I2_LUT4_O_I2 I3=L6_LUT4_I3_19_I2_LUT4_O_I3 O=L6_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I0 I3=R6_LUT4_I3_46_O_LUT4_I2_O O=L6_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_46_O_LUT4_I2_1_O O=L6_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_47_O_LUT4_I2_O O=L6_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I0_LUT4_O_I2 I3=R6_LUT4_I3_47_O_LUT4_I2_O O=L6_LUT4_I3_19_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_46_O_LUT4_I2_2_O O=L6_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_O I1=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_46_O_LUT4_I2_1_O I3=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_O I1=L6_LUT4_I3_1_I0_LUT4_O_I1 I2=L6_LUT4_I3_1_I0_LUT4_O_I2 I3=L6_LUT4_I3_1_I0_LUT4_O_I3 O=L6_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R6_LUT4_I3_32_O I1=R6_LUT4_I3_30_O I2=R6_LUT4_I3_31_O I3=R6_LUT4_I3_33_O O=L6_LUT4_I3_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I0 I1=L6_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_35_O I3=R6_LUT4_I3_34_O O=L6_LUT4_I3_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001100110101
+.subckt LUT4 I0=R6_LUT4_I3_33_O I1=R6_LUT4_I3_31_O I2=R6_LUT4_I3_30_O I3=R6_LUT4_I3_32_O O=L6_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_1_O I1=L6_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I0 I2=L6_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_34_O_LUT4_I2_O O=L6_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_33_O I1=R6_LUT4_I3_30_O I2=R6_LUT4_I3_31_O I3=R6_LUT4_I3_32_O O=L6_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 I3=R6_LUT4_I3_34_O_LUT4_I2_2_O O=L6_LUT4_I3_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 I3=R6_LUT4_I3_34_O_LUT4_I2_1_O O=L6_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_14_I2 I3=L6_LUT4_I3_1_I1_LUT4_O_I3 O=L6_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_7_I2_LUT4_I3_O O=L6_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_34_O_LUT4_I2_1_O O=L6_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_1_I2_LUT4_O_I1 I2=L6_LUT4_I3_1_I2_LUT4_O_I2 I3=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L6_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 I3=R6_LUT4_I3_34_O_LUT4_I2_O O=L6_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I1 I3=R6_LUT4_I3_35_O_LUT4_I2_O O=L6_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I0 I1=R6_LUT4_I3_34_O_LUT4_I2_1_O I2=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=R6_LUT4_I3_32_O I1=R6_LUT4_I3_33_O I2=R6_LUT4_I3_31_O I3=R6_LUT4_I3_30_O O=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R6_LUT4_I3_35_O_LUT4_I2_O O=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_33_O I1=R6_LUT4_I3_32_O I2=R6_LUT4_I3_31_O I3=R6_LUT4_I3_30_O O=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_35_O_LUT4_I2_O I1=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I2 I3=R6_LUT4_I3_34_O_LUT4_I2_1_O O=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I0 I3=R6_LUT4_I3_34_O_LUT4_I2_O O=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_34_O_LUT4_I2_2_O O=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_2_O I1=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I2 I2=R6_LUT4_I3_34_O_LUT4_I2_1_O I3=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_32_O I1=R6_LUT4_I3_31_O I2=R6_LUT4_I3_33_O I3=R6_LUT4_I3_30_O O=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_2_I0 I1=L6_LUT4_I3_2_I1 I2=L6_LUT4_I3_9_I2 I3=L6(25) O=R7_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L6_LUT4_I3_20_I0 I1=L6_LUT4_I3_20_I1 I2=L6_LUT4_I3_20_I2 I3=L6(23) O=R7_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L6_LUT4_I3_I0_LUT4_O_I0 I1=L6_LUT4_I3_I0_LUT4_O_I2 I2=L6_LUT4_I3_20_I0_LUT4_O_I2 I3=L6_LUT4_I3_20_I0_LUT4_O_I3 O=L6_LUT4_I3_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I2 I3=R6_LUT4_I3_40_O_LUT4_I2_2_O O=L6_LUT4_I3_20_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_38_O I1=R6_LUT4_I3_37_O I2=R6_LUT4_I3_36_O I3=R6_LUT4_I3_39_O O=L6_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_37_O I1=R6_LUT4_I3_36_O I2=R6_LUT4_I3_39_O I3=R6_LUT4_I3_38_O O=L6_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_1_O I1=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I2 I3=R6_LUT4_I3_41_O_LUT4_I2_O O=L6_LUT4_I3_20_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_37_O I1=R6_LUT4_I3_38_O I2=R6_LUT4_I3_39_O I3=R6_LUT4_I3_36_O O=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_36_O I1=R6_LUT4_I3_38_O I2=R6_LUT4_I3_37_O I3=R6_LUT4_I3_39_O O=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L6_LUT4_I3_4_I1 I1=L6_LUT4_I3_20_I1_LUT4_O_I1 I2=L6_LUT4_I3_20_I1_LUT4_O_I2 I3=L6_LUT4_I3_20_I1_LUT4_O_I3 O=L6_LUT4_I3_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_20_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_40_O_LUT4_I2_2_O I3=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_1_O I1=L6_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_41_O_LUT4_I2_O I3=L6_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0 O=L6_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_40_O_LUT4_I2_2_O I3=L6_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_40_O_LUT4_I2_O O=L6_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_1_O I1=L6_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_41_O_LUT4_I2_O I3=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_39_O I1=R6_LUT4_I3_38_O I2=R6_LUT4_I3_37_O I3=R6_LUT4_I3_36_O O=L6_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_I0_LUT4_O_I2 I2=L6_LUT4_I3_20_I2_LUT4_O_I2 I3=L6_LUT4_I3_I1_LUT4_O_I2 O=L6_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_1_O I1=L6_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_41_O_LUT4_I2_O O=L6_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I2 I2=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_40_O_LUT4_I2_2_O O=L6_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_21_I0 I1=L6_LUT4_I3_21_I1 I2=L6_LUT4_I3_21_I2 I3=L6(26) O=R7_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O I1=L6_LUT4_I1_1_I3_LUT4_O_I2 I2=L6_LUT4_I3_21_I0_LUT4_O_I2 I3=L6_LUT4_I3_21_I0_LUT4_O_I3 O=L6_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I1_2_I2_LUT4_O_I2 O=L6_LUT4_I3_21_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=L6_LUT4_I3_21_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L6_LUT4_I3_21_I1_LUT4_O_I0 I1=L6_LUT4_I3_21_I1_LUT4_O_I1 I2=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L6_LUT4_I3_21_I1_LUT4_O_I3 O=L6_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I0 I1=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1 I2=R6_LUT4_I3_11_O I3=R6_LUT4_I3_10_O O=L6_LUT4_I3_21_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R6_LUT4_I3_9_O I1=R6_LUT4_I3_8_O I2=R6_LUT4_I3_7_O I3=R6_LUT4_I3_6_O O=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1 I2=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1 I3=R6_LUT4_I3_10_O_LUT4_I2_1_O O=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_2_O I1=L6_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R6_LUT4_I3_11_O_LUT4_I2_O I3=L6_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I0 I3=R6_LUT4_I3_10_O_LUT4_I2_O O=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_10_O_LUT4_I2_2_O I3=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1 O=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_9_O I1=R6_LUT4_I3_8_O I2=R6_LUT4_I3_7_O I3=R6_LUT4_I3_6_O O=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_10_O_LUT4_I2_1_O I3=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_21_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_9_O I1=R6_LUT4_I3_8_O I2=R6_LUT4_I3_7_O I3=R6_LUT4_I3_6_O O=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_1_O I1=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I3 I3=R6_LUT4_I3_11_O_LUT4_I2_O O=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_7_O I1=R6_LUT4_I3_8_O I2=R6_LUT4_I3_9_O I3=R6_LUT4_I3_6_O O=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_21_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_1_O I1=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_11_O_LUT4_I2_O O=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_1_O I1=L6_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R6_LUT4_I3_10_O_LUT4_I2_2_O I3=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=L6_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_10_O_LUT4_I2_O O=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I2=R6_LUT4_I3_11_O_LUT4_I2_O I3=L6_LUT4_I3_21_I1_LUT4_O_I0_LUT4_O_I0 O=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_8_O I1=R6_LUT4_I3_6_O I2=R6_LUT4_I3_7_O I3=R6_LUT4_I3_9_O O=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I3 I2=R6_LUT4_I3_10_O_LUT4_I2_2_O I3=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_21_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_21_I2_LUT4_O_I1 I2=L6_LUT4_I3_21_I2_LUT4_O_I2 I3=R6_LUT4_I3_10_O_LUT4_I2_1_O O=L6_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I3=R6_LUT4_I3_11_O_LUT4_I2_O O=L6_LUT4_I3_21_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_10_O_LUT4_I2_O I1=L6_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_10_O_LUT4_I2_2_O O=L6_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_9_O I1=R6_LUT4_I3_8_O I2=R6_LUT4_I3_7_O I3=R6_LUT4_I3_6_O O=L6_LUT4_I3_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L6_LUT4_I3_22_I0 I1=L6_LUT4_I3_22_I1 I2=L6_LUT4_I3_22_I2 I3=L6(27) O=R7_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_22_I0_LUT4_O_I2 I3=L6_LUT4_I1_5_I2_LUT4_O_I3 O=L6_LUT4_I3_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_22_I0_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_16_O_LUT4_I2_2_O I3=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 O=L6_LUT4_I3_22_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_22_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_22_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_16_O_LUT4_I2_1_O O=L6_LUT4_I3_22_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=R6_LUT4_I3_16_O_LUT4_I2_O I3=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_22_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_15_O I1=R6_LUT4_I3_14_O I2=R6_LUT4_I3_13_O I3=R6_LUT4_I3_12_O O=L6_LUT4_I3_22_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_3_I3_LUT4_O_I0 I2=L6_LUT4_I3_22_I1_LUT4_O_I2 I3=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_I2_O O=L6_LUT4_I3_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_I2_O I1=L6_LUT4_I3_22_I1_LUT4_O_I2 I2=L6_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I0 O=L6_LUT4_I3_22_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_22_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_16_O_LUT4_I2_2_O O=L6_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_16_O_LUT4_I2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I1_5_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_16_O_LUT4_I2_1_O O=L6_LUT4_I3_22_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_3_I2_LUT4_O_I1 I3=L6_LUT4_I3_22_I2_LUT4_O_I3 O=L6_LUT4_I3_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_22_I2_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1 I3=R6_LUT4_I3_16_O_LUT4_I2_1_O O=L6_LUT4_I3_22_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_22_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_22_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_16_O_LUT4_I2_2_O O=L6_LUT4_I3_22_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_17_O_LUT4_I2_O I1=L6_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I3_22_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_16_O_LUT4_I2_O O=L6_LUT4_I3_22_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_15_O I1=R6_LUT4_I3_14_O I2=R6_LUT4_I3_13_O I3=R6_LUT4_I3_12_O O=L6_LUT4_I3_22_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_23_I0 I1=L6_LUT4_I3_23_I1 I2=L6_LUT4_I3_23_I2 I3=L6(30) O=R7_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I3_23_I0_LUT4_O_I2 I3=L6_LUT4_I3_1_I2_LUT4_O_I2 O=L6_LUT4_I3_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_1_O I1=R6_LUT4_I3_35_O_LUT4_I2_O I2=L6_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I3=L6_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_23_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R6_LUT4_I3_35_O_LUT4_I2_O I1=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I2 I2=R6_LUT4_I3_34_O_LUT4_I2_1_O I3=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L6_LUT4_I3_23_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_23_I1_LUT4_O_I1 I2=L6_LUT4_I3_23_I1_LUT4_O_I2 I3=L6_LUT4_I3_1_I1_LUT4_O_I3 O=L6_LUT4_I3_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_2_O I1=L6_LUT4_I3_1_I0_LUT4_O_I1 I2=R6_LUT4_I3_34_O_LUT4_I2_O I3=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I1 O=L6_LUT4_I3_23_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I1=R6_LUT4_I3_35_O_LUT4_I2_O I2=R6_LUT4_I3_34_O_LUT4_I2_1_O I3=L6_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_23_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I1=R6_LUT4_I3_34_O_LUT4_I2_O I2=R6_LUT4_I3_35_O_LUT4_I2_O I3=L6_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_32_O I1=R6_LUT4_I3_31_O I2=R6_LUT4_I3_30_O I3=R6_LUT4_I3_33_O O=L6_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_7_I0_LUT4_O_I1 I2=L6_LUT4_I3_23_I2_LUT4_O_I2 I3=L6_LUT4_I3_23_I2_LUT4_O_I3 O=L6_LUT4_I3_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_1_O I1=R6_LUT4_I3_35_O_LUT4_I2_O I2=L6_LUT4_I3_23_I1_LUT4_O_I2_LUT4_O_I3 I3=L6_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_23_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=L6_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I1=R6_LUT4_I3_34_O_LUT4_I2_1_O I2=R6_LUT4_I3_35_O_LUT4_I2_O I3=L6_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_23_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I1 I1=L6_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_35_O I3=R6_LUT4_I3_34_O O=L6_LUT4_I3_23_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R6_LUT4_I3_33_O I1=R6_LUT4_I3_32_O I2=R6_LUT4_I3_30_O I3=R6_LUT4_I3_31_O O=L6_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L6_LUT4_I3_24_I0 I1=L6_LUT4_I3_24_I1 I2=L6_LUT4_I3_24_I2 I3=L6(32) O=R7_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_24_I0_LUT4_O_I1 I2=L6_LUT4_I3_8_I0_LUT4_O_I3 I3=L6_LUT4_I3_24_I0_LUT4_O_I3 O=L6_LUT4_I3_24_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_1_O I1=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I0 I2=L6_LUT4_I3_8_I0_LUT4_O_I1 I3=L6_LUT4_I3_24_I0_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_24_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_24_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I0_LUT4_O_I2 I3=R6_LUT4_I3_46_O_LUT4_I2_O O=L6_LUT4_I3_24_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_19_I2_LUT4_O_I2 O=L6_LUT4_I3_24_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 I2=R6_LUT4_I3_47_O_LUT4_I2_O I3=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_O I1=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_46_O_LUT4_I2_1_O I3=L6_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_24_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_8_I0_LUT4_O_I2 I2=L6_LUT4_I3_11_I2_LUT4_O_I1 I3=L6_LUT4_I3_24_I0_LUT4_O_I1 O=L6_LUT4_I3_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_24_I2_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I0 I3=L6_LUT4_I3_8_I2 O=L6_LUT4_I3_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_24_I2_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_24_I2_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_24_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2 I2=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_46_O_LUT4_I2_O O=L6_LUT4_I3_24_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_1_O I1=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_47_O_LUT4_I2_O O=L6_LUT4_I3_24_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_I2_O I1=L6_LUT4_I3_9_I1_LUT4_O_I3 I2=L6_LUT4_I3_2_I0_LUT4_O_I2 I3=L6_LUT4_I3_2_I0_LUT4_O_I3 O=L6_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L6_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 I1=R6_LUT4_I3_O_LUT4_I2_1_O I2=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 I2=R6_LUT4_I3_O_LUT4_I3_O I3=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_O_LUT4_I2_1_O I3=L6_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I3_O I1=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_O_LUT4_I2_2_O I3=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_2_I1_LUT4_O_I1 I2=L6_LUT4_I3_9_I1_LUT4_O_I2_LUT4_I2_I0 I3=R6_LUT4_I3_O_LUT4_I2_O O=L6_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_O_LUT4_I3_O O=L6_LUT4_I3_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L6_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 I1=R6_LUT4_I3_O_LUT4_I2_2_O I2=R6_LUT4_I3_O_LUT4_I2_1_O I3=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L6_LUT4_I3_3_I1 I2=L6_LUT4_I3_3_I2 I3=L6(29) O=R7_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L6_LUT4_I3_3_I1_LUT4_O_I0 I1=L6_LUT4_I3_3_I1_LUT4_O_I1 I2=L6_LUT4_I3_3_I1_LUT4_O_I2 I3=L6_LUT4_I3_6_I0_LUT4_O_I1 O=L6_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1 I2=R6_LUT4_I3_28_O_LUT4_I2_2_O I3=L6_LUT4_I3_3_I2_LUT4_O_I3 O=L6_LUT4_I3_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_28_O_LUT4_I2_O O=L6_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_29_O_LUT4_I2_O I1=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I2=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_28_O_LUT4_I2_1_O O=L6_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_26_O I1=R6_LUT4_I3_27_O I2=R6_LUT4_I3_25_O I3=R6_LUT4_I3_24_O O=L6_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_28_O_LUT4_I2_O O=L6_LUT4_I3_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_28_O_LUT4_I2_1_O O=L6_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_29_O_LUT4_I2_O I1=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R6_LUT4_I3_28_O_LUT4_I2_2_O I3=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I0 O=L6_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_27_O I1=R6_LUT4_I3_26_O I2=R6_LUT4_I3_25_O I3=R6_LUT4_I3_24_O O=L6_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3 I2=L6_LUT4_I1_4_I2_LUT4_O_I1 I3=L6_LUT4_I1_4_I3_LUT4_O_I2 O=L6_LUT4_I3_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L6_LUT4_I3_3_I1_LUT4_O_I0 I2=L6_LUT4_I3_3_I2 I3=L6_LUT4_I3_3_I1_LUT4_O_I1 O=L6_LUT4_I3_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_3_I2_LUT4_O_I1 I2=R6_LUT4_I3_29_O_LUT4_I2_O I3=L6_LUT4_I3_3_I2_LUT4_O_I3 O=L6_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_28_O_LUT4_I2_2_O O=L6_LUT4_I3_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I0 I2=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_28_O_LUT4_I2_1_O O=L6_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_27_O I1=R6_LUT4_I3_26_O I2=R6_LUT4_I3_25_O I3=R6_LUT4_I3_24_O O=L6_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_27_O I1=R6_LUT4_I3_26_O I2=R6_LUT4_I3_25_O I3=R6_LUT4_I3_24_O O=L6_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L6_LUT4_I3_4_I0 I1=L6_LUT4_I3_4_I1 I2=L6_LUT4_I3_4_I2 I3=L6(31) O=R7_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L6_LUT4_I3_I0_LUT4_O_I0 I1=L6_LUT4_I3_4_I0_LUT4_O_I1 I2=L6_LUT4_I3_4_I0_LUT4_O_I2 I3=L6_LUT4_I3_I1_LUT4_O_I3 O=L6_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I1=L6_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_41_O I3=R6_LUT4_I3_40_O O=L6_LUT4_I3_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R6_LUT4_I3_39_O I1=R6_LUT4_I3_38_O I2=R6_LUT4_I3_36_O I3=R6_LUT4_I3_37_O O=L6_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=R6_LUT4_I3_40_O_LUT4_I2_2_O O=L6_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=R6_LUT4_I3_40_O_LUT4_I2_1_O O=L6_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_39_O I1=R6_LUT4_I3_38_O I2=R6_LUT4_I3_37_O I3=R6_LUT4_I3_36_O O=L6_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_4_I1_LUT4_O_I1 I2=L6_LUT4_I3_4_I1_LUT4_O_I2 I3=L6_LUT4_I3_I2_LUT4_O_I3 O=L6_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_41_O_LUT4_I2_O O=L6_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0 I2=R6_LUT4_I3_41_O_LUT4_I2_O I3=L6_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L6_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_39_O I1=R6_LUT4_I3_38_O I2=R6_LUT4_I3_37_O I3=R6_LUT4_I3_36_O O=L6_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_1_O I1=L6_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_40_O_LUT4_I2_2_O I3=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_38_O I1=R6_LUT4_I3_36_O I2=R6_LUT4_I3_37_O I3=R6_LUT4_I3_39_O O=L6_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_4_I2 I2=L6_LUT4_I3_I2_LUT4_O_I2 I3=L6_LUT4_I3_20_I1_LUT4_O_I3 O=L6_LUT4_I3_20_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_4_I2_LUT4_O_I2 I3=L6_LUT4_I3_4_I2_LUT4_O_I3 O=L6_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_40_O_LUT4_I2_1_O I3=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_39_O I1=R6_LUT4_I3_37_O I2=R6_LUT4_I3_36_O I3=R6_LUT4_I3_38_O O=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_39_O I1=R6_LUT4_I3_38_O I2=R6_LUT4_I3_37_O I3=R6_LUT4_I3_36_O O=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_41_O_LUT4_I2_O I1=L6_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I2=R6_LUT4_I3_40_O_LUT4_I2_2_O I3=L6_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L6_LUT4_I3_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_5_I0 I1=L6_LUT4_I3_5_I1 I2=L6_LUT4_I3_9_I1 I3=L6(3) O=R7_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_5_I0_LUT4_O_I1 I2=L6_LUT4_I3_9_I0_LUT4_O_I1 I3=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_I2_O O=L6_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1 I2=L6_LUT4_I3_9_I0_LUT4_O_I3 I3=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_5_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_5_I1_LUT4_O_I1 I2=L6_LUT4_I3_5_I1_LUT4_O_I2 I3=L6_LUT4_I3_2_I1 O=L6_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I3_O I1=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_O_LUT4_I2_2_O O=L6_LUT4_I3_5_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_3_O I1=R6_LUT4_I3_4_O I2=R6_LUT4_I3_5_O I3=R6_LUT4_I3_2_O O=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_5_O I1=R6_LUT4_I3_3_O I2=R6_LUT4_I3_4_O I3=R6_LUT4_I3_2_O O=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_2_I1 I1=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_I2_I1 I2=L6_LUT4_I3_5_I1_LUT4_O_I2 I3=L6_LUT4_I3_5_I1_LUT4_O_I1 O=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I1 I2=L6_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_O_LUT4_I2_O O=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 I3=R6_LUT4_I3_O_LUT4_I2_1_O O=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_O_LUT4_I2_1_O I3=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_4_O I1=R6_LUT4_I3_5_O I2=R6_LUT4_I3_3_O I3=R6_LUT4_I3_2_O O=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_5_O I1=R6_LUT4_I3_4_O I2=R6_LUT4_I3_3_O I3=R6_LUT4_I3_2_O O=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L6_LUT4_I3_6_I0 I1=L6_LUT4_I3_6_I1 I2=L6_LUT4_I3_6_I2 I3=L6(4) O=R7_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_6_I0_LUT4_O_I1 I2=L6_LUT4_I1_4_I3 I3=L6_LUT4_I3_6_I0_LUT4_O_I3 O=L6_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I0 I1=R6_LUT4_I3_28_O_LUT4_I2_1_O I2=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R6_LUT4_I3_27_O I1=R6_LUT4_I3_26_O I2=R6_LUT4_I3_25_O I3=R6_LUT4_I3_24_O O=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_27_O I1=R6_LUT4_I3_25_O I2=R6_LUT4_I3_24_O I3=R6_LUT4_I3_26_O O=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=R6_LUT4_I3_28_O_LUT4_I2_O I2=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_2_O I1=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_28_O_LUT4_I2_1_O O=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=L6_LUT4_I3_3_I1_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_29_O_LUT4_I2_O O=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I3_3_I2_LUT4_O_I3 I3=R6_LUT4_I3_28_O_LUT4_I2_O O=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_26_O I1=R6_LUT4_I3_25_O I2=R6_LUT4_I3_27_O I3=R6_LUT4_I3_24_O O=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_27_O I1=R6_LUT4_I3_25_O I2=R6_LUT4_I3_26_O I3=R6_LUT4_I3_24_O O=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_6_I0_LUT4_O_I1 I1=L6_LUT4_I3_6_I1_LUT4_O_I1 I2=L6_LUT4_I3_6_I0_LUT4_O_I3 I3=L6_LUT4_I3_6_I1_LUT4_O_I3 O=L6_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1 I3=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2 O=L6_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_3_I1_LUT4_O_I0 I3=L6_LUT4_I3_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L6_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L6_LUT4_I3_6_I2_LUT4_O_I0 I1=L6_LUT4_I3_6_I2_LUT4_O_I1 I2=L6_LUT4_I3_6_I2_LUT4_O_I2 I3=L6_LUT4_I3_6_I2_LUT4_O_I3 O=L6_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I1_4_I2_LUT4_O_I3 I2=L6_LUT4_I3_6_I2_LUT4_O_I1 I3=L6_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3 O=L6_LUT4_I3_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I2=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_28_O_LUT4_I2_2_O O=L6_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_29_O_LUT4_I2_O I1=L6_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_3_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_28_O_LUT4_I2_1_O O=L6_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_29_O_LUT4_I2_O I1=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2 I3=R6_LUT4_I3_28_O_LUT4_I2_2_O O=L6_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_26_O I1=R6_LUT4_I3_24_O I2=R6_LUT4_I3_25_O I3=R6_LUT4_I3_27_O O=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_27_O I1=R6_LUT4_I3_24_O I2=R6_LUT4_I3_25_O I3=R6_LUT4_I3_26_O O=L6_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_28_O_LUT4_I2_O I1=L6_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_28_O_LUT4_I2_1_O I3=L6_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_25_O I1=R6_LUT4_I3_24_O I2=R6_LUT4_I3_27_O I3=R6_LUT4_I3_26_O O=L6_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 I1=L6_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=R6_LUT4_I3_28_O I3=R6_LUT4_I3_29_O O=L6_LUT4_I1_4_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=R6_LUT4_I3_27_O I1=R6_LUT4_I3_26_O I2=R6_LUT4_I3_25_O I3=R6_LUT4_I3_24_O O=L6_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L6_LUT4_I3_7_I0 I1=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L6_LUT4_I3_7_I2 I3=L6(6) O=R7_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L6_LUT4_I3_7_I0_LUT4_O_I0 I1=L6_LUT4_I3_7_I0_LUT4_O_I1 I2=L6_LUT4_I3_7_I0_LUT4_O_I2 I3=L6_LUT4_I3_7_I0_LUT4_O_I3 O=L6_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=L6_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2 I1=L6_LUT4_I3_1_I0_LUT4_O_I3 I2=L6_LUT4_I3_23_I2_LUT4_O_I2 I3=L6_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3 O=L6_LUT4_I3_7_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L6_LUT4_I3_23_I2_LUT4_O_I3_LUT4_O_I1 I1=R6_LUT4_I3_34_O_LUT4_I2_2_O I2=L6_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_7_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R6_LUT4_I3_35_O_LUT4_I2_O I1=L6_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_34_O_LUT4_I2_O O=L6_LUT4_I3_7_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_33_O I1=R6_LUT4_I3_32_O I2=R6_LUT4_I3_31_O I3=R6_LUT4_I3_30_O O=L6_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R6_LUT4_I3_30_O I1=R6_LUT4_I3_32_O I2=R6_LUT4_I3_31_O I3=R6_LUT4_I3_33_O O=L6_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_7_I2_LUT4_I3_O O=L6_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_2_O I1=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I0 I2=R6_LUT4_I3_34_O_LUT4_I2_O I3=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L6_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_35_O_LUT4_I2_O I1=L6_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I0 I2=R6_LUT4_I3_34_O_LUT4_I2_1_O I3=L6_LUT4_I3_1_I0_LUT4_O_I1 O=L6_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_23_I0_LUT4_O_I2 I2=L6_LUT4_I3_1_I2_LUT4_O_I1 I3=L6_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L6_LUT4_I3_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_7_I2_LUT4_I3_I1 I2=L6_LUT4_I3_7_I2_LUT4_I3_I2 I3=L6_LUT4_I3_7_I2 O=L6_LUT4_I3_7_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_2_O I1=L6_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_35_O_LUT4_I2_O O=L6_LUT4_I3_7_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_1_O I1=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I1 I2=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I2 I3=R6_LUT4_I3_34_O_LUT4_I2_O O=L6_LUT4_I3_7_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_33_O I1=R6_LUT4_I3_32_O I2=R6_LUT4_I3_31_O I3=R6_LUT4_I3_30_O O=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_33_O I1=R6_LUT4_I3_31_O I2=R6_LUT4_I3_32_O I3=R6_LUT4_I3_30_O O=L6_LUT4_I3_7_I2_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_7_I2_LUT4_O_I2 I3=L6_LUT4_I3_7_I2_LUT4_O_I3 O=L6_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_1_O I1=L6_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_34_O_LUT4_I2_O I3=L6_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_31_O I1=R6_LUT4_I3_32_O I2=R6_LUT4_I3_33_O I3=R6_LUT4_I3_30_O O=L6_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_33_O I1=R6_LUT4_I3_32_O I2=R6_LUT4_I3_31_O I3=R6_LUT4_I3_30_O O=L6_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_34_O_LUT4_I2_2_O I1=L6_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_35_O_LUT4_I2_O I3=L6_LUT4_I3_1_I0_LUT4_O_I1 O=L6_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_31_O I1=R6_LUT4_I3_30_O I2=R6_LUT4_I3_33_O I3=R6_LUT4_I3_32_O O=L6_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_8_I0 I1=L6_LUT4_I3_8_I1 I2=L6_LUT4_I3_8_I2 I3=L6(7) O=R7_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_8_I0_LUT4_O_I1 I2=L6_LUT4_I3_8_I0_LUT4_O_I2 I3=L6_LUT4_I3_8_I0_LUT4_O_I3 O=L6_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_8_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_47_O_LUT4_I2_O I3=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_45_O I1=R6_LUT4_I3_43_O I2=R6_LUT4_I3_42_O I3=R6_LUT4_I3_44_O O=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_45_O I1=R6_LUT4_I3_43_O I2=R6_LUT4_I3_44_O I3=R6_LUT4_I3_42_O O=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_O I1=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_46_O_LUT4_I2_1_O I3=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_42_O I1=R6_LUT4_I3_44_O I2=R6_LUT4_I3_43_O I3=R6_LUT4_I3_45_O O=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L6_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I1=R6_LUT4_I3_47_O_LUT4_I2_O I2=R6_LUT4_I3_46_O_LUT4_I2_1_O I3=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_43_O I1=R6_LUT4_I3_42_O I2=R6_LUT4_I3_45_O I3=R6_LUT4_I3_44_O O=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_46_O_LUT4_I2_O I3=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_44_O I1=R6_LUT4_I3_43_O I2=R6_LUT4_I3_45_O I3=R6_LUT4_I3_42_O O=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_45_O I1=R6_LUT4_I3_42_O I2=R6_LUT4_I3_43_O I3=R6_LUT4_I3_44_O O=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_19_I2_LUT4_O_I3 I1=L6_LUT4_I3_11_I2_LUT4_O_I1 I2=L6_LUT4_I3_8_I0_LUT4_O_I2 I3=L6_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_1_O I1=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_47_O_LUT4_I2_O I3=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L6_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_46_O_LUT4_I2_O O=L6_LUT4_I3_8_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_8_I1_LUT4_O_I0 I1=L6_LUT4_I3_8_I1_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I2 I3=L6_LUT4_I3_8_I1_LUT4_O_I3 O=L6_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_8_I1_LUT4_O_I0_LUT4_O_I1 I2=L6_LUT4_I3_8_I1_LUT4_O_I0_LUT4_O_I2 I3=R6_LUT4_I3_46_O_LUT4_I2_2_O O=L6_LUT4_I3_8_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_8_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_46_O_LUT4_I2_1_O O=L6_LUT4_I3_8_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_O I1=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2 I2=R6_LUT4_I3_47_O_LUT4_I2_O I3=L6_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_8_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_43_O I1=R6_LUT4_I3_44_O I2=R6_LUT4_I3_45_O I3=R6_LUT4_I3_42_O O=L6_LUT4_I3_8_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I0 I1=R6_LUT4_I3_46_O_LUT4_I2_2_O I2=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R6_LUT4_I3_45_O I1=R6_LUT4_I3_44_O I2=R6_LUT4_I3_43_O I3=R6_LUT4_I3_42_O O=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R6_LUT4_I3_44_O I1=R6_LUT4_I3_42_O I2=R6_LUT4_I3_43_O I3=R6_LUT4_I3_45_O O=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_O I1=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R6_LUT4_I3_46_O_LUT4_I2_1_O O=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_44_O I1=R6_LUT4_I3_43_O I2=R6_LUT4_I3_42_O I3=R6_LUT4_I3_45_O O=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_O I1=L6_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_46_O_LUT4_I2_1_O I3=L6_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I2 O=L6_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_44_O I1=R6_LUT4_I3_45_O I2=R6_LUT4_I3_43_O I3=R6_LUT4_I3_42_O O=L6_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_47_O_LUT4_I2_O I3=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_45_O I1=R6_LUT4_I3_44_O I2=R6_LUT4_I3_43_O I3=R6_LUT4_I3_42_O O=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R6_LUT4_I3_45_O I1=R6_LUT4_I3_44_O I2=R6_LUT4_I3_43_O I3=R6_LUT4_I3_42_O O=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_8_I2_LUT4_O_I2 I3=L6_LUT4_I3_8_I2_LUT4_O_I3 O=L6_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_O I1=L6_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I0 I2=R6_LUT4_I3_47_O_LUT4_I2_O I3=L6_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_45_O I1=R6_LUT4_I3_44_O I2=R6_LUT4_I3_43_O I3=R6_LUT4_I3_42_O O=L6_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_46_O_LUT4_I2_1_O I3=L6_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L6_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I0 I1=L6_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_46_O_LUT4_I2_2_O I3=R6_LUT4_I3_46_O_LUT4_I2_O O=L6_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=R6_LUT4_I3_46_O_LUT4_I2_2_O I1=L6_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I0 I2=R6_LUT4_I3_47_O_LUT4_I2_O I3=L6_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_24_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_45_O I1=R6_LUT4_I3_44_O I2=R6_LUT4_I3_42_O I3=R6_LUT4_I3_43_O O=L6_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_45_O I1=R6_LUT4_I3_44_O I2=R6_LUT4_I3_43_O I3=R6_LUT4_I3_42_O O=L6_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L6_LUT4_I3_9_I0 I1=L6_LUT4_I3_9_I1 I2=L6_LUT4_I3_9_I2 I3=L6(8) O=R7_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L6_LUT4_I3_9_I0_LUT4_O_I0 I1=L6_LUT4_I3_9_I0_LUT4_O_I1 I2=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_I2_O I3=L6_LUT4_I3_9_I0_LUT4_O_I3 O=L6_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L6_LUT4_I3_13_I2_LUT4_O_I3 I1=L6_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1 I2=L6_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_13_I2_LUT4_O_I1 O=L6_LUT4_I3_9_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 I1=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=L6_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_2_O I1=L6_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R6_LUT4_I3_O_LUT4_I2_1_O O=L6_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R6_LUT4_I3_O_LUT4_I3_O O=L6_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I3_O I1=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2 I3=L6_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_O_LUT4_I2_2_O I3=L6_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_2_O I1=R6_LUT4_I3_4_O I2=R6_LUT4_I3_3_O I3=R6_LUT4_I3_5_O O=L6_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_9_I1_LUT4_O_I1 I2=L6_LUT4_I3_9_I1_LUT4_O_I2 I3=L6_LUT4_I3_9_I1_LUT4_O_I3 O=L6_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I2=R6_LUT4_I3_O_LUT4_I2_1_O I3=L6_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 O=L6_LUT4_I3_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_4_O I1=R6_LUT4_I3_3_O I2=R6_LUT4_I3_5_O I3=R6_LUT4_I3_2_O O=L6_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_9_I1_LUT4_O_I2_LUT4_I2_I0 I1=R6_LUT4_I3_O_LUT4_I2_1_O I2=L6_LUT4_I3_9_I1_LUT4_O_I2 I3=L6_LUT4_I3_9_I1_LUT4_O_I1 O=L6_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R6_LUT4_I3_5_O I1=R6_LUT4_I3_4_O I2=R6_LUT4_I3_3_O I3=R6_LUT4_I3_2_O O=L6_LUT4_I3_9_I1_LUT4_O_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I3_O I1=L6_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 I2=R6_LUT4_I3_O_LUT4_I2_2_O I3=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 O=L6_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_O_LUT4_I2_1_O I3=L6_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_O_LUT4_I2_2_O I3=L6_LUT4_I3_9_I1_LUT4_O_I2_LUT4_I2_I0 O=L6_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I3=R6_LUT4_I3_O_LUT4_I3_O O=L6_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_5_O I1=R6_LUT4_I3_4_O I2=R6_LUT4_I3_3_O I3=R6_LUT4_I3_2_O O=L6_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_2_I0_LUT4_O_I2 I2=L6_LUT4_I3_9_I2 I3=L6_LUT4_I3_9_I1_LUT4_O_I3 O=L6_LUT4_I3_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_9_I2_LUT4_O_I2 I3=L6_LUT4_I3_9_I2_LUT4_O_I3 O=L6_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_O I1=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_O_LUT4_I3_O I3=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_5_O I1=R6_LUT4_I3_4_O I2=R6_LUT4_I3_3_O I3=R6_LUT4_I3_2_O O=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_5_O I1=R6_LUT4_I3_4_O I2=R6_LUT4_I3_2_O I3=R6_LUT4_I3_3_O O=L6_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R6_LUT4_I3_O_LUT4_I2_2_O I1=L6_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I3=R6_LUT4_I3_O_LUT4_I2_1_O O=L6_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_5_O I1=R6_LUT4_I3_2_O I2=R6_LUT4_I3_3_O I3=R6_LUT4_I3_4_O O=L6_LUT4_I3_9_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L6_LUT4_I3_I0_LUT4_O_I0 I1=L6_LUT4_I3_I0_LUT4_O_I1 I2=L6_LUT4_I3_I0_LUT4_O_I2 I3=L6_LUT4_I3_I0_LUT4_O_I3 O=L6_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L6_LUT4_I3_I1_LUT4_O_I3 I1=L6_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1 I2=L6_LUT4_I3_I1_LUT4_O_I2 I3=L6_LUT4_I3_20_I2_LUT4_O_I2 O=L6_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_41_O_LUT4_I2_O I3=L6_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I2 I3=R6_LUT4_I3_40_O_LUT4_I2_2_O O=L6_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L6_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0 I1=L6_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_40_O I3=R6_LUT4_I3_41_O O=L6_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R6_LUT4_I3_39_O I1=R6_LUT4_I3_36_O I2=R6_LUT4_I3_37_O I3=R6_LUT4_I3_38_O O=L6_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_1_O I1=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I2 I2=R6_LUT4_I3_40_O_LUT4_I2_2_O I3=L6_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_41_O_LUT4_I2_O I3=L6_LUT4_I3_20_I0_LUT4_O_I2_LUT4_O_I2 O=L6_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_40_O_LUT4_I2_1_O I3=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_38_O I1=R6_LUT4_I3_37_O I2=R6_LUT4_I3_39_O I3=R6_LUT4_I3_36_O O=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_38_O I1=R6_LUT4_I3_39_O I2=R6_LUT4_I3_37_O I3=R6_LUT4_I3_36_O O=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_I1_LUT4_O_I2 I3=L6_LUT4_I3_I1_LUT4_O_I3 O=L6_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_41_O_LUT4_I2_O I1=L6_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R6_LUT4_I3_40_O_LUT4_I2_2_O I3=L6_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I1 O=L6_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R6_LUT4_I3_39_O I1=R6_LUT4_I3_37_O I2=R6_LUT4_I3_38_O I3=R6_LUT4_I3_36_O O=L6_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_20_I0_LUT4_O_I3_LUT4_O_I2 I2=L6_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1 I3=R6_LUT4_I3_40_O_LUT4_I2_1_O O=L6_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3 I3=R6_LUT4_I3_40_O_LUT4_I2_O O=L6_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L6_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0 I3=R6_LUT4_I3_40_O_LUT4_I2_1_O O=L6_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_41_O_LUT4_I2_O I1=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1 I3=R6_LUT4_I3_40_O_LUT4_I2_2_O O=L6_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L6_LUT4_I3_I2_LUT4_O_I2 I3=L6_LUT4_I3_I2_LUT4_O_I3 O=L6_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_1_O I1=L6_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=L6_LUT4_I3_10_I1_LUT4_O_I1 O=L6_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I3=R6_LUT4_I3_40_O_LUT4_I2_2_O O=L6_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_2_O I1=L6_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L6_LUT4_I3_20_I1_LUT4_O_I1 I3=L6_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R6_LUT4_I3_39_O I1=R6_LUT4_I3_38_O I2=R6_LUT4_I3_37_O I3=R6_LUT4_I3_36_O O=L6_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L6_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R6_LUT4_I3_40_O_LUT4_I2_1_O I3=L6_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3 O=L6_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R6_LUT4_I3_40_O_LUT4_I2_O I1=L6_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1 I2=R6_LUT4_I3_41_O_LUT4_I2_O I3=L6_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L6_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=L6(1) D=R5(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(2) D=R5(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(11) D=R5(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(12) D=R5(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(13) D=R5(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(14) D=R5(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(15) D=R5(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(16) D=R5(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(17) D=R5(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(18) D=R5(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(19) D=R5(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(20) D=R5(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(3) D=R5(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(21) D=R5(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(22) D=R5(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(23) D=R5(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(24) D=R5(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(25) D=R5(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(26) D=R5(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(27) D=R5(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(28) D=R5(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(29) D=R5(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(30) D=R5(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(4) D=R5(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(31) D=R5(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(32) D=R5(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(5) D=R5(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(6) D=R5(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(7) D=R5(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(8) D=R5(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(9) D=R5(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L6(10) D=R5(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:149.1-150.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L7(31) I2=L7_LUT4_I1_I2 I3=L7_LUT4_I1_I3 O=R8_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=K1(1) I1=L7(1) I2=L7_LUT4_I1_1_I2 I3=L7_LUT4_I1_1_I3 O=R8_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I2=L7_LUT4_I1_1_I2_LUT4_O_I2 I3=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=L7_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_1_O O=L7_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_O O=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_2_O I1=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_9_O I1=R7_LUT4_I3_7_O I2=R7_LUT4_I3_8_O I3=R7_LUT4_I3_6_O O=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_9_O I1=R7_LUT4_I3_8_O I2=R7_LUT4_I3_7_O I3=R7_LUT4_I3_6_O O=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I1_1_I3_LUT4_O_I0 I1=L7_LUT4_I1_1_I3_LUT4_O_I1 I2=L7_LUT4_I1_6_I2_LUT4_O_I3 I3=L7_LUT4_I1_1_I3_LUT4_O_I3 O=L7_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I3 O=L7_LUT4_I1_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_O I1=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_11_O_LUT4_I2_O O=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_7_O I1=R7_LUT4_I3_6_O I2=R7_LUT4_I3_9_O I3=R7_LUT4_I3_8_O O=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_9_O I1=R7_LUT4_I3_8_O I2=R7_LUT4_I3_6_O I3=R7_LUT4_I3_7_O O=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_10_O_LUT4_I2_2_O O=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_O I1=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_10_O_LUT4_I2_1_O I3=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_8_O I1=R7_LUT4_I3_7_O I2=R7_LUT4_I3_6_O I3=R7_LUT4_I3_9_O O=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=R7_LUT4_I3_11_O_LUT4_I2_O I2=R7_LUT4_I3_10_O_LUT4_I2_2_O I3=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_8_O I1=R7_LUT4_I3_6_O I2=R7_LUT4_I3_7_O I3=R7_LUT4_I3_9_O O=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_14_I2_LUT4_O_I2 I3=L7_LUT4_I1_6_I2_LUT4_O_I2 O=L7_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L7(4) I2=L7_LUT4_I1_2_I2 I3=L7_LUT4_I1_2_I3 O=R8_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_4_I2_LUT4_O_I1 I2=L7_LUT4_I1_2_I2_LUT4_O_I2 I3=L7_LUT4_I1_2_I2_LUT4_O_I3 O=L7_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_2_O O=L7_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I1=L7_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_28_O_LUT4_I2_O O=L7_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=R7_LUT4_I3_29_O_LUT4_I2_O O=L7_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_27_O I1=R7_LUT4_I3_24_O I2=R7_LUT4_I3_25_O I3=R7_LUT4_I3_26_O O=L7_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I1_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_O I1=L7_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R7_LUT4_I3_28_O_LUT4_I2_2_O I3=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 O=L7_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_29_O_LUT4_I2_O I1=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0 I2=R7_LUT4_I3_28_O_LUT4_I2_1_O I3=L7_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_26_O I1=R7_LUT4_I3_25_O I2=R7_LUT4_I3_24_O I3=R7_LUT4_I3_27_O O=L7_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L7_LUT4_I3_10_I0 I1=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I2=L7_LUT4_I1_2_I3_LUT4_O_I2 I3=L7_LUT4_I3_4_I0 O=L7_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_28_O_LUT4_I2_2_O I3=L7_LUT4_I3_4_I0_LUT4_O_I2 O=L7_LUT4_I1_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_1_O O=L7_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_O I1=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=L7_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_29_O_LUT4_I2_O O=L7_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_24_O I1=R7_LUT4_I3_26_O I2=R7_LUT4_I3_25_O I3=R7_LUT4_I3_27_O O=L7_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L7(18) I2=L7_LUT4_I1_3_I2 I3=L7_LUT4_I1_3_I3 O=R8_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_3_I2_LUT4_O_I1 I2=L7_LUT4_I1_3_I2_LUT4_O_I2 I3=L7_LUT4_I1_3_I2_LUT4_O_I3 O=L7_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I1_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_1_O I1=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_23_O_LUT4_I2_O O=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_19_O I1=R7_LUT4_I3_18_O I2=R7_LUT4_I3_21_O I3=R7_LUT4_I3_20_O O=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I3 I2=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_22_O_LUT4_I2_2_O O=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_18_O I1=R7_LUT4_I3_20_O I2=R7_LUT4_I3_19_O I3=R7_LUT4_I3_21_O O=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I1_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_1_O I1=L7_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I3 I2=R7_LUT4_I3_22_O_LUT4_I2_2_O I3=L7_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 O=L7_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_23_O_LUT4_I2_O I3=L7_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 O=L7_LUT4_I1_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_12_I2_LUT4_O_I3 I3=R7_LUT4_I3_22_O_LUT4_I2_O O=L7_LUT4_I1_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=R7_LUT4_I3_22_O_LUT4_I2_1_O O=L7_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_2_O I1=L7_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I2=R7_LUT4_I3_23_O_LUT4_I2_O I3=L7_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I1 O=L7_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_3_I3_LUT4_O_I1 I2=L7_LUT4_I3_12_I1 I3=L7_LUT4_I1_3_I3_LUT4_O_I3 O=L7_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I1_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_1_O I1=L7_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=L7_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_22_O_LUT4_I2_2_O O=L7_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_23_O_LUT4_I2_O O=L7_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_12_I2_LUT4_I1_I3 I2=L7_LUT4_I3_12_I2_LUT4_I1_I2 I3=L7_LUT4_I3_I2_LUT4_I1_O O=L7_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7(19) I2=L7_LUT4_I1_4_I2 I3=L7_LUT4_I1_4_I3 O=R8_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_4_I2_LUT4_O_I1 I2=L7_LUT4_I1_4_I2_LUT4_O_I2 I3=L7_LUT4_I1_4_I2_LUT4_O_I3 O=L7_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_29_O_LUT4_I2_O O=L7_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R7_LUT4_I3_29_O I3=R7_LUT4_I3_28_O O=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=R7_LUT4_I3_26_O I1=R7_LUT4_I3_24_O I2=R7_LUT4_I3_25_O I3=R7_LUT4_I3_27_O O=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_29_O_LUT4_I2_O I1=L7_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R7_LUT4_I3_28_O_LUT4_I2_2_O I3=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_27_O I1=R7_LUT4_I3_26_O I2=R7_LUT4_I3_24_O I3=R7_LUT4_I3_25_O O=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_27_O I1=R7_LUT4_I3_26_O I2=R7_LUT4_I3_25_O I3=R7_LUT4_I3_24_O O=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I1_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_O I1=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_2_O O=L7_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_29_O_LUT4_I2_O I1=L7_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R7_LUT4_I3_28_O_LUT4_I2_1_O I3=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L7_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I1_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_O I1=L7_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I2=L7_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_2_O O=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_29_O_LUT4_I2_O I1=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_1_O O=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_25_O I1=R7_LUT4_I3_24_O I2=R7_LUT4_I3_27_O I3=R7_LUT4_I3_26_O O=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_26_O I1=R7_LUT4_I3_27_O I2=R7_LUT4_I3_25_O I3=R7_LUT4_I3_24_O O=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_O I1=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=L7_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_29_O_LUT4_I2_O O=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_2_O I1=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_28_O_LUT4_I2_1_O I3=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_4_I0 I3=L7_LUT4_I1_4_I3_LUT4_O_I3 O=L7_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=L7_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I0 I1=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I2=L7_LUT4_I3_10_I0_LUT4_O_I2 I3=L7_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I1_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I1 I1=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_29_O I3=R7_LUT4_I3_28_O O=L7_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_O I1=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R7_LUT4_I3_28_O_LUT4_I2_1_O I3=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7(23) I2=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I3=L7_LUT4_I1_5_I3 O=R8_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=L7_LUT4_I1_5_I3_LUT4_O_I0 I1=L7_LUT4_I1_5_I3_LUT4_O_I1 I2=L7_LUT4_I1_5_I3_LUT4_O_I2 I3=L7_LUT4_I1_5_I3_LUT4_O_I3 O=L7_LUT4_I1_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_I2_LUT4_O_I3 I3=L7_LUT4_I1_I2_LUT4_O_I0 O=L7_LUT4_I1_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L7_LUT4_I1_5_I3_LUT4_O_I2 I1=L7_LUT4_I3_3_I2_LUT4_O_I1 I2=L7_LUT4_I1_I2_LUT4_O_I2 I3=L7_LUT4_I3_3_I2_LUT4_O_I3 O=L7_LUT4_I1_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_40_O_LUT4_I2_1_O I3=L7_LUT4_I3_9_I1_LUT4_O_I2 O=L7_LUT4_I1_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R7_LUT4_I3_40_O_LUT4_I2_O O=L7_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I1=R7_LUT4_I3_40_O_LUT4_I2_2_O I2=R7_LUT4_I3_41_O_LUT4_I2_O I3=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 O=L7_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7(26) I2=L7_LUT4_I1_6_I2 I3=L7_LUT4_I1_6_I3 O=R8_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_6_I2_LUT4_O_I1 I2=L7_LUT4_I1_6_I2_LUT4_O_I2 I3=L7_LUT4_I1_6_I2_LUT4_O_I3 O=L7_LUT4_I1_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_6_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_2_O O=L7_LUT4_I1_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_10_O_LUT4_I2_O O=L7_LUT4_I1_6_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I1_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I1_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_O I1=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_2_O O=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_9_O I1=R7_LUT4_I3_6_O I2=R7_LUT4_I3_7_O I3=R7_LUT4_I3_8_O O=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_9_O I1=R7_LUT4_I3_8_O I2=R7_LUT4_I3_7_O I3=R7_LUT4_I3_6_O O=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_9_O I1=R7_LUT4_I3_8_O I2=R7_LUT4_I3_7_O I3=R7_LUT4_I3_6_O O=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L7_LUT4_I1_1_I3_LUT4_O_I3 I1=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L7_LUT4_I1_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_O O=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_9_O I1=R7_LUT4_I3_8_O I2=R7_LUT4_I3_7_O I3=R7_LUT4_I3_6_O O=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=L7_LUT4_I2_I3_LUT4_O_I2 I2=L7_LUT4_I1_6_I3_LUT4_O_I2 I3=L7_LUT4_I3_14_I1 O=L7_LUT4_I1_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O O=L7_LUT4_I1_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L7_LUT4_I1_I2_LUT4_O_I0 I1=L7_LUT4_I1_I2_LUT4_O_I1 I2=L7_LUT4_I1_I2_LUT4_O_I2 I3=L7_LUT4_I1_I2_LUT4_O_I3 O=L7_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I2=L7_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R7_LUT4_I3_40_O_LUT4_I2_1_O O=L7_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R7_LUT4_I3_40_O_LUT4_I2_2_O I3=L7_LUT4_I3_9_I1_LUT4_O_I2 O=L7_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I2=R7_LUT4_I3_41_O_LUT4_I2_O I3=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_39_O I1=R7_LUT4_I3_38_O I2=R7_LUT4_I3_37_O I3=R7_LUT4_I3_36_O O=L7_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_41_O_LUT4_I2_O O=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_39_O I1=R7_LUT4_I3_38_O I2=R7_LUT4_I3_37_O I3=R7_LUT4_I3_36_O O=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_1_O I1=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 I2=R7_LUT4_I3_40_O_LUT4_I2_2_O I3=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_41_O_LUT4_I2_O I1=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R7_LUT4_I3_40_O_LUT4_I2_2_O I3=L7_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 O=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I3_I2 I3=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I0 I2=R7_LUT4_I3_40_O_LUT4_I2_1_O I3=L7_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_39_O I1=R7_LUT4_I3_37_O I2=R7_LUT4_I3_38_O I3=R7_LUT4_I3_36_O O=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 I2=R7_LUT4_I3_41_O_LUT4_I2_O I3=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0 O=L7_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_1_O I1=L7_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_40_O_LUT4_I2_2_O O=L7_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_39_O I1=R7_LUT4_I3_38_O I2=R7_LUT4_I3_37_O I3=R7_LUT4_I3_36_O O=L7_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_1_O I1=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R7_LUT4_I3_40_O_LUT4_I2_2_O I3=L7_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_38_O I1=R7_LUT4_I3_36_O I2=R7_LUT4_I3_37_O I3=R7_LUT4_I3_39_O O=L7_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I3=R7_LUT4_I3_41_O_LUT4_I2_O O=L7_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I1_I3_LUT4_O_I0 I1=L7_LUT4_I1_I3_LUT4_O_I1 I2=L7_LUT4_I1_I3_LUT4_O_I2 I3=L7_LUT4_I3_9_I1 O=L7_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0 I1=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I2=R7_LUT4_I3_40_O I3=R7_LUT4_I3_41_O O=L7_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_1_O I1=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I0 I2=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0 I3=R7_LUT4_I3_40_O_LUT4_I2_2_O O=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_39_O I1=R7_LUT4_I3_38_O I2=R7_LUT4_I3_37_O I3=R7_LUT4_I3_36_O O=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R7_LUT4_I3_39_O I1=R7_LUT4_I3_38_O I2=R7_LUT4_I3_36_O I3=R7_LUT4_I3_37_O O=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R7_LUT4_I3_40_O_LUT4_I2_2_O I3=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_38_O I1=R7_LUT4_I3_39_O I2=R7_LUT4_I3_37_O I3=R7_LUT4_I3_36_O O=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_39_O I1=R7_LUT4_I3_37_O I2=R7_LUT4_I3_36_O I3=R7_LUT4_I3_38_O O=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0 I1=L7_LUT4_I3_9_I1_LUT4_I0_I1 I2=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I3=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I2 I2=R7_LUT4_I3_41_O I3=R7_LUT4_I3_40_O O=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R7_LUT4_I3_38_O I1=R7_LUT4_I3_37_O I2=R7_LUT4_I3_36_O I3=R7_LUT4_I3_39_O O=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I3=R7_LUT4_I3_40_O_LUT4_I2_1_O O=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_37_O I1=R7_LUT4_I3_36_O I2=R7_LUT4_I3_39_O I3=R7_LUT4_I3_38_O O=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7(10) I3=L7_LUT4_I2_I3 O=R8_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7(14) I3=L7_LUT4_I2_1_I3 O=R8_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L7_LUT4_I2_1_I3_LUT4_O_I0 I1=L7_LUT4_I3_18_I1 I2=L7_LUT4_I2_1_I3_LUT4_O_I2 I3=L7_LUT4_I2_1_I3_LUT4_O_I3 O=L7_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=L7_LUT4_I3_18_I1 I1=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I1 I2=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3 O=L7_LUT4_I2_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 I3=R7_LUT4_I3_4_O_LUT4_I2_O O=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_5_O_LUT4_I2_O O=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_1_O I1=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R7_LUT4_I3_4_O_LUT4_I2_2_O O=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_5_O_LUT4_I2_O I3=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_2_O I1=R7_LUT4_I3_3_O I2=R7_LUT4_I3_1_O I3=R7_LUT4_I3_O O=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_3_O I1=R7_LUT4_I3_2_O I2=R7_LUT4_I3_1_O I3=R7_LUT4_I3_O O=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_1_O I1=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3 I2=R7_LUT4_I3_4_O_LUT4_I2_2_O I3=L7_LUT4_I3_18_I2_LUT4_I2_I1_LUT4_O_I2 O=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3 I1=L7_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 I3=L7_LUT4_I3_8_I1_LUT4_O_I2 O=L7_LUT4_I2_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_2_O I1=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_5_O_LUT4_I2_O I3=L7_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I1 I3=R7_LUT4_I3_4_O_LUT4_I2_1_O O=L7_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I0 I1=R7_LUT4_I3_5_O_LUT4_I2_O I2=L7_LUT4_I3_8_I2_LUT4_O_I1 I3=L7_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R7_LUT4_I3_3_O I1=R7_LUT4_I3_2_O I2=R7_LUT4_I3_1_O I3=R7_LUT4_I3_O O=L7_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_4_O_LUT4_I2_O O=L7_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_1_O I1=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_4_O_LUT4_I2_2_O I3=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7(28) I3=L7_LUT4_I2_2_I3 O=R8_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L7_LUT4_I2_2_I3_LUT4_O_I0 I1=L7_LUT4_I2_2_I3_LUT4_O_I1 I2=L7_LUT4_I3_I0_LUT4_O_I3 I3=L7_LUT4_I3_I0_LUT4_O_I1 O=L7_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000001111111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1 I2=L7_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I1_3_I2_LUT4_O_I3 O=L7_LUT4_I2_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_1_O I1=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_22_O_LUT4_I2_2_O I3=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=L7_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_I1_LUT4_O_I2 I2=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_23_O_LUT4_I2_O O=L7_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I2_I3_LUT4_O_I0 I1=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=L7_LUT4_I2_I3_LUT4_O_I2 I3=L7_LUT4_I2_I3_LUT4_O_I3 O=L7_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L7_LUT4_I1_1_I3_LUT4_O_I3 I1=L7_LUT4_I1_1_I3_LUT4_O_I1 I2=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L7_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_8_O I1=R7_LUT4_I3_9_O I2=R7_LUT4_I3_7_O I3=R7_LUT4_I3_6_O O=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_9_O I1=R7_LUT4_I3_7_O I2=R7_LUT4_I3_6_O I3=R7_LUT4_I3_8_O O=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_O I1=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_2_O O=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_10_O_LUT4_I2_2_O I3=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_6_O I1=R7_LUT4_I3_8_O I2=R7_LUT4_I3_7_O I3=R7_LUT4_I3_9_O O=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=R7_LUT4_I3_10_O_LUT4_I2_1_O I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I3 O=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_O I1=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_2_O O=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_8_O I1=R7_LUT4_I3_7_O I2=R7_LUT4_I3_9_O I3=R7_LUT4_I3_6_O O=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L7_LUT4_I1_1_I2_LUT4_O_I2 I1=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_14_I1_LUT4_O_I2 I3=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_11_O_LUT4_I2_O O=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_O O=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_10_O_LUT4_I2_2_O I3=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_O I1=L7_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R7_LUT4_I3_10_O_LUT4_I2_2_O O=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=L7_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O I1=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I2 I3=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O O=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I2_LUT4_O_I1 I2=R7_LUT4_I3_10_O_LUT4_I2_2_O I3=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_1_O O=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_O I1=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L7_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_11_O_LUT4_I2_O O=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_O O=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_11_O_LUT4_I2_O O=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R7_LUT4_I3_10_O_LUT4_I2_2_O I3=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_I0 I1=L7_LUT4_I3_I1 I2=L7_LUT4_I3_I2 I3=L7(2) O=R8_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L7_LUT4_I3_1_I0 I1=L7_LUT4_I3_1_I1 I2=L7_LUT4_I3_1_I2 I3=L7(6) O=R8_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L7_LUT4_I3_10_I0 I1=L7_LUT4_I3_10_I1 I2=L7_LUT4_I3_10_I2 I3=L7(11) O=R8_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L7_LUT4_I3_10_I0_LUT4_O_I0 I1=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I2=L7_LUT4_I3_10_I0_LUT4_O_I2 I3=L7_LUT4_I3_10_I0_LUT4_O_I3 O=L7_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0 I1=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I1 I2=R7_LUT4_I3_29_O I3=R7_LUT4_I3_28_O O=L7_LUT4_I3_10_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1 I2=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0 I3=R7_LUT4_I3_28_O_LUT4_I2_O O=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=R7_LUT4_I3_28_O_LUT4_I2_1_O I3=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I2 O=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_25_O I1=R7_LUT4_I3_26_O I2=R7_LUT4_I3_27_O I3=R7_LUT4_I3_24_O O=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_27_O I1=R7_LUT4_I3_25_O I2=R7_LUT4_I3_26_O I3=R7_LUT4_I3_24_O O=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_28_O_LUT4_I2_1_O I3=L7_LUT4_I3_4_I0_LUT4_O_I2 O=L7_LUT4_I3_10_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R7_LUT4_I3_28_O_LUT4_I2_2_O I3=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I2 O=L7_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_O I1=L7_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_29_O_LUT4_I2_O O=L7_LUT4_I3_10_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_29_O_LUT4_I2_O I1=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_1_O O=L7_LUT4_I3_10_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_27_O I1=R7_LUT4_I3_25_O I2=R7_LUT4_I3_24_O I3=R7_LUT4_I3_26_O O=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_27_O I1=R7_LUT4_I3_26_O I2=R7_LUT4_I3_25_O I3=R7_LUT4_I3_24_O O=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I1_2_I2_LUT4_O_I3 I3=L7_LUT4_I3_10_I1_LUT4_O_I3 O=L7_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I1_4_I2_LUT4_O_I2 O=L7_LUT4_I3_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_O I1=L7_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L7_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_28_O_LUT4_I2_2_O O=L7_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_29_O_LUT4_I2_O I1=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_1_O O=L7_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_10_I2_LUT4_O_I1 I2=R7_LUT4_I3_29_O_LUT4_I2_O I3=L7_LUT4_I3_4_I0_LUT4_O_I2 O=L7_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_O O=L7_LUT4_I3_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_2_O I1=L7_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R7_LUT4_I3_28_O_LUT4_I2_1_O I3=L7_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=L7_LUT4_I3_10_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_21_I0 I1=L7_LUT4_I3_11_I1 I2=L7_LUT4_I3_11_I2 I3=L7(12) O=R8_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L7_LUT4_I3_21_I2 I1=L7_LUT4_I3_7_I1_LUT4_O_I1 I2=L7_LUT4_I3_7_I2_LUT4_O_I2 I3=L7_LUT4_I3_7_I1_LUT4_O_I2 O=L7_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_11_I2_LUT4_O_I1 I2=L7_LUT4_I3_16_I2_LUT4_O_I3 I3=L7_LUT4_I3_21_I0_LUT4_O_I3 O=L7_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2 I3=R7_LUT4_I3_46_O_LUT4_I2_1_O O=L7_LUT4_I3_11_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_46_O_LUT4_I2_O O=L7_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_47_O_LUT4_I2_O I3=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_11_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_12_I0 I1=L7_LUT4_I3_12_I1 I2=L7_LUT4_I3_12_I2 I3=L7(13) O=R8_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_12_I0_LUT4_O_I1 I2=L7_LUT4_I3_I0_LUT4_O_I2 I3=L7_LUT4_I3_I0_LUT4_O_I0 O=L7_LUT4_I3_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_12_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_22_O_LUT4_I2_2_O I3=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_1_O I1=L7_LUT4_I3_I1_LUT4_O_I2 I2=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_23_O_LUT4_I2_O O=L7_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_12_I2_LUT4_O_I3 I1=R7_LUT4_I3_22_O_LUT4_I2_2_O I2=L7_LUT4_I3_I0_LUT4_O_I3 I3=L7_LUT4_I3_12_I1_LUT4_O_I3 O=L7_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_22_O_LUT4_I2_1_O O=L7_LUT4_I3_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_I2_LUT4_O_I2 I2=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_23_O_LUT4_I2_O O=L7_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_21_O I1=R7_LUT4_I3_19_O I2=R7_LUT4_I3_20_O I3=R7_LUT4_I3_18_O O=L7_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L7_LUT4_I3_I2_LUT4_I1_O I1=L7_LUT4_I3_12_I2 I2=L7_LUT4_I3_12_I2_LUT4_I1_I2 I3=L7_LUT4_I3_12_I2_LUT4_I1_I3 O=L7_LUT4_I2_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_22_O_LUT4_I2_2_O I3=L7_LUT4_I3_I2_LUT4_O_I2 O=L7_LUT4_I3_12_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_1_O I1=L7_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I1 I2=R7_LUT4_I3_23_O_LUT4_I2_O I3=L7_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I3 O=L7_LUT4_I3_12_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_21_O I1=R7_LUT4_I3_20_O I2=R7_LUT4_I3_18_O I3=R7_LUT4_I3_19_O O=L7_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_20_O I1=R7_LUT4_I3_18_O I2=R7_LUT4_I3_19_O I3=R7_LUT4_I3_21_O O=L7_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_12_I2_LUT4_O_I1 I2=R7_LUT4_I3_23_O_LUT4_I2_O I3=L7_LUT4_I3_12_I2_LUT4_O_I3 O=L7_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_22_O_LUT4_I2_1_O O=L7_LUT4_I3_12_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I1 I3=R7_LUT4_I3_22_O_LUT4_I2_2_O O=L7_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_21_O I1=R7_LUT4_I3_20_O I2=R7_LUT4_I3_19_O I3=R7_LUT4_I3_18_O O=L7_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_21_O I1=R7_LUT4_I3_20_O I2=R7_LUT4_I3_19_O I3=R7_LUT4_I3_18_O O=L7_LUT4_I3_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L7_LUT4_I3_13_I0 I1=L7_LUT4_I3_20_I2 I2=L7_LUT4_I3_13_I2 I3=L7(16) O=R8_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L7_LUT4_I3_13_I0_LUT4_O_I0 I1=L7_LUT4_I3_17_I1 I2=L7_LUT4_I3_13_I0_LUT4_O_I2 I3=L7_LUT4_I3_1_I2 O=L7_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_20_I2_LUT4_O_I2 O=L7_LUT4_I3_13_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_2_O I3=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=L7_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_O I1=L7_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I3 I2=R7_LUT4_I3_34_O_LUT4_I2_1_O I3=L7_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_13_I2_LUT4_O_I2 I3=L7_LUT4_I3_20_I1 O=L7_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_1_O I1=R7_LUT4_I3_34_O_LUT4_I2_O I2=L7_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_2_O I1=L7_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_1_O I3=L7_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2 O=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_33_O I1=R7_LUT4_I3_32_O I2=R7_LUT4_I3_31_O I3=R7_LUT4_I3_30_O O=L7_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_O I1=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=L7_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_34_O_LUT4_I2_1_O O=L7_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_14_I0 I1=L7_LUT4_I3_14_I1 I2=L7_LUT4_I3_14_I2 I3=L7(20) O=R8_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=L7_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=L7_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_14_I1_LUT4_O_I2 I3=L7_LUT4_I1_1_I2_LUT4_O_I2 O=L7_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_14_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L7_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R7_LUT4_I3_10_O_LUT4_I2_2_O O=L7_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_7_O I1=R7_LUT4_I3_8_O I2=R7_LUT4_I3_9_O I3=R7_LUT4_I3_6_O O=L7_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_O I1=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_14_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_1_I3_LUT4_O_I0 I2=L7_LUT4_I3_14_I2_LUT4_O_I2 I3=L7_LUT4_I1_6_I2_LUT4_O_I1 O=L7_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_14_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_1_O I1=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_2_O I1=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_11_O_LUT4_I2_O I3=L7_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=R7_LUT4_I3_10_O_LUT4_I2_1_O O=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O I2=L7_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R7_LUT4_I3_10_O_LUT4_I2_O O=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_9_O I1=R7_LUT4_I3_8_O I2=R7_LUT4_I3_7_O I3=R7_LUT4_I3_6_O O=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R7_LUT4_I3_10_O_LUT4_I2_O I1=L7_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=R7_LUT4_I3_10_O_LUT4_I2_2_O I3=L7_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_6_I0 I1=L7_LUT4_I3_15_I1 I2=L7_LUT4_I3_15_I2 I3=L7(21) O=R8_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L7_LUT4_I3_6_I0_LUT4_O_I0 I1=L7_LUT4_I3_2_I2 I2=L7_LUT4_I3_19_I1_LUT4_O_I2 I3=L7_LUT4_I3_2_I1_LUT4_O_I0 O=L7_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I0_LUT4_O_I2 I3=L7_LUT4_I3_19_I2_LUT4_O_I3 O=L7_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L7_LUT4_I3_21_I0 I1=L7_LUT4_I3_16_I1 I2=L7_LUT4_I3_16_I2 I3=L7(22) O=R8_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L7_LUT4_I3_16_I1_LUT4_O_I0 I1=L7_LUT4_I3_7_I1_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I0 I3=L7_LUT4_I3_7_I1_LUT4_O_I2 O=L7_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L7_LUT4_I3_7_I2_LUT4_O_I2 I1=L7_LUT4_I3_21_I2_LUT4_O_I1 I2=L7_LUT4_I3_16_I1_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I3_16_I1_LUT4_O_I0_LUT4_O_I3 O=L7_LUT4_I3_16_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I1=R7_LUT4_I3_46_O_LUT4_I2_1_O I2=R7_LUT4_I3_46_O_LUT4_I2_2_O I3=L7_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_16_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_O I1=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_47_O_LUT4_I2_O I3=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_16_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_21_I0_LUT4_O_I3 I1=L7_LUT4_I3_21_I0_LUT4_O_I1 I2=L7_LUT4_I3_16_I2_LUT4_O_I2 I3=L7_LUT4_I3_16_I2_LUT4_O_I3 O=L7_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I0 I3=R7_LUT4_I3_46_O_LUT4_I2_O O=L7_LUT4_I3_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R7_LUT4_I3_46_O_LUT4_I2_1_O O=L7_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I3=R7_LUT4_I3_47_O_LUT4_I2_O O=L7_LUT4_I3_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2 I3=R7_LUT4_I3_47_O_LUT4_I2_O O=L7_LUT4_I3_16_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R7_LUT4_I3_46_O_LUT4_I2_2_O O=L7_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_O I1=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_46_O_LUT4_I2_1_O I3=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_17_I0 I1=L7_LUT4_I3_17_I1 I2=L7_LUT4_I3_17_I2 I3=L7(24) O=R8_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L7_LUT4_I3_1_I0_LUT4_O_I0 I1=L7_LUT4_I3_1_I0_LUT4_O_I2 I2=L7_LUT4_I3_20_I1_LUT4_O_I2 I3=L7_LUT4_I3_17_I0_LUT4_O_I3 O=L7_LUT4_I3_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_13_I2_LUT4_O_I2 I2=L7_LUT4_I3_13_I0_LUT4_O_I0 I3=L7_LUT4_I3_20_I0_LUT4_O_I3 O=L7_LUT4_I3_17_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_17_I1_LUT4_O_I1 I2=L7_LUT4_I3_17_I1_LUT4_O_I2 I3=R7_LUT4_I3_34_O_LUT4_I2_O O=L7_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_34_O_LUT4_I2_1_O O=L7_LUT4_I3_17_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_17_I1_LUT4_O_I2_LUT4_I3_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_2_O I3=L7_LUT4_I3_17_I1_LUT4_O_I2 O=L7_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_33_O I1=R7_LUT4_I3_32_O I2=R7_LUT4_I3_30_O I3=R7_LUT4_I3_31_O O=L7_LUT4_I3_17_I1_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_33_O I1=R7_LUT4_I3_32_O I2=R7_LUT4_I3_31_O I3=R7_LUT4_I3_30_O O=L7_LUT4_I3_17_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_2_O I1=R7_LUT4_I3_35_O_LUT4_I2_O I2=L7_LUT4_I3_17_I2_LUT4_O_I2 I3=L7_LUT4_I3_17_I2_LUT4_O_I3 O=L7_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_17_I2_LUT4_O_I2 I2=L7_LUT4_I3_1_I1_LUT4_I1_I3_LUT4_O_I1 I3=R7_LUT4_I3_34_O_LUT4_I2_2_O O=L7_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_O I1=L7_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_2_O I3=L7_LUT4_I3_17_I2_LUT4_O_I2 O=L7_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_31_O I1=R7_LUT4_I3_30_O I2=R7_LUT4_I3_33_O I3=R7_LUT4_I3_32_O O=L7_LUT4_I3_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_2_O I3=L7_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_17_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_30_O I1=R7_LUT4_I3_32_O I2=R7_LUT4_I3_31_O I3=R7_LUT4_I3_33_O O=L7_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_32_O I1=R7_LUT4_I3_31_O I2=R7_LUT4_I3_30_O I3=R7_LUT4_I3_33_O O=L7_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L7_LUT4_I3_18_I0 I1=L7_LUT4_I3_18_I1 I2=L7_LUT4_I3_18_I2 I3=L7(25) O=R8_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L7_LUT4_I3_5_I1_LUT4_O_I3 I1=L7_LUT4_I3_18_I0_LUT4_O_I1 I2=L7_LUT4_I2_1_I3_LUT4_O_I0 I3=L7_LUT4_I3_8_I0_LUT4_O_I2 O=L7_LUT4_I3_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_8_I1_LUT4_O_I3 I3=L7_LUT4_I3_5_I1_LUT4_O_I2 O=L7_LUT4_I3_18_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_18_I1_LUT4_O_I1 I2=L7_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I0 I3=R7_LUT4_I3_4_O_LUT4_I2_O O=L7_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 I3=R7_LUT4_I3_4_O_LUT4_I2_1_O O=L7_LUT4_I3_18_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_2_O I1=L7_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_5_O_LUT4_I2_O I3=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_18_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_18_I2_LUT4_I2_I1 I2=L7_LUT4_I3_18_I2 I3=L7_LUT4_I3_8_I2_LUT4_O_I3 O=L7_LUT4_I3_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L7_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 I1=R7_LUT4_I3_5_O_LUT4_I2_O I2=L7_LUT4_I3_18_I2_LUT4_I2_I1_LUT4_O_I2 I3=L7_LUT4_I3_18_I2_LUT4_I2_I1_LUT4_O_I3 O=L7_LUT4_I3_18_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R7_LUT4_I3_3_O I1=R7_LUT4_I3_1_O I2=R7_LUT4_I3_2_O I3=R7_LUT4_I3_O O=L7_LUT4_I3_18_I2_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_4_O_LUT4_I2_1_O I3=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_18_I2_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_18_I2_LUT4_O_I2 I3=L7_LUT4_I3_18_I2_LUT4_O_I3 O=L7_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_4_O_LUT4_I2_1_O I3=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_18_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_3_O I1=R7_LUT4_I3_2_O I2=R7_LUT4_I3_1_O I3=R7_LUT4_I3_O O=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_3_O I1=R7_LUT4_I3_2_O I2=R7_LUT4_I3_O I3=R7_LUT4_I3_1_O O=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_2_O I1=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_5_O_LUT4_I2_O I3=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_18_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_3_O I1=R7_LUT4_I3_O I2=R7_LUT4_I3_1_O I3=R7_LUT4_I3_2_O O=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_1_O I1=R7_LUT4_I3_2_O I2=R7_LUT4_I3_3_O I3=R7_LUT4_I3_O O=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L7_LUT4_I3_6_I0 I1=L7_LUT4_I3_19_I1 I2=L7_LUT4_I3_19_I2 I3=L7(27) O=R8_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L7_LUT4_I3_6_I1_LUT4_O_I1 I1=L7_LUT4_I3_6_I0_LUT4_O_I2 I2=L7_LUT4_I3_19_I1_LUT4_O_I2 I3=L7_LUT4_I3_6_I0_LUT4_O_I1 O=L7_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I3=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 O=L7_LUT4_I3_19_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_2_I0_LUT4_O_I1 I2=L7_LUT4_I3_19_I2_LUT4_O_I2 I3=L7_LUT4_I3_19_I2_LUT4_O_I3 O=L7_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_17_O_LUT4_I2_O O=L7_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_16_O_LUT4_I2_2_O O=L7_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R7_LUT4_I3_16_O_LUT4_I2_1_O O=L7_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_1_O I1=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2 I2=L7_LUT4_I3_2_I0_LUT4_O_I3 I3=L7_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_19_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R7_LUT4_I3_16_O_LUT4_I2_O O=L7_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_17_O_LUT4_I2_O I1=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_16_O_LUT4_I2_2_O I3=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_1_I0_LUT4_O_I0 I1=L7_LUT4_I3_1_I0_LUT4_O_I1 I2=L7_LUT4_I3_1_I0_LUT4_O_I2 I3=L7_LUT4_I3_13_I0 O=L7_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000011111111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I1 I2=L7_LUT4_I3_17_I1_LUT4_O_I2 I3=R7_LUT4_I3_34_O_LUT4_I2_1_O O=L7_LUT4_I3_1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 I3=R7_LUT4_I3_34_O_LUT4_I2_O O=L7_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0 I1=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_20_I1_LUT4_O_I3 I3=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_O I3=L7_LUT4_I3_17_I1_LUT4_O_I2_LUT4_I3_I1 O=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=R7_LUT4_I3_34_O_LUT4_I2_2_O I2=R7_LUT4_I3_35_O_LUT4_I2_O I3=L7_LUT4_I3_1_I2_LUT4_O_I3 O=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001101011111
+.subckt LUT4 I0=R7_LUT4_I3_33_O I1=R7_LUT4_I3_32_O I2=R7_LUT4_I3_31_O I3=R7_LUT4_I3_30_O O=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_17_I1_LUT4_O_I2_LUT4_I3_I1 I2=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_34_O_LUT4_I2_O O=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=R7_LUT4_I3_33_O I1=R7_LUT4_I3_32_O I2=R7_LUT4_I3_31_O I3=R7_LUT4_I3_30_O O=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I1=R7_LUT4_I3_34_O_LUT4_I2_O I2=L7_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_35_O I3=R7_LUT4_I3_34_O O=L7_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001100110101
+.subckt LUT4 I0=L7_LUT4_I3_1_I1_LUT4_I1_I0 I1=L7_LUT4_I3_1_I1 I2=L7_LUT4_I3_1_I1_LUT4_I1_I2 I3=L7_LUT4_I3_1_I1_LUT4_I1_I3 O=L7_LUT4_I3_20_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_1_I1_LUT4_I1_I0_LUT4_O_I2 I3=L7_LUT4_I3_1_I1_LUT4_I1_I0_LUT4_O_I3 O=L7_LUT4_I3_1_I1_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_1_I1_LUT4_I1_I3_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_O I3=L7_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 O=L7_LUT4_I3_1_I1_LUT4_I1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2 I2=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 I3=R7_LUT4_I3_34_O_LUT4_I2_2_O O=L7_LUT4_I3_1_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_O I1=L7_LUT4_I3_1_I1_LUT4_I1_I3_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_1_O I3=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_1_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_32_O I1=R7_LUT4_I3_33_O I2=R7_LUT4_I3_31_O I3=R7_LUT4_I3_30_O O=L7_LUT4_I3_1_I1_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_1_I1 I3=L7_LUT4_I3_1_I1_LUT4_I1_I0 O=L7_LUT4_I3_13_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_1_I1_LUT4_O_I2 I3=L7_LUT4_I3_1_I1_LUT4_O_I3 O=L7_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_O I3=L7_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_2_O I1=L7_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_1_O I3=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I3_1_I1_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_31_O I1=R7_LUT4_I3_32_O I2=R7_LUT4_I3_33_O I3=R7_LUT4_I3_30_O O=L7_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_34_O_LUT4_I2_2_O I3=L7_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I3_1_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_32_O I1=R7_LUT4_I3_30_O I2=R7_LUT4_I3_31_O I3=R7_LUT4_I3_33_O O=L7_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_2_O I1=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_1_O I3=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_33_O I1=R7_LUT4_I3_30_O I2=R7_LUT4_I3_31_O I3=R7_LUT4_I3_32_O O=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_33_O I1=R7_LUT4_I3_31_O I2=R7_LUT4_I3_32_O I3=R7_LUT4_I3_30_O O=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_1_I2_LUT4_O_I1 I2=R7_LUT4_I3_34_O_LUT4_I2_1_O I3=L7_LUT4_I3_1_I2_LUT4_O_I3 O=L7_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_35_O_LUT4_I2_O O=L7_LUT4_I3_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_32_O I1=R7_LUT4_I3_31_O I2=R7_LUT4_I3_33_O I3=R7_LUT4_I3_30_O O=L7_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_33_O I1=R7_LUT4_I3_32_O I2=R7_LUT4_I3_31_O I3=R7_LUT4_I3_30_O O=L7_LUT4_I3_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L7_LUT4_I3_2_I0 I1=L7_LUT4_I3_2_I1 I2=L7_LUT4_I3_2_I2 I3=L7(15) O=R8_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=L7_LUT4_I3_20_I0 I1=L7_LUT4_I3_20_I1 I2=L7_LUT4_I3_20_I2 I3=L7(30) O=R8_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_20_I0_LUT4_O_I2 I3=L7_LUT4_I3_20_I0_LUT4_O_I3 O=L7_LUT4_I3_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0 I2=L7_LUT4_I3_1_I2_LUT4_O_I3 I3=R7_LUT4_I3_35_O_LUT4_I2_O O=L7_LUT4_I3_20_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_20_I1_LUT4_O_I2 I3=L7_LUT4_I3_20_I1_LUT4_O_I3 O=L7_LUT4_I3_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_20_I1_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_1_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_20_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L7_LUT4_I3_1_I2_LUT4_O_I3 I1=R7_LUT4_I3_34_O_LUT4_I2_O I2=R7_LUT4_I3_34_O_LUT4_I2_1_O I3=L7_LUT4_I3_1_I1_LUT4_I1_I3_LUT4_O_I1 O=L7_LUT4_I3_20_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_2_O I1=R7_LUT4_I3_35_O_LUT4_I2_O I2=L7_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R7_LUT4_I3_33_O I1=R7_LUT4_I3_31_O I2=R7_LUT4_I3_30_O I3=R7_LUT4_I3_32_O O=L7_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I3 I2=R7_LUT4_I3_34_O_LUT4_I2_2_O I3=L7_LUT4_I3_17_I1_LUT4_O_I2_LUT4_I3_I1 O=L7_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_20_I2_LUT4_O_I2 I3=L7_LUT4_I3_17_I2 O=L7_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_34_O_LUT4_I2_2_O I1=R7_LUT4_I3_35_O_LUT4_I2_O I2=L7_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I1 I3=L7_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R7_LUT4_I3_35_O_LUT4_I2_O I1=L7_LUT4_I3_17_I2_LUT4_O_I3_LUT4_O_I3 I2=L7_LUT4_I3_1_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_34_O_LUT4_I2_2_O O=L7_LUT4_I3_20_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_21_I0 I1=L7_LUT4_I3_21_I1 I2=L7_LUT4_I3_21_I2 I3=L7(32) O=R8_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_21_I0_LUT4_O_I1 I2=L7_LUT4_I3_7_I0_LUT4_O_I3 I3=L7_LUT4_I3_21_I0_LUT4_O_I3 O=L7_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_1_O I1=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I0 I2=L7_LUT4_I3_7_I0_LUT4_O_I1 I3=L7_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_21_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2 I3=R7_LUT4_I3_46_O_LUT4_I2_O O=L7_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_16_I2_LUT4_O_I2 O=L7_LUT4_I3_21_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 I2=R7_LUT4_I3_47_O_LUT4_I2_O I3=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_O I1=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_46_O_LUT4_I2_1_O I3=L7_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_21_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_7_I0_LUT4_O_I2 I2=L7_LUT4_I3_11_I2_LUT4_O_I1 I3=L7_LUT4_I3_21_I0_LUT4_O_I1 O=L7_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_21_I2_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I0 I3=L7_LUT4_I3_7_I2 O=L7_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_21_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_1_O I1=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R7_LUT4_I3_47_O_LUT4_I2_O O=L7_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2 I2=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 I3=R7_LUT4_I3_46_O_LUT4_I2_O O=L7_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_2_I0_LUT4_O_I0 I1=L7_LUT4_I3_2_I0_LUT4_O_I1 I2=L7_LUT4_I3_2_I0_LUT4_O_I2 I3=L7_LUT4_I3_2_I0_LUT4_O_I3 O=L7_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1 I2=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2 I3=R7_LUT4_I3_16_O_LUT4_I2_2_O O=L7_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_16_O_LUT4_I2_O O=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_17_O_LUT4_I2_O I1=L7_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_16_O_LUT4_I2_1_O O=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2 I2=R7_LUT4_I3_17_O_LUT4_I2_O I3=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_15_O I1=R7_LUT4_I3_14_O I2=R7_LUT4_I3_13_O I3=R7_LUT4_I3_12_O O=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_17_O_LUT4_I2_O I1=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_16_O_LUT4_I2_2_O I3=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_16_O_LUT4_I2_1_O I3=L7_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_13_O I1=R7_LUT4_I3_12_O I2=R7_LUT4_I3_15_O I3=R7_LUT4_I3_14_O O=L7_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_2_O I1=L7_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_16_O_LUT4_I2_1_O O=L7_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_17_O_LUT4_I2_O I3=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_17_O_LUT4_I2_O I3=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_13_O I1=R7_LUT4_I3_14_O I2=R7_LUT4_I3_15_O I3=R7_LUT4_I3_12_O O=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_15_O I1=R7_LUT4_I3_13_O I2=R7_LUT4_I3_12_O I3=R7_LUT4_I3_14_O O=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_2_O I1=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_16_O_LUT4_I2_1_O I3=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_12_O I1=R7_LUT4_I3_14_O I2=R7_LUT4_I3_13_O I3=R7_LUT4_I3_15_O O=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_15_O I1=R7_LUT4_I3_14_O I2=R7_LUT4_I3_13_O I3=R7_LUT4_I3_12_O O=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L7_LUT4_I3_2_I1_LUT4_O_I0 I1=L7_LUT4_I3_6_I0_LUT4_O_I2 I2=L7_LUT4_I3_6_I0_LUT4_O_I0 I3=L7_LUT4_I3_6_I1_LUT4_O_I0 O=L7_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I3 O=L7_LUT4_I3_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_2_O I1=L7_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_16_O_LUT4_I2_1_O I3=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_15_O I1=R7_LUT4_I3_14_O I2=R7_LUT4_I3_13_O I3=R7_LUT4_I3_12_O O=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I0 I2=R7_LUT4_I3_17_O_LUT4_I2_O I3=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_15_O I1=R7_LUT4_I3_12_O I2=R7_LUT4_I3_13_O I3=R7_LUT4_I3_14_O O=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I2 I3=L7_LUT4_I3_2_I1_LUT4_O_I0 O=L7_LUT4_I3_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I2_LUT4_O_I2 I3=L7_LUT4_I3_2_I2_LUT4_O_I3 O=L7_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I0 I1=R7_LUT4_I3_16_O_LUT4_I2_2_O I2=R7_LUT4_I3_16_O_LUT4_I2_1_O I3=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_15_O I1=R7_LUT4_I3_14_O I2=R7_LUT4_I3_13_O I3=R7_LUT4_I3_12_O O=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_15_O I1=R7_LUT4_I3_14_O I2=R7_LUT4_I3_13_O I3=R7_LUT4_I3_12_O O=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I2=L7_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_17_O_LUT4_I2_O O=L7_LUT4_I3_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_14_O I1=R7_LUT4_I3_12_O I2=R7_LUT4_I3_13_O I3=R7_LUT4_I3_15_O O=L7_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L7_LUT4_I3_3_I0 I1=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I2=L7_LUT4_I3_3_I2 I3=L7(17) O=R8_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L7_LUT4_I3_3_I0_LUT4_O_I0 I1=L7_LUT4_I3_3_I0_LUT4_O_I1 I2=L7_LUT4_I3_9_I2_LUT4_O_I2 I3=L7_LUT4_I1_I3_LUT4_O_I2 O=L7_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L7_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I1=L7_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I2=R7_LUT4_I3_40_O I3=R7_LUT4_I3_41_O O=L7_LUT4_I3_3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R7_LUT4_I3_38_O I1=R7_LUT4_I3_37_O I2=R7_LUT4_I3_39_O I3=R7_LUT4_I3_36_O O=L7_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_1_O I1=L7_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_40_O_LUT4_I2_2_O I3=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 O=L7_LUT4_I3_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I1_I2_LUT4_O_I0 I1=L7_LUT4_I3_3_I2_LUT4_O_I1 I2=L7_LUT4_I1_I2_LUT4_O_I1 I3=L7_LUT4_I3_3_I2_LUT4_O_I3 O=L7_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_9_I0_LUT4_O_I1 I2=L7_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R7_LUT4_I3_40_O_LUT4_I2_2_O O=L7_LUT4_I3_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_40_O_LUT4_I2_O O=L7_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_1_O I1=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_41_O_LUT4_I2_O I3=L7_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_39_O I1=R7_LUT4_I3_36_O I2=R7_LUT4_I3_37_O I3=R7_LUT4_I3_38_O O=L7_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L7_LUT4_I3_4_I0 I1=L7_LUT4_I3_4_I1 I2=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I3=L7(29) O=R8_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_4_I0_LUT4_O_I1 I2=L7_LUT4_I3_4_I0_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_O O=L7_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_29_O_LUT4_I2_O O=L7_LUT4_I3_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_28_O_LUT4_I2_2_O I1=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I1 I3=R7_LUT4_I3_28_O_LUT4_I2_1_O O=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_26_O I1=R7_LUT4_I3_25_O I2=R7_LUT4_I3_27_O I3=R7_LUT4_I3_24_O O=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_27_O I1=R7_LUT4_I3_26_O I2=R7_LUT4_I3_25_O I3=R7_LUT4_I3_24_O O=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_27_O I1=R7_LUT4_I3_26_O I2=R7_LUT4_I3_25_O I3=R7_LUT4_I3_24_O O=L7_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I3_4_I1_LUT4_O_I0 I1=L7_LUT4_I3_4_I1_LUT4_O_I1 I2=L7_LUT4_I1_2_I3_LUT4_O_I2 I3=L7_LUT4_I1_4_I3_LUT4_O_I3 O=L7_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=L7_LUT4_I1_2_I2_LUT4_O_I3 I1=L7_LUT4_I1_4_I2_LUT4_O_I1 I2=L7_LUT4_I3_10_I1_LUT4_O_I3 I3=L7_LUT4_I1_4_I2_LUT4_O_I3 O=L7_LUT4_I3_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_O O=L7_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_28_O_LUT4_I2_1_O O=L7_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_29_O_LUT4_I2_O I1=L7_LUT4_I3_10_I0_LUT4_O_I0_LUT4_O_I1 I2=R7_LUT4_I3_28_O_LUT4_I2_2_O I3=L7_LUT4_I3_10_I0_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_27_O I1=R7_LUT4_I3_26_O I2=R7_LUT4_I3_25_O I3=R7_LUT4_I3_24_O O=L7_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L7_LUT4_I3_8_I0 I1=L7_LUT4_I3_5_I1 I2=L7_LUT4_I3_5_I2 I3=L7(3) O=R8_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_5_I1_LUT4_O_I2 I3=L7_LUT4_I3_5_I1_LUT4_O_I3 O=L7_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_2_O I1=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_5_O_LUT4_I2_O O=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_4_O_LUT4_I2_1_O I3=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_3_O I1=R7_LUT4_I3_1_O I2=R7_LUT4_I3_O I3=R7_LUT4_I3_2_O O=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_O I1=R7_LUT4_I3_2_O I2=R7_LUT4_I3_1_O I3=R7_LUT4_I3_3_O O=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=R7_LUT4_I3_4_O_LUT4_I2_2_O I3=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_1_O I1=L7_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_5_O_LUT4_I2_O I3=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_5_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_1_O I1=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R7_LUT4_I3_5_O_LUT4_I2_O O=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_4_O_LUT4_I2_2_O O=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_3_O I1=R7_LUT4_I3_2_O I2=R7_LUT4_I3_1_O I3=R7_LUT4_I3_O O=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_4_O_LUT4_I2_1_O I3=L7_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I0 O=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I1 I3=R7_LUT4_I3_4_O_LUT4_I2_O O=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_2_O I1=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_5_O_LUT4_I2_O I3=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_8_I2_LUT4_O_I1 I2=L7_LUT4_I3_8_I2_LUT4_O_I3 I3=L7_LUT4_I3_5_I2_LUT4_O_I3 O=L7_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3 I2=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I3_18_I1 O=L7_LUT4_I3_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L7_LUT4_I3_6_I0 I1=L7_LUT4_I3_6_I1 I2=L7_LUT4_I3_6_I2 I3=L7(5) O=R8_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L7_LUT4_I3_6_I0_LUT4_O_I0 I1=L7_LUT4_I3_6_I0_LUT4_O_I1 I2=L7_LUT4_I3_6_I0_LUT4_O_I2 I3=L7_LUT4_I3_6_I0_LUT4_O_I3 O=L7_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 I1=L7_LUT4_I3_6_I1_LUT4_O_I1 I2=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O O=L7_LUT4_I3_6_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 I2=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I1_O I3=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R7_LUT4_I3_17_O_LUT4_I2_O I1=L7_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_16_O_LUT4_I2_1_O I3=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I0 I1=R7_LUT4_I3_17_O_LUT4_I2_O I2=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_16_O_LUT4_I2_2_O I3=L7_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_2_O I1=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_16_O_LUT4_I2_1_O I3=L7_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=R7_LUT4_I3_17_O_LUT4_I2_O I3=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I0 O=L7_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_16_O_LUT4_I2_2_O O=L7_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_17_O_LUT4_I2_O I1=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_16_O_LUT4_I2_1_O O=L7_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_14_O I1=R7_LUT4_I3_13_O I2=R7_LUT4_I3_15_O I3=R7_LUT4_I3_12_O O=L7_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L7_LUT4_I3_6_I1_LUT4_O_I0 I1=L7_LUT4_I3_6_I1_LUT4_O_I1 I2=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I3=L7_LUT4_I3_6_I1_LUT4_O_I3 O=L7_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I2=L7_LUT4_I3_6_I0_LUT4_O_I0_LUT4_O_I0 I3=L7_LUT4_I3_6_I0_LUT4_O_I1 O=L7_LUT4_I3_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_16_O_LUT4_I2_1_O O=L7_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=R7_LUT4_I3_16_O_LUT4_I2_2_O I2=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=R7_LUT4_I3_15_O I1=R7_LUT4_I3_14_O I2=R7_LUT4_I3_12_O I3=R7_LUT4_I3_13_O O=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R7_LUT4_I3_16_O_LUT4_I2_O O=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_14_O I1=R7_LUT4_I3_15_O I2=R7_LUT4_I3_13_O I3=R7_LUT4_I3_12_O O=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_6_I1_LUT4_O_I3 I2=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_16_O_LUT4_I2_2_O O=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_2_O I1=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_16_O_LUT4_I2_1_O O=L7_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_14_O I1=R7_LUT4_I3_13_O I2=R7_LUT4_I3_12_O I3=R7_LUT4_I3_15_O O=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_15_O I1=R7_LUT4_I3_13_O I2=R7_LUT4_I3_14_O I3=R7_LUT4_I3_12_O O=L7_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_2_I0_LUT4_O_I0 I3=L7_LUT4_I3_6_I2_LUT4_O_I3 O=L7_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L7_LUT4_I3_19_I2_LUT4_O_I2 I1=L7_LUT4_I3_2_I0_LUT4_O_I3 I2=L7_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R7_LUT4_I3_16_O_LUT4_I2_O I1=L7_LUT4_I3_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_16_O_LUT4_I2_2_O I3=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_17_O_LUT4_I2_O I1=L7_LUT4_I3_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_16_O_LUT4_I2_1_O I3=L7_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=L7_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_7_I0 I1=L7_LUT4_I3_7_I1 I2=L7_LUT4_I3_7_I2 I3=L7(7) O=R8_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_7_I0_LUT4_O_I1 I2=L7_LUT4_I3_7_I0_LUT4_O_I2 I3=L7_LUT4_I3_7_I0_LUT4_O_I3 O=L7_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_7_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_47_O_LUT4_I2_O I3=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_45_O I1=R7_LUT4_I3_43_O I2=R7_LUT4_I3_42_O I3=R7_LUT4_I3_44_O O=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_45_O I1=R7_LUT4_I3_43_O I2=R7_LUT4_I3_44_O I3=R7_LUT4_I3_42_O O=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_O I1=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_46_O_LUT4_I2_1_O I3=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_42_O I1=R7_LUT4_I3_44_O I2=R7_LUT4_I3_43_O I3=R7_LUT4_I3_45_O O=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L7_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I1=R7_LUT4_I3_47_O_LUT4_I2_O I2=R7_LUT4_I3_46_O_LUT4_I2_1_O I3=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_43_O I1=R7_LUT4_I3_42_O I2=R7_LUT4_I3_45_O I3=R7_LUT4_I3_44_O O=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_46_O_LUT4_I2_O I3=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_44_O I1=R7_LUT4_I3_43_O I2=R7_LUT4_I3_45_O I3=R7_LUT4_I3_42_O O=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_45_O I1=R7_LUT4_I3_42_O I2=R7_LUT4_I3_43_O I3=R7_LUT4_I3_44_O O=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L7_LUT4_I3_16_I2_LUT4_O_I3 I1=L7_LUT4_I3_11_I2_LUT4_O_I1 I2=L7_LUT4_I3_7_I0_LUT4_O_I2 I3=L7_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_1_O I1=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_47_O_LUT4_I2_O I3=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_46_O_LUT4_I2_O O=L7_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_7_I1_LUT4_O_I0 I1=L7_LUT4_I3_7_I1_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I2 I3=L7_LUT4_I3_7_I1_LUT4_O_I3 O=L7_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1 I2=L7_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2 I3=R7_LUT4_I3_46_O_LUT4_I2_2_O O=L7_LUT4_I3_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_7_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R7_LUT4_I3_46_O_LUT4_I2_1_O O=L7_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_O I1=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2 I2=R7_LUT4_I3_47_O_LUT4_I2_O I3=L7_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_43_O I1=R7_LUT4_I3_44_O I2=R7_LUT4_I3_45_O I3=R7_LUT4_I3_42_O O=L7_LUT4_I3_7_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I0 I1=R7_LUT4_I3_46_O_LUT4_I2_2_O I2=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R7_LUT4_I3_45_O I1=R7_LUT4_I3_44_O I2=R7_LUT4_I3_43_O I3=R7_LUT4_I3_42_O O=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R7_LUT4_I3_44_O I1=R7_LUT4_I3_42_O I2=R7_LUT4_I3_43_O I3=R7_LUT4_I3_45_O O=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_O I1=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_46_O_LUT4_I2_1_O O=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_44_O I1=R7_LUT4_I3_43_O I2=R7_LUT4_I3_42_O I3=R7_LUT4_I3_45_O O=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_O I1=L7_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_46_O_LUT4_I2_1_O I3=L7_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I2 O=L7_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_44_O I1=R7_LUT4_I3_45_O I2=R7_LUT4_I3_43_O I3=R7_LUT4_I3_42_O O=L7_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_47_O_LUT4_I2_O I3=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_45_O I1=R7_LUT4_I3_44_O I2=R7_LUT4_I3_43_O I3=R7_LUT4_I3_42_O O=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_45_O I1=R7_LUT4_I3_44_O I2=R7_LUT4_I3_43_O I3=R7_LUT4_I3_42_O O=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_7_I2_LUT4_O_I2 I3=L7_LUT4_I3_7_I2_LUT4_O_I3 O=L7_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_O I1=L7_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I0 I2=R7_LUT4_I3_47_O_LUT4_I2_O I3=L7_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_45_O I1=R7_LUT4_I3_44_O I2=R7_LUT4_I3_43_O I3=R7_LUT4_I3_42_O O=L7_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_46_O_LUT4_I2_1_O I3=L7_LUT4_I3_7_I1_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I0 I1=L7_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_46_O_LUT4_I2_2_O I3=R7_LUT4_I3_46_O_LUT4_I2_O O=L7_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=R7_LUT4_I3_46_O_LUT4_I2_2_O I1=L7_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I0 I2=R7_LUT4_I3_47_O_LUT4_I2_O I3=L7_LUT4_I3_7_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_21_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_45_O I1=R7_LUT4_I3_44_O I2=R7_LUT4_I3_42_O I3=R7_LUT4_I3_43_O O=L7_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_45_O I1=R7_LUT4_I3_44_O I2=R7_LUT4_I3_43_O I3=R7_LUT4_I3_42_O O=L7_LUT4_I3_7_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L7_LUT4_I3_8_I0 I1=L7_LUT4_I3_8_I1 I2=L7_LUT4_I3_8_I2 I3=L7(8) O=R8_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I2_1_I3_LUT4_O_I3 I2=L7_LUT4_I3_8_I0_LUT4_O_I2 I3=L7_LUT4_I2_1_I3_LUT4_O_I0 O=L7_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_8_I1_LUT4_O_I2 I3=L7_LUT4_I3_8_I1_LUT4_O_I3 O=L7_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_4_O_LUT4_I2_2_O O=L7_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_1_O I1=L7_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I1 I3=R7_LUT4_I3_5_O_LUT4_I2_O O=L7_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_2_O I1=R7_LUT4_I3_O I2=R7_LUT4_I3_1_O I3=R7_LUT4_I3_3_O O=L7_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_18_I2_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_4_O_LUT4_I2_1_O I3=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_2_O I1=R7_LUT4_I3_1_O I2=R7_LUT4_I3_O I3=R7_LUT4_I3_3_O O=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_2_O I1=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=R7_LUT4_I3_5_O_LUT4_I2_O O=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_1_O I1=R7_LUT4_I3_O I2=R7_LUT4_I3_3_O I3=R7_LUT4_I3_2_O O=L7_LUT4_I3_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_8_I2_LUT4_O_I1 I2=L7_LUT4_I3_18_I2 I3=L7_LUT4_I3_8_I2_LUT4_O_I3 O=L7_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_1_O I1=L7_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_5_O_LUT4_I2_O I3=L7_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_2_O I1=R7_LUT4_I3_1_O I2=R7_LUT4_I3_3_O I3=R7_LUT4_I3_O O=L7_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_18_I2_LUT4_I2_I1_LUT4_O_I2 I2=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3 I3=R7_LUT4_I3_4_O_LUT4_I2_2_O O=L7_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_5_O_LUT4_I2_O I3=L7_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R7_LUT4_I3_4_O_LUT4_I2_2_O I3=L7_LUT4_I2_1_I3_LUT4_O_I3_LUT4_O_I0 O=L7_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_4_O_LUT4_I2_O I1=L7_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3 I2=R7_LUT4_I3_4_O_LUT4_I2_1_O I3=L7_LUT4_I3_18_I2_LUT4_I2_I1_LUT4_O_I2 O=L7_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_3_O I1=R7_LUT4_I3_2_O I2=R7_LUT4_I3_1_O I3=R7_LUT4_I3_O O=L7_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L7_LUT4_I3_9_I0 I1=L7_LUT4_I3_9_I1 I2=L7_LUT4_I3_9_I2 I3=L7(9) O=R8_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110001110011
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_9_I0_LUT4_O_I1 I2=L7_LUT4_I1_I2_LUT4_O_I1 I3=L7_LUT4_I1_5_I3_LUT4_O_I1 O=L7_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R7_LUT4_I3_40_O_LUT4_I2_1_O I3=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I2 O=L7_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_41_O_LUT4_I2_O I1=L7_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_40_O_LUT4_I2_2_O I3=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_9_I1 I1=L7_LUT4_I3_9_I1_LUT4_I0_I1 I2=L7_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I3=L7_LUT4_I3_9_I1_LUT4_I0_I3 O=L7_LUT4_I1_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_9_I1_LUT4_I0_I1_LUT4_O_I1 I2=R7_LUT4_I3_41_O_LUT4_I2_O I3=L7_LUT4_I3_9_I1_LUT4_O_I2 O=L7_LUT4_I3_9_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I2 I3=R7_LUT4_I3_40_O_LUT4_I2_O O=L7_LUT4_I3_9_I1_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I0 I1=R7_LUT4_I3_40_O_LUT4_I2_2_O I2=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I2 I3=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I3 O=L7_LUT4_I3_9_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R7_LUT4_I3_36_O I1=R7_LUT4_I3_38_O I2=R7_LUT4_I3_37_O I3=R7_LUT4_I3_39_O O=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_37_O I1=R7_LUT4_I3_38_O I2=R7_LUT4_I3_39_O I3=R7_LUT4_I3_36_O O=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=R7_LUT4_I3_40_O_LUT4_I2_1_O I3=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_9_I1_LUT4_O_I1 I2=L7_LUT4_I3_9_I1_LUT4_O_I2 I3=R7_LUT4_I3_40_O_LUT4_I2_O O=L7_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1 I2=R7_LUT4_I3_40_O_LUT4_I2_1_O I3=L7_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 O=L7_LUT4_I3_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_41_O_LUT4_I2_O I1=L7_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 I2=R7_LUT4_I3_40_O_LUT4_I2_2_O I3=L7_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 O=L7_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_39_O I1=R7_LUT4_I3_38_O I2=R7_LUT4_I3_37_O I3=R7_LUT4_I3_36_O O=L7_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_9_I2_LUT4_O_I2 I3=L7_LUT4_I1_5_I3_LUT4_O_I3 O=L7_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I3=L7_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 O=L7_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_O I1=L7_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R7_LUT4_I3_41_O_LUT4_I2_O I3=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L7_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_40_O_LUT4_I2_1_O I1=L7_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=L7_LUT4_I3_9_I1_LUT4_I0_I3_LUT4_O_I0 I3=R7_LUT4_I3_40_O_LUT4_I2_2_O O=L7_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_I0_LUT4_O_I0 I1=L7_LUT4_I3_I0_LUT4_O_I1 I2=L7_LUT4_I3_I0_LUT4_O_I2 I3=L7_LUT4_I3_I0_LUT4_O_I3 O=L7_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1 I2=L7_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2 I3=L7_LUT4_I1_3_I2_LUT4_O_I2 O=L7_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I2=R7_LUT4_I3_23_O_LUT4_I2_O I3=L7_LUT4_I3_I2_LUT4_O_I2 O=L7_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_1_O I1=L7_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_12_I2_LUT4_I1_I3_LUT4_O_I3 I3=R7_LUT4_I3_22_O_LUT4_I2_2_O O=L7_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_20_O I1=R7_LUT4_I3_19_O I2=R7_LUT4_I3_21_O I3=R7_LUT4_I3_18_O O=L7_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L7_LUT4_I1_3_I2_LUT4_O_I3 I1=L7_LUT4_I1_3_I2_LUT4_O_I1 I2=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I2 I1=L7_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I3 I2=L7_LUT4_I3_12_I0_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I2_2_I3_LUT4_O_I0_LUT4_O_I1 O=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=R7_LUT4_I3_22_O_LUT4_I2_O I2=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R7_LUT4_I3_19_O I1=R7_LUT4_I3_20_O I2=R7_LUT4_I3_21_O I3=R7_LUT4_I3_18_O O=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_20_O I1=R7_LUT4_I3_19_O I2=R7_LUT4_I3_18_O I3=R7_LUT4_I3_21_O O=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_2_O I1=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_23_O_LUT4_I2_O I3=L7_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 O=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1 I2=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I1_3_I2_LUT4_O_I1 O=L7_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L7_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L7_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L7_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_2_O I1=L7_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R7_LUT4_I3_23_O_LUT4_I2_O I3=L7_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L7_LUT4_I3_12_I2_LUT4_O_I3 I1=R7_LUT4_I3_22_O_LUT4_I2_1_O I2=L7_LUT4_I1_3_I3_LUT4_O_I1 I3=L7_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L7_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R7_LUT4_I3_23_O_LUT4_I2_O I3=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=L7_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_22_O_LUT4_I2_2_O I3=L7_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L7_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_23_O_LUT4_I2_O I1=R7_LUT4_I3_22_O_LUT4_I2_2_O I2=L7_LUT4_I3_I1_LUT4_O_I2 I3=L7_LUT4_I3_I1_LUT4_O_I3 O=L7_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R7_LUT4_I3_21_O I1=R7_LUT4_I3_20_O I2=R7_LUT4_I3_19_O I3=R7_LUT4_I3_18_O O=L7_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I3=R7_LUT4_I3_22_O_LUT4_I2_1_O O=L7_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_22_O_LUT4_I2_2_O O=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_21_O I1=R7_LUT4_I3_20_O I2=R7_LUT4_I3_19_O I3=R7_LUT4_I3_18_O O=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R7_LUT4_I3_21_O I1=R7_LUT4_I3_18_O I2=R7_LUT4_I3_19_O I3=R7_LUT4_I3_20_O O=L7_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_I2 I2=L7_LUT4_I3_I1_LUT4_O_I2 I3=R7_LUT4_I3_22_O_LUT4_I2_2_O O=L7_LUT4_I3_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L7_LUT4_I3_I2_LUT4_O_I1 I2=L7_LUT4_I3_I2_LUT4_O_I2 I3=R7_LUT4_I3_22_O_LUT4_I2_1_O O=L7_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=L7_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R7_LUT4_I3_23_O_LUT4_I2_O O=L7_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_22_O_LUT4_I2_O I1=L7_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=R7_LUT4_I3_22_O_LUT4_I2_1_O I3=L7_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 O=L7_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R7_LUT4_I3_20_O I1=R7_LUT4_I3_21_O I2=R7_LUT4_I3_19_O I3=R7_LUT4_I3_18_O O=L7_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R7_LUT4_I3_21_O I1=R7_LUT4_I3_19_O I2=R7_LUT4_I3_18_O I3=R7_LUT4_I3_20_O O=L7_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R7_LUT4_I3_21_O I1=R7_LUT4_I3_20_O I2=R7_LUT4_I3_19_O I3=R7_LUT4_I3_18_O O=L7_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=L7(1) D=R6(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(2) D=R6(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(11) D=R6(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(12) D=R6(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(13) D=R6(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(14) D=R6(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(15) D=R6(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(16) D=R6(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(17) D=R6(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(18) D=R6(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(19) D=R6(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(20) D=R6(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(3) D=R6(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(21) D=R6(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(22) D=R6(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(23) D=R6(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(24) D=R6(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(25) D=R6(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(26) D=R6(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(27) D=R6(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(28) D=R6(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(29) D=R6(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(30) D=R6(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(4) D=R6(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(31) D=R6(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(32) D=R6(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(5) D=R6(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(6) D=R6(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(7) D=R6(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(8) D=R6(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(9) D=R6(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L7(10) D=R6(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:155.1-156.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L8(3) I2=L8_LUT4_I1_I2 I3=L8_LUT4_I1_I3 O=R9_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L8(10) I2=L8_LUT4_I1_1_I2 I3=L8_LUT4_I1_1_I3 O=R9_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I1=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L8_LUT4_I1_1_I2_LUT4_O_I2 I3=L8_LUT4_I1_1_I2_LUT4_O_I3 O=L8_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I1=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I2=L8_LUT4_I1_1_I2_LUT4_O_I2 I3=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3 O=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0 I2=R8_LUT4_I3_10_O_LUT4_I2_2_O I3=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_11_O_LUT4_I2_O O=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_20_I2_LUT4_O_I2 I3=R8_LUT4_I3_10_O_LUT4_I2_O O=L8_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_10_O_LUT4_I2_2_O O=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_11_O_LUT4_I2_O O=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_8_O I1=R8_LUT4_I3_9_O I2=R8_LUT4_I3_7_O I3=R8_LUT4_I3_6_O O=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_10_O_LUT4_I2_2_O I3=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_6_O I1=R8_LUT4_I3_8_O I2=R8_LUT4_I3_7_O I3=R8_LUT4_I3_9_O O=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_8_O I1=R8_LUT4_I3_7_O I2=R8_LUT4_I3_6_O I3=R8_LUT4_I3_9_O O=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_11_O_LUT4_I2_O I3=L8_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 O=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O I1=L8_LUT4_I1_1_I3_LUT4_O_I1 I2=L8_LUT4_I1_1_I3_LUT4_O_I2 I3=L8_LUT4_I1_1_I3_LUT4_O_I3 O=L8_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I1=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_11_O I3=R8_LUT4_I3_10_O O=L8_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R8_LUT4_I3_9_O I1=R8_LUT4_I3_8_O I2=R8_LUT4_I3_6_O I3=R8_LUT4_I3_7_O O=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_9_O I1=R8_LUT4_I3_8_O I2=R8_LUT4_I3_7_O I3=R8_LUT4_I3_6_O O=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I1_2_I2_LUT4_O_I2 I1=L8_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_16_I1_LUT4_O_I2 I3=L8_LUT4_I1_1_I2_LUT4_O_I3 O=L8_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_20_I2_LUT4_O_I2 I3=R8_LUT4_I3_10_O_LUT4_I2_2_O O=L8_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I3=R8_LUT4_I3_10_O_LUT4_I2_O O=L8_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R8_LUT4_I3_11_O_LUT4_I2_O I3=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=L8_LUT4_I3_20_I1_LUT4_O_I3 I2=L8_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I1_2_I3_LUT4_O_I0 O=L8_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_11_O_LUT4_I2_O I3=L8_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L8_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8(1) I2=L8_LUT4_I1_2_I2 I3=L8_LUT4_I1_2_I3 O=R9_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=L8_LUT4_I1_2_I2_LUT4_O_I2 I3=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O O=L8_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_20_I2_LUT4_O_I2 I3=R8_LUT4_I3_11_O_LUT4_I2_O O=L8_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_10_O_LUT4_I2_O O=L8_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_10_O_LUT4_I2_2_O I3=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 O=L8_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_9_O I1=R8_LUT4_I3_6_O I2=R8_LUT4_I3_7_O I3=R8_LUT4_I3_8_O O=L8_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I1_2_I3_LUT4_O_I0 I1=L8_LUT4_I1_2_I3_LUT4_O_I1 I2=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L8_LUT4_I3_20_I1 O=L8_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2 I3=L8_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3 O=L8_LUT4_I1_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_11_O_LUT4_I2_O I3=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_10_O_LUT4_I2_2_O O=L8_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_8_O I1=R8_LUT4_I3_7_O I2=R8_LUT4_I3_9_O I3=R8_LUT4_I3_6_O O=L8_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I1_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_11_O_LUT4_I2_O I3=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_9_O I1=R8_LUT4_I3_7_O I2=R8_LUT4_I3_6_O I3=R8_LUT4_I3_8_O O=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_10_O_LUT4_I2_2_O O=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_7_O I1=R8_LUT4_I3_6_O I2=R8_LUT4_I3_9_O I3=R8_LUT4_I3_8_O O=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L8(5) I2=L8_LUT4_I1_3_I2 I3=L8_LUT4_I1_3_I3 O=R9_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_3_I2_LUT4_O_I1 I2=L8_LUT4_I3_4_I2_LUT4_O_I1 I3=L8_LUT4_I1_3_I2_LUT4_O_I3 O=L8_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I1_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_O I1=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R8_LUT4_I3_17_O_LUT4_I2_O O=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_15_O I1=R8_LUT4_I3_14_O I2=R8_LUT4_I3_13_O I3=R8_LUT4_I3_12_O O=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I2 I2=R8_LUT4_I3_16_O_LUT4_I2_2_O I3=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_14_O I1=R8_LUT4_I3_15_O I2=R8_LUT4_I3_13_O I3=R8_LUT4_I3_12_O O=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I0 I1=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I1=R8_LUT4_I3_16_O_LUT4_I2_2_O I2=R8_LUT4_I3_17_O_LUT4_I2_O I3=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_15_O I1=R8_LUT4_I3_14_O I2=R8_LUT4_I3_13_O I3=R8_LUT4_I3_12_O O=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_16_O_LUT4_I2_O I3=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_15_O I1=R8_LUT4_I3_12_O I2=R8_LUT4_I3_13_O I3=R8_LUT4_I3_14_O O=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_15_O I1=R8_LUT4_I3_14_O I2=R8_LUT4_I3_12_O I3=R8_LUT4_I3_13_O O=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_O I1=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_16_O_LUT4_I2_2_O O=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_17_O_LUT4_I2_O I3=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I2_I3_LUT4_O_I0 I1=L8_LUT4_I1_3_I3_LUT4_O_I1 I2=L8_LUT4_I3_4_I0_LUT4_I0_O I3=L8_LUT4_I1_3_I3_LUT4_O_I3 O=L8_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I1_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I3=R8_LUT4_I3_16_O_LUT4_I2_2_O O=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_14_O I1=R8_LUT4_I3_13_O I2=R8_LUT4_I3_12_O I3=R8_LUT4_I3_15_O O=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_O I1=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_17_O_LUT4_I2_O O=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_15_O I1=R8_LUT4_I3_13_O I2=R8_LUT4_I3_14_O I3=R8_LUT4_I3_12_O O=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_15_O I1=R8_LUT4_I3_14_O I2=R8_LUT4_I3_13_O I3=R8_LUT4_I3_12_O O=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L8(6) I2=L8_LUT4_I1_4_I2 I3=L8_LUT4_I1_4_I3 O=R9_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=L8_LUT4_I1_4_I2_LUT4_O_I2 I3=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=L8_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0 I1=R8_LUT4_I3_34_O_LUT4_I2_2_O I2=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=R8_LUT4_I3_30_O I1=R8_LUT4_I3_32_O I2=R8_LUT4_I3_31_O I3=R8_LUT4_I3_33_O O=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R8_LUT4_I3_35_O_LUT4_I2_O O=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_32_O I1=R8_LUT4_I3_31_O I2=R8_LUT4_I3_30_O I3=R8_LUT4_I3_33_O O=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1 I2=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3 I3=R8_LUT4_I3_35_O_LUT4_I2_O O=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0 I2=R8_LUT4_I3_34_O_LUT4_I2_2_O I3=L8_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=L8_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2 I3=R8_LUT4_I3_34_O_LUT4_I2_1_O O=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_35_O_LUT4_I2_O I1=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_34_O_LUT4_I2_2_O I3=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=R8_LUT4_I3_34_O_LUT4_I2_1_O I3=L8_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_31_O I1=R8_LUT4_I3_30_O I2=R8_LUT4_I3_33_O I3=R8_LUT4_I3_32_O O=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I1_4_I3_LUT4_O_I0 I1=L8_LUT4_I1_4_I3_LUT4_O_I1 I2=L8_LUT4_I1_8_I3_LUT4_O_I3 I3=L8_LUT4_I1_4_I3_LUT4_O_I3 O=L8_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I0 I1=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I1 I2=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2 I3=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I3 O=L8_LUT4_I1_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=R8_LUT4_I3_34_O_LUT4_I2_1_O I3=R8_LUT4_I3_34_O_LUT4_I2_O O=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=R8_LUT4_I3_33_O I1=R8_LUT4_I3_32_O I2=R8_LUT4_I3_31_O I3=R8_LUT4_I3_30_O O=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2 I2=R8_LUT4_I3_35_O_LUT4_I2_O I3=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_1_O I1=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_34_O_LUT4_I2_2_O I3=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_32_O I1=R8_LUT4_I3_33_O I2=R8_LUT4_I3_31_O I3=R8_LUT4_I3_30_O O=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_33_O I1=R8_LUT4_I3_32_O I2=R8_LUT4_I3_30_O I3=R8_LUT4_I3_31_O O=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_34_O_LUT4_I2_1_O I3=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I0 I1=L8_LUT4_I3_14_I1_LUT4_O_I3 I2=L8_LUT4_I1_8_I2_LUT4_O_I2 I3=L8_LUT4_I3_19_I0_LUT4_O_I3 O=L8_LUT4_I1_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I1=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_34_O_LUT4_I2_1_O I3=L8_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=L8_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_2_O I1=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_35_O_LUT4_I2_O I3=L8_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2 O=L8_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_19_I2_LUT4_O_I1 I1=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=L8_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0 I3=R8_LUT4_I3_34_O_LUT4_I2_1_O O=L8_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_35_O_LUT4_I2_O I1=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R8_LUT4_I3_34_O_LUT4_I2_2_O O=L8_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8(7) I2=L8_LUT4_I1_5_I2 I3=L8_LUT4_I1_5_I3 O=R9_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_5_I2_LUT4_O_I1 I2=L8_LUT4_I1_5_I2_LUT4_O_I2 I3=L8_LUT4_I1_5_I2_LUT4_O_I3 O=L8_LUT4_I1_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_11_I1_LUT4_O_I3 I3=L8_LUT4_I3_11_I1_LUT4_O_I1 O=L8_LUT4_I1_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_46_O_LUT4_I2_2_O I3=R8_LUT4_I3_46_O_LUT4_I2_1_O O=L8_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011001100110101
+.subckt LUT4 I0=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I0 I1=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I2=R8_LUT4_I3_46_O_LUT4_I2_2_O I3=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R8_LUT4_I3_45_O I1=R8_LUT4_I3_42_O I2=R8_LUT4_I3_43_O I3=R8_LUT4_I3_44_O O=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_1_O I1=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=R8_LUT4_I3_47_O_LUT4_I2_O I3=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_45_O I1=R8_LUT4_I3_44_O I2=R8_LUT4_I3_43_O I3=R8_LUT4_I3_42_O O=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I3 I3=L8_LUT4_I1_5_I2_LUT4_O_I3 O=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_2_O I1=L8_LUT4_I3_2_I1_LUT4_O_I2 I2=L8_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R8_LUT4_I3_46_O_LUT4_I2_O O=L8_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_46_O_LUT4_I2_1_O I3=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I0 O=L8_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_2_I2_LUT4_O_I2 I2=L8_LUT4_I1_5_I3_LUT4_O_I2 I3=L8_LUT4_I1_5_I3_LUT4_O_I3 O=L8_LUT4_I1_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_1_O I1=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_46_O_LUT4_I2_O I3=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_44_O I1=R8_LUT4_I3_42_O I2=R8_LUT4_I3_43_O I3=R8_LUT4_I3_45_O O=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_45_O I1=R8_LUT4_I3_44_O I2=R8_LUT4_I3_43_O I3=R8_LUT4_I3_42_O O=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_46_O_LUT4_I2_2_O I3=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_43_O I1=R8_LUT4_I3_42_O I2=R8_LUT4_I3_45_O I3=R8_LUT4_I3_44_O O=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_45_O I1=R8_LUT4_I3_43_O I2=R8_LUT4_I3_44_O I3=R8_LUT4_I3_42_O O=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L8(8) I2=L8_LUT4_I1_6_I2 I3=L8_LUT4_I1_6_I3 O=R9_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_6_I2_LUT4_O_I1 I2=L8_LUT4_I3_3_I2 I3=L8_LUT4_I1_6_I2_LUT4_O_I3 O=L8_LUT4_I1_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_6_I2_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I1_6_I2_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I1_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_1_O I1=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0 I3=R8_LUT4_I3_5_O_LUT4_I2_O O=L8_LUT4_I1_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 O=L8_LUT4_I1_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_5_O_LUT4_I2_O I3=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 O=L8_LUT4_I1_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I0 O=L8_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I2=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I3 I3=R8_LUT4_I3_4_O_LUT4_I2_1_O O=L8_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I1_6_I3_LUT4_O_I0 I1=L8_LUT4_I1_I2_LUT4_O_I1 I2=L8_LUT4_I3_13_I0 I3=L8_LUT4_I1_6_I3_LUT4_O_I3 O=L8_LUT4_I1_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I3_13_I2_LUT4_O_I3 I1=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_13_I2_LUT4_O_I1 O=L8_LUT4_I1_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I0 I1=R8_LUT4_I3_5_O_LUT4_I2_O I2=L8_LUT4_I1_6_I2_LUT4_O_I1 I3=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R8_LUT4_I3_3_O I1=R8_LUT4_I3_2_O I2=R8_LUT4_I3_1_O I3=R8_LUT4_I3_O O=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_4_O_LUT4_I2_2_O O=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I3=R8_LUT4_I3_4_O_LUT4_I2_1_O O=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_1_O I1=R8_LUT4_I3_2_O I2=R8_LUT4_I3_3_O I3=R8_LUT4_I3_O O=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L8(19) I2=L8_LUT4_I1_7_I2 I3=L8_LUT4_I1_7_I3 O=R9_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_7_I2_LUT4_O_I1 I2=L8_LUT4_I1_7_I2_LUT4_O_I2 I3=L8_LUT4_I1_7_I2_LUT4_O_I3 O=L8_LUT4_I1_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I1_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I0 I1=R8_LUT4_I3_28_O_LUT4_I2_O I2=R8_LUT4_I3_28_O_LUT4_I2_1_O I3=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_28_O_LUT4_I2_2_O I3=L8_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_26_O I1=R8_LUT4_I3_25_O I2=R8_LUT4_I3_27_O I3=R8_LUT4_I3_24_O O=L8_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_28_O_LUT4_I2_2_O I1=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_28_O_LUT4_I2_1_O I3=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 O=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_27_O I1=R8_LUT4_I3_26_O I2=R8_LUT4_I3_25_O I3=R8_LUT4_I3_24_O O=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_28_O_LUT4_I2_O I3=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_27_O I1=R8_LUT4_I3_26_O I2=R8_LUT4_I3_25_O I3=R8_LUT4_I3_24_O O=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_7_I3_LUT4_O_I1 I2=L8_LUT4_I1_7_I3_LUT4_O_I2 I3=L8_LUT4_I3_10_I0 O=L8_LUT4_I1_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=L8_LUT4_I3_8_I1_LUT4_O_I2 I1=L8_LUT4_I3_8_I1_LUT4_O_I1 I2=L8_LUT4_I3_5_I2_LUT4_I1_I2 I3=L8_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I0 I1=R8_LUT4_I3_28_O_LUT4_I2_2_O I2=R8_LUT4_I3_28_O_LUT4_I2_O I3=L8_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I3 I2=L8_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 I3=R8_LUT4_I3_28_O_LUT4_I2_1_O O=L8_LUT4_I1_7_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8(30) I2=L8_LUT4_I1_8_I2 I3=L8_LUT4_I1_8_I3 O=R9_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_8_I2_LUT4_O_I1 I2=L8_LUT4_I1_8_I2_LUT4_O_I2 I3=L8_LUT4_I3_14_I1 O=L8_LUT4_I1_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L8_LUT4_I3_19_I2_LUT4_O_I1 I1=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I1_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R8_LUT4_I3_35_O_LUT4_I2_O I1=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_34_O_LUT4_I2_2_O O=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_33_O I1=R8_LUT4_I3_31_O I2=R8_LUT4_I3_32_O I3=R8_LUT4_I3_30_O O=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_34_O_LUT4_I2_1_O I3=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_33_O I1=R8_LUT4_I3_30_O I2=R8_LUT4_I3_31_O I3=R8_LUT4_I3_32_O O=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2 I3=R8_LUT4_I3_34_O_LUT4_I2_2_O O=L8_LUT4_I1_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_33_O I1=R8_LUT4_I3_32_O I2=R8_LUT4_I3_31_O I3=R8_LUT4_I3_30_O O=L8_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O I2=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=L8_LUT4_I1_8_I3_LUT4_O_I3 O=L8_LUT4_I1_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O I2=L8_LUT4_I1_4_I2_LUT4_O_I2 I3=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_8_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_2_O I1=R8_LUT4_I3_35_O_LUT4_I2_O I2=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_1_O I1=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_34_O_LUT4_I2_2_O O=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_31_O I1=R8_LUT4_I3_32_O I2=R8_LUT4_I3_33_O I3=R8_LUT4_I3_30_O O=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=R8_LUT4_I3_35_O_LUT4_I2_O I2=R8_LUT4_I3_34_O_LUT4_I2_2_O I3=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I1_I2_LUT4_O_I0 I1=L8_LUT4_I1_I2_LUT4_O_I1 I2=L8_LUT4_I1_I2_LUT4_O_I2 I3=L8_LUT4_I1_I2_LUT4_O_I3 O=L8_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I2=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R8_LUT4_I3_4_O_LUT4_I2_O O=L8_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_4_O_LUT4_I2_1_O O=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_5_O_LUT4_I2_O I1=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_3_O I1=R8_LUT4_I3_2_O I2=R8_LUT4_I3_1_O I3=R8_LUT4_I3_O O=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R8_LUT4_I3_3_O I1=R8_LUT4_I3_2_O I2=R8_LUT4_I3_1_O I3=R8_LUT4_I3_O O=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I1_6_I3_LUT4_O_I3 I3=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 I1=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R8_LUT4_I3_4_O_LUT4_I2_1_O O=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_5_O_LUT4_I2_O I1=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_4_O_LUT4_I2_2_O O=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_13_I0_LUT4_O_I2 I1=L8_LUT4_I3_13_I0_LUT4_O_I3 I2=L8_LUT4_I1_6_I2_LUT4_O_I3 I3=L8_LUT4_I1_6_I2_LUT4_O_I1 O=L8_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_I3_LUT4_O_I1 I2=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I0 I3=R8_LUT4_I3_4_O_LUT4_I2_O O=L8_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R8_LUT4_I3_4_O_LUT4_I2_1_O O=L8_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_5_O_LUT4_I2_O I1=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0 O=L8_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8(15) I3=L8_LUT4_I2_I3 O=R9_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L8_LUT4_I2_I3_LUT4_O_I0 I1=L8_LUT4_I3_4_I0_LUT4_I0_O I2=L8_LUT4_I2_I3_LUT4_O_I2 I3=L8_LUT4_I2_I3_LUT4_O_I3 O=L8_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L8_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_16_O_LUT4_I2_O I3=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_14_O I1=R8_LUT4_I3_12_O I2=R8_LUT4_I3_13_O I3=R8_LUT4_I3_15_O O=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_17_O_LUT4_I2_O I1=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I2=R8_LUT4_I3_16_O_LUT4_I2_2_O I3=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_15_O I1=R8_LUT4_I3_13_O I2=R8_LUT4_I3_12_O I3=R8_LUT4_I3_14_O O=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_4_I0_LUT4_O_I3 I3=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O O=L8_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_17_I2_LUT4_O_I2 O=L8_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I2 I3=R8_LUT4_I3_17_O_LUT4_I2_O O=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=R8_LUT4_I3_16_O_LUT4_I2_1_O I2=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100001101
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=R8_LUT4_I3_16_O_LUT4_I2_O O=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I0 I1=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3 I3=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2 O=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_I0 I1=L8_LUT4_I3_I1 I2=L8_LUT4_I3_I2 I3=L8(2) O=R9_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=L8_LUT4_I3_1_I0 I1=L8_LUT4_I3_1_I1 I2=L8_LUT4_I3_1_I2 I3=L8(17) O=R9_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L8_LUT4_I3_10_I0 I1=L8_LUT4_I3_10_I1 I2=L8_LUT4_I3_10_I2 I3=L8(11) O=R9_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_8_I1_LUT4_O_I3 I3=L8_LUT4_I3_5_I1 O=L8_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_28_O_LUT4_I2_1_O I1=L8_LUT4_I3_10_I1_LUT4_O_I1 I2=L8_LUT4_I3_10_I1_LUT4_O_I2 I3=L8_LUT4_I3_10_I1_LUT4_O_I3 O=L8_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R8_LUT4_I3_27_O I1=R8_LUT4_I3_26_O I2=R8_LUT4_I3_25_O I3=R8_LUT4_I3_24_O O=L8_LUT4_I3_10_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I1_7_I2_LUT4_O_I1 O=L8_LUT4_I3_10_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I0 I2=R8_LUT4_I3_28_O_LUT4_I2_1_O I3=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L8_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_28_O_LUT4_I2_2_O I1=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_28_O_LUT4_I2_O I3=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_29_O_LUT4_I2_O O=L8_LUT4_I3_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_28_O_LUT4_I2_2_O I1=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2 I2=R8_LUT4_I3_28_O_LUT4_I2_O I3=L8_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_26_O I1=R8_LUT4_I3_25_O I2=R8_LUT4_I3_24_O I3=R8_LUT4_I3_27_O O=L8_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L8_LUT4_I3_10_I1_LUT4_O_I2 I1=L8_LUT4_I3_10_I2 I2=L8_LUT4_I3_10_I2_LUT4_I1_I2 I3=L8_LUT4_I3_10_I2_LUT4_I1_I3 O=L8_LUT4_I3_5_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_10_I2_LUT4_I1_I2 I3=L8_LUT4_I3_10_I2 O=L8_LUT4_I1_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_7_I2_LUT4_O_I2 I3=L8_LUT4_I3_10_I2_LUT4_O_I3 O=L8_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_8_I0_LUT4_O_I2 I3=L8_LUT4_I3_10_I2_LUT4_O_I3 O=L8_LUT4_I3_10_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_10_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_28_O_LUT4_I2_1_O I1=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_28_O_LUT4_I2_O I3=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2 O=L8_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I0 I2=L8_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I0 I3=R8_LUT4_I3_28_O_LUT4_I2_2_O O=L8_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_21_I0 I1=L8_LUT4_I3_11_I1 I2=L8_LUT4_I3_11_I2 I3=L8(12) O=R9_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L8_LUT4_I3_21_I2_LUT4_O_I3 I1=L8_LUT4_I3_11_I1_LUT4_O_I1 I2=L8_LUT4_I3_11_I1_LUT4_O_I2 I3=L8_LUT4_I3_11_I1_LUT4_O_I3 O=L8_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_11_I1_LUT4_O_I1_LUT4_I3_I1 I2=L8_LUT4_I3_11_I1_LUT4_O_I1_LUT4_I3_I2 I3=L8_LUT4_I3_11_I1_LUT4_O_I1 O=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_46_O_LUT4_I2_2_O I3=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I0 O=L8_LUT4_I3_11_I1_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_1_O I1=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R8_LUT4_I3_46_O_LUT4_I2_O O=L8_LUT4_I3_11_I1_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_11_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_46_O_LUT4_I2_O I3=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_2_O I1=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R8_LUT4_I3_46_O_LUT4_I2_1_O O=L8_LUT4_I3_11_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_5_I2_LUT4_O_I2 I3=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3 O=L8_LUT4_I3_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_2_O I1=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_46_O_LUT4_I2_1_O I3=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I0 I2=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_46_O_LUT4_I2_O O=L8_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_2_I0_LUT4_O_I2 I2=L8_LUT4_I3_11_I2_LUT4_O_I2 I3=L8_LUT4_I3_2_I1 O=L8_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_2_I1_LUT4_O_I2 I3=R8_LUT4_I3_47_O_LUT4_I2_O O=L8_LUT4_I3_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_46_O_LUT4_I2_1_O O=L8_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=R8_LUT4_I3_46_O_LUT4_I2_2_O I2=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_46_O_LUT4_I2_O O=L8_LUT4_I3_11_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_12_I0 I1=L8_LUT4_I3_12_I1 I2=L8_LUT4_I3_12_I2 I3=L8(13) O=R9_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=L8_LUT4_I3_I0_LUT4_O_I2 I1=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I2=L8_LUT4_I3_I0_LUT4_O_I1 I3=L8_LUT4_I3_12_I0_LUT4_O_I3 O=L8_LUT4_I3_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_I1_LUT4_O_I1 I2=L8_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L8_LUT4_I3_12_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L8_LUT4_I3_12_I2_LUT4_O_I3 I1=R8_LUT4_I3_22_O_LUT4_I2_2_O I2=L8_LUT4_I3_I2_LUT4_O_I2 I3=L8_LUT4_I3_12_I1_LUT4_O_I3 O=L8_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_22_O_LUT4_I2_1_O O=L8_LUT4_I3_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_15_I2_LUT4_I3_I1_LUT4_O_I3 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 O=L8_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_21_O I1=R8_LUT4_I3_18_O I2=R8_LUT4_I3_19_O I3=R8_LUT4_I3_20_O O=L8_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_12_I2_LUT4_O_I1 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_12_I2_LUT4_O_I3 O=L8_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_22_O_LUT4_I2_1_O O=L8_LUT4_I3_12_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_15_I2_LUT4_I3_I2_LUT4_O_I1 I2=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_22_O_LUT4_I2_2_O O=L8_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_21_O I1=R8_LUT4_I3_20_O I2=R8_LUT4_I3_19_O I3=R8_LUT4_I3_18_O O=L8_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_21_O I1=R8_LUT4_I3_20_O I2=R8_LUT4_I3_19_O I3=R8_LUT4_I3_18_O O=L8_LUT4_I3_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I3_13_I0 I1=L8_LUT4_I1_I3 I2=L8_LUT4_I3_13_I2 I3=L8(14) O=R9_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=L8_LUT4_I1_I3 I1=L8_LUT4_I1_I2_LUT4_O_I0 I2=L8_LUT4_I3_13_I0_LUT4_O_I2 I3=L8_LUT4_I3_13_I0_LUT4_O_I3 O=L8_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R8_LUT4_I3_5_O_LUT4_I2_O I1=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_13_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_3_O I1=R8_LUT4_I3_2_O I2=R8_LUT4_I3_O I3=R8_LUT4_I3_1_O O=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_3_O I1=R8_LUT4_I3_O I2=R8_LUT4_I3_1_O I3=R8_LUT4_I3_2_O O=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R8_LUT4_I3_4_O_LUT4_I2_1_O O=L8_LUT4_I3_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_2_O I1=R8_LUT4_I3_3_O I2=R8_LUT4_I3_1_O I3=R8_LUT4_I3_O O=L8_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I1_6_I3_LUT4_O_I3 I1=L8_LUT4_I3_13_I2_LUT4_O_I1 I2=L8_LUT4_I3_13_I2_LUT4_O_I2 I3=L8_LUT4_I3_13_I2_LUT4_O_I3 O=L8_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 I2=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_5_O_LUT4_I2_O O=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I0 I1=R8_LUT4_I3_4_O_LUT4_I2_1_O I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_1_O I1=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R8_LUT4_I3_5_O_LUT4_I2_O I3=L8_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_I3_I1 I2=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_I3_I2 I3=L8_LUT4_I3_13_I2_LUT4_O_I2 O=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=L8_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1 I3=R8_LUT4_I3_5_O_LUT4_I2_O O=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_1_O I1=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_4_O_LUT4_I2_2_O O=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0 I3=R8_LUT4_I3_4_O_LUT4_I2_1_O O=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_2_O I1=R8_LUT4_I3_1_O I2=R8_LUT4_I3_O I3=R8_LUT4_I3_3_O O=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_5_O_LUT4_I2_O I1=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_1_O I1=R8_LUT4_I3_O I2=R8_LUT4_I3_3_O I3=R8_LUT4_I3_2_O O=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_3_O I1=R8_LUT4_I3_1_O I2=R8_LUT4_I3_O I3=R8_LUT4_I3_2_O O=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_13_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_1_O I1=L8_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_4_O_LUT4_I2_2_O O=L8_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_2_O I1=R8_LUT4_I3_1_O I2=R8_LUT4_I3_3_O I3=R8_LUT4_I3_O O=L8_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 I3=R8_LUT4_I3_5_O_LUT4_I2_O O=L8_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_14_I0 I1=L8_LUT4_I3_14_I1 I2=L8_LUT4_I3_14_I2 I3=L8(16) O=R9_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_4_I3_LUT4_O_I3 I2=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O I3=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=L8_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_14_I1_LUT4_O_I2 I3=L8_LUT4_I3_14_I1_LUT4_O_I3 O=L8_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I1 I3=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2 O=L8_LUT4_I3_14_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_2_O I1=R8_LUT4_I3_35_O_LUT4_I2_O I2=L8_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_35_O_LUT4_I2_O O=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_33_O I1=R8_LUT4_I3_31_O I2=R8_LUT4_I3_30_O I3=R8_LUT4_I3_32_O O=L8_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_35_O_LUT4_I2_O I1=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_34_O_LUT4_I2_2_O O=L8_LUT4_I3_14_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_1_O I1=R8_LUT4_I3_34_O_LUT4_I2_O I2=L8_LUT4_I3_14_I2_LUT4_O_I2 I3=L8_LUT4_I3_14_I2_LUT4_O_I3 O=L8_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_14_I2_LUT4_O_I2_LUT4_I2_I1 I2=L8_LUT4_I3_14_I2_LUT4_O_I2 I3=R8_LUT4_I3_34_O_LUT4_I2_1_O O=L8_LUT4_I1_8_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0 I3=R8_LUT4_I3_35_O_LUT4_I2_O O=L8_LUT4_I3_14_I2_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_33_O I1=R8_LUT4_I3_32_O I2=R8_LUT4_I3_31_O I3=R8_LUT4_I3_30_O O=L8_LUT4_I3_14_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_34_O_LUT4_I2_1_O O=L8_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_33_O I1=R8_LUT4_I3_32_O I2=R8_LUT4_I3_31_O I3=R8_LUT4_I3_30_O O=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2 I2=R8_LUT4_I3_35_O_LUT4_I2_O I3=L8_LUT4_I1_8_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_32_O I1=R8_LUT4_I3_30_O I2=R8_LUT4_I3_31_O I3=R8_LUT4_I3_33_O O=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I3_15_I0 I1=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I2=L8_LUT4_I3_15_I2 I3=L8(18) O=R9_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_15_I0_LUT4_O_I1 I2=L8_LUT4_I3_12_I1 I3=L8_LUT4_I3_7_I0_LUT4_O_I3 O=L8_LUT4_I3_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_15_I0_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_15_I0_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_15_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_1_O I1=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_22_O_LUT4_I2_2_O I3=L8_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2 O=L8_LUT4_I3_15_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L8_LUT4_I3_15_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_15_I2_LUT4_I3_I1 I2=L8_LUT4_I3_15_I2_LUT4_I3_I2 I3=L8_LUT4_I3_15_I2 O=L8_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_15_I2_LUT4_I3_I1_LUT4_O_I3 O=L8_LUT4_I3_15_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_21_O I1=R8_LUT4_I3_20_O I2=R8_LUT4_I3_18_O I3=R8_LUT4_I3_19_O O=L8_LUT4_I3_15_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_1_O I1=L8_LUT4_I3_15_I2_LUT4_I3_I2_LUT4_O_I1 I2=L8_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_22_O_LUT4_I2_2_O O=L8_LUT4_I3_15_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_20_O I1=R8_LUT4_I3_18_O I2=R8_LUT4_I3_19_O I3=R8_LUT4_I3_21_O O=L8_LUT4_I3_15_I2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_15_I2_LUT4_O_I1 I2=L8_LUT4_I3_15_I2_LUT4_O_I2 I3=L8_LUT4_I3_I1_LUT4_O_I1 O=L8_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_1_O I1=L8_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_22_O_LUT4_I2_2_O I3=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_15_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_20_O I1=R8_LUT4_I3_19_O I2=R8_LUT4_I3_21_O I3=R8_LUT4_I3_18_O O=L8_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_19_O I1=R8_LUT4_I3_18_O I2=R8_LUT4_I3_21_O I3=R8_LUT4_I3_20_O O=L8_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_20_O I1=R8_LUT4_I3_21_O I2=R8_LUT4_I3_19_O I3=R8_LUT4_I3_18_O O=L8_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I3_16_I0 I1=L8_LUT4_I3_16_I1 I2=L8_LUT4_I3_16_I2 I3=L8(20) O=R9_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O O=L8_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_16_I1_LUT4_O_I2 I3=L8_LUT4_I1_2_I2_LUT4_O_I2 O=L8_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_16_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I1_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_11_O_LUT4_I2_O I3=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I1 O=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_10_O_LUT4_I2_2_O I3=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_10_O_LUT4_I2_2_O I3=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I2=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_10_O_LUT4_I2_O O=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I2=R8_LUT4_I3_11_O_LUT4_I2_O I3=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0 O=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_8_O I1=R8_LUT4_I3_6_O I2=R8_LUT4_I3_7_O I3=R8_LUT4_I3_9_O O=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_2_I3_LUT4_O_I1 I2=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L8_LUT4_I3_20_I2 O=L8_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L8_LUT4_I3_17_I0 I1=L8_LUT4_I3_17_I1 I2=L8_LUT4_I3_17_I2 I3=L8(21) O=R9_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_3_I3_LUT4_O_I1 I2=L8_LUT4_I2_I3_LUT4_O_I0 I3=L8_LUT4_I3_4_I0_LUT4_I0_O O=L8_LUT4_I3_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_4_I0_LUT4_O_I2 I2=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O I3=L8_LUT4_I3_4_I0_LUT4_I0_O O=L8_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_3_I2_LUT4_O_I1 I2=L8_LUT4_I3_17_I2_LUT4_O_I2 I3=L8_LUT4_I3_4_I2_LUT4_O_I2 O=L8_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I2 I3=R8_LUT4_I3_16_O_LUT4_I2_O O=L8_LUT4_I3_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_16_O_LUT4_I2_1_O O=L8_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_17_O_LUT4_I2_O I1=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=R8_LUT4_I3_16_O_LUT4_I2_2_O O=L8_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_15_O I1=R8_LUT4_I3_14_O I2=R8_LUT4_I3_13_O I3=R8_LUT4_I3_12_O O=L8_LUT4_I3_17_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I3_9_I0 I1=L8_LUT4_I3_18_I1 I2=L8_LUT4_I3_18_I2 I3=L8(23) O=R9_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L8_LUT4_I3_6_I1 I1=L8_LUT4_I3_9_I1_LUT4_O_I1 I2=L8_LUT4_I3_9_I1_LUT4_O_I0 I3=L8_LUT4_I3_18_I1_LUT4_O_I3 O=L8_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_18_I1_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 O=L8_LUT4_I3_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_40_O_LUT4_I2_O O=L8_LUT4_I3_18_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_41_O_LUT4_I2_O I1=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_40_O_LUT4_I2_2_O I3=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_9_I0_LUT4_O_I1 I2=L8_LUT4_I3_9_I2_LUT4_O_I2 I3=L8_LUT4_I3_1_I1_LUT4_O_I2 O=L8_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L8_LUT4_I3_19_I0 I1=L8_LUT4_I3_19_I1 I2=L8_LUT4_I3_19_I2 I3=L8(24) O=R9_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_14_I1_LUT4_O_I2 I2=L8_LUT4_I1_4_I3_LUT4_O_I0 I3=L8_LUT4_I3_19_I0_LUT4_O_I3 O=L8_LUT4_I3_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_34_O_LUT4_I2_1_O I3=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_19_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_34_O_LUT4_I2_2_O O=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I2=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3 I3=R8_LUT4_I3_34_O_LUT4_I2_O O=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_33_O I1=R8_LUT4_I3_32_O I2=R8_LUT4_I3_31_O I3=R8_LUT4_I3_30_O O=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_19_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=L8_LUT4_I1_4_I2_LUT4_O_I2 I3=L8_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=L8_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=L8_LUT4_I1_8_I2_LUT4_O_I2 I1=L8_LUT4_I3_19_I2_LUT4_O_I1 I2=L8_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=L8_LUT4_I3_14_I2 O=L8_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_19_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_O I1=L8_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_35_O_LUT4_I2_O I3=L8_LUT4_I1_8_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=L8_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_32_O I1=R8_LUT4_I3_31_O I2=R8_LUT4_I3_33_O I3=R8_LUT4_I3_30_O O=L8_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_34_O_LUT4_I2_1_O I1=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=R8_LUT4_I3_34_O_LUT4_I2_2_O I3=L8_LUT4_I1_4_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_19_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_9_I0_LUT4_O_I0 I1=L8_LUT4_I3_1_I0_LUT4_O_I1 I2=L8_LUT4_I3_9_I0_LUT4_O_I1 I3=L8_LUT4_I3_1_I0_LUT4_O_I3 O=L8_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0 I1=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_41_O I3=R8_LUT4_I3_40_O O=L8_LUT4_I3_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R8_LUT4_I3_39_O I1=R8_LUT4_I3_37_O I2=R8_LUT4_I3_38_O I3=R8_LUT4_I3_36_O O=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_39_O I1=R8_LUT4_I3_38_O I2=R8_LUT4_I3_37_O I3=R8_LUT4_I3_36_O O=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_41_O_LUT4_I2_O I3=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_1_I1_LUT4_O_I2 I3=L8_LUT4_I3_1_I1_LUT4_O_I3 O=L8_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_41_O_LUT4_I2_O I1=L8_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_40_O_LUT4_I2_2_O I3=L8_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_O I3=L8_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 O=L8_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0 I3=R8_LUT4_I3_41_O_LUT4_I2_O O=L8_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_2_O I1=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_1_I2_LUT4_O_I2 I3=L8_LUT4_I3_6_I1_LUT4_O_I3 O=L8_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_2_O I1=L8_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_2_I0 I1=L8_LUT4_I3_2_I1 I2=L8_LUT4_I3_2_I2 I3=L8(22) O=R9_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L8_LUT4_I3_20_I0 I1=L8_LUT4_I3_20_I1 I2=L8_LUT4_I3_20_I2 I3=L8(26) O=R9_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_I2_O I1=L8_LUT4_I1_1_I3_LUT4_O_I2 I2=L8_LUT4_I3_16_I1 I3=L8_LUT4_I3_20_I0_LUT4_O_I3 O=L8_LUT4_I3_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=L8_LUT4_I3_20_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L8_LUT4_I3_20_I1_LUT4_O_I0 I1=L8_LUT4_I3_20_I1_LUT4_O_I1 I2=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=L8_LUT4_I3_20_I1_LUT4_O_I3 O=L8_LUT4_I3_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0 I1=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1 I2=R8_LUT4_I3_11_O I3=R8_LUT4_I3_10_O O=L8_LUT4_I3_20_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=R8_LUT4_I3_9_O I1=R8_LUT4_I3_8_O I2=R8_LUT4_I3_7_O I3=R8_LUT4_I3_6_O O=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1 I2=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1 I3=R8_LUT4_I3_10_O_LUT4_I2_1_O O=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_2_O I1=L8_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_11_O_LUT4_I2_O I3=L8_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I0 I3=R8_LUT4_I3_10_O_LUT4_I2_O O=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I1_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R8_LUT4_I3_10_O_LUT4_I2_2_O I3=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1 O=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_9_O I1=R8_LUT4_I3_8_O I2=R8_LUT4_I3_7_O I3=R8_LUT4_I3_6_O O=L8_LUT4_I3_20_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_10_O_LUT4_I2_1_O I3=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_20_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_9_O I1=R8_LUT4_I3_8_O I2=R8_LUT4_I3_7_O I3=R8_LUT4_I3_6_O O=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3 I3=R8_LUT4_I3_11_O_LUT4_I2_O O=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_7_O I1=R8_LUT4_I3_8_O I2=R8_LUT4_I3_9_O I3=R8_LUT4_I3_6_O O=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I3_20_I1_LUT4_O_I1_LUT4_O_I3 I2=R8_LUT4_I3_10_O_LUT4_I2_2_O I3=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_1_O I1=L8_LUT4_I3_16_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_11_O_LUT4_I2_O O=L8_LUT4_I3_20_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_20_I2_LUT4_O_I1 I2=L8_LUT4_I3_20_I2_LUT4_O_I2 I3=R8_LUT4_I3_10_O_LUT4_I2_1_O O=L8_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_10_O_LUT4_I2_2_O O=L8_LUT4_I3_20_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_10_O_LUT4_I2_O I1=L8_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L8_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I3=R8_LUT4_I3_11_O_LUT4_I2_O O=L8_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_9_O I1=R8_LUT4_I3_7_O I2=R8_LUT4_I3_8_O I3=R8_LUT4_I3_6_O O=L8_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_9_O I1=R8_LUT4_I3_8_O I2=R8_LUT4_I3_7_O I3=R8_LUT4_I3_6_O O=L8_LUT4_I3_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_21_I0 I1=L8_LUT4_I3_21_I1 I2=L8_LUT4_I3_21_I2 I3=L8(32) O=R9_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_21_I0_LUT4_O_I2 I3=L8_LUT4_I1_5_I3_LUT4_O_I3 O=L8_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_5_I3_LUT4_O_I2 I2=L8_LUT4_I3_2_I2 I3=L8_LUT4_I3_11_I2_LUT4_O_I2 O=L8_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_5_I2_LUT4_O_I3 I3=L8_LUT4_I3_21_I2_LUT4_O_I3 O=L8_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I1_5_I2_LUT4_O_I1_LUT4_O_I1 I3=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2 O=L8_LUT4_I3_21_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L8_LUT4_I3_2_I0_LUT4_O_I0 I1=L8_LUT4_I1_5_I3_LUT4_O_I3 I2=L8_LUT4_I3_2_I0_LUT4_O_I2 I3=L8_LUT4_I3_2_I0_LUT4_O_I3 O=L8_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=L8_LUT4_I1_5_I2_LUT4_O_I2 I1=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1 I2=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I2 I3=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3 O=L8_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_2_O I1=L8_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_46_O_LUT4_I2_1_O I3=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_46_O_LUT4_I2_O I3=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_1_O I1=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I2=L8_LUT4_I3_2_I0_LUT4_O_I3 I3=L8_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_46_O_LUT4_I2_O O=L8_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_46_O_LUT4_I2_2_O O=L8_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_2_O I1=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_46_O_LUT4_I2_O O=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_45_O I1=R8_LUT4_I3_44_O I2=R8_LUT4_I3_43_O I3=R8_LUT4_I3_42_O O=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_46_O_LUT4_I2_1_O I3=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_45_O I1=R8_LUT4_I3_44_O I2=R8_LUT4_I3_43_O I3=R8_LUT4_I3_42_O O=L8_LUT4_I3_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I3_2_I1 I1=L8_LUT4_I3_11_I2_LUT4_O_I2 I2=L8_LUT4_I1_5_I3_LUT4_O_I2 I3=L8_LUT4_I3_2_I1_LUT4_I0_I3 O=L8_LUT4_I1_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_2_I1_LUT4_I0_I3_LUT4_O_I2 I3=L8_LUT4_I3_2_I1_LUT4_I0_I3_LUT4_O_I3 O=L8_LUT4_I3_2_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_46_O_LUT4_I2_O I3=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_2_I1_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_2_O I1=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_46_O_LUT4_I2_1_O I3=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_2_I1_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_2_I1_LUT4_O_I1 I2=L8_LUT4_I3_2_I1_LUT4_O_I2 I3=R8_LUT4_I3_46_O_LUT4_I2_O O=L8_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_46_O_LUT4_I2_1_O O=L8_LUT4_I3_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_46_O_LUT4_I2_2_O I3=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_44_O I1=R8_LUT4_I3_43_O I2=R8_LUT4_I3_45_O I3=R8_LUT4_I3_42_O O=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_45_O I1=R8_LUT4_I3_43_O I2=R8_LUT4_I3_42_O I3=R8_LUT4_I3_44_O O=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_44_O I1=R8_LUT4_I3_45_O I2=R8_LUT4_I3_43_O I3=R8_LUT4_I3_42_O O=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_43_O I1=R8_LUT4_I3_44_O I2=R8_LUT4_I3_45_O I3=R8_LUT4_I3_42_O O=L8_LUT4_I3_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_2_I0_LUT4_O_I2 I3=L8_LUT4_I3_2_I2 O=L8_LUT4_I3_21_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_1_O I1=L8_LUT4_I3_2_I1_LUT4_O_I2 I2=L8_LUT4_I3_2_I2_LUT4_O_I2 I3=L8_LUT4_I3_2_I2_LUT4_O_I3 O=L8_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_46_O_LUT4_I2_2_O I1=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_46_O_LUT4_I2_O O=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_44_O I1=R8_LUT4_I3_43_O I2=R8_LUT4_I3_42_O I3=R8_LUT4_I3_45_O O=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_47_O_LUT4_I2_O I1=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_46_O_LUT4_I2_1_O I3=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_42_O I1=R8_LUT4_I3_44_O I2=R8_LUT4_I3_43_O I3=R8_LUT4_I3_45_O O=L8_LUT4_I3_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_47_O_LUT4_I2_O O=L8_LUT4_I3_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L8_LUT4_I1_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=R8_LUT4_I3_46_O_LUT4_I2_O I2=R8_LUT4_I3_46_O_LUT4_I2_2_O I3=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_45_O I1=R8_LUT4_I3_44_O I2=R8_LUT4_I3_42_O I3=R8_LUT4_I3_43_O O=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_45_O I1=R8_LUT4_I3_44_O I2=R8_LUT4_I3_43_O I3=R8_LUT4_I3_42_O O=L8_LUT4_I3_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_3_I0 I1=L8_LUT4_I1_I3 I2=L8_LUT4_I3_3_I2 I3=L8(25) O=R9_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L8_LUT4_I3_13_I0 I1=L8_LUT4_I1_6_I2_LUT4_O_I3 I2=L8_LUT4_I3_3_I0_LUT4_O_I2 I3=L8_LUT4_I3_3_I0_LUT4_O_I3 O=L8_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L8_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0 I1=L8_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I2=R8_LUT4_I3_4_O_LUT4_I2_O I3=L8_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R8_LUT4_I3_2_O I1=R8_LUT4_I3_O I2=R8_LUT4_I3_1_O I3=R8_LUT4_I3_3_O O=L8_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_1_O I1=L8_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_13_I0_LUT4_O_I2_LUT4_O_I3 I3=R8_LUT4_I3_5_O_LUT4_I2_O O=L8_LUT4_I3_3_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_13_I2_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_5_O_LUT4_I2_O I3=L8_LUT4_I1_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=L8_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_1_O I1=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_3_I0_LUT4_O_I2 I2=L8_LUT4_I3_3_I2 I3=L8_LUT4_I1_6_I2_LUT4_O_I3 O=L8_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_3_I2_LUT4_O_I2 I3=L8_LUT4_I3_3_I2_LUT4_O_I3 O=L8_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_1_O I1=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R8_LUT4_I3_5_O_LUT4_I2_O O=L8_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_3_O I1=R8_LUT4_I3_2_O I2=R8_LUT4_I3_1_O I3=R8_LUT4_I3_O O=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_O I1=R8_LUT4_I3_2_O I2=R8_LUT4_I3_1_O I3=R8_LUT4_I3_3_O O=L8_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_4_O_LUT4_I2_O I1=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_4_O_LUT4_I2_2_O I3=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_3_O I1=R8_LUT4_I3_2_O I2=R8_LUT4_I3_1_O I3=R8_LUT4_I3_O O=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_3_O I1=R8_LUT4_I3_1_O I2=R8_LUT4_I3_2_O I3=R8_LUT4_I3_O O=L8_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I3_4_I0 I1=L8_LUT4_I3_4_I1 I2=L8_LUT4_I3_4_I2 I3=L8(27) O=R9_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L8_LUT4_I3_4_I0 I1=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O I2=L8_LUT4_I3_4_I1_LUT4_O_I3 I3=L8_LUT4_I3_4_I1_LUT4_O_I1 O=L8_LUT4_I3_4_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_4_I1_LUT4_O_I3 I1=L8_LUT4_I3_4_I0 I2=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O I3=L8_LUT4_I3_4_I0_LUT4_I1_I3 O=L8_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2 I3=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3 O=L8_LUT4_I3_4_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_17_O_LUT4_I2_O I1=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_16_O_LUT4_I2_2_O I3=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3 I1=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I2 I2=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_I2 I3=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_I3 O=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_16_O_LUT4_I2_O I3=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_17_O_LUT4_I2_O I1=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_16_O_LUT4_I2_2_O I3=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 O=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_4_I0_LUT4_O_I2 I3=L8_LUT4_I3_4_I0_LUT4_O_I3 O=L8_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I2=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I3=R8_LUT4_I3_16_O_LUT4_I2_O O=L8_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_17_O_LUT4_I2_O I1=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_16_O_LUT4_I2_2_O I3=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 O=L8_LUT4_I3_4_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I2=R8_LUT4_I3_16_O_LUT4_I2_O I3=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_17_O_LUT4_I2_O I1=L8_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_16_O_LUT4_I2_2_O I3=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 O=L8_LUT4_I3_4_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I1_3_I3_LUT4_O_I1 I1=L8_LUT4_I3_4_I1_LUT4_O_I1 I2=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_I0_O I3=L8_LUT4_I3_4_I1_LUT4_O_I3 O=L8_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0 I1=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_16_O_LUT4_I2_O I3=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=R8_LUT4_I3_12_O I1=R8_LUT4_I3_14_O I2=R8_LUT4_I3_13_O I3=R8_LUT4_I3_15_O O=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_14_O I1=R8_LUT4_I3_13_O I2=R8_LUT4_I3_15_O I3=R8_LUT4_I3_12_O O=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=R8_LUT4_I3_16_O_LUT4_I2_2_O I2=R8_LUT4_I3_17_O_LUT4_I2_O I3=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_4_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I1=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_17_O_LUT4_I2_O I3=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R8_LUT4_I3_13_O I1=R8_LUT4_I3_14_O I2=R8_LUT4_I3_15_O I3=R8_LUT4_I3_12_O O=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_13_O I1=R8_LUT4_I3_12_O I2=R8_LUT4_I3_15_O I3=R8_LUT4_I3_14_O O=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=R8_LUT4_I3_16_O_LUT4_I2_1_O I2=R8_LUT4_I3_16_O_LUT4_I2_2_O I3=L8_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_4_I2_LUT4_O_I1 I2=L8_LUT4_I3_4_I2_LUT4_O_I2 I3=L8_LUT4_I3_4_I2_LUT4_O_I3 O=L8_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=R8_LUT4_I3_16_O_LUT4_I2_2_O I2=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R8_LUT4_I3_16_O_LUT4_I2_O O=L8_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=L8_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I0 I3=R8_LUT4_I3_17_O_LUT4_I2_O O=L8_LUT4_I3_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_16_O_LUT4_I2_O I3=L8_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_17_O_LUT4_I2_O I3=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=L8_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=R8_LUT4_I3_16_O_LUT4_I2_2_O I3=L8_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_16_O_LUT4_I2_1_O I1=L8_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 I2=L8_LUT4_I1_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_16_O_LUT4_I2_O O=L8_LUT4_I3_4_I0_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_15_O I1=R8_LUT4_I3_14_O I2=R8_LUT4_I3_13_O I3=R8_LUT4_I3_12_O O=L8_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I1_3_I2_LUT4_O_I3 I2=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L8_LUT4_I3_5_I0 I1=L8_LUT4_I3_5_I1 I2=L8_LUT4_I3_5_I2 I3=L8(29) O=R9_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L8_LUT4_I3_5_I0_LUT4_O_I0 I1=L8_LUT4_I1_7_I3_LUT4_O_I2 I2=L8_LUT4_I3_8_I1_LUT4_O_I3 I3=L8_LUT4_I3_8_I1_LUT4_O_I2 O=L8_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_5_I1_LUT4_O_I1 I2=L8_LUT4_I3_5_I1_LUT4_O_I2 I3=R8_LUT4_I3_28_O_LUT4_I2_2_O O=L8_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_28_O_LUT4_I2_O O=L8_LUT4_I3_5_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_28_O_LUT4_I2_1_O I3=L8_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 O=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_27_O I1=R8_LUT4_I3_25_O I2=R8_LUT4_I3_24_O I3=R8_LUT4_I3_26_O O=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_26_O I1=R8_LUT4_I3_27_O I2=R8_LUT4_I3_25_O I3=R8_LUT4_I3_24_O O=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_24_O I1=R8_LUT4_I3_26_O I2=R8_LUT4_I3_25_O I3=R8_LUT4_I3_27_O O=L8_LUT4_I3_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_5_I2 I2=L8_LUT4_I3_5_I2_LUT4_I1_I2 I3=L8_LUT4_I3_8_I1_LUT4_O_I1 O=L8_LUT4_I1_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_5_I2_LUT4_I1_I2_LUT4_O_I1 I2=L8_LUT4_I3_5_I1_LUT4_O_I2 I3=R8_LUT4_I3_28_O_LUT4_I2_O O=L8_LUT4_I3_5_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_5_I2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_28_O_LUT4_I2_2_O O=L8_LUT4_I3_5_I2_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_28_O_LUT4_I2_1_O I3=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_5_I2_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_5_I1_LUT4_O_I2 I2=L8_LUT4_I3_5_I2 I3=L8_LUT4_I3_5_I2_LUT4_I2_I3 O=L8_LUT4_I3_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_5_I2_LUT4_I2_I3_LUT4_O_I1 I2=L8_LUT4_I3_10_I1_LUT4_O_I1 I3=R8_LUT4_I3_28_O_LUT4_I2_2_O O=L8_LUT4_I3_5_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_28_O_LUT4_I2_1_O I1=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_28_O_LUT4_I2_O I3=L8_LUT4_I3_10_I1_LUT4_O_I3_LUT4_O_I2 O=L8_LUT4_I3_5_I2_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_5_I2_LUT4_O_I2 I3=L8_LUT4_I3_5_I2_LUT4_O_I3 O=L8_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I0 I1=R8_LUT4_I3_28_O_LUT4_I2_1_O I2=R8_LUT4_I3_28_O_LUT4_I2_O I3=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_27_O I1=R8_LUT4_I3_26_O I2=R8_LUT4_I3_24_O I3=R8_LUT4_I3_25_O O=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_26_O I1=R8_LUT4_I3_24_O I2=R8_LUT4_I3_25_O I3=R8_LUT4_I3_27_O O=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_28_O_LUT4_I2_2_O I3=L8_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_25_O I1=R8_LUT4_I3_24_O I2=R8_LUT4_I3_27_O I3=R8_LUT4_I3_26_O O=L8_LUT4_I3_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I3_6_I0 I1=L8_LUT4_I3_6_I1 I2=L8_LUT4_I3_6_I2 I3=L8(31) O=R9_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L8_LUT4_I3_9_I0_LUT4_O_I0 I1=L8_LUT4_I3_6_I0_LUT4_O_I1 I2=L8_LUT4_I3_6_I0_LUT4_O_I2 I3=L8_LUT4_I3_1_I1_LUT4_O_I3 O=L8_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=L8_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I1=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_40_O I3=R8_LUT4_I3_41_O O=L8_LUT4_I3_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=R8_LUT4_I3_41_O_LUT4_I2_O I1=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_2_O I3=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_39_O I1=R8_LUT4_I3_37_O I2=R8_LUT4_I3_36_O I3=R8_LUT4_I3_38_O O=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_39_O I1=R8_LUT4_I3_38_O I2=R8_LUT4_I3_37_O I3=R8_LUT4_I3_36_O O=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_6_I1_LUT4_O_I1 I2=L8_LUT4_I3_6_I1_LUT4_O_I2 I3=L8_LUT4_I3_6_I1_LUT4_O_I3 O=L8_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_40_O_LUT4_I2_2_O O=L8_LUT4_I3_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_39_O I1=R8_LUT4_I3_38_O I2=R8_LUT4_I3_36_O I3=R8_LUT4_I3_37_O O=L8_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_38_O I1=R8_LUT4_I3_36_O I2=R8_LUT4_I3_37_O I3=R8_LUT4_I3_39_O O=L8_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_41_O_LUT4_I2_O I1=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_38_O I1=R8_LUT4_I3_37_O I2=R8_LUT4_I3_39_O I3=R8_LUT4_I3_36_O O=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_38_O I1=R8_LUT4_I3_39_O I2=R8_LUT4_I3_37_O I3=R8_LUT4_I3_36_O O=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I1=R8_LUT4_I3_41_O_LUT4_I2_O I2=L8_LUT4_I3_9_I1_LUT4_O_I1 I3=L8_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R8_LUT4_I3_39_O I1=R8_LUT4_I3_38_O I2=R8_LUT4_I3_37_O I3=R8_LUT4_I3_36_O O=L8_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1 I3=R8_LUT4_I3_40_O_LUT4_I2_1_O O=L8_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_40_O_LUT4_I2_2_O I3=L8_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_6_I2 I2=L8_LUT4_I3_1_I2_LUT4_O_I2 I3=L8_LUT4_I3_18_I1_LUT4_O_I3 O=L8_LUT4_I3_9_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_6_I2_LUT4_O_I2 I3=L8_LUT4_I3_6_I2_LUT4_O_I3 O=L8_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_2_O I1=L8_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I1 O=L8_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_41_O_LUT4_I2_O O=L8_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_39_O I1=R8_LUT4_I3_38_O I2=R8_LUT4_I3_37_O I3=R8_LUT4_I3_36_O O=L8_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_41_O_LUT4_I2_O I3=L8_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_39_O I1=R8_LUT4_I3_38_O I2=R8_LUT4_I3_37_O I3=R8_LUT4_I3_36_O O=L8_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I3_7_I0 I1=L8_LUT4_I3_I0 I2=L8_LUT4_I3_7_I2 I3=L8(28) O=R9_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_12_I2 I2=L8_LUT4_I3_I2_LUT4_O_I2 I3=L8_LUT4_I3_7_I0_LUT4_O_I3 O=L8_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_I2_LUT4_O_I1 O=L8_LUT4_I3_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_1_O I1=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 O=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_2_O I1=L8_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I2=L8_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R8_LUT4_I3_22_O_LUT4_I2_1_O O=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I2=L8_LUT4_I3_12_I2_LUT4_O_I3 I3=R8_LUT4_I3_22_O_LUT4_I2_O O=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_21_O I1=R8_LUT4_I3_20_O I2=R8_LUT4_I3_19_O I3=R8_LUT4_I3_18_O O=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2 I2=L8_LUT4_I3_15_I2_LUT4_I3_I1_LUT4_O_I3 I3=R8_LUT4_I3_22_O_LUT4_I2_2_O O=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_7_I2_LUT4_O_I1 I2=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O I3=L8_LUT4_I3_I0_LUT4_O_I2 O=L8_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_22_O_LUT4_I2_O O=L8_LUT4_I3_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_22_O_LUT4_I2_1_O O=L8_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L8_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=R8_LUT4_I3_22_O_LUT4_I2_2_O I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_19_O I1=R8_LUT4_I3_20_O I2=R8_LUT4_I3_21_O I3=R8_LUT4_I3_18_O O=L8_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I3_8_I0 I1=L8_LUT4_I3_8_I1 I2=L8_LUT4_I3_8_I2 I3=L8(4) O=R9_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_8_I0_LUT4_O_I2 I3=L8_LUT4_I1_7_I2_LUT4_O_I3 O=L8_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2 I2=L8_LUT4_I3_8_I0_LUT4_O_I2 I3=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_I2_I3 O=L8_LUT4_I3_10_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_28_O_LUT4_I2_2_O I1=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I3=R8_LUT4_I3_28_O_LUT4_I2_O O=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_25_O I1=R8_LUT4_I3_26_O I2=R8_LUT4_I3_27_O I3=R8_LUT4_I3_24_O O=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_28_O_LUT4_I2_1_O I3=L8_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I0 O=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_8_I1_LUT4_O_I1 I2=L8_LUT4_I3_8_I1_LUT4_O_I2 I3=L8_LUT4_I3_8_I1_LUT4_O_I3 O=L8_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_10_I1_LUT4_O_I1 I3=R8_LUT4_I3_29_O_LUT4_I2_O O=L8_LUT4_I3_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_28_O_LUT4_I2_O O=L8_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_28_O_LUT4_I2_2_O I1=L8_LUT4_I1_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_28_O_LUT4_I2_1_O I3=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_10_I1_LUT4_O_I1 I3=R8_LUT4_I3_28_O_LUT4_I2_O O=L8_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_5_I1_LUT4_O_I2 I3=R8_LUT4_I3_28_O_LUT4_I2_1_O O=L8_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I1_7_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_28_O_LUT4_I2_2_O I3=L8_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_8_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_8_I2_LUT4_O_I2 I3=L8_LUT4_I3_8_I2_LUT4_O_I3 O=L8_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L8_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I0 I1=R8_LUT4_I3_28_O_LUT4_I2_O I2=R8_LUT4_I3_28_O_LUT4_I2_2_O I3=L8_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_27_O I1=R8_LUT4_I3_26_O I2=R8_LUT4_I3_25_O I3=R8_LUT4_I3_24_O O=L8_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3 I1=L8_LUT4_I3_5_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_29_O I3=R8_LUT4_I3_28_O O=L8_LUT4_I3_8_I0_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=R8_LUT4_I3_27_O I1=R8_LUT4_I3_26_O I2=R8_LUT4_I3_25_O I3=R8_LUT4_I3_24_O O=L8_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R8_LUT4_I3_29_O_LUT4_I2_O I1=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_28_O_LUT4_I2_1_O O=L8_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_27_O I1=R8_LUT4_I3_24_O I2=R8_LUT4_I3_25_O I3=R8_LUT4_I3_26_O O=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_27_O I1=R8_LUT4_I3_25_O I2=R8_LUT4_I3_26_O I3=R8_LUT4_I3_24_O O=L8_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L8_LUT4_I3_9_I0 I1=L8_LUT4_I3_9_I1 I2=L8_LUT4_I3_9_I2 I3=L8(9) O=R9_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=L8_LUT4_I3_9_I0_LUT4_O_I0 I1=L8_LUT4_I3_9_I0_LUT4_O_I1 I2=L8_LUT4_I3_9_I0_LUT4_O_I2 I3=L8_LUT4_I3_9_I0_LUT4_O_I3 O=L8_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_1_I1_LUT4_O_I3 I1=L8_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1 I2=L8_LUT4_I3_1_I1_LUT4_O_I2 I3=L8_LUT4_I3_9_I2_LUT4_O_I2 O=L8_LUT4_I3_9_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_2_O I3=L8_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 O=L8_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=L8_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_40_O_LUT4_I2_1_O O=L8_LUT4_I3_9_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_41_O_LUT4_I2_O O=L8_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_2_O I1=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1 O=L8_LUT4_I3_9_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_41_O_LUT4_I2_O I1=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_9_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_36_O I1=R8_LUT4_I3_38_O I2=R8_LUT4_I3_37_O I3=R8_LUT4_I3_39_O O=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_37_O I1=R8_LUT4_I3_36_O I2=R8_LUT4_I3_39_O I3=R8_LUT4_I3_38_O O=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_40_O_LUT4_I2_2_O O=L8_LUT4_I3_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_38_O I1=R8_LUT4_I3_37_O I2=R8_LUT4_I3_36_O I3=R8_LUT4_I3_39_O O=L8_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_37_O I1=R8_LUT4_I3_38_O I2=R8_LUT4_I3_39_O I3=R8_LUT4_I3_36_O O=L8_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L8_LUT4_I3_9_I1_LUT4_O_I0 I1=L8_LUT4_I3_9_I1_LUT4_O_I1 I2=L8_LUT4_I3_9_I1_LUT4_O_I2 I3=L8_LUT4_I3_9_I1_LUT4_O_I3 O=L8_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_6_I0_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_41_O_LUT4_I2_O I1=L8_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_2_O I3=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I0 O=L8_LUT4_I3_9_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_41_O_LUT4_I2_O I1=L8_LUT4_I3_1_I0_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_9_I1_LUT4_O_I2 I3=L8_LUT4_I3_9_I1_LUT4_O_I3 O=L8_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_40_O_LUT4_I2_1_O I3=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_39_O I1=R8_LUT4_I3_36_O I2=R8_LUT4_I3_37_O I3=R8_LUT4_I3_38_O O=L8_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R8_LUT4_I3_41_O_LUT4_I2_O I1=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3 I2=L8_LUT4_I3_6_I1_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_40_O_LUT4_I2_2_O O=L8_LUT4_I3_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_9_I2_LUT4_O_I2 I3=L8_LUT4_I3_1_I1_LUT4_O_I3 O=L8_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_41_O_LUT4_I2_O I1=L8_LUT4_I3_9_I0_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_40_O_LUT4_I2_2_O O=L8_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_40_O_LUT4_I2_O I1=L8_LUT4_I3_9_I0_LUT4_O_I2_LUT4_O_I3 I2=L8_LUT4_I3_6_I1_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_40_O_LUT4_I2_1_O O=L8_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I1=L8_LUT4_I3_I0_LUT4_O_I1 I2=L8_LUT4_I3_I0_LUT4_O_I2 I3=L8_LUT4_I3_I0_LUT4_O_I3 O=L8_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_7_I2_LUT4_O_I1 O=L8_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=L8_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_1_O I1=L8_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=L8_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 I3=R8_LUT4_I3_23_O_LUT4_I2_O O=L8_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R8_LUT4_I3_22_O_LUT4_I2_2_O I3=L8_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=L8_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R8_LUT4_I3_22_O_LUT4_I2_1_O I3=L8_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L8_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_2_O I1=L8_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_12_I2_LUT4_O_I1_LUT4_O_I2 O=L8_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I1=L8_LUT4_I3_I1_LUT4_O_I1 I2=L8_LUT4_I3_I0_LUT4_O_I1 I3=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L8_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L8_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=L8_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L8_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_22_O_LUT4_I2_1_O I3=L8_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_20_O I1=R8_LUT4_I3_19_O I2=R8_LUT4_I3_18_O I3=R8_LUT4_I3_21_O O=L8_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_2_O I1=L8_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_15_I2_LUT4_I3_I2_LUT4_O_I1 O=L8_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L8_LUT4_I3_I2_LUT4_O_I0 I1=L8_LUT4_I3_I2_LUT4_O_I1 I2=L8_LUT4_I3_I2_LUT4_O_I2 I3=L8_LUT4_I3_I2_LUT4_O_I3 O=L8_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I1=L8_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=R8_LUT4_I3_22_O I3=R8_LUT4_I3_23_O O=L8_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R8_LUT4_I3_21_O I1=R8_LUT4_I3_19_O I2=R8_LUT4_I3_20_O I3=R8_LUT4_I3_18_O O=L8_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_22_O_LUT4_I2_2_O O=L8_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_15_I2_LUT4_I3_I1_LUT4_O_I3 I3=R8_LUT4_I3_22_O_LUT4_I2_1_O O=L8_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_21_O I1=R8_LUT4_I3_20_O I2=R8_LUT4_I3_19_O I3=R8_LUT4_I3_18_O O=L8_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L8_LUT4_I3_12_I2_LUT4_O_I3 I1=R8_LUT4_I3_22_O_LUT4_I2_1_O I2=L8_LUT4_I3_15_I0_LUT4_O_I1 I3=L8_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=L8_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R8_LUT4_I3_23_O_LUT4_I2_O I3=L8_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=L8_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=L8_LUT4_I3_15_I2_LUT4_I3_I2_LUT4_O_I1 I3=R8_LUT4_I3_22_O_LUT4_I2_2_O O=L8_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_18_O I1=R8_LUT4_I3_20_O I2=R8_LUT4_I3_19_O I3=R8_LUT4_I3_21_O O=L8_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_22_O_LUT4_I2_2_O O=L8_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_21_O I1=R8_LUT4_I3_19_O I2=R8_LUT4_I3_18_O I3=R8_LUT4_I3_20_O O=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_1_O I1=L8_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I1 I2=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=R8_LUT4_I3_23_O_LUT4_I2_O O=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1 I2=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=L8_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I1_O O=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R8_LUT4_I3_22_O_LUT4_I2_O I1=L8_LUT4_I3_15_I2_LUT4_O_I1_LUT4_O_I1 I2=L8_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R8_LUT4_I3_22_O_LUT4_I2_2_O O=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R8_LUT4_I3_21_O I1=R8_LUT4_I3_20_O I2=R8_LUT4_I3_19_O I3=R8_LUT4_I3_18_O O=L8_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=L8(1) D=R7(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(2) D=R7(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(11) D=R7(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(12) D=R7(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(13) D=R7(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(14) D=R7(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(15) D=R7(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(16) D=R7(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(17) D=R7(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(18) D=R7(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(19) D=R7(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(20) D=R7(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(3) D=R7(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(21) D=R7(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(22) D=R7(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(23) D=R7(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(24) D=R7(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(25) D=R7(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(26) D=R7(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(27) D=R7(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(28) D=R7(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(29) D=R7(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(30) D=R7(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(4) D=R7(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(31) D=R7(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(32) D=R7(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(5) D=R7(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(6) D=R7(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(7) D=R7(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(8) D=R7(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(9) D=R7(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L8(10) D=R7(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:161.1-162.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=K1(1) I1=L9(10) I2=L9_LUT4_I1_I2 I3=L9_LUT4_I1_I3 O=R10_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L9(22) I2=L9_LUT4_I1_1_I2 I3=L9_LUT4_I1_1_I3 O=R10_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_1_I2_LUT4_O_I1 I2=L9_LUT4_I1_1_I2_LUT4_O_I2 I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_I2_O O=L9_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I1_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_1_O I1=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_46_O_LUT4_I2_O I3=L9_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_45_O I1=R9_LUT4_I3_44_O I2=R9_LUT4_I3_43_O I3=R9_LUT4_I3_42_O O=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R9_LUT4_I3_46_O_LUT4_I2_2_O I3=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_42_O I1=R9_LUT4_I3_44_O I2=R9_LUT4_I3_43_O I3=R9_LUT4_I3_45_O O=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_47_O_LUT4_I2_O O=L9_LUT4_I1_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_46_O_LUT4_I2_O O=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_2_O I1=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_46_O_LUT4_I2_1_O I3=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_45_O I1=R9_LUT4_I3_43_O I2=R9_LUT4_I3_44_O I3=R9_LUT4_I3_42_O O=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_43_O I1=R9_LUT4_I3_44_O I2=R9_LUT4_I3_45_O I3=R9_LUT4_I3_42_O O=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L9_LUT4_I1_1_I3_LUT4_O_I0 I1=L9_LUT4_I1_1_I3_LUT4_O_I1 I2=L9_LUT4_I1_4_I3_LUT4_O_I3 I3=L9_LUT4_I1_1_I3_LUT4_O_I3 O=L9_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2 I3=L9_LUT4_I1_4_I2_LUT4_O_I3 O=L9_LUT4_I1_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0 I2=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_46_O_LUT4_I2_1_O O=L9_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0 I1=L9_LUT4_I3_21_I2_LUT4_O_I3 I2=L9_LUT4_I1_4_I2_LUT4_O_I2 I3=L9_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L9_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_47_O I3=R9_LUT4_I3_46_O O=L9_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100111111
+.subckt LUT4 I0=K1(1) I1=R9_LUT4_I3_46_O_LUT4_I2_1_O I2=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I1_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_I2_O I1=L9_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I1_1_I2_LUT4_O_I2 I3=L9_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2 I2=R9_LUT4_I3_47_O I3=R9_LUT4_I3_46_O O=L9_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_46_O_LUT4_I2_O I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_44_O I1=R9_LUT4_I3_43_O I2=R9_LUT4_I3_42_O I3=R9_LUT4_I3_45_O O=L9_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L9(1) I2=L9_LUT4_I1_2_I2 I3=L9_LUT4_I1_2_I3 O=R10_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_2_I2_LUT4_O_I1 I2=L9_LUT4_I1_2_I2_LUT4_O_I2 I3=L9_LUT4_I1_2_I2_LUT4_O_I3 O=L9_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I1_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_2_O I1=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_6_O_LUT4_I2_O I3=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_11_O I1=R9_LUT4_I3_9_O I2=R9_LUT4_I3_8_O I3=R9_LUT4_I3_10_O O=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_7_O_LUT4_I2_O I1=L9_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R9_LUT4_I3_6_O_LUT4_I2_1_O I3=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_9_O I1=R9_LUT4_I3_8_O I2=R9_LUT4_I3_11_O I3=R9_LUT4_I3_10_O O=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_2_O I1=L9_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R9_LUT4_I3_6_O_LUT4_I2_O I3=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_7_O_LUT4_I2_O I1=L9_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R9_LUT4_I3_6_O_LUT4_I2_1_O I3=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_7_O_LUT4_I2_O I1=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2 I2=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0 I3=L9_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_1_O O=L9_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_2_O I1=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_6_O_LUT4_I2_O I3=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_11_O I1=R9_LUT4_I3_10_O I2=R9_LUT4_I3_8_O I3=R9_LUT4_I3_9_O O=L9_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_I2_LUT4_O_I2 I2=L9_LUT4_I1_2_I3_LUT4_O_I2 I3=L9_LUT4_I1_I3_LUT4_O_I3 O=L9_LUT4_I1_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_O O=L9_LUT4_I1_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_6_O_LUT4_I2_1_O I3=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 O=L9_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I1=R9_LUT4_I3_7_O_LUT4_I2_O I2=R9_LUT4_I3_6_O_LUT4_I2_2_O I3=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9(5) I2=L9_LUT4_I1_3_I2 I3=L9_LUT4_I1_3_I3 O=R10_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_3_I2_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I3 I3=L9_LUT4_I3_6_I2_LUT4_O_I1 O=L9_LUT4_I1_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1 I3=L9_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I1_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_O I1=L9_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=R9_LUT4_I3_17_O_LUT4_I2_O O=L9_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_15_O I1=R9_LUT4_I3_14_O I2=R9_LUT4_I3_13_O I3=R9_LUT4_I3_12_O O=L9_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L9_LUT4_I1_3_I3_LUT4_O_I0 I1=L9_LUT4_I1_3_I3_LUT4_O_I1 I2=L9_LUT4_I1_3_I3_LUT4_O_I2 I3=L9_LUT4_I1_3_I3_LUT4_O_I3 O=L9_LUT4_I1_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2 I3=L9_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3 O=L9_LUT4_I1_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_16_O_LUT4_I2_O I3=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_17_O_LUT4_I2_O I1=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_16_O_LUT4_I2_2_O I3=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_3_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I1_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_O I1=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_16_O_LUT4_I2_2_O I3=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 O=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_15_O I1=R9_LUT4_I3_13_O I2=R9_LUT4_I3_14_O I3=R9_LUT4_I3_12_O O=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_17_O_LUT4_I2_O O=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_15_O I1=R9_LUT4_I3_14_O I2=R9_LUT4_I3_13_O I3=R9_LUT4_I3_12_O O=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I2=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I3_O I3=L9_LUT4_I3_5_I1_LUT4_I3_O O=L9_LUT4_I1_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L9_LUT4_I3_6_I1_LUT4_O_I3 I1=L9_LUT4_I3_5_I1_LUT4_I3_O I2=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I3=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_17_O_LUT4_I2_O I1=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=R9_LUT4_I3_16_O_LUT4_I2_2_O I3=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I2 I3=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3 O=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I2=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R9_LUT4_I3_17_O_LUT4_I2_O O=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_O I1=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_16_O_LUT4_I2_2_O O=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9(7) I2=L9_LUT4_I1_4_I2 I3=L9_LUT4_I1_4_I3 O=R10_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_4_I2_LUT4_O_I1 I2=L9_LUT4_I1_4_I2_LUT4_O_I2 I3=L9_LUT4_I1_4_I2_LUT4_O_I3 O=L9_LUT4_I1_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_21_I2_LUT4_O_I1 I2=L9_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_12_I1_LUT4_O_I3 O=L9_LUT4_I1_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 I3=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I0 O=L9_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0 I1=R9_LUT4_I3_46_O_LUT4_I2_O I2=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=R9_LUT4_I3_44_O I1=R9_LUT4_I3_43_O I2=R9_LUT4_I3_45_O I3=R9_LUT4_I3_42_O O=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_45_O I1=R9_LUT4_I3_44_O I2=R9_LUT4_I3_43_O I3=R9_LUT4_I3_42_O O=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I1_1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R9_LUT4_I3_46_O_LUT4_I2_1_O O=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_45_O I1=R9_LUT4_I3_44_O I2=R9_LUT4_I3_43_O I3=R9_LUT4_I3_42_O O=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_2_O I1=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I2=L9_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0 I3=R9_LUT4_I3_46_O_LUT4_I2_1_O O=L9_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_46_O_LUT4_I2_O I3=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_4_I3_LUT4_O_I1 I2=L9_LUT4_I1_4_I3_LUT4_O_I2 I3=L9_LUT4_I1_4_I3_LUT4_O_I3 O=L9_LUT4_I1_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I2 I2=L9_LUT4_I1_4_I3_LUT4_O_I1 I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_I2_I3 O=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I2=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_46_O_LUT4_I2_1_O O=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I1_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_1_O I1=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_46_O_LUT4_I2_O I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_44_O I1=R9_LUT4_I3_45_O I2=R9_LUT4_I3_43_O I3=R9_LUT4_I3_42_O O=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_45_O I1=R9_LUT4_I3_44_O I2=R9_LUT4_I3_42_O I3=R9_LUT4_I3_43_O O=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_46_O_LUT4_I2_2_O I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_43_O I1=R9_LUT4_I3_42_O I2=R9_LUT4_I3_45_O I3=R9_LUT4_I3_44_O O=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_45_O I1=R9_LUT4_I3_42_O I2=R9_LUT4_I3_43_O I3=R9_LUT4_I3_44_O O=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_2_O I1=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_46_O_LUT4_I2_1_O I3=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_45_O I1=R9_LUT4_I3_44_O I2=R9_LUT4_I3_43_O I3=R9_LUT4_I3_42_O O=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_46_O_LUT4_I2_O I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_44_O I1=R9_LUT4_I3_42_O I2=R9_LUT4_I3_43_O I3=R9_LUT4_I3_45_O O=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I1_4_I3_LUT4_O_I2 I3=L9_LUT4_I3_21_I1_LUT4_O_I1 O=L9_LUT4_I1_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=R9_LUT4_I3_47_O_LUT4_I2_O I2=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=L9_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=R9_LUT4_I3_46_O_LUT4_I2_2_O I2=R9_LUT4_I3_46_O_LUT4_I2_1_O I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9(19) I2=L9_LUT4_I1_5_I2 I3=L9_LUT4_I1_5_I3 O=R10_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=L9_LUT4_I3_1_I1 I1=L9_LUT4_I3_3_I2_LUT4_O_I3 I2=L9_LUT4_I1_5_I2_LUT4_O_I2 I3=L9_LUT4_I1_5_I2_LUT4_O_I3 O=L9_LUT4_I1_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R9_LUT4_I3_29_O_LUT4_I2_O I1=L9_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I2=L9_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_28_O_LUT4_I2_1_O O=L9_LUT4_I1_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_26_O I1=R9_LUT4_I3_27_O I2=R9_LUT4_I3_25_O I3=R9_LUT4_I3_24_O O=L9_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_O I1=L9_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I2=L9_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_28_O_LUT4_I2_2_O O=L9_LUT4_I1_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_25_O I1=R9_LUT4_I3_26_O I2=R9_LUT4_I3_27_O I3=R9_LUT4_I3_24_O O=L9_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_5_I3_LUT4_O_I1 I2=L9_LUT4_I3_3_I1 I3=L9_LUT4_I1_5_I3_LUT4_O_I3 O=L9_LUT4_I1_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_7_I0_LUT4_O_I3 I2=L9_LUT4_I3_7_I1_LUT4_I0_I2 I3=L9_LUT4_I3_1_I2_LUT4_O_I2 O=L9_LUT4_I1_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=L9(28) I2=L9_LUT4_I1_6_I2 I3=L9_LUT4_I1_6_I3 O=R10_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=L9_LUT4_I1_6_I2_LUT4_O_I0 I1=L9_LUT4_I3_I0_LUT4_O_I2 I2=L9_LUT4_I1_6_I2_LUT4_O_I2 I3=L9_LUT4_I1_6_I2_LUT4_O_I3 O=L9_LUT4_I1_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_4_I0_LUT4_O_I1 I2=L9_LUT4_I3_4_I0_LUT4_O_I0 I3=L9_LUT4_I3_I0_LUT4_O_I0 O=L9_LUT4_I1_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=R9_LUT4_I3_23_O_LUT4_I3_2_O I3=L9_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I1 O=L9_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I2_O I1=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I3=R9_LUT4_I3_23_O_LUT4_I3_1_O O=L9_LUT4_I1_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I2 O=L9_LUT4_I1_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_I2_LUT4_O_I0 I2=R9_LUT4_I3_23_O_LUT4_I3_1_O I3=L9_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_14_I2 I1=L9_LUT4_I1_6_I3_LUT4_O_I1 I2=L9_LUT4_I3_I2 I3=L9_LUT4_I3_I0_LUT4_O_I3 O=L9_LUT4_I1_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I1_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_23_O_LUT4_I3_1_O O=L9_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_2_O I1=L9_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_23_O_LUT4_I2_O O=L9_LUT4_I1_6_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I1_I2_LUT4_O_I0 I1=L9_LUT4_I1_I2_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I2 I3=L9_LUT4_I1_I2_LUT4_O_I3 O=L9_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_1_O O=L9_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_6_O_LUT4_I2_2_O O=L9_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_O I1=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_7_O_LUT4_I2_O O=L9_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_11_O I1=R9_LUT4_I3_10_O I2=R9_LUT4_I3_9_O I3=R9_LUT4_I3_8_O O=L9_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_O O=L9_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_7_O_LUT4_I2_O O=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_2_O I1=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I2=R9_LUT4_I3_6_O_LUT4_I2_1_O I3=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_10_O I1=R9_LUT4_I3_9_O I2=R9_LUT4_I3_11_O I3=R9_LUT4_I3_8_O O=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_11_O I1=R9_LUT4_I3_10_O I2=R9_LUT4_I3_9_O I3=R9_LUT4_I3_8_O O=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_1_O O=L9_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_O O=L9_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_2_O I1=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_7_O_LUT4_I2_O I3=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 O=L9_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_10_O I1=R9_LUT4_I3_8_O I2=R9_LUT4_I3_9_O I3=R9_LUT4_I3_11_O O=L9_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_O I1=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_6_O_LUT4_I2_1_O I3=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_11_O I1=R9_LUT4_I3_8_O I2=R9_LUT4_I3_9_O I3=R9_LUT4_I3_10_O O=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_9_O I1=R9_LUT4_I3_10_O I2=R9_LUT4_I3_11_O I3=R9_LUT4_I3_8_O O=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_2_O I1=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_7_O_LUT4_I2_O I3=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_11_O I1=R9_LUT4_I3_10_O I2=R9_LUT4_I3_9_O I3=R9_LUT4_I3_8_O O=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_10_O I1=R9_LUT4_I3_9_O I2=R9_LUT4_I3_8_O I3=R9_LUT4_I3_11_O O=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L9_LUT4_I1_I3_LUT4_O_I0 I1=L9_LUT4_I1_I3_LUT4_O_I1 I2=L9_LUT4_I1_I3_LUT4_O_I2 I3=L9_LUT4_I1_I3_LUT4_O_I3 O=L9_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=L9_LUT4_I1_2_I3_LUT4_O_I2 I1=L9_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I2=L9_LUT4_I3_15_I1_LUT4_O_I2 I3=L9_LUT4_I1_I2_LUT4_O_I3 O=L9_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R9_LUT4_I3_7_O_LUT4_I2_O O=L9_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_6_O_LUT4_I2_O O=L9_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I1=R9_LUT4_I3_6_O_LUT4_I2_1_O I2=R9_LUT4_I3_6_O_LUT4_I2_2_O I3=L9_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L9_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0 I1=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_7_O I3=R9_LUT4_I3_6_O O=L9_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010111110011
+.subckt LUT4 I0=R9_LUT4_I3_11_O I1=R9_LUT4_I3_9_O I2=R9_LUT4_I3_10_O I3=R9_LUT4_I3_8_O O=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_11_O I1=R9_LUT4_I3_10_O I2=R9_LUT4_I3_9_O I3=R9_LUT4_I3_8_O O=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0 I1=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_15_I2_LUT4_O_I2 I3=L9_LUT4_I1_2_I2_LUT4_O_I2 O=L9_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_7_O_LUT4_I2_O I1=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_6_O_LUT4_I2_1_O I3=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_2_O I1=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R9_LUT4_I3_6_O_LUT4_I2_O I3=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_10_O I1=R9_LUT4_I3_11_O I2=R9_LUT4_I3_9_O I3=R9_LUT4_I3_8_O O=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_7_O_LUT4_I2_O I1=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_6_O_LUT4_I2_1_O I3=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I1_I2_LUT4_O_I0 I1=L9_LUT4_I3_20_I2_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I1 I3=L9_LUT4_I1_I2_LUT4_O_I2 O=L9_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9(14) I3=L9_LUT4_I2_I3 O=R10_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9(17) I3=L9_LUT4_I2_1_I3 O=R10_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=L9_LUT4_I2_1_I3_LUT4_O_I0 I1=L9_LUT4_I2_1_I3_LUT4_O_I1 I2=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=L9_LUT4_I2_1_I3_LUT4_O_I3 O=L9_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=L9_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I0 I1=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 I3=L9_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3 O=L9_LUT4_I2_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=R9_LUT4_I3_40_O_LUT4_I2_O I2=R9_LUT4_I3_40_O_LUT4_I2_1_O I3=L9_LUT4_I3_2_I1_LUT4_O_I1 O=L9_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001101011111
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_2_I0_LUT4_O_I3 I2=R9_LUT4_I3_41_O_LUT4_I2_O I3=L9_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_39_O I1=R9_LUT4_I3_38_O I2=R9_LUT4_I3_36_O I3=R9_LUT4_I3_37_O O=L9_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I2_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_1_O I1=L9_LUT4_I3_2_I0_LUT4_O_I3 I2=L9_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_40_O_LUT4_I2_O O=L9_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_37_O I1=R9_LUT4_I3_38_O I2=R9_LUT4_I3_39_O I3=R9_LUT4_I3_36_O O=L9_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_8_I1_LUT4_O_I2 I2=R9_LUT4_I3_41_O_LUT4_I2_O I3=L9_LUT4_I3_8_I0_LUT4_O_I0 O=L9_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3 I3=L9_LUT4_I3_8_I2_LUT4_O_I0 O=L9_LUT4_I2_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9(30) I3=L9_LUT4_I2_2_I3 O=R10_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=L9_LUT4_I2_2_I3_LUT4_O_I0 I1=L9_LUT4_I3_13_I1 I2=L9_LUT4_I2_2_I3_LUT4_O_I2 I3=L9_LUT4_I2_2_I3_LUT4_O_I3 O=L9_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_18_I1_LUT4_O_I2 I2=L9_LUT4_I3_18_I1_LUT4_O_I3 I3=L9_LUT4_I3_10_I2_LUT4_O_I3 O=L9_LUT4_I2_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_10_I2_LUT4_O_I1 I3=L9_LUT4_I3_18_I2_LUT4_O_I1 O=L9_LUT4_I2_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_O I1=L9_LUT4_I3_10_I1_LUT4_O_I0 I2=L9_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I2_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=L9_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I0 I1=R9_LUT4_I3_34_O_LUT4_I2_2_O I2=R9_LUT4_I3_35_O_LUT4_I2_O I3=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I2_I3_LUT4_O_I0 I1=L9_LUT4_I3_19_I1 I2=L9_LUT4_I2_I3_LUT4_O_I2 I3=L9_LUT4_I2_I3_LUT4_O_I3 O=L9_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=L9_LUT4_I3_19_I1 I1=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1 I2=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=L9_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 I3=R9_LUT4_I3_4_O_LUT4_I2_O O=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1 I3=R9_LUT4_I3_4_O_LUT4_I2_2_O O=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_5_O_LUT4_I2_O I1=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I3 I2=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 I3=R9_LUT4_I3_5_O_LUT4_I2_O O=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_2_O I1=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I3_19_I2_LUT4_I1_I0_LUT4_O_I2 O=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_3_O I1=R9_LUT4_I3_2_O I2=R9_LUT4_I3_1_O I3=R9_LUT4_I3_O O=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0 I1=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_11_I1_LUT4_O_I2 O=L9_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R9_LUT4_I3_5_O_LUT4_I2_O I3=L9_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 O=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_4_O_LUT4_I2_O O=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_2_O I1=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I3 I3=R9_LUT4_I3_4_O_LUT4_I2_1_O O=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_2_O I1=L9_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_5_O_LUT4_I2_O O=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_5_O_LUT4_I2_O I1=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I1 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=R9_LUT4_I3_4_O_LUT4_I2_2_O I3=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 I1=R9_LUT4_I3_4_O_LUT4_I2_2_O I2=L9_LUT4_I3_9_I2_LUT4_O_I1 I3=L9_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R9_LUT4_I3_3_O I1=R9_LUT4_I3_2_O I2=R9_LUT4_I3_1_O I3=R9_LUT4_I3_O O=L9_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=R9_LUT4_I3_4_O_LUT4_I2_O O=L9_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_5_O_LUT4_I2_O I1=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_I0 I1=L9_LUT4_I3_I1 I2=L9_LUT4_I3_I2 I3=L9(2) O=R10_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L9_LUT4_I3_1_I0 I1=L9_LUT4_I3_1_I1 I2=L9_LUT4_I3_1_I2 I3=L9(4) O=R10_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L9_LUT4_I3_10_I0 I1=L9_LUT4_I3_10_I1 I2=L9_LUT4_I3_10_I2 I3=L9(6) O=R10_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_13_I0_LUT4_O_I1 I3=L9_LUT4_I2_2_I3_LUT4_O_I2 O=L9_LUT4_I3_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I3_10_I1_LUT4_O_I0 I1=L9_LUT4_I3_10_I1_LUT4_O_I1 I2=L9_LUT4_I3_10_I1_LUT4_O_I2 I3=L9_LUT4_I3_18_I0_LUT4_O_I3 O=L9_LUT4_I3_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=R9_LUT4_I3_33_O I1=R9_LUT4_I3_32_O I2=R9_LUT4_I3_31_O I3=R9_LUT4_I3_30_O O=L9_LUT4_I3_10_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L9_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I0 I1=L9_LUT4_I3_13_I1_LUT4_O_I3 I2=L9_LUT4_I3_13_I1_LUT4_O_I2 I3=L9_LUT4_I2_2_I3_LUT4_O_I3 O=L9_LUT4_I3_10_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_31_O I3=R9_LUT4_I3_30_O O=L9_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=L9_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I0 I1=L9_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_35_O I3=R9_LUT4_I3_34_O O=L9_LUT4_I3_10_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=K1(1) I1=R9_LUT4_I3_30_O I2=R9_LUT4_I3_31_O I3=L9_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_10_I2_LUT4_O_I1 I2=L9_LUT4_I3_10_I2_LUT4_O_I2 I3=L9_LUT4_I3_10_I2_LUT4_O_I3 O=L9_LUT4_I3_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_13_I0_LUT4_O_I3 I3=L9_LUT4_I3_18_I2_LUT4_O_I3 O=L9_LUT4_I3_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I0 I1=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_34_O_LUT4_I2_2_O I3=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_10_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R9_LUT4_I3_32_O I1=R9_LUT4_I3_31_O I2=R9_LUT4_I3_33_O I3=R9_LUT4_I3_30_O O=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_30_O I1=R9_LUT4_I3_32_O I2=R9_LUT4_I3_31_O I3=R9_LUT4_I3_33_O O=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_35_O_LUT4_I2_O I1=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_34_O_LUT4_I2_1_O I3=L9_LUT4_I3_10_I1_LUT4_O_I0 O=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_O I1=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_18_I1_LUT4_O_I2 I3=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_10_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R9_LUT4_I3_32_O I1=R9_LUT4_I3_31_O I2=R9_LUT4_I3_30_O I3=R9_LUT4_I3_33_O O=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_O I1=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I0 I3=R9_LUT4_I3_35_O_LUT4_I2_O O=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=R9_LUT4_I3_31_O I1=R9_LUT4_I3_32_O I2=R9_LUT4_I3_33_O I3=R9_LUT4_I3_30_O O=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L9_LUT4_I3_9_I0 I1=L9_LUT4_I3_11_I1 I2=L9_LUT4_I3_11_I2 I3=L9(8) O=R10_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_11_I1_LUT4_O_I2 I3=L9_LUT4_I3_11_I1_LUT4_O_I3 O=L9_LUT4_I3_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_4_O_LUT4_I2_2_O O=L9_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_5_O_LUT4_I2_O I1=L9_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1 I3=R9_LUT4_I3_4_O_LUT4_I2_1_O O=L9_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_2_O I1=R9_LUT4_I3_O I2=R9_LUT4_I3_1_O I3=R9_LUT4_I3_3_O O=L9_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2 O=L9_LUT4_I3_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_5_O_LUT4_I2_O I3=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_2_O I1=R9_LUT4_I3_1_O I2=R9_LUT4_I3_O I3=R9_LUT4_I3_3_O O=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_2_O I1=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_1_O I1=R9_LUT4_I3_O I2=R9_LUT4_I3_3_O I3=R9_LUT4_I3_2_O O=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_9_I2_LUT4_O_I1 I2=L9_LUT4_I3_19_I2 I3=L9_LUT4_I3_9_I2_LUT4_O_I2 O=L9_LUT4_I3_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L9_LUT4_I3_21_I0 I1=L9_LUT4_I3_12_I1 I2=L9_LUT4_I3_12_I2 I3=L9(12) O=R10_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=L9_LUT4_I3_12_I1_LUT4_O_I0 I1=L9_LUT4_I1_1_I3_LUT4_O_I0 I2=L9_LUT4_I1_4_I2_LUT4_O_I2 I3=L9_LUT4_I3_12_I1_LUT4_O_I3 O=L9_LUT4_I3_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_4_I2_LUT4_O_I1_LUT4_O_I2 I2=L9_LUT4_I3_21_I2_LUT4_O_I1 I3=L9_LUT4_I3_21_I2_LUT4_O_I3 O=L9_LUT4_I3_12_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I1_1_I3_LUT4_O_I0_LUT4_O_I2 O=L9_LUT4_I3_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_2_O I1=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R9_LUT4_I3_46_O_LUT4_I2_O I3=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I3_12_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_21_I1_LUT4_O_I1 I2=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_I2_O I3=L9_LUT4_I1_1_I3_LUT4_O_I3 O=L9_LUT4_I3_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=L9_LUT4_I3_13_I0 I1=L9_LUT4_I3_13_I1 I2=L9_LUT4_I3_13_I2 I3=L9(16) O=R10_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L9_LUT4_I2_2_I3_LUT4_O_I2 I1=L9_LUT4_I3_13_I0_LUT4_O_I1 I2=L9_LUT4_I2_2_I3_LUT4_O_I0 I3=L9_LUT4_I3_13_I0_LUT4_O_I3 O=L9_LUT4_I3_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_10_I2_LUT4_O_I2 I2=L9_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_10_I2_LUT4_O_I3 O=L9_LUT4_I3_13_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 I1=R9_LUT4_I3_34_O_LUT4_I2_2_O I2=L9_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=L9_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=L9_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I0 I1=R9_LUT4_I3_35_O_LUT4_I2_O I2=R9_LUT4_I3_34_O_LUT4_I2_1_O I3=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I3_13_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_2_O I1=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_35_O_LUT4_I2_O I3=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I0 O=L9_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_1_O I1=L9_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_34_O_LUT4_I2_O O=L9_LUT4_I3_13_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_13_I1_LUT4_O_I1 I2=L9_LUT4_I3_13_I1_LUT4_O_I2 I3=L9_LUT4_I3_13_I1_LUT4_O_I3 O=L9_LUT4_I3_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_13_I1_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_13_I1_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_13_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 I1=R9_LUT4_I3_35_O_LUT4_I2_O I2=R9_LUT4_I3_34_O_LUT4_I2_1_O I3=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_13_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I0 I1=R9_LUT4_I3_34_O_LUT4_I2_O I2=R9_LUT4_I3_34_O_LUT4_I2_2_O I3=L9_LUT4_I3_10_I1_LUT4_O_I0 O=L9_LUT4_I3_13_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_34_O_LUT4_I2_1_O I3=L9_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_13_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_34_O_LUT4_I2_O O=L9_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_33_O I1=R9_LUT4_I3_32_O I2=R9_LUT4_I3_31_O I3=R9_LUT4_I3_30_O O=L9_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I0 I1=R9_LUT4_I3_34_O_LUT4_I2_O I2=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=R9_LUT4_I3_33_O I1=R9_LUT4_I3_31_O I2=R9_LUT4_I3_32_O I3=R9_LUT4_I3_30_O O=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_35_O_LUT4_I2_O I3=L9_LUT4_I3_10_I1_LUT4_O_I1_LUT4_O_I0 O=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_2_O I1=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I0 I2=R9_LUT4_I3_35_O_LUT4_I2_O I3=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_33_O I1=R9_LUT4_I3_31_O I2=R9_LUT4_I3_30_O I3=R9_LUT4_I3_32_O O=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_1_O I1=R9_LUT4_I3_34_O_LUT4_I2_2_O I2=L9_LUT4_I3_13_I2_LUT4_O_I2 I3=L9_LUT4_I3_13_I2_LUT4_O_I3 O=L9_LUT4_I3_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_34_O_LUT4_I2_1_O I3=L9_LUT4_I3_13_I2_LUT4_O_I2 O=L9_LUT4_I2_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_30_O I3=R9_LUT4_I3_31_O O=L9_LUT4_I3_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_32_O I3=R9_LUT4_I3_33_O O=L9_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=L9_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I0 I1=R9_LUT4_I3_34_O_LUT4_I2_2_O I2=R9_LUT4_I3_34_O_LUT4_I2_1_O I3=L9_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_13_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R9_LUT4_I3_30_O I2=L9_LUT4_I3_13_I2_LUT4_O_I2_LUT4_O_I1 I3=R9_LUT4_I3_31_O O=L9_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R9_LUT4_I3_32_O I1=R9_LUT4_I3_30_O I2=R9_LUT4_I3_31_O I3=R9_LUT4_I3_33_O O=L9_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L9_LUT4_I3_14_I0 I1=L9_LUT4_I3_14_I1 I2=L9_LUT4_I3_14_I2 I3=L9(18) O=R10_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_14_I0_LUT4_O_I1 I2=L9_LUT4_I1_6_I2_LUT4_O_I0 I3=L9_LUT4_I3_I0_LUT4_O_I1 O=L9_LUT4_I3_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_14_I0_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_14_I0_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I1_6_I2_LUT4_O_I3 O=L9_LUT4_I3_14_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 I2=R9_LUT4_I3_23_O_LUT4_I3_2_O I3=L9_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_14_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I2_O I1=L9_LUT4_I3_I2_LUT4_O_I0 I2=R9_LUT4_I3_23_O_LUT4_I3_1_O I3=L9_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_14_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_4_I2_LUT4_O_I2 I3=L9_LUT4_I3_I2_LUT4_O_I3 O=L9_LUT4_I3_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I3_I1_LUT4_O_I1 I1=L9_LUT4_I3_I1_LUT4_O_I2 I2=L9_LUT4_I3_14_I2_LUT4_O_I2 I3=L9_LUT4_I3_14_I2_LUT4_O_I3 O=L9_LUT4_I3_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_2_O I1=L9_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_23_O_LUT4_I2_O I3=L9_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_14_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_21_O I1=R9_LUT4_I3_18_O I2=R9_LUT4_I3_19_O I3=R9_LUT4_I3_20_O O=L9_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_23_O_LUT4_I3_1_O I3=L9_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I1 O=L9_LUT4_I3_14_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_20_O I1=R9_LUT4_I3_19_O I2=R9_LUT4_I3_18_O I3=R9_LUT4_I3_21_O O=L9_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L9_LUT4_I3_15_I0 I1=L9_LUT4_I3_15_I1 I2=L9_LUT4_I3_15_I2 I3=L9(20) O=R10_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_I2_LUT4_O_I1 I3=L9_LUT4_I1_I3_LUT4_O_I3 O=L9_LUT4_I3_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_15_I1_LUT4_O_I2 I3=L9_LUT4_I1_2_I3_LUT4_O_I2 O=L9_LUT4_I3_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_15_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_2_O I1=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_1_O O=L9_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_O I1=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_7_O_LUT4_I2_O I3=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_15_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_2_I2_LUT4_O_I1 I2=L9_LUT4_I3_15_I2_LUT4_O_I2 I3=L9_LUT4_I3_20_I2_LUT4_O_I3 O=L9_LUT4_I3_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_2_O I1=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_7_O_LUT4_I2_O I3=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_11_O I1=R9_LUT4_I3_10_O I2=R9_LUT4_I3_9_O I3=R9_LUT4_I3_8_O O=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R9_LUT4_I3_6_O_LUT4_I2_O I1=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_6_O_LUT4_I2_1_O I3=L9_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_8_O I1=R9_LUT4_I3_10_O I2=R9_LUT4_I3_9_O I3=R9_LUT4_I3_11_O O=L9_LUT4_I3_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L9_LUT4_I3_16_I0 I1=L9_LUT4_I3_16_I1 I2=L9_LUT4_I3_16_I2 I3=L9(21) O=R10_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_3_I3_LUT4_O_I1 I2=L9_LUT4_I1_3_I3_LUT4_O_I0 I3=L9_LUT4_I1_3_I3_LUT4_O_I2 O=L9_LUT4_I3_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I3_O I1=L9_LUT4_I3_16_I1_LUT4_O_I1 I2=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I3=L9_LUT4_I3_5_I1 O=L9_LUT4_I3_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_16_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I3=R9_LUT4_I3_16_O_LUT4_I2_O O=L9_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_17_O_LUT4_I2_O I1=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3 I2=R9_LUT4_I3_16_O_LUT4_I2_2_O I3=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I3_16_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I1_3_I2_LUT4_O_I1 I2=L9_LUT4_I3_5_I2_LUT4_O_I2 I3=L9_LUT4_I3_6_I2_LUT4_O_I2 O=L9_LUT4_I3_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L9_LUT4_I3_17_I0 I1=L9_LUT4_I3_17_I1 I2=L9_LUT4_I3_17_I2 I3=L9(23) O=R10_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_2_I0_LUT4_O_I0 I3=L9_LUT4_I3_8_I2 O=L9_LUT4_I3_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=L9_LUT4_I3_17_I1_LUT4_O_I0 I1=L9_LUT4_I3_17_I1_LUT4_O_I1 I2=L9_LUT4_I3_2_I1 I3=L9_LUT4_I3_2_I0_LUT4_O_I2 O=L9_LUT4_I3_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3 I3=L9_LUT4_I3_8_I2_LUT4_O_I1 O=L9_LUT4_I3_17_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_2_I2_LUT4_O_I2 I3=R9_LUT4_I3_40_O_LUT4_I2_2_O O=L9_LUT4_I3_17_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_8_I0_LUT4_O_I0 I3=R9_LUT4_I3_40_O_LUT4_I2_O O=L9_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_41_O_LUT4_I2_O I1=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_40_O_LUT4_I2_1_O O=L9_LUT4_I3_17_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=L9_LUT4_I2_1_I3_LUT4_O_I1 O=L9_LUT4_I3_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I3_18_I0 I1=L9_LUT4_I3_18_I1 I2=L9_LUT4_I3_18_I2 I3=L9(24) O=R10_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_13_I1_LUT4_O_I1 I2=L9_LUT4_I3_13_I1_LUT4_O_I2 I3=L9_LUT4_I3_18_I0_LUT4_O_I3 O=L9_LUT4_I3_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L9_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I0 I1=R9_LUT4_I3_34_O_LUT4_I2_1_O I2=L9_LUT4_I3_13_I1_LUT4_O_I1_LUT4_O_I3 I3=L9_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_18_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L9_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=L9_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_35_O I3=R9_LUT4_I3_34_O O=L9_LUT4_I3_18_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_18_I1_LUT4_O_I2 I3=L9_LUT4_I3_18_I1_LUT4_O_I3 O=L9_LUT4_I3_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_18_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_O I1=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_35_O_LUT4_I2_O I3=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_31_O I1=R9_LUT4_I3_30_O I2=R9_LUT4_I3_33_O I3=R9_LUT4_I3_32_O O=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_32_O I1=R9_LUT4_I3_33_O I2=R9_LUT4_I3_31_O I3=R9_LUT4_I3_30_O O=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_2_O I1=L9_LUT4_I3_13_I1_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_34_O_LUT4_I2_1_O I3=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I0 O=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_18_I1_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_35_O_LUT4_I2_O I3=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000011
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I1 I3=R9_LUT4_I3_34_O_LUT4_I2_O O=L9_LUT4_I3_18_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=L9_LUT4_I2_2_I3_LUT4_O_I3 I1=L9_LUT4_I3_18_I2_LUT4_O_I1 I2=L9_LUT4_I3_13_I2 I3=L9_LUT4_I3_18_I2_LUT4_O_I3 O=L9_LUT4_I3_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_18_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_O I1=L9_LUT4_I3_18_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_35_O_LUT4_I2_O I3=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_10_I1_LUT4_O_I2_LUT4_O_I1 I1=R9_LUT4_I3_34_O_LUT4_I2_1_O I2=R9_LUT4_I3_34_O_LUT4_I2_2_O I3=L9_LUT4_I3_10_I2_LUT4_O_I2_LUT4_O_I0 O=L9_LUT4_I3_18_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_18_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_2_O I1=L9_LUT4_I3_13_I2_LUT4_O_I3_LUT4_O_I3 I2=L9_LUT4_I3_13_I1_LUT4_O_I3_LUT4_O_I0 I3=R9_LUT4_I3_34_O_LUT4_I2_1_O O=L9_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_34_O_LUT4_I2_O I1=L9_LUT4_I3_10_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_35_O_LUT4_I2_O I3=L9_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_33_O I1=R9_LUT4_I3_30_O I2=R9_LUT4_I3_31_O I3=R9_LUT4_I3_32_O O=L9_LUT4_I3_18_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L9_LUT4_I3_19_I0 I1=L9_LUT4_I3_19_I1 I2=L9_LUT4_I3_19_I2 I3=L9(25) O=R10_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=L9_LUT4_I3_9_I1_LUT4_O_I3 I1=L9_LUT4_I3_19_I0_LUT4_O_I1 I2=L9_LUT4_I2_I3_LUT4_O_I0 I3=L9_LUT4_I3_9_I0_LUT4_O_I2 O=L9_LUT4_I3_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_11_I1_LUT4_O_I3 I3=L9_LUT4_I3_9_I1_LUT4_O_I2 O=L9_LUT4_I3_19_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_19_I1_LUT4_O_I1 I2=L9_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 I3=R9_LUT4_I3_4_O_LUT4_I2_O O=L9_LUT4_I3_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 I3=R9_LUT4_I3_5_O_LUT4_I2_O O=L9_LUT4_I3_19_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_2_O I1=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I1 O=L9_LUT4_I3_19_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_19_I2_LUT4_I1_I0 I1=L9_LUT4_I3_19_I2 I2=L9_LUT4_I3_9_I2_LUT4_O_I2 I3=L9_LUT4_I3_19_I2_LUT4_I1_I3 O=L9_LUT4_I3_9_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R9_LUT4_I3_4_O_LUT4_I2_2_O I2=L9_LUT4_I3_19_I2_LUT4_I1_I0_LUT4_O_I2 I3=L9_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_19_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=R9_LUT4_I3_3_O I1=R9_LUT4_I3_1_O I2=R9_LUT4_I3_2_O I3=R9_LUT4_I3_O O=L9_LUT4_I3_19_I2_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I1 I2=R9_LUT4_I3_5_O_LUT4_I2_O I3=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I3 O=L9_LUT4_I3_19_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_2_O I1=R9_LUT4_I3_1_O I2=R9_LUT4_I3_3_O I3=R9_LUT4_I3_O O=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_2_O I1=R9_LUT4_I3_3_O I2=R9_LUT4_I3_1_O I3=R9_LUT4_I3_O O=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_19_I2_LUT4_O_I2 I3=L9_LUT4_I3_19_I2_LUT4_O_I3 O=L9_LUT4_I3_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_4_O_LUT4_I2_2_O I3=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_3_O I1=R9_LUT4_I3_2_O I2=R9_LUT4_I3_1_O I3=R9_LUT4_I3_O O=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_1_O I1=R9_LUT4_I3_2_O I2=R9_LUT4_I3_3_O I3=R9_LUT4_I3_O O=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_5_O_LUT4_I2_O I1=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_19_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_3_O I1=R9_LUT4_I3_2_O I2=R9_LUT4_I3_O I3=R9_LUT4_I3_1_O O=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_3_O I1=R9_LUT4_I3_O I2=R9_LUT4_I3_1_O I3=R9_LUT4_I3_2_O O=L9_LUT4_I3_19_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L9_LUT4_I3_1_I0_LUT4_O_I0 I1=L9_LUT4_I3_1_I0_LUT4_O_I1 I2=R9_LUT4_I3_29_O_LUT4_I2_O I3=L9_LUT4_I3_1_I0_LUT4_O_I3 O=L9_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R9_LUT4_I3_24_O I1=R9_LUT4_I3_26_O I2=R9_LUT4_I3_25_O I3=R9_LUT4_I3_27_O O=L9_LUT4_I3_1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_26_O I1=R9_LUT4_I3_25_O I2=R9_LUT4_I3_27_O I3=R9_LUT4_I3_24_O O=L9_LUT4_I3_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L9_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I1=R9_LUT4_I3_28_O_LUT4_I2_O I2=L9_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I2 O=L9_LUT4_I3_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L9_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I1=R9_LUT4_I3_28_O_LUT4_I2_1_O I2=R9_LUT4_I3_28_O_LUT4_I2_2_O I3=L9_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2 O=L9_LUT4_I3_1_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001101011111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_1_I1_LUT4_O_I2 I3=L9_LUT4_I3_1_I1_LUT4_O_I3 O=L9_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_O I1=L9_LUT4_I3_1_I0_LUT4_O_I1 I2=L9_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_28_O_LUT4_I2_1_O O=L9_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_29_O_LUT4_I2_O I1=L9_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=R9_LUT4_I3_28_O_LUT4_I2_2_O O=L9_LUT4_I3_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_29_O_LUT4_I2_O O=L9_LUT4_I3_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L9_LUT4_I3_1_I0_LUT4_O_I1 I1=L9_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_29_O I3=R9_LUT4_I3_28_O O=L9_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=R9_LUT4_I3_27_O I1=R9_LUT4_I3_26_O I2=R9_LUT4_I3_25_O I3=R9_LUT4_I3_24_O O=L9_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_3_I1_LUT4_O_I2 I2=L9_LUT4_I3_1_I2_LUT4_O_I2 I3=L9_LUT4_I3_7_I1 O=L9_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_28_O_LUT4_I2_2_O I3=L9_LUT4_I3_7_I1_LUT4_O_I2 O=L9_LUT4_I3_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_28_O_LUT4_I2_1_O O=L9_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_O I1=L9_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2 I2=L9_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_29_O_LUT4_I2_O O=L9_LUT4_I3_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_2_I0 I1=L9_LUT4_I3_2_I1 I2=L9_LUT4_I3_2_I2 I3=L9(9) O=R10_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=L9_LUT4_I3_20_I0 I1=L9_LUT4_I3_20_I1 I2=L9_LUT4_I3_20_I2 I3=L9(26) O=R10_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011101111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_15_I1 I3=L9_LUT4_I1_I3_LUT4_O_I0 O=L9_LUT4_I3_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_15_I2_LUT4_O_I2 I3=L9_LUT4_I1_2_I2_LUT4_O_I3 O=L9_LUT4_I3_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_20_I2_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I0 I3=L9_LUT4_I3_20_I2_LUT4_O_I3 O=L9_LUT4_I3_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_2_O O=L9_LUT4_I3_20_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_O O=L9_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_7_O_LUT4_I2_O I1=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_6_O_LUT4_I2_1_O I3=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_20_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I2 I3=R9_LUT4_I3_6_O_LUT4_I2_2_O O=L9_LUT4_I3_20_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R9_LUT4_I3_6_O_LUT4_I2_1_O O=L9_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=L9_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I1=R9_LUT4_I3_6_O_LUT4_I2_O I2=R9_LUT4_I3_7_O_LUT4_I2_O I3=L9_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I3_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_21_I0 I1=L9_LUT4_I3_21_I1 I2=L9_LUT4_I3_21_I2 I3=L9(32) O=R10_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I1_4_I3_LUT4_O_I3 I3=L9_LUT4_I1_1_I3_LUT4_O_I3 O=L9_LUT4_I3_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I1_4_I3_LUT4_O_I2 I1=L9_LUT4_I3_21_I1_LUT4_O_I1 I2=L9_LUT4_I1_1_I2_LUT4_O_I1 I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_I2_O O=L9_LUT4_I3_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I1_1_I2_LUT4_O_I1 O=L9_LUT4_I3_21_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_2_O I1=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_46_O_LUT4_I2_1_O I3=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R9_LUT4_I3_46_O_LUT4_I2_O I3=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_21_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_21_I2_LUT4_O_I1 I2=L9_LUT4_I1_4_I2_LUT4_O_I3 I3=L9_LUT4_I3_21_I2_LUT4_O_I3 O=L9_LUT4_I3_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I0 I1=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_46_O_LUT4_I2_1_O I3=R9_LUT4_I3_46_O_LUT4_I2_O O=L9_LUT4_I3_21_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011001100110101
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_2_O I1=L9_LUT4_I1_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_46_O_LUT4_I2_O I3=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I0 O=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_45_O I1=R9_LUT4_I3_44_O I2=R9_LUT4_I3_43_O I3=R9_LUT4_I3_42_O O=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_45_O I1=R9_LUT4_I3_43_O I2=R9_LUT4_I3_42_O I3=R9_LUT4_I3_44_O O=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I0 I1=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_21_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_46_O_LUT4_I2_O O=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_2_O I1=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_21_I2_LUT4_O_I1_LUT4_O_I0 I3=R9_LUT4_I3_46_O_LUT4_I2_1_O O=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_46_O_LUT4_I2_1_O I1=L9_LUT4_I1_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R9_LUT4_I3_46_O_LUT4_I2_O I3=L9_LUT4_I1_4_I2_LUT4_O_I2_LUT4_O_I0 O=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_47_O_LUT4_I2_O I1=L9_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I1_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R9_LUT4_I3_46_O_LUT4_I2_2_O O=L9_LUT4_I3_21_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_2_I0_LUT4_O_I0 I1=L9_LUT4_I3_2_I0_LUT4_O_I1 I2=L9_LUT4_I3_2_I0_LUT4_O_I2 I3=L9_LUT4_I3_2_I0_LUT4_O_I3 O=L9_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110110000
+.subckt LUT4 I0=L9_LUT4_I3_17_I1_LUT4_O_I1 I1=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I2 I2=L9_LUT4_I3_8_I2_LUT4_O_I1 I3=L9_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3 O=L9_LUT4_I3_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 I1=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2 I2=L9_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=R9_LUT4_I3_41_O_LUT4_I2_O I3=L9_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=L9_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_41_O_LUT4_I2_O I1=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_40_O_LUT4_I2_1_O I3=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_39_O I1=R9_LUT4_I3_36_O I2=R9_LUT4_I3_37_O I3=R9_LUT4_I3_38_O O=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_41_O_LUT4_I2_O I1=L9_LUT4_I3_2_I0_LUT4_O_I3 I2=R9_LUT4_I3_40_O_LUT4_I2_O I3=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I2 I3=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 I2=R9_LUT4_I3_40_O_LUT4_I2_1_O I3=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_39_O I1=R9_LUT4_I3_37_O I2=R9_LUT4_I3_38_O I3=R9_LUT4_I3_36_O O=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_2_I1_LUT4_O_I1 I2=L9_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_40_O_LUT4_I2_O O=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_41_O_LUT4_I2_O I1=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_40_O_LUT4_I2_1_O O=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R9_LUT4_I3_40_O_LUT4_I2_O O=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_41_O_LUT4_I2_O I1=L9_LUT4_I3_2_I1_LUT4_O_I1 I2=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=R9_LUT4_I3_40_O_LUT4_I2_1_O I2=L9_LUT4_I2_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=L9_LUT4_I3_2_I0_LUT4_O_I3 O=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R9_LUT4_I3_40_O_LUT4_I2_2_O O=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_2_I2_LUT4_O_I2 I3=R9_LUT4_I3_40_O_LUT4_I2_O O=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R9_LUT4_I3_41_O_LUT4_I2_O O=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_36_O I1=R9_LUT4_I3_38_O I2=R9_LUT4_I3_37_O I3=R9_LUT4_I3_39_O O=L9_LUT4_I3_2_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_39_O I1=R9_LUT4_I3_38_O I2=R9_LUT4_I3_37_O I3=R9_LUT4_I3_36_O O=L9_LUT4_I3_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_1_O I1=L9_LUT4_I3_2_I1_LUT4_O_I1 I2=L9_LUT4_I3_2_I2 I3=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=L9_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R9_LUT4_I3_39_O I1=R9_LUT4_I3_38_O I2=R9_LUT4_I3_37_O I3=R9_LUT4_I3_36_O O=L9_LUT4_I3_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_8_I1 I2=L9_LUT4_I3_2_I2_LUT4_O_I2 I3=R9_LUT4_I3_40_O_LUT4_I2_1_O O=L9_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_39_O I1=R9_LUT4_I3_38_O I2=R9_LUT4_I3_37_O I3=R9_LUT4_I3_36_O O=L9_LUT4_I3_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L9_LUT4_I3_3_I0 I1=L9_LUT4_I3_3_I1 I2=L9_LUT4_I3_3_I2 I3=L9(11) O=R10_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L9_LUT4_I3_3_I0_LUT4_O_I0 I1=L9_LUT4_I3_3_I0_LUT4_O_I1 I2=L9_LUT4_I3_1_I1_LUT4_O_I2 I3=L9_LUT4_I3_3_I0_LUT4_O_I3 O=L9_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L9_LUT4_I3_7_I1_LUT4_O_I2 I1=L9_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I2=R9_LUT4_I3_28_O I3=R9_LUT4_I3_29_O O=L9_LUT4_I3_3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R9_LUT4_I3_27_O I1=R9_LUT4_I3_26_O I2=R9_LUT4_I3_25_O I3=R9_LUT4_I3_24_O O=L9_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_O I1=L9_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 I2=R9_LUT4_I3_28_O_LUT4_I2_1_O I3=L9_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1 O=L9_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_29_O_LUT4_I2_O I1=L9_LUT4_I3_1_I0_LUT4_O_I0 I2=R9_LUT4_I3_28_O_LUT4_I2_2_O I3=L9_LUT4_I3_1_I1_LUT4_O_I3_LUT4_O_I2 O=L9_LUT4_I3_3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_2_O I1=L9_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_28_O_LUT4_I2_1_O I3=L9_LUT4_I3_1_I0_LUT4_O_I1 O=L9_LUT4_I3_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_27_O I1=R9_LUT4_I3_26_O I2=R9_LUT4_I3_24_O I3=R9_LUT4_I3_25_O O=L9_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_3_I1_LUT4_O_I2 I3=L9_LUT4_I3_7_I2 O=L9_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I3_7_I2_LUT4_O_I3 I1=R9_LUT4_I3_28_O_LUT4_I2_2_O I2=L9_LUT4_I3_7_I0_LUT4_O_I3 I3=L9_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_28_O_LUT4_I2_1_O I3=L9_LUT4_I3_7_I1_LUT4_O_I2 O=L9_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_O I1=L9_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_29_O_LUT4_I2_O O=L9_LUT4_I3_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_3_I0_LUT4_O_I1 I2=L9_LUT4_I3_1_I1_LUT4_O_I3 I3=L9_LUT4_I3_3_I2 O=L9_LUT4_I3_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_3_I2_LUT4_O_I1 I2=L9_LUT4_I3_3_I2_LUT4_O_I2 I3=L9_LUT4_I3_3_I2_LUT4_O_I3 O=L9_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_O I1=L9_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_28_O_LUT4_I2_2_O O=L9_LUT4_I3_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_26_O I1=R9_LUT4_I3_25_O I2=R9_LUT4_I3_24_O I3=R9_LUT4_I3_27_O O=L9_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_25_O I1=R9_LUT4_I3_24_O I2=R9_LUT4_I3_27_O I3=R9_LUT4_I3_26_O O=L9_LUT4_I3_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_29_O_LUT4_I2_O I1=L9_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_28_O_LUT4_I2_1_O O=L9_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_27_O I1=R9_LUT4_I3_26_O I2=R9_LUT4_I3_25_O I3=R9_LUT4_I3_24_O O=L9_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_27_O I1=R9_LUT4_I3_25_O I2=R9_LUT4_I3_26_O I3=R9_LUT4_I3_24_O O=L9_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_O I1=L9_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=L9_LUT4_I1_5_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_28_O_LUT4_I2_2_O O=L9_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_29_O_LUT4_I2_O I1=L9_LUT4_I1_5_I2_LUT4_O_I3_LUT4_O_I2 I2=R9_LUT4_I3_28_O_LUT4_I2_1_O I3=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L9_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_4_I0 I1=L9_LUT4_I3_4_I1 I2=L9_LUT4_I3_4_I2 I3=L9(13) O=R10_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=L9_LUT4_I3_4_I0_LUT4_O_I0 I1=L9_LUT4_I3_4_I0_LUT4_O_I1 I2=L9_LUT4_I1_6_I2_LUT4_O_I2 I3=L9_LUT4_I3_I0_LUT4_O_I0 O=L9_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I1 I2=L9_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 I3=R9_LUT4_I3_23_O_LUT4_I3_1_O O=L9_LUT4_I3_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_20_O I1=R9_LUT4_I3_19_O I2=R9_LUT4_I3_21_O I3=R9_LUT4_I3_18_O O=L9_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L9_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I1=R9_LUT4_I3_23_O_LUT4_I3_2_O I2=R9_LUT4_I3_23_O_LUT4_I2_O I3=L9_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_21_O I1=R9_LUT4_I3_20_O I2=R9_LUT4_I3_19_O I3=R9_LUT4_I3_18_O O=L9_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_4_I1 I3=L9_LUT4_I3_4_I1_LUT4_I2_I3 O=L9_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_2_O I1=L9_LUT4_I3_I2_LUT4_O_I0 I2=L9_LUT4_I3_4_I1_LUT4_O_I2 I3=L9_LUT4_I3_4_I1_LUT4_O_I3 O=L9_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_I2_I0 I1=R9_LUT4_I3_23_O_LUT4_I3_2_O I2=L9_LUT4_I3_4_I1_LUT4_O_I2 I3=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_I2_I3 O=L9_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I1 I3=L9_LUT4_I3_I2_LUT4_O_I0 O=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=L9_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 I1=R9_LUT4_I3_23_O_LUT4_I3_1_O I2=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110100000000
+.subckt LUT4 I0=K1(1) I1=R9_LUT4_I3_22_O I2=L9_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 I3=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_I2_LUT4_O_I0 I2=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_2_O I1=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_23_O_LUT4_I2_O I3=L9_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I2_O I1=L9_LUT4_I3_4_I0_LUT4_O_I0_LUT4_O_I1 I2=R9_LUT4_I3_23_O_LUT4_I3_1_O I3=L9_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_4_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 I2=R9_LUT4_I3_23_O_LUT4_I3_1_O I3=L9_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_21_O I1=R9_LUT4_I3_20_O I2=R9_LUT4_I3_19_O I3=R9_LUT4_I3_18_O O=L9_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_I2 I2=L9_LUT4_I3_4_I2_LUT4_O_I2 I3=L9_LUT4_I1_6_I3_LUT4_O_I1 O=L9_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_2_O I1=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R9_LUT4_I3_23_O_LUT4_I2_O I3=L9_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_23_O_LUT4_I3_1_O I3=L9_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I1 O=L9_LUT4_I3_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_5_I0 I1=L9_LUT4_I3_5_I1 I2=L9_LUT4_I3_5_I2 I3=L9(15) O=R10_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I3_O I1=L9_LUT4_I3_5_I1_LUT4_I3_O I2=L9_LUT4_I1_3_I3_LUT4_O_I0 I3=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O O=L9_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_16_I1_LUT4_O_I1 I3=L9_LUT4_I3_5_I1 O=L9_LUT4_I3_5_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_5_I1_LUT4_O_I2 I3=L9_LUT4_I3_5_I1_LUT4_O_I3 O=L9_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_16_O_LUT4_I2_O I3=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_12_O I1=R9_LUT4_I3_14_O I2=R9_LUT4_I3_13_O I3=R9_LUT4_I3_15_O O=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_15_O I1=R9_LUT4_I3_13_O I2=R9_LUT4_I3_12_O I3=R9_LUT4_I3_14_O O=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_17_O_LUT4_I2_O I1=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_16_O_LUT4_I2_2_O I3=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_5_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_14_O I1=R9_LUT4_I3_12_O I2=R9_LUT4_I3_13_O I3=R9_LUT4_I3_15_O O=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_14_O I1=R9_LUT4_I3_13_O I2=R9_LUT4_I3_15_O I3=R9_LUT4_I3_12_O O=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_5_I2_LUT4_O_I2 I3=L9_LUT4_I3_6_I2_LUT4_O_I0 O=L9_LUT4_I3_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_16_O_LUT4_I2_O O=L9_LUT4_I3_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_16_O_LUT4_I2_1_O O=L9_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_17_O_LUT4_I2_O I1=L9_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_16_O_LUT4_I2_2_O O=L9_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_15_O I1=R9_LUT4_I3_14_O I2=R9_LUT4_I3_13_O I3=R9_LUT4_I3_12_O O=L9_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L9_LUT4_I3_5_I1_LUT4_I3_O I1=L9_LUT4_I3_6_I1 I2=L9_LUT4_I3_6_I2 I3=L9(27) O=R10_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L9_LUT4_I1_3_I3_LUT4_O_I1 I1=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I3_O I2=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I3=L9_LUT4_I3_6_I1_LUT4_O_I3 O=L9_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I3_I1 I2=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I3_I2 I3=L9_LUT4_I3_6_I1_LUT4_O_I3 O=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I3 I2=R9_LUT4_I3_17_O_LUT4_I2_O I3=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_O I1=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=R9_LUT4_I3_16_O_LUT4_I2_2_O O=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0 I1=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_16_O_LUT4_I2_2_O I3=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R9_LUT4_I3_13_O I1=R9_LUT4_I3_12_O I2=R9_LUT4_I3_15_O I3=R9_LUT4_I3_14_O O=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_14_O I1=R9_LUT4_I3_13_O I2=R9_LUT4_I3_12_O I3=R9_LUT4_I3_15_O O=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=L9_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=R9_LUT4_I3_16_O_LUT4_I2_O I2=R9_LUT4_I3_16_O_LUT4_I2_1_O I3=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_6_I2_LUT4_O_I0 I1=L9_LUT4_I3_6_I2_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I2 I3=L9_LUT4_I3_6_I2_LUT4_O_I3 O=L9_LUT4_I3_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I2 I3=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3 O=L9_LUT4_I3_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I2=R9_LUT4_I3_16_O_LUT4_I2_2_O I3=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_14_O I1=R9_LUT4_I3_15_O I2=R9_LUT4_I3_13_O I3=R9_LUT4_I3_12_O O=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 I2=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I0 I3=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_O I1=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R9_LUT4_I3_16_O_LUT4_I2_2_O I3=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_17_O_LUT4_I2_O I1=L9_LUT4_I3_5_I2_LUT4_O_I2_LUT4_O_I2 I2=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1 I3=L9_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I0 I1=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 I3=R9_LUT4_I3_16_O_LUT4_I2_2_O O=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_15_O I1=R9_LUT4_I3_12_O I2=R9_LUT4_I3_13_O I3=R9_LUT4_I3_14_O O=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_O I1=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R9_LUT4_I3_17_O_LUT4_I2_O O=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_15_O I1=R9_LUT4_I3_14_O I2=R9_LUT4_I3_12_O I3=R9_LUT4_I3_13_O O=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_15_O I1=R9_LUT4_I3_14_O I2=R9_LUT4_I3_13_O I3=R9_LUT4_I3_12_O O=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_O I1=L9_LUT4_I3_6_I1_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_5_I1_LUT4_O_I3_LUT4_O_I1 I3=R9_LUT4_I3_16_O_LUT4_I2_2_O O=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I1_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_17_O_LUT4_I2_O I3=L9_LUT4_I3_5_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_16_O_LUT4_I2_O I3=L9_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_17_O_LUT4_I2_O I3=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=L9_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R9_LUT4_I3_16_O_LUT4_I2_2_O I3=L9_LUT4_I1_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3 I2=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=R9_LUT4_I3_16_O_LUT4_I2_O O=L9_LUT4_I1_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_15_O I1=R9_LUT4_I3_14_O I2=R9_LUT4_I3_13_O I3=R9_LUT4_I3_12_O O=L9_LUT4_I3_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=R9_LUT4_I3_16_O_LUT4_I2_2_O I2=L9_LUT4_I3_6_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=R9_LUT4_I3_16_O_LUT4_I2_O O=L9_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_16_O_LUT4_I2_1_O I1=L9_LUT4_I3_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_17_O_LUT4_I2_O O=L9_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_13_O I1=R9_LUT4_I3_14_O I2=R9_LUT4_I3_15_O I3=R9_LUT4_I3_12_O O=L9_LUT4_I3_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L9_LUT4_I3_7_I0 I1=L9_LUT4_I3_7_I1 I2=L9_LUT4_I3_7_I2 I3=L9(29) O=R10_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=L9_LUT4_I3_3_I1_LUT4_O_I2 I1=L9_LUT4_I1_5_I3_LUT4_O_I3 I2=L9_LUT4_I3_7_I0_LUT4_O_I2 I3=L9_LUT4_I3_7_I0_LUT4_O_I3 O=L9_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_O I1=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=R9_LUT4_I3_29_O_LUT4_I2_O I3=L9_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_27_O I1=R9_LUT4_I3_25_O I2=R9_LUT4_I3_24_O I3=R9_LUT4_I3_26_O O=L9_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_2_O I1=L9_LUT4_I3_1_I0_LUT4_O_I0 I2=L9_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I3=R9_LUT4_I3_28_O_LUT4_I2_1_O O=L9_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=L9_LUT4_I3_7_I1 I1=L9_LUT4_I3_1_I2_LUT4_O_I2 I2=L9_LUT4_I3_7_I1_LUT4_I0_I2 I3=L9_LUT4_I3_7_I1_LUT4_I0_I3 O=L9_LUT4_I1_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_7_I1_LUT4_I0_I2_LUT4_O_I1 I2=L9_LUT4_I3_7_I2_LUT4_O_I3 I3=R9_LUT4_I3_28_O_LUT4_I2_O O=L9_LUT4_I3_7_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_7_I1_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I3=R9_LUT4_I3_28_O_LUT4_I2_2_O O=L9_LUT4_I3_7_I1_LUT4_I0_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_29_O_LUT4_I2_O I1=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=R9_LUT4_I3_28_O_LUT4_I2_1_O I3=L9_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_7_I1_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_7_I1_LUT4_I0_I3_LUT4_O_I2 I3=L9_LUT4_I3_7_I1_LUT4_I0_I3_LUT4_O_I3 O=L9_LUT4_I3_7_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_O I1=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_28_O_LUT4_I2_1_O I3=L9_LUT4_I3_7_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_7_I1_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_29_O_LUT4_I2_O I1=L9_LUT4_I3_3_I0_LUT4_O_I0_LUT4_O_I1 I2=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=R9_LUT4_I3_28_O_LUT4_I2_2_O O=L9_LUT4_I3_7_I1_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_7_I1_LUT4_O_I1 I2=L9_LUT4_I3_7_I1_LUT4_O_I2 I3=R9_LUT4_I3_28_O_LUT4_I2_O O=L9_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_7_I2_LUT4_O_I3 I3=R9_LUT4_I3_29_O_LUT4_I2_O O=L9_LUT4_I3_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_28_O_LUT4_I2_2_O I1=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_28_O_LUT4_I2_1_O I3=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_26_O I1=R9_LUT4_I3_24_O I2=R9_LUT4_I3_25_O I3=R9_LUT4_I3_27_O O=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_27_O I1=R9_LUT4_I3_24_O I2=R9_LUT4_I3_25_O I3=R9_LUT4_I3_26_O O=L9_LUT4_I3_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_27_O I1=R9_LUT4_I3_26_O I2=R9_LUT4_I3_25_O I3=R9_LUT4_I3_24_O O=L9_LUT4_I3_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_7_I2_LUT4_O_I1 I2=R9_LUT4_I3_28_O_LUT4_I2_1_O I3=L9_LUT4_I3_7_I2_LUT4_O_I3 O=L9_LUT4_I3_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_1_I0_LUT4_O_I0 I3=R9_LUT4_I3_28_O_LUT4_I2_O O=L9_LUT4_I3_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_29_O_LUT4_I2_O I1=L9_LUT4_I3_3_I0_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_28_O_LUT4_I2_2_O I3=L9_LUT4_I3_3_I2_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I3_7_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_27_O I1=R9_LUT4_I3_26_O I2=R9_LUT4_I3_25_O I3=R9_LUT4_I3_24_O O=L9_LUT4_I3_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L9_LUT4_I3_8_I0 I1=L9_LUT4_I3_8_I1 I2=L9_LUT4_I3_8_I2 I3=L9(31) O=R10_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111101110000
+.subckt LUT4 I0=L9_LUT4_I3_8_I0_LUT4_O_I0 I1=L9_LUT4_I3_8_I0_LUT4_O_I1 I2=L9_LUT4_I3_2_I2_LUT4_O_I2 I3=R9_LUT4_I3_40_O_LUT4_I2_1_O O=L9_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100110011
+.subckt LUT4 I0=R9_LUT4_I3_38_O I1=R9_LUT4_I3_39_O I2=R9_LUT4_I3_37_O I3=R9_LUT4_I3_36_O O=L9_LUT4_I3_8_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_41_O_LUT4_I2_O I1=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 I2=L9_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I2_1_I3_LUT4_O_I0 O=L9_LUT4_I3_8_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I3=R9_LUT4_I3_40_O_LUT4_I2_O O=L9_LUT4_I3_8_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_8_I1_LUT4_O_I1 I2=L9_LUT4_I3_8_I1_LUT4_O_I2 I3=R9_LUT4_I3_41_O_LUT4_I2_O O=L9_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_40_O_LUT4_I2_O I3=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_38_O I1=R9_LUT4_I3_37_O I2=R9_LUT4_I3_36_O I3=R9_LUT4_I3_39_O O=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_39_O I1=R9_LUT4_I3_37_O I2=R9_LUT4_I3_36_O I3=R9_LUT4_I3_38_O O=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_37_O I1=R9_LUT4_I3_36_O I2=R9_LUT4_I3_39_O I3=R9_LUT4_I3_38_O O=L9_LUT4_I3_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L9_LUT4_I3_8_I2_LUT4_O_I0 I1=L9_LUT4_I3_8_I2_LUT4_O_I1 I2=L9_LUT4_I3_8_I2_LUT4_O_I2 I3=L9_LUT4_I3_8_I2_LUT4_O_I3 O=L9_LUT4_I3_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R9_LUT4_I3_41_O_LUT4_I2_O I1=L9_LUT4_I3_2_I2_LUT4_O_I2 I2=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I2 I3=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I3 O=L9_LUT4_I3_8_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=R9_LUT4_I3_40_O_LUT4_I2_1_O I2=R9_LUT4_I3_40_O_LUT4_I2_O I3=L9_LUT4_I3_8_I1_LUT4_O_I2 O=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 I2=R9_LUT4_I3_41_O_LUT4_I2_O I3=L9_LUT4_I3_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_40_O_LUT4_I2_O I3=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I2_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R9_LUT4_I3_40_O_LUT4_I2_1_O I3=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I1 O=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_38_O I1=R9_LUT4_I3_37_O I2=R9_LUT4_I3_39_O I3=R9_LUT4_I3_36_O O=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=L9_LUT4_I3_8_I1_LUT4_O_I1_LUT4_O_I3 I1=R9_LUT4_I3_40_O_LUT4_I2_1_O I2=R9_LUT4_I3_40_O_LUT4_I2_O I3=L9_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_39_O I1=R9_LUT4_I3_38_O I2=R9_LUT4_I3_37_O I3=R9_LUT4_I3_36_O O=L9_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_8_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=R9_LUT4_I3_41_O_LUT4_I2_O O=L9_LUT4_I3_8_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_1_O I1=L9_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_40_O_LUT4_I2_O I3=L9_LUT4_I3_2_I0_LUT4_O_I3 O=L9_LUT4_I3_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_1_O I1=L9_LUT4_I3_8_I1_LUT4_O_I2 I2=R9_LUT4_I3_40_O_LUT4_I2_O I3=L9_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1 O=L9_LUT4_I3_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_39_O I1=R9_LUT4_I3_38_O I2=R9_LUT4_I3_37_O I3=R9_LUT4_I3_36_O O=L9_LUT4_I3_8_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_40_O_LUT4_I2_2_O I1=L9_LUT4_I3_8_I0_LUT4_O_I0 I2=R9_LUT4_I3_41_O_LUT4_I2_O I3=L9_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_38_O I1=R9_LUT4_I3_36_O I2=R9_LUT4_I3_37_O I3=R9_LUT4_I3_39_O O=L9_LUT4_I3_8_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L9_LUT4_I3_9_I0 I1=L9_LUT4_I3_9_I1 I2=L9_LUT4_I3_9_I2 I3=L9(3) O=R10_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I2_I3_LUT4_O_I3 I2=L9_LUT4_I3_9_I0_LUT4_O_I2 I3=L9_LUT4_I2_I3_LUT4_O_I0 O=L9_LUT4_I3_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_9_I1_LUT4_O_I2 I3=L9_LUT4_I3_9_I1_LUT4_O_I3 O=L9_LUT4_I3_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I2 O=L9_LUT4_I3_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_2_O I1=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I3 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_5_O_LUT4_I2_O I3=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_3_O I1=R9_LUT4_I3_1_O I2=R9_LUT4_I3_O I3=R9_LUT4_I3_2_O O=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_O I1=R9_LUT4_I3_2_O I2=R9_LUT4_I3_1_O I3=R9_LUT4_I3_3_O O=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I0 O=L9_LUT4_I3_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_11_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_11_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R9_LUT4_I3_4_O_LUT4_I2_2_O O=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_5_O_LUT4_I2_O I1=L9_LUT4_I3_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R9_LUT4_I3_4_O_LUT4_I2_1_O O=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_3_O I1=R9_LUT4_I3_2_O I2=R9_LUT4_I3_1_O I3=R9_LUT4_I3_O O=L9_LUT4_I3_9_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_9_I2_LUT4_O_I1 I2=L9_LUT4_I3_9_I2_LUT4_O_I2 I3=L9_LUT4_I3_9_I2_LUT4_O_I3 O=L9_LUT4_I3_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_19_I2_LUT4_I1_I0_LUT4_O_I2 I2=L9_LUT4_I3_19_I2_LUT4_I1_I3_LUT4_O_I1 I3=R9_LUT4_I3_4_O_LUT4_I2_2_O O=L9_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_5_O_LUT4_I2_O I1=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 I3=R9_LUT4_I3_4_O_LUT4_I2_1_O O=L9_LUT4_I3_9_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_4_O_LUT4_I2_2_O I3=L9_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R9_LUT4_I3_4_O_LUT4_I2_1_O I3=L9_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I0 O=L9_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_4_O_LUT4_I2_O I1=L9_LUT4_I3_19_I2_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_5_O_LUT4_I2_O I3=L9_LUT4_I3_19_I2_LUT4_I1_I0_LUT4_O_I2 O=L9_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_3_O I1=R9_LUT4_I3_2_O I2=R9_LUT4_I3_1_O I3=R9_LUT4_I3_O O=L9_LUT4_I3_9_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 I2=L9_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I2 I3=L9_LUT4_I3_19_I1 O=L9_LUT4_I3_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=L9_LUT4_I3_I0_LUT4_O_I0 I1=L9_LUT4_I3_I0_LUT4_O_I1 I2=L9_LUT4_I3_I0_LUT4_O_I2 I3=L9_LUT4_I3_I0_LUT4_O_I3 O=L9_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2 I3=L9_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I3 O=L9_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_2_O I1=L9_LUT4_I3_4_I0_LUT4_O_I1_LUT4_O_I3 I2=L9_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_23_O_LUT4_I3_1_O O=L9_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_21_O I1=R9_LUT4_I3_19_O I2=R9_LUT4_I3_20_O I3=R9_LUT4_I3_18_O O=L9_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_23_O_LUT4_I2_O I3=L9_LUT4_I3_4_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_14_I0_LUT4_O_I1_LUT4_O_I1 I2=L9_LUT4_I3_14_I0_LUT4_O_I1_LUT4_O_I2 I3=L9_LUT4_I3_I0_LUT4_O_I2 O=L9_LUT4_I3_4_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2 I3=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_2_O I1=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_23_O_LUT4_I2_O O=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_19_O I1=R9_LUT4_I3_18_O I2=R9_LUT4_I3_21_O I3=R9_LUT4_I3_20_O O=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R9_LUT4_I3_18_O I1=R9_LUT4_I3_20_O I2=R9_LUT4_I3_19_O I3=R9_LUT4_I3_21_O O=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R9_LUT4_I3_23_O_LUT4_I3_1_O I3=L9_LUT4_I3_14_I2_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_21_O I1=R9_LUT4_I3_20_O I2=R9_LUT4_I3_19_O I3=R9_LUT4_I3_18_O O=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L9_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I0 I1=L9_LUT4_I3_4_I1_LUT4_I2_I3 I2=L9_LUT4_I1_6_I2_LUT4_O_I0 I3=L9_LUT4_I1_6_I2_LUT4_O_I2 O=L9_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L9_LUT4_I3_I1_LUT4_O_I0 I1=L9_LUT4_I3_I1_LUT4_O_I1 I2=L9_LUT4_I3_I1_LUT4_O_I2 I3=L9_LUT4_I3_I1_LUT4_O_I3 O=L9_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=L9_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 I1=L9_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I1 I2=R9_LUT4_I3_23_O I3=R9_LUT4_I3_22_O O=L9_LUT4_I3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R9_LUT4_I3_20_O I1=R9_LUT4_I3_18_O I2=R9_LUT4_I3_19_O I3=R9_LUT4_I3_21_O O=L9_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=L9_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I1=R9_LUT4_I3_23_O_LUT4_I3_1_O I2=R9_LUT4_I3_23_O_LUT4_I3_2_O I3=L9_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=L9_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_21_O I1=R9_LUT4_I3_20_O I2=R9_LUT4_I3_19_O I3=R9_LUT4_I3_18_O O=L9_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I2=R9_LUT4_I3_23_O_LUT4_I2_O I3=L9_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 O=L9_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_21_O I1=R9_LUT4_I3_19_O I2=R9_LUT4_I3_18_O I3=R9_LUT4_I3_20_O O=L9_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R9_LUT4_I3_19_O I1=R9_LUT4_I3_20_O I2=R9_LUT4_I3_21_O I3=R9_LUT4_I3_18_O O=L9_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=L9_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I1=R9_LUT4_I3_23_O_LUT4_I2_O I2=R9_LUT4_I3_23_O_LUT4_I3_2_O I3=L9_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_21_O I1=R9_LUT4_I3_20_O I2=R9_LUT4_I3_19_O I3=R9_LUT4_I3_18_O O=L9_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=L9_LUT4_I3_I2_LUT4_O_I0 I1=R9_LUT4_I3_23_O_LUT4_I3_1_O I2=L9_LUT4_I3_I2_LUT4_O_I2 I3=L9_LUT4_I3_I2_LUT4_O_I3 O=L9_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R9_LUT4_I3_20_O I1=R9_LUT4_I3_21_O I2=R9_LUT4_I3_19_O I3=R9_LUT4_I3_18_O O=L9_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=L9_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I2=L9_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=R9_LUT4_I3_23_O_LUT4_I3_O O=L9_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_2_O I1=L9_LUT4_I3_14_I2_LUT4_O_I2_LUT4_O_I3 I2=R9_LUT4_I3_23_O_LUT4_I2_O I3=L9_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_21_O I1=R9_LUT4_I3_20_O I2=R9_LUT4_I3_18_O I3=R9_LUT4_I3_19_O O=L9_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=L9_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=L9_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3 O=L9_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_O I1=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R9_LUT4_I3_23_O_LUT4_I3_1_O I3=L9_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=L9_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R9_LUT4_I3_23_O_LUT4_I3_2_O I1=L9_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=R9_LUT4_I3_23_O_LUT4_I2_O I3=L9_LUT4_I3_I1_LUT4_O_I0_LUT4_O_I1 O=L9_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=L9(1) D=R8(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(2) D=R8(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(11) D=R8(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(12) D=R8(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(13) D=R8(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(14) D=R8(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(15) D=R8(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(16) D=R8(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(17) D=R8(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(18) D=R8(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(19) D=R8(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(20) D=R8(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(3) D=R8(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(21) D=R8(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(22) D=R8(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(23) D=R8(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(24) D=R8(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(25) D=R8(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(26) D=R8(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(27) D=R8(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(28) D=R8(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(29) D=R8(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(30) D=R8(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(4) D=R8(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(31) D=R8(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(32) D=R8(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(5) D=R8(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(6) D=R8(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(7) D=R8(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(8) D=R8(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(9) D=R8(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=L9(10) D=R8(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:167.1-168.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r0(38) I1=uk.K_r0(0) I2=uk.decrypt I3=R0(21) O=R0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(22) I1=uk.K_r0(43) I2=uk.decrypt I3=R0(16) O=R0_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(6) I1=uk.K_r0(27) I2=uk.decrypt I3=R0(17) O=R0_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_10_O I3=R0_LUT4_I3_11_O O=R0_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_10_O I3=R0_LUT4_I3_11_O O=R0_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_10_O I3=R0_LUT4_I3_11_O O=R0_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r0(47) I1=uk.K_r0(11) I2=uk.decrypt I3=R0(12) O=R0_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_11_O I3=R0_LUT4_I3_10_O O=R0_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(42) I1=uk.K_r0(8) I2=uk.decrypt I3=R0(31) O=R0_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(29) I1=uk.K_r0(50) I2=uk.decrypt I3=R0(29) O=R0_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(52) I1=uk.K_r0(14) I2=uk.decrypt I3=R0(32) O=R0_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(30) I1=uk.K_r0(51) I2=uk.decrypt I3=R0(30) O=R0_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(14) I1=uk.K_r0(35) I2=uk.decrypt I3=R0(1) O=R0_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_16_O I3=R0_LUT4_I3_17_O O=R0_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_16_O I3=R0_LUT4_I3_17_O O=R0_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_16_O I3=R0_LUT4_I3_17_O O=R0_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_17_O I3=R0_LUT4_I3_16_O O=R0_LUT4_I3_16_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(2) I1=uk.K_r0(23) I2=uk.decrypt I3=R0(28) O=R0_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(34) I1=uk.K_r0(55) I2=uk.decrypt I3=R0(7) O=R0_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(25) I1=uk.K_r0(46) I2=uk.decrypt I3=R0(8) O=R0_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(44) I1=uk.K_r0(38) I2=uk.decrypt I3=R0(17) O=R0_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(40) I1=uk.K_r0(4) I2=uk.decrypt I3=R0(6) O=R0_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(17) I1=uk.K_r0(13) I2=uk.decrypt I3=R0(5) O=R0_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(5) I1=uk.K_r0(26) I2=uk.decrypt I3=R0(9) O=R0_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_22_O I3=R0_LUT4_I3_23_O O=R0_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_22_O I3=R0_LUT4_I3_23_O O=R0_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_22_O I3=R0_LUT4_I3_23_O O=R0_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r0(13) I1=uk.K_r0(34) I2=uk.decrypt I3=R0(4) O=R0_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_23_O I3=R0_LUT4_I3_22_O O=R0_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(15) I1=uk.K_r0(36) I2=uk.decrypt I3=R0(21) O=R0_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(37) I1=uk.K_r0(31) I2=uk.decrypt I3=R0(22) O=R0_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(21) I1=uk.K_r0(42) I2=uk.decrypt I3=R0(24) O=R0_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(50) I1=uk.K_r0(16) I2=uk.decrypt I3=R0(23) O=R0_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(0) I1=uk.K_r0(21) I2=uk.decrypt I3=R0(20) O=R0_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_28_O I3=R0_LUT4_I3_29_O O=R0_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_28_O I3=R0_LUT4_I3_29_O O=R0_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_28_O I3=R0_LUT4_I3_29_O O=R0_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r0(16) I1=uk.K_r0(37) I2=uk.decrypt I3=R0(25) O=R0_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_29_O I3=R0_LUT4_I3_28_O O=R0_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(7) I1=uk.K_r0(28) I2=uk.decrypt I3=R0(18) O=R0_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(20) I1=uk.K_r0(41) I2=uk.decrypt I3=R0(11) O=R0_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(3) I1=uk.K_r0(24) I2=uk.decrypt I3=R0(12) O=R0_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(19) I1=uk.K_r0(40) I2=uk.decrypt I3=R0(10) O=R0_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(11) I1=uk.K_r0(32) I2=uk.decrypt I3=R0(9) O=R0_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(39) I1=uk.K_r0(3) I2=uk.decrypt I3=R0(8) O=R0_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_34_O I3=R0_LUT4_I3_35_O O=R0_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_34_O I3=R0_LUT4_I3_35_O O=R0_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_34_O I3=R0_LUT4_I3_35_O O=R0_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(48) I1=uk.K_r0(12) I2=uk.decrypt I3=R0(13) O=R0_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_35_O I3=R0_LUT4_I3_34_O O=R0_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(54) I1=uk.K_r0(18) I2=uk.decrypt I3=R0(1) O=R0_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(12) I1=uk.K_r0(33) I2=uk.decrypt I3=R0(2) O=R0_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(24) I1=uk.K_r0(20) I2=uk.decrypt I3=R0(4) O=R0_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(46) I1=uk.K_r0(10) I2=uk.decrypt I3=R0(3) O=R0_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(9) I1=uk.K_r0(30) I2=uk.decrypt I3=R0(20) O=R0_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(33) I1=uk.K_r0(54) I2=uk.decrypt I3=R0(32) O=R0_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_40_O I3=R0_LUT4_I3_41_O O=R0_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_40_O I3=R0_LUT4_I3_41_O O=R0_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_40_O I3=R0_LUT4_I3_41_O O=R0_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(27) I1=uk.K_r0(48) I2=uk.decrypt I3=R0(5) O=R0_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_41_O I3=R0_LUT4_I3_40_O O=R0_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(8) I1=uk.K_r0(29) I2=uk.decrypt I3=R0(26) O=R0_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(45) I1=uk.K_r0(7) I2=uk.decrypt I3=R0(27) O=R0_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(23) I1=uk.K_r0(44) I2=uk.decrypt I3=R0(25) O=R0_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(28) I1=uk.K_r0(49) I2=uk.decrypt I3=R0(28) O=R0_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(51) I1=uk.K_r0(45) I2=uk.decrypt I3=R0(29) O=R0_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_46_O I3=R0_LUT4_I3_47_O O=R0_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_46_O I3=R0_LUT4_I3_47_O O=R0_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_46_O I3=R0_LUT4_I3_47_O O=R0_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(43) I1=uk.K_r0(9) I2=uk.decrypt I3=R0(24) O=R0_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_47_O I3=R0_LUT4_I3_46_O O=R0_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r0(49) I1=uk.K_r0(15) I2=uk.decrypt I3=R0(19) O=R0_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(41) I1=uk.K_r0(5) I2=uk.decrypt I3=R0(13) O=R0_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(10) I1=uk.K_r0(6) I2=uk.decrypt I3=R0(14) O=R0_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(26) I1=uk.K_r0(47) I2=uk.decrypt I3=R0(16) O=R0_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r0(18) I1=uk.K_r0(39) I2=uk.decrypt I3=R0(15) O=R0_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_O I3=R0_LUT4_I3_1_O O=R0_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_O I3=R0_LUT4_I3_1_O O=R0_LUT4_I3_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_O I3=R0_LUT4_I3_1_O O=R0_LUT4_I3_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_LUT4_I3_1_O I3=R0_LUT4_I3_O O=R0_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=R0(1) D=R0_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(2) D=R0_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(11) D=R0_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(12) D=R0_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(13) D=R0_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(14) D=R0_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(15) D=R0_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(16) D=R0_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(17) D=R0_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(18) D=R0_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(19) D=R0_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(20) D=R0_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(3) D=R0_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(21) D=R0_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(22) D=R0_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(23) D=R0_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(24) D=R0_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(25) D=R0_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(26) D=R0_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(27) D=R0_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(28) D=R0_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(29) D=R0_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(30) D=R0_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(4) D=R0_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(31) D=R0_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(32) D=R0_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(5) D=R0_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(6) D=R0_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(7) D=R0_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(8) D=R0_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(9) D=R0_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R0(10) D=R0_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:112.1-113.34|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2 I3=IP(2) O=R0_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1 I2=R0_ff_CQZ_D_LUT4_O_1_I2 I3=IP(4) O=R0_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0 I1=R0_ff_CQZ_D_LUT4_O_10_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I2 I3=IP(7) O=R0_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_13_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(50) I1=key_r(2) I2=uk.decrypt I3=IP(56) O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(31) I1=key_r(38) I2=uk.decrypt I3=IP(61) O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2 I3=IP(8) O=R0_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011101111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_I0 I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_I3 O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_I0 O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=key_r(1) I1=key_r(8) I2=uk.decrypt I3=IP(51) O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(16) I1=key_r(23) I2=uk.decrypt I3=IP(52) O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(21) I1=key_r(14) I2=IP(50) I3=uk.decrypt O=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110001011010
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_12_I0 I1=R0_ff_CQZ_D_LUT4_O_12_I1 I2=R0_ff_CQZ_D_LUT4_O_12_I2 I3=IP(10) O=R0_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I1_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_12_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_12_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_12_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_12_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_12_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_12_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I1_O I3=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I1_O O=R0_ff_CQZ_D_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=IP(12) I2=R0_ff_CQZ_D_LUT4_O_13_I2 I3=R0_ff_CQZ_D_LUT4_O_13_I3 O=R0_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_13_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_13_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=IP(13) I3=R0_ff_CQZ_D_LUT4_O_14_I3 O=R0_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0 I1=R0_ff_CQZ_D_LUT4_O_8_I0 I2=R0_ff_CQZ_D_LUT4_O_15_I2 I3=IP(14) O=R0_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=key_r(51) I1=key_r(31) I2=uk.decrypt I3=IP(49) O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(29) I1=key_r(36) I2=uk.decrypt I3=IP(48) O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(45) I1=key_r(52) I2=uk.decrypt I3=IP(53) O=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=IP(15) I3=R0_ff_CQZ_D_LUT4_O_16_I3 O=R0_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_I3_O I3=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_16_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_I3_I1 I2=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_I3_I2 I3=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_30_I3 I1=R0_ff_CQZ_D_LUT4_O_17_I1 I2=R0_ff_CQZ_D_LUT4_O_17_I2 I3=IP(16) O=R0_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_17_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_17_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=IP(17) I3=R0_ff_CQZ_D_LUT4_O_18_I3 O=R0_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_18_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_19_I0 I1=R0_ff_CQZ_D_LUT4_O_19_I1 I2=R0_ff_CQZ_D_LUT4_O_19_I2 I3=IP(18) O=R0_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_19_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_19_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_19_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_19_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_19_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_19_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_19_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_19_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=key_r(22) I1=key_r(29) I2=uk.decrypt I3=IP(53) O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(28) I1=key_r(35) I2=uk.decrypt I3=IP(56) O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(44) I1=key_r(51) I2=uk.decrypt I3=IP(54) O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(2) I1=key_r(9) I2=uk.decrypt I3=IP(55) O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_I3_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_1_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I2 I3=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3 O=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_I3_I1 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=K1(1) I1=IP(6) I2=R0_ff_CQZ_D_LUT4_O_2_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3 O=R0_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0 I1=R0_ff_CQZ_D_LUT4_O_20_I1 I2=R0_ff_CQZ_D_LUT4_O_20_I2 I3=IP(20) O=R0_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011101111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_20_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_20_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_20_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_20_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_20_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_26_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2 O=R0_ff_CQZ_D_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=IP(21) I2=R0_ff_CQZ_D_LUT4_O_21_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I3 O=R0_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_I0_I3 O=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=key_r(36) I1=key_r(43) I2=uk.decrypt I3=IP(61) O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(37) I1=key_r(44) I2=uk.decrypt I3=IP(62) O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(49) I1=key_r(1) I2=uk.decrypt I3=IP(63) O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(0) I1=key_r(7) I2=uk.decrypt I3=IP(64) O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_I3_O O=R0_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101100001111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2 I3=IP(22) O=R0_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=key_r(52) I1=key_r(0) I2=uk.decrypt I3=IP(59) O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(35) I1=key_r(42) I2=uk.decrypt I3=IP(60) O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(30) I1=key_r(37) I2=uk.decrypt I3=IP(57) O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(15) I1=key_r(22) I2=uk.decrypt I3=IP(58) O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_23_I0 I1=R0_ff_CQZ_D_LUT4_O_23_I1 I2=R0_ff_CQZ_D_LUT4_O_23_I2 I3=IP(23) O=R0_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I3 I3=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_23_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_23_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_23_I1_LUT4_O_I3_LUT4_I2_I3 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_23_I1_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_23_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_23_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_23_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_23_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_23_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_23_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_23_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_24_I0 I1=R0_ff_CQZ_D_LUT4_O_24_I1 I2=R0_ff_CQZ_D_LUT4_O_24_I2 I3=IP(24) O=R0_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I2=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=IP(25) I3=R0_ff_CQZ_D_LUT4_O_25_I3 O=R0_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_25_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2 I3=IP(26) O=R0_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000010111111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_12_I1 O=R0_ff_CQZ_D_LUT4_O_26_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I1_O I1=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_26_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_26_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_26_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_26_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_26_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_26_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=key_r(13) I1=key_r(20) I2=uk.decrypt I3=IP(49) O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(54) I1=key_r(4) I2=uk.decrypt I3=IP(44) O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=key_r(25) I1=key_r(32) I2=uk.decrypt I3=IP(47) O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(33) I1=key_r(40) I2=uk.decrypt I3=IP(48) O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(17) I1=key_r(24) I2=uk.decrypt I3=IP(46) O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(48) I1=key_r(55) I2=uk.decrypt I3=IP(45) O=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=IP(27) I3=R0_ff_CQZ_D_LUT4_O_27_I3 O=R0_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=IP(28) I2=R0_ff_CQZ_D_LUT4_O_28_I2 I3=R0_ff_CQZ_D_LUT4_O_28_I3 O=R0_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2_LUT4_I2_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100011100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_19_I2 I2=R0_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_28_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=IP(29) I3=R0_ff_CQZ_D_LUT4_O_29_I3 O=R0_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I2 I2=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I3 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001100110001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(55) I1=key_r(5) I2=uk.decrypt I3=IP(45) O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(46) I1=key_r(53) I2=uk.decrypt I3=IP(40) O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=key_r(26) I1=key_r(33) I2=uk.decrypt I3=IP(42) O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(10) I1=key_r(17) I2=uk.decrypt I3=IP(44) O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(18) I1=key_r(25) I2=uk.decrypt I3=IP(41) O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(27) I1=key_r(34) I2=uk.decrypt I3=IP(43) O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_3_I0 I1=R0_ff_CQZ_D_LUT4_O_3_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I2 I3=IP(9) O=R0_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=K1(1) I1=IP(30) I2=R0_ff_CQZ_D_LUT4_O_30_I2 I3=R0_ff_CQZ_D_LUT4_O_30_I3 O=R0_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I2 I3=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_30_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_1_O I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_30_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_24_I0_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_2_I2_LUT4_I1_I0_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I2 I3=IP(32) O=R0_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000001001111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110111001111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_31_I0_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110011001010
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_31_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I2=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_23_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3 I3=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001101011111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I2=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000111111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_3_I1 I3=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3 O=R0_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_4_I0 I1=R0_ff_CQZ_D_LUT4_O_4_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I2 I3=IP(19) O=R0_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_I2_I3 O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_4_I1 I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I2 I2=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=IP(31) I2=R0_ff_CQZ_D_LUT4_O_5_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I3 O=R0_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(34) I1=key_r(41) I2=uk.decrypt I3=IP(37) O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=key_r(40) I1=key_r(47) I2=uk.decrypt I3=IP(64) O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=key_r(4) I1=key_r(11) I2=uk.decrypt I3=IP(33) O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(6) I1=key_r(13) I2=uk.decrypt I3=IP(36) O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(53) I1=key_r(3) I2=uk.decrypt I3=IP(35) O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(19) I1=key_r(26) I2=uk.decrypt I3=IP(34) O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_23_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0 I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_6_I2 I3=IP(11) O=R0_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100001011
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(23) I1=key_r(30) I2=uk.decrypt I3=IP(57) O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(7) I1=key_r(14) I2=uk.decrypt I3=IP(52) O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_I3_I1 I2=R0_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3 I2=R0_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I2 I3=R0_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=IP(1) I2=R0_ff_CQZ_D_LUT4_O_7_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I3 O=R0_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I1_O I3=R0_ff_CQZ_D_LUT4_O_12_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_8_I0 I1=R0_ff_CQZ_D_LUT4_O_8_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I2 I3=IP(3) O=R0_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000010001111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_I0 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_8_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_11_I2 I3=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_11_I2_LUT4_O_I3_LUT4_I2_I0 I3=R0_ff_CQZ_D_LUT4_O_15_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=IP(5) I3=R0_ff_CQZ_D_LUT4_O_9_I3 O=R0_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111110101
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(28) I1=key_r(21) I2=IP(33) I3=uk.decrypt O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110001011010
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(9) I1=key_r(16) I2=uk.decrypt I3=IP(60) O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_I3_O I3=R0_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100001011
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001101011111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_I3_O O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001111110101
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_2_O I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I2_LUT4_I0_I3 I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1 I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2 I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(12) I1=key_r(19) I2=uk.decrypt I3=IP(41) O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=key_r(20) I1=key_r(27) I2=uk.decrypt I3=IP(36) O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_19_I1_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111100
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=key_r(41) I1=key_r(48) I2=uk.decrypt I3=IP(39) O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(24) I1=key_r(6) I2=uk.decrypt I3=IP(37) O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(32) I1=key_r(39) I2=uk.decrypt I3=IP(40) O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=key_r(47) I1=key_r(54) I2=uk.decrypt I3=IP(38) O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=R0_ff_CQZ_D_LUT4_O_19_I2_LUT4_O_I3_LUT4_O_I1 I3=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_2_O I1=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_1_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=R0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=R0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=R0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=uk.K_r10(42) I1=uk.K_r10(23) I2=uk.decrypt I3=R10(21) O=R10_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(30) I1=uk.K_r10(35) I2=uk.decrypt I3=R10(16) O=R10_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(12) I1=uk.K_r10(46) I2=uk.decrypt I3=R10(17) O=R10_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_10_O I3=R10_LUT4_I3_11_O O=R10_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_10_O I3=R10_LUT4_I3_11_O O=R10_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_10_O I3=R10_LUT4_I3_11_O O=R10_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r10(53) I1=uk.K_r10(5) I2=uk.decrypt I3=R10(12) O=R10_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_11_O I3=R10_LUT4_I3_10_O O=R10_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r10(1) I1=uk.K_r10(37) I2=uk.decrypt I3=R10(32) O=R10_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(50) I1=uk.K_r10(0) I2=uk.decrypt I3=R10(31) O=R10_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(7) I1=uk.K_r10(43) I2=uk.decrypt I3=R10(30) O=R10_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(37) I1=uk.K_r10(42) I2=uk.decrypt I3=R10(29) O=R10_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(38) I1=uk.K_r10(15) I2=uk.decrypt I3=R10(28) O=R10_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_16_O I3=R10_LUT4_I3_17_O O=R10_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_16_O I3=R10_LUT4_I3_17_O O=R10_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_16_O I3=R10_LUT4_I3_17_O O=R10_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r10(22) I1=uk.K_r10(31) I2=uk.decrypt I3=R10(1) O=R10_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_17_O I3=R10_LUT4_I3_16_O O=R10_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r10(6) I1=uk.K_r10(40) I2=uk.decrypt I3=R10(8) O=R10_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(40) I1=uk.K_r10(17) I2=uk.decrypt I3=R10(7) O=R10_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(21) I1=uk.K_r10(2) I2=uk.decrypt I3=R10(17) O=R10_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(46) I1=uk.K_r10(55) I2=uk.decrypt I3=R10(6) O=R10_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(55) I1=uk.K_r10(32) I2=uk.decrypt I3=R10(5) O=R10_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(11) I1=uk.K_r10(20) I2=uk.decrypt I3=R10(9) O=R10_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_22_O I3=R10_LUT4_I3_23_O O=R10_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_22_O I3=R10_LUT4_I3_23_O O=R10_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_22_O I3=R10_LUT4_I3_23_O O=R10_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r10(19) I1=uk.K_r10(53) I2=uk.decrypt I3=R10(4) O=R10_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_23_O I3=R10_LUT4_I3_22_O O=R10_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r10(29) I1=uk.K_r10(38) I2=uk.decrypt I3=R10(24) O=R10_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(31) I1=uk.K_r10(8) I2=uk.decrypt I3=R10(23) O=R10_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(14) I1=uk.K_r10(50) I2=uk.decrypt I3=R10(22) O=R10_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(23) I1=uk.K_r10(28) I2=uk.decrypt I3=R10(21) O=R10_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(52) I1=uk.K_r10(29) I2=uk.decrypt I3=R10(25) O=R10_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_28_O I3=R10_LUT4_I3_29_O O=R10_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_28_O I3=R10_LUT4_I3_29_O O=R10_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_28_O I3=R10_LUT4_I3_29_O O=R10_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r10(8) I1=uk.K_r10(44) I2=uk.decrypt I3=R10(20) O=R10_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_29_O I3=R10_LUT4_I3_28_O O=R10_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r10(15) I1=uk.K_r10(51) I2=uk.decrypt I3=R10(18) O=R10_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(25) I1=uk.K_r10(34) I2=uk.decrypt I3=R10(10) O=R10_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(17) I1=uk.K_r10(26) I2=uk.decrypt I3=R10(9) O=R10_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(41) I1=uk.K_r10(18) I2=uk.decrypt I3=R10(12) O=R10_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(26) I1=uk.K_r10(3) I2=uk.decrypt I3=R10(11) O=R10_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(20) I1=uk.K_r10(54) I2=uk.decrypt I3=R10(8) O=R10_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_34_O I3=R10_LUT4_I3_35_O O=R10_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_34_O I3=R10_LUT4_I3_35_O O=R10_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_34_O I3=R10_LUT4_I3_35_O O=R10_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r10(54) I1=uk.K_r10(6) I2=uk.decrypt I3=R10(13) O=R10_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_35_O I3=R10_LUT4_I3_34_O O=R10_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r10(5) I1=uk.K_r10(39) I2=uk.decrypt I3=R10(4) O=R10_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(27) I1=uk.K_r10(4) I2=uk.decrypt I3=R10(3) O=R10_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(18) I1=uk.K_r10(27) I2=uk.decrypt I3=R10(2) O=R10_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(3) I1=uk.K_r10(12) I2=uk.decrypt I3=R10(1) O=R10_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(45) I1=uk.K_r10(22) I2=uk.decrypt I3=R10(20) O=R10_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(33) I1=uk.K_r10(10) I2=uk.decrypt I3=R10(5) O=R10_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_40_O I3=R10_LUT4_I3_41_O O=R10_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_40_O I3=R10_LUT4_I3_41_O O=R10_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_40_O I3=R10_LUT4_I3_41_O O=R10_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r10(39) I1=uk.K_r10(48) I2=uk.decrypt I3=R10(32) O=R10_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_41_O I3=R10_LUT4_I3_40_O O=R10_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r10(0) I1=uk.K_r10(36) I2=uk.decrypt I3=R10(25) O=R10_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(49) I1=uk.K_r10(30) I2=uk.decrypt I3=R10(27) O=R10_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(36) I1=uk.K_r10(45) I2=uk.decrypt I3=R10(28) O=R10_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(16) I1=uk.K_r10(21) I2=uk.decrypt I3=R10(26) O=R10_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(28) I1=uk.K_r10(9) I2=uk.decrypt I3=R10(29) O=R10_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_46_O I3=R10_LUT4_I3_47_O O=R10_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_46_O I3=R10_LUT4_I3_47_O O=R10_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_46_O I3=R10_LUT4_I3_47_O O=R10_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r10(51) I1=uk.K_r10(1) I2=uk.decrypt I3=R10(24) O=R10_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_47_O I3=R10_LUT4_I3_46_O O=R10_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r10(2) I1=uk.K_r10(7) I2=uk.decrypt I3=R10(19) O=R10_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(48) I1=uk.K_r10(25) I2=uk.decrypt I3=R10(14) O=R10_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(47) I1=uk.K_r10(24) I2=uk.decrypt I3=R10(13) O=R10_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(32) I1=uk.K_r10(41) I2=uk.decrypt I3=R10(16) O=R10_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r10(24) I1=uk.K_r10(33) I2=uk.decrypt I3=R10(15) O=R10_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_O I3=R10_LUT4_I3_1_O O=R10_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_O I3=R10_LUT4_I3_1_O O=R10_LUT4_I3_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_O I3=R10_LUT4_I3_1_O O=R10_LUT4_I3_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R10_LUT4_I3_1_O I3=R10_LUT4_I3_O O=R10_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=R10(1) D=R10_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(2) D=R10_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(11) D=R10_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(12) D=R10_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(13) D=R10_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(14) D=R10_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(15) D=R10_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(16) D=R10_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(17) D=R10_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(18) D=R10_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(19) D=R10_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(20) D=R10_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(3) D=R10_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(21) D=R10_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(22) D=R10_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(23) D=R10_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(24) D=R10_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(25) D=R10_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(26) D=R10_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(27) D=R10_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(28) D=R10_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(29) D=R10_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(30) D=R10_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(4) D=R10_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(31) D=R10_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(32) D=R10_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(5) D=R10_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(6) D=R10_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(7) D=R10_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(8) D=R10_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(9) D=R10_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R10(10) D=R10_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:176.1-177.28|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r11(7) I1=uk.K_r11(16) I2=uk.decrypt I3=R11(17) O=R11_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(1) I1=uk.K_r11(38) I2=uk.decrypt I3=R11(18) O=R11_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(55) I1=uk.K_r11(3) I2=uk.decrypt I3=R11(17) O=R11_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_10_O I3=R11_LUT4_I3_11_O O=R11_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_10_O I3=R11_LUT4_I3_11_O O=R11_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_10_O I3=R11_LUT4_I3_11_O O=R11_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(39) I1=uk.K_r11(19) I2=uk.decrypt I3=R11(12) O=R11_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_11_O I3=R11_LUT4_I3_10_O O=R11_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(23) I1=uk.K_r11(1) I2=uk.decrypt I3=R11(29) O=R11_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(52) I1=uk.K_r11(2) I2=uk.decrypt I3=R11(30) O=R11_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(42) I1=uk.K_r11(51) I2=uk.decrypt I3=R11(32) O=R11_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(36) I1=uk.K_r11(14) I2=uk.decrypt I3=R11(31) O=R11_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(8) I1=uk.K_r11(45) I2=uk.decrypt I3=R11(1) O=R11_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_16_O I3=R11_LUT4_I3_17_O O=R11_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_16_O I3=R11_LUT4_I3_17_O O=R11_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_16_O I3=R11_LUT4_I3_17_O O=R11_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r11(51) I1=uk.K_r11(29) I2=uk.decrypt I3=R11(28) O=R11_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_17_O I3=R11_LUT4_I3_16_O O=R11_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(17) I1=uk.K_r11(54) I2=uk.decrypt I3=R11(8) O=R11_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(26) I1=uk.K_r11(6) I2=uk.decrypt I3=R11(7) O=R11_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(31) I1=uk.K_r11(36) I2=uk.decrypt I3=R11(20) O=R11_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(32) I1=uk.K_r11(12) I2=uk.decrypt I3=R11(6) O=R11_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(41) I1=uk.K_r11(46) I2=uk.decrypt I3=R11(5) O=R11_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(54) I1=uk.K_r11(34) I2=uk.decrypt I3=R11(9) O=R11_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_22_O I3=R11_LUT4_I3_23_O O=R11_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_22_O I3=R11_LUT4_I3_23_O O=R11_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_22_O I3=R11_LUT4_I3_23_O O=R11_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r11(5) I1=uk.K_r11(10) I2=uk.decrypt I3=R11(4) O=R11_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_23_O I3=R11_LUT4_I3_22_O O=R11_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(15) I1=uk.K_r11(52) I2=uk.decrypt I3=R11(24) O=R11_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(44) I1=uk.K_r11(22) I2=uk.decrypt I3=R11(23) O=R11_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(0) I1=uk.K_r11(9) I2=uk.decrypt I3=R11(22) O=R11_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(9) I1=uk.K_r11(42) I2=uk.decrypt I3=R11(21) O=R11_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(38) I1=uk.K_r11(43) I2=uk.decrypt I3=R11(25) O=R11_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_28_O I3=R11_LUT4_I3_29_O O=R11_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_28_O I3=R11_LUT4_I3_29_O O=R11_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_28_O I3=R11_LUT4_I3_29_O O=R11_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(49) I1=uk.K_r11(31) I2=uk.decrypt I3=R11(20) O=R11_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_29_O I3=R11_LUT4_I3_28_O O=R11_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(43) I1=uk.K_r11(21) I2=uk.decrypt I3=R11(19) O=R11_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(3) I1=uk.K_r11(40) I2=uk.decrypt I3=R11(9) O=R11_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(11) I1=uk.K_r11(48) I2=uk.decrypt I3=R11(10) O=R11_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(12) I1=uk.K_r11(17) I2=uk.decrypt I3=R11(11) O=R11_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(27) I1=uk.K_r11(32) I2=uk.decrypt I3=R11(12) O=R11_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(40) I1=uk.K_r11(20) I2=uk.decrypt I3=R11(13) O=R11_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_34_O I3=R11_LUT4_I3_35_O O=R11_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_34_O I3=R11_LUT4_I3_35_O O=R11_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_34_O I3=R11_LUT4_I3_35_O O=R11_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(6) I1=uk.K_r11(11) I2=uk.decrypt I3=R11(8) O=R11_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_35_O I3=R11_LUT4_I3_34_O O=R11_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(13) I1=uk.K_r11(18) I2=uk.decrypt I3=R11(3) O=R11_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(48) I1=uk.K_r11(53) I2=uk.decrypt I3=R11(4) O=R11_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(4) I1=uk.K_r11(41) I2=uk.decrypt I3=R11(2) O=R11_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(46) I1=uk.K_r11(26) I2=uk.decrypt I3=R11(1) O=R11_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(28) I1=uk.K_r11(37) I2=uk.decrypt I3=R11(21) O=R11_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(19) I1=uk.K_r11(24) I2=uk.decrypt I3=R11(5) O=R11_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_40_O I3=R11_LUT4_I3_41_O O=R11_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_40_O I3=R11_LUT4_I3_41_O O=R11_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_40_O I3=R11_LUT4_I3_41_O O=R11_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(25) I1=uk.K_r11(5) I2=uk.decrypt I3=R11(32) O=R11_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_41_O I3=R11_LUT4_I3_40_O O=R11_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(22) I1=uk.K_r11(0) I2=uk.decrypt I3=R11(28) O=R11_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(35) I1=uk.K_r11(44) I2=uk.decrypt I3=R11(27) O=R11_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(2) I1=uk.K_r11(35) I2=uk.decrypt I3=R11(26) O=R11_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(45) I1=uk.K_r11(50) I2=uk.decrypt I3=R11(25) O=R11_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(37) I1=uk.K_r11(15) I2=uk.decrypt I3=R11(24) O=R11_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_46_O I3=R11_LUT4_I3_47_O O=R11_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_46_O I3=R11_LUT4_I3_47_O O=R11_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_46_O I3=R11_LUT4_I3_47_O O=R11_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r11(14) I1=uk.K_r11(23) I2=uk.decrypt I3=R11(29) O=R11_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_47_O I3=R11_LUT4_I3_46_O O=R11_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_4_O I3=R11_LUT4_I3_5_O O=R11_LUT4_I3_4_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_4_O I3=R11_LUT4_I3_5_O O=R11_LUT4_I3_4_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_4_O I3=R11_LUT4_I3_5_O O=R11_LUT4_I3_4_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(16) I1=uk.K_r11(49) I2=uk.decrypt I3=R11(16) O=R11_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R11_LUT4_I3_5_O I3=R11_LUT4_I3_4_O O=R11_LUT4_I3_5_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r11(33) I1=uk.K_r11(13) I2=uk.decrypt I3=R11(13) O=R11_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(34) I1=uk.K_r11(39) I2=uk.decrypt I3=R11(14) O=R11_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(18) I1=uk.K_r11(55) I2=uk.decrypt I3=R11(16) O=R11_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r11(10) I1=uk.K_r11(47) I2=uk.decrypt I3=R11(15) O=R11_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=R11(1) D=R11_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(2) D=R11_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(11) D=R11_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(12) D=R11_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(13) D=R11_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(14) D=R11_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(15) D=R11_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(16) D=R11_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(17) D=R11_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(18) D=R11_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(19) D=R11_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(20) D=R11_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(3) D=R11_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(21) D=R11_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(22) D=R11_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(23) D=R11_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(24) D=R11_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(25) D=R11_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(26) D=R11_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(27) D=R11_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(28) D=R11_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(29) D=R11_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(30) D=R11_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(4) D=R11_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(31) D=R11_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(32) D=R11_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(5) D=R11_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(6) D=R11_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(7) D=R11_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(8) D=R11_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(9) D=R11_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R11(10) D=R11_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:182.1-183.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r12(14) I1=uk.K_r12(51) I2=uk.decrypt I3=R12(21) O=R12_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(2) I1=uk.K_r12(8) I2=uk.decrypt I3=R12(16) O=R12_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(41) I1=uk.K_r12(17) I2=uk.decrypt I3=R12(17) O=R12_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_10_O I3=R12_LUT4_I3_11_O O=R12_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_10_O I3=R12_LUT4_I3_11_O O=R12_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_10_O I3=R12_LUT4_I3_11_O O=R12_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(25) I1=uk.K_r12(33) I2=uk.decrypt I3=R12(12) O=R12_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_11_O I3=R12_LUT4_I3_10_O O=R12_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(28) I1=uk.K_r12(38) I2=uk.decrypt I3=R12(32) O=R12_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(22) I1=uk.K_r12(28) I2=uk.decrypt I3=R12(31) O=R12_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(38) I1=uk.K_r12(16) I2=uk.decrypt I3=R12(30) O=R12_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(9) I1=uk.K_r12(15) I2=uk.decrypt I3=R12(29) O=R12_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(37) I1=uk.K_r12(43) I2=uk.decrypt I3=R12(28) O=R12_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_16_O I3=R12_LUT4_I3_17_O O=R12_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_16_O I3=R12_LUT4_I3_17_O O=R12_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_16_O I3=R12_LUT4_I3_17_O O=R12_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(49) I1=uk.K_r12(0) I2=uk.decrypt I3=R12(1) O=R12_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_17_O I3=R12_LUT4_I3_16_O O=R12_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(12) I1=uk.K_r12(20) I2=uk.decrypt I3=R12(7) O=R12_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(18) I1=uk.K_r12(26) I2=uk.decrypt I3=R12(6) O=R12_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(52) I1=uk.K_r12(30) I2=uk.decrypt I3=R12(17) O=R12_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(27) I1=uk.K_r12(3) I2=uk.decrypt I3=R12(5) O=R12_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(3) I1=uk.K_r12(11) I2=uk.decrypt I3=R12(8) O=R12_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(40) I1=uk.K_r12(48) I2=uk.decrypt I3=R12(9) O=R12_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_22_O I3=R12_LUT4_I3_23_O O=R12_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_22_O I3=R12_LUT4_I3_23_O O=R12_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_22_O I3=R12_LUT4_I3_23_O O=R12_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r12(48) I1=uk.K_r12(24) I2=uk.decrypt I3=R12(4) O=R12_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_23_O I3=R12_LUT4_I3_22_O O=R12_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(50) I1=uk.K_r12(1) I2=uk.decrypt I3=R12(21) O=R12_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(45) I1=uk.K_r12(23) I2=uk.decrypt I3=R12(22) O=R12_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(1) I1=uk.K_r12(7) I2=uk.decrypt I3=R12(24) O=R12_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(30) I1=uk.K_r12(36) I2=uk.decrypt I3=R12(23) O=R12_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(51) I1=uk.K_r12(2) I2=uk.decrypt I3=R12(25) O=R12_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_28_O I3=R12_LUT4_I3_29_O O=L12_LUT4_I1_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_28_O I3=R12_LUT4_I3_29_O O=R12_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_28_O I3=R12_LUT4_I3_29_O O=R12_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(35) I1=uk.K_r12(45) I2=uk.decrypt I3=R12(20) O=R12_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_29_O I3=R12_LUT4_I3_28_O O=L12_LUT4_I1_2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(42) I1=uk.K_r12(52) I2=uk.decrypt I3=R12(18) O=R12_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(55) I1=uk.K_r12(6) I2=uk.decrypt I3=R12(11) O=R12_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(13) I1=uk.K_r12(46) I2=uk.decrypt I3=R12(12) O=R12_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(54) I1=uk.K_r12(5) I2=uk.decrypt I3=R12(10) O=R12_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(46) I1=uk.K_r12(54) I2=uk.decrypt I3=R12(9) O=R12_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(26) I1=uk.K_r12(34) I2=uk.decrypt I3=R12(13) O=R12_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_34_O I3=R12_LUT4_I3_35_O O=R12_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_34_O I3=R12_LUT4_I3_35_O O=R12_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_34_O I3=R12_LUT4_I3_35_O O=R12_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(17) I1=uk.K_r12(25) I2=uk.decrypt I3=R12(8) O=R12_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_35_O I3=R12_LUT4_I3_34_O O=R12_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(34) I1=uk.K_r12(10) I2=uk.decrypt I3=R12(4) O=R12_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(24) I1=uk.K_r12(32) I2=uk.decrypt I3=R12(3) O=R12_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(47) I1=uk.K_r12(55) I2=uk.decrypt I3=R12(2) O=R12_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(32) I1=uk.K_r12(40) I2=uk.decrypt I3=R12(1) O=R12_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(44) I1=uk.K_r12(50) I2=uk.decrypt I3=R12(20) O=R12_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(11) I1=uk.K_r12(19) I2=uk.decrypt I3=R12(32) O=R12_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_40_O I3=R12_LUT4_I3_41_O O=R12_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_40_O I3=R12_LUT4_I3_41_O O=R12_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_40_O I3=R12_LUT4_I3_41_O O=R12_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r12(5) I1=uk.K_r12(13) I2=uk.decrypt I3=R12(5) O=R12_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_41_O I3=R12_LUT4_I3_40_O O=R12_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(31) I1=uk.K_r12(9) I2=uk.decrypt I3=R12(25) O=R12_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(21) I1=uk.K_r12(31) I2=uk.decrypt I3=R12(27) O=R12_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(8) I1=uk.K_r12(14) I2=uk.decrypt I3=R12(28) O=R12_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(43) I1=uk.K_r12(49) I2=uk.decrypt I3=R12(26) O=R12_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(0) I1=uk.K_r12(37) I2=uk.decrypt I3=R12(29) O=R12_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_46_O I3=R12_LUT4_I3_47_O O=R12_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_46_O I3=R12_LUT4_I3_47_O O=R12_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_46_O I3=R12_LUT4_I3_47_O O=R12_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r12(23) I1=uk.K_r12(29) I2=uk.decrypt I3=R12(24) O=R12_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_47_O I3=R12_LUT4_I3_46_O O=R12_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r12(29) I1=uk.K_r12(35) I2=uk.decrypt I3=R12(19) O=R12_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(20) I1=uk.K_r12(53) I2=uk.decrypt I3=R12(14) O=R12_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(19) I1=uk.K_r12(27) I2=uk.decrypt I3=R12(13) O=R12_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(4) I1=uk.K_r12(12) I2=uk.decrypt I3=R12(16) O=R12_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r12(53) I1=uk.K_r12(4) I2=uk.decrypt I3=R12(15) O=R12_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_O I3=R12_LUT4_I3_1_O O=R12_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_O I3=R12_LUT4_I3_1_O O=R12_LUT4_I3_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_O I3=R12_LUT4_I3_1_O O=R12_LUT4_I3_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R12_LUT4_I3_1_O I3=R12_LUT4_I3_O O=R12_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=R12(1) D=R12_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(2) D=R12_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(11) D=R12_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(12) D=R12_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(13) D=R12_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(14) D=R12_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(15) D=R12_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(16) D=R12_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(17) D=R12_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(18) D=R12_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(19) D=R12_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(20) D=R12_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(3) D=R12_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(21) D=R12_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(22) D=R12_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(23) D=R12_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(24) D=R12_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(25) D=R12_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(26) D=R12_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(27) D=R12_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(28) D=R12_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(29) D=R12_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(30) D=R12_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(4) D=R12_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(31) D=R12_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(32) D=R12_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(5) D=R12_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(6) D=R12_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(7) D=R12_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(8) D=R12_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(9) D=R12_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R12(10) D=R12_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:188.1-189.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r13(38) I1=uk.K_r13(44) I2=uk.decrypt I3=R13(17) O=R13_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(28) I1=uk.K_r13(7) I2=uk.decrypt I3=R13(18) O=R13_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(11) I1=uk.K_r13(47) I2=uk.decrypt I3=R13(12) O=R13_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_10_O I3=R13_LUT4_I3_11_O O=R13_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_10_O I3=R13_LUT4_I3_11_O O=R13_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_10_O I3=R13_LUT4_I3_11_O O=R13_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(27) I1=uk.K_r13(6) I2=uk.decrypt I3=R13(17) O=R13_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_11_O I3=R13_LUT4_I3_10_O O=R13_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(51) I1=uk.K_r13(30) I2=uk.decrypt I3=R13(30) O=R13_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(8) I1=uk.K_r13(42) I2=uk.decrypt I3=R13(31) O=R13_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(50) I1=uk.K_r13(29) I2=uk.decrypt I3=R13(29) O=R13_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(14) I1=uk.K_r13(52) I2=uk.decrypt I3=R13(32) O=R13_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(35) I1=uk.K_r13(14) I2=uk.decrypt I3=R13(1) O=R13_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_16_O I3=R13_LUT4_I3_17_O O=R13_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_16_O I3=R13_LUT4_I3_17_O O=R13_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_16_O I3=R13_LUT4_I3_17_O O=R13_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r13(23) I1=uk.K_r13(2) I2=uk.decrypt I3=R13(28) O=R13_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_17_O I3=R13_LUT4_I3_16_O O=R13_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(4) I1=uk.K_r13(40) I2=uk.decrypt I3=R13(6) O=R13_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(13) I1=uk.K_r13(17) I2=uk.decrypt I3=R13(5) O=R13_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(30) I1=uk.K_r13(9) I2=uk.decrypt I3=R13(20) O=R13_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(46) I1=uk.K_r13(25) I2=uk.decrypt I3=R13(8) O=R13_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(55) I1=uk.K_r13(34) I2=uk.decrypt I3=R13(7) O=R13_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(26) I1=uk.K_r13(5) I2=uk.decrypt I3=R13(9) O=R13_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_22_O I3=R13_LUT4_I3_23_O O=R13_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_22_O I3=R13_LUT4_I3_23_O O=R13_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_22_O I3=R13_LUT4_I3_23_O O=R13_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r13(34) I1=uk.K_r13(13) I2=uk.decrypt I3=R13(4) O=R13_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_23_O I3=R13_LUT4_I3_22_O O=R13_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(36) I1=uk.K_r13(15) I2=uk.decrypt I3=R13(21) O=R13_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(31) I1=uk.K_r13(37) I2=uk.decrypt I3=R13(22) O=R13_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(42) I1=uk.K_r13(21) I2=uk.decrypt I3=R13(24) O=R13_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(16) I1=uk.K_r13(50) I2=uk.decrypt I3=R13(23) O=R13_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(37) I1=uk.K_r13(16) I2=uk.decrypt I3=R13(25) O=R13_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_28_O I3=R13_LUT4_I3_29_O O=R13_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_28_O I3=R13_LUT4_I3_29_O O=R13_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_28_O I3=R13_LUT4_I3_29_O O=R13_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(21) I1=uk.K_r13(0) I2=uk.decrypt I3=R13(20) O=R13_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_29_O I3=R13_LUT4_I3_28_O O=R13_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(15) I1=uk.K_r13(49) I2=uk.decrypt I3=R13(19) O=R13_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(24) I1=uk.K_r13(3) I2=uk.decrypt I3=R13(12) O=R13_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(32) I1=uk.K_r13(11) I2=uk.decrypt I3=R13(9) O=R13_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(41) I1=uk.K_r13(20) I2=uk.decrypt I3=R13(11) O=R13_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(40) I1=uk.K_r13(19) I2=uk.decrypt I3=R13(10) O=R13_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(12) I1=uk.K_r13(48) I2=uk.decrypt I3=R13(13) O=R13_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_34_O I3=R13_LUT4_I3_35_O O=R13_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_34_O I3=R13_LUT4_I3_35_O O=R13_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_34_O I3=R13_LUT4_I3_35_O O=R13_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(3) I1=uk.K_r13(39) I2=uk.decrypt I3=R13(8) O=R13_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_35_O I3=R13_LUT4_I3_34_O O=R13_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(10) I1=uk.K_r13(46) I2=uk.decrypt I3=R13(3) O=R13_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(20) I1=uk.K_r13(24) I2=uk.decrypt I3=R13(4) O=R13_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(33) I1=uk.K_r13(12) I2=uk.decrypt I3=R13(2) O=R13_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(18) I1=uk.K_r13(54) I2=uk.decrypt I3=R13(1) O=R13_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(43) I1=uk.K_r13(22) I2=uk.decrypt I3=R13(16) O=R13_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(48) I1=uk.K_r13(27) I2=uk.decrypt I3=R13(5) O=R13_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_40_O I3=R13_LUT4_I3_41_O O=R13_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_40_O I3=R13_LUT4_I3_41_O O=R13_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_40_O I3=R13_LUT4_I3_41_O O=R13_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(54) I1=uk.K_r13(33) I2=uk.decrypt I3=R13(32) O=R13_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_41_O I3=R13_LUT4_I3_40_O O=R13_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(44) I1=uk.K_r13(23) I2=uk.decrypt I3=R13(25) O=R13_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(7) I1=uk.K_r13(45) I2=uk.decrypt I3=R13(27) O=R13_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(29) I1=uk.K_r13(8) I2=uk.decrypt I3=R13(26) O=R13_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(49) I1=uk.K_r13(28) I2=uk.decrypt I3=R13(28) O=R13_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(9) I1=uk.K_r13(43) I2=uk.decrypt I3=R13(24) O=R13_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_46_O I3=R13_LUT4_I3_47_O O=R13_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_46_O I3=R13_LUT4_I3_47_O O=R13_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_46_O I3=R13_LUT4_I3_47_O O=R13_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(45) I1=uk.K_r13(51) I2=uk.decrypt I3=R13(29) O=R13_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_47_O I3=R13_LUT4_I3_46_O O=R13_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_4_O I3=R13_LUT4_I3_5_O O=R13_LUT4_I3_4_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_4_O I3=R13_LUT4_I3_5_O O=R13_LUT4_I3_4_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_4_O I3=R13_LUT4_I3_5_O O=R13_LUT4_I3_4_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r13(0) I1=uk.K_r13(38) I2=uk.decrypt I3=R13(21) O=R13_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R13_LUT4_I3_5_O I3=R13_LUT4_I3_4_O O=R13_LUT4_I3_5_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r13(39) I1=uk.K_r13(18) I2=uk.decrypt I3=R13(15) O=R13_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(47) I1=uk.K_r13(26) I2=uk.decrypt I3=R13(16) O=R13_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(6) I1=uk.K_r13(10) I2=uk.decrypt I3=R13(14) O=R13_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r13(5) I1=uk.K_r13(41) I2=uk.decrypt I3=R13(13) O=R13_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=R13(1) D=R13_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:194.1-195.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R13(2) D=R13_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:194.1-195.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R13(11) D=R13_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:194.1-195.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R13(12) D=R13_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:194.1-195.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R13(13) D=R13_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:194.1-195.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R13(14) D=R13_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:194.1-195.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R13(15) D=R13_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:194.1-195.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R13(16) D=R13_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:194.1-195.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R13(17) D=R13_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=FP(62) D=R14_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=FP(36) D=R14_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=FP(63) D=R14_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=FP(64) D=R14_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=FP(37) D=R14_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=FP(38) D=R14_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=FP(39) D=R14_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=FP(40) D=R14_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=FP(41) D=R14_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=FP(42) D=R14_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:200.1-201.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r1(8) I1=uk.K_r1(2) I2=uk.decrypt I3=R1(16) O=R1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(51) I1=uk.K_r1(14) I2=uk.decrypt I3=R1(21) O=R1_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(17) I1=uk.K_r1(41) I2=uk.decrypt I3=R1(17) O=R1_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_10_O I3=R1_LUT4_I3_11_O O=R1_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_10_O I3=R1_LUT4_I3_11_O O=R1_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_10_O I3=R1_LUT4_I3_11_O O=R1_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(33) I1=uk.K_r1(25) I2=uk.decrypt I3=R1(12) O=R1_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_11_O I3=R1_LUT4_I3_10_O O=R1_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(38) I1=uk.K_r1(28) I2=uk.decrypt I3=R1(32) O=R1_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(28) I1=uk.K_r1(22) I2=uk.decrypt I3=R1(31) O=R1_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(16) I1=uk.K_r1(38) I2=uk.decrypt I3=R1(30) O=R1_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(15) I1=uk.K_r1(9) I2=uk.decrypt I3=R1(29) O=R1_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(43) I1=uk.K_r1(37) I2=uk.decrypt I3=R1(28) O=R1_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_16_O I3=R1_LUT4_I3_17_O O=R1_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_16_O I3=R1_LUT4_I3_17_O O=R1_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_16_O I3=R1_LUT4_I3_17_O O=R1_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(0) I1=uk.K_r1(49) I2=uk.decrypt I3=R1(1) O=R1_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_17_O I3=R1_LUT4_I3_16_O O=R1_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(26) I1=uk.K_r1(18) I2=uk.decrypt I3=R1(6) O=R1_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(3) I1=uk.K_r1(27) I2=uk.decrypt I3=R1(5) O=R1_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(35) I1=uk.K_r1(29) I2=uk.decrypt I3=R1(19) O=R1_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(11) I1=uk.K_r1(3) I2=uk.decrypt I3=R1(8) O=R1_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(20) I1=uk.K_r1(12) I2=uk.decrypt I3=R1(7) O=R1_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(48) I1=uk.K_r1(40) I2=uk.decrypt I3=R1(9) O=R1_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_22_O I3=R1_LUT4_I3_23_O O=R1_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_22_O I3=R1_LUT4_I3_23_O O=R1_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_22_O I3=R1_LUT4_I3_23_O O=R1_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r1(24) I1=uk.K_r1(48) I2=uk.decrypt I3=R1(4) O=R1_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_23_O I3=R1_LUT4_I3_22_O O=R1_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(1) I1=uk.K_r1(50) I2=uk.decrypt I3=R1(21) O=R1_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(23) I1=uk.K_r1(45) I2=uk.decrypt I3=R1(22) O=R1_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(7) I1=uk.K_r1(1) I2=uk.decrypt I3=R1(24) O=R1_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(36) I1=uk.K_r1(30) I2=uk.decrypt I3=R1(23) O=R1_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(2) I1=uk.K_r1(51) I2=uk.decrypt I3=R1(25) O=R1_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_28_O I3=R1_LUT4_I3_29_O O=R1_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_28_O I3=R1_LUT4_I3_29_O O=R1_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_28_O I3=R1_LUT4_I3_29_O O=R1_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(45) I1=uk.K_r1(35) I2=uk.decrypt I3=R1(20) O=R1_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_29_O I3=R1_LUT4_I3_28_O O=R1_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(50) I1=uk.K_r1(44) I2=uk.decrypt I3=R1(20) O=R1_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(5) I1=uk.K_r1(54) I2=uk.decrypt I3=R1(10) O=R1_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(6) I1=uk.K_r1(55) I2=uk.decrypt I3=R1(11) O=R1_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(46) I1=uk.K_r1(13) I2=uk.decrypt I3=R1(12) O=R1_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(54) I1=uk.K_r1(46) I2=uk.decrypt I3=R1(9) O=R1_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(25) I1=uk.K_r1(17) I2=uk.decrypt I3=R1(8) O=R1_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_34_O I3=R1_LUT4_I3_35_O O=R1_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_34_O I3=R1_LUT4_I3_35_O O=R1_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_34_O I3=R1_LUT4_I3_35_O O=R1_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(34) I1=uk.K_r1(26) I2=uk.decrypt I3=R1(13) O=R1_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_35_O I3=R1_LUT4_I3_34_O O=R1_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(32) I1=uk.K_r1(24) I2=uk.decrypt I3=R1(3) O=R1_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(10) I1=uk.K_r1(34) I2=uk.decrypt I3=R1(4) O=R1_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(55) I1=uk.K_r1(47) I2=uk.decrypt I3=R1(2) O=R1_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(40) I1=uk.K_r1(32) I2=uk.decrypt I3=R1(1) O=R1_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(52) I1=uk.K_r1(42) I2=uk.decrypt I3=R1(18) O=R1_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(19) I1=uk.K_r1(11) I2=uk.decrypt I3=R1(32) O=R1_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_40_O I3=R1_LUT4_I3_41_O O=R1_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_40_O I3=R1_LUT4_I3_41_O O=R1_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_40_O I3=R1_LUT4_I3_41_O O=R1_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(13) I1=uk.K_r1(5) I2=uk.decrypt I3=R1(5) O=R1_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_41_O I3=R1_LUT4_I3_40_O O=R1_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(14) I1=uk.K_r1(8) I2=uk.decrypt I3=R1(28) O=R1_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(31) I1=uk.K_r1(21) I2=uk.decrypt I3=R1(27) O=R1_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(9) I1=uk.K_r1(31) I2=uk.decrypt I3=R1(25) O=R1_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(49) I1=uk.K_r1(43) I2=uk.decrypt I3=R1(26) O=R1_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(29) I1=uk.K_r1(23) I2=uk.decrypt I3=R1(24) O=R1_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_46_O I3=R1_LUT4_I3_47_O O=R1_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_46_O I3=R1_LUT4_I3_47_O O=R1_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_46_O I3=R1_LUT4_I3_47_O O=R1_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r1(37) I1=uk.K_r1(0) I2=uk.decrypt I3=R1(29) O=R1_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_47_O I3=R1_LUT4_I3_46_O O=R1_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r1(30) I1=uk.K_r1(52) I2=uk.decrypt I3=R1(17) O=R1_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(27) I1=uk.K_r1(19) I2=uk.decrypt I3=R1(13) O=R1_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(53) I1=uk.K_r1(20) I2=uk.decrypt I3=R1(14) O=R1_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(12) I1=uk.K_r1(4) I2=uk.decrypt I3=R1(16) O=R1_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r1(4) I1=uk.K_r1(53) I2=uk.decrypt I3=R1(15) O=R1_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_O I3=R1_LUT4_I3_1_O O=R1_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_O I3=R1_LUT4_I3_1_O O=R1_LUT4_I3_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_O I3=R1_LUT4_I3_1_O O=R1_LUT4_I3_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R1_LUT4_I3_1_O I3=R1_LUT4_I3_O O=R1_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=R1(1) D=R1_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(2) D=R1_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(11) D=R1_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(12) D=R1_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(13) D=R1_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(14) D=R1_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(15) D=R1_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(16) D=R1_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(17) D=R1_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(18) D=R1_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(19) D=R1_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(20) D=R1_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(3) D=R1_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(21) D=R1_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(22) D=R1_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(23) D=R1_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(24) D=R1_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(25) D=R1_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(26) D=R1_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(27) D=R1_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(28) D=R1_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(29) D=R1_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(30) D=R1_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(4) D=R1_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(31) D=R1_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(32) D=R1_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(5) D=R1_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(6) D=R1_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(7) D=R1_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(8) D=R1_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(9) D=R1_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R1(10) D=R1_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:120.1-121.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r2(16) I1=uk.K_r2(7) I2=uk.decrypt I3=R2(17) O=R2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(38) I1=uk.K_r2(1) I2=uk.decrypt I3=R2(18) O=R2_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(19) I1=uk.K_r2(39) I2=uk.decrypt I3=R2(12) O=R2_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_10_O I3=R2_LUT4_I3_11_O O=R2_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_10_O I3=R2_LUT4_I3_11_O O=R2_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_10_O I3=R2_LUT4_I3_11_O O=R2_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r2(3) I1=uk.K_r2(55) I2=uk.decrypt I3=R2(17) O=R2_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_11_O I3=R2_LUT4_I3_10_O O=R2_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(51) I1=uk.K_r2(42) I2=uk.decrypt I3=R2(32) O=R2_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(14) I1=uk.K_r2(36) I2=uk.decrypt I3=R2(31) O=R2_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(2) I1=uk.K_r2(52) I2=uk.decrypt I3=R2(30) O=R2_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(1) I1=uk.K_r2(23) I2=uk.decrypt I3=R2(29) O=R2_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(29) I1=uk.K_r2(51) I2=uk.decrypt I3=R2(28) O=R2_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_16_O I3=R2_LUT4_I3_17_O O=R2_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_16_O I3=R2_LUT4_I3_17_O O=R2_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_16_O I3=R2_LUT4_I3_17_O O=R2_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(45) I1=uk.K_r2(8) I2=uk.decrypt I3=R2(1) O=R2_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_17_O I3=R2_LUT4_I3_16_O O=R2_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(54) I1=uk.K_r2(17) I2=uk.decrypt I3=R2(8) O=R2_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(6) I1=uk.K_r2(26) I2=uk.decrypt I3=R2(7) O=R2_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(36) I1=uk.K_r2(31) I2=uk.decrypt I3=R2(20) O=R2_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(12) I1=uk.K_r2(32) I2=uk.decrypt I3=R2(6) O=R2_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(46) I1=uk.K_r2(41) I2=uk.decrypt I3=R2(5) O=R2_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(34) I1=uk.K_r2(54) I2=uk.decrypt I3=R2(9) O=R2_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_22_O I3=R2_LUT4_I3_23_O O=R2_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_22_O I3=R2_LUT4_I3_23_O O=R2_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_22_O I3=R2_LUT4_I3_23_O O=R2_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r2(10) I1=uk.K_r2(5) I2=uk.decrypt I3=R2(4) O=R2_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_23_O I3=R2_LUT4_I3_22_O O=R2_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(9) I1=uk.K_r2(0) I2=uk.decrypt I3=R2(22) O=R2_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(42) I1=uk.K_r2(9) I2=uk.decrypt I3=R2(21) O=R2_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(52) I1=uk.K_r2(15) I2=uk.decrypt I3=R2(24) O=R2_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(22) I1=uk.K_r2(44) I2=uk.decrypt I3=R2(23) O=R2_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(31) I1=uk.K_r2(49) I2=uk.decrypt I3=R2(20) O=R2_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_28_O I3=R2_LUT4_I3_29_O O=R2_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_28_O I3=R2_LUT4_I3_29_O O=R2_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_28_O I3=R2_LUT4_I3_29_O O=R2_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r2(43) I1=uk.K_r2(38) I2=uk.decrypt I3=R2(25) O=R2_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_29_O I3=R2_LUT4_I3_28_O O=R2_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(21) I1=uk.K_r2(43) I2=uk.decrypt I3=R2(19) O=R2_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(48) I1=uk.K_r2(11) I2=uk.decrypt I3=R2(10) O=R2_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(17) I1=uk.K_r2(12) I2=uk.decrypt I3=R2(11) O=R2_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(40) I1=uk.K_r2(3) I2=uk.decrypt I3=R2(9) O=R2_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(32) I1=uk.K_r2(27) I2=uk.decrypt I3=R2(12) O=R2_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(20) I1=uk.K_r2(40) I2=uk.decrypt I3=R2(13) O=R2_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_34_O I3=R2_LUT4_I3_35_O O=R2_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_34_O I3=R2_LUT4_I3_35_O O=R2_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_34_O I3=R2_LUT4_I3_35_O O=R2_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(11) I1=uk.K_r2(6) I2=uk.decrypt I3=R2(8) O=R2_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_35_O I3=R2_LUT4_I3_34_O O=R2_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(5) I1=uk.K_r2(25) I2=uk.decrypt I3=R2(32) O=R2_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_36_O I3=R2_LUT4_I3_37_O O=R2_LUT4_I3_36_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_36_O I3=R2_LUT4_I3_37_O O=R2_LUT4_I3_36_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_36_O I3=R2_LUT4_I3_37_O O=R2_LUT4_I3_36_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(24) I1=uk.K_r2(19) I2=uk.decrypt I3=R2(5) O=R2_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_37_O I3=R2_LUT4_I3_36_O O=R2_LUT4_I3_37_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(18) I1=uk.K_r2(13) I2=uk.decrypt I3=R2(3) O=R2_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(53) I1=uk.K_r2(48) I2=uk.decrypt I3=R2(4) O=R2_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(37) I1=uk.K_r2(28) I2=uk.decrypt I3=R2(21) O=R2_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(41) I1=uk.K_r2(4) I2=uk.decrypt I3=R2(2) O=R2_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(26) I1=uk.K_r2(46) I2=uk.decrypt I3=R2(1) O=R2_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(50) I1=uk.K_r2(45) I2=uk.decrypt I3=R2(25) O=R2_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(35) I1=uk.K_r2(2) I2=uk.decrypt I3=R2(26) O=R2_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(44) I1=uk.K_r2(35) I2=uk.decrypt I3=R2(27) O=R2_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(0) I1=uk.K_r2(22) I2=uk.decrypt I3=R2(28) O=R2_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(23) I1=uk.K_r2(14) I2=uk.decrypt I3=R2(29) O=R2_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_46_O I3=R2_LUT4_I3_47_O O=R2_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_46_O I3=R2_LUT4_I3_47_O O=R2_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_46_O I3=R2_LUT4_I3_47_O O=R2_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r2(15) I1=uk.K_r2(37) I2=uk.decrypt I3=R2(24) O=R2_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_47_O I3=R2_LUT4_I3_46_O O=R2_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_4_O I3=R2_LUT4_I3_5_O O=R2_LUT4_I3_4_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_4_O I3=R2_LUT4_I3_5_O O=R2_LUT4_I3_4_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_4_O I3=R2_LUT4_I3_5_O O=R2_LUT4_I3_4_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(49) I1=uk.K_r2(16) I2=uk.decrypt I3=R2(16) O=R2_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R2_LUT4_I3_5_O I3=R2_LUT4_I3_4_O O=R2_LUT4_I3_5_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r2(13) I1=uk.K_r2(33) I2=uk.decrypt I3=R2(13) O=R2_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(39) I1=uk.K_r2(34) I2=uk.decrypt I3=R2(14) O=R2_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(55) I1=uk.K_r2(18) I2=uk.decrypt I3=R2(16) O=R2_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r2(47) I1=uk.K_r2(10) I2=uk.decrypt I3=R2(15) O=R2_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=R2(1) D=R2_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(2) D=R2_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(11) D=R2_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(12) D=R2_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(13) D=R2_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(14) D=R2_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(15) D=R2_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(16) D=R2_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(17) D=R2_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(18) D=R2_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(19) D=R2_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(20) D=R2_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(3) D=R2_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(21) D=R2_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(22) D=R2_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(23) D=R2_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(24) D=R2_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(25) D=R2_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(26) D=R2_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(27) D=R2_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(28) D=R2_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(29) D=R2_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(30) D=R2_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(4) D=R2_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(31) D=R2_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(32) D=R2_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(5) D=R2_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(6) D=R2_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(7) D=R2_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(8) D=R2_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(9) D=R2_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R2(10) D=R2_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:128.1-129.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r3(2) I1=uk.K_r3(21) I2=uk.decrypt I3=R3(17) O=R3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(51) I1=uk.K_r3(15) I2=uk.decrypt I3=R3(18) O=R3_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(46) I1=uk.K_r3(12) I2=uk.decrypt I3=R3(17) O=R3_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_10_O I3=R3_LUT4_I3_11_O O=R3_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_10_O I3=R3_LUT4_I3_11_O O=R3_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_10_O I3=R3_LUT4_I3_11_O O=R3_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(5) I1=uk.K_r3(53) I2=uk.decrypt I3=R3(12) O=R3_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_11_O I3=R3_LUT4_I3_10_O O=R3_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(37) I1=uk.K_r3(1) I2=uk.decrypt I3=R3(32) O=R3_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(0) I1=uk.K_r3(50) I2=uk.decrypt I3=R3(31) O=R3_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(43) I1=uk.K_r3(7) I2=uk.decrypt I3=R3(30) O=R3_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(42) I1=uk.K_r3(37) I2=uk.decrypt I3=R3(29) O=R3_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(15) I1=uk.K_r3(38) I2=uk.decrypt I3=R3(28) O=R3_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_16_O I3=R3_LUT4_I3_17_O O=R3_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_16_O I3=R3_LUT4_I3_17_O O=R3_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_16_O I3=R3_LUT4_I3_17_O O=R3_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(31) I1=uk.K_r3(22) I2=uk.decrypt I3=R3(1) O=R3_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_17_O I3=R3_LUT4_I3_16_O O=R3_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(40) I1=uk.K_r3(6) I2=uk.decrypt I3=R3(8) O=R3_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(17) I1=uk.K_r3(40) I2=uk.decrypt I3=R3(7) O=R3_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(22) I1=uk.K_r3(45) I2=uk.decrypt I3=R3(20) O=R3_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(55) I1=uk.K_r3(46) I2=uk.decrypt I3=R3(6) O=R3_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(32) I1=uk.K_r3(55) I2=uk.decrypt I3=R3(5) O=R3_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(53) I1=uk.K_r3(19) I2=uk.decrypt I3=R3(4) O=R3_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_22_O I3=R3_LUT4_I3_23_O O=R3_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_22_O I3=R3_LUT4_I3_23_O O=R3_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_22_O I3=R3_LUT4_I3_23_O O=R3_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r3(20) I1=uk.K_r3(11) I2=uk.decrypt I3=R3(9) O=R3_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_23_O I3=R3_LUT4_I3_22_O O=R3_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(28) I1=uk.K_r3(23) I2=uk.decrypt I3=R3(21) O=R3_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(50) I1=uk.K_r3(14) I2=uk.decrypt I3=R3(22) O=R3_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(38) I1=uk.K_r3(29) I2=uk.decrypt I3=R3(24) O=R3_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(8) I1=uk.K_r3(31) I2=uk.decrypt I3=R3(23) O=R3_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(29) I1=uk.K_r3(52) I2=uk.decrypt I3=R3(25) O=R3_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_28_O I3=R3_LUT4_I3_29_O O=R3_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_28_O I3=R3_LUT4_I3_29_O O=R3_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_28_O I3=R3_LUT4_I3_29_O O=R3_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(44) I1=uk.K_r3(8) I2=uk.decrypt I3=R3(20) O=R3_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_29_O I3=R3_LUT4_I3_28_O O=R3_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(7) I1=uk.K_r3(2) I2=uk.decrypt I3=R3(19) O=R3_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(34) I1=uk.K_r3(25) I2=uk.decrypt I3=R3(10) O=R3_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(26) I1=uk.K_r3(17) I2=uk.decrypt I3=R3(9) O=R3_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(18) I1=uk.K_r3(41) I2=uk.decrypt I3=R3(12) O=R3_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(3) I1=uk.K_r3(26) I2=uk.decrypt I3=R3(11) O=R3_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(6) I1=uk.K_r3(54) I2=uk.decrypt I3=R3(13) O=R3_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_34_O I3=R3_LUT4_I3_35_O O=R3_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_34_O I3=R3_LUT4_I3_35_O O=R3_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_34_O I3=R3_LUT4_I3_35_O O=R3_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(54) I1=uk.K_r3(20) I2=uk.decrypt I3=R3(8) O=R3_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_35_O I3=R3_LUT4_I3_34_O O=R3_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(48) I1=uk.K_r3(39) I2=uk.decrypt I3=R3(32) O=R3_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_36_O I3=R3_LUT4_I3_37_O O=R3_LUT4_I3_36_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_36_O I3=R3_LUT4_I3_37_O O=R3_LUT4_I3_36_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_36_O I3=R3_LUT4_I3_37_O O=R3_LUT4_I3_36_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r3(10) I1=uk.K_r3(33) I2=uk.decrypt I3=R3(5) O=R3_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_37_O I3=R3_LUT4_I3_36_O O=R3_LUT4_I3_37_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(4) I1=uk.K_r3(27) I2=uk.decrypt I3=R3(3) O=R3_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(39) I1=uk.K_r3(5) I2=uk.decrypt I3=R3(4) O=R3_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(23) I1=uk.K_r3(42) I2=uk.decrypt I3=R3(21) O=R3_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(27) I1=uk.K_r3(18) I2=uk.decrypt I3=R3(2) O=R3_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(12) I1=uk.K_r3(3) I2=uk.decrypt I3=R3(1) O=R3_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(36) I1=uk.K_r3(0) I2=uk.decrypt I3=R3(25) O=R3_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(30) I1=uk.K_r3(49) I2=uk.decrypt I3=R3(27) O=R3_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(45) I1=uk.K_r3(36) I2=uk.decrypt I3=R3(28) O=R3_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(21) I1=uk.K_r3(16) I2=uk.decrypt I3=R3(26) O=R3_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(1) I1=uk.K_r3(51) I2=uk.decrypt I3=R3(24) O=R3_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_46_O I3=R3_LUT4_I3_47_O O=R3_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_46_O I3=R3_LUT4_I3_47_O O=R3_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_46_O I3=R3_LUT4_I3_47_O O=R3_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r3(9) I1=uk.K_r3(28) I2=uk.decrypt I3=R3(29) O=R3_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_47_O I3=R3_LUT4_I3_46_O O=R3_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_4_O I3=R3_LUT4_I3_5_O O=R3_LUT4_I3_4_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_4_O I3=R3_LUT4_I3_5_O O=R3_LUT4_I3_4_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_4_O I3=R3_LUT4_I3_5_O O=R3_LUT4_I3_4_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(35) I1=uk.K_r3(30) I2=uk.decrypt I3=R3(16) O=R3_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R3_LUT4_I3_5_O I3=R3_LUT4_I3_4_O O=R3_LUT4_I3_5_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r3(24) I1=uk.K_r3(47) I2=uk.decrypt I3=R3(13) O=R3_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(25) I1=uk.K_r3(48) I2=uk.decrypt I3=R3(14) O=R3_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(41) I1=uk.K_r3(32) I2=uk.decrypt I3=R3(16) O=R3_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r3(33) I1=uk.K_r3(24) I2=uk.decrypt I3=R3(15) O=R3_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=R3(1) D=R3_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(2) D=R3_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(11) D=R3_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(12) D=R3_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(13) D=R3_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(14) D=R3_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(15) D=R3_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(16) D=R3_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(17) D=R3_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(18) D=R3_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(19) D=R3_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(20) D=R3_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(3) D=R3_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(21) D=R3_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(22) D=R3_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(23) D=R3_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(24) D=R3_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(25) D=R3_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(26) D=R3_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(27) D=R3_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(28) D=R3_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(29) D=R3_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(30) D=R3_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(4) D=R3_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(31) D=R3_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(32) D=R3_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(5) D=R3_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(6) D=R3_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(7) D=R3_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(8) D=R3_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(9) D=R3_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R3(10) D=R3_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:134.1-135.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r4(43) I1=uk.K_r4(35) I2=uk.decrypt I3=R4(17) O=R4_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(52) I1=uk.K_r4(16) I2=uk.decrypt I3=R4(19) O=R4_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(27) I1=uk.K_r4(46) I2=uk.decrypt I3=R4(16) O=R4_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(19) I1=uk.K_r4(13) I2=uk.decrypt I3=R4(15) O=R4_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(23) I1=uk.K_r4(15) I2=uk.decrypt I3=R4(32) O=R4_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(45) I1=uk.K_r4(9) I2=uk.decrypt I3=R4(31) O=R4_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(29) I1=uk.K_r4(21) I2=uk.decrypt I3=R4(30) O=R4_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(28) I1=uk.K_r4(51) I2=uk.decrypt I3=R4(29) O=R4_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(1) I1=uk.K_r4(52) I2=uk.decrypt I3=R4(28) O=R4_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_16_O I3=R4_LUT4_I3_17_O O=R4_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_16_O I3=R4_LUT4_I3_17_O O=R4_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_16_O I3=R4_LUT4_I3_17_O O=R4_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r4(44) I1=uk.K_r4(36) I2=uk.decrypt I3=R4(1) O=R4_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_17_O I3=R4_LUT4_I3_16_O O=R4_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r4(3) I1=uk.K_r4(54) I2=uk.decrypt I3=R4(7) O=R4_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(18) I1=uk.K_r4(12) I2=uk.decrypt I3=R4(5) O=R4_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(37) I1=uk.K_r4(29) I2=uk.decrypt I3=R4(18) O=R4_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(26) I1=uk.K_r4(20) I2=uk.decrypt I3=R4(8) O=R4_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(41) I1=uk.K_r4(3) I2=uk.decrypt I3=R4(6) O=R4_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(6) I1=uk.K_r4(25) I2=uk.decrypt I3=R4(9) O=R4_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_22_O I3=R4_LUT4_I3_23_O O=R4_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_22_O I3=R4_LUT4_I3_23_O O=R4_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_22_O I3=R4_LUT4_I3_23_O O=R4_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r4(39) I1=uk.K_r4(33) I2=uk.decrypt I3=R4(4) O=R4_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_23_O I3=R4_LUT4_I3_22_O O=R4_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r4(49) I1=uk.K_r4(45) I2=uk.decrypt I3=R4(23) O=R4_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(51) I1=uk.K_r4(43) I2=uk.decrypt I3=R4(24) O=R4_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(36) I1=uk.K_r4(28) I2=uk.decrypt I3=R4(22) O=R4_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(14) I1=uk.K_r4(37) I2=uk.decrypt I3=R4(21) O=R4_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(30) I1=uk.K_r4(22) I2=uk.decrypt I3=R4(20) O=R4_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_28_O I3=R4_LUT4_I3_29_O O=R4_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_28_O I3=R4_LUT4_I3_29_O O=R4_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_28_O I3=R4_LUT4_I3_29_O O=R4_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r4(15) I1=uk.K_r4(7) I2=uk.decrypt I3=R4(25) O=R4_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_29_O I3=R4_LUT4_I3_28_O O=R4_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r4(8) I1=uk.K_r4(0) I2=uk.decrypt I3=R4(20) O=R4_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(4) I1=uk.K_r4(55) I2=uk.decrypt I3=R4(12) O=R4_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(12) I1=uk.K_r4(6) I2=uk.decrypt I3=R4(9) O=R4_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(46) I1=uk.K_r4(40) I2=uk.decrypt I3=R4(11) O=R4_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(20) I1=uk.K_r4(39) I2=uk.decrypt I3=R4(10) O=R4_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(17) I1=uk.K_r4(11) I2=uk.decrypt I3=R4(13) O=R4_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_34_O I3=R4_LUT4_I3_35_O O=R4_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_34_O I3=R4_LUT4_I3_35_O O=R4_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_34_O I3=R4_LUT4_I3_35_O O=R4_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r4(40) I1=uk.K_r4(34) I2=uk.decrypt I3=R4(8) O=R4_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_35_O I3=R4_LUT4_I3_34_O O=R4_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r4(47) I1=uk.K_r4(41) I2=uk.decrypt I3=R4(3) O=R4_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(25) I1=uk.K_r4(19) I2=uk.decrypt I3=R4(4) O=R4_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(13) I1=uk.K_r4(32) I2=uk.decrypt I3=R4(2) O=R4_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(55) I1=uk.K_r4(17) I2=uk.decrypt I3=R4(1) O=R4_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(21) I1=uk.K_r4(44) I2=uk.decrypt I3=R4(16) O=R4_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(53) I1=uk.K_r4(47) I2=uk.decrypt I3=R4(5) O=R4_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_40_O I3=R4_LUT4_I3_41_O O=R4_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_40_O I3=R4_LUT4_I3_41_O O=R4_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_40_O I3=R4_LUT4_I3_41_O O=R4_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r4(34) I1=uk.K_r4(53) I2=uk.decrypt I3=R4(32) O=R4_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_41_O I3=R4_LUT4_I3_40_O O=R4_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r4(22) I1=uk.K_r4(14) I2=uk.decrypt I3=R4(25) O=R4_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(16) I1=uk.K_r4(8) I2=uk.decrypt I3=R4(27) O=R4_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(31) I1=uk.K_r4(50) I2=uk.decrypt I3=R4(28) O=R4_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(7) I1=uk.K_r4(30) I2=uk.decrypt I3=R4(26) O=R4_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(50) I1=uk.K_r4(42) I2=uk.decrypt I3=R4(29) O=R4_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_46_O I3=R4_LUT4_I3_47_O O=R4_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_46_O I3=R4_LUT4_I3_47_O O=R4_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_46_O I3=R4_LUT4_I3_47_O O=R4_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r4(42) I1=uk.K_r4(38) I2=uk.decrypt I3=R4(24) O=R4_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_47_O I3=R4_LUT4_I3_46_O O=R4_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_4_O I3=R4_LUT4_I3_5_O O=R4_LUT4_I3_4_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_4_O I3=R4_LUT4_I3_5_O O=R4_LUT4_I3_4_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_4_O I3=R4_LUT4_I3_5_O O=R4_LUT4_I3_4_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r4(9) I1=uk.K_r4(1) I2=uk.decrypt I3=R4(21) O=R4_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_5_O I3=R4_LUT4_I3_4_O O=R4_LUT4_I3_5_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r4(32) I1=uk.K_r4(26) I2=uk.decrypt I3=R4(17) O=R4_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_6_O I3=R4_LUT4_I3_7_O O=R4_LUT4_I3_6_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_6_O I3=R4_LUT4_I3_7_O O=R4_LUT4_I3_6_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_6_O I3=R4_LUT4_I3_7_O O=R4_LUT4_I3_6_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r4(48) I1=uk.K_r4(10) I2=uk.decrypt I3=R4(12) O=R4_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R4_LUT4_I3_7_O I3=R4_LUT4_I3_6_O O=R4_LUT4_I3_7_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r4(10) I1=uk.K_r4(4) I2=uk.decrypt I3=R4(13) O=R4_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r4(11) I1=uk.K_r4(5) I2=uk.decrypt I3=R4(14) O=R4_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=R4(1) D=R4_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(2) D=R4_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(11) D=R4_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(12) D=R4_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(13) D=R4_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(14) D=R4_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(15) D=R4_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(16) D=R4_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(17) D=R4_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(18) D=R4_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(19) D=R4_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(20) D=R4_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(3) D=R4_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(21) D=R4_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(22) D=R4_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(23) D=R4_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(24) D=R4_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(25) D=R4_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(26) D=R4_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(27) D=R4_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(28) D=R4_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(29) D=R4_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(30) D=R4_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(4) D=R4_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(31) D=R4_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(32) D=R4_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(5) D=R4_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(6) D=R4_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(7) D=R4_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(8) D=R4_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(9) D=R4_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R4(10) D=R4_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:140.1-141.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r5(29) I1=uk.K_r5(49) I2=uk.decrypt I3=R5(17) O=R5_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(23) I1=uk.K_r5(43) I2=uk.decrypt I3=R5(18) O=R5_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(18) I1=uk.K_r5(40) I2=uk.decrypt I3=R5(17) O=R5_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_10_O I3=R5_LUT4_I3_11_O O=R5_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_10_O I3=R5_LUT4_I3_11_O O=R5_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_10_O I3=R5_LUT4_I3_11_O O=R5_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(34) I1=uk.K_r5(24) I2=uk.decrypt I3=R5(12) O=R5_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_11_O I3=R5_LUT4_I3_10_O O=R5_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(31) I1=uk.K_r5(23) I2=uk.decrypt I3=R5(31) O=R5_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(9) I1=uk.K_r5(29) I2=uk.decrypt I3=R5(32) O=R5_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(15) I1=uk.K_r5(35) I2=uk.decrypt I3=R5(30) O=R5_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(14) I1=uk.K_r5(38) I2=uk.decrypt I3=R5(29) O=R5_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(42) I1=uk.K_r5(7) I2=uk.decrypt I3=R5(28) O=R5_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_16_O I3=R5_LUT4_I3_17_O O=R5_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_16_O I3=R5_LUT4_I3_17_O O=R5_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_16_O I3=R5_LUT4_I3_17_O O=R5_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(30) I1=uk.K_r5(50) I2=uk.decrypt I3=R5(1) O=R5_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_17_O I3=R5_LUT4_I3_16_O O=R5_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(46) I1=uk.K_r5(11) I2=uk.decrypt I3=R5(7) O=R5_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(12) I1=uk.K_r5(34) I2=uk.decrypt I3=R5(8) O=R5_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(49) I1=uk.K_r5(14) I2=uk.decrypt I3=R5(20) O=R5_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(27) I1=uk.K_r5(17) I2=uk.decrypt I3=R5(6) O=R5_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(4) I1=uk.K_r5(26) I2=uk.decrypt I3=R5(5) O=R5_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(17) I1=uk.K_r5(39) I2=uk.decrypt I3=R5(9) O=R5_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_22_O I3=R5_LUT4_I3_23_O O=R5_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_22_O I3=R5_LUT4_I3_23_O O=R5_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_22_O I3=R5_LUT4_I3_23_O O=R5_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r5(25) I1=uk.K_r5(47) I2=uk.decrypt I3=R5(4) O=R5_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_23_O I3=R5_LUT4_I3_22_O O=R5_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(37) I1=uk.K_r5(2) I2=uk.decrypt I3=R5(24) O=R5_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(35) I1=uk.K_r5(0) I2=uk.decrypt I3=R5(23) O=R5_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(22) I1=uk.K_r5(42) I2=uk.decrypt I3=R5(22) O=R5_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(0) I1=uk.K_r5(51) I2=uk.decrypt I3=R5(21) O=R5_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(1) I1=uk.K_r5(21) I2=uk.decrypt I3=R5(25) O=R5_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_28_O I3=R5_LUT4_I3_29_O O=R5_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_28_O I3=R5_LUT4_I3_29_O O=R5_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_28_O I3=R5_LUT4_I3_29_O O=R5_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(16) I1=uk.K_r5(36) I2=uk.decrypt I3=R5(20) O=R5_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_29_O I3=R5_LUT4_I3_28_O O=R5_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(38) I1=uk.K_r5(30) I2=uk.decrypt I3=R5(19) O=R5_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(47) I1=uk.K_r5(12) I2=uk.decrypt I3=R5(12) O=R5_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(55) I1=uk.K_r5(20) I2=uk.decrypt I3=R5(9) O=R5_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(6) I1=uk.K_r5(53) I2=uk.decrypt I3=R5(10) O=R5_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(32) I1=uk.K_r5(54) I2=uk.decrypt I3=R5(11) O=R5_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(26) I1=uk.K_r5(48) I2=uk.decrypt I3=R5(8) O=R5_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_34_O I3=R5_LUT4_I3_35_O O=R5_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_34_O I3=R5_LUT4_I3_35_O O=R5_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_34_O I3=R5_LUT4_I3_35_O O=R5_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r5(3) I1=uk.K_r5(25) I2=uk.decrypt I3=R5(13) O=R5_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_35_O I3=R5_LUT4_I3_34_O O=R5_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(33) I1=uk.K_r5(55) I2=uk.decrypt I3=R5(3) O=R5_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(11) I1=uk.K_r5(33) I2=uk.decrypt I3=R5(4) O=R5_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(24) I1=uk.K_r5(46) I2=uk.decrypt I3=R5(2) O=R5_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(41) I1=uk.K_r5(6) I2=uk.decrypt I3=R5(1) O=R5_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(50) I1=uk.K_r5(15) I2=uk.decrypt I3=R5(21) O=R5_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(20) I1=uk.K_r5(10) I2=uk.decrypt I3=R5(32) O=R5_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_40_O I3=R5_LUT4_I3_41_O O=R5_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_40_O I3=R5_LUT4_I3_41_O O=R5_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_40_O I3=R5_LUT4_I3_41_O O=R5_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(39) I1=uk.K_r5(4) I2=uk.decrypt I3=R5(5) O=R5_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_41_O I3=R5_LUT4_I3_40_O O=R5_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(28) I1=uk.K_r5(52) I2=uk.decrypt I3=R5(24) O=R5_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_42_O I3=R5_LUT4_I3_43_O O=R5_LUT4_I3_42_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_42_O I3=R5_LUT4_I3_43_O O=R5_LUT4_I3_42_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_42_O I3=R5_LUT4_I3_43_O O=R5_LUT4_I3_42_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(36) I1=uk.K_r5(1) I2=uk.decrypt I3=R5(29) O=R5_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_43_O I3=R5_LUT4_I3_42_O O=R5_LUT4_I3_43_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(2) I1=uk.K_r5(22) I2=uk.decrypt I3=R5(27) O=R5_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(52) I1=uk.K_r5(44) I2=uk.decrypt I3=R5(26) O=R5_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(8) I1=uk.K_r5(28) I2=uk.decrypt I3=R5(25) O=R5_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(44) I1=uk.K_r5(9) I2=uk.decrypt I3=R5(28) O=R5_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_4_O I3=R5_LUT4_I3_5_O O=R5_LUT4_I3_4_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_4_O I3=R5_LUT4_I3_5_O O=R5_LUT4_I3_4_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_4_O I3=R5_LUT4_I3_5_O O=R5_LUT4_I3_4_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(7) I1=uk.K_r5(31) I2=uk.decrypt I3=R5(16) O=R5_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R5_LUT4_I3_5_O I3=R5_LUT4_I3_4_O O=R5_LUT4_I3_5_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r5(53) I1=uk.K_r5(18) I2=uk.decrypt I3=R5(13) O=R5_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(54) I1=uk.K_r5(19) I2=uk.decrypt I3=R5(14) O=R5_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(13) I1=uk.K_r5(3) I2=uk.decrypt I3=R5(16) O=R5_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r5(5) I1=uk.K_r5(27) I2=uk.decrypt I3=R5(15) O=R5_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=R5(1) D=R5_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(2) D=R5_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(11) D=R5_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(12) D=R5_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(13) D=R5_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(14) D=R5_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(15) D=R5_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(16) D=R5_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(17) D=R5_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(18) D=R5_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(19) D=R5_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(20) D=R5_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(3) D=R5_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(21) D=R5_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(22) D=R5_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(23) D=R5_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(24) D=R5_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(25) D=R5_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(26) D=R5_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(27) D=R5_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(28) D=R5_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(29) D=R5_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(30) D=R5_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(4) D=R5_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(31) D=R5_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(32) D=R5_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(5) D=R5_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(6) D=R5_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(7) D=R5_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(8) D=R5_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(9) D=R5_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R5(10) D=R5_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:146.1-147.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r6(36) I1=uk.K_r6(29) I2=uk.decrypt I3=R6(21) O=R6_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(52) I1=uk.K_r6(45) I2=uk.decrypt I3=R6(16) O=R6_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(4) I1=uk.K_r6(54) I2=uk.decrypt I3=R6(17) O=R6_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_10_O I3=R6_LUT4_I3_11_O O=R6_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_10_O I3=R6_LUT4_I3_11_O O=R6_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_10_O I3=R6_LUT4_I3_11_O O=R6_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r6(20) I1=uk.K_r6(13) I2=uk.decrypt I3=R6(12) O=R6_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_11_O I3=R6_LUT4_I3_10_O O=R6_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r6(50) I1=uk.K_r6(43) I2=uk.decrypt I3=R6(32) O=R6_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(44) I1=uk.K_r6(37) I2=uk.decrypt I3=R6(31) O=R6_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(1) I1=uk.K_r6(49) I2=uk.decrypt I3=R6(30) O=R6_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(0) I1=uk.K_r6(52) I2=uk.decrypt I3=R6(29) O=R6_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(28) I1=uk.K_r6(21) I2=uk.decrypt I3=R6(28) O=R6_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_16_O I3=R6_LUT4_I3_17_O O=R6_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_16_O I3=R6_LUT4_I3_17_O O=R6_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_16_O I3=R6_LUT4_I3_17_O O=R6_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r6(16) I1=uk.K_r6(9) I2=uk.decrypt I3=R6(1) O=R6_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_17_O I3=R6_LUT4_I3_16_O O=R6_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r6(32) I1=uk.K_r6(25) I2=uk.decrypt I3=R6(7) O=R6_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(55) I1=uk.K_r6(48) I2=uk.decrypt I3=R6(8) O=R6_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(15) I1=uk.K_r6(8) I2=uk.decrypt I3=R6(17) O=R6_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(13) I1=uk.K_r6(6) I2=uk.decrypt I3=R6(6) O=R6_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(47) I1=uk.K_r6(40) I2=uk.decrypt I3=R6(5) O=R6_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(3) I1=uk.K_r6(53) I2=uk.decrypt I3=R6(9) O=R6_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_22_O I3=R6_LUT4_I3_23_O O=R6_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_22_O I3=R6_LUT4_I3_23_O O=R6_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_22_O I3=R6_LUT4_I3_23_O O=R6_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r6(11) I1=uk.K_r6(4) I2=uk.decrypt I3=R6(4) O=R6_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_23_O I3=R6_LUT4_I3_22_O O=R6_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r6(45) I1=uk.K_r6(38) I2=uk.decrypt I3=R6(21) O=R6_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(8) I1=uk.K_r6(1) I2=uk.decrypt I3=R6(22) O=R6_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(23) I1=uk.K_r6(16) I2=uk.decrypt I3=R6(24) O=R6_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(21) I1=uk.K_r6(14) I2=uk.decrypt I3=R6(23) O=R6_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(42) I1=uk.K_r6(35) I2=uk.decrypt I3=R6(25) O=R6_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_28_O I3=R6_LUT4_I3_29_O O=R6_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_28_O I3=R6_LUT4_I3_29_O O=R6_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_28_O I3=R6_LUT4_I3_29_O O=R6_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r6(2) I1=uk.K_r6(50) I2=uk.decrypt I3=R6(20) O=R6_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_29_O I3=R6_LUT4_I3_28_O O=R6_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r6(9) I1=uk.K_r6(2) I2=uk.decrypt I3=R6(18) O=R6_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(41) I1=uk.K_r6(34) I2=uk.decrypt I3=R6(9) O=R6_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(33) I1=uk.K_r6(26) I2=uk.decrypt I3=R6(12) O=R6_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(18) I1=uk.K_r6(11) I2=uk.decrypt I3=R6(11) O=R6_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(17) I1=uk.K_r6(10) I2=uk.decrypt I3=R6(10) O=R6_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(46) I1=uk.K_r6(39) I2=uk.decrypt I3=R6(13) O=R6_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_34_O I3=R6_LUT4_I3_35_O O=R6_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_34_O I3=R6_LUT4_I3_35_O O=R6_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_34_O I3=R6_LUT4_I3_35_O O=R6_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r6(12) I1=uk.K_r6(5) I2=uk.decrypt I3=R6(8) O=R6_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_35_O I3=R6_LUT4_I3_34_O O=R6_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r6(54) I1=uk.K_r6(47) I2=uk.decrypt I3=R6(4) O=R6_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(19) I1=uk.K_r6(12) I2=uk.decrypt I3=R6(3) O=R6_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(10) I1=uk.K_r6(3) I2=uk.decrypt I3=R6(2) O=R6_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(27) I1=uk.K_r6(20) I2=uk.decrypt I3=R6(1) O=R6_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(35) I1=uk.K_r6(28) I2=uk.decrypt I3=R6(20) O=R6_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(25) I1=uk.K_r6(18) I2=uk.decrypt I3=R6(5) O=R6_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_40_O I3=R6_LUT4_I3_41_O O=R6_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_40_O I3=R6_LUT4_I3_41_O O=R6_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_40_O I3=R6_LUT4_I3_41_O O=R6_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r6(6) I1=uk.K_r6(24) I2=uk.decrypt I3=R6(32) O=R6_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_41_O I3=R6_LUT4_I3_40_O O=R6_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r6(30) I1=uk.K_r6(23) I2=uk.decrypt I3=R6(28) O=R6_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(43) I1=uk.K_r6(36) I2=uk.decrypt I3=R6(27) O=R6_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(49) I1=uk.K_r6(42) I2=uk.decrypt I3=R6(25) O=R6_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(38) I1=uk.K_r6(31) I2=uk.decrypt I3=R6(26) O=R6_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(14) I1=uk.K_r6(7) I2=uk.decrypt I3=R6(24) O=R6_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_46_O I3=R6_LUT4_I3_47_O O=R6_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_46_O I3=R6_LUT4_I3_47_O O=R6_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_46_O I3=R6_LUT4_I3_47_O O=R6_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r6(22) I1=uk.K_r6(15) I2=uk.decrypt I3=R6(29) O=R6_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_47_O I3=R6_LUT4_I3_46_O O=R6_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r6(51) I1=uk.K_r6(44) I2=uk.decrypt I3=R6(19) O=R6_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(40) I1=uk.K_r6(33) I2=uk.decrypt I3=R6(14) O=R6_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(39) I1=uk.K_r6(32) I2=uk.decrypt I3=R6(13) O=R6_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(24) I1=uk.K_r6(17) I2=uk.decrypt I3=R6(16) O=R6_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r6(48) I1=uk.K_r6(41) I2=uk.decrypt I3=R6(15) O=R6_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_O I3=R6_LUT4_I3_1_O O=R6_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_O I3=R6_LUT4_I3_1_O O=R6_LUT4_I3_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_O I3=R6_LUT4_I3_1_O O=R6_LUT4_I3_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R6_LUT4_I3_1_O I3=R6_LUT4_I3_O O=R6_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=R6(1) D=R6_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(2) D=R6_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(11) D=R6_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(12) D=R6_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(13) D=R6_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(14) D=R6_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(15) D=R6_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(16) D=R6_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(17) D=R6_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(18) D=R6_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(19) D=R6_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(20) D=R6_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(3) D=R6_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(21) D=R6_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(22) D=R6_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(23) D=R6_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(24) D=R6_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(25) D=R6_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(26) D=R6_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(27) D=R6_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(28) D=R6_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(29) D=R6_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(30) D=R6_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(4) D=R6_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(31) D=R6_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(32) D=R6_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(5) D=R6_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(6) D=R6_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(7) D=R6_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(8) D=R6_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(9) D=R6_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R6(10) D=R6_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:152.1-153.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r7(8) I1=uk.K_r7(15) I2=uk.decrypt I3=R7(17) O=R7_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(2) I1=uk.K_r7(9) I2=uk.decrypt I3=R7(18) O=R7_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(13) I1=uk.K_r7(20) I2=uk.decrypt I3=R7(12) O=R7_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_10_O I3=R7_LUT4_I3_11_O O=R7_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_10_O I3=R7_LUT4_I3_11_O O=R7_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_10_O I3=R7_LUT4_I3_11_O O=R7_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r7(54) I1=uk.K_r7(4) I2=uk.decrypt I3=R7(17) O=R7_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_11_O I3=R7_LUT4_I3_10_O O=R7_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(49) I1=uk.K_r7(1) I2=uk.decrypt I3=R7(30) O=R7_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(52) I1=uk.K_r7(0) I2=uk.decrypt I3=R7(29) O=R7_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(37) I1=uk.K_r7(44) I2=uk.decrypt I3=R7(31) O=R7_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(43) I1=uk.K_r7(50) I2=uk.decrypt I3=R7(32) O=R7_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(21) I1=uk.K_r7(28) I2=uk.decrypt I3=R7(28) O=R7_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_16_O I3=R7_LUT4_I3_17_O O=R7_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_16_O I3=R7_LUT4_I3_17_O O=R7_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_16_O I3=R7_LUT4_I3_17_O O=R7_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(9) I1=uk.K_r7(16) I2=uk.decrypt I3=R7(1) O=R7_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_17_O I3=R7_LUT4_I3_16_O O=R7_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(25) I1=uk.K_r7(32) I2=uk.decrypt I3=R7(7) O=R7_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(48) I1=uk.K_r7(55) I2=uk.decrypt I3=R7(8) O=R7_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(28) I1=uk.K_r7(35) I2=uk.decrypt I3=R7(20) O=R7_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(6) I1=uk.K_r7(13) I2=uk.decrypt I3=R7(6) O=R7_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(40) I1=uk.K_r7(47) I2=uk.decrypt I3=R7(5) O=R7_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(53) I1=uk.K_r7(3) I2=uk.decrypt I3=R7(9) O=R7_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_22_O I3=R7_LUT4_I3_23_O O=R7_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_22_O I3=R7_LUT4_I3_23_O O=R7_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_22_O I3=R7_LUT4_I3_23_O O=R7_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r7(4) I1=uk.K_r7(11) I2=uk.decrypt I3=R7(4) O=R7_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_23_O I3=R7_LUT4_I3_22_O O=R7_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(38) I1=uk.K_r7(45) I2=uk.decrypt I3=R7(21) O=R7_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(1) I1=uk.K_r7(8) I2=uk.decrypt I3=R7(22) O=R7_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(16) I1=uk.K_r7(23) I2=uk.decrypt I3=R7(24) O=R7_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(14) I1=uk.K_r7(21) I2=uk.decrypt I3=R7(23) O=R7_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(35) I1=uk.K_r7(42) I2=uk.decrypt I3=R7(25) O=R7_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_28_O I3=R7_LUT4_I3_29_O O=R7_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_28_O I3=R7_LUT4_I3_29_O O=R7_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_28_O I3=R7_LUT4_I3_29_O O=R7_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(50) I1=uk.K_r7(2) I2=uk.decrypt I3=R7(20) O=R7_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_29_O I3=R7_LUT4_I3_28_O O=R7_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(44) I1=uk.K_r7(51) I2=uk.decrypt I3=R7(19) O=R7_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(11) I1=uk.K_r7(18) I2=uk.decrypt I3=R7(11) O=R7_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(26) I1=uk.K_r7(33) I2=uk.decrypt I3=R7(12) O=R7_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(10) I1=uk.K_r7(17) I2=uk.decrypt I3=R7(10) O=R7_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(34) I1=uk.K_r7(41) I2=uk.decrypt I3=R7(9) O=R7_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(5) I1=uk.K_r7(12) I2=uk.decrypt I3=R7(8) O=R7_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_34_O I3=R7_LUT4_I3_35_O O=R7_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_34_O I3=R7_LUT4_I3_35_O O=R7_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_34_O I3=R7_LUT4_I3_35_O O=R7_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(39) I1=uk.K_r7(46) I2=uk.decrypt I3=R7(13) O=R7_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_35_O I3=R7_LUT4_I3_34_O O=R7_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(47) I1=uk.K_r7(54) I2=uk.decrypt I3=R7(4) O=R7_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(12) I1=uk.K_r7(19) I2=uk.decrypt I3=R7(3) O=R7_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(3) I1=uk.K_r7(10) I2=uk.decrypt I3=R7(2) O=R7_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(20) I1=uk.K_r7(27) I2=uk.decrypt I3=R7(1) O=R7_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(45) I1=uk.K_r7(52) I2=uk.decrypt I3=R7(16) O=R7_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(18) I1=uk.K_r7(25) I2=uk.decrypt I3=R7(5) O=R7_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_40_O I3=R7_LUT4_I3_41_O O=R7_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_40_O I3=R7_LUT4_I3_41_O O=R7_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_40_O I3=R7_LUT4_I3_41_O O=R7_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(24) I1=uk.K_r7(6) I2=uk.decrypt I3=R7(32) O=R7_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_41_O I3=R7_LUT4_I3_40_O O=R7_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(23) I1=uk.K_r7(30) I2=uk.decrypt I3=R7(28) O=R7_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(36) I1=uk.K_r7(43) I2=uk.decrypt I3=R7(27) O=R7_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(42) I1=uk.K_r7(49) I2=uk.decrypt I3=R7(25) O=R7_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(31) I1=uk.K_r7(38) I2=uk.decrypt I3=R7(26) O=R7_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(7) I1=uk.K_r7(14) I2=uk.decrypt I3=R7(24) O=R7_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_46_O I3=R7_LUT4_I3_47_O O=R7_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_46_O I3=R7_LUT4_I3_47_O O=R7_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_46_O I3=R7_LUT4_I3_47_O O=R7_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r7(15) I1=uk.K_r7(22) I2=uk.decrypt I3=R7(29) O=R7_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_47_O I3=R7_LUT4_I3_46_O O=R7_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_4_O I3=R7_LUT4_I3_5_O O=R7_LUT4_I3_4_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_4_O I3=R7_LUT4_I3_5_O O=R7_LUT4_I3_4_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_4_O I3=R7_LUT4_I3_5_O O=R7_LUT4_I3_4_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r7(29) I1=uk.K_r7(36) I2=uk.decrypt I3=R7(21) O=R7_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R7_LUT4_I3_5_O I3=R7_LUT4_I3_4_O O=R7_LUT4_I3_5_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r7(32) I1=uk.K_r7(39) I2=uk.decrypt I3=R7(13) O=R7_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(33) I1=uk.K_r7(40) I2=uk.decrypt I3=R7(14) O=R7_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(17) I1=uk.K_r7(24) I2=uk.decrypt I3=R7(16) O=R7_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r7(41) I1=uk.K_r7(48) I2=uk.decrypt I3=R7(15) O=R7_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=R7(1) D=R7_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(2) D=R7_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(11) D=R7_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(12) D=R7_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(13) D=R7_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(14) D=R7_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(15) D=R7_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(16) D=R7_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(17) D=R7_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(18) D=R7_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(19) D=R7_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(20) D=R7_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(3) D=R7_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(21) D=R7_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(22) D=R7_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(23) D=R7_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(24) D=R7_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(25) D=R7_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(26) D=R7_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(27) D=R7_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(28) D=R7_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(29) D=R7_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(30) D=R7_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(4) D=R7_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(31) D=R7_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(32) D=R7_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(5) D=R7_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(6) D=R7_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(7) D=R7_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(8) D=R7_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(9) D=R7_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R7(10) D=R7_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:158.1-159.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r8(43) I1=uk.K_r8(23) I2=uk.decrypt I3=R8(18) O=R8_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(49) I1=uk.K_r8(29) I2=uk.decrypt I3=R8(17) O=R8_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(40) I1=uk.K_r8(18) I2=uk.decrypt I3=R8(17) O=R8_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_10_O I3=R8_LUT4_I3_11_O O=R8_LUT4_I3_10_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_10_O I3=R8_LUT4_I3_11_O O=R8_LUT4_I3_10_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_10_O I3=R8_LUT4_I3_11_O O=R8_LUT4_I3_10_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(24) I1=uk.K_r8(34) I2=uk.decrypt I3=R8(12) O=R8_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_11_O I3=R8_LUT4_I3_10_O O=R8_LUT4_I3_11_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(29) I1=uk.K_r8(9) I2=uk.decrypt I3=R8(32) O=R8_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(23) I1=uk.K_r8(31) I2=uk.decrypt I3=R8(31) O=R8_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(35) I1=uk.K_r8(15) I2=uk.decrypt I3=R8(30) O=R8_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(38) I1=uk.K_r8(14) I2=uk.decrypt I3=R8(29) O=R8_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(7) I1=uk.K_r8(42) I2=uk.decrypt I3=R8(28) O=R8_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_16_O I3=R8_LUT4_I3_17_O O=R8_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_16_O I3=R8_LUT4_I3_17_O O=R8_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_16_O I3=R8_LUT4_I3_17_O O=R8_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(50) I1=uk.K_r8(30) I2=uk.decrypt I3=R8(1) O=R8_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_17_O I3=R8_LUT4_I3_16_O O=R8_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(34) I1=uk.K_r8(12) I2=uk.decrypt I3=R8(8) O=R8_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(11) I1=uk.K_r8(46) I2=uk.decrypt I3=R8(7) O=R8_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(14) I1=uk.K_r8(49) I2=uk.decrypt I3=R8(20) O=R8_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(17) I1=uk.K_r8(27) I2=uk.decrypt I3=R8(6) O=R8_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(26) I1=uk.K_r8(4) I2=uk.decrypt I3=R8(5) O=R8_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(39) I1=uk.K_r8(17) I2=uk.decrypt I3=R8(9) O=R8_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_22_O I3=R8_LUT4_I3_23_O O=R8_LUT4_I3_22_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_22_O I3=R8_LUT4_I3_23_O O=R8_LUT4_I3_22_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_22_O I3=R8_LUT4_I3_23_O O=R8_LUT4_I3_22_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r8(47) I1=uk.K_r8(25) I2=uk.decrypt I3=R8(4) O=R8_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_23_O I3=R8_LUT4_I3_22_O O=R8_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(0) I1=uk.K_r8(35) I2=uk.decrypt I3=R8(23) O=R8_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(2) I1=uk.K_r8(37) I2=uk.decrypt I3=R8(24) O=R8_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(42) I1=uk.K_r8(22) I2=uk.decrypt I3=R8(22) O=R8_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(51) I1=uk.K_r8(0) I2=uk.decrypt I3=R8(21) O=R8_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(36) I1=uk.K_r8(16) I2=uk.decrypt I3=R8(20) O=R8_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_28_O I3=R8_LUT4_I3_29_O O=R8_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_28_O I3=R8_LUT4_I3_29_O O=R8_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_28_O I3=R8_LUT4_I3_29_O O=R8_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r8(21) I1=uk.K_r8(1) I2=uk.decrypt I3=R8(25) O=R8_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_29_O I3=R8_LUT4_I3_28_O O=R8_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(30) I1=uk.K_r8(38) I2=uk.decrypt I3=R8(19) O=R8_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(54) I1=uk.K_r8(32) I2=uk.decrypt I3=R8(11) O=R8_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(12) I1=uk.K_r8(47) I2=uk.decrypt I3=R8(12) O=R8_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(53) I1=uk.K_r8(6) I2=uk.decrypt I3=R8(10) O=R8_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(20) I1=uk.K_r8(55) I2=uk.decrypt I3=R8(9) O=R8_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(25) I1=uk.K_r8(3) I2=uk.decrypt I3=R8(13) O=R8_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_34_O I3=R8_LUT4_I3_35_O O=R8_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_34_O I3=R8_LUT4_I3_35_O O=R8_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_34_O I3=R8_LUT4_I3_35_O O=R8_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(48) I1=uk.K_r8(26) I2=uk.decrypt I3=R8(8) O=R8_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_35_O I3=R8_LUT4_I3_34_O O=R8_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(55) I1=uk.K_r8(33) I2=uk.decrypt I3=R8(3) O=R8_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(33) I1=uk.K_r8(11) I2=uk.decrypt I3=R8(4) O=R8_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(46) I1=uk.K_r8(24) I2=uk.decrypt I3=R8(2) O=R8_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(6) I1=uk.K_r8(41) I2=uk.decrypt I3=R8(1) O=R8_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(31) I1=uk.K_r8(7) I2=uk.decrypt I3=R8(16) O=R8_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(10) I1=uk.K_r8(20) I2=uk.decrypt I3=R8(32) O=R8_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_40_O I3=R8_LUT4_I3_41_O O=R8_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_40_O I3=R8_LUT4_I3_41_O O=R8_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_40_O I3=R8_LUT4_I3_41_O O=R8_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(4) I1=uk.K_r8(39) I2=uk.decrypt I3=R8(5) O=R8_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_41_O I3=R8_LUT4_I3_40_O O=R8_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(9) I1=uk.K_r8(44) I2=uk.decrypt I3=R8(28) O=R8_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(22) I1=uk.K_r8(2) I2=uk.decrypt I3=R8(27) O=R8_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(44) I1=uk.K_r8(52) I2=uk.decrypt I3=R8(26) O=R8_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(28) I1=uk.K_r8(8) I2=uk.decrypt I3=R8(25) O=R8_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(1) I1=uk.K_r8(36) I2=uk.decrypt I3=R8(29) O=R8_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_46_O I3=R8_LUT4_I3_47_O O=R8_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_46_O I3=R8_LUT4_I3_47_O O=R8_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_46_O I3=R8_LUT4_I3_47_O O=R8_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r8(52) I1=uk.K_r8(28) I2=uk.decrypt I3=R8(24) O=R8_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_47_O I3=R8_LUT4_I3_46_O O=R8_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_4_O I3=R8_LUT4_I3_5_O O=R8_LUT4_I3_4_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_4_O I3=R8_LUT4_I3_5_O O=R8_LUT4_I3_4_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_4_O I3=R8_LUT4_I3_5_O O=R8_LUT4_I3_4_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r8(15) I1=uk.K_r8(50) I2=uk.decrypt I3=R8(21) O=R8_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R8_LUT4_I3_5_O I3=R8_LUT4_I3_4_O O=R8_LUT4_I3_5_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r8(19) I1=uk.K_r8(54) I2=uk.decrypt I3=R8(14) O=R8_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(18) I1=uk.K_r8(53) I2=uk.decrypt I3=R8(13) O=R8_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(3) I1=uk.K_r8(13) I2=uk.decrypt I3=R8(16) O=R8_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r8(27) I1=uk.K_r8(5) I2=uk.decrypt I3=R8(15) O=R8_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=R8(1) D=R8_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(2) D=R8_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(11) D=R8_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(12) D=R8_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(13) D=R8_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(14) D=R8_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(15) D=R8_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(16) D=R8_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(17) D=R8_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(18) D=R8_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(19) D=R8_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(20) D=R8_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(3) D=R8_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(21) D=R8_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(22) D=R8_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(23) D=R8_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(24) D=R8_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(25) D=R8_ff_CQZ_D(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(26) D=R8_ff_CQZ_D(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(27) D=R8_ff_CQZ_D(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(28) D=R8_ff_CQZ_D(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(29) D=R8_ff_CQZ_D(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(30) D=R8_ff_CQZ_D(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(4) D=R8_ff_CQZ_D(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(31) D=R8_ff_CQZ_D(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(32) D=R8_ff_CQZ_D(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(5) D=R8_ff_CQZ_D(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(6) D=R8_ff_CQZ_D(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(7) D=R8_ff_CQZ_D(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(8) D=R8_ff_CQZ_D(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(9) D=R8_ff_CQZ_D(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R8(10) D=R8_ff_CQZ_D(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:164.1-165.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=uk.K_r9(35) I1=uk.K_r9(43) I2=uk.decrypt I3=R9(17) O=R9_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(29) I1=uk.K_r9(37) I2=uk.decrypt I3=R9(18) O=R9_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(46) I1=uk.K_r9(27) I2=uk.decrypt I3=R9(16) O=R9_LUT4_I3_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(13) I1=uk.K_r9(19) I2=uk.decrypt I3=R9(15) O=R9_LUT4_I3_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(15) I1=uk.K_r9(23) I2=uk.decrypt I3=R9(32) O=R9_LUT4_I3_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(9) I1=uk.K_r9(45) I2=uk.decrypt I3=R9(31) O=R9_LUT4_I3_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(21) I1=uk.K_r9(29) I2=uk.decrypt I3=R9(30) O=R9_LUT4_I3_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(51) I1=uk.K_r9(28) I2=uk.decrypt I3=R9(29) O=R9_LUT4_I3_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(52) I1=uk.K_r9(1) I2=uk.decrypt I3=R9(28) O=R9_LUT4_I3_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_16_O I3=R9_LUT4_I3_17_O O=R9_LUT4_I3_16_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_16_O I3=R9_LUT4_I3_17_O O=R9_LUT4_I3_16_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_16_O I3=R9_LUT4_I3_17_O O=R9_LUT4_I3_16_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(36) I1=uk.K_r9(44) I2=uk.decrypt I3=R9(1) O=R9_LUT4_I3_17_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_17_O I3=R9_LUT4_I3_16_O O=R9_LUT4_I3_17_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(12) I1=uk.K_r9(18) I2=uk.decrypt I3=R9(5) O=R9_LUT4_I3_18_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(3) I1=uk.K_r9(41) I2=uk.decrypt I3=R9(6) O=R9_LUT4_I3_19_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(0) I1=uk.K_r9(8) I2=uk.decrypt I3=R9(20) O=R9_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(54) I1=uk.K_r9(3) I2=uk.decrypt I3=R9(7) O=R9_LUT4_I3_20_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(20) I1=uk.K_r9(26) I2=uk.decrypt I3=R9(8) O=R9_LUT4_I3_21_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(33) I1=uk.K_r9(39) I2=uk.decrypt I3=R9(4) O=R9_LUT4_I3_22_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(25) I1=uk.K_r9(6) I2=uk.decrypt I3=R9(9) O=R9_LUT4_I3_23_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_23_O I3=R9_LUT4_I3_22_O O=R9_LUT4_I3_23_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_22_O I3=R9_LUT4_I3_23_O O=R9_LUT4_I3_23_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_22_O I3=R9_LUT4_I3_23_O O=R9_LUT4_I3_23_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_22_O I3=R9_LUT4_I3_23_O O=R9_LUT4_I3_23_O_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r9(28) I1=uk.K_r9(36) I2=uk.decrypt I3=R9(22) O=R9_LUT4_I3_24_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(37) I1=uk.K_r9(14) I2=uk.decrypt I3=R9(21) O=R9_LUT4_I3_25_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(43) I1=uk.K_r9(51) I2=uk.decrypt I3=R9(24) O=R9_LUT4_I3_26_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(45) I1=uk.K_r9(49) I2=uk.decrypt I3=R9(23) O=R9_LUT4_I3_27_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(7) I1=uk.K_r9(15) I2=uk.decrypt I3=R9(25) O=R9_LUT4_I3_28_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_28_O I3=R9_LUT4_I3_29_O O=R9_LUT4_I3_28_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_28_O I3=R9_LUT4_I3_29_O O=R9_LUT4_I3_28_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_28_O I3=R9_LUT4_I3_29_O O=R9_LUT4_I3_28_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(22) I1=uk.K_r9(30) I2=uk.decrypt I3=R9(20) O=R9_LUT4_I3_29_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_29_O I3=R9_LUT4_I3_28_O O=R9_LUT4_I3_29_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(16) I1=uk.K_r9(52) I2=uk.decrypt I3=R9(19) O=R9_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(40) I1=uk.K_r9(46) I2=uk.decrypt I3=R9(11) O=R9_LUT4_I3_30_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(55) I1=uk.K_r9(4) I2=uk.decrypt I3=R9(12) O=R9_LUT4_I3_31_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(39) I1=uk.K_r9(20) I2=uk.decrypt I3=R9(10) O=R9_LUT4_I3_32_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(6) I1=uk.K_r9(12) I2=uk.decrypt I3=R9(9) O=R9_LUT4_I3_33_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(11) I1=uk.K_r9(17) I2=uk.decrypt I3=R9(13) O=R9_LUT4_I3_34_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_34_O I3=R9_LUT4_I3_35_O O=R9_LUT4_I3_34_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_34_O I3=R9_LUT4_I3_35_O O=R9_LUT4_I3_34_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_34_O I3=R9_LUT4_I3_35_O O=R9_LUT4_I3_34_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk.K_r9(34) I1=uk.K_r9(40) I2=uk.decrypt I3=R9(8) O=R9_LUT4_I3_35_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_35_O I3=R9_LUT4_I3_34_O O=R9_LUT4_I3_35_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(19) I1=uk.K_r9(25) I2=uk.decrypt I3=R9(4) O=R9_LUT4_I3_36_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(17) I1=uk.K_r9(55) I2=uk.decrypt I3=R9(1) O=R9_LUT4_I3_37_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(32) I1=uk.K_r9(13) I2=uk.decrypt I3=R9(2) O=R9_LUT4_I3_38_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(41) I1=uk.K_r9(47) I2=uk.decrypt I3=R9(3) O=R9_LUT4_I3_39_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(1) I1=uk.K_r9(9) I2=uk.decrypt I3=R9(21) O=R9_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(53) I1=uk.K_r9(34) I2=uk.decrypt I3=R9(32) O=R9_LUT4_I3_40_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_40_O I3=R9_LUT4_I3_41_O O=R9_LUT4_I3_40_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_40_O I3=R9_LUT4_I3_41_O O=R9_LUT4_I3_40_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_40_O I3=R9_LUT4_I3_41_O O=R9_LUT4_I3_40_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r9(47) I1=uk.K_r9(53) I2=uk.decrypt I3=R9(5) O=R9_LUT4_I3_41_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_41_O I3=R9_LUT4_I3_40_O O=R9_LUT4_I3_41_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(8) I1=uk.K_r9(16) I2=uk.decrypt I3=R9(27) O=R9_LUT4_I3_42_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(14) I1=uk.K_r9(22) I2=uk.decrypt I3=R9(25) O=R9_LUT4_I3_43_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(50) I1=uk.K_r9(31) I2=uk.decrypt I3=R9(28) O=R9_LUT4_I3_44_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(30) I1=uk.K_r9(7) I2=uk.decrypt I3=R9(26) O=R9_LUT4_I3_45_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(42) I1=uk.K_r9(50) I2=uk.decrypt I3=R9(29) O=R9_LUT4_I3_46_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_46_O I3=R9_LUT4_I3_47_O O=R9_LUT4_I3_46_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_46_O I3=R9_LUT4_I3_47_O O=R9_LUT4_I3_46_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_46_O I3=R9_LUT4_I3_47_O O=R9_LUT4_I3_46_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(38) I1=uk.K_r9(42) I2=uk.decrypt I3=R9(24) O=R9_LUT4_I3_47_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_47_O I3=R9_LUT4_I3_46_O O=R9_LUT4_I3_47_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_4_O I3=R9_LUT4_I3_5_O O=R9_LUT4_I3_4_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_4_O I3=R9_LUT4_I3_5_O O=R9_LUT4_I3_4_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_4_O I3=R9_LUT4_I3_5_O O=R9_LUT4_I3_4_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(44) I1=uk.K_r9(21) I2=uk.decrypt I3=R9(16) O=R9_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_5_O I3=R9_LUT4_I3_4_O O=R9_LUT4_I3_5_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(10) I1=uk.K_r9(48) I2=uk.decrypt I3=R9(12) O=R9_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_6_O I3=R9_LUT4_I3_7_O O=R9_LUT4_I3_6_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_6_O I3=R9_LUT4_I3_7_O O=R9_LUT4_I3_6_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_6_O I3=R9_LUT4_I3_7_O O=R9_LUT4_I3_6_O_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=uk.K_r9(26) I1=uk.K_r9(32) I2=uk.decrypt I3=R9(17) O=R9_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=K1(1) I1=K1(1) I2=R9_LUT4_I3_7_O I3=R9_LUT4_I3_6_O O=R9_LUT4_I3_7_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=uk.K_r9(4) I1=uk.K_r9(10) I2=uk.decrypt I3=R9(13) O=R9_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=uk.K_r9(5) I1=uk.K_r9(11) I2=uk.decrypt I3=R9(14) O=R9_LUT4_I3_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=R9(1) D=R9_ff_CQZ_D(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(2) D=R9_ff_CQZ_D(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(11) D=R9_ff_CQZ_D(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(12) D=R9_ff_CQZ_D(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(13) D=R9_ff_CQZ_D(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(14) D=R9_ff_CQZ_D(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(15) D=R9_ff_CQZ_D(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(16) D=R9_ff_CQZ_D(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(17) D=R9_ff_CQZ_D(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(18) D=R9_ff_CQZ_D(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(19) D=R9_ff_CQZ_D(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(20) D=R9_ff_CQZ_D(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(3) D=R9_ff_CQZ_D(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(21) D=R9_ff_CQZ_D(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(22) D=R9_ff_CQZ_D(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(23) D=R9_ff_CQZ_D(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:170.1-171.26|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=R9(24) D=R9_ff_CQZ_D(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt ff CQZ=IP(60) D=$iopadmap$desIn(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
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+.subckt ff CQZ=IP(28) D=$iopadmap$desIn(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
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+.subckt ff CQZ=IP(56) D=$iopadmap$desIn(59) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=IP(49) D=$iopadmap$desIn(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=IP(57) D=$iopadmap$desIn(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=IP(25) D=$iopadmap$desIn(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=IP(32) D=$iopadmap$desIn(56) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=IP(39) D=$iopadmap$desIn(55) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=IP(7) D=$iopadmap$desIn(54) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:57.1-58.19|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(63) D=FP(40) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(62) D=FP(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(53) D=FP(47) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(52) D=FP(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(51) D=FP(55) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(50) D=FP(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(49) D=FP(63) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(48) D=FP(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(47) D=FP(38) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(46) D=FP(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(45) D=FP(46) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(44) D=FP(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(61) D=FP(48) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(43) D=FP(54) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(42) D=FP(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(37) D=FP(45) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(36) D=FP(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
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+.attr module_not_derived 00000000000000000000000000000001
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(21) D=FP(43) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(18) D=FP(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(17) D=FP(59) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(16) D=FP(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(15) D=FP(34) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(14) D=FP(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(58) D=FP(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(13) D=FP(42) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(12) D=FP(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(11) D=FP(50) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(10) D=FP(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(9) D=FP(58) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(8) D=FP(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(7) D=FP(33) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(6) D=FP(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(5) D=FP(41) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(4) D=FP(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(57) D=FP(64) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(3) D=FP(49) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(2) D=FP(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(1) D=FP(57) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(0) D=FP(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(56) D=FP(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(55) D=FP(39) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$desOut(54) D=FP(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:225.1-233.69|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(55) D=$iopadmap$key(55) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(54) D=$iopadmap$key(54) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(45) D=$iopadmap$key(45) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(44) D=$iopadmap$key(44) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(43) D=$iopadmap$key(43) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(42) D=$iopadmap$key(42) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(41) D=$iopadmap$key(41) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(40) D=$iopadmap$key(40) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(39) D=$iopadmap$key(39) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(38) D=$iopadmap$key(38) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(37) D=$iopadmap$key(37) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(36) D=$iopadmap$key(36) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(53) D=$iopadmap$key(53) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(35) D=$iopadmap$key(35) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(34) D=$iopadmap$key(34) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(33) D=$iopadmap$key(33) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(32) D=$iopadmap$key(32) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(31) D=$iopadmap$key(31) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(30) D=$iopadmap$key(30) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(29) D=$iopadmap$key(29) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(28) D=$iopadmap$key(28) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(27) D=$iopadmap$key(27) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(26) D=$iopadmap$key(26) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(52) D=$iopadmap$key(52) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(25) D=$iopadmap$key(25) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(24) D=$iopadmap$key(24) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(23) D=$iopadmap$key(23) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(22) D=$iopadmap$key(22) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(21) D=$iopadmap$key(21) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(20) D=$iopadmap$key(20) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(19) D=$iopadmap$key(19) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(18) D=$iopadmap$key(18) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(17) D=$iopadmap$key(17) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(16) D=$iopadmap$key(16) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(51) D=$iopadmap$key(51) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(15) D=$iopadmap$key(15) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(14) D=$iopadmap$key(14) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(13) D=$iopadmap$key(13) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(12) D=$iopadmap$key(12) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(11) D=$iopadmap$key(11) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(10) D=$iopadmap$key(10) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(9) D=$iopadmap$key(9) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(8) D=$iopadmap$key(8) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(7) D=$iopadmap$key(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=key_r(6) D=$iopadmap$key(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:53.1-54.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
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+.subckt ff CQZ=uk.K_r9(7) D=uk.K_r8(7) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(6) D=uk.K_r8(6) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(50) D=uk.K_r8(50) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(5) D=uk.K_r8(5) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(4) D=uk.K_r8(4) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(3) D=uk.K_r8(3) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(2) D=uk.K_r8(2) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(1) D=uk.K_r8(1) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(0) D=uk.K_r8(0) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(49) D=uk.K_r8(49) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(48) D=uk.K_r8(48) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(47) D=uk.K_r8(47) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=uk.K_r9(46) D=uk.K_r8(46) QCK=uk.clk QEN=$auto$hilomap.cc:39:hilomap_worker$256819 QRT=K1(1) QST=K1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:67.9-87.3|/home/tpagarani/git/yosys-testing/Designs/des_perf/rtl/des_perf.v:285.1-302.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.end
diff --git a/BENCHMARK/des_perf/rtl/des_perf.v b/BENCHMARK/des_perf/rtl/des_perf.v
new file mode 100644
index 0000000..255c405
--- /dev/null
+++ b/BENCHMARK/des_perf/rtl/des_perf.v
@@ -0,0 +1,2061 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  DES                                                        ////
+////  DES Top Level module                                       ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module des_perf(desOut, desIn, key, decrypt, clk);
+output	[63:0]	desOut;
+input	[63:0]	desIn;
+input	[55:0]	key;
+input		decrypt;
+input		clk;
+
+wire	[1:64]	IP, FP;
+reg	[63:0]	desIn_r;
+reg	[55:0]	key_r;
+reg	[63:0]	desOut;
+reg	[1:32]	L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15;
+reg	[1:32]	R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;
+wire	[1:32]	out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15;
+wire	[1:48]	K1, K2, K3, K4, K5, K6, K7, K8, K9;
+wire	[1:48]	K10, K11, K12, K13, K14, K15, K16;
+
+// Register the 56 bit key
+always @(posedge clk)
+	key_r <= key;
+
+// Register the 64 bit input
+always @(posedge clk)
+	desIn_r <= desIn;
+
+// XOR 32 bit out15 with 32 bit L14         ( FP  1:32 )
+//    then concatinate the 32 bit R14 value ( FP 33:64 )
+//       This value ( FP 1:64 ) is then registered by the desOut[63:0] register 
+assign FP = { (out15 ^ L14), R14};
+
+// Key schedule provides a linear means of intermixing the 56 bit key to form a
+//   different 48 bit key for each of the 16 bit rounds
+key_sel uk(
+	.clk(		clk		),
+	.K(		key_r		),
+	.decrypt(	decrypt		),
+	.K1(		K1		),
+	.K2(		K2		),
+	.K3(		K3		),
+	.K4(		K4		),
+	.K5(		K5		),
+	.K6(		K6		),
+	.K7(		K7		),
+	.K8(		K8		),
+	.K9(		K9		),
+	.K10(		K10		),
+	.K11(		K11		),
+	.K12(		K12		),
+	.K13(		K13		),
+	.K14(		K14		),
+	.K15(		K15		),
+	.K16(		K16		)
+	);
+
+// 16 CRP blocks 
+crp u0( .P(out0), .R(IP[33:64]), .K_sub(K1) );
+crp u1( .P(out1), .R(R0), .K_sub(K2) );
+crp u2( .P(out2), .R(R1), .K_sub(K3) );
+crp u3( .P(out3), .R(R2), .K_sub(K4) );
+crp u4( .P(out4), .R(R3), .K_sub(K5) );
+crp u5( .P(out5), .R(R4), .K_sub(K6) );
+crp u6( .P(out6), .R(R5), .K_sub(K7) );
+crp u7( .P(out7), .R(R6), .K_sub(K8) );
+crp u8( .P(out8), .R(R7), .K_sub(K9) );
+crp u9( .P(out9), .R(R8), .K_sub(K10) );
+crp u10( .P(out10), .R(R9), .K_sub(K11) );
+crp u11( .P(out11), .R(R10), .K_sub(K12) );
+crp u12( .P(out12), .R(R11), .K_sub(K13) );
+crp u13( .P(out13), .R(R12), .K_sub(K14) );
+crp u14( .P(out14), .R(R13), .K_sub(K15) );
+crp u15( .P(out15), .R(R14), .K_sub(K16) );
+
+// 32 bit L0 get upper 32 bits of IP
+always @(posedge clk)
+        L0 <= IP[33:64];
+
+// 32 bit R0 gets lower 32 bits of IP XOR'd with 32 bit out0
+always @(posedge clk)
+        R0 <=   IP[01:32] ^ out0;
+
+// 32 bit L1 gets 32 bit R0
+always @(posedge clk)
+        L1 <=  R0;
+
+// 32 bit R1 gets 32 bit L0 XOR'd with 32 bit out1
+always @(posedge clk)
+        R1 <=  L0 ^ out1;
+
+// 32 bit L2 gets 32 bit R1
+always @(posedge clk)
+        L2 <=  R1;
+
+// 32 bit R2 gets 32 bit L1 XOR'd with 32 bit out2
+always @(posedge clk)
+        R2 <=  L1 ^ out2;
+
+always @(posedge clk)
+        L3 <=  R2;
+
+always @(posedge clk)
+        R3 <=  L2 ^ out3;
+
+always @(posedge clk)
+        L4 <=  R3;
+
+always @(posedge clk)
+        R4 <=  L3 ^ out4;
+
+always @(posedge clk)
+        L5 <=  R4;
+
+always @(posedge clk)
+        R5 <=  L4 ^ out5;
+
+always @(posedge clk)
+        L6 <=  R5;
+
+always @(posedge clk)
+        R6 <=  L5 ^ out6;
+
+always @(posedge clk)
+        L7 <=  R6;
+
+always @(posedge clk)
+        R7 <=  L6 ^ out7;
+
+always @(posedge clk)
+        L8 <=  R7;
+
+always @(posedge clk)
+        R8 <=  L7 ^ out8;
+
+always @(posedge clk)
+        L9 <=  R8;
+
+always @(posedge clk)
+        R9 <=  L8 ^ out9;
+
+always @(posedge clk)
+        L10 <=  R9;
+
+always @(posedge clk)
+        R10 <=  L9 ^ out10;
+
+always @(posedge clk)
+        L11 <=  R10;
+
+always @(posedge clk)
+        R11 <=  L10 ^ out11;
+
+always @(posedge clk)
+        L12 <=  R11;
+
+always @(posedge clk)
+        R12 <=  L11 ^ out12;
+
+always @(posedge clk)
+        L13 <=  R12;
+
+always @(posedge clk)
+        R13 <=  L12 ^ out13;
+
+always @(posedge clk)
+        L14 <=  R13;
+
+always @(posedge clk)
+        R14 <=  L13 ^ out14;
+
+// 32 bit L15 gets 32 bit R14
+always @(posedge clk)
+        L15 <=  R14;
+
+// 32 bit R15 gets 32 bit L14 XOR'd with 32 bit out15
+always @(posedge clk)
+        R15 <=  L14 ^ out15;
+
+// Perform the initial permutationi with the registerd desIn
+assign IP[1:64] = {	desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46],
+			desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28],
+			desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10], 
+			desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58], 
+			desIn_r[0], desIn_r[08], desIn_r[16], desIn_r[24], desIn_r[32], desIn_r[40], 
+			desIn_r[48], desIn_r[56], desIn_r[07], desIn_r[15], desIn_r[23], desIn_r[31], 
+			desIn_r[39], desIn_r[47], desIn_r[55], desIn_r[63], desIn_r[05], desIn_r[13],
+			desIn_r[21], desIn_r[29], desIn_r[37], desIn_r[45], desIn_r[53], desIn_r[61],
+			desIn_r[03], desIn_r[11], desIn_r[19], desIn_r[27], desIn_r[35], desIn_r[43],
+			desIn_r[51], desIn_r[59], desIn_r[01], desIn_r[09], desIn_r[17], desIn_r[25],
+			desIn_r[33], desIn_r[41], desIn_r[49], desIn_r[57] };
+
+// Perform the final permutation
+always @(posedge clk)
+	desOut <=  {	FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32], 
+			FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31], 
+			FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30], 
+			FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29], 
+			FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28], 
+			FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
+			FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26], 
+			FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
+
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  KEY_SEL                                                    ////
+////  Generate 16 pipelined sub-keys                             ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+
+module  key_sel(clk, K, decrypt, K1, K2, K3, K4, K5, K6, K7, K8, K9,
+		K10, K11, K12, K13, K14, K15, K16);
+input		clk;
+input	[55:0]	K;
+input decrypt;
+output	[1:48]	K1, K2, K3, K4, K5, K6, K7, K8, K9;
+output	[1:48]	K10, K11, K12, K13, K14, K15, K16;
+
+wire	[1:48]	K1, K2, K3, K4, K5, K6, K7, K8, K9;
+wire	[1:48]	K10, K11, K12, K13, K14, K15, K16;
+reg	[55:0]	K_r0, K_r1, K_r2, K_r3, K_r4, K_r5, K_r6, K_r7;
+reg	[55:0]	K_r8, K_r9, K_r10, K_r11, K_r12, K_r13, K_r14;
+
+always @(posedge clk)
+   begin
+	K_r0  <=  K;
+	K_r1  <=  K_r0;
+	K_r2  <=  K_r1;
+	K_r3  <=  K_r2;
+	K_r4  <=  K_r3;
+	K_r5  <=  K_r4;
+	K_r6  <=  K_r5;
+	K_r7  <=  K_r6;
+	K_r8  <=  K_r7;
+	K_r9  <=  K_r8;
+	K_r10 <=  K_r9;
+	K_r11 <=  K_r10;
+	K_r12 <=  K_r11;
+	K_r13 <=  K_r12;
+	K_r14 <=  K_r13;
+   end
+
+assign K16[1] = decrypt ? K_r14[47] : K_r14[40];
+assign K16[2] = decrypt ? K_r14[11] : K_r14[4];
+assign K16[3] = decrypt ? K_r14[26] : K_r14[19];
+assign K16[4] = decrypt ? K_r14[3] : K_r14[53];
+assign K16[5] = decrypt ? K_r14[13] : K_r14[6];
+assign K16[6] = decrypt ? K_r14[41] : K_r14[34];
+assign K16[7] = decrypt ? K_r14[27] : K_r14[20];
+assign K16[8] = decrypt ? K_r14[6] : K_r14[24];
+assign K16[9] = decrypt ? K_r14[54] : K_r14[47];
+assign K16[10] = decrypt ? K_r14[48] : K_r14[41];
+assign K16[11] = decrypt ? K_r14[39] : K_r14[32];
+assign K16[12] = decrypt ? K_r14[19] : K_r14[12];
+assign K16[13] = decrypt ? K_r14[53] : K_r14[46];
+assign K16[14] = decrypt ? K_r14[25] : K_r14[18];
+assign K16[15] = decrypt ? K_r14[33] : K_r14[26];
+assign K16[16] = decrypt ? K_r14[34] : K_r14[27];
+assign K16[17] = decrypt ? K_r14[17] : K_r14[10];
+assign K16[18] = decrypt ? K_r14[5] : K_r14[55];
+assign K16[19] = decrypt ? K_r14[4] : K_r14[54];
+assign K16[20] = decrypt ? K_r14[55] : K_r14[48];
+assign K16[21] = decrypt ? K_r14[24] : K_r14[17];
+assign K16[22] = decrypt ? K_r14[32] : K_r14[25];
+assign K16[23] = decrypt ? K_r14[40] : K_r14[33];
+assign K16[24] = decrypt ? K_r14[20] : K_r14[13];
+assign K16[25] = decrypt ? K_r14[36] : K_r14[29];
+assign K16[26] = decrypt ? K_r14[31] : K_r14[51];
+assign K16[27] = decrypt ? K_r14[21] : K_r14[14];
+assign K16[28] = decrypt ? K_r14[8] : K_r14[1];
+assign K16[29] = decrypt ? K_r14[23] : K_r14[16];
+assign K16[30] = decrypt ? K_r14[52] : K_r14[45];
+assign K16[31] = decrypt ? K_r14[14] : K_r14[7];
+assign K16[32] = decrypt ? K_r14[29] : K_r14[22];
+assign K16[33] = decrypt ? K_r14[51] : K_r14[44];
+assign K16[34] = decrypt ? K_r14[9] : K_r14[2];
+assign K16[35] = decrypt ? K_r14[35] : K_r14[28];
+assign K16[36] = decrypt ? K_r14[30] : K_r14[23];
+assign K16[37] = decrypt ? K_r14[2] : K_r14[50];
+assign K16[38] = decrypt ? K_r14[37] : K_r14[30];
+assign K16[39] = decrypt ? K_r14[22] : K_r14[15];
+assign K16[40] = decrypt ? K_r14[0] : K_r14[52];
+assign K16[41] = decrypt ? K_r14[42] : K_r14[35];
+assign K16[42] = decrypt ? K_r14[38] : K_r14[31];
+assign K16[43] = decrypt ? K_r14[16] : K_r14[9];
+assign K16[44] = decrypt ? K_r14[43] : K_r14[36];
+assign K16[45] = decrypt ? K_r14[44] : K_r14[37];
+assign K16[46] = decrypt ? K_r14[1] : K_r14[49];
+assign K16[47] = decrypt ? K_r14[7] : K_r14[0];
+assign K16[48] = decrypt ? K_r14[28] : K_r14[21];
+
+assign K15[1] = decrypt ? K_r13[54] : K_r13[33];
+assign K15[2] = decrypt ? K_r13[18] : K_r13[54];
+assign K15[3] = decrypt ? K_r13[33] : K_r13[12];
+assign K15[4] = decrypt ? K_r13[10] : K_r13[46];
+assign K15[5] = decrypt ? K_r13[20] : K_r13[24];
+assign K15[6] = decrypt ? K_r13[48] : K_r13[27];
+assign K15[7] = decrypt ? K_r13[34] : K_r13[13];
+assign K15[8] = decrypt ? K_r13[13] : K_r13[17];
+assign K15[9] = decrypt ? K_r13[4] : K_r13[40];
+assign K15[10] = decrypt ? K_r13[55] : K_r13[34];
+assign K15[11] = decrypt ? K_r13[46] : K_r13[25];
+assign K15[12] = decrypt ? K_r13[26] : K_r13[5];
+assign K15[13] = decrypt ? K_r13[3] : K_r13[39];
+assign K15[14] = decrypt ? K_r13[32] : K_r13[11];
+assign K15[15] = decrypt ? K_r13[40] : K_r13[19];
+assign K15[16] = decrypt ? K_r13[41] : K_r13[20];
+assign K15[17] = decrypt ? K_r13[24] : K_r13[3];
+assign K15[18] = decrypt ? K_r13[12] : K_r13[48];
+assign K15[19] = decrypt ? K_r13[11] : K_r13[47];
+assign K15[20] = decrypt ? K_r13[5] : K_r13[41];
+assign K15[21] = decrypt ? K_r13[6] : K_r13[10];
+assign K15[22] = decrypt ? K_r13[39] : K_r13[18];
+assign K15[23] = decrypt ? K_r13[47] : K_r13[26];
+assign K15[24] = decrypt ? K_r13[27] : K_r13[6];
+assign K15[25] = decrypt ? K_r13[43] : K_r13[22];
+assign K15[26] = decrypt ? K_r13[38] : K_r13[44];
+assign K15[27] = decrypt ? K_r13[28] : K_r13[7];
+assign K15[28] = decrypt ? K_r13[15] : K_r13[49];
+assign K15[29] = decrypt ? K_r13[30] : K_r13[9];
+assign K15[30] = decrypt ? K_r13[0] : K_r13[38];
+assign K15[31] = decrypt ? K_r13[21] : K_r13[0];
+assign K15[32] = decrypt ? K_r13[36] : K_r13[15];
+assign K15[33] = decrypt ? K_r13[31] : K_r13[37];
+assign K15[34] = decrypt ? K_r13[16] : K_r13[50];
+assign K15[35] = decrypt ? K_r13[42] : K_r13[21];
+assign K15[36] = decrypt ? K_r13[37] : K_r13[16];
+assign K15[37] = decrypt ? K_r13[9] : K_r13[43];
+assign K15[38] = decrypt ? K_r13[44] : K_r13[23];
+assign K15[39] = decrypt ? K_r13[29] : K_r13[8];
+assign K15[40] = decrypt ? K_r13[7] : K_r13[45];
+assign K15[41] = decrypt ? K_r13[49] : K_r13[28];
+assign K15[42] = decrypt ? K_r13[45] : K_r13[51];
+assign K15[43] = decrypt ? K_r13[23] : K_r13[2];
+assign K15[44] = decrypt ? K_r13[50] : K_r13[29];
+assign K15[45] = decrypt ? K_r13[51] : K_r13[30];
+assign K15[46] = decrypt ? K_r13[8] : K_r13[42];
+assign K15[47] = decrypt ? K_r13[14] : K_r13[52];
+assign K15[48] = decrypt ? K_r13[35] : K_r13[14];
+
+assign K14[1] = decrypt ? K_r12[11] : K_r12[19];
+assign K14[2] = decrypt ? K_r12[32] : K_r12[40];
+assign K14[3] = decrypt ? K_r12[47] : K_r12[55];
+assign K14[4] = decrypt ? K_r12[24] : K_r12[32];
+assign K14[5] = decrypt ? K_r12[34] : K_r12[10];
+assign K14[6] = decrypt ? K_r12[5] : K_r12[13];
+assign K14[7] = decrypt ? K_r12[48] : K_r12[24];
+assign K14[8] = decrypt ? K_r12[27] : K_r12[3];
+assign K14[9] = decrypt ? K_r12[18] : K_r12[26];
+assign K14[10] = decrypt ? K_r12[12] : K_r12[20];
+assign K14[11] = decrypt ? K_r12[3] : K_r12[11];
+assign K14[12] = decrypt ? K_r12[40] : K_r12[48];
+assign K14[13] = decrypt ? K_r12[17] : K_r12[25];
+assign K14[14] = decrypt ? K_r12[46] : K_r12[54];
+assign K14[15] = decrypt ? K_r12[54] : K_r12[5];
+assign K14[16] = decrypt ? K_r12[55] : K_r12[6];
+assign K14[17] = decrypt ? K_r12[13] : K_r12[46];
+assign K14[18] = decrypt ? K_r12[26] : K_r12[34];
+assign K14[19] = decrypt ? K_r12[25] : K_r12[33];
+assign K14[20] = decrypt ? K_r12[19] : K_r12[27];
+assign K14[21] = decrypt ? K_r12[20] : K_r12[53];
+assign K14[22] = decrypt ? K_r12[53] : K_r12[4];
+assign K14[23] = decrypt ? K_r12[4] : K_r12[12];
+assign K14[24] = decrypt ? K_r12[41] : K_r12[17];
+assign K14[25] = decrypt ? K_r12[2] : K_r12[8];
+assign K14[26] = decrypt ? K_r12[52] : K_r12[30];
+assign K14[27] = decrypt ? K_r12[42] : K_r12[52];
+assign K14[28] = decrypt ? K_r12[29] : K_r12[35];
+assign K14[29] = decrypt ? K_r12[44] : K_r12[50];
+assign K14[30] = decrypt ? K_r12[14] : K_r12[51];
+assign K14[31] = decrypt ? K_r12[35] : K_r12[45];
+assign K14[32] = decrypt ? K_r12[50] : K_r12[1];
+assign K14[33] = decrypt ? K_r12[45] : K_r12[23];
+assign K14[34] = decrypt ? K_r12[30] : K_r12[36];
+assign K14[35] = decrypt ? K_r12[1] : K_r12[7];
+assign K14[36] = decrypt ? K_r12[51] : K_r12[2];
+assign K14[37] = decrypt ? K_r12[23] : K_r12[29];
+assign K14[38] = decrypt ? K_r12[31] : K_r12[9];
+assign K14[39] = decrypt ? K_r12[43] : K_r12[49];
+assign K14[40] = decrypt ? K_r12[21] : K_r12[31];
+assign K14[41] = decrypt ? K_r12[8] : K_r12[14];
+assign K14[42] = decrypt ? K_r12[0] : K_r12[37];
+assign K14[43] = decrypt ? K_r12[37] : K_r12[43];
+assign K14[44] = decrypt ? K_r12[9] : K_r12[15];
+assign K14[45] = decrypt ? K_r12[38] : K_r12[16];
+assign K14[46] = decrypt ? K_r12[22] : K_r12[28];
+assign K14[47] = decrypt ? K_r12[28] : K_r12[38];
+assign K14[48] = decrypt ? K_r12[49] : K_r12[0];
+
+assign K13[1] = decrypt ? K_r11[25] : K_r11[5];
+assign K13[2] = decrypt ? K_r11[46] : K_r11[26];
+assign K13[3] = decrypt ? K_r11[4] : K_r11[41];
+assign K13[4] = decrypt ? K_r11[13] : K_r11[18];
+assign K13[5] = decrypt ? K_r11[48] : K_r11[53];
+assign K13[6] = decrypt ? K_r11[19] : K_r11[24];
+assign K13[7] = decrypt ? K_r11[5] : K_r11[10];
+assign K13[8] = decrypt ? K_r11[41] : K_r11[46];
+assign K13[9] = decrypt ? K_r11[32] : K_r11[12];
+assign K13[10] = decrypt ? K_r11[26] : K_r11[6];
+assign K13[11] = decrypt ? K_r11[17] : K_r11[54];
+assign K13[12] = decrypt ? K_r11[54] : K_r11[34];
+assign K13[13] = decrypt ? K_r11[6] : K_r11[11];
+assign K13[14] = decrypt ? K_r11[3] : K_r11[40];
+assign K13[15] = decrypt ? K_r11[11] : K_r11[48];
+assign K13[16] = decrypt ? K_r11[12] : K_r11[17];
+assign K13[17] = decrypt ? K_r11[27] : K_r11[32];
+assign K13[18] = decrypt ? K_r11[40] : K_r11[20];
+assign K13[19] = decrypt ? K_r11[39] : K_r11[19];
+assign K13[20] = decrypt ? K_r11[33] : K_r11[13];
+assign K13[21] = decrypt ? K_r11[34] : K_r11[39];
+assign K13[22] = decrypt ? K_r11[10] : K_r11[47];
+assign K13[23] = decrypt ? K_r11[18] : K_r11[55];
+assign K13[24] = decrypt ? K_r11[55] : K_r11[3];
+assign K13[25] = decrypt ? K_r11[16] : K_r11[49];
+assign K13[26] = decrypt ? K_r11[7] : K_r11[16];
+assign K13[27] = decrypt ? K_r11[1] : K_r11[38];
+assign K13[28] = decrypt ? K_r11[43] : K_r11[21];
+assign K13[29] = decrypt ? K_r11[31] : K_r11[36];
+assign K13[30] = decrypt ? K_r11[28] : K_r11[37];
+assign K13[31] = decrypt ? K_r11[49] : K_r11[31];
+assign K13[32] = decrypt ? K_r11[9] : K_r11[42];
+assign K13[33] = decrypt ? K_r11[0] : K_r11[9];
+assign K13[34] = decrypt ? K_r11[44] : K_r11[22];
+assign K13[35] = decrypt ? K_r11[15] : K_r11[52];
+assign K13[36] = decrypt ? K_r11[38] : K_r11[43];
+assign K13[37] = decrypt ? K_r11[37] : K_r11[15];
+assign K13[38] = decrypt ? K_r11[45] : K_r11[50];
+assign K13[39] = decrypt ? K_r11[2] : K_r11[35];
+assign K13[40] = decrypt ? K_r11[35] : K_r11[44];
+assign K13[41] = decrypt ? K_r11[22] : K_r11[0];
+assign K13[42] = decrypt ? K_r11[14] : K_r11[23];
+assign K13[43] = decrypt ? K_r11[51] : K_r11[29];
+assign K13[44] = decrypt ? K_r11[23] : K_r11[1];
+assign K13[45] = decrypt ? K_r11[52] : K_r11[2];
+assign K13[46] = decrypt ? K_r11[36] : K_r11[14];
+assign K13[47] = decrypt ? K_r11[42] : K_r11[51];
+assign K13[48] = decrypt ? K_r11[8] : K_r11[45];
+
+assign K12[1] = decrypt ? K_r10[39] : K_r10[48];
+assign K12[2] = decrypt ? K_r10[3] : K_r10[12];
+assign K12[3] = decrypt ? K_r10[18] : K_r10[27];
+assign K12[4] = decrypt ? K_r10[27] : K_r10[4];
+assign K12[5] = decrypt ? K_r10[5] : K_r10[39];
+assign K12[6] = decrypt ? K_r10[33] : K_r10[10];
+assign K12[7] = decrypt ? K_r10[19] : K_r10[53];
+assign K12[8] = decrypt ? K_r10[55] : K_r10[32];
+assign K12[9] = decrypt ? K_r10[46] : K_r10[55];
+assign K12[10] = decrypt ? K_r10[40] : K_r10[17];
+assign K12[11] = decrypt ? K_r10[6] : K_r10[40];
+assign K12[12] = decrypt ? K_r10[11] : K_r10[20];
+assign K12[13] = decrypt ? K_r10[20] : K_r10[54];
+assign K12[14] = decrypt ? K_r10[17] : K_r10[26];
+assign K12[15] = decrypt ? K_r10[25] : K_r10[34];
+assign K12[16] = decrypt ? K_r10[26] : K_r10[3];
+assign K12[17] = decrypt ? K_r10[41] : K_r10[18];
+assign K12[18] = decrypt ? K_r10[54] : K_r10[6];
+assign K12[19] = decrypt ? K_r10[53] : K_r10[5];
+assign K12[20] = decrypt ? K_r10[47] : K_r10[24];
+assign K12[21] = decrypt ? K_r10[48] : K_r10[25];
+assign K12[22] = decrypt ? K_r10[24] : K_r10[33];
+assign K12[23] = decrypt ? K_r10[32] : K_r10[41];
+assign K12[24] = decrypt ? K_r10[12] : K_r10[46];
+assign K12[25] = decrypt ? K_r10[30] : K_r10[35];
+assign K12[26] = decrypt ? K_r10[21] : K_r10[2];
+assign K12[27] = decrypt ? K_r10[15] : K_r10[51];
+assign K12[28] = decrypt ? K_r10[2] : K_r10[7];
+assign K12[29] = decrypt ? K_r10[45] : K_r10[22];
+assign K12[30] = decrypt ? K_r10[42] : K_r10[23];
+assign K12[31] = decrypt ? K_r10[8] : K_r10[44];
+assign K12[32] = decrypt ? K_r10[23] : K_r10[28];
+assign K12[33] = decrypt ? K_r10[14] : K_r10[50];
+assign K12[34] = decrypt ? K_r10[31] : K_r10[8];
+assign K12[35] = decrypt ? K_r10[29] : K_r10[38];
+assign K12[36] = decrypt ? K_r10[52] : K_r10[29];
+assign K12[37] = decrypt ? K_r10[51] : K_r10[1];
+assign K12[38] = decrypt ? K_r10[0] : K_r10[36];
+assign K12[39] = decrypt ? K_r10[16] : K_r10[21];
+assign K12[40] = decrypt ? K_r10[49] : K_r10[30];
+assign K12[41] = decrypt ? K_r10[36] : K_r10[45];
+assign K12[42] = decrypt ? K_r10[28] : K_r10[9];
+assign K12[43] = decrypt ? K_r10[38] : K_r10[15];
+assign K12[44] = decrypt ? K_r10[37] : K_r10[42];
+assign K12[45] = decrypt ? K_r10[7] : K_r10[43];
+assign K12[46] = decrypt ? K_r10[50] : K_r10[0];
+assign K12[47] = decrypt ? K_r10[1] : K_r10[37];
+assign K12[48] = decrypt ? K_r10[22] : K_r10[31];
+
+assign K11[1] = decrypt ? K_r9[53] : K_r9[34];
+assign K11[2] = decrypt ? K_r9[17] : K_r9[55];
+assign K11[3] = decrypt ? K_r9[32] : K_r9[13];
+assign K11[4] = decrypt ? K_r9[41] : K_r9[47];
+assign K11[5] = decrypt ? K_r9[19] : K_r9[25];
+assign K11[6] = decrypt ? K_r9[47] : K_r9[53];
+assign K11[7] = decrypt ? K_r9[33] : K_r9[39];
+assign K11[8] = decrypt ? K_r9[12] : K_r9[18];
+assign K11[9] = decrypt ? K_r9[3] : K_r9[41];
+assign K11[10] = decrypt ? K_r9[54] : K_r9[3];
+assign K11[11] = decrypt ? K_r9[20] : K_r9[26];
+assign K11[12] = decrypt ? K_r9[25] : K_r9[6];
+assign K11[13] = decrypt ? K_r9[34] : K_r9[40];
+assign K11[14] = decrypt ? K_r9[6] : K_r9[12];
+assign K11[15] = decrypt ? K_r9[39] : K_r9[20];
+assign K11[16] = decrypt ? K_r9[40] : K_r9[46];
+assign K11[17] = decrypt ? K_r9[55] : K_r9[4];
+assign K11[18] = decrypt ? K_r9[11] : K_r9[17];
+assign K11[19] = decrypt ? K_r9[10] : K_r9[48];
+assign K11[20] = decrypt ? K_r9[4] : K_r9[10];
+assign K11[21] = decrypt ? K_r9[5] : K_r9[11];
+assign K11[22] = decrypt ? K_r9[13] : K_r9[19];
+assign K11[23] = decrypt ? K_r9[46] : K_r9[27];
+assign K11[24] = decrypt ? K_r9[26] : K_r9[32];
+assign K11[25] = decrypt ? K_r9[44] : K_r9[21];
+assign K11[26] = decrypt ? K_r9[35] : K_r9[43];
+assign K11[27] = decrypt ? K_r9[29] : K_r9[37];
+assign K11[28] = decrypt ? K_r9[16] : K_r9[52];
+assign K11[29] = decrypt ? K_r9[0] : K_r9[8];
+assign K11[30] = decrypt ? K_r9[1] : K_r9[9];
+assign K11[31] = decrypt ? K_r9[22] : K_r9[30];
+assign K11[32] = decrypt ? K_r9[37] : K_r9[14];
+assign K11[33] = decrypt ? K_r9[28] : K_r9[36];
+assign K11[34] = decrypt ? K_r9[45] : K_r9[49];
+assign K11[35] = decrypt ? K_r9[43] : K_r9[51];
+assign K11[36] = decrypt ? K_r9[7] : K_r9[15];
+assign K11[37] = decrypt ? K_r9[38] : K_r9[42];
+assign K11[38] = decrypt ? K_r9[14] : K_r9[22];
+assign K11[39] = decrypt ? K_r9[30] : K_r9[7];
+assign K11[40] = decrypt ? K_r9[8] : K_r9[16];
+assign K11[41] = decrypt ? K_r9[50] : K_r9[31];
+assign K11[42] = decrypt ? K_r9[42] : K_r9[50];
+assign K11[43] = decrypt ? K_r9[52] : K_r9[1];
+assign K11[44] = decrypt ? K_r9[51] : K_r9[28];
+assign K11[45] = decrypt ? K_r9[21] : K_r9[29];
+assign K11[46] = decrypt ? K_r9[9] : K_r9[45];
+assign K11[47] = decrypt ? K_r9[15] : K_r9[23];
+assign K11[48] = decrypt ? K_r9[36] : K_r9[44];
+
+assign K10[1] = decrypt ? K_r8[10] : K_r8[20];
+assign K10[2] = decrypt ? K_r8[6] : K_r8[41];
+assign K10[3] = decrypt ? K_r8[46] : K_r8[24];
+assign K10[4] = decrypt ? K_r8[55] : K_r8[33];
+assign K10[5] = decrypt ? K_r8[33] : K_r8[11];
+assign K10[6] = decrypt ? K_r8[4] : K_r8[39];
+assign K10[7] = decrypt ? K_r8[47] : K_r8[25];
+assign K10[8] = decrypt ? K_r8[26] : K_r8[4];
+assign K10[9] = decrypt ? K_r8[17] : K_r8[27];
+assign K10[10] = decrypt ? K_r8[11] : K_r8[46];
+assign K10[11] = decrypt ? K_r8[34] : K_r8[12];
+assign K10[12] = decrypt ? K_r8[39] : K_r8[17];
+assign K10[13] = decrypt ? K_r8[48] : K_r8[26];
+assign K10[14] = decrypt ? K_r8[20] : K_r8[55];
+assign K10[15] = decrypt ? K_r8[53] : K_r8[6];
+assign K10[16] = decrypt ? K_r8[54] : K_r8[32];
+assign K10[17] = decrypt ? K_r8[12] : K_r8[47];
+assign K10[18] = decrypt ? K_r8[25] : K_r8[3];
+assign K10[19] = decrypt ? K_r8[24] : K_r8[34];
+assign K10[20] = decrypt ? K_r8[18] : K_r8[53];
+assign K10[21] = decrypt ? K_r8[19] : K_r8[54];
+assign K10[22] = decrypt ? K_r8[27] : K_r8[5];
+assign K10[23] = decrypt ? K_r8[3] : K_r8[13];
+assign K10[24] = decrypt ? K_r8[40] : K_r8[18];
+assign K10[25] = decrypt ? K_r8[31] : K_r8[7];
+assign K10[26] = decrypt ? K_r8[49] : K_r8[29];
+assign K10[27] = decrypt ? K_r8[43] : K_r8[23];
+assign K10[28] = decrypt ? K_r8[30] : K_r8[38];
+assign K10[29] = decrypt ? K_r8[14] : K_r8[49];
+assign K10[30] = decrypt ? K_r8[15] : K_r8[50];
+assign K10[31] = decrypt ? K_r8[36] : K_r8[16];
+assign K10[32] = decrypt ? K_r8[51] : K_r8[0];
+assign K10[33] = decrypt ? K_r8[42] : K_r8[22];
+assign K10[34] = decrypt ? K_r8[0] : K_r8[35];
+assign K10[35] = decrypt ? K_r8[2] : K_r8[37];
+assign K10[36] = decrypt ? K_r8[21] : K_r8[1];
+assign K10[37] = decrypt ? K_r8[52] : K_r8[28];
+assign K10[38] = decrypt ? K_r8[28] : K_r8[8];
+assign K10[39] = decrypt ? K_r8[44] : K_r8[52];
+assign K10[40] = decrypt ? K_r8[22] : K_r8[2];
+assign K10[41] = decrypt ? K_r8[9] : K_r8[44];
+assign K10[42] = decrypt ? K_r8[1] : K_r8[36];
+assign K10[43] = decrypt ? K_r8[7] : K_r8[42];
+assign K10[44] = decrypt ? K_r8[38] : K_r8[14];
+assign K10[45] = decrypt ? K_r8[35] : K_r8[15];
+assign K10[46] = decrypt ? K_r8[23] : K_r8[31];
+assign K10[47] = decrypt ? K_r8[29] : K_r8[9];
+assign K10[48] = decrypt ? K_r8[50] : K_r8[30];
+
+assign K9[1] = decrypt ? K_r7[24] : K_r7[6];
+assign K9[2] = decrypt ? K_r7[20] : K_r7[27];
+assign K9[3] = decrypt ? K_r7[3] : K_r7[10];
+assign K9[4] = decrypt ? K_r7[12] : K_r7[19];
+assign K9[5] = decrypt ? K_r7[47] : K_r7[54];
+assign K9[6] = decrypt ? K_r7[18] : K_r7[25];
+assign K9[7] = decrypt ? K_r7[4] : K_r7[11];
+assign K9[8] = decrypt ? K_r7[40] : K_r7[47];
+assign K9[9] = decrypt ? K_r7[6] : K_r7[13];
+assign K9[10] = decrypt ? K_r7[25] : K_r7[32];
+assign K9[11] = decrypt ? K_r7[48] : K_r7[55];
+assign K9[12] = decrypt ? K_r7[53] : K_r7[3];
+assign K9[13] = decrypt ? K_r7[5] : K_r7[12];
+assign K9[14] = decrypt ? K_r7[34] : K_r7[41];
+assign K9[15] = decrypt ? K_r7[10] : K_r7[17];
+assign K9[16] = decrypt ? K_r7[11] : K_r7[18];
+assign K9[17] = decrypt ? K_r7[26] : K_r7[33];
+assign K9[18] = decrypt ? K_r7[39] : K_r7[46];
+assign K9[19] = decrypt ? K_r7[13] : K_r7[20];
+assign K9[20] = decrypt ? K_r7[32] : K_r7[39];
+assign K9[21] = decrypt ? K_r7[33] : K_r7[40];
+assign K9[22] = decrypt ? K_r7[41] : K_r7[48];
+assign K9[23] = decrypt ? K_r7[17] : K_r7[24];
+assign K9[24] = decrypt ? K_r7[54] : K_r7[4];
+assign K9[25] = decrypt ? K_r7[45] : K_r7[52];
+assign K9[26] = decrypt ? K_r7[8] : K_r7[15];
+assign K9[27] = decrypt ? K_r7[2] : K_r7[9];
+assign K9[28] = decrypt ? K_r7[44] : K_r7[51];
+assign K9[29] = decrypt ? K_r7[28] : K_r7[35];
+assign K9[30] = decrypt ? K_r7[29] : K_r7[36];
+assign K9[31] = decrypt ? K_r7[50] : K_r7[2];
+assign K9[32] = decrypt ? K_r7[38] : K_r7[45];
+assign K9[33] = decrypt ? K_r7[1] : K_r7[8];
+assign K9[34] = decrypt ? K_r7[14] : K_r7[21];
+assign K9[35] = decrypt ? K_r7[16] : K_r7[23];
+assign K9[36] = decrypt ? K_r7[35] : K_r7[42];
+assign K9[37] = decrypt ? K_r7[7] : K_r7[14];
+assign K9[38] = decrypt ? K_r7[42] : K_r7[49];
+assign K9[39] = decrypt ? K_r7[31] : K_r7[38];
+assign K9[40] = decrypt ? K_r7[36] : K_r7[43];
+assign K9[41] = decrypt ? K_r7[23] : K_r7[30];
+assign K9[42] = decrypt ? K_r7[15] : K_r7[22];
+assign K9[43] = decrypt ? K_r7[21] : K_r7[28];
+assign K9[44] = decrypt ? K_r7[52] : K_r7[0];
+assign K9[45] = decrypt ? K_r7[49] : K_r7[1];
+assign K9[46] = decrypt ? K_r7[37] : K_r7[44];
+assign K9[47] = decrypt ? K_r7[43] : K_r7[50];
+assign K9[48] = decrypt ? K_r7[9] : K_r7[16];
+
+assign K8[1] = decrypt ? K_r6[6] : K_r6[24];
+assign K8[2] = decrypt ? K_r6[27] : K_r6[20];
+assign K8[3] = decrypt ? K_r6[10] : K_r6[3];
+assign K8[4] = decrypt ? K_r6[19] : K_r6[12];
+assign K8[5] = decrypt ? K_r6[54] : K_r6[47];
+assign K8[6] = decrypt ? K_r6[25] : K_r6[18];
+assign K8[7] = decrypt ? K_r6[11] : K_r6[4];
+assign K8[8] = decrypt ? K_r6[47] : K_r6[40];
+assign K8[9] = decrypt ? K_r6[13] : K_r6[6];
+assign K8[10] = decrypt ? K_r6[32] : K_r6[25];
+assign K8[11] = decrypt ? K_r6[55] : K_r6[48];
+assign K8[12] = decrypt ? K_r6[3] : K_r6[53];
+assign K8[13] = decrypt ? K_r6[12] : K_r6[5];
+assign K8[14] = decrypt ? K_r6[41] : K_r6[34];
+assign K8[15] = decrypt ? K_r6[17] : K_r6[10];
+assign K8[16] = decrypt ? K_r6[18] : K_r6[11];
+assign K8[17] = decrypt ? K_r6[33] : K_r6[26];
+assign K8[18] = decrypt ? K_r6[46] : K_r6[39];
+assign K8[19] = decrypt ? K_r6[20] : K_r6[13];
+assign K8[20] = decrypt ? K_r6[39] : K_r6[32];
+assign K8[21] = decrypt ? K_r6[40] : K_r6[33];
+assign K8[22] = decrypt ? K_r6[48] : K_r6[41];
+assign K8[23] = decrypt ? K_r6[24] : K_r6[17];
+assign K8[24] = decrypt ? K_r6[4] : K_r6[54];
+assign K8[25] = decrypt ? K_r6[52] : K_r6[45];
+assign K8[26] = decrypt ? K_r6[15] : K_r6[8];
+assign K8[27] = decrypt ? K_r6[9] : K_r6[2];
+assign K8[28] = decrypt ? K_r6[51] : K_r6[44];
+assign K8[29] = decrypt ? K_r6[35] : K_r6[28];
+assign K8[30] = decrypt ? K_r6[36] : K_r6[29];
+assign K8[31] = decrypt ? K_r6[2] : K_r6[50];
+assign K8[32] = decrypt ? K_r6[45] : K_r6[38];
+assign K8[33] = decrypt ? K_r6[8] : K_r6[1];
+assign K8[34] = decrypt ? K_r6[21] : K_r6[14];
+assign K8[35] = decrypt ? K_r6[23] : K_r6[16];
+assign K8[36] = decrypt ? K_r6[42] : K_r6[35];
+assign K8[37] = decrypt ? K_r6[14] : K_r6[7];
+assign K8[38] = decrypt ? K_r6[49] : K_r6[42];
+assign K8[39] = decrypt ? K_r6[38] : K_r6[31];
+assign K8[40] = decrypt ? K_r6[43] : K_r6[36];
+assign K8[41] = decrypt ? K_r6[30] : K_r6[23];
+assign K8[42] = decrypt ? K_r6[22] : K_r6[15];
+assign K8[43] = decrypt ? K_r6[28] : K_r6[21];
+assign K8[44] = decrypt ? K_r6[0] : K_r6[52];
+assign K8[45] = decrypt ? K_r6[1] : K_r6[49];
+assign K8[46] = decrypt ? K_r6[44] : K_r6[37];
+assign K8[47] = decrypt ? K_r6[50] : K_r6[43];
+assign K8[48] = decrypt ? K_r6[16] : K_r6[9];
+
+assign K7[1] = decrypt ? K_r5[20] : K_r5[10];
+assign K7[2] = decrypt ? K_r5[41] : K_r5[6];
+assign K7[3] = decrypt ? K_r5[24] : K_r5[46];
+assign K7[4] = decrypt ? K_r5[33] : K_r5[55];
+assign K7[5] = decrypt ? K_r5[11] : K_r5[33];
+assign K7[6] = decrypt ? K_r5[39] : K_r5[4];
+assign K7[7] = decrypt ? K_r5[25] : K_r5[47];
+assign K7[8] = decrypt ? K_r5[4] : K_r5[26];
+assign K7[9] = decrypt ? K_r5[27] : K_r5[17];
+assign K7[10] = decrypt ? K_r5[46] : K_r5[11];
+assign K7[11] = decrypt ? K_r5[12] : K_r5[34];
+assign K7[12] = decrypt ? K_r5[17] : K_r5[39];
+assign K7[13] = decrypt ? K_r5[26] : K_r5[48];
+assign K7[14] = decrypt ? K_r5[55] : K_r5[20];
+assign K7[15] = decrypt ? K_r5[6] : K_r5[53];
+assign K7[16] = decrypt ? K_r5[32] : K_r5[54];
+assign K7[17] = decrypt ? K_r5[47] : K_r5[12];
+assign K7[18] = decrypt ? K_r5[3] : K_r5[25];
+assign K7[19] = decrypt ? K_r5[34] : K_r5[24];
+assign K7[20] = decrypt ? K_r5[53] : K_r5[18];
+assign K7[21] = decrypt ? K_r5[54] : K_r5[19];
+assign K7[22] = decrypt ? K_r5[5] : K_r5[27];
+assign K7[23] = decrypt ? K_r5[13] : K_r5[3];
+assign K7[24] = decrypt ? K_r5[18] : K_r5[40];
+assign K7[25] = decrypt ? K_r5[7] : K_r5[31];
+assign K7[26] = decrypt ? K_r5[29] : K_r5[49];
+assign K7[27] = decrypt ? K_r5[23] : K_r5[43];
+assign K7[28] = decrypt ? K_r5[38] : K_r5[30];
+assign K7[29] = decrypt ? K_r5[49] : K_r5[14];
+assign K7[30] = decrypt ? K_r5[50] : K_r5[15];
+assign K7[31] = decrypt ? K_r5[16] : K_r5[36];
+assign K7[32] = decrypt ? K_r5[0] : K_r5[51];
+assign K7[33] = decrypt ? K_r5[22] : K_r5[42];
+assign K7[34] = decrypt ? K_r5[35] : K_r5[0];
+assign K7[35] = decrypt ? K_r5[37] : K_r5[2];
+assign K7[36] = decrypt ? K_r5[1] : K_r5[21];
+assign K7[37] = decrypt ? K_r5[28] : K_r5[52];
+assign K7[38] = decrypt ? K_r5[8] : K_r5[28];
+assign K7[39] = decrypt ? K_r5[52] : K_r5[44];
+assign K7[40] = decrypt ? K_r5[2] : K_r5[22];
+assign K7[41] = decrypt ? K_r5[44] : K_r5[9];
+assign K7[42] = decrypt ? K_r5[36] : K_r5[1];
+assign K7[43] = decrypt ? K_r5[42] : K_r5[7];
+assign K7[44] = decrypt ? K_r5[14] : K_r5[38];
+assign K7[45] = decrypt ? K_r5[15] : K_r5[35];
+assign K7[46] = decrypt ? K_r5[31] : K_r5[23];
+assign K7[47] = decrypt ? K_r5[9] : K_r5[29];
+assign K7[48] = decrypt ? K_r5[30] : K_r5[50];
+
+assign K6[1] = decrypt ? K_r4[34] : K_r4[53];
+assign K6[2] = decrypt ? K_r4[55] : K_r4[17];
+assign K6[3] = decrypt ? K_r4[13] : K_r4[32];
+assign K6[4] = decrypt ? K_r4[47] : K_r4[41];
+assign K6[5] = decrypt ? K_r4[25] : K_r4[19];
+assign K6[6] = decrypt ? K_r4[53] : K_r4[47];
+assign K6[7] = decrypt ? K_r4[39] : K_r4[33];
+assign K6[8] = decrypt ? K_r4[18] : K_r4[12];
+assign K6[9] = decrypt ? K_r4[41] : K_r4[3];
+assign K6[10] = decrypt ? K_r4[3] : K_r4[54];
+assign K6[11] = decrypt ? K_r4[26] : K_r4[20];
+assign K6[12] = decrypt ? K_r4[6] : K_r4[25];
+assign K6[13] = decrypt ? K_r4[40] : K_r4[34];
+assign K6[14] = decrypt ? K_r4[12] : K_r4[6];
+assign K6[15] = decrypt ? K_r4[20] : K_r4[39];
+assign K6[16] = decrypt ? K_r4[46] : K_r4[40];
+assign K6[17] = decrypt ? K_r4[4] : K_r4[55];
+assign K6[18] = decrypt ? K_r4[17] : K_r4[11];
+assign K6[19] = decrypt ? K_r4[48] : K_r4[10];
+assign K6[20] = decrypt ? K_r4[10] : K_r4[4];
+assign K6[21] = decrypt ? K_r4[11] : K_r4[5];
+assign K6[22] = decrypt ? K_r4[19] : K_r4[13];
+assign K6[23] = decrypt ? K_r4[27] : K_r4[46];
+assign K6[24] = decrypt ? K_r4[32] : K_r4[26];
+assign K6[25] = decrypt ? K_r4[21] : K_r4[44];
+assign K6[26] = decrypt ? K_r4[43] : K_r4[35];
+assign K6[27] = decrypt ? K_r4[37] : K_r4[29];
+assign K6[28] = decrypt ? K_r4[52] : K_r4[16];
+assign K6[29] = decrypt ? K_r4[8] : K_r4[0];
+assign K6[30] = decrypt ? K_r4[9] : K_r4[1];
+assign K6[31] = decrypt ? K_r4[30] : K_r4[22];
+assign K6[32] = decrypt ? K_r4[14] : K_r4[37];
+assign K6[33] = decrypt ? K_r4[36] : K_r4[28];
+assign K6[34] = decrypt ? K_r4[49] : K_r4[45];
+assign K6[35] = decrypt ? K_r4[51] : K_r4[43];
+assign K6[36] = decrypt ? K_r4[15] : K_r4[7];
+assign K6[37] = decrypt ? K_r4[42] : K_r4[38];
+assign K6[38] = decrypt ? K_r4[22] : K_r4[14];
+assign K6[39] = decrypt ? K_r4[7] : K_r4[30];
+assign K6[40] = decrypt ? K_r4[16] : K_r4[8];
+assign K6[41] = decrypt ? K_r4[31] : K_r4[50];
+assign K6[42] = decrypt ? K_r4[50] : K_r4[42];
+assign K6[43] = decrypt ? K_r4[1] : K_r4[52];
+assign K6[44] = decrypt ? K_r4[28] : K_r4[51];
+assign K6[45] = decrypt ? K_r4[29] : K_r4[21];
+assign K6[46] = decrypt ? K_r4[45] : K_r4[9];
+assign K6[47] = decrypt ? K_r4[23] : K_r4[15];
+assign K6[48] = decrypt ? K_r4[44] : K_r4[36];
+
+assign K5[1] = decrypt ? K_r3[48] : K_r3[39];
+assign K5[2] = decrypt ? K_r3[12] : K_r3[3];
+assign K5[3] = decrypt ? K_r3[27] : K_r3[18];
+assign K5[4] = decrypt ? K_r3[4] : K_r3[27];
+assign K5[5] = decrypt ? K_r3[39] : K_r3[5];
+assign K5[6] = decrypt ? K_r3[10] : K_r3[33];
+assign K5[7] = decrypt ? K_r3[53] : K_r3[19];
+assign K5[8] = decrypt ? K_r3[32] : K_r3[55];
+assign K5[9] = decrypt ? K_r3[55] : K_r3[46];
+assign K5[10] = decrypt ? K_r3[17] : K_r3[40];
+assign K5[11] = decrypt ? K_r3[40] : K_r3[6];
+assign K5[12] = decrypt ? K_r3[20] : K_r3[11];
+assign K5[13] = decrypt ? K_r3[54] : K_r3[20];
+assign K5[14] = decrypt ? K_r3[26] : K_r3[17];
+assign K5[15] = decrypt ? K_r3[34] : K_r3[25];
+assign K5[16] = decrypt ? K_r3[3] : K_r3[26];
+assign K5[17] = decrypt ? K_r3[18] : K_r3[41];
+assign K5[18] = decrypt ? K_r3[6] : K_r3[54];
+assign K5[19] = decrypt ? K_r3[5] : K_r3[53];
+assign K5[20] = decrypt ? K_r3[24] : K_r3[47];
+assign K5[21] = decrypt ? K_r3[25] : K_r3[48];
+assign K5[22] = decrypt ? K_r3[33] : K_r3[24];
+assign K5[23] = decrypt ? K_r3[41] : K_r3[32];
+assign K5[24] = decrypt ? K_r3[46] : K_r3[12];
+assign K5[25] = decrypt ? K_r3[35] : K_r3[30];
+assign K5[26] = decrypt ? K_r3[2] : K_r3[21];
+assign K5[27] = decrypt ? K_r3[51] : K_r3[15];
+assign K5[28] = decrypt ? K_r3[7] : K_r3[2];
+assign K5[29] = decrypt ? K_r3[22] : K_r3[45];
+assign K5[30] = decrypt ? K_r3[23] : K_r3[42];
+assign K5[31] = decrypt ? K_r3[44] : K_r3[8];
+assign K5[32] = decrypt ? K_r3[28] : K_r3[23];
+assign K5[33] = decrypt ? K_r3[50] : K_r3[14];
+assign K5[34] = decrypt ? K_r3[8] : K_r3[31];
+assign K5[35] = decrypt ? K_r3[38] : K_r3[29];
+assign K5[36] = decrypt ? K_r3[29] : K_r3[52];
+assign K5[37] = decrypt ? K_r3[1] : K_r3[51];
+assign K5[38] = decrypt ? K_r3[36] : K_r3[0];
+assign K5[39] = decrypt ? K_r3[21] : K_r3[16];
+assign K5[40] = decrypt ? K_r3[30] : K_r3[49];
+assign K5[41] = decrypt ? K_r3[45] : K_r3[36];
+assign K5[42] = decrypt ? K_r3[9] : K_r3[28];
+assign K5[43] = decrypt ? K_r3[15] : K_r3[38];
+assign K5[44] = decrypt ? K_r3[42] : K_r3[37];
+assign K5[45] = decrypt ? K_r3[43] : K_r3[7];
+assign K5[46] = decrypt ? K_r3[0] : K_r3[50];
+assign K5[47] = decrypt ? K_r3[37] : K_r3[1];
+assign K5[48] = decrypt ? K_r3[31] : K_r3[22];
+
+assign K4[1] = decrypt ? K_r2[5] : K_r2[25];
+assign K4[2] = decrypt ? K_r2[26] : K_r2[46];
+assign K4[3] = decrypt ? K_r2[41] : K_r2[4];
+assign K4[4] = decrypt ? K_r2[18] : K_r2[13];
+assign K4[5] = decrypt ? K_r2[53] : K_r2[48];
+assign K4[6] = decrypt ? K_r2[24] : K_r2[19];
+assign K4[7] = decrypt ? K_r2[10] : K_r2[5];
+assign K4[8] = decrypt ? K_r2[46] : K_r2[41];
+assign K4[9] = decrypt ? K_r2[12] : K_r2[32];
+assign K4[10] = decrypt ? K_r2[6] : K_r2[26];
+assign K4[11] = decrypt ? K_r2[54] : K_r2[17];
+assign K4[12] = decrypt ? K_r2[34] : K_r2[54];
+assign K4[13] = decrypt ? K_r2[11] : K_r2[6];
+assign K4[14] = decrypt ? K_r2[40] : K_r2[3];
+assign K4[15] = decrypt ? K_r2[48] : K_r2[11];
+assign K4[16] = decrypt ? K_r2[17] : K_r2[12];
+assign K4[17] = decrypt ? K_r2[32] : K_r2[27];
+assign K4[18] = decrypt ? K_r2[20] : K_r2[40];
+assign K4[19] = decrypt ? K_r2[19] : K_r2[39];
+assign K4[20] = decrypt ? K_r2[13] : K_r2[33];
+assign K4[21] = decrypt ? K_r2[39] : K_r2[34];
+assign K4[22] = decrypt ? K_r2[47] : K_r2[10];
+assign K4[23] = decrypt ? K_r2[55] : K_r2[18];
+assign K4[24] = decrypt ? K_r2[3] : K_r2[55];
+assign K4[25] = decrypt ? K_r2[49] : K_r2[16];
+assign K4[26] = decrypt ? K_r2[16] : K_r2[7];
+assign K4[27] = decrypt ? K_r2[38] : K_r2[1];
+assign K4[28] = decrypt ? K_r2[21] : K_r2[43];
+assign K4[29] = decrypt ? K_r2[36] : K_r2[31];
+assign K4[30] = decrypt ? K_r2[37] : K_r2[28];
+assign K4[31] = decrypt ? K_r2[31] : K_r2[49];
+assign K4[32] = decrypt ? K_r2[42] : K_r2[9];
+assign K4[33] = decrypt ? K_r2[9] : K_r2[0];
+assign K4[34] = decrypt ? K_r2[22] : K_r2[44];
+assign K4[35] = decrypt ? K_r2[52] : K_r2[15];
+assign K4[36] = decrypt ? K_r2[43] : K_r2[38];
+assign K4[37] = decrypt ? K_r2[15] : K_r2[37];
+assign K4[38] = decrypt ? K_r2[50] : K_r2[45];
+assign K4[39] = decrypt ? K_r2[35] : K_r2[2];
+assign K4[40] = decrypt ? K_r2[44] : K_r2[35];
+assign K4[41] = decrypt ? K_r2[0] : K_r2[22];
+assign K4[42] = decrypt ? K_r2[23] : K_r2[14];
+assign K4[43] = decrypt ? K_r2[29] : K_r2[51];
+assign K4[44] = decrypt ? K_r2[1] : K_r2[23];
+assign K4[45] = decrypt ? K_r2[2] : K_r2[52];
+assign K4[46] = decrypt ? K_r2[14] : K_r2[36];
+assign K4[47] = decrypt ? K_r2[51] : K_r2[42];
+assign K4[48] = decrypt ? K_r2[45] : K_r2[8];
+
+assign K3[1] = decrypt ? K_r1[19] : K_r1[11];
+assign K3[2] = decrypt ? K_r1[40] : K_r1[32];
+assign K3[3] = decrypt ? K_r1[55] : K_r1[47];
+assign K3[4] = decrypt ? K_r1[32] : K_r1[24];
+assign K3[5] = decrypt ? K_r1[10] : K_r1[34];
+assign K3[6] = decrypt ? K_r1[13] : K_r1[5];
+assign K3[7] = decrypt ? K_r1[24] : K_r1[48];
+assign K3[8] = decrypt ? K_r1[3] : K_r1[27];
+assign K3[9] = decrypt ? K_r1[26] : K_r1[18];
+assign K3[10] = decrypt ? K_r1[20] : K_r1[12];
+assign K3[11] = decrypt ? K_r1[11] : K_r1[3];
+assign K3[12] = decrypt ? K_r1[48] : K_r1[40];
+assign K3[13] = decrypt ? K_r1[25] : K_r1[17];
+assign K3[14] = decrypt ? K_r1[54] : K_r1[46];
+assign K3[15] = decrypt ? K_r1[5] : K_r1[54];
+assign K3[16] = decrypt ? K_r1[6] : K_r1[55];
+assign K3[17] = decrypt ? K_r1[46] : K_r1[13];
+assign K3[18] = decrypt ? K_r1[34] : K_r1[26];
+assign K3[19] = decrypt ? K_r1[33] : K_r1[25];
+assign K3[20] = decrypt ? K_r1[27] : K_r1[19];
+assign K3[21] = decrypt ? K_r1[53] : K_r1[20];
+assign K3[22] = decrypt ? K_r1[4] : K_r1[53];
+assign K3[23] = decrypt ? K_r1[12] : K_r1[4];
+assign K3[24] = decrypt ? K_r1[17] : K_r1[41];
+assign K3[25] = decrypt ? K_r1[8] : K_r1[2];
+assign K3[26] = decrypt ? K_r1[30] : K_r1[52];
+assign K3[27] = decrypt ? K_r1[52] : K_r1[42];
+assign K3[28] = decrypt ? K_r1[35] : K_r1[29];
+assign K3[29] = decrypt ? K_r1[50] : K_r1[44];
+assign K3[30] = decrypt ? K_r1[51] : K_r1[14];
+assign K3[31] = decrypt ? K_r1[45] : K_r1[35];
+assign K3[32] = decrypt ? K_r1[1] : K_r1[50];
+assign K3[33] = decrypt ? K_r1[23] : K_r1[45];
+assign K3[34] = decrypt ? K_r1[36] : K_r1[30];
+assign K3[35] = decrypt ? K_r1[7] : K_r1[1];
+assign K3[36] = decrypt ? K_r1[2] : K_r1[51];
+assign K3[37] = decrypt ? K_r1[29] : K_r1[23];
+assign K3[38] = decrypt ? K_r1[9] : K_r1[31];
+assign K3[39] = decrypt ? K_r1[49] : K_r1[43];
+assign K3[40] = decrypt ? K_r1[31] : K_r1[21];
+assign K3[41] = decrypt ? K_r1[14] : K_r1[8];
+assign K3[42] = decrypt ? K_r1[37] : K_r1[0];
+assign K3[43] = decrypt ? K_r1[43] : K_r1[37];
+assign K3[44] = decrypt ? K_r1[15] : K_r1[9];
+assign K3[45] = decrypt ? K_r1[16] : K_r1[38];
+assign K3[46] = decrypt ? K_r1[28] : K_r1[22];
+assign K3[47] = decrypt ? K_r1[38] : K_r1[28];
+assign K3[48] = decrypt ? K_r1[0] : K_r1[49];
+
+assign K2[1] = decrypt ? K_r0[33] : K_r0[54];
+assign K2[2] = decrypt ? K_r0[54] : K_r0[18];
+assign K2[3] = decrypt ? K_r0[12] : K_r0[33];
+assign K2[4] = decrypt ? K_r0[46] : K_r0[10];
+assign K2[5] = decrypt ? K_r0[24] : K_r0[20];
+assign K2[6] = decrypt ? K_r0[27] : K_r0[48];
+assign K2[7] = decrypt ? K_r0[13] : K_r0[34];
+assign K2[8] = decrypt ? K_r0[17] : K_r0[13];
+assign K2[9] = decrypt ? K_r0[40] : K_r0[4];
+assign K2[10] = decrypt ? K_r0[34] : K_r0[55];
+assign K2[11] = decrypt ? K_r0[25] : K_r0[46];
+assign K2[12] = decrypt ? K_r0[5] : K_r0[26];
+assign K2[13] = decrypt ? K_r0[39] : K_r0[3];
+assign K2[14] = decrypt ? K_r0[11] : K_r0[32];
+assign K2[15] = decrypt ? K_r0[19] : K_r0[40];
+assign K2[16] = decrypt ? K_r0[20] : K_r0[41];
+assign K2[17] = decrypt ? K_r0[3] : K_r0[24];
+assign K2[18] = decrypt ? K_r0[48] : K_r0[12];
+assign K2[19] = decrypt ? K_r0[47] : K_r0[11];
+assign K2[20] = decrypt ? K_r0[41] : K_r0[5];
+assign K2[21] = decrypt ? K_r0[10] : K_r0[6];
+assign K2[22] = decrypt ? K_r0[18] : K_r0[39];
+assign K2[23] = decrypt ? K_r0[26] : K_r0[47];
+assign K2[24] = decrypt ? K_r0[6] : K_r0[27];
+assign K2[25] = decrypt ? K_r0[22] : K_r0[43];
+assign K2[26] = decrypt ? K_r0[44] : K_r0[38];
+assign K2[27] = decrypt ? K_r0[7] : K_r0[28];
+assign K2[28] = decrypt ? K_r0[49] : K_r0[15];
+assign K2[29] = decrypt ? K_r0[9] : K_r0[30];
+assign K2[30] = decrypt ? K_r0[38] : K_r0[0];
+assign K2[31] = decrypt ? K_r0[0] : K_r0[21];
+assign K2[32] = decrypt ? K_r0[15] : K_r0[36];
+assign K2[33] = decrypt ? K_r0[37] : K_r0[31];
+assign K2[34] = decrypt ? K_r0[50] : K_r0[16];
+assign K2[35] = decrypt ? K_r0[21] : K_r0[42];
+assign K2[36] = decrypt ? K_r0[16] : K_r0[37];
+assign K2[37] = decrypt ? K_r0[43] : K_r0[9];
+assign K2[38] = decrypt ? K_r0[23] : K_r0[44];
+assign K2[39] = decrypt ? K_r0[8] : K_r0[29];
+assign K2[40] = decrypt ? K_r0[45] : K_r0[7];
+assign K2[41] = decrypt ? K_r0[28] : K_r0[49];
+assign K2[42] = decrypt ? K_r0[51] : K_r0[45];
+assign K2[43] = decrypt ? K_r0[2] : K_r0[23];
+assign K2[44] = decrypt ? K_r0[29] : K_r0[50];
+assign K2[45] = decrypt ? K_r0[30] : K_r0[51];
+assign K2[46] = decrypt ? K_r0[42] : K_r0[8];
+assign K2[47] = decrypt ? K_r0[52] : K_r0[14];
+assign K2[48] = decrypt ? K_r0[14] : K_r0[35];
+
+assign K1[1] = decrypt ? K[40] : K[47];
+assign K1[2] = decrypt ? K[4] : K[11];
+assign K1[3] = decrypt ? K[19] : K[26];
+assign K1[4] = decrypt ? K[53] : K[3];
+assign K1[5] = decrypt ? K[6] : K[13];
+assign K1[6] = decrypt ? K[34] : K[41];
+assign K1[7] = decrypt ? K[20] : K[27];
+assign K1[8] = decrypt ? K[24] : K[6];
+assign K1[9] = decrypt ? K[47] : K[54];
+assign K1[10] = decrypt ? K[41] : K[48];
+assign K1[11] = decrypt ? K[32] : K[39];
+assign K1[12] = decrypt ? K[12] : K[19];
+assign K1[13] = decrypt ? K[46] : K[53];
+assign K1[14] = decrypt ? K[18] : K[25];
+assign K1[15] = decrypt ? K[26] : K[33];
+assign K1[16] = decrypt ? K[27] : K[34];
+assign K1[17] = decrypt ? K[10] : K[17];
+assign K1[18] = decrypt ? K[55] : K[5];
+assign K1[19] = decrypt ? K[54] : K[4];
+assign K1[20] = decrypt ? K[48] : K[55];
+assign K1[21] = decrypt ? K[17] : K[24];
+assign K1[22] = decrypt ? K[25] : K[32];
+assign K1[23] = decrypt ? K[33] : K[40];
+assign K1[24] = decrypt ? K[13] : K[20];
+assign K1[25] = decrypt ? K[29] : K[36];
+assign K1[26] = decrypt ? K[51] : K[31];
+assign K1[27] = decrypt ? K[14] : K[21];
+assign K1[28] = decrypt ? K[1] : K[8];
+assign K1[29] = decrypt ? K[16] : K[23];
+assign K1[30] = decrypt ? K[45] : K[52];
+assign K1[31] = decrypt ? K[7] : K[14];
+assign K1[32] = decrypt ? K[22] : K[29];
+assign K1[33] = decrypt ? K[44] : K[51];
+assign K1[34] = decrypt ? K[2] : K[9];
+assign K1[35] = decrypt ? K[28] : K[35];
+assign K1[36] = decrypt ? K[23] : K[30];
+assign K1[37] = decrypt ? K[50] : K[2];
+assign K1[38] = decrypt ? K[30] : K[37];
+assign K1[39] = decrypt ? K[15] : K[22];
+assign K1[40] = decrypt ? K[52] : K[0];
+assign K1[41] = decrypt ? K[35] : K[42];
+assign K1[42] = decrypt ? K[31] : K[38];
+assign K1[43] = decrypt ? K[9] : K[16];
+assign K1[44] = decrypt ? K[36] : K[43];
+assign K1[45] = decrypt ? K[37] : K[44];
+assign K1[46] = decrypt ? K[49] : K[1];
+assign K1[47] = decrypt ? K[0] : K[7];
+assign K1[48] = decrypt ? K[21] : K[28];
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  CRP                                                        ////
+////  DES Crypt Module                                           ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module  crp(P, R, K_sub);
+output	[1:32]	P;
+input	[1:32]	R;
+input	[1:48]	K_sub;
+
+wire	[1:48] E;
+wire	[1:48] X;
+wire	[1:32] S;
+
+assign E[1:48] = {	R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5],
+			R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11],
+			R[12], R[13], R[12], R[13], R[14], R[15], R[16],
+			R[17], R[16], R[17], R[18], R[19], R[20], R[21],
+			R[20], R[21], R[22], R[23], R[24], R[25], R[24],
+			R[25], R[26], R[27], R[28], R[29], R[28], R[29],
+			R[30], R[31], R[32], R[1]};
+
+assign X = E ^ K_sub;
+
+sbox1 u0( .addr(X[01:06]), .dout(S[01:04]) );
+sbox2 u1( .addr(X[07:12]), .dout(S[05:08]) );
+sbox3 u2( .addr(X[13:18]), .dout(S[09:12]) );
+sbox4 u3( .addr(X[19:24]), .dout(S[13:16]) );
+sbox5 u4( .addr(X[25:30]), .dout(S[17:20]) );
+sbox6 u5( .addr(X[31:36]), .dout(S[21:24]) );
+sbox7 u6( .addr(X[37:42]), .dout(S[25:28]) );
+sbox8 u7( .addr(X[43:48]), .dout(S[29:32]) );
+
+assign P[1:32] = {	S[16], S[7], S[20], S[21], S[29], S[12], S[28],
+			S[17], S[1], S[15], S[23], S[26], S[5], S[18],
+			S[31], S[10], S[2], S[8], S[24], S[14], S[32],
+			S[27], S[3], S[9], S[19], S[13], S[30], S[6],
+			S[22], S[11], S[4], S[25]};
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SBOX                                                       ////
+////  The SBOX is essentially a 64x4 ROM                         ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module  sbox1(addr, dout);
+input	[1:6] addr;
+output	[1:4] dout;
+reg	[1:4] dout;
+
+always @(addr) begin
+    case ({addr[1], addr[6], addr[2:5]})	//synopsys full_case parallel_case
+         0:  dout =  14;
+         1:  dout =   4;
+         2:  dout =  13;
+         3:  dout =   1;
+         4:  dout =   2;
+         5:  dout =  15;
+         6:  dout =  11;
+         7:  dout =   8;
+         8:  dout =   3;
+         9:  dout =  10;
+        10:  dout =   6;
+        11:  dout =  12;
+        12:  dout =   5;
+        13:  dout =   9;
+        14:  dout =   0;
+        15:  dout =   7;
+
+        16:  dout =   0;
+        17:  dout =  15;
+        18:  dout =   7;
+        19:  dout =   4;
+        20:  dout =  14;
+        21:  dout =   2;
+        22:  dout =  13;
+        23:  dout =   1;
+        24:  dout =  10;
+        25:  dout =   6;
+        26:  dout =  12;
+        27:  dout =  11;
+        28:  dout =   9;
+        29:  dout =   5;
+        30:  dout =   3;
+        31:  dout =   8;
+
+        32:  dout =   4;
+        33:  dout =   1;
+        34:  dout =  14;
+        35:  dout =   8;
+        36:  dout =  13;
+        37:  dout =   6;
+        38:  dout =   2;
+        39:  dout =  11;
+        40:  dout =  15;
+        41:  dout =  12;
+        42:  dout =   9;
+        43:  dout =   7;
+        44:  dout =   3;
+        45:  dout =  10;
+        46:  dout =   5;
+        47:  dout =   0;
+
+        48:  dout =  15;
+        49:  dout =  12;
+        50:  dout =   8;
+        51:  dout =   2;
+        52:  dout =   4;
+        53:  dout =   9;
+        54:  dout =   1;
+        55:  dout =   7;
+        56:  dout =   5;
+        57:  dout =  11;
+        58:  dout =   3;
+        59:  dout =  14;
+        60:  dout =  10;
+        61:  dout =   0;
+        62:  dout =   6;
+        63:  dout =  13;
+
+    endcase
+    end
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SBOX                                                       ////
+////  The SBOX is essentially a 64x4 ROM                         ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module  sbox2(addr, dout);
+input	[1:6] addr;
+output	[1:4] dout;
+reg	[1:4] dout;
+
+always @(addr) begin
+    case ({addr[1], addr[6], addr[2:5]})	//synopsys full_case parallel_case
+         0:  dout = 15;
+         1:  dout =  1;
+         2:  dout =  8;
+         3:  dout = 14;
+         4:  dout =  6;
+         5:  dout = 11;
+         6:  dout =  3;
+         7:  dout =  4;
+         8:  dout =  9;
+         9:  dout =  7;
+        10:  dout =  2;
+        11:  dout = 13;
+        12:  dout = 12;
+        13:  dout =  0;
+        14:  dout =  5;
+        15:  dout = 10;
+
+        16:  dout =  3;
+        17:  dout = 13;
+        18:  dout =  4;
+        19:  dout =  7;
+        20:  dout = 15;
+        21:  dout =  2;
+        22:  dout =  8;
+        23:  dout = 14;
+        24:  dout = 12;
+        25:  dout =  0;
+        26:  dout =  1;
+        27:  dout = 10;
+        28:  dout =  6;
+        29:  dout =  9;
+        30:  dout = 11;
+        31:  dout =  5;
+
+        32:  dout =  0;
+        33:  dout = 14;
+        34:  dout =  7;
+        35:  dout = 11;
+        36:  dout = 10;
+        37:  dout =  4;
+        38:  dout = 13;
+        39:  dout =  1;
+        40:  dout =  5;
+        41:  dout =  8;
+        42:  dout = 12;
+        43:  dout =  6;
+        44:  dout =  9;
+        45:  dout =  3;
+        46:  dout =  2;
+        47:  dout = 15;
+
+        48:  dout = 13;
+        49:  dout =  8;
+        50:  dout = 10;
+        51:  dout =  1;
+        52:  dout =  3;
+        53:  dout = 15;
+        54:  dout =  4;
+        55:  dout =  2;
+        56:  dout = 11;
+        57:  dout =  6;
+        58:  dout =  7;
+        59:  dout = 12;
+        60:  dout =  0;
+        61:  dout =  5;
+        62:  dout = 14;
+        63:  dout =  9;
+
+    endcase
+    end
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SBOX                                                       ////
+////  The SBOX is essentially a 64x4 ROM                         ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module  sbox3(addr, dout);
+input	[1:6] addr;
+output	[1:4] dout;
+reg	[1:4] dout;
+
+always @(addr) begin
+    case ({addr[1], addr[6], addr[2:5]})	//synopsys full_case parallel_case
+         0:  dout = 10;
+         1:  dout =  0;
+         2:  dout =  9;
+         3:  dout = 14;
+         4:  dout =  6;
+         5:  dout =  3;
+         6:  dout = 15;
+         7:  dout =  5;
+         8:  dout =  1;
+         9:  dout = 13;
+        10:  dout = 12;
+        11:  dout =  7;
+        12:  dout = 11;
+        13:  dout =  4;
+        14:  dout =  2;
+        15:  dout =  8;
+
+        16:  dout = 13;
+        17:  dout =  7;
+        18:  dout =  0;
+        19:  dout =  9;
+        20:  dout =  3;
+        21:  dout =  4;
+        22:  dout =  6;
+        23:  dout = 10;
+        24:  dout =  2;
+        25:  dout =  8;
+        26:  dout =  5;
+        27:  dout = 14;
+        28:  dout = 12;
+        29:  dout = 11;
+        30:  dout = 15;
+        31:  dout =  1;
+
+        32:  dout = 13;
+        33:  dout =  6;
+        34:  dout =  4;
+        35:  dout =  9;
+        36:  dout =  8;
+        37:  dout = 15;
+        38:  dout =  3;
+        39:  dout =  0;
+        40:  dout = 11;
+        41:  dout =  1;
+        42:  dout =  2;
+        43:  dout = 12;
+        44:  dout =  5;
+        45:  dout = 10;
+        46:  dout = 14;
+        47:  dout =  7;
+
+        48:  dout =  1;
+        49:  dout = 10;
+        50:  dout = 13;
+        51:  dout =  0;
+        52:  dout =  6;
+        53:  dout =  9;
+        54:  dout =  8;
+        55:  dout =  7;
+        56:  dout =  4;
+        57:  dout = 15;
+        58:  dout = 14;
+        59:  dout =  3;
+        60:  dout = 11;
+        61:  dout =  5;
+        62:  dout =  2;
+        63:  dout = 12;
+
+    endcase
+    end
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SBOX                                                       ////
+////  The SBOX is essentially a 64x4 ROM                         ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module  sbox4(addr, dout);
+input	[1:6] addr;
+output	[1:4] dout;
+reg	[1:4] dout;
+
+always @(addr) begin
+    case ({addr[1], addr[6], addr[2:5]})	//synopsys full_case parallel_case
+         0:  dout =  7;
+         1:  dout = 13;
+         2:  dout = 14;
+         3:  dout =  3;
+         4:  dout =  0;
+         5:  dout =  6;
+         6:  dout =  9;
+         7:  dout = 10;
+         8:  dout =  1;
+         9:  dout =  2;
+        10:  dout =  8;
+        11:  dout =  5;
+        12:  dout = 11;
+        13:  dout = 12;
+        14:  dout =  4;
+        15:  dout = 15;
+
+        16:  dout = 13;
+        17:  dout =  8;
+        18:  dout = 11;
+        19:  dout =  5;
+        20:  dout =  6;
+        21:  dout = 15;
+        22:  dout =  0;
+        23:  dout =  3;
+        24:  dout =  4;
+        25:  dout =  7;
+        26:  dout =  2;
+        27:  dout = 12;
+        28:  dout =  1;
+        29:  dout = 10;
+        30:  dout = 14;
+        31:  dout =  9;
+
+        32:  dout = 10;
+        33:  dout =  6;
+        34:  dout =  9;
+        35:  dout =  0;
+        36:  dout = 12;
+        37:  dout = 11;
+        38:  dout =  7;
+        39:  dout = 13;
+        40:  dout = 15;
+        41:  dout =  1;
+        42:  dout =  3;
+        43:  dout = 14;
+        44:  dout =  5;
+        45:  dout =  2;
+        46:  dout =  8;
+        47:  dout =  4;
+
+        48:  dout =  3;
+        49:  dout = 15;
+        50:  dout =  0;
+        51:  dout =  6;
+        52:  dout = 10;
+        53:  dout =  1;
+        54:  dout = 13;
+        55:  dout =  8;
+        56:  dout =  9;
+        57:  dout =  4;
+        58:  dout =  5;
+        59:  dout = 11;
+        60:  dout = 12;
+        61:  dout =  7;
+        62:  dout =  2;
+        63:  dout = 14;
+
+    endcase
+    end
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SBOX                                                       ////
+////  The SBOX is essentially a 64x4 ROM                         ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module  sbox5(addr, dout);
+input	[1:6] addr;
+output	[1:4] dout;
+reg	[1:4] dout;
+
+always @(addr) begin
+    case ({addr[1], addr[6], addr[2:5]})	//synopsys full_case parallel_case
+         0:  dout =  2;
+         1:  dout = 12;
+         2:  dout =  4;
+         3:  dout =  1;
+         4:  dout =  7;
+         5:  dout = 10;
+         6:  dout = 11;
+         7:  dout =  6;
+         8:  dout =  8;
+         9:  dout =  5;
+        10:  dout =  3;
+        11:  dout = 15;
+        12:  dout = 13;
+        13:  dout =  0;
+        14:  dout = 14;
+        15:  dout =  9;
+
+        16:  dout = 14;
+        17:  dout = 11;
+        18:  dout =  2;
+        19:  dout = 12;
+        20:  dout =  4;
+        21:  dout =  7;
+        22:  dout = 13;
+        23:  dout =  1;
+        24:  dout =  5;
+        25:  dout =  0;
+        26:  dout = 15;
+        27:  dout = 10;
+        28:  dout =  3;
+        29:  dout =  9;
+        30:  dout =  8;
+        31:  dout =  6;
+
+        32:  dout =  4;
+        33:  dout =  2;
+        34:  dout =  1;
+        35:  dout = 11;
+        36:  dout = 10;
+        37:  dout = 13;
+        38:  dout =  7;
+        39:  dout =  8;
+        40:  dout = 15;
+        41:  dout =  9;
+        42:  dout = 12;
+        43:  dout =  5;
+        44:  dout =  6;
+        45:  dout =  3;
+        46:  dout =  0;
+        47:  dout = 14;
+
+        48:  dout = 11;
+        49:  dout =  8;
+        50:  dout = 12;
+        51:  dout =  7;
+        52:  dout =  1;
+        53:  dout = 14;
+        54:  dout =  2;
+        55:  dout = 13;
+        56:  dout =  6;
+        57:  dout = 15;
+        58:  dout =  0;
+        59:  dout =  9;
+        60:  dout = 10;
+        61:  dout =  4;
+        62:  dout =  5;
+        63:  dout =  3;
+
+    endcase
+    end
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SBOX                                                       ////
+////  The SBOX is essentially a 64x4 ROM                         ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module  sbox6(addr, dout);
+input	[1:6] addr;
+output	[1:4] dout;
+reg	[1:4] dout;
+
+always @(addr) begin
+    case ({addr[1], addr[6], addr[2:5]})	//synopsys full_case parallel_case
+         0:  dout = 12;
+         1:  dout =  1;
+         2:  dout = 10;
+         3:  dout = 15;
+         4:  dout =  9;
+         5:  dout =  2;
+         6:  dout =  6;
+         7:  dout =  8;
+         8:  dout =  0;
+         9:  dout = 13;
+        10:  dout =  3;
+        11:  dout =  4;
+        12:  dout = 14;
+        13:  dout =  7;
+        14:  dout =  5;
+        15:  dout = 11;
+
+        16:  dout = 10;
+        17:  dout = 15;
+        18:  dout =  4;
+        19:  dout =  2;
+        20:  dout =  7;
+        21:  dout = 12;
+        22:  dout =  9;
+        23:  dout =  5;
+        24:  dout =  6;
+        25:  dout =  1;
+        26:  dout = 13;
+        27:  dout = 14;
+        28:  dout =  0;
+        29:  dout = 11;
+        30:  dout =  3;
+        31:  dout =  8;
+
+        32:  dout =  9;
+        33:  dout = 14;
+        34:  dout = 15;
+        35:  dout =  5;
+        36:  dout =  2;
+        37:  dout =  8;
+        38:  dout = 12;
+        39:  dout =  3;
+        40:  dout =  7;
+        41:  dout =  0;
+        42:  dout =  4;
+        43:  dout = 10;
+        44:  dout =  1;
+        45:  dout = 13;
+        46:  dout = 11;
+        47:  dout =  6;
+
+        48:  dout =  4;
+        49:  dout =  3;
+        50:  dout =  2;
+        51:  dout = 12;
+        52:  dout =  9;
+        53:  dout =  5;
+        54:  dout = 15;
+        55:  dout = 10;
+        56:  dout = 11;
+        57:  dout = 14;
+        58:  dout =  1;
+        59:  dout =  7;
+        60:  dout =  6;
+        61:  dout =  0;
+        62:  dout =  8;
+        63:  dout = 13;
+
+    endcase
+    end
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SBOX                                                       ////
+////  The SBOX is essentially a 64x4 ROM                         ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module  sbox7(addr, dout);
+input	[1:6] addr;
+output	[1:4] dout;
+reg	[1:4] dout;
+
+always @(addr) begin
+    case ({addr[1], addr[6], addr[2:5]})	//synopsys full_case parallel_case
+         0:  dout =  4;
+         1:  dout = 11;
+         2:  dout =  2;
+         3:  dout = 14;
+         4:  dout = 15;
+         5:  dout =  0;
+         6:  dout =  8;
+         7:  dout = 13;
+         8:  dout =  3;
+         9:  dout = 12;
+        10:  dout =  9;
+        11:  dout =  7;
+        12:  dout =  5;
+        13:  dout = 10;
+        14:  dout =  6;
+        15:  dout =  1;
+
+        16:  dout = 13;
+        17:  dout =  0;
+        18:  dout = 11;
+        19:  dout =  7;
+        20:  dout =  4;
+        21:  dout =  9;
+        22:  dout =  1;
+        23:  dout = 10;
+        24:  dout = 14;
+        25:  dout =  3;
+        26:  dout =  5;
+        27:  dout = 12;
+        28:  dout =  2;
+        29:  dout = 15;
+        30:  dout =  8;
+        31:  dout =  6;
+
+        32:  dout =  1;
+        33:  dout =  4;
+        34:  dout = 11;
+        35:  dout = 13;
+        36:  dout = 12;
+        37:  dout =  3;
+        38:  dout =  7;
+        39:  dout = 14;
+        40:  dout = 10;
+        41:  dout = 15;
+        42:  dout =  6;
+        43:  dout =  8;
+        44:  dout =  0;
+        45:  dout =  5;
+        46:  dout =  9;
+        47:  dout =  2;
+
+        48:  dout =  6;
+        49:  dout = 11;
+        50:  dout = 13;
+        51:  dout =  8;
+        52:  dout =  1;
+        53:  dout =  4;
+        54:  dout = 10;
+        55:  dout =  7;
+        56:  dout =  9;
+        57:  dout =  5;
+        58:  dout =  0;
+        59:  dout = 15;
+        60:  dout = 14;
+        61:  dout =  2;
+        62:  dout =  3;
+        63:  dout = 12;
+
+    endcase
+    end
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SBOX                                                       ////
+////  The SBOX is essentially a 64x4 ROM                         ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Rudolf Usselmann                         ////
+////                    rudi@asics.ws                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+module  sbox8(addr, dout);
+input	[1:6] addr;
+output	[1:4] dout;
+reg	[1:4] dout;
+
+always @(addr) begin
+    case ({addr[1], addr[6], addr[2:5]})	//synopsys full_case parallel_case
+         0:  dout = 13;
+         1:  dout =  2;
+         2:  dout =  8;
+         3:  dout =  4;
+         4:  dout =  6;
+         5:  dout = 15;
+         6:  dout = 11;
+         7:  dout =  1;
+         8:  dout = 10;
+         9:  dout =  9;
+        10:  dout =  3;
+        11:  dout = 14;
+        12:  dout =  5;
+        13:  dout =  0;
+        14:  dout = 12;
+        15:  dout =  7;
+
+        16:  dout =  1;
+        17:  dout = 15;
+        18:  dout = 13;
+        19:  dout =  8;
+        20:  dout = 10;
+        21:  dout =  3;
+        22:  dout =  7;
+        23:  dout =  4;
+        24:  dout = 12;
+        25:  dout =  5;
+        26:  dout =  6;
+        27:  dout = 11;
+        28:  dout =  0;
+        29:  dout = 14;
+        30:  dout =  9;
+        31:  dout =  2;
+
+        32:  dout =  7;
+        33:  dout = 11;
+        34:  dout =  4;
+        35:  dout =  1;
+        36:  dout =  9;
+        37:  dout = 12;
+        38:  dout = 14;
+        39:  dout =  2;
+        40:  dout =  0;
+        41:  dout =  6;
+        42:  dout = 10;
+        43:  dout = 13;
+        44:  dout = 15;
+        45:  dout =  3;
+        46:  dout =  5;
+        47:  dout =  8;
+
+        48:  dout =  2;
+        49:  dout =  1;
+        50:  dout = 14;
+        51:  dout =  7;
+        52:  dout =  4;
+        53:  dout = 10;
+        54:  dout =  8;
+        55:  dout = 13;
+        56:  dout = 15;
+        57:  dout = 12;
+        58:  dout =  9;
+        59:  dout =  0;
+        60:  dout =  3;
+        61:  dout =  5;
+        62:  dout =  6;
+        63:  dout = 11;
+
+    endcase
+    end
+
+endmodule
diff --git a/BENCHMARK/diffeq_f_systemC/diffeq_f_systemC_yosys.blif b/BENCHMARK/diffeq_f_systemC/diffeq_f_systemC_yosys.blif
new file mode 100644
index 0000000..53eeb30
--- /dev/null
+++ b/BENCHMARK/diffeq_f_systemC/diffeq_f_systemC_yosys.blif
@@ -0,0 +1,24635 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model diffeq_f_systemC
+.inputs aport(0) aport(1) aport(2) aport(3) aport(4) aport(5) aport(6) aport(7) aport(8) aport(9) aport(10) aport(11) aport(12) aport(13) aport(14) aport(15) aport(16) aport(17) aport(18) aport(19) aport(20) aport(21) aport(22) aport(23) aport(24) aport(25) aport(26) aport(27) aport(28) aport(29) aport(30) aport(31) dxport(0) dxport(1) dxport(2) dxport(3) dxport(4) dxport(5) dxport(6) dxport(7) dxport(8) dxport(9) dxport(10) dxport(11) dxport(12) dxport(13) dxport(14) dxport(15) dxport(16) dxport(17) dxport(18) dxport(19) dxport(20) dxport(21) dxport(22) dxport(23) dxport(24) dxport(25) dxport(26) dxport(27) dxport(28) dxport(29) dxport(30) dxport(31) clk reset
+.outputs xport(0) xport(1) xport(2) xport(3) xport(4) xport(5) xport(6) xport(7) xport(8) xport(9) xport(10) xport(11) xport(12) xport(13) xport(14) xport(15) xport(16) xport(17) xport(18) xport(19) xport(20) xport(21) xport(22) xport(23) xport(24) xport(25) xport(26) xport(27) xport(28) xport(29) xport(30) xport(31) yport(0) yport(1) yport(2) yport(3) yport(4) yport(5) yport(6) yport(7) yport(8) yport(9) yport(10) yport(11) yport(12) yport(13) yport(14) yport(15) yport(16) yport(17) yport(18) yport(19) yport(20) yport(21) yport(22) yport(23) yport(24) yport(25) yport(26) yport(27) yport(28) yport(29) yport(30) yport(31) uport(0) uport(1) uport(2) uport(3) uport(4) uport(5) uport(6) uport(7) uport(8) uport(9) uport(10) uport(11) uport(12) uport(13) uport(14) uport(15) uport(16) uport(17) uport(18) uport(19) uport(20) uport(21) uport(22) uport(23) uport(24) uport(25) uport(26) uport(27) uport(28) uport(29) uport(30) uport(31)
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_0 a=$auto$hilomap.cc:47:hilomap_worker$35946
+.subckt in_buff A=aport(0) Q=$iopadmap$aport(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(1) Q=$iopadmap$aport(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(10) Q=$iopadmap$aport(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(11) Q=$iopadmap$aport(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(12) Q=$iopadmap$aport(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(13) Q=$iopadmap$aport(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(14) Q=$iopadmap$aport(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(15) Q=$iopadmap$aport(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(16) Q=$iopadmap$aport(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(17) Q=$iopadmap$aport(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(18) Q=$iopadmap$aport(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(19) Q=$iopadmap$aport(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(2) Q=$iopadmap$aport(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(20) Q=$iopadmap$aport(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(21) Q=$iopadmap$aport(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(22) Q=$iopadmap$aport(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(23) Q=$iopadmap$aport(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(24) Q=$iopadmap$aport(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(25) Q=$iopadmap$aport(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(26) Q=$iopadmap$aport(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(27) Q=$iopadmap$aport(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(28) Q=$iopadmap$aport(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(29) Q=$iopadmap$aport(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(3) Q=$iopadmap$aport(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(30) Q=$iopadmap$aport(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(31) Q=$iopadmap$aport(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(4) Q=$iopadmap$aport(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(5) Q=$iopadmap$aport(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(6) Q=$iopadmap$aport(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(7) Q=$iopadmap$aport(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(8) Q=$iopadmap$aport(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=aport(9) Q=$iopadmap$aport(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=clk Q=$iopadmap$clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(0) Q=$iopadmap$dxport(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(1) Q=$iopadmap$dxport(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(10) Q=$iopadmap$dxport(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(11) Q=$iopadmap$dxport(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(12) Q=$iopadmap$dxport(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(13) Q=$iopadmap$dxport(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(14) Q=$iopadmap$dxport(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(15) Q=$iopadmap$dxport(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(16) Q=$iopadmap$dxport(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(17) Q=$iopadmap$dxport(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(18) Q=$iopadmap$dxport(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(19) Q=$iopadmap$dxport(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(2) Q=$iopadmap$dxport(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(20) Q=$iopadmap$dxport(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(21) Q=$iopadmap$dxport(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(22) Q=$iopadmap$dxport(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(23) Q=$iopadmap$dxport(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(24) Q=$iopadmap$dxport(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(25) Q=$iopadmap$dxport(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(26) Q=$iopadmap$dxport(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(27) Q=$iopadmap$dxport(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(28) Q=$iopadmap$dxport(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(29) Q=$iopadmap$dxport(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(3) Q=$iopadmap$dxport(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(30) Q=$iopadmap$dxport(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(31) Q=$iopadmap$dxport(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(4) Q=$iopadmap$dxport(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(5) Q=$iopadmap$dxport(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(6) Q=$iopadmap$dxport(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(7) Q=$iopadmap$dxport(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(8) Q=$iopadmap$dxport(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=dxport(9) Q=$iopadmap$dxport(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=reset Q=$iopadmap$reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=$iopadmap$uport(0) Q=uport(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(1) Q=uport(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(10) Q=uport(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(11) Q=uport(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(12) Q=uport(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(13) Q=uport(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(14) Q=uport(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(15) Q=uport(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(16) Q=uport(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(17) Q=uport(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$uport(18) Q=uport(18)
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt out_buff A=$iopadmap$yport(3) Q=yport(3)
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+.subckt out_buff A=$iopadmap$yport(30) Q=yport(30)
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+.subckt out_buff A=$iopadmap$yport(4) Q=yport(4)
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+.subckt out_buff A=$iopadmap$yport(5) Q=yport(5)
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+.subckt out_buff A=$iopadmap$yport(6) Q=yport(6)
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+.subckt out_buff A=$iopadmap$yport(7) Q=yport(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$yport(8) Q=yport(8)
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+.subckt out_buff A=$iopadmap$yport(9) Q=yport(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt LUT4 I0=$iopadmap$aport(17) I1=$iopadmap$xport(17) I2=$iopadmap$xport(18) I3=$iopadmap$aport(18) O=aport_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000001011
+.subckt LUT4 I0=$iopadmap$aport(21) I1=$iopadmap$xport(21) I2=$iopadmap$xport(22) I3=$iopadmap$aport(22) O=aport_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000001011
+.subckt LUT4 I0=$iopadmap$aport(13) I1=$iopadmap$xport(13) I2=$iopadmap$xport(15) I3=$iopadmap$aport(15) O=aport_LUT4_I0_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000001011
+.subckt LUT4 I0=$iopadmap$aport(5) I1=$iopadmap$xport(5) I2=$iopadmap$xport(6) I3=$iopadmap$aport(6) O=aport_LUT4_I0_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000001011
+.subckt LUT4 I0=$iopadmap$xport(0) I1=$iopadmap$aport(0) I2=$iopadmap$xport(1) I3=$iopadmap$aport(1) O=aport_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=$iopadmap$xport(24) I1=$iopadmap$aport(24) I2=$iopadmap$xport(25) I3=$iopadmap$aport(25) O=aport_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=$iopadmap$xport(12) I1=$iopadmap$aport(12) I2=$iopadmap$xport(13) I3=$iopadmap$aport(13) O=aport_LUT4_I1_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=$iopadmap$xport(12) I1=$iopadmap$aport(12) I2=aport_LUT4_I2_12_O I3=aport_LUT4_I1_10_O O=aport_LUT4_I1_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=aport_LUT4_I2_14_O_LUT4_I0_O I1=aport_LUT4_I1_8_O_LUT4_I2_O I2=aport_LUT4_I2_10_O_LUT4_I1_O I3=aport_LUT4_I1_11_O O=aport_LUT4_I1_11_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=$iopadmap$xport(2) I1=$iopadmap$aport(2) I2=$iopadmap$xport(3) I3=$iopadmap$aport(3) O=aport_LUT4_I1_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=$iopadmap$xport(4) I1=$iopadmap$aport(4) I2=$iopadmap$xport(5) I3=$iopadmap$aport(5) O=aport_LUT4_I1_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=$iopadmap$xport(4) I1=$iopadmap$aport(4) I2=aport_LUT4_I2_16_O I3=aport_LUT4_I1_13_O O=aport_LUT4_I1_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=aport_LUT4_I1_14_O I3=aport_LUT4_I1_O_LUT4_I3_O O=aport_LUT4_I1_14_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=aport_LUT4_I1_1_O I2=aport_LUT4_I1_2_O I3=aport_LUT4_I1_3_O_LUT4_I2_O O=aport_LUT4_I1_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$iopadmap$xport(26) I1=$iopadmap$aport(26) I2=$iopadmap$xport(27) I3=$iopadmap$aport(27) O=aport_LUT4_I1_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=$iopadmap$xport(28) I1=$iopadmap$aport(28) I2=$iopadmap$xport(29) I3=$iopadmap$aport(29) O=aport_LUT4_I1_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=aport_LUT4_I1_3_O I3=aport_LUT4_I1_4_O O=aport_LUT4_I1_3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$xport(30) I1=$iopadmap$aport(30) I2=$iopadmap$xport(31) I3=$iopadmap$aport(31) O=aport_LUT4_I1_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=$iopadmap$xport(16) I1=$iopadmap$aport(16) I2=$iopadmap$xport(17) I3=$iopadmap$aport(17) O=aport_LUT4_I1_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=$iopadmap$xport(20) I1=$iopadmap$aport(20) I2=$iopadmap$xport(21) I3=$iopadmap$aport(21) O=aport_LUT4_I1_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=$iopadmap$xport(20) I1=$iopadmap$aport(20) I2=aport_LUT4_I2_8_O I3=aport_LUT4_I1_6_O O=aport_LUT4_I1_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=$iopadmap$xport(8) I1=$iopadmap$aport(8) I2=$iopadmap$xport(9) I3=$iopadmap$aport(9) O=aport_LUT4_I1_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=aport_LUT4_I1_8_O I3=aport_LUT4_I1_9_O O=aport_LUT4_I1_8_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$xport(10) I1=$iopadmap$aport(10) I2=$iopadmap$xport(11) I3=$iopadmap$aport(11) O=aport_LUT4_I1_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=aport_LUT4_I1_11_O I1=aport_LUT4_I1_8_O_LUT4_I2_O I2=aport_LUT4_I1_12_O I3=aport_LUT4_I1_O O=aport_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=aport_LUT4_I1_5_O I2=$iopadmap$aport(16) I3=$iopadmap$xport(16) O=aport_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=$iopadmap$xport(31) I1=$iopadmap$xport(30) I2=$iopadmap$aport(31) I3=$iopadmap$aport(30) O=aport_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=$iopadmap$xport(11) I1=$iopadmap$xport(10) I2=$iopadmap$aport(11) I3=$iopadmap$aport(10) O=aport_LUT4_I2_10_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=aport_LUT4_I2_10_O I2=aport_LUT4_I2_11_O I3=aport_LUT4_I1_9_O O=aport_LUT4_I2_10_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=$iopadmap$xport(9) I1=$iopadmap$xport(8) I2=$iopadmap$aport(9) I3=$iopadmap$aport(8) O=aport_LUT4_I2_11_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000101010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=aport_LUT4_I0_2_O I2=$iopadmap$aport(14) I3=$iopadmap$xport(14) O=aport_LUT4_I2_12_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$iopadmap$xport(3) I1=$iopadmap$xport(2) I2=$iopadmap$aport(3) I3=$iopadmap$aport(2) O=aport_LUT4_I2_13_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=aport_LUT4_I3_O I1=$iopadmap$xport(1) I2=$iopadmap$aport(1) I3=aport_LUT4_I1_12_O O=aport_LUT4_I2_14_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100000000
+.subckt LUT4 I0=aport_LUT4_I2_14_O I1=aport_LUT4_I2_13_O I2=aport_LUT4_I1_14_O I3=aport_LUT4_I2_15_O_LUT4_I1_O O=aport_LUT4_I2_14_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=$iopadmap$xport(7) I1=$iopadmap$xport(6) I2=$iopadmap$aport(7) I3=$iopadmap$aport(6) O=aport_LUT4_I2_15_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=aport_LUT4_I2_15_O I2=aport_LUT4_I1_13_O I3=aport_LUT4_I2_16_O O=aport_LUT4_I2_15_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=aport_LUT4_I0_3_O I2=$iopadmap$aport(7) I3=$iopadmap$xport(7) O=aport_LUT4_I2_16_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=aport_LUT4_I2_1_O I2=aport_LUT4_I2_2_O I3=aport_LUT4_I1_4_O O=aport_LUT4_I2_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=$iopadmap$xport(29) I1=$iopadmap$xport(28) I2=$iopadmap$aport(29) I3=$iopadmap$aport(28) O=aport_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=$iopadmap$xport(27) I1=$iopadmap$xport(26) I2=$iopadmap$aport(27) I3=$iopadmap$aport(26) O=aport_LUT4_I2_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=$iopadmap$xport(25) I1=$iopadmap$xport(24) I2=$iopadmap$aport(25) I3=$iopadmap$aport(24) O=aport_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=aport_LUT4_I2_4_O I1=aport_LUT4_I1_2_O I2=aport_LUT4_I2_3_O I3=aport_LUT4_I1_3_O_LUT4_I2_O O=aport_LUT4_I2_4_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=$iopadmap$xport(23) I1=$iopadmap$xport(22) I2=$iopadmap$aport(23) I3=$iopadmap$aport(22) O=aport_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=aport_LUT4_I2_8_O I1=aport_LUT4_I1_6_O I2=aport_LUT4_I2_6_O_LUT4_I2_O I3=aport_LUT4_I2_5_O O=aport_LUT4_I2_5_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=aport_LUT4_I2_5_O_LUT4_I3_O I1=aport_LUT4_I1_1_O_LUT4_I1_O I2=aport_LUT4_I2_4_O_LUT4_I0_O I3=aport_LUT4_I2_1_O_LUT4_I1_O O=reset_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=$iopadmap$xport(19) I1=$iopadmap$xport(18) I2=$iopadmap$aport(19) I3=$iopadmap$aport(18) O=aport_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=aport_LUT4_I1_5_O I1=aport_LUT4_I2_7_O I2=aport_LUT4_I2_6_O I3=aport_LUT4_I1_7_O O=aport_LUT4_I2_6_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=aport_LUT4_I0_O I2=$iopadmap$aport(19) I3=$iopadmap$xport(19) O=aport_LUT4_I2_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=aport_LUT4_I0_1_O I2=$iopadmap$aport(23) I3=$iopadmap$xport(23) O=aport_LUT4_I2_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$iopadmap$xport(15) I1=$iopadmap$xport(14) I2=$iopadmap$aport(15) I3=$iopadmap$aport(14) O=aport_LUT4_I2_9_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=aport_LUT4_I2_12_O I1=aport_LUT4_I1_10_O I2=aport_LUT4_I1_11_O_LUT4_I3_O I3=aport_LUT4_I2_9_O O=aport_LUT4_I2_9_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=aport_LUT4_I1_7_O I1=aport_LUT4_I1_1_O_LUT4_I1_O I2=aport_LUT4_I2_7_O I3=aport_LUT4_I2_O O=aport_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(0) I3=$iopadmap$aport(0) O=aport_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_I1 I2=$iopadmap$xport(14) I3=$iopadmap$dxport(14) O=xport_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_1_I1 I2=$iopadmap$xport(13) I3=$iopadmap$dxport(13) O=xport_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_10_I1 I2=$iopadmap$xport(4) I3=$iopadmap$dxport(4) O=xport_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(3) I2=$iopadmap$xport(3) I3=reset_LUT4_I0_11_I1 O=reset_LUT4_I0_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_11_I1 I2=$iopadmap$xport(3) I3=$iopadmap$dxport(3) O=xport_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(2) I2=$iopadmap$xport(2) I3=reset_LUT4_I0_12_I1 O=reset_LUT4_I0_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_12_I1 I2=$iopadmap$xport(2) I3=$iopadmap$dxport(2) O=xport_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$iopadmap$xport(1) I1=$iopadmap$dxport(1) I2=$iopadmap$dxport(0) I3=$iopadmap$xport(0) O=reset_LUT4_I0_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_13_I1 I2=reset_LUT4_I0_13_I2 I3=$iopadmap$yport(31) O=yport_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2 I1=$iopadmap$yport(30) I2=reset_LUT4_I2_2_I3_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I0 O=reset_LUT4_I0_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1 I2=$iopadmap$xport(0) I3=reset_LUT4_I0_13_I2 O=reset_LUT4_I0_13_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$uport(26) I2=$iopadmap$dxport(26) I3=$iopadmap$yport(0) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(26) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=$iopadmap$uport(26) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(25) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$yport(1) I3=$iopadmap$yport(0) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(27) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$uport(27) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(26) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(24) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(23) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(25) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(28) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(28) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(27) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=$iopadmap$uport(27) I2=$iopadmap$dxport(27) I3=$iopadmap$yport(0) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(25) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(24) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(26) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(24) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(22) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(21) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(23) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(21) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(22) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(29) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(29) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(28) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(28) I2=$iopadmap$dxport(28) I3=$iopadmap$yport(0) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(26) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(25) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(27) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(25) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(23) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(22) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(24) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(22) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(21) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(19) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(20) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(20) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(17) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(16) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(18) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(20) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(18) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(19) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$dxport(19) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(17) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(18) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(16) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(17) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(30) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(30) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(30) I2=$iopadmap$dxport(30) I3=$iopadmap$yport(0) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=$iopadmap$dxport(30) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(31) I2=$iopadmap$dxport(31) I3=$iopadmap$yport(0) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(29) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(29) I2=$iopadmap$dxport(29) I3=$iopadmap$yport(0) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(27) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(27) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(26) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(28) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I2=$iopadmap$dxport(24) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(27) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(29) I3=$iopadmap$dxport(28) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001110010101111
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(25) I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O I3=$iopadmap$dxport(26) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I1=$iopadmap$dxport(18) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(26) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(24) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(24) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(23) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(25) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(23) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=$iopadmap$dxport(10) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(22) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(22) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(20) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(21) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(21) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1 I2=$iopadmap$dxport(20) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(21) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(23) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(22) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(18) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(18) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(15) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(17) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(16) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(17) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(19) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I1=$iopadmap$dxport(12) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(13) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(14) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(17) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(16) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(16) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(15) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(12) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(12) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(11) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(10) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(10) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(5) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(4) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(15) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(16) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(14) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(13) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(16) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(15) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(14) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(11) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$dxport(10) O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(9) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3_LUT4_I0_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110001010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(19) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_O I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(10) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$dxport(9) O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(8) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(7) O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(4) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(2) I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(3) I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2 I1=$iopadmap$dxport(0) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0 I3=$iopadmap$dxport(1) O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(4) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(3) O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(17) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(19) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(24) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(20) I3=$iopadmap$uport(24) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(16) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(18) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(17) I3=$iopadmap$uport(18) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(11) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(14) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(13) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(15) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(14) I3=$iopadmap$uport(15) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(8) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(10) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(12) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(11) I3=$iopadmap$uport(12) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(9) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(8) I3=$iopadmap$uport(9) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$dxport(27) I3=$iopadmap$uport(0) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(2) I3=$iopadmap$dxport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(5) I3=$iopadmap$dxport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$dxport(19) I3=$iopadmap$uport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(18) I3=$iopadmap$uport(6) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(4) I3=$iopadmap$dxport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$dxport(25) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(23) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$uport(3) I2=$iopadmap$dxport(22) I3=$iopadmap$uport(2) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$dxport(22) I2=$iopadmap$uport(2) I3=$iopadmap$uport(3) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(24) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(19) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(23) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(22) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(21) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(20) I3=$iopadmap$uport(21) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(20) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(24) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(23) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(22) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(21) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(21) I3=$iopadmap$uport(22) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(18) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(20) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(19) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(20) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(25) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(21) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(21) I3=$iopadmap$uport(25) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(17) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(19) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(18) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(18) I3=$iopadmap$uport(19) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(13) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(15) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(16) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(18) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(15) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(16) I3=$iopadmap$uport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(12) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(14) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(13) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(15) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(17) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(16) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(14) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(16) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(15) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(15) I3=$iopadmap$uport(16) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(5) I3=$iopadmap$dxport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(22) I2=$iopadmap$dxport(21) I3=$iopadmap$uport(7) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(8) I3=$iopadmap$dxport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(10) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(9) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(8) I3=$iopadmap$uport(9) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(11) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(13) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(12) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(13) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(14) I3=$iopadmap$uport(15) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(10) I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(11) I3=$iopadmap$uport(12) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$dxport(22) I1=$iopadmap$uport(5) I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(21) I3=$iopadmap$uport(6) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(4) I3=$iopadmap$dxport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(7) I3=$iopadmap$dxport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(9) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$dxport(20) I2=$iopadmap$uport(6) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(7) I3=$iopadmap$uport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(10) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(12) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(12) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(13) I3=$iopadmap$uport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(9) I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(10) I3=$iopadmap$uport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(9) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(11) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(10) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(11) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(13) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(12) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(12) I3=$iopadmap$uport(13) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(8) I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(10) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(9) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(9) I3=$iopadmap$uport(10) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(24) I1=$iopadmap$uport(5) I2=$iopadmap$dxport(25) I3=$iopadmap$uport(4) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(26) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(24) I1=$iopadmap$dxport(25) I2=$iopadmap$uport(3) I3=$iopadmap$uport(4) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(5) I2=$iopadmap$dxport(23) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(22) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$dxport(27) I1=$iopadmap$uport(1) I2=$iopadmap$dxport(28) I3=$iopadmap$uport(0) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(2) I3=$iopadmap$dxport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(24) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(25) I3=$iopadmap$uport(3) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$dxport(22) I3=$iopadmap$uport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(26) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(24) I1=$iopadmap$dxport(25) I2=$iopadmap$uport(2) I3=$iopadmap$uport(3) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(24) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(25) I3=$iopadmap$uport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(23) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(22) I3=$iopadmap$uport(3) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$dxport(22) I2=$iopadmap$uport(3) I3=$iopadmap$uport(4) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(25) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$uport(5) I2=$iopadmap$dxport(22) I3=$iopadmap$uport(4) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$dxport(20) I3=$iopadmap$uport(6) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(8) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(7) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(5) I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(19) I2=$iopadmap$dxport(18) I3=$iopadmap$uport(7) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(19) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(24) I1=$iopadmap$uport(3) I2=$iopadmap$dxport(25) I3=$iopadmap$uport(2) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(23) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$dxport(22) I2=$iopadmap$uport(4) I3=$iopadmap$uport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(26) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(25) I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(16) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(18) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(23) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(19) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(19) I3=$iopadmap$uport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(15) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(17) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(16) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(16) I3=$iopadmap$uport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(10) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(13) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(12) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(14) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(13) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(13) I3=$iopadmap$uport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(7) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(9) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(11) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(10) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(10) I3=$iopadmap$uport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$dxport(17) I2=$iopadmap$uport(6) I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(8) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(7) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(7) I3=$iopadmap$uport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$dxport(27) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(19) I1=$iopadmap$uport(5) I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(5) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(4) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(4) I3=$iopadmap$uport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(25) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(24) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(18) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(22) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(21) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(20) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(19) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(19) I3=$iopadmap$uport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$dxport(25) I1=$iopadmap$uport(5) I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$dxport(25) I3=$iopadmap$uport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(24) I3=$iopadmap$uport(6) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(4) I3=$iopadmap$dxport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(23) I2=$iopadmap$uport(6) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$dxport(22) I2=$iopadmap$uport(7) I3=$iopadmap$uport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(26) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(24) I1=$iopadmap$dxport(25) I2=$iopadmap$uport(4) I3=$iopadmap$uport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(7) I3=$iopadmap$dxport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(23) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$dxport(22) I2=$iopadmap$uport(8) I3=$iopadmap$uport(9) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$uport(9) I2=$iopadmap$dxport(22) I3=$iopadmap$uport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(10) I3=$iopadmap$dxport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(12) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(9) I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(10) I3=$iopadmap$uport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(13) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(15) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(15) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(16) I3=$iopadmap$uport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(12) I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(13) I3=$iopadmap$uport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(16) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(18) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(19) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(21) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(18) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(19) I3=$iopadmap$uport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(22) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(24) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(24) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(25) I3=$iopadmap$uport(29) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(21) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(22) I3=$iopadmap$uport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(25) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(30) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(29) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(28) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(27) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(28) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(26) I3=$iopadmap$uport(27) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(23) I3=$iopadmap$uport(6) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$uport(8) I2=$iopadmap$dxport(22) I3=$iopadmap$uport(7) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(9) I3=$iopadmap$dxport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(11) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(10) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(8) I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(9) I3=$iopadmap$uport(10) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(12) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(14) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(13) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(14) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(15) I3=$iopadmap$uport(16) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(11) I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(12) I3=$iopadmap$uport(13) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(15) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(17) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(16) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(18) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(20) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(19) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(17) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(18) I3=$iopadmap$uport(19) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(21) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(23) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(22) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(23) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(24) I3=$iopadmap$uport(28) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(20) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(21) I3=$iopadmap$uport(22) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(24) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(29) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(25) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(28) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(27) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(27) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(25) I3=$iopadmap$uport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(14) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(16) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(15) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(17) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(19) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(18) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(16) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(17) I3=$iopadmap$uport(18) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(20) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(22) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(21) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(22) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(23) I3=$iopadmap$uport(27) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(19) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(20) I3=$iopadmap$uport(21) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(23) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(28) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(24) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(27) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(26) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(25) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(26) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(24) I3=$iopadmap$uport(25) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(19) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(21) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(21) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(22) I3=$iopadmap$uport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(18) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(19) I3=$iopadmap$uport(20) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(22) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(27) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(26) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(25) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(24) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(25) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(23) I3=$iopadmap$uport(24) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(21) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(26) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(22) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(25) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(24) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(24) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(23) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(22) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(22) I3=$iopadmap$uport(23) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$iopadmap$dxport(23) I1=$iopadmap$uport(8) I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$iopadmap$dxport(20) I1=$iopadmap$uport(11) I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(10) I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(11) I3=$iopadmap$uport(12) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(13) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(12) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$uport(10) I2=$iopadmap$dxport(22) I3=$iopadmap$uport(9) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(13) I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(14) I3=$iopadmap$uport(15) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(17) I1=$iopadmap$uport(14) I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(16) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(17) I3=$iopadmap$uport(18) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(16) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(15) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(22) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(23) I3=$iopadmap$uport(24) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(8) I1=$iopadmap$uport(23) I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(25) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(26) I3=$iopadmap$uport(30) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(25) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(24) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$uport(26) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(29) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(27) I3=$iopadmap$uport(28) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(14) I1=$iopadmap$uport(17) I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(19) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(20) I3=$iopadmap$uport(21) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(11) I1=$iopadmap$uport(20) I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(19) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(18) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(22) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(21) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(1) I1=$iopadmap$uport(30) I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(31) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(27) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(29) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(28) O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$dxport(29) I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$dxport(29) I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110110000010
+.subckt LUT4 I0=$iopadmap$dxport(30) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=$iopadmap$dxport(30) I3=$iopadmap$uport(0) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I0 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(5) I3=$iopadmap$dxport(26) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(25) I2=$iopadmap$dxport(24) I3=$iopadmap$uport(7) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(29) I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(27) I1=$iopadmap$dxport(28) I2=$iopadmap$uport(1) I3=$iopadmap$uport(2) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(29) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(29) I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(27) I1=$iopadmap$dxport(28) I2=$iopadmap$uport(2) I3=$iopadmap$uport(3) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(31) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$dxport(29) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(30) I3=$iopadmap$uport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(27) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(28) I3=$iopadmap$uport(3) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(27) I1=$iopadmap$uport(3) I2=$iopadmap$dxport(28) I3=$iopadmap$uport(2) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(27) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(28) I3=$iopadmap$uport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(29) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$iopadmap$dxport(27) I1=$iopadmap$dxport(28) I2=$iopadmap$uport(0) I3=$iopadmap$uport(1) O=reset_LUT4_I0_13_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_14_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=$iopadmap$yport(28) O=yport_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_14_I1 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=$iopadmap$yport(28) I3=reset_LUT4_I0_14_I1_LUT4_I0_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=$iopadmap$yport(29) O=reset_LUT4_I0_14_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(27) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O I3=reset_LUT4_I0_14_I1_LUT4_O_I3 O=reset_LUT4_I0_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_15_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O I3=$iopadmap$yport(26) O=yport_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O I2=$iopadmap$yport(26) I3=reset_LUT4_I0_15_I1 O=reset_LUT4_I0_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(25) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I0_16_I1 O=reset_LUT4_I0_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_16_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O I3=$iopadmap$yport(25) O=yport_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O I1=$iopadmap$yport(24) I2=reset_LUT4_I2_5_I3_LUT4_O_I1 I3=reset_LUT4_I2_5_I3_LUT4_O_I0 O=reset_LUT4_I0_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_17_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O I3=$iopadmap$yport(22) O=yport_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_17_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O I2=$iopadmap$yport(22) I3=reset_LUT4_I2_6_I3_LUT4_O_I3 O=reset_LUT4_I2_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I2=$iopadmap$yport(21) I3=reset_LUT4_I0_18_I1 O=reset_LUT4_I0_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_18_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I3=$iopadmap$yport(21) O=yport_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(20) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O I3=reset_LUT4_I0_19_I1 O=reset_LUT4_I0_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_19_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O I3=$iopadmap$yport(20) O=yport_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(19) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_20_I1 O=reset_LUT4_I0_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(12) I2=$iopadmap$xport(12) I3=reset_LUT4_I0_2_I1 O=reset_LUT4_I0_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_2_I1 I2=$iopadmap$xport(12) I3=$iopadmap$dxport(12) O=xport_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_20_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I3=$iopadmap$yport(19) O=yport_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(18) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O I3=reset_LUT4_I0_21_I1 O=reset_LUT4_I0_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_21_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O I3=$iopadmap$yport(18) O=yport_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(17) I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I0_22_I1 O=reset_LUT4_I0_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_22_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=$iopadmap$yport(17) O=yport_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(16) I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O I3=reset_LUT4_I0_23_I1 O=reset_LUT4_I0_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_23_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O I3=$iopadmap$yport(16) O=yport_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(15) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O I3=reset_LUT4_I0_24_I1 O=reset_LUT4_I0_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_24_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O I3=$iopadmap$yport(15) O=yport_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(14) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O I3=reset_LUT4_I0_25_I1 O=reset_LUT4_I0_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_25_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O I3=$iopadmap$yport(14) O=yport_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(13) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O I3=reset_LUT4_I0_26_I1 O=reset_LUT4_I0_25_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_26_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O I3=$iopadmap$yport(13) O=yport_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(12) I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O I3=reset_LUT4_I0_27_I1 O=reset_LUT4_I0_26_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_27_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O I3=$iopadmap$yport(12) O=yport_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(11) I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I3=reset_LUT4_I0_28_I1 O=reset_LUT4_I0_27_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_28_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I3=$iopadmap$yport(11) O=yport_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(10) I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_29_I1 O=reset_LUT4_I0_28_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_29_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=$iopadmap$yport(10) O=yport_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(9) I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=reset_LUT4_I0_30_I1 O=reset_LUT4_I0_29_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(11) I2=$iopadmap$xport(11) I3=reset_LUT4_I0_3_I1 O=reset_LUT4_I0_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_3_I1 I2=$iopadmap$xport(11) I3=$iopadmap$dxport(11) O=xport_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_30_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=$iopadmap$yport(9) O=yport_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(8) I2=reset_LUT4_I0_31_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_30_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_31_I2 I3=$iopadmap$yport(8) O=yport_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(7) I2=reset_LUT4_I0_32_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I0_32_I2 I3=$iopadmap$yport(7) O=yport_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(6) I2=reset_LUT4_I0_33_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_32_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I2=reset_LUT4_I0_33_I2 I3=$iopadmap$yport(6) O=yport_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(5) I2=reset_LUT4_I0_34_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_33_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I0_34_I2 I3=$iopadmap$yport(5) O=yport_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(4) I2=reset_LUT4_I0_35_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I0_34_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I0_35_I2 I3=$iopadmap$yport(4) O=yport_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(3) I2=reset_LUT4_I0_36_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_35_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I0_36_I2 I3=$iopadmap$yport(3) O=yport_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(2) I2=reset_LUT4_I0_37_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_36_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I0_37_I2 I3=$iopadmap$yport(2) O=yport_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_38_I2 I1=$iopadmap$yport(1) I2=$iopadmap$yport(0) I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_37_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_38_I1 I2=reset_LUT4_I0_38_I2 I3=$iopadmap$yport(1) O=yport_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(0) I3=reset_LUT4_I3_3_I2_LUT4_O_I0 O=reset_LUT4_I0_38_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(1) I2=$iopadmap$dxport(1) I3=$iopadmap$uport(0) O=reset_LUT4_I0_38_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_39_I1 I2=reset_LUT4_I0_39_I2 I3=reset_LUT4_I0_39_I3 O=uport_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I2 I1=reset_LUT4_I2_7_I3_LUT4_O_I0 I2=reset_LUT4_I2_7_I3_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_39_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_39_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_39_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_39_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101110110000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100111111100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(12) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(11) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(10) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(7) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(6) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(5) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(19) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(18) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(20) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(17) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(16) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(18) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(16) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(16) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(15) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(12) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(15) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$dxport(14) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(11) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(10) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(9) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(8) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(11) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(10) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(9) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(6) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(5) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(4) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3_LUT4_I0_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(3) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(5) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(4) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(3) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(0) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(2) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(4) O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3_LUT4_I0_O I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3_LUT4_I0_O I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=$iopadmap$xport(0) O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(1) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(2) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(1) O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(21) O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(22) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(19) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(18) O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(19) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(17) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(16) O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(13) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(10) I2=$iopadmap$xport(10) I3=reset_LUT4_I0_4_I1 O=reset_LUT4_I0_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_4_I1 I2=$iopadmap$xport(10) I3=$iopadmap$dxport(10) O=xport_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_40_I1 I2=reset_LUT4_I0_40_I2 I3=reset_LUT4_I0_40_I3 O=uport_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_40_I1 I1=reset_LUT4_I0_40_I2 I2=reset_LUT4_I0_40_I3 I3=reset_LUT4_I2_8_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I2 I1=reset_LUT4_I2_9_I3_LUT4_O_I0 I2=reset_LUT4_I2_9_I3_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_38_I2 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100000000
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(16) O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(17) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(14) I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(13) O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(13) I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(12) O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(9) I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(4) I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(2) I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_40_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I3 O=reset_LUT4_I2_8_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3_LUT4_I0_O I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(1) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(0) O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_40_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_40_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_41_I1 I2=reset_LUT4_I0_41_I2 I3=reset_LUT4_I0_41_I3 O=uport_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I2_10_I3_LUT4_O_I2 I1=reset_LUT4_I0_41_I1 I2=reset_LUT4_I2_10_I3_LUT4_O_I1 I3=reset_LUT4_I2_10_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I2_11_I3_LUT4_O_I2 I1=reset_LUT4_I2_11_I3_LUT4_O_I3 I2=reset_LUT4_I2_11_I3_LUT4_O_I0 I3=reset_LUT4_I2_11_I3_LUT4_O_I1 O=reset_LUT4_I0_41_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I2 I3=reset_LUT4_I0_41_I3 O=reset_LUT4_I2_10_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I1 O=reset_LUT4_I0_41_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3 I3=reset_LUT4_I0_41_I2 O=reset_LUT4_I2_10_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(23) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=$iopadmap$uport(23) O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(22) I2=$iopadmap$dxport(22) I3=$iopadmap$yport(0) O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(20) I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(22) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(22) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(21) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(21) I2=$iopadmap$dxport(21) I3=$iopadmap$yport(0) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(19) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(0) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=$iopadmap$xport(0) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(8) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(10) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(9) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(10) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(15) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(11) I3=$iopadmap$uport(15) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(8) I3=$iopadmap$uport(9) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(5) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(4) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$dxport(11) I3=$iopadmap$uport(6) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(8) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(7) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(5) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(9) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(7) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(3) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(2) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(4) I3=$iopadmap$uport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(16) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(5) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(13) I2=$iopadmap$dxport(12) I3=$iopadmap$uport(7) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(8) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(10) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(9) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(8) I3=$iopadmap$uport(9) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(11) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(13) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(12) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(13) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(14) I3=$iopadmap$uport(18) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(10) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(11) I3=$iopadmap$uport(12) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(14) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(19) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(15) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(17) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(15) I3=$iopadmap$uport(16) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(1) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(0) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(2) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(3) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$dxport(13) I3=$iopadmap$uport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(2) I3=$iopadmap$uport(3) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$dxport(18) I3=$iopadmap$uport(0) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1_LUT4_O_I1 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(1) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(0) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(2) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(3) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(3) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(2) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(2) I3=$iopadmap$uport(3) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(5) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(4) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(3) I3=$iopadmap$uport(4) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(5) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$dxport(6) I3=$iopadmap$uport(7) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(7) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(12) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(8) I3=$iopadmap$uport(12) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(4) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(4) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(6) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(6) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(15) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(1) I3=$iopadmap$uport(2) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(11) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(16) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(12) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(15) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(14) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(13) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(14) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(12) I3=$iopadmap$uport(13) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(10) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(14) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(13) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(12) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(13) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(11) I3=$iopadmap$uport(12) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(9) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(13) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(12) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(12) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(10) I3=$iopadmap$uport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I2_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(8) I3=$iopadmap$uport(6) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(8) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(7) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(8) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(13) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(9) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(9) I3=$iopadmap$uport(13) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(5) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(6) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(7) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(4) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(9) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(4) I3=$iopadmap$uport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$dxport(16) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(15) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(15) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(9) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(11) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(10) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(11) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(12) I3=$iopadmap$uport(16) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(8) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(9) I3=$iopadmap$uport(10) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(12) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(17) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(13) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(16) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(15) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(15) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(13) I3=$iopadmap$uport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(7) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(9) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(9) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(14) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(10) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(10) I3=$iopadmap$uport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(8) I2=$iopadmap$uport(6) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(7) I3=$iopadmap$uport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(2) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(5) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(10) I2=$iopadmap$dxport(9) I3=$iopadmap$uport(7) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(4) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(9) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(16) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(16) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(3) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(2) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(2) I3=$iopadmap$uport(3) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(17) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(3) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(3) I3=$iopadmap$uport(4) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$dxport(13) I1=$iopadmap$uport(5) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(13) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=$iopadmap$uport(6) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(4) I3=$iopadmap$dxport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(7) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(9) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$dxport(11) I2=$iopadmap$uport(6) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(7) I3=$iopadmap$uport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(10) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(12) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(12) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(13) I3=$iopadmap$uport(17) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(9) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(10) I3=$iopadmap$uport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(13) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(18) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(17) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(16) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(15) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(16) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(14) I3=$iopadmap$uport(15) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(1) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(15) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(16) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(13) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(12) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(12) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(8) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(8) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(7) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(6) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111010100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(1) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(0) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(2) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(3) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(3) O=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I2=$iopadmap$dxport(0) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(14) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(12) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(11) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(11) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(10) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(7) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(2) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(7) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(6) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(5) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100111111100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_42_I1 I2=reset_LUT4_I0_42_I2 I3=reset_LUT4_I0_42_I3 O=uport_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_42_I1 I1=reset_LUT4_I0_42_I2 I2=reset_LUT4_I0_42_I3 I3=reset_LUT4_I2_12_I3_LUT4_O_I3 O=reset_LUT4_I2_11_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=reset_LUT4_I2_13_I3_LUT4_O_I2 I1=reset_LUT4_I2_13_I3_LUT4_O_I3 I2=reset_LUT4_I2_13_I3_LUT4_O_I1 I3=reset_LUT4_I2_13_I3_LUT4_O_I0 O=reset_LUT4_I0_42_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_42_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_42_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(20) I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(20) O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(19) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(19) I2=$iopadmap$dxport(19) I3=$iopadmap$yport(0) O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(17) I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(0) O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(21) I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(21) O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(20) I2=$iopadmap$dxport(20) I3=$iopadmap$yport(0) O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(18) I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101010101100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(0) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I1=$iopadmap$xport(0) I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=$iopadmap$xport(1) O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I1 I1=reset_LUT4_I0_42_I3_LUT4_O_I0 I2=reset_LUT4_I0_42_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3 O=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I3 I3=reset_LUT4_I0_42_I3_LUT4_O_I0 O=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(0) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(18) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(18) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(17) I2=$iopadmap$dxport(17) I3=$iopadmap$yport(0) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(15) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(19) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(19) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(18) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(18) I2=$iopadmap$dxport(18) I3=$iopadmap$yport(0) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(16) I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000011101110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(13) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(11) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(10) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(10) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=$iopadmap$dxport(9) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(6) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(6) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(5) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(4) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(1) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I2=$iopadmap$dxport(0) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(12) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(10) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(9) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=$iopadmap$dxport(8) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(5) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(1) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(5) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(4) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(3) O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111000010111
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_38_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_43_I1 I2=reset_LUT4_I0_43_I2 I3=reset_LUT4_I0_43_I3 O=uport_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I2_14_I3_LUT4_O_I2 I1=reset_LUT4_I0_43_I1 I2=reset_LUT4_I2_14_I3_LUT4_O_I1 I3=reset_LUT4_I2_14_I3_LUT4_O_I3 O=reset_LUT4_I2_13_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I2_15_I3_LUT4_O_I2 I1=reset_LUT4_I2_15_I3_LUT4_O_I3 I2=reset_LUT4_I2_15_I3_LUT4_O_I1 I3=reset_LUT4_I2_15_I3_LUT4_O_I0 O=reset_LUT4_I0_43_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I2 I3=reset_LUT4_I0_43_I3 O=reset_LUT4_I2_14_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_43_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3 I3=reset_LUT4_I0_43_I2 O=reset_LUT4_I2_14_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$iopadmap$xport(0) I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I2_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100000000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(0) I3=$iopadmap$uport(1) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_I3_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000001011
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=$iopadmap$xport(1) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I1=$iopadmap$xport(0) I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=$iopadmap$xport(0) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110111110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(0) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(11) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(9) I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(8) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=$iopadmap$dxport(7) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(4) I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(4) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(3) I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(2) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(2) O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I1 I1=reset_LUT4_I0_43_I3_LUT4_O_I0 I2=reset_LUT4_I0_43_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I3 O=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I0 O=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(6) O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(16) I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(16) O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(15) I2=$iopadmap$dxport(15) I3=$iopadmap$yport(0) O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(13) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(3) O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(2) I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(17) I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(17) O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(16) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(16) I2=$iopadmap$dxport(16) I3=$iopadmap$yport(0) O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(14) I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001110001110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111101110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I0_38_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111110011010
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_42_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_43_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_44_I1 I2=reset_LUT4_I0_44_I2 I3=reset_LUT4_I0_44_I3 O=uport_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_44_I1 I1=reset_LUT4_I0_44_I2 I2=reset_LUT4_I0_44_I3 I3=reset_LUT4_I2_16_I3_LUT4_O_I3 O=reset_LUT4_I2_15_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=reset_LUT4_I2_17_I3_LUT4_O_I2 I1=reset_LUT4_I2_17_I3_LUT4_O_I1 I2=reset_LUT4_I2_17_I3_LUT4_O_I0 I3=reset_LUT4_I2_17_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3 O=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$iopadmap$xport(0) I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(9) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(7) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(3) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(3) I3=$iopadmap$uport(7) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(7) I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$dxport(10) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(5) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(9) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(8) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(7) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(8) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(2) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(7) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(9) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(4) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(8) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(3) I2=$iopadmap$dxport(2) I3=$iopadmap$uport(7) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(2) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(7) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(2) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2_LUT4_O_I1 I1=$iopadmap$dxport(1) I2=$iopadmap$uport(6) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(4) I3=$iopadmap$uport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(2) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(3) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(4) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(9) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(5) I3=$iopadmap$uport(9) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(2) I3=$iopadmap$uport(3) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(11) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(5) I2=$iopadmap$uport(6) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(7) I3=$iopadmap$uport(11) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(4) I3=$iopadmap$uport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(11) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(10) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(9) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(10) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(8) I3=$iopadmap$uport(9) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$dxport(10) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(10) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(9) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(3) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(2) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(8) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(4) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(4) I3=$iopadmap$uport(8) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(1) I3=$iopadmap$uport(2) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(5) I3=$iopadmap$uport(6) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(11) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(7) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(10) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(9) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(8) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(9) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(7) I3=$iopadmap$uport(8) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(8) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(5) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(4) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(5) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(4) I2=$iopadmap$dxport(0) I3=$iopadmap$uport(10) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(0) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(10) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(3) I3=$iopadmap$uport(4) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(1) I3=$iopadmap$uport(2) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(11) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$dxport(12) I3=$iopadmap$uport(0) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(8) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(12) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(11) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(10) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(11) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(9) I3=$iopadmap$uport(10) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I3=$iopadmap$xport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O I1=$iopadmap$xport(0) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111000001111
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$xport(0) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=$iopadmap$xport(0) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(3) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(15) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(15) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(14) I2=$iopadmap$dxport(14) I3=$iopadmap$yport(0) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(12) I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(9) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(7) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(6) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=$iopadmap$dxport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(6) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(6) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(4) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(3) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(3) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(2) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=$iopadmap$dxport(2) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(1) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(3) I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(4) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(7) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(5) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(4) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(11) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(11) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(10) I2=$iopadmap$dxport(10) I3=$iopadmap$yport(0) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(8) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(5) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(6) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(8) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I2=$iopadmap$dxport(0) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(14) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(14) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(13) I2=$iopadmap$dxport(13) I3=$iopadmap$yport(0) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(11) I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(10) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(8) I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(7) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110010101010
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(1) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(4) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(12) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(12) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(11) I2=$iopadmap$dxport(11) I3=$iopadmap$yport(0) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(9) I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(13) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(13) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(12) I2=$iopadmap$dxport(12) I3=$iopadmap$yport(0) O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(10) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I3 O=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_38_I2 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_38_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110111110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1 O=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I2_O I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=reset_LUT4_I0_38_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010111
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100111111100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_45_I1 I2=reset_LUT4_I0_45_I2 I3=reset_LUT4_I0_45_I3 O=uport_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3 I2=reset_LUT4_I0_46_I2 I3=reset_LUT4_I0_46_I1 O=reset_LUT4_I0_45_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_45_I2 I3=reset_LUT4_I0_45_I3 O=reset_LUT4_I2_17_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_45_I2_LUT4_O_I2 I3=reset_LUT4_I0_45_I2_LUT4_O_I3 O=reset_LUT4_I0_45_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_45_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I2_O I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_45_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_45_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_45_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_45_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_45_I3 I2=reset_LUT4_I0_45_I2_LUT4_O_I2 I3=reset_LUT4_I0_45_I2_LUT4_O_I3 O=reset_LUT4_I0_45_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_46_I3_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I3 O=reset_LUT4_I0_45_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_46_I1 I2=reset_LUT4_I0_46_I2 I3=reset_LUT4_I0_46_I3 O=uport_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_46_I1 I1=reset_LUT4_I0_46_I2 I2=reset_LUT4_I0_46_I3 I3=reset_LUT4_I0_45_I3_LUT4_I1_O O=reset_LUT4_I2_17_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_47_I2 I2=reset_LUT4_I0_47_I3 I3=reset_LUT4_I0_47_I1 O=reset_LUT4_I0_46_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_47_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_46_I3_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I3 O=reset_LUT4_I0_46_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I2_O O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I3_O O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I3=$iopadmap$xport(0) O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(10) I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(10) O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(9) I2=$iopadmap$dxport(9) I3=$iopadmap$yport(0) O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(7) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(9) I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(9) O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=$iopadmap$uport(8) I2=$iopadmap$dxport(8) I3=$iopadmap$yport(0) O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(6) I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(1) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(9) I2=$iopadmap$yport(10) I3=$iopadmap$dxport(0) O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_46_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_47_I1 I2=reset_LUT4_I0_47_I2 I3=reset_LUT4_I0_47_I3 O=uport_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2 I2=reset_LUT4_I0_48_I3 I3=reset_LUT4_I0_48_I1 O=reset_LUT4_I0_47_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_47_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_47_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_47_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_47_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I0_47_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_47_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I3 O=reset_LUT4_I0_47_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_48_I1 I2=reset_LUT4_I0_48_I2 I3=reset_LUT4_I0_48_I3 O=uport_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2 I2=reset_LUT4_I0_49_I3 I3=reset_LUT4_I0_49_I1 O=reset_LUT4_I0_48_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I1=$iopadmap$xport(0) I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(1) I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(0) I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(1) I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I3_I2 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O I3=$iopadmap$xport(0) O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I1=$iopadmap$xport(0) I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I3_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_1_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100100010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_1_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_1_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_I1_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_I1_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=reset_LUT4_I0_38_I2 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I0_38_I2 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111110011010
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_38_I2 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I0_49_I2_LUT4_O_I1 O=reset_LUT4_I0_48_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_48_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_49_I1 I2=reset_LUT4_I0_49_I2 I3=reset_LUT4_I0_49_I3 O=uport_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2 I2=reset_LUT4_I0_50_I3 I3=reset_LUT4_I0_50_I1 O=reset_LUT4_I0_49_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_49_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_1_O I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_49_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_1_O I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_47_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_46_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(2) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(3) I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(4) I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(6) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001110010101111
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 I1=$iopadmap$dxport(6) I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=$iopadmap$dxport(5) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(1) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(0) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(6) I2=$iopadmap$yport(0) I3=$iopadmap$uport(6) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=$iopadmap$dxport(3) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(7) I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$uport(7) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=$iopadmap$dxport(4) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(8) I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$uport(8) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(7) I3=$iopadmap$yport(0) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O I3=$iopadmap$dxport(0) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(2) I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(3) I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(5) I3=$iopadmap$dxport(4) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001110010101111
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 I1=$iopadmap$dxport(5) I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=$iopadmap$dxport(4) O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_49_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1 I1=reset_LUT4_I0_50_I2_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_50_I2_LUT4_O_I0 O=reset_LUT4_I0_49_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(9) I2=$iopadmap$xport(9) I3=reset_LUT4_I0_5_I1 O=reset_LUT4_I0_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_5_I1 I2=$iopadmap$xport(9) I3=$iopadmap$dxport(9) O=xport_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_50_I1 I2=reset_LUT4_I0_50_I2 I3=reset_LUT4_I0_50_I3 O=uport_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3 I2=reset_LUT4_I0_51_I2 I3=reset_LUT4_I0_51_I1 O=reset_LUT4_I0_50_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_50_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I2 O=reset_LUT4_I0_50_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I0_50_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I0_38_I2 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111110011010
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110111110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$xport(0) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$iopadmap$xport(0) I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$xport(0) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$xport(1) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_1_O O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_I1 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_I3 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(0) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(2) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(7) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=$iopadmap$dxport(7) I1=$iopadmap$uport(0) I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(6) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(0) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(2) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(5) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(5) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(3) I3=$iopadmap$uport(4) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(2) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2_LUT4_O_I1 I2=$iopadmap$dxport(1) I3=$iopadmap$uport(6) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(5) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(4) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(3) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(4) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(2) I3=$iopadmap$uport(3) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(1) I3=$iopadmap$uport(5) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(6) O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_50_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I3 I2=reset_LUT4_I0_51_I3_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I2 O=reset_LUT4_I0_50_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_51_I1 I2=reset_LUT4_I0_51_I2 I3=reset_LUT4_I0_51_I3 O=uport_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_18_I3_LUT4_O_I3 I3=reset_LUT4_I2_18_I3_LUT4_O_I2 O=reset_LUT4_I0_51_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_18_I3_LUT4_O_I0 I1=reset_LUT4_I2_18_I3_LUT4_O_I1 I2=reset_LUT4_I2_18_I3_LUT4_O_I2 I3=reset_LUT4_I2_18_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=$iopadmap$xport(0) I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$xport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2_LUT4_I1_1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2_LUT4_I1_1_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(5) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(5) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$uport(4) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(3) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(2) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2_LUT4_I1_1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(4) I2=$iopadmap$dxport(4) I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=$iopadmap$uport(0) I1=$iopadmap$dxport(3) I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(1) I3=$iopadmap$uport(2) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$iopadmap$dxport(1) I1=$iopadmap$dxport(2) I2=$iopadmap$uport(0) I3=$iopadmap$uport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(2) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(1) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O I3=$iopadmap$xport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2_LUT4_I1_1_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(6) I2=$iopadmap$dxport(6) I3=$iopadmap$yport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(5) I2=$iopadmap$dxport(5) I3=$iopadmap$yport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(3) I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(3) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$dxport(2) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(2) I2=$iopadmap$dxport(1) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(2) I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O I3=$iopadmap$dxport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110111011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000000000001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=reset_LUT4_I0_38_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100111111100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=reset_LUT4_I0_38_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100111111100
+.subckt LUT4 I0=$iopadmap$xport(0) I1=$iopadmap$xport(2) I2=$iopadmap$xport(1) I3=$iopadmap$xport(3) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(3) I3=$iopadmap$yport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(4) I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(4) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(3) I2=$iopadmap$yport(1) I3=$iopadmap$yport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$yport(3) I2=$iopadmap$yport(4) I3=$iopadmap$dxport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$yport(3) I2=$iopadmap$yport(5) I3=$iopadmap$yport(4) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110101000000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$yport(3) I2=$iopadmap$yport(5) I3=$iopadmap$yport(4) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001010110100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O I1=$iopadmap$yport(5) I2=$iopadmap$yport(7) I3=$iopadmap$yport(6) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(6) I2=$iopadmap$yport(5) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(4) I2=$iopadmap$yport(3) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$yport(2) I2=$iopadmap$yport(1) I3=$iopadmap$yport(3) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001001100111111
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(2) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001110010101111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(1) I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(4) I2=$iopadmap$dxport(4) I3=$iopadmap$yport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(5) I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(5) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(4) I2=$iopadmap$yport(1) I3=$iopadmap$yport(0) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$yport(3) I2=$iopadmap$yport(4) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(3) I3=$iopadmap$dxport(2) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001110010101111
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$dxport(1) O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I0_51_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010011101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_49_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(0) I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100000000
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=$iopadmap$xport(0) I2=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I0_51_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_18_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_18_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_52_I1 I2=reset_LUT4_I0_52_I2 I3=reset_LUT4_I0_52_I3 O=uport_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_20_I3_LUT4_O_I3 I2=reset_LUT4_I1_I3_LUT4_I2_O I3=reset_LUT4_I3_3_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I1_O O=reset_LUT4_I0_52_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_19_I3_LUT4_O_I0 I2=reset_LUT4_I0_52_I2 I3=reset_LUT4_I0_52_I1 O=reset_LUT4_I2_19_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I1_O I1=reset_LUT4_I1_I2 I2=reset_LUT4_I1_I3_LUT4_I2_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3 O=reset_LUT4_I0_52_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=reset_LUT4_I0_52_I3_LUT4_O_I3 O=reset_LUT4_I0_52_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_52_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_53_I1 I2=$iopadmap$xport(30) I3=$iopadmap$dxport(30) O=xport_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(29) I2=$iopadmap$xport(29) I3=reset_LUT4_I0_54_I1 O=reset_LUT4_I0_53_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_54_I1 I2=$iopadmap$xport(29) I3=$iopadmap$dxport(29) O=xport_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$iopadmap$xport(28) I1=$iopadmap$dxport(28) I2=reset_LUT4_I2_23_I3_LUT4_O_I0 I3=reset_LUT4_I2_23_I3_LUT4_O_I1 O=reset_LUT4_I0_54_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_55_I1 I2=$iopadmap$xport(27) I3=$iopadmap$dxport(27) O=xport_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_55_I1 I2=$iopadmap$dxport(27) I3=$iopadmap$xport(27) O=reset_LUT4_I2_23_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(26) I2=$iopadmap$xport(26) I3=reset_LUT4_I0_56_I1 O=reset_LUT4_I0_55_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_56_I1 I2=$iopadmap$xport(26) I3=$iopadmap$dxport(26) O=xport_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(25) I2=$iopadmap$xport(25) I3=reset_LUT4_I0_57_I1 O=reset_LUT4_I0_56_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_57_I1 I2=$iopadmap$xport(25) I3=$iopadmap$dxport(25) O=xport_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(24) I2=$iopadmap$xport(24) I3=reset_LUT4_I0_58_I1 O=reset_LUT4_I0_57_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_58_I1 I2=$iopadmap$xport(24) I3=$iopadmap$dxport(24) O=xport_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(23) I2=$iopadmap$xport(23) I3=reset_LUT4_I0_59_I1 O=reset_LUT4_I0_58_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_59_I1 I2=$iopadmap$xport(23) I3=$iopadmap$dxport(23) O=xport_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(22) I2=$iopadmap$xport(22) I3=reset_LUT4_I0_60_I1 O=reset_LUT4_I0_59_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(8) I2=$iopadmap$xport(8) I3=reset_LUT4_I0_6_I1 O=reset_LUT4_I0_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_6_I1 I2=$iopadmap$xport(8) I3=$iopadmap$dxport(8) O=xport_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_60_I1 I2=$iopadmap$xport(22) I3=$iopadmap$dxport(22) O=xport_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(21) I2=$iopadmap$xport(21) I3=reset_LUT4_I0_61_I1 O=reset_LUT4_I0_60_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_61_I1 I2=$iopadmap$xport(21) I3=$iopadmap$dxport(21) O=xport_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(20) I2=$iopadmap$xport(20) I3=reset_LUT4_I0_62_I1 O=reset_LUT4_I0_61_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_62_I1 I2=$iopadmap$xport(20) I3=$iopadmap$dxport(20) O=xport_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(19) I2=$iopadmap$xport(19) I3=reset_LUT4_I0_63_I1 O=reset_LUT4_I0_62_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_63_I1 I2=$iopadmap$xport(19) I3=$iopadmap$dxport(19) O=xport_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(18) I2=$iopadmap$xport(18) I3=reset_LUT4_I0_64_I1 O=reset_LUT4_I0_63_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_64_I1 I2=$iopadmap$xport(18) I3=$iopadmap$dxport(18) O=xport_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(17) I2=$iopadmap$xport(17) I3=reset_LUT4_I0_65_I1 O=reset_LUT4_I0_64_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_65_I1 I2=$iopadmap$xport(17) I3=$iopadmap$dxport(17) O=xport_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(16) I2=$iopadmap$xport(16) I3=reset_LUT4_I0_66_I1 O=reset_LUT4_I0_65_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_66_I1 I2=$iopadmap$xport(16) I3=$iopadmap$dxport(16) O=xport_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(15) I2=$iopadmap$xport(15) I3=reset_LUT4_I0_67_I1 O=reset_LUT4_I0_66_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_67_I1 I2=$iopadmap$xport(15) I3=$iopadmap$dxport(15) O=xport_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(14) I2=$iopadmap$xport(14) I3=reset_LUT4_I0_I1 O=reset_LUT4_I0_67_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(7) I2=$iopadmap$xport(7) I3=reset_LUT4_I0_7_I1 O=reset_LUT4_I0_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_7_I1 I2=$iopadmap$xport(7) I3=$iopadmap$dxport(7) O=xport_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(6) I2=$iopadmap$xport(6) I3=reset_LUT4_I0_8_I1 O=reset_LUT4_I0_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_8_I1 I2=$iopadmap$xport(6) I3=$iopadmap$dxport(6) O=xport_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(5) I2=$iopadmap$xport(5) I3=reset_LUT4_I0_9_I1 O=reset_LUT4_I0_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$reset I1=reset_LUT4_I0_9_I1 I2=$iopadmap$xport(5) I3=$iopadmap$dxport(5) O=xport_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(4) I2=$iopadmap$xport(4) I3=reset_LUT4_I0_10_I1 O=reset_LUT4_I0_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(13) I2=$iopadmap$xport(13) I3=reset_LUT4_I0_1_I1 O=reset_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$reset I2=reset_LUT4_I1_I2 I3=reset_LUT4_I1_I3 O=uport_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=$iopadmap$xport(0) I1=$iopadmap$dxport(0) I2=$iopadmap$yport(0) I3=$iopadmap$uport(0) O=reset_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011011111000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I1_I3 I3=reset_LUT4_I3_3_I2 O=reset_LUT4_I1_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(0) I2=$iopadmap$xport(0) I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_I3 O=xport_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_1_I3 O=xport_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_10_I3 O=uport_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_41_I1 I1=reset_LUT4_I2_10_I3_LUT4_O_I1 I2=reset_LUT4_I2_10_I3_LUT4_O_I2 I3=reset_LUT4_I2_10_I3_LUT4_O_I3 O=reset_LUT4_I2_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_10_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_11_I3 O=uport_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_11_I3_LUT4_O_I0 I1=reset_LUT4_I2_11_I3_LUT4_O_I1 I2=reset_LUT4_I2_11_I3_LUT4_O_I2 I3=reset_LUT4_I2_11_I3_LUT4_O_I3 O=reset_LUT4_I2_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_11_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_11_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I0 I2=reset_LUT4_I0_41_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3 O=reset_LUT4_I2_11_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_12_I3 O=uport_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_42_I1 I1=reset_LUT4_I0_42_I2 I2=reset_LUT4_I0_42_I3 I3=reset_LUT4_I2_12_I3_LUT4_O_I3 O=reset_LUT4_I2_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_12_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I0_41_I3_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I2_12_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_13_I3 O=uport_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_13_I3_LUT4_O_I0 I1=reset_LUT4_I2_13_I3_LUT4_O_I1 I2=reset_LUT4_I2_13_I3_LUT4_O_I2 I3=reset_LUT4_I2_13_I3_LUT4_O_I3 O=reset_LUT4_I2_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_13_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_13_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_13_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I2_13_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_13_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_42_I2_LUT4_O_I2 I3=reset_LUT4_I0_42_I2_LUT4_O_I3 O=reset_LUT4_I2_13_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_14_I3 O=uport_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_43_I1 I1=reset_LUT4_I2_14_I3_LUT4_O_I1 I2=reset_LUT4_I2_14_I3_LUT4_O_I2 I3=reset_LUT4_I2_14_I3_LUT4_O_I3 O=reset_LUT4_I2_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_14_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_42_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_42_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_14_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_15_I3 O=uport_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_15_I3_LUT4_O_I0 I1=reset_LUT4_I2_15_I3_LUT4_O_I1 I2=reset_LUT4_I2_15_I3_LUT4_O_I2 I3=reset_LUT4_I2_15_I3_LUT4_O_I3 O=reset_LUT4_I2_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_15_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_15_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_15_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I2_15_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_15_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I2_LUT4_O_I2 I3=reset_LUT4_I0_43_I2_LUT4_O_I3 O=reset_LUT4_I2_15_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_16_I3 O=uport_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_44_I1 I1=reset_LUT4_I0_44_I2 I2=reset_LUT4_I0_44_I3 I3=reset_LUT4_I2_16_I3_LUT4_O_I3 O=reset_LUT4_I2_16_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_16_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I0_43_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I2=reset_LUT4_I0_43_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_43_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_44_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_44_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_16_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_17_I3 O=uport_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_17_I3_LUT4_O_I0 I1=reset_LUT4_I2_17_I3_LUT4_O_I1 I2=reset_LUT4_I2_17_I3_LUT4_O_I2 I3=reset_LUT4_I2_17_I3_LUT4_O_I3 O=reset_LUT4_I2_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_44_I2_LUT4_O_I3 I3=reset_LUT4_I0_44_I2_LUT4_O_I2 O=reset_LUT4_I2_17_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_45_I2_LUT4_O_I2 I3=reset_LUT4_I0_45_I2_LUT4_O_I3 O=reset_LUT4_I2_17_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_18_I3 O=uport_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_18_I3_LUT4_O_I0 I1=reset_LUT4_I2_18_I3_LUT4_O_I1 I2=reset_LUT4_I2_18_I3_LUT4_O_I2 I3=reset_LUT4_I2_18_I3_LUT4_O_I3 O=reset_LUT4_I2_18_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I2_19_I3_LUT4_O_I2 I1=reset_LUT4_I2_19_I3_LUT4_O_I1 I2=reset_LUT4_I2_19_I3_LUT4_O_I0 I3=reset_LUT4_I2_19_I3_LUT4_O_I3 O=reset_LUT4_I2_18_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111010101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_19_I3_LUT4_O_I1 I3=reset_LUT4_I2_19_I3_LUT4_O_I3 O=reset_LUT4_I2_18_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_18_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_18_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_18_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_18_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_18_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_18_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_19_I3 O=uport_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_19_I3_LUT4_O_I0 I1=reset_LUT4_I2_19_I3_LUT4_O_I1 I2=reset_LUT4_I2_19_I3_LUT4_O_I2 I3=reset_LUT4_I2_19_I3_LUT4_O_I3 O=reset_LUT4_I2_19_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=reset_LUT4_I0_52_I3_LUT4_O_I3 O=reset_LUT4_I2_19_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=reset_LUT4_I0_52_I3_LUT4_O_I3 O=reset_LUT4_I2_19_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_19_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O I2=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1 O=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$iopadmap$xport(0) I1=$iopadmap$dxport(0) I2=$iopadmap$xport(1) I3=$iopadmap$dxport(1) O=reset_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_2_I3 O=yport_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_20_I3 O=uport_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I1_I3_LUT4_I2_O I1=reset_LUT4_I1_I2 I2=reset_LUT4_I3_3_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I1_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3 O=reset_LUT4_I2_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_20_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I2_LUT4_I0_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010111
+.subckt LUT4 I0=$iopadmap$xport(1) I1=reset_LUT4_I0_38_I2 I2=$iopadmap$xport(0) I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101000110000
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(0) I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_38_I2 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=reset_LUT4_I0_38_I2 I1=reset_LUT4_I3_1_I2 I2=$iopadmap$xport(0) I3=$iopadmap$xport(1) O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$xport(0) O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$xport(0) O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$uport(2) I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(2) I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(1) I2=$iopadmap$uport(0) I3=$iopadmap$uport(1) O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$iopadmap$dxport(1) I1=$iopadmap$uport(1) I2=$iopadmap$dxport(2) I3=$iopadmap$uport(0) O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_38_I2 O=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I1_I3_LUT4_I2_O I1=reset_LUT4_I1_I2 I2=$iopadmap$reset I3=reset_LUT4_I3_3_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I1_O O=uport_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=reset_LUT4_I2_22_I0 I1=reset_LUT4_I2_22_I1 I2=$iopadmap$reset I3=reset_LUT4_I2_22_I3 O=xport_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=reset_LUT4_I0_54_I1 I1=$iopadmap$xport(29) I2=$iopadmap$dxport(29) I3=reset_LUT4_I2_22_I0_LUT4_O_I3 O=reset_LUT4_I2_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(30) I3=$iopadmap$xport(30) O=reset_LUT4_I2_22_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(30) I3=$iopadmap$xport(30) O=reset_LUT4_I2_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(31) I3=$iopadmap$xport(31) O=reset_LUT4_I2_22_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_23_I3 O=xport_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_23_I3_LUT4_O_I0 I1=reset_LUT4_I2_23_I3_LUT4_O_I1 I2=$iopadmap$xport(28) I3=$iopadmap$dxport(28) O=reset_LUT4_I2_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(27) I3=$iopadmap$xport(27) O=reset_LUT4_I2_23_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2 I3=$iopadmap$yport(30) O=reset_LUT4_I2_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$yport(29) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I2_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=$iopadmap$xport(1) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100111111100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(2) I3=$iopadmap$xport(0) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(8) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(5) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(4) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(9) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(6) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(6) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(5) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I1=$iopadmap$dxport(6) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(7) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$dxport(2) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(27) I2=$iopadmap$yport(29) I3=$iopadmap$yport(28) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(28) I2=$iopadmap$yport(27) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(25) I2=$iopadmap$yport(27) I3=$iopadmap$yport(26) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(25) I2=$iopadmap$yport(27) I3=$iopadmap$yport(26) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(26) I2=$iopadmap$yport(25) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(23) I2=$iopadmap$yport(25) I3=$iopadmap$yport(24) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(23) I2=$iopadmap$yport(25) I3=$iopadmap$yport(24) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(24) I2=$iopadmap$yport(23) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(21) I2=$iopadmap$yport(23) I3=$iopadmap$yport(22) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(21) I2=$iopadmap$yport(23) I3=$iopadmap$yport(22) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(22) I2=$iopadmap$yport(21) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(19) I2=$iopadmap$yport(21) I3=$iopadmap$yport(20) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(19) I2=$iopadmap$yport(21) I3=$iopadmap$yport(20) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(20) I2=$iopadmap$yport(19) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(17) I2=$iopadmap$yport(19) I3=$iopadmap$yport(18) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(17) I2=$iopadmap$yport(19) I3=$iopadmap$yport(18) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(18) I2=$iopadmap$yport(17) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(15) I2=$iopadmap$yport(17) I3=$iopadmap$yport(16) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(15) I2=$iopadmap$yport(17) I3=$iopadmap$yport(16) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(16) I2=$iopadmap$yport(15) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(13) I2=$iopadmap$yport(15) I3=$iopadmap$yport(14) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(13) I2=$iopadmap$yport(15) I3=$iopadmap$yport(14) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(14) I2=$iopadmap$yport(13) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(11) I2=$iopadmap$yport(13) I3=$iopadmap$yport(12) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(11) I2=$iopadmap$yport(13) I3=$iopadmap$yport(12) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(12) I2=$iopadmap$yport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(9) I2=$iopadmap$yport(11) I3=$iopadmap$yport(10) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(9) I2=$iopadmap$yport(11) I3=$iopadmap$yport(10) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(10) I2=$iopadmap$yport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(7) I2=$iopadmap$yport(9) I3=$iopadmap$yport(8) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(7) I2=$iopadmap$yport(9) I3=$iopadmap$yport(8) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(8) I2=$iopadmap$yport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O I1=$iopadmap$yport(5) I2=$iopadmap$yport(7) I3=$iopadmap$yport(6) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=$iopadmap$yport(29) I2=$iopadmap$yport(30) I3=$iopadmap$yport(31) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001100011100111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(4) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(1) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(30) I2=$iopadmap$yport(29) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$yport(27) I2=$iopadmap$yport(29) I3=$iopadmap$yport(28) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1 I3=$iopadmap$xport(0) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100001000101011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=$iopadmap$xport(0) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I0 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(15) I3=$iopadmap$dxport(8) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(17) I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(22) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(18) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(18) I3=$iopadmap$uport(22) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(14) I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(16) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(15) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(15) I3=$iopadmap$uport(16) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(9) I3=$iopadmap$dxport(14) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(12) I3=$iopadmap$dxport(11) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(11) I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(13) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(12) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(12) I3=$iopadmap$uport(13) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$dxport(17) I3=$iopadmap$uport(6) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(8) I2=$iopadmap$dxport(14) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(10) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(9) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(9) I3=$iopadmap$uport(10) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(5) I2=$iopadmap$dxport(17) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$uport(6) I1=$iopadmap$dxport(16) I2=$iopadmap$dxport(15) I3=$iopadmap$uport(7) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(16) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$dxport(24) I1=$iopadmap$uport(0) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(23) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(22) I3=$iopadmap$uport(1) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(22) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(23) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(20) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(20) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(4) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(3) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(3) I3=$iopadmap$uport(4) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(17) I3=$iopadmap$dxport(5) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(21) I3=$iopadmap$dxport(1) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(20) I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(19) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(18) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(18) I3=$iopadmap$uport(19) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I0_13_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(22) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(21) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_I3 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$dxport(20) I1=$iopadmap$uport(2) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=$iopadmap$dxport(20) I1=$iopadmap$uport(2) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(20) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(1) I3=$iopadmap$dxport(20) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I3_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I2=$iopadmap$dxport(21) I3=$iopadmap$uport(0) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=$iopadmap$dxport(21) I1=$iopadmap$uport(0) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I3_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$uport(0) I2=$iopadmap$dxport(20) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(1) I3=$iopadmap$uport(2) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(3) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(2) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(2) I3=$iopadmap$uport(3) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(24) I1=$iopadmap$uport(0) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(14) I3=$iopadmap$dxport(8) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(16) I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(21) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(17) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(17) I3=$iopadmap$uport(21) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(13) I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(15) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(14) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(14) I3=$iopadmap$uport(15) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(8) I3=$iopadmap$dxport(14) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(11) I3=$iopadmap$dxport(11) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(10) I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(12) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(11) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(11) I3=$iopadmap$uport(12) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(5) I3=$iopadmap$dxport(17) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(7) I2=$iopadmap$dxport(14) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(9) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(8) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(8) I3=$iopadmap$uport(9) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$dxport(16) I3=$iopadmap$uport(5) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=$iopadmap$uport(6) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(4) I3=$iopadmap$dxport(17) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(16) I3=$iopadmap$dxport(5) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(20) I3=$iopadmap$dxport(1) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(19) I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(18) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(17) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(17) I3=$iopadmap$uport(18) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$xport(0) I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3 O=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=$iopadmap$xport(1) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$xport(0) I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$xport(0) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(13) I3=$iopadmap$dxport(8) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$uport(15) I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$uport(20) I2=$iopadmap$dxport(4) I3=$iopadmap$uport(16) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(16) I3=$iopadmap$uport(20) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(12) I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(12) I3=$iopadmap$dxport(8) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(14) I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(0) I1=$iopadmap$dxport(4) I2=$iopadmap$uport(15) I3=$iopadmap$uport(19) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(11) I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(12) I3=$iopadmap$uport(13) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$uport(14) I2=$iopadmap$dxport(7) I3=$iopadmap$uport(13) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(6) I1=$iopadmap$dxport(7) I2=$iopadmap$uport(13) I3=$iopadmap$uport(14) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(7) I3=$iopadmap$dxport(14) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(10) I3=$iopadmap$dxport(11) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(9) I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(9) I3=$iopadmap$dxport(11) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$uport(11) I2=$iopadmap$dxport(10) I3=$iopadmap$uport(10) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(10) I3=$iopadmap$uport(11) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$dxport(16) I1=$iopadmap$uport(5) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$dxport(14) I2=$iopadmap$uport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$dxport(14) I3=$iopadmap$uport(6) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I1_1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$uport(8) I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(9) I1=$iopadmap$dxport(10) I2=$iopadmap$uport(9) I3=$iopadmap$uport(10) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$uport(8) I2=$iopadmap$dxport(13) I3=$iopadmap$uport(7) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(12) I1=$iopadmap$dxport(13) I2=$iopadmap$uport(7) I3=$iopadmap$uport(8) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(3) I2=$iopadmap$dxport(17) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(3) I3=$iopadmap$dxport(17) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(17) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(3) I3=$iopadmap$uport(4) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$uport(5) I2=$iopadmap$dxport(14) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$uport(5) I2=$iopadmap$dxport(16) I3=$iopadmap$uport(4) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(15) I1=$iopadmap$dxport(16) I2=$iopadmap$uport(4) I3=$iopadmap$uport(5) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$uport(15) I3=$iopadmap$dxport(5) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(19) I3=$iopadmap$dxport(1) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$uport(18) I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$uport(18) I3=$iopadmap$dxport(1) O=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$uport(17) I2=$iopadmap$dxport(3) I3=$iopadmap$uport(16) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$dxport(2) I1=$iopadmap$dxport(3) I2=$iopadmap$uport(16) I3=$iopadmap$uport(17) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$dxport(20) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$uport(2) I2=$iopadmap$dxport(19) I3=$iopadmap$uport(1) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$dxport(20) I1=$iopadmap$uport(0) I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$iopadmap$dxport(18) I1=$iopadmap$dxport(19) I2=$iopadmap$uport(0) I3=$iopadmap$uport(1) O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$dxport(20) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I1_1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I1_1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I2_1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_3_I3 O=yport_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_14_I1 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=$iopadmap$yport(28) I3=reset_LUT4_I2_3_I3_LUT4_O_I3 O=reset_LUT4_I2_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$yport(29) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I2_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_4_I3 O=yport_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_15_I1 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O I2=$iopadmap$yport(26) I3=reset_LUT4_I2_4_I3_LUT4_O_I3 O=reset_LUT4_I2_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$yport(27) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O_LUT4_I1_O O=reset_LUT4_I2_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_5_I3 O=yport_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_5_I3_LUT4_O_I0 I1=reset_LUT4_I2_5_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O I3=$iopadmap$yport(24) O=reset_LUT4_I2_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$yport(23) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I2_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_6_I3 O=yport_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_17_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O I2=$iopadmap$yport(22) I3=reset_LUT4_I2_6_I3_LUT4_O_I3 O=reset_LUT4_I2_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$yport(23) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I2_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_7_I3 O=uport_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_8_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_8_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3 I1=reset_LUT4_I0_39_I3_LUT4_O_I0 I2=reset_LUT4_I0_39_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(20) O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(19) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(21) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(18) I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(17) O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_1_O I1=$iopadmap$xport(0) I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_I3_LUT4_I0_O I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100111111100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_38_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110111110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_8_I3 O=uport_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_40_I1 I1=reset_LUT4_I0_40_I2 I2=reset_LUT4_I0_40_I3 I3=reset_LUT4_I2_8_I3_LUT4_O_I3 O=reset_LUT4_I2_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_8_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_8_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_8_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I0 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_8_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$reset I3=reset_LUT4_I2_9_I3 O=uport_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I0 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I3 I3=reset_LUT4_I0_40_I2_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I2_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(18) O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(17) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(19) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(16) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(15) O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_41_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$dxport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(0) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(0) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(1) I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(17) O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(16) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(18) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(15) I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(16) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(14) O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(14) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(13) O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(10) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(9) O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(8) I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(7) O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_1_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I0_38_I2 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111110011010
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_42_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_42_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_40_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_41_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I2_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=aport_LUT4_I2_9_O_LUT4_I3_O I1=reset_LUT4_I2_I3_LUT4_O_I1 I2=aport_LUT4_I1_14_O_LUT4_I2_O I3=aport_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100110011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(0) I2=$iopadmap$xport(0) I3=$iopadmap$reset O=xport_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(0) I2=reset_LUT4_I3_1_I2 I3=$iopadmap$reset O=yport_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$uport(0) I3=$iopadmap$dxport(0) O=reset_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1 I2=reset_LUT4_I3_2_I2 I3=$iopadmap$reset O=uport_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_39_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(23) O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(22) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(24) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(21) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(20) O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3_LUT4_I0_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I0_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3_LUT4_I0_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I0_LUT4_I2_O I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I0_LUT4_I2_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001001101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I0_LUT4_O_I0_LUT4_I2_O I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3_LUT4_I0_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(8) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(7) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$dxport(7) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(6) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(8) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(6) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(5) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(6) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(3) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(2) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(5) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(2) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(3) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O I3=$iopadmap$dxport(0) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(1) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$dxport(3) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(2) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(4) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(22) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(21) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(23) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I1=$iopadmap$dxport(20) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(19) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(21) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(19) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(18) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_O_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(20) I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I0_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(19) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(18) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(15) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(18) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(16) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(17) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$dxport(17) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(16) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(14) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(13) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(15) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$dxport(13) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(12) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(14) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(12) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(11) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=$iopadmap$dxport(11) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(9) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(10) I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=$iopadmap$dxport(14) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(13) I2=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$dxport(12) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(9) I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=$iopadmap$dxport(8) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_O I1=$iopadmap$dxport(7) I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$uport(23) I2=$iopadmap$dxport(23) I3=$iopadmap$yport(0) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(22) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(24) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$uport(24) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(23) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(21) I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(25) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=$iopadmap$uport(25) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(24) I3=reset_LUT4_I0_13_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=$iopadmap$uport(24) I2=$iopadmap$dxport(24) I3=$iopadmap$yport(0) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(22) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=$iopadmap$uport(25) I2=$iopadmap$dxport(25) I3=$iopadmap$yport(0) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$dxport(23) I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I2_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I0_13_I2_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I1=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O_LUT4_I3_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I0_50_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110010101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_48_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O_LUT4_I1_O_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I2_7_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_I0_1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I0_44_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_43_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I1_LUT4_I0_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_1_O_LUT4_I2_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O_LUT4_I3_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=reset_LUT4_I0_41_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I3_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_1_I2 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=$iopadmap$xport(28) I1=$iopadmap$xport(30) I2=$iopadmap$xport(29) I3=$iopadmap$xport(31) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$xport(28) I3=$iopadmap$xport(30) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$xport(28) I3=$iopadmap$xport(30) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=$iopadmap$xport(27) I3=$iopadmap$xport(29) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(29) I2=$iopadmap$xport(27) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(28) I3=$iopadmap$xport(26) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(29) I3=$iopadmap$xport(27) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=reset_LUT4_I0_39_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I0_38_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$xport(25) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=$iopadmap$xport(27) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111100010101
+.subckt LUT4 I0=$iopadmap$xport(24) I1=$iopadmap$xport(26) I2=$iopadmap$xport(25) I3=$iopadmap$xport(23) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(27) I2=$iopadmap$xport(25) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(26) I3=$iopadmap$xport(24) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$iopadmap$xport(23) I1=$iopadmap$xport(25) I2=$iopadmap$xport(24) I3=$iopadmap$xport(26) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$xport(23) I3=$iopadmap$xport(25) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(24) I3=$iopadmap$xport(22) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$xport(22) I1=$iopadmap$xport(24) I2=$iopadmap$xport(23) I3=$iopadmap$xport(21) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$iopadmap$xport(20) I1=$iopadmap$xport(22) I2=$iopadmap$xport(21) I3=$iopadmap$xport(19) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$iopadmap$xport(20) I1=$iopadmap$xport(22) I2=$iopadmap$xport(21) I3=$iopadmap$xport(23) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$iopadmap$xport(18) I1=$iopadmap$xport(20) I2=$iopadmap$xport(19) I3=$iopadmap$xport(17) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$iopadmap$xport(18) I1=$iopadmap$xport(20) I2=$iopadmap$xport(19) I3=$iopadmap$xport(21) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(19) I2=$iopadmap$xport(17) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(18) I3=$iopadmap$xport(16) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(17) I2=$iopadmap$xport(15) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(16) I3=$iopadmap$xport(14) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(15) I2=$iopadmap$xport(13) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(14) I3=$iopadmap$xport(12) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(13) I2=$iopadmap$xport(11) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(12) I3=$iopadmap$xport(10) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(11) I2=$iopadmap$xport(9) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(10) I3=$iopadmap$xport(8) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000111111110
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(6) I3=$iopadmap$xport(4) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(5) I3=$iopadmap$xport(3) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$xport(3) I3=$iopadmap$xport(5) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$xport(3) I3=$iopadmap$xport(5) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(4) I2=$iopadmap$xport(2) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(4) I2=$iopadmap$xport(2) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$xport(1) I1=$iopadmap$xport(3) I2=$iopadmap$xport(2) I3=$iopadmap$xport(0) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(4) I3=$iopadmap$xport(2) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(7) I2=$iopadmap$xport(5) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$xport(6) I3=$iopadmap$xport(4) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$xport(7) I3=$iopadmap$xport(5) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$xport(6) I1=$iopadmap$xport(8) I2=$iopadmap$xport(7) I3=$iopadmap$xport(9) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$iopadmap$xport(5) I1=$iopadmap$xport(7) I2=$iopadmap$xport(6) I3=$iopadmap$xport(8) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$iopadmap$xport(7) I1=$iopadmap$xport(9) I2=$iopadmap$xport(8) I3=$iopadmap$xport(6) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$xport(9) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011110001
+.subckt LUT4 I0=$iopadmap$xport(6) I1=$iopadmap$xport(8) I2=$iopadmap$xport(7) I3=$iopadmap$xport(5) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$iopadmap$xport(7) I1=$iopadmap$xport(9) I2=$iopadmap$xport(8) I3=$iopadmap$xport(10) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$xport(9) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=$iopadmap$xport(11) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111100010101
+.subckt LUT4 I0=$iopadmap$xport(8) I1=$iopadmap$xport(10) I2=$iopadmap$xport(9) I3=$iopadmap$xport(7) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$iopadmap$xport(9) I1=$iopadmap$xport(11) I2=$iopadmap$xport(10) I3=$iopadmap$xport(12) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$xport(11) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=$iopadmap$xport(13) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111100010101
+.subckt LUT4 I0=$iopadmap$xport(10) I1=$iopadmap$xport(12) I2=$iopadmap$xport(11) I3=$iopadmap$xport(9) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$iopadmap$xport(11) I1=$iopadmap$xport(13) I2=$iopadmap$xport(12) I3=$iopadmap$xport(14) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$xport(13) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=$iopadmap$xport(15) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111100010101
+.subckt LUT4 I0=$iopadmap$xport(12) I1=$iopadmap$xport(14) I2=$iopadmap$xport(13) I3=$iopadmap$xport(11) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$iopadmap$xport(13) I1=$iopadmap$xport(15) I2=$iopadmap$xport(14) I3=$iopadmap$xport(16) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$xport(15) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=$iopadmap$xport(17) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111100010101
+.subckt LUT4 I0=$iopadmap$xport(14) I1=$iopadmap$xport(16) I2=$iopadmap$xport(15) I3=$iopadmap$xport(13) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$iopadmap$xport(15) I1=$iopadmap$xport(17) I2=$iopadmap$xport(16) I3=$iopadmap$xport(18) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$xport(17) I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=$iopadmap$xport(19) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111100010101
+.subckt LUT4 I0=$iopadmap$xport(16) I1=$iopadmap$xport(18) I2=$iopadmap$xport(17) I3=$iopadmap$xport(15) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$iopadmap$xport(17) I1=$iopadmap$xport(19) I2=$iopadmap$xport(18) I3=$iopadmap$xport(20) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(21) I2=$iopadmap$xport(19) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 I2=$iopadmap$xport(20) I3=$iopadmap$xport(18) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=$iopadmap$xport(19) I1=$iopadmap$xport(21) I2=$iopadmap$xport(20) I3=$iopadmap$xport(22) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(23) I2=$iopadmap$xport(21) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I2 I2=$iopadmap$xport(22) I3=$iopadmap$xport(20) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=$iopadmap$xport(21) I1=$iopadmap$xport(23) I2=$iopadmap$xport(22) I3=$iopadmap$xport(24) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$xport(25) I2=$iopadmap$xport(23) I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=$iopadmap$xport(25) I1=$iopadmap$xport(27) I2=$iopadmap$xport(26) I3=$iopadmap$xport(28) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$iopadmap$xport(26) I1=$iopadmap$xport(28) I2=$iopadmap$xport(27) I3=$iopadmap$xport(25) O=reset_LUT4_I3_2_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I0_39_I3 I2=reset_LUT4_I0_39_I2 I3=reset_LUT4_I0_39_I1 O=reset_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I1_I2 I2=reset_LUT4_I3_3_I2 I3=$iopadmap$reset O=uport_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I0 I1=$iopadmap$uport(0) I2=reset_LUT4_I3_3_I2_LUT4_O_I2 I3=reset_LUT4_I3_3_I2_LUT4_O_I3 O=reset_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$yport(0) I3=$iopadmap$dxport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I2 I1=reset_LUT4_I3_3_I2_LUT4_O_I3 I2=reset_LUT4_I3_3_I2_LUT4_O_I0 I3=$iopadmap$uport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000101110
+.subckt LUT4 I0=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=reset_LUT4_I3_3_I2_LUT4_O_I2_LUT4_I0_O I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I3=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=reset_LUT4_I3_3_I2_LUT4_O_I2_LUT4_I0_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$iopadmap$xport(1) I1=reset_LUT4_I3_1_I2 I2=reset_LUT4_I0_38_I2 I3=$iopadmap$xport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001110111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_3_I2_LUT4_O_I3 I2=$iopadmap$uport(0) I3=reset_LUT4_I3_3_I2_LUT4_O_I0 O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O I1=reset_LUT4_I2_20_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110011001010
+.subckt LUT4 I0=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3 O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$dxport(1) I3=$iopadmap$dxport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001110010101111
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$yport(1) I2=$iopadmap$yport(2) I3=$iopadmap$yport(3) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011100011000111
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(3) I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=$iopadmap$uport(3) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(2) I2=$iopadmap$yport(1) I3=$iopadmap$yport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I1=$iopadmap$uport(2) I2=$iopadmap$dxport(2) I3=$iopadmap$yport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_I1_O_LUT4_I1_O I1=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=reset_LUT4_I0_51_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=reset_LUT4_I2_19_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 O=reset_LUT4_I3_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$uport(0) I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2 I3=reset_LUT4_I3_3_I2_LUT4_O_I0 O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2 O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=$iopadmap$yport(0) I1=$iopadmap$dxport(2) I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=$iopadmap$uport(2) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(1) I2=$iopadmap$yport(1) I3=$iopadmap$yport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$auto$hilomap.cc:47:hilomap_worker$35946 I2=$iopadmap$dxport(0) I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3 O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$yport(2) I2=$iopadmap$yport(1) I3=$iopadmap$yport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(1) I3=$iopadmap$yport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3 I1=$iopadmap$uport(1) I2=$iopadmap$dxport(1) I3=$iopadmap$yport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2 I2=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1 I3=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$auto$hilomap.cc:47:hilomap_worker$35946 I1=$iopadmap$dxport(0) I2=$iopadmap$yport(1) I3=$iopadmap$yport(0) O=reset_LUT4_I3_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=$iopadmap$uport(31) D=uport_ff_CQZ_D(31) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(30) D=uport_ff_CQZ_D(30) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(21) D=uport_ff_CQZ_D(21) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(20) D=uport_ff_CQZ_D(20) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(19) D=uport_ff_CQZ_D(19) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(18) D=uport_ff_CQZ_D(18) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(17) D=uport_ff_CQZ_D(17) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(16) D=uport_ff_CQZ_D(16) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(15) D=uport_ff_CQZ_D(15) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(14) D=uport_ff_CQZ_D(14) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(13) D=uport_ff_CQZ_D(13) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(12) D=uport_ff_CQZ_D(12) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(29) D=uport_ff_CQZ_D(29) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(11) D=uport_ff_CQZ_D(11) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(10) D=uport_ff_CQZ_D(10) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(9) D=uport_ff_CQZ_D(9) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(8) D=uport_ff_CQZ_D(8) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(7) D=uport_ff_CQZ_D(7) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(6) D=uport_ff_CQZ_D(6) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(5) D=uport_ff_CQZ_D(5) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(4) D=uport_ff_CQZ_D(4) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(3) D=uport_ff_CQZ_D(3) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(2) D=uport_ff_CQZ_D(2) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(28) D=uport_ff_CQZ_D(28) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(1) D=uport_ff_CQZ_D(1) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(0) D=uport_ff_CQZ_D(0) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(27) D=uport_ff_CQZ_D(27) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(26) D=uport_ff_CQZ_D(26) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(25) D=uport_ff_CQZ_D(25) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(24) D=uport_ff_CQZ_D(24) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(23) D=uport_ff_CQZ_D(23) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$uport(22) D=uport_ff_CQZ_D(22) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(31) D=xport_ff_CQZ_D(31) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(30) D=xport_ff_CQZ_D(30) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(21) D=xport_ff_CQZ_D(21) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(20) D=xport_ff_CQZ_D(20) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(19) D=xport_ff_CQZ_D(19) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(18) D=xport_ff_CQZ_D(18) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(17) D=xport_ff_CQZ_D(17) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(16) D=xport_ff_CQZ_D(16) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(15) D=xport_ff_CQZ_D(15) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(14) D=xport_ff_CQZ_D(14) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(13) D=xport_ff_CQZ_D(13) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(12) D=xport_ff_CQZ_D(12) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(29) D=xport_ff_CQZ_D(29) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(11) D=xport_ff_CQZ_D(11) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(10) D=xport_ff_CQZ_D(10) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(9) D=xport_ff_CQZ_D(9) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(8) D=xport_ff_CQZ_D(8) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(7) D=xport_ff_CQZ_D(7) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(6) D=xport_ff_CQZ_D(6) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(5) D=xport_ff_CQZ_D(5) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(4) D=xport_ff_CQZ_D(4) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(3) D=xport_ff_CQZ_D(3) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(2) D=xport_ff_CQZ_D(2) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(28) D=xport_ff_CQZ_D(28) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(1) D=xport_ff_CQZ_D(1) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(0) D=xport_ff_CQZ_D(0) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(27) D=xport_ff_CQZ_D(27) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(26) D=xport_ff_CQZ_D(26) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(25) D=xport_ff_CQZ_D(25) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(24) D=xport_ff_CQZ_D(24) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(23) D=xport_ff_CQZ_D(23) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$xport(22) D=xport_ff_CQZ_D(22) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(31) D=yport_ff_CQZ_D(31) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(30) D=yport_ff_CQZ_D(30) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(21) D=yport_ff_CQZ_D(21) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(20) D=yport_ff_CQZ_D(20) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(19) D=yport_ff_CQZ_D(19) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(18) D=yport_ff_CQZ_D(18) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(17) D=yport_ff_CQZ_D(17) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(16) D=yport_ff_CQZ_D(16) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(15) D=yport_ff_CQZ_D(15) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(14) D=yport_ff_CQZ_D(14) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(13) D=yport_ff_CQZ_D(13) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(12) D=yport_ff_CQZ_D(12) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(29) D=yport_ff_CQZ_D(29) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(11) D=yport_ff_CQZ_D(11) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(10) D=yport_ff_CQZ_D(10) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(9) D=yport_ff_CQZ_D(9) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(8) D=yport_ff_CQZ_D(8) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(7) D=yport_ff_CQZ_D(7) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(6) D=yport_ff_CQZ_D(6) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(5) D=yport_ff_CQZ_D(5) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(4) D=yport_ff_CQZ_D(4) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(3) D=yport_ff_CQZ_D(3) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(2) D=yport_ff_CQZ_D(2) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(28) D=yport_ff_CQZ_D(28) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(1) D=yport_ff_CQZ_D(1) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(0) D=yport_ff_CQZ_D(0) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(27) D=yport_ff_CQZ_D(27) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(26) D=yport_ff_CQZ_D(26) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(25) D=yport_ff_CQZ_D(25) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(24) D=yport_ff_CQZ_D(24) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(23) D=yport_ff_CQZ_D(23) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$yport(22) D=yport_ff_CQZ_D(22) QCK=$iopadmap$clk QEN=xport_ff_CQZ_QEN QRT=$auto$hilomap.cc:47:hilomap_worker$35946 QST=$auto$hilomap.cc:47:hilomap_worker$35946
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/diffeq_f_systemC/rtl/diffeq2.v:47.1-62.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.end
diff --git a/BENCHMARK/diffeq_f_systemC/rtl/diffeq2.v b/BENCHMARK/diffeq_f_systemC/rtl/diffeq2.v
new file mode 100644
index 0000000..f88fab2
--- /dev/null
+++ b/BENCHMARK/diffeq_f_systemC/rtl/diffeq2.v
@@ -0,0 +1,63 @@
+
+/*--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+--	File Name 	: diffeq.v
+--	Author(s)	: P. Sridhar
+--	Affiliation	: Laboratory for Digital Design Environments
+--			  Department of Electrical & Computer Engineering
+--			  University of Cincinnati
+--	Date Created	: June 1991.
+--	Introduction	: Behavioral description of a differential equation
+--			  solver written in a synthesizable subset of VHDL.
+--	Source		: Written in HardwareC by Rajesh Gupta, Stanford Univ. 
+--			  Obtained from the Highlevel Synthesis Workshop
+--                        Repository.
+--
+--	Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
+--	Date Modified	: Sept, 91.
+--
+--	Disclaimer	: This comes with absolutely no guarantees of any
+--			  kind (just stating the obvious ...)
+--
+--      Acknowledgement : The Distributed Synthesis Systems research at 
+--                        the Laboratory for Digital Design Environments,
+--                        University of Cincinnati, is sponsored in part 
+--                        by the Defense Advanced Research Projects Agency 
+--                        under order number 7056 monitored by the Federal 
+--                        Bureau of Investigation under contract number 
+--                        J-FBI-89-094.
+--
+--------------------------------------------------------------------------
+-------------------------------------------------------------------------*/
+module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset);
+
+input clk;
+input reset;
+input [31:0]aport;
+input [31:0]dxport;
+output [31:0]xport;
+output [31:0]yport;
+output [31:0]uport;
+reg [31:0]xport;
+reg [31:0]yport;
+reg [31:0]uport;
+wire [31:0]temp;
+
+assign temp = uport * dxport;
+always @(posedge clk )
+begin
+	if (reset == 1'b1)
+	begin
+		xport <= 0;
+		yport <= 0;
+		uport <= 0;
+	end
+else
+  	if (xport < aport) 
+	begin
+		xport <= xport + dxport;
+		yport <= yport + temp;//(uport * dxport);
+		uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport));
+	end
+end
+endmodule
diff --git a/BENCHMARK/i2c_master_top/i2c_master_top_yosys.blif b/BENCHMARK/i2c_master_top/i2c_master_top_yosys.blif
new file mode 100644
index 0000000..68b3e66
--- /dev/null
+++ b/BENCHMARK/i2c_master_top/i2c_master_top_yosys.blif
@@ -0,0 +1,2085 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model i2c_master_top
+.inputs wb_clk_i wb_rst_i arst_i wb_adr_i(0) wb_adr_i(1) wb_adr_i(2) wb_dat_i(0) wb_dat_i(1) wb_dat_i(2) wb_dat_i(3) wb_dat_i(4) wb_dat_i(5) wb_dat_i(6) wb_dat_i(7) wb_we_i wb_stb_i wb_cyc_i scl_pad_i sda_pad_i
+.outputs wb_dat_o(0) wb_dat_o(1) wb_dat_o(2) wb_dat_o(3) wb_dat_o(4) wb_dat_o(5) wb_dat_o(6) wb_dat_o(7) wb_ack_o wb_inta_o scl_pad_o scl_padoen_o sda_pad_o sda_padoen_o tip_o DrivingI2cBusOut TP1 TP2
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_1 a=$auto$hilomap.cc:39:hilomap_worker$5532
+.subckt logic_0 a=byte_controller.bit_controller.al
+.subckt out_buff A=byte_controller.DrivingI2cBusOut Q=DrivingI2cBusOut
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=byte_controller.TP1 Q=TP1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=byte_controller.TP2 Q=TP2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=arst_i Q=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=scl_pad_i Q=byte_controller.bit_controller.scl_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=byte_controller.bit_controller.al Q=scl_pad_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=byte_controller.bit_controller.scl_oen Q=scl_padoen_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=sda_pad_i Q=byte_controller.bit_controller.sda_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=byte_controller.bit_controller.al Q=sda_pad_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=byte_controller.bit_controller.sda_oen Q=sda_padoen_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sr(1) Q=tip_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=wb_ack_i Q=wb_ack_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=wb_adr_i(0) Q=$iopadmap$wb_adr_i(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_adr_i(1) Q=$iopadmap$wb_adr_i(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_adr_i(2) Q=$iopadmap$wb_adr_i(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_clk_i Q=byte_controller.bit_controller.clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_cyc_i Q=$iopadmap$wb_cyc_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_dat_i(0) Q=$iopadmap$wb_dat_i(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_dat_i(1) Q=$iopadmap$wb_dat_i(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_dat_i(2) Q=$iopadmap$wb_dat_i(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_dat_i(3) Q=$iopadmap$wb_dat_i(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_dat_i(4) Q=$iopadmap$wb_dat_i(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_dat_i(5) Q=$iopadmap$wb_dat_i(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_dat_i(6) Q=$iopadmap$wb_dat_i(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_dat_i(7) Q=$iopadmap$wb_dat_i(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=$iopadmap$wb_dat_o(0) Q=wb_dat_o(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$wb_dat_o(1) Q=wb_dat_o(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$wb_dat_o(2) Q=wb_dat_o(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$wb_dat_o(3) Q=wb_dat_o(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$wb_dat_o(4) Q=wb_dat_o(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$wb_dat_o(5) Q=wb_dat_o(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$wb_dat_o(6) Q=wb_dat_o(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$wb_dat_o(7) Q=wb_dat_o(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$wb_inta_o Q=wb_inta_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=wb_rst_i Q=byte_controller.bit_controller.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_stb_i Q=$iopadmap$wb_stb_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=wb_we_i Q=$iopadmap$wb_we_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt LUT4 I0=byte_controller.core_cmd(4) I1=byte_controller.core_cmd(3) I2=byte_controller.core_cmd(0) I3=byte_controller.core_cmd(2) O=byte_controller.DrivingI2cBusOut
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111110
+.subckt ff CQZ=byte_controller.TP1 D=TP1_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O I2=byte_controller.TP1 I3=byte_controller.bit_controller.clk_cnt(0) O=TP1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=byte_controller.bit_controller.cnt(2) I1=byte_controller.bit_controller.cnt(3) I2=byte_controller.TP2 I3=byte_controller.TP1 O=byte_controller.bit_controller.cnt_ff_CQZ_11_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=byte_controller.TP2 D=TP2_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(1) I1=byte_controller.TP2 I2=byte_controller.TP1 I3=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O O=TP2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101011000011
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(1) I2=byte_controller.read I3=al O=al_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=$iopadmap$wb_adr_i(1) I1=byte_controller.din(5) I2=al_LUT4_I3_O I3=$iopadmap$wb_adr_i(0) O=al_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt ff CQZ=al D=al_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:283.2-304.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=al I2=byte_controller.bit_controller.rst I3=byte_controller.start O=al_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cr_LUT4_I1_I0 I1=byte_controller.ack_in I2=byte_controller.din(3) I3=cr_LUT4_I1_I3 O=byte_controller.ack_in_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=byte_controller.ack_in_LUT4_I1_O_LUT4_I3_I0 I1=byte_controller.ack_in_LUT4_I1_O_LUT4_I3_I1 I2=$iopadmap$wb_adr_i(2) I3=byte_controller.ack_in_LUT4_I1_O O=cr_LUT4_I1_O_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(11) I1=byte_controller.bit_controller.clk_cnt(3) I2=cr_LUT4_I1_O_LUT4_I3_I0_LUT4_O_I3 I3=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I0_LUT4_O_I3 O=byte_controller.ack_in_LUT4_I1_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=ctr(3) I1=$iopadmap$wb_adr_i(1) I2=byte_controller.dout(3) I3=irq_flag_LUT4_I0_I3_LUT4_I2_O O=byte_controller.ack_in_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=byte_controller.c_state(5) I1=byte_controller.bit_controller.cmd_ack I2=byte_controller.c_state(3) I3=byte_controller.ack_in O=byte_controller.ack_in_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt ff CQZ=byte_controller.ack_in D=wb_dat_i_LUT4_I2_4_O(3) QCK=byte_controller.bit_controller.clk QEN=byte_controller.ack_in_ff_CQZ_QEN QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:221.2-238.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=irq_flag_LUT4_I0_I1 I1=byte_controller.bit_controller.ena I2=wb_we_i_LUT4_I2_O I3=byte_controller.bit_controller.rst O=byte_controller.ack_in_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.ack_out I3=byte_controller.bit_controller.rst O=rxack_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=byte_controller.ack_out D=byte_controller.ack_out_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.ack_out_ff_CQZ_QEN QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.rst I2=byte_controller.c_state(3) I3=byte_controller.bit_controller.cmd_ack O=byte_controller.ack_out_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(1) I2=byte_controller.stop I3=byte_controller.bit_controller.busy O=byte_controller.bit_controller.busy_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=$iopadmap$wb_adr_i(1) I1=byte_controller.din(6) I2=byte_controller.bit_controller.busy_LUT4_I3_O I3=$iopadmap$wb_adr_i(0) O=byte_controller.bit_controller.busy_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt ff CQZ=byte_controller.bit_controller.busy D=byte_controller.bit_controller.busy_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:343.5-346.76|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.cSCL(0) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.cSCL_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.cSCL(1) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.fSCL_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=byte_controller.bit_controller.cSCL(1) D=byte_controller.bit_controller.cSCL_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:249.5-264.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.bit_controller.cSCL(0) D=scl_pad_i_LUT4_I2_O QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:249.5-264.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.cSDA(0) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.cSDA_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.cSDA(1) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.fSDA_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=byte_controller.bit_controller.cSDA(1) D=byte_controller.bit_controller.cSDA_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:249.5-264.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.bit_controller.cSDA(0) D=sda_pad_i_LUT4_I2_O QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:249.5-264.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.bit_controller.c_state(17) D=byte_controller.bit_controller.c_state_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.bit_controller.c_state(16) D=byte_controller.bit_controller.c_state_ff_CQZ_1_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.bit_controller.c_state(7) D=byte_controller.bit_controller.c_state_ff_CQZ_10_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(8) I1=byte_controller.bit_controller.c_state(7) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(6) D=byte_controller.bit_controller.c_state_ff_CQZ_11_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(7) I1=byte_controller.bit_controller.c_state(6) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(5) D=byte_controller.bit_controller.c_state_ff_CQZ_12_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(6) I1=byte_controller.bit_controller.c_state(5) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(4) D=byte_controller.bit_controller.c_state_ff_CQZ_13_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state_ff_CQZ_13_D_LUT4_O_I0 I1=byte_controller.core_cmd(2) I2=byte_controller.bit_controller.c_state_ff_CQZ_D_LUT4_O_I2 I3=byte_controller.bit_controller.c_state(4) O=byte_controller.bit_controller.c_state_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.c_state_ff_CQZ_13_D_LUT4_O_I0 I3=byte_controller.core_cmd(2) O=byte_controller.bit_controller.c_state_ff_CQZ_13_D_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.c_state(0) I2=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I3 I3=byte_controller.core_cmd(1) O=byte_controller.bit_controller.c_state_ff_CQZ_13_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=byte_controller.bit_controller.c_state(3) D=byte_controller.bit_controller.c_state_ff_CQZ_14_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(4) I1=byte_controller.bit_controller.c_state(3) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(2) D=byte_controller.bit_controller.c_state_ff_CQZ_15_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(3) I1=byte_controller.bit_controller.c_state(2) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(1) D=byte_controller.bit_controller.c_state_ff_CQZ_16_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(2) I1=byte_controller.bit_controller.c_state(1) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(0) D=byte_controller.bit_controller.c_state_ff_CQZ_17_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt LUT4 I0=byte_controller.core_cmd(3) I1=byte_controller.core_cmd(4) I2=byte_controller.bit_controller.c_state_ff_CQZ_13_D_LUT4_O_I0_LUT4_I2_O I3=byte_controller.bit_controller.c_state_ff_CQZ_17_D_LUT4_O_I3 O=byte_controller.bit_controller.c_state_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100010000
+.subckt LUT4 I0=byte_controller.bit_controller.c_state_ff_CQZ_17_D_LUT4_O_I3_LUT4_O_I0 I1=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I2 I2=byte_controller.bit_controller.c_state(0) I3=byte_controller.bit_controller.c_state_ff_CQZ_D_LUT4_O_I2 O=byte_controller.bit_controller.c_state_ff_CQZ_17_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001110111
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.c_state(9) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.c_state_ff_CQZ_17_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(17) I1=byte_controller.bit_controller.c_state(16) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(15) D=byte_controller.bit_controller.c_state_ff_CQZ_2_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(16) I1=byte_controller.bit_controller.c_state(15) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(14) D=byte_controller.bit_controller.c_state_ff_CQZ_3_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(15) I1=byte_controller.bit_controller.c_state(14) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(13) D=byte_controller.bit_controller.c_state_ff_CQZ_4_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(14) I1=byte_controller.bit_controller.c_state(13) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(12) D=byte_controller.bit_controller.c_state_ff_CQZ_5_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state_ff_CQZ_13_D_LUT4_O_I0_LUT4_I2_O I1=byte_controller.core_cmd(3) I2=byte_controller.bit_controller.c_state_ff_CQZ_D_LUT4_O_I2 I3=byte_controller.bit_controller.c_state(12) O=byte_controller.bit_controller.c_state_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt ff CQZ=byte_controller.bit_controller.c_state(11) D=byte_controller.bit_controller.c_state_ff_CQZ_6_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(12) I1=byte_controller.bit_controller.c_state(11) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(10) D=byte_controller.bit_controller.c_state_ff_CQZ_7_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(11) I1=byte_controller.bit_controller.c_state(10) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(9) D=byte_controller.bit_controller.c_state_ff_CQZ_8_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(10) I1=byte_controller.bit_controller.c_state(9) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt ff CQZ=byte_controller.bit_controller.c_state(8) D=byte_controller.bit_controller.c_state_ff_CQZ_9_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.c_state_ff_CQZ_9_D_LUT4_O_I0 I1=byte_controller.bit_controller.c_state(8) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.c_state(0) I3=byte_controller.core_cmd(1) O=byte_controller.bit_controller.c_state_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.c_state_ff_CQZ_D_LUT4_O_I1 I2=byte_controller.bit_controller.c_state_ff_CQZ_D_LUT4_O_I2 I3=byte_controller.bit_controller.c_state(17) O=byte_controller.bit_controller.c_state_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.c_state_ff_CQZ_13_D_LUT4_O_I0_LUT4_I2_O I2=byte_controller.core_cmd(4) I3=byte_controller.core_cmd(3) O=byte_controller.bit_controller.c_state_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.clk_en O=byte_controller.bit_controller.c_state_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=byte_controller.bit_controller.clk_en D=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt ff CQZ=byte_controller.bit_controller.cmd_ack D=byte_controller.bit_controller.cmd_ack_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:399.5-591.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I0 I1=byte_controller.shift_LUT4_I2_I0 I2=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I2 I3=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I3 O=byte_controller.bit_controller.cmd_ack_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=byte_controller.bit_controller.c_state(10) I3=byte_controller.shift_LUT4_I2_I0 O=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.c_state(14) I2=byte_controller.bit_controller.c_state(6) I3=byte_controller.bit_controller.c_state(2) O=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.c_state(5) I2=byte_controller.bit_controller.c_state(13) I3=byte_controller.bit_controller.c_state(1) O=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.clk_en I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=byte_controller.bit_controller.cnt(15) D=byte_controller.bit_controller.cnt_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.cnt(14) D=byte_controller.bit_controller.cnt_ff_CQZ_1_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.cnt(5) D=byte_controller.bit_controller.cnt_ff_CQZ_10_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O I2=byte_controller.bit_controller.cnt_ff_CQZ_10_D_LUT4_O_I2 I3=byte_controller.bit_controller.clk_cnt(5) O=byte_controller.bit_controller.cnt_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt(5) I2=byte_controller.bit_controller.cnt_ff_CQZ_11_D_LUT4_O_I1 I3=byte_controller.bit_controller.cnt(4) O=byte_controller.bit_controller.cnt_ff_CQZ_10_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt ff CQZ=byte_controller.bit_controller.cnt(4) D=byte_controller.bit_controller.cnt_ff_CQZ_11_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(4) I1=byte_controller.bit_controller.cnt_ff_CQZ_11_D_LUT4_O_I1 I2=byte_controller.bit_controller.cnt(4) I3=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O O=byte_controller.bit_controller.cnt_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt ff CQZ=byte_controller.bit_controller.cnt(3) D=byte_controller.bit_controller.cnt_ff_CQZ_12_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O I2=byte_controller.bit_controller.cnt_ff_CQZ_12_D_LUT4_O_I2 I3=byte_controller.bit_controller.clk_cnt(3) O=byte_controller.bit_controller.cnt_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=byte_controller.bit_controller.cnt(2) I1=byte_controller.TP2 I2=byte_controller.TP1 I3=byte_controller.bit_controller.cnt(3) O=byte_controller.bit_controller.cnt_ff_CQZ_12_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000001
+.subckt ff CQZ=byte_controller.bit_controller.cnt(2) D=byte_controller.bit_controller.cnt_ff_CQZ_13_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O I2=byte_controller.bit_controller.cnt_ff_CQZ_13_D_LUT4_O_I2 I3=byte_controller.bit_controller.clk_cnt(2) O=byte_controller.bit_controller.cnt_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt(2) I2=byte_controller.TP1 I3=byte_controller.TP2 O=byte_controller.bit_controller.cnt_ff_CQZ_13_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_1_D_LUT4_O_I1 I2=byte_controller.bit_controller.clk_cnt(14) I3=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O O=byte_controller.bit_controller.cnt_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=byte_controller.bit_controller.cnt(13) I1=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1 I2=byte_controller.bit_controller.cnt(14) I3=byte_controller.bit_controller.dSCL_LUT4_I2_O O=byte_controller.bit_controller.cnt_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100000000
+.subckt ff CQZ=byte_controller.bit_controller.cnt(13) D=byte_controller.bit_controller.cnt_ff_CQZ_2_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(13) I1=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1 I2=byte_controller.bit_controller.cnt(13) I3=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O O=byte_controller.bit_controller.cnt_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt LUT4 I0=byte_controller.bit_controller.cnt_ff_CQZ_11_D_LUT4_O_I1 I1=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I2=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I3=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3 O=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I3=byte_controller.bit_controller.cnt_ff_CQZ_11_D_LUT4_O_I1 O=byte_controller.bit_controller.cnt_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt(6) I2=byte_controller.bit_controller.cnt(5) I3=byte_controller.bit_controller.cnt(4) O=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt(7) I2=byte_controller.bit_controller.cnt(9) I3=byte_controller.bit_controller.cnt(8) O=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt(11) I2=byte_controller.bit_controller.cnt(10) I3=byte_controller.bit_controller.cnt(12) O=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt ff CQZ=byte_controller.bit_controller.cnt(12) D=byte_controller.bit_controller.cnt_ff_CQZ_3_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O I2=byte_controller.bit_controller.cnt_ff_CQZ_3_D_LUT4_O_I2 I3=byte_controller.bit_controller.clk_cnt(12) O=byte_controller.bit_controller.cnt_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=byte_controller.bit_controller.cnt(10) I1=byte_controller.bit_controller.cnt(11) I2=byte_controller.bit_controller.cnt_ff_CQZ_5_D_LUT4_O_I1 I3=byte_controller.bit_controller.cnt(12) O=byte_controller.bit_controller.cnt_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100010000
+.subckt ff CQZ=byte_controller.bit_controller.cnt(11) D=byte_controller.bit_controller.cnt_ff_CQZ_4_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O I2=byte_controller.bit_controller.cnt_ff_CQZ_4_D_LUT4_O_I2 I3=byte_controller.bit_controller.clk_cnt(11) O=byte_controller.bit_controller.cnt_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt(11) I2=byte_controller.bit_controller.cnt_ff_CQZ_5_D_LUT4_O_I1 I3=byte_controller.bit_controller.cnt(10) O=byte_controller.bit_controller.cnt_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt ff CQZ=byte_controller.bit_controller.cnt(10) D=byte_controller.bit_controller.cnt_ff_CQZ_5_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(10) I1=byte_controller.bit_controller.cnt_ff_CQZ_5_D_LUT4_O_I1 I2=byte_controller.bit_controller.cnt(10) I3=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O O=byte_controller.bit_controller.cnt_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I3=byte_controller.bit_controller.cnt_ff_CQZ_8_D_LUT4_O_I1 O=byte_controller.bit_controller.cnt_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=byte_controller.bit_controller.cnt(9) D=byte_controller.bit_controller.cnt_ff_CQZ_6_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O I2=byte_controller.bit_controller.cnt_ff_CQZ_6_D_LUT4_O_I2 I3=byte_controller.bit_controller.clk_cnt(9) O=byte_controller.bit_controller.cnt_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=byte_controller.bit_controller.cnt(8) I1=byte_controller.bit_controller.cnt(7) I2=byte_controller.bit_controller.cnt_ff_CQZ_8_D_LUT4_O_I1 I3=byte_controller.bit_controller.cnt(9) O=byte_controller.bit_controller.cnt_ff_CQZ_6_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100010000
+.subckt ff CQZ=byte_controller.bit_controller.cnt(8) D=byte_controller.bit_controller.cnt_ff_CQZ_7_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O I2=byte_controller.bit_controller.cnt_ff_CQZ_7_D_LUT4_O_I2 I3=byte_controller.bit_controller.clk_cnt(8) O=byte_controller.bit_controller.cnt_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt(8) I2=byte_controller.bit_controller.cnt_ff_CQZ_8_D_LUT4_O_I1 I3=byte_controller.bit_controller.cnt(7) O=byte_controller.bit_controller.cnt_ff_CQZ_7_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt ff CQZ=byte_controller.bit_controller.cnt(7) D=byte_controller.bit_controller.cnt_ff_CQZ_8_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(7) I1=byte_controller.bit_controller.cnt_ff_CQZ_8_D_LUT4_O_I1 I2=byte_controller.bit_controller.cnt(7) I3=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O O=byte_controller.bit_controller.cnt_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt ff CQZ=byte_controller.bit_controller.cnt(6) D=byte_controller.bit_controller.cnt_ff_CQZ_9_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.slave_wait_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:222.5-242.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O I2=byte_controller.bit_controller.cnt_ff_CQZ_9_D_LUT4_O_I2 I3=byte_controller.bit_controller.clk_cnt(6) O=byte_controller.bit_controller.cnt_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=byte_controller.bit_controller.cnt(4) I1=byte_controller.bit_controller.cnt(5) I2=byte_controller.bit_controller.cnt_ff_CQZ_11_D_LUT4_O_I1 I3=byte_controller.bit_controller.cnt(6) O=byte_controller.bit_controller.cnt_ff_CQZ_9_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100010000
+.subckt LUT4 I0=byte_controller.bit_controller.dSCL_LUT4_I2_O I1=byte_controller.bit_controller.cnt(15) I2=byte_controller.bit_controller.clk_cnt(15) I3=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3 O=byte_controller.bit_controller.cnt_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100001110000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3 I2=byte_controller.bit_controller.cnt(15) I3=byte_controller.bit_controller.dSCL_LUT4_I2_O O=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=byte_controller.bit_controller.cnt(14) I1=byte_controller.bit_controller.cnt(13) I2=byte_controller.bit_controller.cnt_ff_CQZ_2_D_LUT4_O_I1 I3=byte_controller.bit_controller.dSCL_LUT4_I2_O O=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=byte_controller.bit_controller.sSCL I1=byte_controller.bit_controller.scl_oen I2=byte_controller.bit_controller.dSCL I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.dSCL_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.sSCL I3=byte_controller.bit_controller.dSCL O=byte_controller.bit_controller.dout_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=byte_controller.bit_controller.dSCL D=byte_controller.bit_controller.dSCL_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:294.5-318.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.sSCL I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.dSCL_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.dSDA I2=byte_controller.bit_controller.sSCL I3=byte_controller.bit_controller.dSDA_ff_CQZ_D O=byte_controller.bit_controller.sta_condition_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=byte_controller.bit_controller.rst I1=byte_controller.bit_controller.dSDA I2=byte_controller.bit_controller.sSCL I3=byte_controller.bit_controller.sSDA O=byte_controller.bit_controller.sto_condition_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt ff CQZ=byte_controller.bit_controller.dSDA D=byte_controller.bit_controller.dSDA_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:294.5-318.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.dout I3=byte_controller.bit_controller.rst O=byte_controller.ack_out_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=byte_controller.bit_controller.dout D=byte_controller.bit_controller.sSDA QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.dout_ff_CQZ_QEN QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:373.5-374.41|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=byte_controller.bit_controller.dscl_oen I1=byte_controller.bit_controller.scl_oen I2=byte_controller.bit_controller.slave_wait I3=byte_controller.bit_controller.sSCL O=byte_controller.bit_controller.slave_wait_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt ff CQZ=byte_controller.bit_controller.dscl_oen D=byte_controller.bit_controller.scl_oen QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:207.5-208.30|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.ena I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.ena_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=byte_controller.bit_controller.ena D=$auto$hilomap.cc:39:hilomap_worker$5532 QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt ff CQZ=byte_controller.bit_controller.fSCL(2) D=byte_controller.bit_controller.fSCL_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.fSCL_ff_CQZ_QEN QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:275.5-290.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt ff CQZ=byte_controller.bit_controller.fSCL(1) D=byte_controller.bit_controller.fSCL_ff_CQZ_1_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.fSCL_ff_CQZ_QEN QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:275.5-290.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.fSCL(0) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.fSCL_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=byte_controller.bit_controller.fSCL(0) D=byte_controller.bit_controller.fSCL_ff_CQZ_2_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.fSCL_ff_CQZ_QEN QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:275.5-290.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.fSCL(1) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.fSCL_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=byte_controller.bit_controller.fSDA(2) D=byte_controller.bit_controller.fSDA_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.fSCL_ff_CQZ_QEN QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:275.5-290.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt ff CQZ=byte_controller.bit_controller.fSDA(1) D=byte_controller.bit_controller.fSDA_ff_CQZ_1_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.fSCL_ff_CQZ_QEN QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:275.5-290.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.fSDA(0) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.fSDA_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=byte_controller.bit_controller.fSDA(0) D=byte_controller.bit_controller.fSDA_ff_CQZ_2_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.fSCL_ff_CQZ_QEN QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:275.5-290.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.fSDA(1) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.fSDA_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(13) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(12) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_1_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(3) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_10_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(5) I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_10_D_LUT4_O_I1 I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt(2) I1=byte_controller.bit_controller.filter_cnt(1) I2=byte_controller.bit_controller.filter_cnt(0) I3=byte_controller.bit_controller.filter_cnt(3) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_10_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000001
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(2) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_11_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_11_D_LUT4_O_I1 I2=byte_controller.bit_controller.clk_cnt(4) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt(1) I1=byte_controller.bit_controller.filter_cnt(0) I2=byte_controller.bit_controller.filter_cnt(2) I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_11_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(1) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_12_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_12_D_LUT4_O_I1 I2=byte_controller.bit_controller.clk_cnt(3) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.ena_LUT4_I2_O I2=byte_controller.bit_controller.filter_cnt(0) I3=byte_controller.bit_controller.filter_cnt(1) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_12_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(0) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_13_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(2) I1=byte_controller.bit_controller.filter_cnt(0) I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt_ff_CQZ_1_D_LUT4_O_I0 I1=byte_controller.bit_controller.filter_cnt(12) I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_1_D_LUT4_O_I2 I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001110000000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.clk_cnt(14) I3=byte_controller.bit_controller.filter_cnt(13) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I2 I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=byte_controller.bit_controller.filter_cnt_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt(12) I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I2 I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3 O=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.filter_cnt(11) I3=byte_controller.bit_controller.filter_cnt(10) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(11) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_2_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O I1=byte_controller.bit_controller.clk_cnt(13) I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_2_D_LUT4_O_I2 I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.filter_cnt(11) I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 I3=byte_controller.bit_controller.filter_cnt(10) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(10) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D_LUT4_O_I1 I2=byte_controller.bit_controller.clk_cnt(12) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.ena_LUT4_I2_O I2=byte_controller.bit_controller.filter_cnt(10) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3 O=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.filter_cnt(7) I2=byte_controller.bit_controller.filter_cnt(9) I3=byte_controller.bit_controller.filter_cnt(8) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(9) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_4_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.ena_LUT4_I2_O I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_4_D_LUT4_O_I3 O=byte_controller.bit_controller.filter_cnt_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(11) I1=byte_controller.bit_controller.filter_cnt(13) I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2 I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2 O=byte_controller.bit_controller.filter_cnt_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101011110000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt(8) I1=byte_controller.bit_controller.filter_cnt(7) I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3 I3=byte_controller.bit_controller.filter_cnt(9) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100010000
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(8) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_5_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_5_D_LUT4_O_I1 I2=byte_controller.bit_controller.clk_cnt(10) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt(7) I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3 I2=byte_controller.bit_controller.filter_cnt(8) I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(7) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D_LUT4_O_I1 I2=byte_controller.bit_controller.clk_cnt(9) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.ena_LUT4_I2_O I2=byte_controller.bit_controller.filter_cnt(7) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3 O=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt(4) I1=byte_controller.bit_controller.filter_cnt(5) I2=byte_controller.bit_controller.filter_cnt(6) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=byte_controller.bit_controller.filter_cnt_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(6) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_7_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(8) I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_7_D_LUT4_O_I1 I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt(4) I1=byte_controller.bit_controller.filter_cnt(5) I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=byte_controller.bit_controller.filter_cnt(6) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_7_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100010000
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(5) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_8_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_8_D_LUT4_O_I1 I2=byte_controller.bit_controller.clk_cnt(7) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt(4) I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I2=byte_controller.bit_controller.filter_cnt(5) I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt ff CQZ=byte_controller.bit_controller.filter_cnt(4) D=byte_controller.bit_controller.filter_cnt_ff_CQZ_9_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:268.5-272.58|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.filter_cnt_ff_CQZ_9_D_LUT4_O_I1 I2=byte_controller.bit_controller.clk_cnt(6) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.ena_LUT4_I2_O I2=byte_controller.bit_controller.filter_cnt(4) I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=byte_controller.bit_controller.filter_cnt_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=byte_controller.bit_controller.filter_cnt(2) I1=byte_controller.bit_controller.filter_cnt(3) I2=byte_controller.bit_controller.filter_cnt(1) I3=byte_controller.bit_controller.filter_cnt(0) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(15) I1=byte_controller.bit_controller.filter_cnt(13) I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2 I3=byte_controller.bit_controller.ena_LUT4_I2_O O=byte_controller.bit_controller.filter_cnt_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110000000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2 I3=byte_controller.bit_controller.filter_cnt(13) O=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.filter_cnt_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O O=byte_controller.bit_controller.fSCL_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=byte_controller.bit_controller.sSCL D=byte_controller.bit_controller.sSCL_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:294.5-318.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt LUT4 I0=byte_controller.bit_controller.fSCL(1) I1=byte_controller.bit_controller.fSCL(2) I2=byte_controller.bit_controller.fSCL(0) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.sSCL_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111101000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.sSDA I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.dSDA_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=byte_controller.bit_controller.sSDA D=byte_controller.bit_controller.sSDA_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:294.5-318.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt LUT4 I0=byte_controller.bit_controller.fSDA(1) I1=byte_controller.bit_controller.fSDA(2) I2=byte_controller.bit_controller.fSDA(0) I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.sSDA_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111101000
+.subckt ff CQZ=byte_controller.bit_controller.scl_oen D=byte_controller.bit_controller.scl_oen_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.scl_oen_ff_CQZ_QEN QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:399.5-591.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.scl_oen_ff_CQZ_D_LUT4_O_I3 O=byte_controller.bit_controller.scl_oen_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.scl_oen_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I2 O=byte_controller.bit_controller.scl_oen_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.rst I1=byte_controller.bit_controller.c_state(4) I2=byte_controller.bit_controller.c_state(8) I3=byte_controller.bit_controller.c_state(12) O=byte_controller.bit_controller.scl_oen_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.c_state_ff_CQZ_D_LUT4_O_I2 I2=byte_controller.bit_controller.scl_oen_ff_CQZ_QEN_LUT4_O_I2 I3=byte_controller.bit_controller.scl_oen_ff_CQZ_D_LUT4_O_I3 O=byte_controller.bit_controller.scl_oen_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(2) I1=byte_controller.bit_controller.c_state(6) I2=byte_controller.bit_controller.scl_oen_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2 I3=byte_controller.bit_controller.scl_oen_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=byte_controller.bit_controller.scl_oen_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(14) I1=byte_controller.bit_controller.c_state(10) I2=byte_controller.bit_controller.c_state(11) I3=byte_controller.bit_controller.c_state(15) O=byte_controller.bit_controller.scl_oen_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(3) I1=byte_controller.bit_controller.c_state(9) I2=byte_controller.bit_controller.c_state(7) I3=byte_controller.bit_controller.c_state(16) O=byte_controller.bit_controller.scl_oen_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=byte_controller.bit_controller.sda_oen D=byte_controller.bit_controller.sda_oen_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.sda_oen_ff_CQZ_QEN QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:399.5-591.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=byte_controller.core_txd_LUT4_I1_I0 I1=byte_controller.core_txd_LUT4_I1_I3 I2=byte_controller.bit_controller.sda_oen_ff_CQZ_QEN_LUT4_O_I2 I3=byte_controller.bit_controller.c_state_ff_CQZ_D_LUT4_O_I2 O=byte_controller.bit_controller.sda_oen_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(13) I1=byte_controller.bit_controller.c_state(12) I2=byte_controller.bit_controller.cmd_ack_ff_CQZ_D_LUT4_O_I3 I3=byte_controller.bit_controller.scl_oen_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2 O=byte_controller.bit_controller.sda_oen_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.slave_wait I3=byte_controller.bit_controller.cnt_ff_CQZ_D_LUT4_O_I3_LUT4_I1_O O=byte_controller.bit_controller.slave_wait_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=byte_controller.bit_controller.slave_wait D=byte_controller.bit_controller.slave_wait_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:212.5-214.87|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.busy I1=byte_controller.bit_controller.sta_condition I2=byte_controller.bit_controller.sto_condition I3=byte_controller.bit_controller.rst O=byte_controller.bit_controller.busy_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt ff CQZ=byte_controller.bit_controller.sta_condition D=byte_controller.bit_controller.sta_condition_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:324.5-339.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.bit_controller.sto_condition D=byte_controller.bit_controller.sto_condition_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_bit_ctrl.v:324.5-339.10|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:166.22-186.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.c_state(6) D=byte_controller.c_state_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.c_state(5) D=byte_controller.c_state_ff_CQZ_1_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.rst I1=byte_controller.c_state_ff_CQZ_1_D_LUT4_O_I1 I2=byte_controller.read I3=byte_controller.c_state_ff_CQZ_1_D_LUT4_O_I3 O=byte_controller.c_state_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100010000
+.subckt LUT4 I0=byte_controller.start I1=byte_controller.cmd_ack_LUT4_I3_O_LUT4_I3_O I2=byte_controller.bit_controller.cmd_ack I3=byte_controller.c_state(6) O=byte_controller.c_state_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.c_state(5) I2=byte_controller.bit_controller.rst I3=byte_controller.c_state_ff_CQZ_2_D_LUT4_O_I0 O=byte_controller.c_state_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=byte_controller.c_state(4) D=byte_controller.c_state_ff_CQZ_2_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I0 I1=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I1 I2=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I2 I3=byte_controller.c_state_ff_CQZ_2_D O=byte_controller.core_cmd_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.c_state(5) I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I3 O=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=byte_controller.c_state(5) I1=byte_controller.c_state(2) I2=byte_controller.c_state(3) I3=byte_controller.c_state(4) O=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=byte_controller.c_state_ff_CQZ_2_D_LUT4_O_I0 I1=byte_controller.c_state(4) I2=byte_controller.c_state_ff_CQZ_2_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.c_state_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.cmd_ack I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I3 O=byte_controller.c_state_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.read I1=byte_controller.c_state(6) I2=byte_controller.bit_controller.cmd_ack I3=byte_controller.c_state(1) O=byte_controller.c_state_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt ff CQZ=byte_controller.c_state(3) D=byte_controller.c_state_ff_CQZ_3_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0 I1=byte_controller.c_state(3) I2=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I2 I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I3 O=byte_controller.c_state_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt LUT4 I0=byte_controller.c_state(1) I1=byte_controller.c_state(6) I2=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I2 I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0 O=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=byte_controller.bit_controller.rst I1=byte_controller.cmd_ack_LUT4_I3_O_LUT4_I3_O I2=byte_controller.c_state_ff_CQZ_5_D_LUT4_I3_I2 I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0_LUT4_I3_O O=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.cmd_ack O=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I2 I2=byte_controller.c_state(3) I3=byte_controller.c_state(2) O=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=byte_controller.c_state(5) I1=byte_controller.c_state(4) I2=byte_controller.bit_controller.rst I3=byte_controller.bit_controller.cmd_ack O=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt ff CQZ=byte_controller.c_state(2) D=byte_controller.c_state_ff_CQZ_4_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.write I1=byte_controller.cmd_ack_LUT4_I3_O_LUT4_I3_O I2=byte_controller.c_state_ff_CQZ_5_D_LUT4_O_I2 I3=byte_controller.c_state_ff_CQZ_4_D_LUT4_O_I3 O=byte_controller.c_state_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000011111111
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.c_state_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I1 I2=byte_controller.c_state(2) I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0 O=byte_controller.c_state_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=byte_controller.bit_controller.rst I1=byte_controller.stop I2=byte_controller.c_state(3) I3=byte_controller.bit_controller.cmd_ack O=byte_controller.c_state_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt ff CQZ=byte_controller.c_state(1) D=byte_controller.c_state_ff_CQZ_5_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.c_state_ff_CQZ_5_D_LUT4_I3_I2 I3=byte_controller.c_state_ff_CQZ_5_D O=byte_controller.core_cmd_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I2 I2=byte_controller.c_state(6) I3=byte_controller.c_state(1) O=byte_controller.c_state_ff_CQZ_5_D_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.write I2=byte_controller.c_state_ff_CQZ_5_D_LUT4_O_I2 I3=byte_controller.cmd_ack_LUT4_I3_O_LUT4_I3_O O=byte_controller.c_state_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.rst I2=byte_controller.start I3=byte_controller.read O=byte_controller.c_state_ff_CQZ_5_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt ff CQZ=byte_controller.c_state(0) D=byte_controller.c_state_ff_CQZ_6_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.c_state_ff_CQZ_6_D_LUT4_O_I1 I2=byte_controller.c_state(0) I3=byte_controller.cmd_ack_LUT4_I3_O O=byte_controller.c_state_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.rst I2=byte_controller.bit_controller.cmd_ack I3=byte_controller.cmd_ack_ff_CQZ_D_LUT4_O_I3 O=byte_controller.c_state_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=byte_controller.start I1=byte_controller.cmd_ack_LUT4_I3_O_LUT4_I3_O I2=byte_controller.c_state_ff_CQZ_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.c_state_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=byte_controller.c_state_ff_CQZ_D_LUT4_O_I2 I1=byte_controller.c_state(1) I2=byte_controller.bit_controller.rst I3=byte_controller.read O=byte_controller.core_cmd_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.c_state(6) I3=byte_controller.bit_controller.cmd_ack O=byte_controller.c_state_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.ack_in_ff_CQZ_QEN I2=byte_controller.cmd_ack I3=wb_we_i_LUT4_I2_O O=byte_controller.cmd_ack_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=byte_controller.write I1=byte_controller.stop I2=byte_controller.read I3=byte_controller.cmd_ack O=byte_controller.cmd_ack_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.c_state(0) I3=byte_controller.cmd_ack_LUT4_I3_O O=byte_controller.cmd_ack_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=byte_controller.cmd_ack D=byte_controller.cmd_ack_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.cmd_ack I2=byte_controller.bit_controller.rst I3=byte_controller.cmd_ack_ff_CQZ_D_LUT4_O_I3 O=byte_controller.cmd_ack_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.c_state(2) I2=byte_controller.c_state(3) I3=byte_controller.stop O=byte_controller.cmd_ack_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt ff CQZ=byte_controller.core_cmd(4) D=byte_controller.core_cmd_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.core_cmd(3) D=byte_controller.core_cmd_ff_CQZ_1_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I1=byte_controller.core_cmd(3) I2=byte_controller.core_cmd_ff_CQZ_1_D_LUT4_O_I2 I3=byte_controller.core_cmd_ff_CQZ_1_D_LUT4_O_I3 O=byte_controller.core_cmd_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111110100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.c_state(3) I2=byte_controller.bit_controller.cmd_ack I3=byte_controller.core_cmd_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I3 O=byte_controller.core_cmd_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.stop I2=byte_controller.bit_controller.rst I3=byte_controller.c_state(2) O=byte_controller.core_cmd_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=byte_controller.write I1=byte_controller.c_state_ff_CQZ_5_D_LUT4_I3_I2 I2=byte_controller.c_state_ff_CQZ_5_D_LUT4_O_I2 I3=byte_controller.cmd_ack_LUT4_I3_O_LUT4_I3_O O=byte_controller.core_cmd_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt ff CQZ=byte_controller.core_cmd(2) D=byte_controller.core_cmd_ff_CQZ_2_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.core_cmd_ff_CQZ_2_D_LUT4_O_I1 I2=byte_controller.core_cmd(2) I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O O=byte_controller.core_cmd_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt ff CQZ=byte_controller.core_cmd(1) D=byte_controller.core_cmd_ff_CQZ_3_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.core_cmd_ff_CQZ_3_D_LUT4_O_I1 I2=byte_controller.core_cmd(1) I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O O=byte_controller.core_cmd_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=byte_controller.c_state_ff_CQZ_1_D_LUT4_O_I1 I1=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I2 I2=byte_controller.core_cmd_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 I3=byte_controller.core_cmd_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=byte_controller.core_cmd_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.c_state_ff_CQZ_2_D_LUT4_I3_I1 I2=byte_controller.c_state(5) I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I3 O=byte_controller.core_cmd_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=byte_controller.core_cmd(0) D=byte_controller.core_cmd_ff_CQZ_4_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.Reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt LUT4 I0=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I1=byte_controller.core_cmd(0) I2=byte_controller.core_cmd_ff_CQZ_4_D_LUT4_O_I2 I3=byte_controller.c_state_ff_CQZ_6_D_LUT4_O_I1 O=byte_controller.core_cmd_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010011111111
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.core_cmd_ff_CQZ_D_LUT4_O_I1 I2=byte_controller.core_cmd(4) I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O O=byte_controller.core_cmd_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=byte_controller.bit_controller.rst I1=byte_controller.c_state_ff_CQZ_5_D_LUT4_I3_I2 I2=byte_controller.start I3=byte_controller.cmd_ack_LUT4_I3_O_LUT4_I3_O O=byte_controller.core_cmd_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=byte_controller.core_txd_LUT4_I1_I0 I1=byte_controller.bit_controller.din I2=byte_controller.bit_controller.rst I3=byte_controller.core_txd_LUT4_I1_I3 O=byte_controller.bit_controller.sda_oen_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010111111100
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(8) I1=byte_controller.bit_controller.c_state(16) I2=byte_controller.bit_controller.c_state(17) I3=byte_controller.core_txd_LUT4_I1_I0_LUT4_O_I3 O=byte_controller.core_txd_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(6) I1=byte_controller.bit_controller.c_state(9) I2=byte_controller.bit_controller.c_state(5) I3=byte_controller.bit_controller.c_state(7) O=byte_controller.core_txd_LUT4_I1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=byte_controller.bit_controller.c_state(2) I1=byte_controller.bit_controller.c_state(1) I2=byte_controller.bit_controller.c_state(3) I3=byte_controller.bit_controller.c_state(4) O=byte_controller.core_txd_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=byte_controller.bit_controller.din D=byte_controller.core_txd_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.rst I2=byte_controller.ack_in_LUT4_I3_O I3=byte_controller.core_txd_ff_CQZ_D_LUT4_O_I3 O=byte_controller.core_txd_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=byte_controller.c_state(5) I1=byte_controller.bit_controller.cmd_ack I2=byte_controller.dout(7) I3=byte_controller.c_state(3) O=byte_controller.core_txd_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110001110000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.dcnt(1) I2=byte_controller.dcnt(0) I3=byte_controller.dcnt(2) O=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt ff CQZ=byte_controller.dcnt(2) D=byte_controller.dcnt_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.dcnt_ff_CQZ_QEN QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:213.2-221.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.dcnt(1) D=byte_controller.dcnt_ff_CQZ_1_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.dcnt_ff_CQZ_QEN QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:213.2-221.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.ld I1=byte_controller.dcnt(1) I2=byte_controller.dcnt(0) I3=byte_controller.bit_controller.rst O=byte_controller.dcnt_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt ff CQZ=byte_controller.dcnt(0) D=byte_controller.dcnt_ff_CQZ_2_D QCK=byte_controller.bit_controller.clk QEN=byte_controller.dcnt_ff_CQZ_QEN QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:213.2-221.29|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.rst I2=byte_controller.ld I3=byte_controller.dcnt(0) O=byte_controller.dcnt_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.rst I3=byte_controller.dcnt_ff_CQZ_D_LUT4_O_I3 O=byte_controller.dcnt_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=byte_controller.dcnt(0) I1=byte_controller.dcnt(1) I2=byte_controller.ld I3=byte_controller.dcnt(2) O=byte_controller.dcnt_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt ff CQZ=byte_controller.ld D=byte_controller.ld_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.cmd_ack_LUT4_I3_O_LUT4_I3_O I1=byte_controller.bit_controller.cmd_ack I2=byte_controller.bit_controller.rst I3=byte_controller.c_state(6) O=byte_controller.ld_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt ff CQZ=byte_controller.read D=wb_dat_i_LUT4_I2_4_O(5) QCK=byte_controller.bit_controller.clk QEN=byte_controller.cmd_ack_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:221.2-238.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.shift I2=byte_controller.shift_LUT4_I2_I1 I3=byte_controller.shift_LUT4_I2_I0 O=byte_controller.shift_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.shift I2=byte_controller.ld I3=byte_controller.bit_controller.rst O=byte_controller.dcnt_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111110
+.subckt LUT4 I0=byte_controller.shift_LUT4_I2_I0 I1=byte_controller.shift_LUT4_I2_I1 I2=byte_controller.shift I3=byte_controller.ld O=byte_controller.shift_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=byte_controller.shift_LUT4_I2_I0_LUT4_O_I0 I1=byte_controller.shift_LUT4_I2_I0_LUT4_O_I1 I2=byte_controller.shift_LUT4_I2_I0_LUT4_O_I2 I3=byte_controller.shift_LUT4_I2_I0_LUT4_O_I3 O=byte_controller.shift_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(4) I1=byte_controller.bit_controller.clk_cnt(5) I2=byte_controller.bit_controller.clk_cnt(6) I3=byte_controller.bit_controller.clk_cnt(7) O=byte_controller.shift_LUT4_I2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(0) I1=byte_controller.bit_controller.clk_cnt(1) I2=byte_controller.bit_controller.clk_cnt(2) I3=byte_controller.bit_controller.clk_cnt(3) O=byte_controller.shift_LUT4_I2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(12) I1=byte_controller.bit_controller.clk_cnt(13) I2=byte_controller.bit_controller.clk_cnt(14) I3=byte_controller.bit_controller.clk_cnt(15) O=byte_controller.shift_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(8) I1=byte_controller.bit_controller.clk_cnt(9) I2=byte_controller.bit_controller.clk_cnt(10) I3=byte_controller.bit_controller.clk_cnt(11) O=byte_controller.shift_LUT4_I2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.shift_LUT4_I2_I1_LUT4_O_I1 I2=byte_controller.c_state(3) I3=byte_controller.c_state(2) O=byte_controller.shift_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=byte_controller.c_state(5) I1=byte_controller.c_state(1) I2=byte_controller.c_state(0) I3=byte_controller.c_state(6) O=byte_controller.shift_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=byte_controller.shift D=byte_controller.shift_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.rst I3=byte_controller.shift_ff_CQZ_D_LUT4_O_I3 O=byte_controller.shift_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=byte_controller.shift_LUT4_I2_I0 I1=byte_controller.shift_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=byte_controller.c_state(3) I3=byte_controller.bit_controller.cmd_ack O=byte_controller.shift_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110011111111
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.c_state(5) I2=byte_controller.c_state(4) I3=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I3 O=byte_controller.shift_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt ff CQZ=byte_controller.dout(7) D=byte_controller.sr_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=byte_controller.dout(6) D=byte_controller.sr_ff_CQZ_1_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 I1=byte_controller.sr_ff_CQZ_1_D_LUT4_O_I1 I2=byte_controller.sr_ff_CQZ_1_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.sr_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=byte_controller.shift_LUT4_I1_O I1=byte_controller.dout(6) I2=byte_controller.din(6) I3=byte_controller.ld O=byte_controller.sr_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=byte_controller.ld I1=byte_controller.shift_LUT4_I1_O I2=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 I3=byte_controller.dout(5) O=byte_controller.sr_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt ff CQZ=byte_controller.dout(5) D=byte_controller.sr_ff_CQZ_2_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 I1=byte_controller.sr_ff_CQZ_2_D_LUT4_O_I1 I2=byte_controller.sr_ff_CQZ_2_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.sr_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=byte_controller.shift_LUT4_I1_O I1=byte_controller.dout(5) I2=byte_controller.din(5) I3=byte_controller.ld O=byte_controller.sr_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=byte_controller.ld I1=byte_controller.shift_LUT4_I1_O I2=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 I3=byte_controller.dout(4) O=byte_controller.sr_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt ff CQZ=byte_controller.dout(4) D=byte_controller.sr_ff_CQZ_3_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.sr_ff_CQZ_D_LUT4_O_I0 I1=byte_controller.dout(3) I2=byte_controller.sr_ff_CQZ_3_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.sr_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=byte_controller.dout(4) I1=byte_controller.shift_LUT4_I2_O I2=byte_controller.sr_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I2 I3=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 O=byte_controller.sr_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.din(4) I3=byte_controller.ld O=byte_controller.sr_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=byte_controller.dout(3) D=byte_controller.sr_ff_CQZ_4_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 I1=byte_controller.sr_ff_CQZ_4_D_LUT4_O_I1 I2=byte_controller.sr_ff_CQZ_4_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.sr_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=byte_controller.shift_LUT4_I1_O I1=byte_controller.dout(3) I2=byte_controller.din(3) I3=byte_controller.ld O=byte_controller.sr_ff_CQZ_4_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=byte_controller.ld I1=byte_controller.shift_LUT4_I1_O I2=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 I3=byte_controller.dout(2) O=byte_controller.sr_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt ff CQZ=byte_controller.dout(2) D=byte_controller.sr_ff_CQZ_5_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 I1=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I1 I2=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.sr_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=byte_controller.c_state_ff_CQZ_3_D_LUT4_O_I3 I1=byte_controller.shift_LUT4_I2_I0 I2=byte_controller.bit_controller.cmd_ack I3=byte_controller.c_state(4) O=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=byte_controller.shift_LUT4_I1_O I1=byte_controller.dout(2) I2=byte_controller.din(2) I3=byte_controller.ld O=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=byte_controller.ld I1=byte_controller.shift_LUT4_I1_O I2=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 I3=byte_controller.dout(1) O=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt ff CQZ=byte_controller.dout(1) D=byte_controller.sr_ff_CQZ_6_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.sr_ff_CQZ_D_LUT4_O_I0 I1=byte_controller.dout(0) I2=byte_controller.sr_ff_CQZ_6_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.sr_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=byte_controller.dout(1) I1=byte_controller.shift_LUT4_I2_O I2=byte_controller.sr_ff_CQZ_6_D_LUT4_O_I2_LUT4_O_I2 I3=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 O=byte_controller.sr_ff_CQZ_6_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.din(1) I3=byte_controller.ld O=byte_controller.sr_ff_CQZ_6_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=byte_controller.dout(0) D=byte_controller.sr_ff_CQZ_7_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:254.23-280.3|/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_byte_ctrl.v:225.2-385.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.sr_ff_CQZ_D_LUT4_O_I0 I1=byte_controller.bit_controller.dout I2=byte_controller.sr_ff_CQZ_7_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.sr_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=byte_controller.dout(0) I1=byte_controller.shift_LUT4_I2_O I2=byte_controller.sr_ff_CQZ_7_D_LUT4_O_I2_LUT4_O_I2 I3=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 O=byte_controller.sr_ff_CQZ_7_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.din(0) I3=byte_controller.ld O=byte_controller.sr_ff_CQZ_7_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.sr_ff_CQZ_D_LUT4_O_I0 I1=byte_controller.dout(6) I2=byte_controller.sr_ff_CQZ_D_LUT4_O_I2 I3=byte_controller.bit_controller.rst O=byte_controller.sr_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 I2=byte_controller.ld I3=byte_controller.shift_LUT4_I1_O O=byte_controller.sr_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=byte_controller.dout(7) I1=byte_controller.shift_LUT4_I2_O I2=byte_controller.sr_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=byte_controller.sr_ff_CQZ_5_D_LUT4_O_I0 O=byte_controller.sr_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.din(7) I3=byte_controller.ld O=byte_controller.sr_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=byte_controller.start D=wb_dat_i_LUT4_I2_4_O(7) QCK=byte_controller.bit_controller.clk QEN=byte_controller.cmd_ack_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:221.2-238.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.stop D=wb_dat_i_LUT4_I2_4_O(6) QCK=byte_controller.bit_controller.clk QEN=byte_controller.cmd_ack_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:221.2-238.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.write D=wb_dat_i_LUT4_I2_4_O(4) QCK=byte_controller.bit_controller.clk QEN=byte_controller.cmd_ack_LUT4_I2_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:221.2-238.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cr_LUT4_I1_I0 I1=cr(2) I2=byte_controller.din(2) I3=cr_LUT4_I1_I3 O=cr_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cr_LUT4_I1_I0 I1=byte_controller.write I2=cr_LUT4_I1_I3 I3=byte_controller.din(4) O=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(1) I2=$iopadmap$wb_adr_i(2) I3=$iopadmap$wb_adr_i(0) O=cr_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(2) I2=$iopadmap$wb_adr_i(0) I3=$iopadmap$wb_adr_i(1) O=cr_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cr_LUT4_I1_O_LUT4_I3_I0 I1=cr_LUT4_I1_O_LUT4_I3_I1 I2=$iopadmap$wb_adr_i(2) I3=cr_LUT4_I1_O O=cr_LUT4_I1_O_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(10) I1=byte_controller.bit_controller.clk_cnt(2) I2=$iopadmap$wb_adr_i(1) I3=cr_LUT4_I1_O_LUT4_I3_I0_LUT4_O_I3 O=cr_LUT4_I1_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(0) I2=$iopadmap$wb_adr_i(1) I3=$iopadmap$wb_adr_i(2) O=cr_LUT4_I1_O_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=ctr(2) I1=$iopadmap$wb_adr_i(1) I2=byte_controller.dout(2) I3=irq_flag_LUT4_I0_I3_LUT4_I2_O O=cr_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_I0 I1=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_I1 I2=al_LUT4_I3_O_LUT4_I2_O I3=$iopadmap$wb_adr_i(2) O=cr_LUT4_I1_O_LUT4_I3_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010001000
+.subckt LUT4 I0=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I0 I1=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I1 I2=$iopadmap$wb_adr_i(2) I3=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3 O=cr_LUT4_I1_O_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(12) I1=byte_controller.bit_controller.clk_cnt(4) I2=cr_LUT4_I1_O_LUT4_I3_I0_LUT4_O_I3 I3=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I0_LUT4_O_I3 O=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=ctr(4) I1=$iopadmap$wb_adr_i(1) I2=byte_controller.dout(4) I3=irq_flag_LUT4_I0_I3_LUT4_I2_O O=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(13) I1=byte_controller.dout(5) I2=$iopadmap$wb_adr_i(1) I3=$iopadmap$wb_adr_i(0) O=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011111111
+.subckt LUT4 I0=ctr(5) I1=byte_controller.bit_controller.clk_cnt(5) I2=$iopadmap$wb_adr_i(0) I3=$iopadmap$wb_adr_i(1) O=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101011111100
+.subckt ff CQZ=cr(2) D=wb_dat_i_LUT4_I2_4_O(2) QCK=byte_controller.bit_controller.clk QEN=cr_ff_CQZ_QEN QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:221.2-238.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cr(1) D=wb_dat_i_LUT4_I2_4_O(1) QCK=byte_controller.bit_controller.clk QEN=cr_ff_CQZ_QEN QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:221.2-238.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=irq_flag_LUT4_I0_I1 I1=byte_controller.bit_controller.ena I2=byte_controller.bit_controller.rst I3=wb_we_i_LUT4_I2_O O=cr_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt ff CQZ=ctr(5) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=ctr(4) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=ctr(3) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=ctr(2) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=ctr(1) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=ctr(0) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.din(0) I1=cr(0) I2=$iopadmap$wb_adr_i(1) I3=$iopadmap$wb_adr_i(0) O=iack_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010100110000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(2) I2=iack_LUT4_I1_O_LUT4_I3_I2 I3=iack_LUT4_I1_O O=iack_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(8) I1=byte_controller.bit_controller.clk_cnt(0) I2=$iopadmap$wb_adr_i(1) I3=$iopadmap$wb_adr_i(0) O=iack_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt ff CQZ=cr(0) D=wb_dat_i_LUT4_I2_4_O(0) QCK=byte_controller.bit_controller.clk QEN=cr_ff_CQZ_QEN QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:221.2-238.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=ctr(6) I1=byte_controller.dout(6) I2=$iopadmap$wb_adr_i(0) I3=$iopadmap$wb_adr_i(1) O=ien_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011111111
+.subckt LUT4 I0=ien_LUT4_I0_O_LUT4_I1_I0 I1=ien_LUT4_I0_O I2=byte_controller.bit_controller.busy_LUT4_I3_O_LUT4_I2_O I3=$iopadmap$wb_adr_i(2) O=cr_LUT4_I1_O_LUT4_I3_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(14) I1=byte_controller.bit_controller.clk_cnt(6) I2=$iopadmap$wb_adr_i(1) I3=$iopadmap$wb_adr_i(0) O=ien_LUT4_I0_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt ff CQZ=ctr(6) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=irq_flag I1=irq_flag_LUT4_I0_I1 I2=byte_controller.dout(0) I3=irq_flag_LUT4_I0_I3 O=irq_flag_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(2) I2=$iopadmap$wb_adr_i(1) I3=$iopadmap$wb_adr_i(0) O=irq_flag_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=irq_flag_LUT4_I0_I3 I3=$iopadmap$wb_adr_i(2) O=irq_flag_LUT4_I0_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.rst I2=wb_we_i_LUT4_I2_O I3=irq_flag_LUT4_I0_I3_LUT4_I2_O O=irq_flag_LUT4_I0_I3_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_adr_i(1) I3=$iopadmap$wb_adr_i(0) O=irq_flag_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=irq_flag_LUT4_I0_O_LUT4_I3_I0 I1=ctr(0) I2=iack_LUT4_I1_O_LUT4_I3_O I3=irq_flag_LUT4_I0_O O=cr_LUT4_I1_O_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=irq_flag_LUT4_I0_O_LUT4_I3_I0 I3=irq_flag_LUT4_I0_I3_LUT4_I2_O O=cr_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(1) I2=$iopadmap$wb_adr_i(0) I3=$iopadmap$wb_adr_i(2) O=irq_flag_LUT4_I0_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=irq_flag D=irq_flag_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:283.2-304.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.cmd_ack I1=irq_flag I2=byte_controller.bit_controller.rst I3=cr(0) O=irq_flag_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(15) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(14) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(5) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(4) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(3) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(2) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(1) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(0) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(13) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(12) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(11) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(10) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(9) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(8) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(7) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.bit_controller.clk_cnt(6) D=byte_controller.bit_controller.al QCK=byte_controller.bit_controller.clk QEN=byte_controller.bit_controller.rst QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(1) I2=byte_controller.start I3=rxack O=rxack_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=$iopadmap$wb_adr_i(1) I1=byte_controller.din(7) I2=rxack_LUT4_I3_O I3=$iopadmap$wb_adr_i(0) O=rxack_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(2) I2=rxack_LUT4_I3_O_LUT4_I2_O I3=rxack_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3 O=cr_LUT4_I1_O_LUT4_I3_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(0) I2=rxack_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 I3=rxack_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3 O=rxack_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(1) I2=byte_controller.dout(7) I3=byte_controller.bit_controller.clk_cnt(15) O=rxack_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(1) I2=byte_controller.bit_controller.ena I3=byte_controller.bit_controller.clk_cnt(7) O=rxack_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt ff CQZ=rxack D=rxack_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:283.2-304.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.scl_i I3=byte_controller.bit_controller.rst O=scl_pad_i_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=byte_controller.bit_controller.sda_i I3=byte_controller.bit_controller.rst O=sda_pad_i_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_adr_i(1) I2=cr(1) I3=sr(1) O=tip_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=$iopadmap$wb_adr_i(1) I1=byte_controller.din(1) I2=tip_LUT4_I3_O I3=$iopadmap$wb_adr_i(0) O=tip_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=tip_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0 I1=tip_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I1 I2=tip_LUT4_I3_O_LUT4_I2_O I3=$iopadmap$wb_adr_i(2) O=cr_LUT4_I1_O_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010001000
+.subckt LUT4 I0=byte_controller.bit_controller.clk_cnt(9) I1=byte_controller.dout(1) I2=$iopadmap$wb_adr_i(1) I3=$iopadmap$wb_adr_i(0) O=tip_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011111111
+.subckt LUT4 I0=ctr(1) I1=byte_controller.bit_controller.clk_cnt(1) I2=$iopadmap$wb_adr_i(0) I3=$iopadmap$wb_adr_i(1) O=tip_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101011111100
+.subckt ff CQZ=sr(1) D=tip_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:283.2-304.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.rst I2=byte_controller.write I3=byte_controller.read O=tip_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=byte_controller.din(7) D=wb_dat_i_LUT4_I2_O(7) QCK=byte_controller.bit_controller.clk QEN=irq_flag_LUT4_I0_I3_LUT4_I2_O_LUT4_I3_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.din(6) D=wb_dat_i_LUT4_I2_O(6) QCK=byte_controller.bit_controller.clk QEN=irq_flag_LUT4_I0_I3_LUT4_I2_O_LUT4_I3_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.din(5) D=wb_dat_i_LUT4_I2_O(5) QCK=byte_controller.bit_controller.clk QEN=irq_flag_LUT4_I0_I3_LUT4_I2_O_LUT4_I3_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.din(4) D=wb_dat_i_LUT4_I2_O(4) QCK=byte_controller.bit_controller.clk QEN=irq_flag_LUT4_I0_I3_LUT4_I2_O_LUT4_I3_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.din(3) D=wb_dat_i_LUT4_I2_4_O(3) QCK=byte_controller.bit_controller.clk QEN=irq_flag_LUT4_I0_I3_LUT4_I2_O_LUT4_I3_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.din(2) D=wb_dat_i_LUT4_I2_O(2) QCK=byte_controller.bit_controller.clk QEN=irq_flag_LUT4_I0_I3_LUT4_I2_O_LUT4_I3_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.din(1) D=wb_dat_i_LUT4_I2_O(1) QCK=byte_controller.bit_controller.clk QEN=irq_flag_LUT4_I0_I3_LUT4_I2_O_LUT4_I3_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=byte_controller.din(0) D=wb_dat_i_LUT4_I2_O(0) QCK=byte_controller.bit_controller.clk QEN=irq_flag_LUT4_I0_I3_LUT4_I2_O_LUT4_I3_O QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:193.2-218.15|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=wb_ack_i D=wb_ack_o_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:174.2-175.51|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_dat_i(7) I3=byte_controller.bit_controller.rst O=wb_dat_i_LUT4_I2_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_dat_i(6) I3=byte_controller.bit_controller.rst O=wb_dat_i_LUT4_I2_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_dat_i(5) I3=byte_controller.bit_controller.rst O=wb_dat_i_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_dat_i(4) I3=byte_controller.bit_controller.rst O=wb_dat_i_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_dat_i(3) I3=byte_controller.bit_controller.rst O=wb_dat_i_LUT4_I2_4_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_dat_i(2) I3=byte_controller.bit_controller.rst O=wb_dat_i_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_dat_i(1) I3=byte_controller.bit_controller.rst O=wb_dat_i_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_dat_i(0) I3=byte_controller.bit_controller.rst O=wb_dat_i_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=$iopadmap$wb_dat_o(7) D=cr_LUT4_I1_O_LUT4_I3_O(7) QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:178.2-190.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$wb_dat_o(6) D=cr_LUT4_I1_O_LUT4_I3_O(6) QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:178.2-190.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$wb_dat_o(5) D=cr_LUT4_I1_O_LUT4_I3_O(5) QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:178.2-190.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$wb_dat_o(4) D=cr_LUT4_I1_O_LUT4_I3_O(4) QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:178.2-190.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$wb_dat_o(3) D=cr_LUT4_I1_O_LUT4_I3_O(3) QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:178.2-190.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$wb_dat_o(2) D=cr_LUT4_I1_O_LUT4_I3_O(2) QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:178.2-190.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$wb_dat_o(1) D=cr_LUT4_I1_O_LUT4_I3_O(1) QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:178.2-190.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$wb_dat_o(0) D=cr_LUT4_I1_O_LUT4_I3_O(0) QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.bit_controller.al QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:178.2-190.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$wb_inta_o D=wb_inta_o_ff_CQZ_D QCK=byte_controller.bit_controller.clk QEN=$auto$hilomap.cc:39:hilomap_worker$5532 QRT=byte_controller.Reset QST=byte_controller.bit_controller.al
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/i2c_master_top/rtl/i2c_master_top.v:307.2-313.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=ctr(6) I2=irq_flag I3=byte_controller.bit_controller.rst O=wb_inta_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=$iopadmap$wb_stb_i I2=$iopadmap$wb_cyc_i I3=wb_ack_i O=wb_ack_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=$iopadmap$wb_we_i I3=wb_ack_i O=wb_we_i_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=wb_dat_i_LUT4_I2_O(7) I3=wb_we_i_LUT4_I2_O O=wb_dat_i_LUT4_I2_4_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=wb_dat_i_LUT4_I2_O(6) I3=wb_we_i_LUT4_I2_O O=wb_dat_i_LUT4_I2_4_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=wb_dat_i_LUT4_I2_O(5) I3=wb_we_i_LUT4_I2_O O=wb_dat_i_LUT4_I2_4_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=wb_dat_i_LUT4_I2_O(4) I3=wb_we_i_LUT4_I2_O O=wb_dat_i_LUT4_I2_4_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=wb_dat_i_LUT4_I2_O(2) I3=wb_we_i_LUT4_I2_O O=wb_dat_i_LUT4_I2_4_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=wb_dat_i_LUT4_I2_O(1) I3=wb_we_i_LUT4_I2_O O=wb_dat_i_LUT4_I2_4_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=byte_controller.bit_controller.al I1=byte_controller.bit_controller.al I2=wb_dat_i_LUT4_I2_O(0) I3=wb_we_i_LUT4_I2_O O=wb_dat_i_LUT4_I2_4_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.end
diff --git a/BENCHMARK/i2c_master_top/rtl/StateMachine.v b/BENCHMARK/i2c_master_top/rtl/StateMachine.v
new file mode 100644
index 0000000..91344b0
--- /dev/null
+++ b/BENCHMARK/i2c_master_top/rtl/StateMachine.v
@@ -0,0 +1,589 @@
+// -----------------------------------------------------------------------------
+// title          : Sensor Manager Statemachine
+// project        : ULP Sensor Hub
+// -----------------------------------------------------------------------------
+// file           : StateMachine.v
+// author         : Glen Gomes
+// company        : QuickLogic Corp
+// created        : 2013/12/06	
+// last update    : 2013/12/06
+// platform       : PolarPro III
+// standard       : Verilog 2001
+// -----------------------------------------------------------------------------
+// description: The Sensor Manger Statemachine is responsible for controlling the
+//              operations of the Sensor Manager. These include performing
+//              transfers between Sensor Memory and various registers.
+// -----------------------------------------------------------------------------
+// copyright (c) 2013
+// -----------------------------------------------------------------------------
+// revisions  :
+// date            version    author         description
+// 2013/12/06      1.0        Glen Gomes     created
+// -----------------------------------------------------------------------------
+// Comments: This solution is specifically for use with the QuickLogic
+//           PolarPro III device. 
+// -----------------------------------------------------------------------------
+
+`timescale 1ns/10ps
+
+module StateMachine (
+
+               CLK_IN,
+               RESET_IN,
+
+			   RUNTIME_ADDRESS,
+               CONTROL_JUMP_REG_DCD,
+               SAVE_REG_2_MEM,
+
+               WB_ACK_I,
+               WB_BUSY_I,
+			   WB_BUSY_POLL_I,
+
+               WB_WE_O,
+               WB_STB_O,
+               WB_CYC_O,
+
+               SM_CNTL_REG_RUN,
+               SM_CNTL_INIT_SEQ,
+               SM_READ_DATA,
+
+               SM_INSTR_PTR,
+               SM_READ_SELECT,
+
+               SM_WRITE_SELECT,
+
+               SM_BUSY
+
+               );
+  
+
+//-----Port Signals--------------------
+//
+
+input          CLK_IN;
+input          RESET_IN;
+
+input    [7:0] RUNTIME_ADDRESS;
+input          CONTROL_JUMP_REG_DCD;
+input          SAVE_REG_2_MEM;
+
+input          WB_ACK_I;
+input          WB_BUSY_I;
+input          WB_BUSY_POLL_I;
+
+output         WB_WE_O;
+output         WB_STB_O;
+output         WB_CYC_O;
+
+input          SM_CNTL_REG_RUN;
+input          SM_CNTL_INIT_SEQ;
+input    [7:0] SM_READ_DATA;
+
+output   [7:0] SM_INSTR_PTR;
+output         SM_READ_SELECT;
+
+output         SM_WRITE_SELECT;
+
+output         SM_BUSY;
+
+
+wire           CLK_IN;
+wire           RESET_IN;
+
+wire     [7:0] RUNTIME_ADDRESS;
+wire           CONTROL_JUMP_REG_DCD;
+wire           SAVE_REG_2_MEM;
+
+wire           WB_ACK_I;
+wire           WB_BUSY_I;
+wire           WB_BUSY_POLL_I;
+
+reg            WB_WE_O;
+reg            wb_we_o_nxt;
+
+reg            WB_STB_O;
+reg            wb_stb_o_nxt;
+
+reg            WB_CYC_O;
+reg            wb_cyc_o_nxt;
+
+wire           SM_CNTL_REG_RUN;
+wire           SM_CNTL_INIT_SEQ;
+wire     [7:0] SM_READ_DATA;
+
+reg      [7:0] SM_INSTR_PTR;
+reg      [7:0] sm_instr_ptr_nxt;
+
+reg            SM_READ_SELECT;
+reg            sm_read_select_nxt;
+
+reg            SM_WRITE_SELECT;
+reg            sm_write_select_nxt;
+
+reg            SM_BUSY;
+reg            sm_busy_nxt;
+
+//-----Internal Signals--------------------
+//
+
+
+//
+// Define the Statemachine registers
+//
+reg      [3:0] sensor_manager_sm;
+reg      [3:0] sensor_manager_sm_nxt;
+
+
+//
+// Define the Instruction Pointer variables
+//
+
+reg            sm_instr_ptr_ce;
+reg            sm_instr_ptr_ce_nxt;
+
+reg            sm_instr_ptr_ld;
+reg            sm_instr_ptr_ld_nxt;
+
+reg            sm_instr_ptr_sel;
+reg            sm_instr_ptr_sel_nxt;
+
+
+
+//------Define Parameters---------
+//
+
+//
+// Define the Sensor Manager Statemachine States
+//
+// Note: These states are chosen to allow for overlap of various signals
+//       during operation. This overlap should help reduce timing
+//       dependancies.
+//
+parameter SM_IDLE           = 4'h0;
+parameter SM_INC_PTR        = 4'h1;
+parameter SM_INST_RD        = 4'h2;
+//parameter SM_INST_DCD       = 4'h3; // Note: Will be used for TimeStamp Support in a future design
+parameter SM_REG_WR         = 4'h4;
+parameter SM_REG_RD         = 4'h5;
+parameter SM_WAIT_BUSY_ON   = 4'h6;
+parameter SM_WAIT_BUSY_OFF  = 4'h7;
+
+
+//
+// Sensor Manager Initialization Start Address
+//
+// Note: The previous IP used the reset of the "RuntimeAddress" register to
+//       select the sensor initialization code. This value explicity selects
+//       the value for the start (or re-start) of initialization.
+//
+parameter SM_INIT_INSTR_ADR = 8'h0; // Address for the start in initialization instructions
+
+
+//------Logic Operations----------
+//
+
+//
+// Define the Instruction Pointer
+//
+// Note: This pointer can start at either the sensor initialization code start
+//       address or the run-time code start address. 
+//
+always @( SM_INSTR_PTR         or
+		  sm_instr_ptr_ld      or
+		  sm_instr_ptr_ce      or
+		  sm_instr_ptr_sel     or
+		  SM_READ_DATA         or
+          CONTROL_JUMP_REG_DCD or
+		  RUNTIME_ADDRESS
+		 )
+begin
+	case({sm_instr_ptr_ld, sm_instr_ptr_ce})
+	2'b00: sm_instr_ptr_nxt    <= SM_INSTR_PTR;        // Hold Current Value
+	2'b01: sm_instr_ptr_nxt    <= SM_INSTR_PTR + 1'b1; // Increment to the next address
+	2'b10:
+	begin
+        case({CONTROL_JUMP_REG_DCD, sm_instr_ptr_sel})
+        2'b00: sm_instr_ptr_nxt <= SM_INIT_INSTR_ADR;  // Initialization Code Address
+        2'b01: sm_instr_ptr_nxt <= RUNTIME_ADDRESS;    //       Run-time Code Address
+        2'b10: sm_instr_ptr_nxt <= SM_READ_DATA[7:0];  //           Jump      Address
+        2'b11: sm_instr_ptr_nxt <= SM_READ_DATA[7:0];  //           Jump      Address
+        endcase
+	end
+	2'b11: sm_instr_ptr_nxt    <= SM_INSTR_PTR;        // Hold Current Value
+	endcase
+end
+
+
+// Define the registers associated with the Sensor Manager Statemachine
+//
+always @(posedge CLK_IN or posedge RESET_IN) 
+begin
+    if (RESET_IN)
+    begin
+        sensor_manager_sm  <= SM_IDLE;
+
+        SM_INSTR_PTR       <=  8'h0;
+        sm_instr_ptr_ce    <=  1'b0;
+        sm_instr_ptr_ld    <=  1'b0;
+        sm_instr_ptr_sel   <=  1'b0;
+
+        WB_WE_O            <=  1'b0;
+        WB_STB_O           <=  1'b0;
+		WB_CYC_O           <=  1'b0;
+
+        SM_READ_SELECT     <=  1'b0;
+        SM_WRITE_SELECT    <=  1'b0;
+
+        SM_BUSY            <=  1'b0;
+    end
+    else 
+    begin  
+        sensor_manager_sm  <= sensor_manager_sm_nxt;    
+
+        SM_INSTR_PTR       <= sm_instr_ptr_nxt;
+        sm_instr_ptr_ce    <= sm_instr_ptr_ce_nxt;
+        sm_instr_ptr_ld    <= sm_instr_ptr_ld_nxt;
+        sm_instr_ptr_sel   <= sm_instr_ptr_sel_nxt;
+
+        WB_WE_O            <=  wb_we_o_nxt;
+        WB_STB_O           <=  wb_stb_o_nxt;
+		WB_CYC_O           <=  wb_cyc_o_nxt;
+
+        SM_READ_SELECT     <= sm_read_select_nxt;
+        SM_WRITE_SELECT    <= sm_write_select_nxt;
+
+        SM_BUSY            <= sm_busy_nxt;
+ 	end
+end   
+
+
+// Define the Sensor Manager Statemachine
+//
+always @( sensor_manager_sm     or
+          SM_CNTL_INIT_SEQ      or
+          SM_CNTL_REG_RUN       or
+          CONTROL_JUMP_REG_DCD  or
+          SAVE_REG_2_MEM        or
+          WB_BUSY_I             or
+		  WB_BUSY_POLL_I        or
+		  WB_ACK_I
+         )
+begin
+    case(sensor_manager_sm)
+    SM_IDLE:
+	begin
+		case({SM_CNTL_INIT_SEQ, SM_CNTL_REG_RUN})
+		2'b00:    // No Activity
+		begin
+            sensor_manager_sm_nxt <= SM_IDLE;
+
+		    sm_busy_nxt           <= 1'b0;
+            sm_instr_ptr_ld_nxt   <= 1'b0;
+            sm_instr_ptr_sel_nxt  <= 1'b0;
+        end
+		2'b01:    // Start at the Sensor Run-Time Code
+		begin
+            sensor_manager_sm_nxt <= SM_INC_PTR;
+
+		    sm_busy_nxt           <= 1'b1;
+            sm_instr_ptr_ld_nxt   <= 1'b1;
+            sm_instr_ptr_sel_nxt  <= 1'b1;
+        end
+		2'b10:    // No Activity
+		begin
+            sensor_manager_sm_nxt <= SM_IDLE;
+
+		    sm_busy_nxt           <= 1'b0;
+            sm_instr_ptr_ld_nxt   <= 1'b0;
+            sm_instr_ptr_sel_nxt  <= 1'b0;
+        end
+		2'b11:    // Start at the Sensor Initialization Code
+		begin
+            sensor_manager_sm_nxt <= SM_INC_PTR;
+
+		    sm_busy_nxt           <= 1'b1;
+            sm_instr_ptr_ld_nxt   <= 1'b1;
+            sm_instr_ptr_sel_nxt  <= 1'b0;
+        end
+        endcase
+
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+		wb_stb_o_nxt          <= 1'b0;
+		wb_cyc_o_nxt          <= 1'b0;
+	end
+    SM_INC_PTR:
+	begin
+        sensor_manager_sm_nxt <= SM_INST_RD;
+
+		sm_busy_nxt           <= 1'b1;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+        sm_instr_ptr_sel_nxt  <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b1;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+		wb_stb_o_nxt          <= 1'b0;
+		wb_cyc_o_nxt          <= 1'b0;
+	end
+    SM_INST_RD:
+	begin
+        sensor_manager_sm_nxt <= SM_REG_WR;
+
+		sm_busy_nxt           <= 1'b1;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+        sm_instr_ptr_sel_nxt  <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b1;
+		wb_stb_o_nxt          <= 1'b1;
+		wb_cyc_o_nxt          <= 1'b1;
+	end
+    SM_REG_WR:
+	begin
+        sm_instr_ptr_sel_nxt  <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+
+		case(SM_CNTL_REG_RUN)
+		1'b0:  // A write of "0" to bit "0" of the Command register at address "0" turns off 
+			   // the Sensor Manager's Statemachine
+		begin
+		    sensor_manager_sm_nxt <= SM_IDLE;
+
+		    sm_busy_nxt           <= 1'b0;
+
+            sm_instr_ptr_ld_nxt   <= 1'b0;
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_we_o_nxt           <= 1'b0;
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+		end
+		1'b1: // Sensor Manager Statemachine is not stopped; continue processing
+		begin
+		    sm_busy_nxt           <= 1'b1;
+
+		    case({WB_BUSY_POLL_I, WB_ACK_I})
+            2'b00:    // Wait for Wish Bone Acknowledge and no need to wait for transfer complete
+	        begin
+		    	sensor_manager_sm_nxt <= SM_REG_WR;
+
+                sm_instr_ptr_ld_nxt   <= 1'b0;
+                sm_instr_ptr_ce_nxt   <= 1'b0;
+
+                sm_write_select_nxt   <= 1'b0;
+
+		        wb_we_o_nxt           <= 1'b1;
+		        wb_stb_o_nxt          <= 1'b1;
+		        wb_cyc_o_nxt          <= 1'b1;
+		    end
+            2'b01:    // Wish Bone Acknowledge Received and no need to wait for transfer complete
+	        begin
+                case(SAVE_REG_2_MEM)
+				1'b0: 
+				begin
+			        sensor_manager_sm_nxt <= SM_INC_PTR;
+
+                    sm_instr_ptr_ld_nxt   <=  CONTROL_JUMP_REG_DCD;
+                    sm_instr_ptr_ce_nxt   <= ~CONTROL_JUMP_REG_DCD;
+
+                    sm_write_select_nxt   <= 1'b0;
+
+		            wb_we_o_nxt           <= 1'b0;
+		            wb_stb_o_nxt          <= 1'b0;
+		            wb_cyc_o_nxt          <= 1'b0;
+				end
+				1'b1: 
+				begin
+			        sensor_manager_sm_nxt <= SM_REG_RD;
+
+                    sm_instr_ptr_ld_nxt   <= 1'b0;
+                    sm_instr_ptr_ce_nxt   <= 1'b0;
+
+                    sm_write_select_nxt   <= 1'b1;
+
+		            wb_we_o_nxt           <= 1'b0;
+		            wb_stb_o_nxt          <= 1'b1;
+		            wb_cyc_o_nxt          <= 1'b1;
+				end
+		        endcase
+		    end
+            2'b10:    // Wait for Wish Bone Acknowledge and will need to wait for transfer complete
+	        begin
+			    sensor_manager_sm_nxt <= SM_REG_WR;
+
+                sm_instr_ptr_ld_nxt   <= 1'b0;
+                sm_instr_ptr_ce_nxt   <= 1'b0;
+
+                sm_write_select_nxt   <= 1'b0;
+
+		        wb_we_o_nxt           <= 1'b1;
+		        wb_stb_o_nxt          <= 1'b1;
+		        wb_cyc_o_nxt          <= 1'b1;
+		    end
+            2'b11:     // Acknowledge received but need to wait for transfer complete
+	        begin
+			    sensor_manager_sm_nxt <= SM_WAIT_BUSY_ON;
+
+                sm_instr_ptr_ld_nxt   <= 1'b0;
+                sm_instr_ptr_ce_nxt   <= 1'b0;
+
+                sm_write_select_nxt   <= 1'b0;
+
+		        wb_we_o_nxt           <= 1'b0;
+		        wb_stb_o_nxt          <= 1'b0;
+		        wb_cyc_o_nxt          <= 1'b0;
+		    end
+            endcase
+		end
+        endcase
+	end
+    SM_REG_RD:
+	begin
+		sm_busy_nxt           <= 1'b1;
+
+        sm_instr_ptr_sel_nxt  <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+
+		case(WB_ACK_I)
+        1'b0:    // Waiting for Wish Bone Acknowledge
+		begin
+            sensor_manager_sm_nxt <= SM_REG_RD;
+
+            sm_instr_ptr_ld_nxt   <= 1'b0;
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+
+            sm_write_select_nxt   <= 1'b1;
+
+		    wb_stb_o_nxt          <= 1'b1;
+		    wb_cyc_o_nxt          <= 1'b1;
+        end
+        1'b1:    // Got Wish Bone Acknowledge
+        begin
+            sensor_manager_sm_nxt <= SM_INC_PTR;
+
+            sm_instr_ptr_ld_nxt   <=  CONTROL_JUMP_REG_DCD;
+            sm_instr_ptr_ce_nxt   <= ~CONTROL_JUMP_REG_DCD;
+
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+        end
+        endcase
+	end
+    SM_WAIT_BUSY_ON:
+	begin
+		sm_busy_nxt           <= 1'b1;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+        sm_instr_ptr_sel_nxt  <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+		wb_stb_o_nxt          <= 1'b0;
+		wb_cyc_o_nxt          <= 1'b0;
+
+        case(WB_BUSY_I)
+        1'b0: sensor_manager_sm_nxt <= SM_WAIT_BUSY_ON;    // Wait for Busy from I/F
+        1'b1: sensor_manager_sm_nxt <= SM_WAIT_BUSY_OFF;   // Got      Busy from I/F
+        endcase
+	end
+    SM_WAIT_BUSY_OFF:
+	begin
+		sm_busy_nxt           <= 1'b1;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+        sm_instr_ptr_sel_nxt  <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+
+	    wb_we_o_nxt           <= 1'b0;
+
+        case({SAVE_REG_2_MEM, WB_BUSY_I})
+        2'b00:    // Wishbone transfer complete; no need to write anything to Sensor Manager Memory
+				  // 
+				  // Note: Writes to the command register do not enter this state. 
+				  //       Therefore, there is no need to check for the end of processing.
+		begin
+			sensor_manager_sm_nxt <= SM_INC_PTR;
+
+            sm_instr_ptr_ce_nxt   <= 1'b1;
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+		end
+        2'b01:    // Wait for Wishbone transfer to complete
+		begin
+			sensor_manager_sm_nxt <= SM_WAIT_BUSY_OFF;
+
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+		end
+        2'b10:    // Wishbone transfer complete; Write resulting register value to Sensor Manager Memory
+		begin
+			sensor_manager_sm_nxt <= SM_REG_RD;
+
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+            sm_write_select_nxt   <= 1'b1;
+
+		    wb_stb_o_nxt          <= 1'b1;
+		    wb_cyc_o_nxt          <= 1'b1;
+		end
+        2'b11:    // Wait for Wishbone transfer to complete
+		begin
+			sensor_manager_sm_nxt <= SM_WAIT_BUSY_OFF;
+
+            sm_instr_ptr_ce_nxt   <= 1'b0;
+            sm_write_select_nxt   <= 1'b0;
+
+		    wb_stb_o_nxt          <= 1'b0;
+		    wb_cyc_o_nxt          <= 1'b0;
+		end
+        endcase
+	end
+	default:
+	begin
+        sensor_manager_sm_nxt <= SM_IDLE;
+
+		sm_busy_nxt           <= 1'b0;
+
+        sm_instr_ptr_ld_nxt   <= 1'b0;
+        sm_instr_ptr_ce_nxt   <= 1'b0;
+        sm_instr_ptr_sel_nxt  <= 1'b0;
+
+        sm_read_select_nxt    <= 1'b0;
+        sm_write_select_nxt   <= 1'b0;
+
+		wb_we_o_nxt           <= 1'b0;
+		wb_stb_o_nxt          <= 1'b0;
+		wb_cyc_o_nxt          <= 1'b0;
+	end
+	endcase
+end	
+
+endmodule
diff --git a/BENCHMARK/i2c_master_top/rtl/i2c_master_bit_ctrl.v b/BENCHMARK/i2c_master_top/rtl/i2c_master_bit_ctrl.v
new file mode 100644
index 0000000..c94101f
--- /dev/null
+++ b/BENCHMARK/i2c_master_top/rtl/i2c_master_bit_ctrl.v
@@ -0,0 +1,598 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_bit_ctrl.v,v 1.14 2009-01-20 10:25:29 rherveille Exp $
+//
+//  $Date: 2009-01-20 10:25:29 $
+//  $Revision: 1.14 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: $
+//               Revision 1.14  2009/01/20 10:25:29  rherveille
+//               Added clock synchronization logic
+//               Fixed slave_wait signal
+//
+//               Revision 1.13  2009/01/19 20:29:26  rherveille
+//               Fixed synopsys miss spell (synopsis)
+//               Fixed cr[0] register width
+//               Fixed ! usage instead of ~
+//               Fixed bit controller parameter width to 18bits
+//
+//               Revision 1.12  2006/09/04 09:08:13  rherveille
+//               fixed short scl high pulse after clock stretch
+//               fixed slave model not returning correct '(n)ack' signal
+//
+//               Revision 1.11  2004/05/07 11:02:26  rherveille
+//               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
+//
+//               Revision 1.10  2003/08/09 07:01:33  rherveille
+//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+//               Fixed a potential bug in the byte controller's host-acknowledge generation.
+//
+//               Revision 1.9  2003/03/10 14:26:37  rherveille
+//               Fixed cmd_ack generation item (no bug).
+//
+//               Revision 1.8  2003/02/05 00:06:10  rherveille
+//               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
+//
+//               Revision 1.7  2002/12/26 16:05:12  rherveille
+//               Small code simplifications
+//
+//               Revision 1.6  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.5  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.4  2002/10/30 18:10:07  rherveille
+//               Fixed some reported minor start/stop generation timing issuess.
+//
+//               Revision 1.3  2002/06/15 07:37:03  rherveille
+//               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
+//
+//               Revision 1.2  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+//
+/////////////////////////////////////
+// Bit controller section
+/////////////////////////////////////
+//
+// Translate simple commands into SCL/SDA transitions
+// Each command has 5 states, A/B/C/D/idle
+//
+// start:	SCL	~~~~~~~~~~\____
+//			SDA	~~~~~~~~\______
+//			 x 	| A | B | C | D | i
+//
+// repstart	SCL	____/~~~~\___
+//			SDA	__/~~~\______
+//			 x 	| A | B | C | D | i
+//
+// stop		SCL	____/~~~~~~~~
+//			SDA	==\____/~~~~~
+//			 x 	| A | B | C | D | i
+//
+//- write	SCL	____/~~~~\____
+//			SDA	==X=========X=
+//			 x 	| A | B | C | D | i
+//
+//- read	SCL	____/~~~~\____
+//			SDA	XXXX=====XXXX
+//			 x 	| A | B | C | D | i
+//
+
+// Timing:     Normal mode      Fast mode
+///////////////////////////////////////////////////////////////////////
+// Fscl        100KHz           400KHz
+// Th_scl      4.0us            0.6us   High period of SCL
+// Tl_scl      4.7us            1.3us   Low period of SCL
+// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
+// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
+// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
+//
+
+///////////////////////////////////////////////////////////////////////
+// QuickLogic Change History:
+// 
+// Date: February 11, 2014
+// Engineer: Anthony Le
+// Issue: i2c master generates back to back stop conditions that violate i2c protocol
+// Change:
+//   1. Move the generation of cmd_ack to one clock earlier in stop_c state
+//   2. Change the condition to unset (set to 0) for cmd_ack in stop_d state
+// 
+// synopsys translate_off
+// synopsys translate_on
+`timescale 1ns / 10ps
+
+`include "i2c_master_defines.v"
+
+module i2c_master_bit_ctrl (
+    input             clk,      // system clock
+    input             rst,      // synchronous active high reset
+    input             Reset,    // asynchronous active low reset
+    input             ena,      // core enable signal
+
+    input      [15:0] clk_cnt,  // clock prescale value
+
+    input      [ 3:0] cmd,      // command (from byte controller)
+    output reg        cmd_ack,  // command complete acknowledge
+    output reg        busy,     // i2c bus busy
+    output reg        al,       // i2c bus arbitration lost
+
+    input             din,
+    output reg        dout,
+
+    input             scl_i,    // i2c clock line input
+    output            scl_o,    // i2c clock line output
+    output reg        scl_oen,  // i2c clock line output enable (active low)
+    input             sda_i,    // i2c data line input
+    output            sda_o,    // i2c data line output
+    output reg        sda_oen,   // i2c data line output enable (active low)
+	output				TP1,
+	output				TP2
+);
+
+
+    //
+    // variable declarations
+    //
+
+    reg [ 1:0] cSCL, cSDA;      // capture SCL and SDA
+    reg [ 2:0] fSCL, fSDA;      // SCL and SDA filter inputs
+    reg        sSCL, sSDA;      // filtered and synchronized SCL and SDA inputs
+    reg        dSCL, dSDA;      // delayed versions of sSCL and sSDA
+    reg        dscl_oen;        // delayed scl_oen
+    reg        sda_chk;         // check SDA output (Multi-master arbitration)
+    reg        clk_en;          // clock generation signals
+    reg        slave_wait;      // slave inserts wait states
+    reg [15:0] cnt;             // clock divider counter (synthesis)
+    reg [13:0] filter_cnt;      // clock divider for filter
+
+	assign TP1 = cnt[0];
+	assign TP2 = cnt[1];
+
+    // state machine variable
+    reg [17:0] c_state; // synopsys enum_state
+
+    //
+    // module body
+    //
+
+    // whenever the slave is not ready it can delay the cycle by pulling SCL low
+    // delay scl_oen
+    always @(posedge clk)
+      dscl_oen <= #1 scl_oen;
+
+    // slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
+    // slave_wait remains asserted until the slave releases SCL
+    always @(posedge clk or posedge Reset)
+      if (Reset) slave_wait <= 1'b0;
+      else         slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
+
+    // master drives SCL high, but another master pulls it low
+    // master start counting down its low cycle now (clock synchronization)
+    wire scl_sync   = dSCL & ~sSCL & scl_oen;
+
+
+    // generate clk enable signal
+    always @(posedge clk or posedge Reset)
+      if (Reset)
+      begin
+          cnt    <= #1 16'h0;
+          clk_en <= #1 1'b1;
+      end
+      else if (rst || ~|cnt || !ena || scl_sync)
+      begin
+          cnt    <= #1 clk_cnt;
+          clk_en <= #1 1'b1;
+      end
+      else if (slave_wait)
+      begin
+          cnt    <= #1 cnt;
+          clk_en <= #1 1'b0;    
+      end
+      else
+      begin
+          cnt    <= #1 cnt - 16'h1;
+          clk_en <= #1 1'b0;
+      end
+
+
+    // generate bus status controller
+
+    // capture SDA and SCL
+    // reduce metastability risk
+    always @(posedge clk or posedge Reset)
+      if (Reset)
+      begin
+          cSCL <= #1 2'b00;
+          cSDA <= #1 2'b00;
+      end
+      else if (rst)
+      begin
+          cSCL <= #1 2'b00;
+          cSDA <= #1 2'b00;
+      end
+      else
+      begin
+          cSCL <= {cSCL[0],scl_i};
+          cSDA <= {cSDA[0],sda_i};
+      end
+
+
+    // filter SCL and SDA signals; (attempt to) remove glitches
+    always @(posedge clk or posedge Reset)
+      if      (Reset     ) filter_cnt <= 14'h0;
+      else if (rst || !ena ) filter_cnt <= 14'h0;
+      else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
+      else                   filter_cnt <= filter_cnt -1;
+
+
+    always @(posedge clk or posedge Reset)
+      if (Reset)
+      begin
+          fSCL <= 3'b111;
+          fSDA <= 3'b111;
+      end
+      else if (rst)
+      begin
+          fSCL <= 3'b111;
+          fSDA <= 3'b111;
+      end
+      else if (~|filter_cnt)
+      begin
+          fSCL <= {fSCL[1:0],cSCL[1]};
+          fSDA <= {fSDA[1:0],cSDA[1]};
+      end
+
+
+    // generate filtered SCL and SDA signals
+    always @(posedge clk or posedge Reset)
+      if (Reset)
+      begin
+          sSCL <= #1 1'b1;
+          sSDA <= #1 1'b1;
+
+          dSCL <= #1 1'b1;
+          dSDA <= #1 1'b1;
+      end
+      else if (rst)
+      begin
+          sSCL <= #1 1'b1;
+          sSDA <= #1 1'b1;
+
+          dSCL <= #1 1'b1;
+          dSDA <= #1 1'b1;
+      end
+      else
+      begin
+          sSCL <= #1 &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
+          sSDA <= #1 &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
+
+          dSCL <= #1 sSCL;
+          dSDA <= #1 sSDA;
+      end
+
+    // detect start condition => detect falling edge on SDA while SCL is high
+    // detect stop condition => detect rising edge on SDA while SCL is high
+    reg sta_condition;
+    reg sto_condition;
+    always @(posedge clk or posedge Reset)
+      if (Reset)
+      begin
+          sta_condition <= #1 1'b0;
+          sto_condition <= #1 1'b0;
+      end
+      else if (rst)
+      begin
+          sta_condition <= #1 1'b0;
+          sto_condition <= #1 1'b0;
+      end
+      else
+      begin
+          sta_condition <= #1 ~sSDA &  dSDA & sSCL;
+          sto_condition <= #1  sSDA & ~dSDA & sSCL;
+      end
+
+
+    // generate i2c bus busy signal
+    always @(posedge clk or posedge Reset)
+      if      (Reset) busy <= #1 1'b0;
+      else if (rst  ) busy <= #1 1'b0;
+      else              busy <= #1 (sta_condition | busy) & ~sto_condition;
+
+
+    // generate arbitration lost signal
+    // aribitration lost when:
+    // 1) master drives SDA high, but the i2c bus is low
+    // 2) stop detected while not requested
+    reg cmd_stop;
+    always @(posedge clk or posedge Reset)
+      if (Reset)
+          cmd_stop <= #1 1'b0;
+      else if (rst)
+          cmd_stop <= #1 1'b0;
+      else if (clk_en)
+          cmd_stop <= #1 cmd == `I2C_CMD_STOP;
+
+    always @(posedge clk or posedge Reset)
+      if (Reset)
+          al <= #1 1'b0;
+      else if (rst)
+          al <= #1 1'b0;
+      else
+          al <= 0;
+          // al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
+
+
+    // generate dout signal (store SDA on rising edge of SCL)
+    always @(posedge clk)
+      if (sSCL & ~dSCL) dout <= #1 sSDA;
+
+
+    // generate statemachine
+
+    // nxt_state decoder
+    parameter [17:0] idle    = 18'b0_0000_0000_0000_0000;
+    parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
+    parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
+    parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
+    parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
+    parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
+    parameter [17:0] stop_a  = 18'b0_0000_0000_0010_0000;
+    parameter [17:0] stop_b  = 18'b0_0000_0000_0100_0000;
+    parameter [17:0] stop_c  = 18'b0_0000_0000_1000_0000;
+    parameter [17:0] stop_d  = 18'b0_0000_0001_0000_0000;
+    parameter [17:0] rd_a    = 18'b0_0000_0010_0000_0000;
+    parameter [17:0] rd_b    = 18'b0_0000_0100_0000_0000;
+    parameter [17:0] rd_c    = 18'b0_0000_1000_0000_0000;
+    parameter [17:0] rd_d    = 18'b0_0001_0000_0000_0000;
+    parameter [17:0] wr_a    = 18'b0_0010_0000_0000_0000;
+    parameter [17:0] wr_b    = 18'b0_0100_0000_0000_0000;
+    parameter [17:0] wr_c    = 18'b0_1000_0000_0000_0000;
+    parameter [17:0] wr_d    = 18'b1_0000_0000_0000_0000;
+
+    always @(posedge clk or posedge Reset)
+      if (Reset)
+      begin
+          c_state <= #1 idle;
+          cmd_ack <= #1 1'b0;
+          scl_oen <= #1 1'b1;
+          sda_oen <= #1 1'b1;
+          sda_chk <= #1 1'b0;
+      end
+      else if (rst | al)
+      begin
+          c_state <= #1 idle;
+          cmd_ack <= #1 1'b0;
+          scl_oen <= #1 1'b1;
+          sda_oen <= #1 1'b1;
+          sda_chk <= #1 1'b0;
+      end
+      else
+      begin
+          cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
+
+          if (clk_en)
+              case (c_state) // synopsys full_case parallel_case
+                    // idle state
+                    idle:
+                    begin
+                        case (cmd) // synopsys full_case parallel_case
+                             `I2C_CMD_START: c_state <= #1 start_a;
+                             `I2C_CMD_STOP:  c_state <= #1 stop_a;
+                             `I2C_CMD_WRITE: c_state <= #1 wr_a;
+                             `I2C_CMD_READ:  c_state <= #1 rd_a;
+                             default:        c_state <= #1 idle;
+                        endcase
+
+                        scl_oen <= #1 scl_oen; // keep SCL in same state
+                        sda_oen <= #1 sda_oen; // keep SDA in same state
+                        sda_chk <= #1 1'b0;    // don't check SDA output
+                    end
+
+                    // start
+                    start_a:
+                    begin
+                        c_state <= #1 start_b;
+                        scl_oen <= #1 scl_oen; // keep SCL in same state
+                        sda_oen <= #1 1'b1;    // set SDA high
+                        sda_chk <= #1 1'b0;    // don't check SDA output
+                    end
+
+                    start_b:
+                    begin
+                        c_state <= #1 start_c;
+                        scl_oen <= #1 1'b1; // set SCL high
+                        sda_oen <= #1 1'b1; // keep SDA high
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    start_c:
+                    begin
+                        c_state <= #1 start_d;
+                        scl_oen <= #1 1'b1; // keep SCL high
+                        sda_oen <= #1 1'b0; // set SDA low
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    start_d:
+                    begin
+                        c_state <= #1 start_e;
+                        scl_oen <= #1 1'b1; // keep SCL high
+                        sda_oen <= #1 1'b0; // keep SDA low
+                        sda_chk <= #1 1'b0; // don't check SDA output
+						if(clk_cnt == 0) cmd_ack <= #1 1'b1;
+                    end
+
+                    start_e:
+                    begin
+                        c_state <= #1 idle;
+                        if(clk_cnt == 0) cmd_ack <= #1 1'b0;
+						else cmd_ack <= #1 1'b1;
+                        scl_oen <= #1 1'b0; // set SCL low
+                        sda_oen <= #1 1'b0; // keep SDA low
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    // stop
+                    stop_a:
+                    begin
+                        c_state <= #1 stop_b;
+                        scl_oen <= #1 1'b0; // keep SCL low
+                        sda_oen <= #1 1'b0; // set SDA low
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    stop_b:
+                    begin
+                        c_state <= #1 stop_c;
+                        scl_oen <= #1 1'b1; // set SCL high
+                        sda_oen <= #1 1'b0; // keep SDA low
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    stop_c:
+                    begin
+                        c_state <= #1 stop_d;
+						cmd_ack <= #1 1'b1;
+                        scl_oen <= #1 1'b1; // keep SCL high
+                        sda_oen <= #1 1'b0; // keep SDA low
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    stop_d:
+                    begin
+                        c_state <= #1 idle;
+						cmd_ack <= #1 1'b0;
+                        scl_oen <= #1 1'b1; // keep SCL high
+                        sda_oen <= #1 1'b1; // set SDA high
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    // read
+                    rd_a:
+                    begin
+                        c_state <= #1 rd_b;
+                        scl_oen <= #1 1'b0; // keep SCL low
+                        sda_oen <= #1 1'b1; // tri-state SDA
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    rd_b:
+                    begin
+                        c_state <= #1 rd_c;
+                        scl_oen <= #1 1'b1; // set SCL high
+                        sda_oen <= #1 1'b1; // keep SDA tri-stated
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    rd_c:
+                    begin
+                        c_state <= #1 rd_d;
+                        scl_oen <= #1 1'b1; // keep SCL high
+                        sda_oen <= #1 1'b1; // keep SDA tri-stated
+                        sda_chk <= #1 1'b0; // don't check SDA output
+						if (clk_cnt == 0) cmd_ack <= #1 1'b1;
+                    end
+
+                    rd_d:
+                    begin
+                        c_state <= #1 idle;
+						if (clk_cnt == 0) cmd_ack <= #1 0;
+						else cmd_ack <= #1 1;
+                        scl_oen <= #1 1'b0; // set SCL low
+                        sda_oen <= #1 1'b1; // keep SDA tri-stated
+                        sda_chk <= #1 1'b0; // don't check SDA output
+                    end
+
+                    // write
+                    wr_a:
+                    begin
+                        c_state <= #1 wr_b;
+                        scl_oen <= #1 1'b0; // keep SCL low
+                        sda_oen <= #1 din;  // set SDA
+                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
+                    end
+
+                    wr_b:
+                    begin
+                        c_state <= #1 wr_c;
+                        scl_oen <= #1 1'b1; // set SCL high
+                        sda_oen <= #1 din;  // keep SDA
+                        sda_chk <= #1 1'b0; // don't check SDA output yet
+                                            // allow some time for SDA and SCL to settle
+                    end
+
+                    wr_c:
+                    begin
+                        c_state <= #1 wr_d;
+                        scl_oen <= #1 1'b1; // keep SCL high
+                        sda_oen <= #1 din;
+                        sda_chk <= #1 1'b1; // check SDA output
+						if (clk_cnt == 0) cmd_ack <= #1 1'b1; 
+                    end
+
+                    wr_d:
+                    begin
+                        c_state <= #1 idle;
+						if (clk_cnt == 0) cmd_ack <= #1 0;  
+						else cmd_ack <= #1 1;
+                        scl_oen <= #1 1'b0; // set SCL low
+                        sda_oen <= #1 din;
+                        sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
+                    end
+
+              endcase
+      end
+
+
+    // assign scl and sda output (always gnd)
+    assign scl_o = 1'b0;
+    assign sda_o = 1'b0;
+
+endmodule
diff --git a/BENCHMARK/i2c_master_top/rtl/i2c_master_byte_ctrl.v b/BENCHMARK/i2c_master_top/rtl/i2c_master_byte_ctrl.v
new file mode 100644
index 0000000..f97f91b
--- /dev/null
+++ b/BENCHMARK/i2c_master_top/rtl/i2c_master_byte_ctrl.v
@@ -0,0 +1,386 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master byte-controller       ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_byte_ctrl.v,v 1.8 2009-01-19 20:29:26 rherveille Exp $
+//
+//  $Date: 2009-01-19 20:29:26 $
+//  $Revision: 1.8 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.7  2004/02/18 11:40:46  rherveille
+//               Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
+//
+//               Revision 1.6  2003/08/09 07:01:33  rherveille
+//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+//               Fixed a potential bug in the byte controller's host-acknowledge generation.
+//
+//               Revision 1.5  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.4  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.3  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+///////////////////////////////////////////////////////////////////////
+// QuickLogic Change History:
+// 
+// Date: February 12, 2014
+// Engineer: Anthony Le
+// Issue: i2c SDA to SCL timing violation
+// Change:
+//   1. Generate LD during IDLE to speed up the input data to SR
+// 
+
+// synopsys translate_off
+// synopsys translate_on
+`timescale 1ns / 10ps
+
+`include "i2c_master_defines.v"
+
+module i2c_master_byte_ctrl (
+	clk, rst, Reset, ena, clk_cnt, start, stop, read, write, ack_in, din,
+	cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen, DrivingI2cBusOut,
+	TP1,
+	TP2	);
+
+	//
+	// inputs & outputs
+	//
+	input clk;     // master clock
+	input rst;     // synchronous active high reset
+	input Reset;  // asynchronous active high reset
+	input ena;     // core enable signal
+
+	input [15:0] clk_cnt; // 4x SCL
+
+	// control inputs
+	input       start;
+	input       stop;
+	input       read;
+	input       write;
+	input       ack_in;
+	input [7:0] din;
+
+	// status outputs
+	output       cmd_ack;
+	reg cmd_ack;
+	output       ack_out;
+	reg ack_out;
+	output       i2c_busy;
+	output       i2c_al;
+	output [7:0] dout;
+
+	// I2C signals
+	input  scl_i;
+	output scl_o;
+	output scl_oen;
+	input  sda_i;
+	output sda_o;
+	output sda_oen;
+	
+	// control signals
+	output		DrivingI2cBusOut;
+	
+	// test signals
+	output	TP1;
+	output	TP2;
+
+
+	//
+	// Variable declarations
+	//
+
+	// statemachine
+	parameter [5:0] ST_IDLE  = 6'b00_0000;
+	parameter [5:0] ST_START = 6'b00_0001;
+	parameter [5:0] ST_READ  = 6'b00_0010;
+	parameter [5:0] ST_WRITE = 6'b00_0100;
+	parameter [5:0] ST_ACK   = 6'b00_1000;
+	parameter [5:0] ST_STOP  = 6'b01_0000;
+	parameter [5:0] ST_DLWR  = 6'b10_0000;
+
+	// signals for bit_controller
+	reg  [3:0] core_cmd;
+	reg        core_txd;
+	wire       core_ack, core_rxd;
+
+	// signals for shift register
+	reg [7:0] sr; //8bit shift register
+	reg       shift, ld;
+
+	// signals for state machine
+	wire       go;
+	reg  [2:0] dcnt;
+	wire       cnt_done;
+
+	//
+	// Module body
+	//
+	assign	DrivingI2cBusOut = (core_cmd != `I2C_CMD_READ);
+
+	// hookup bit_controller
+	i2c_master_bit_ctrl bit_controller (
+		.clk     ( clk      ),
+		.rst     ( rst      ),
+		.Reset   ( Reset   ),
+		.ena     ( ena      ),
+		.clk_cnt ( clk_cnt  ),
+		.cmd     ( core_cmd ),
+		.cmd_ack ( core_ack ),
+		.busy    ( i2c_busy ),
+		.al      ( i2c_al   ),
+		.din     ( core_txd ),
+		.dout    ( core_rxd ),
+		.scl_i   ( scl_i    ),
+		.scl_o   ( scl_o    ),
+		.scl_oen ( scl_oen  ),
+		.sda_i   ( sda_i    ),
+		.sda_o   ( sda_o    ),
+		.sda_oen ( sda_oen  ),
+		.TP1	 ( TP1		),
+		.TP2	 ( TP2		)
+	);
+
+	// generate go-signal
+	assign go = (read | write | stop) & ~cmd_ack;
+
+	// assign dout output to shift-register
+	assign dout = sr;
+
+  //
+  // state machine
+  //
+  reg [5:0] c_state; // synopsys enum_state
+
+	// generate shift register
+	// always @(posedge clk or posedge Reset)
+	  // if (Reset)
+	    // sr <= #1 8'h0;
+	  // else if (rst)
+	    // sr <= #1 8'h0;
+	  // else if (ld)
+	    // sr <= #1 din;
+	  // else if (shift && clk_cnt !=0)
+		// sr <= #1 {sr[6:0], core_rxd}; 
+	  // else if (shift && c_state != ST_WRITE)
+	    // sr <= #1 {sr[6:0], core_rxd};  
+
+	// generate counter
+	always @(posedge clk or posedge Reset)
+	  if (Reset)
+	    dcnt <= #1 3'h0;
+	  else if (rst)
+	    dcnt <= #1 3'h0;
+	  else if (ld)
+	    dcnt <= #1 3'h7;
+	  else if (shift)
+	    dcnt <= #1 dcnt - 3'h1;
+
+	assign cnt_done = ~(|dcnt);
+
+	always @(posedge clk or posedge Reset)
+	  if (Reset)
+	    begin
+			sr <= #1 8'h0;
+	        core_cmd <= #1 `I2C_CMD_NOP;
+	        core_txd <= #1 1'b0;
+	        shift    <= #1 1'b0;
+	        ld       <= #1 1'b0;
+	        cmd_ack  <= #1 1'b0;
+	        c_state  <= #1 ST_IDLE;
+	        ack_out  <= #1 1'b0;
+	    end
+	  else if (rst | i2c_al)
+	   begin
+			sr <= #1 8'h0;
+	       core_cmd <= #1 `I2C_CMD_NOP;
+	       core_txd <= #1 1'b0;
+	       shift    <= #1 1'b0;
+	       ld       <= #1 1'b0;
+	       cmd_ack  <= #1 1'b0;
+	       c_state  <= #1 ST_IDLE;
+	       ack_out  <= #1 1'b0;
+	   end
+	else
+	  begin
+	  if (ld)
+	    sr <= #1 din;
+	  else if (shift && clk_cnt !=0)
+		sr <= #1 {sr[6:0], core_rxd}; 
+	  else if (shift && c_state != ST_WRITE)
+	    sr <= #1 {sr[6:0], core_rxd};  
+	      // initially reset all signals
+	      core_txd <= #1 sr[7];
+	      shift    <= #1 1'b0;
+	      ld       <= #1 1'b0;
+	      cmd_ack  <= #1 1'b0;
+
+	      case (c_state) // synopsys full_case parallel_case
+	        ST_IDLE:
+	          if (go)
+	            begin
+	                if (start)
+	                  begin
+	                      c_state  <= #1 ST_START;
+	                      core_cmd <= #1 `I2C_CMD_START;
+	                  end
+	                else if (read)
+	                  begin
+	                      c_state  <= #1 ST_READ;
+	                      core_cmd <= #1 `I2C_CMD_READ;
+	                  end
+	                else if (write)
+	                  begin
+	                      c_state  <= #1 ST_DLWR;
+	                      core_cmd <= #1 `I2C_CMD_NOP;
+	                  end
+	                else // stop
+	                  begin
+	                      c_state  <= #1 ST_STOP;
+	                      core_cmd <= #1 `I2C_CMD_STOP;
+	                  end
+
+	                ld <= #1 1'b1;
+	            end
+
+	        ST_START:
+	          if (core_ack)
+	            begin
+	                if (read)
+	                  begin
+	                      c_state  <= #1 ST_READ;
+	                      core_cmd <= #1 `I2C_CMD_READ;
+	                  end
+	                else
+	                  begin
+	                      c_state  <= #1 ST_WRITE;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+
+	                ld <= #1 1'b1;
+	            end
+				
+			ST_DLWR:
+			begin
+	             c_state  <= #1 ST_WRITE;
+	             core_cmd <= #1 `I2C_CMD_WRITE;
+	        end
+
+	        ST_WRITE:
+	          if (core_ack)
+	            if (cnt_done)
+	              begin
+	                  c_state  <= #1 ST_ACK;
+	                  core_cmd <= #1 `I2C_CMD_READ;
+	              end
+	            else
+	              begin
+	                  c_state  <= #1 ST_WRITE;       // stay in same state
+	                  core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
+	                  shift    <= #1 1'b1;
+					  if (clk_cnt == 0) sr <= #1 {sr[6:0], core_rxd};
+	              end
+
+	        ST_READ:
+	          if (core_ack)
+	            begin
+	                if (cnt_done)
+	                  begin
+	                      c_state  <= #1 ST_ACK;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+	                else
+	                  begin
+	                      c_state  <= #1 ST_READ;       // stay in same state
+	                      core_cmd <= #1 `I2C_CMD_READ; // read next bit
+	                  end
+
+	                shift    <= #1 1'b1;
+					//sr <= #1 {sr[6:0], core_rxd};
+	                core_txd <= #1 ack_in;
+	            end
+
+	        ST_ACK:
+	          if (core_ack)
+	            begin
+	               if (stop)
+	                 begin
+	                     c_state  <= #1 ST_STOP;
+	                     core_cmd <= #1 `I2C_CMD_STOP;
+	                 end
+	               else
+	                 begin
+	                     c_state  <= #1 ST_IDLE;
+	                     core_cmd <= #1 `I2C_CMD_NOP;
+
+	                     // generate command acknowledge signal
+	                     cmd_ack  <= #1 1'b1;
+	                 end
+
+	                 // assign ack_out output to bit_controller_rxd (contains last received bit)
+	                 ack_out <= #1 core_rxd;
+
+	                 core_txd <= #1 1'b1;
+					 
+					 if (clk_cnt == 0) shift <= #1 1;
+	             end
+	           else
+	             core_txd <= #1 ack_in;
+
+	        ST_STOP:
+	          if (core_ack)
+	            begin
+	                c_state  <= #1 ST_IDLE;
+	                core_cmd <= #1 `I2C_CMD_NOP;
+
+	                // generate command acknowledge signal
+	                cmd_ack  <= #1 1'b1;
+	            end
+
+	      endcase
+	  end
+endmodule
diff --git a/BENCHMARK/i2c_master_top/rtl/i2c_master_defines.v b/BENCHMARK/i2c_master_top/rtl/i2c_master_defines.v
new file mode 100644
index 0000000..e81c546
--- /dev/null
+++ b/BENCHMARK/i2c_master_top/rtl/i2c_master_defines.v
@@ -0,0 +1,59 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master controller defines    ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_defines.v,v 1.3 2001-11-05 11:59:25 rherveille Exp $
+//
+//  $Date: 2001-11-05 11:59:25 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+
+
+// I2C registers wishbone addresses
+
+// bitcontroller states
+`define I2C_CMD_NOP   4'b0000
+`define I2C_CMD_START 4'b0001
+`define I2C_CMD_STOP  4'b0010
+`define I2C_CMD_WRITE 4'b0100
+`define I2C_CMD_READ  4'b1000
diff --git a/BENCHMARK/i2c_master_top/rtl/i2c_master_top.v b/BENCHMARK/i2c_master_top/rtl/i2c_master_top.v
new file mode 100644
index 0000000..84b5564
--- /dev/null
+++ b/BENCHMARK/i2c_master_top/rtl/i2c_master_top.v
@@ -0,0 +1,323 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE revB.2 compliant I2C Master controller Top-level  ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+// 1.12	2012-12-17 Tim Saxe
+//	Changed wb_ack_o to be derived from in internal version
+//	wb_ack_i
+
+//  CVS Log
+//
+//  $Id: i2c_master_top.v,v 1.12 2009-01-19 20:29:26 rherveille Exp $
+//
+//  $Date: 2009-01-19 20:29:26 $
+//  $Revision: 1.12 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               Revision 1.11  2005/02/27 09:26:24  rherveille
+//               Fixed register overwrite issue.
+//               Removed full_case pragma, replaced it by a default statement.
+//
+//               Revision 1.10  2003/09/01 10:34:38  rherveille
+//               Fix a blocking vs. non-blocking error in the wb_dat output mux.
+//
+//               Revision 1.9  2003/01/09 16:44:45  rherveille
+//               Fixed a bug in the Command Register declaration.
+//
+//               Revision 1.8  2002/12/26 16:05:12  rherveille
+//               Small code simplifications
+//
+//               Revision 1.7  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.6  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.5  2001/11/10 10:52:55  rherveille
+//               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
+//
+
+// synopsys translate_off
+// synopsys translate_on
+`timescale 1ns / 10ps
+
+`include "i2c_master_defines.v"
+
+module i2c_master_top(
+	wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
+	wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
+	scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o, tip_o, DrivingI2cBusOut,
+	TP1,
+	TP2);
+
+	// parameters
+
+	//
+	// inputs & outputs
+	//
+
+	// wishbone signals
+	input        wb_clk_i;     // master clock input
+	input        wb_rst_i;     // synchronous active high reset
+	input        arst_i;       // asynchronous reset
+	input  [2:0] wb_adr_i;     // lower address bits
+	input  [7:0] wb_dat_i;     // databus input
+	output [7:0] wb_dat_o;     // databus output
+	input        wb_we_i;      // write enable input
+	input        wb_stb_i;     // stobe/core select signal
+	input        wb_cyc_i;     // valid bus cycle input
+	inout        wb_ack_o;     // bus cycle acknowledge output
+	output       wb_inta_o;   	// interrupt request signal output
+	
+	// control signals
+	output		tip_o;				// transfer in progress
+	output		DrivingI2cBusOut;	// master is driving i2c bus
+
+	reg [7:0] wb_dat_o;
+	reg wb_ack_i;
+	wire wb_ack_o = wb_ack_i;
+	reg wb_inta_o;
+
+	// I2C signals
+	// i2c clock line
+	input  scl_pad_i;       // SCL-line input
+	output scl_pad_o;       // SCL-line output (always 1'b0)
+	output scl_padoen_o;    // SCL-line output enable (active low)
+
+	// i2c data line
+	input  sda_pad_i;       // SDA-line input
+	output sda_pad_o;       // SDA-line output (always 1'b0)
+	output sda_padoen_o;    // SDA-line output enable (active low)
+	
+	// test signal
+	output	TP1;
+	output	TP2;
+
+
+	//
+	// variable declarations
+	//
+
+	// registers
+	reg  [15:0] prer; // clock prescale register
+	reg  [ 7:0] ctr;  // control register
+	reg  [ 7:0] txr;  // transmit register
+	wire [ 7:0] rxr;  // receive register
+	reg  [ 7:0] cr;   // command register
+	wire [ 7:0] sr;   // status register
+
+	// done signal: command completed, clear command register
+	wire done;
+
+	// core enable signal
+	wire core_en;
+	wire ien;
+
+	// status register signals
+	wire irxack;
+	reg  rxack;       // received aknowledge from slave
+	reg  tip;         // transfer in progress
+	reg  irq_flag;    // interrupt pending flag
+	wire i2c_busy;    // bus busy (start signal detected)
+	wire i2c_al;      // i2c bus arbitration lost
+	reg  al;          // status register arbitration lost bit
+
+	//
+	// module body
+	//
+
+	assign tip_o = tip;
+	
+	// generate internal reset
+	wire rst_i = arst_i;
+
+	// generate wishbone signals
+	wire wb_wacc = wb_we_i & wb_ack_i;
+
+	// generate acknowledge output signal
+	always @(posedge wb_clk_i)
+	  wb_ack_i <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_i; // because timing is always honored
+
+	// assign DAT_O
+	always @(posedge wb_clk_i)
+	begin
+	  case (wb_adr_i) // synopsys parallel_case
+	    3'b000: wb_dat_o <= #1 prer[ 7:0];
+	    3'b001: wb_dat_o <= #1 prer[15:8];
+	    3'b010: wb_dat_o <= #1 ctr;
+	    3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
+	    3'b100: wb_dat_o <= #1 sr;  // write is command register (cr)
+	    3'b101: wb_dat_o <= #1 txr;
+	    3'b110: wb_dat_o <= #1 cr;
+	    3'b111: wb_dat_o <= #1 0;   // reserved
+	  endcase
+	end
+
+	// generate registers
+	always @(posedge wb_clk_i or posedge rst_i)
+	  if (rst_i)
+	    begin
+	        // prer <= #1 16'hffff;
+	        // ctr  <= #1  8'h0;
+			prer <= #1 16'h0000;
+	        ctr  <= #1  8'h80;
+	        txr  <= #1  8'h0;
+	    end
+	  else if (wb_rst_i)
+	    begin
+	        // prer <= #1 16'hffff;
+	        // ctr  <= #1  8'h0;
+			prer <= #1 16'h0000;
+	        ctr  <= #1  8'h80;
+	        txr  <= #1  8'h0;
+	    end
+	  else
+	   if (wb_wacc)
+	      case (wb_adr_i) // synopsys parallel_case
+	        // 3'b000 : prer [ 7:0] <= #1 wb_dat_i;
+	        // 3'b001 : prer [15:8] <= #1 wb_dat_i;
+	        // 3'b010 : ctr         <= #1 wb_dat_i;
+	         3'b011 : txr         <= #1 wb_dat_i;
+	         default: ;
+	      endcase
+
+	// generate command register (special case)
+	always @(posedge wb_clk_i or posedge rst_i)
+	  if (rst_i)
+	    cr <= #1 8'h0;
+	  else if (wb_rst_i)
+	    cr <= #1 8'h0;
+	  else if (wb_wacc)
+	    begin
+	        if (core_en & (wb_adr_i == 3'b100) )
+	          cr <= #1 wb_dat_i;
+	    end
+	  else
+	    begin
+	        if (done | i2c_al)
+	          cr[7:4] <= #1 4'h0;           // clear command bits when done
+	                                        // or when aribitration lost
+	        cr[2:1] <= #1 2'b0;             // reserved bits
+	        cr[0]   <= #1 1'b0;             // clear IRQ_ACK bit
+	    end
+
+
+	// decode command register
+	wire sta  = cr[7];
+	wire sto  = cr[6];
+	wire rd   = cr[5];
+	wire wr   = cr[4];
+	wire ack  = cr[3];
+	wire iack = cr[0];
+
+	// decode control register
+	assign core_en = ctr[7];
+	assign ien = ctr[6];
+
+	// hookup byte controller block
+	i2c_master_byte_ctrl byte_controller (
+		.clk      ( wb_clk_i     ),
+		.rst      ( wb_rst_i     ),
+		.Reset    ( rst_i        ),
+		.ena      ( core_en      ),
+		.clk_cnt  ( prer         ),
+		.start    ( sta          ),
+		.stop     ( sto          ),
+		.read     ( rd           ),
+		.write    ( wr           ),
+		.ack_in   ( ack          ),
+		.din      ( txr          ),
+		.cmd_ack  ( done         ),
+		.ack_out  ( irxack       ),
+		.dout     ( rxr          ),
+		.i2c_busy ( i2c_busy     ),
+		.i2c_al   ( i2c_al       ),
+		.scl_i    ( scl_pad_i    ),
+		.scl_o    ( scl_pad_o    ),
+		.scl_oen  ( scl_padoen_o ),
+		.sda_i    ( sda_pad_i    ),
+		.sda_o    ( sda_pad_o    ),
+		.sda_oen  ( sda_padoen_o ),
+		.DrivingI2cBusOut (DrivingI2cBusOut),
+		.TP1	  ( TP1 		 ),
+		.TP2	  ( TP2			 )
+	);
+
+	// status register block + interrupt request signal
+	always @(posedge wb_clk_i or posedge rst_i)
+	  if (rst_i)
+	    begin
+	        al       <= #1 1'b0;
+	        rxack    <= #1 1'b0;
+	        tip      <= #1 1'b0;
+	        irq_flag <= #1 1'b0;
+	    end
+	  else if (wb_rst_i)
+	    begin
+	        al       <= #1 1'b0;
+	        rxack    <= #1 1'b0;
+	        tip      <= #1 1'b0;
+	        irq_flag <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        al       <= #1 i2c_al | (al & ~sta);
+	        rxack    <= #1 irxack;
+	        tip      <= #1 (rd | wr);
+	        irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
+	    end
+
+	// generate interrupt request signals
+	always @(posedge wb_clk_i or posedge rst_i)
+	  if (rst_i)
+	    wb_inta_o <= #1 1'b0;
+	  else if (wb_rst_i)
+	    wb_inta_o <= #1 1'b0;
+	  else
+	    wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
+
+	// assign status register bits
+	assign sr[7]   = rxack;
+	assign sr[6]   = i2c_busy;
+	assign sr[5]   = al;
+	assign sr[4:2] = 3'h0; // reserved
+	assign sr[1]   = tip;
+	assign sr[0]   = irq_flag;
+
+endmodule
diff --git a/BENCHMARK/iir/iir_yosys.blif b/BENCHMARK/iir/iir_yosys.blif
new file mode 100644
index 0000000..f8703fc
--- /dev/null
+++ b/BENCHMARK/iir/iir_yosys.blif
@@ -0,0 +1,14847 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model iir
+.inputs clk reset start din(0) din(1) din(2) din(3) din(4) din(5) din(6) din(7) params(0) params(1) params(2) params(3) params(4) params(5) params(6) params(7) params(8) params(9) params(10) params(11) params(12) params(13) params(14) params(15) iir_start
+.outputs dout(0) dout(1) dout(2) dout(3) dout(4) dout(5) dout(6) dout(7) ready iir_done
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_1 a=$auto$hilomap.cc:39:hilomap_worker$18951
+.subckt logic_0 a=temp_yk(0)
+.subckt in_buff A=clk Q=$iopadmap$clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(0) Q=$iopadmap$din(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(1) Q=$iopadmap$din(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(2) Q=$iopadmap$din(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(3) Q=$iopadmap$din(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(4) Q=$iopadmap$din(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(5) Q=$iopadmap$din(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(6) Q=$iopadmap$din(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(7) Q=$iopadmap$din(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=$iopadmap$dout(0) Q=dout(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$dout(1) Q=dout(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=a2(4) D=temp_a2(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
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+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=a2(10) D=temp_a2(10) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=a2(9) D=temp_a2(9) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=a2(8) D=temp_a2(8) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=a2(7) D=temp_a2(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=a2(6) D=temp_a2(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(15) D=temp_b0(15) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(14) D=temp_b0(14) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(5) D=temp_b0(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(4) D=temp_b0(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(3) D=temp_b0(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(2) D=temp_b0(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(1) D=temp_b0(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(0) D=temp_b0(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(13) D=temp_b0(13) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(12) D=temp_b0(12) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(11) D=temp_b0(11) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(10) D=temp_b0(10) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(9) D=temp_b0(9) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(8) D=temp_b0(8) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(7) D=temp_b0(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b0(6) D=temp_b0(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(15) D=temp_b1(15) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(14) D=temp_b1(14) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(5) D=temp_b1(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(4) D=temp_b1(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(3) D=temp_b1(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(2) D=temp_b1(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(1) D=temp_b1(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(0) D=temp_b1(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(13) D=temp_b1(13) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(12) D=temp_b1(12) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(11) D=temp_b1(11) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(10) D=temp_b1(10) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(9) D=temp_b1(9) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(8) D=temp_b1(8) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(7) D=temp_b1(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b1(6) D=temp_b1(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(15) D=temp_b2(15) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(14) D=temp_b2(14) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(5) D=temp_b2(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(4) D=temp_b2(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(3) D=temp_b2(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(2) D=temp_b2(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(1) D=temp_b2(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(0) D=temp_b2(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(13) D=temp_b2(13) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(12) D=temp_b2(12) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(11) D=temp_b2(11) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(10) D=temp_b2(10) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(9) D=temp_b2(9) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(8) D=temp_b2(8) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(7) D=temp_b2(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=b2(6) D=temp_b2(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=finite_counter(4) I1=finite_counter(5) I2=finite_counter(6) I3=count0_LUT4_O_I3 O=count0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=finite_counter(4) I1=count0_LUT4_O_I3 I2=$iopadmap$reset I3=finite_counter(5) O=count0_LUT4_O_I3_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101111110100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=$iopadmap$reset I3=count0_LUT4_O_I3_LUT4_I2_O O=count0_LUT4_O_I3_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=$iopadmap$reset I3=count0_LUT4_O_I3_LUT4_I1_O_LUT4_O_1_I3 O=count0_LUT4_O_I3_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=finite_counter(0) I1=finite_counter(1) I2=finite_counter(2) I3=finite_counter(3) O=count0_LUT4_O_I3_LUT4_I1_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000111111110
+.subckt LUT4 I0=finite_counter(0) I1=finite_counter(1) I2=$iopadmap$reset I3=finite_counter(2) O=count0_LUT4_O_I3_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011110001
+.subckt LUT4 I0=temp_yk(0) I1=finite_counter(0) I2=finite_counter(1) I3=$iopadmap$reset O=count0_LUT4_O_I3_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=$iopadmap$reset I3=finite_counter(0) O=count0_LUT4_O_I3_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=finite_counter(4) I1=finite_counter(5) I2=count0_LUT4_O_I3 I3=finite_counter(6) O=count0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100010000
+.subckt LUT4 I0=temp_yk(0) I1=finite_counter(4) I2=count0_LUT4_O_I3 I3=$iopadmap$reset O=count0_LUT4_O_I3_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=finite_counter(0) I1=finite_counter(1) I2=finite_counter(2) I3=finite_counter(3) O=count0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=del_count0 D=count0 QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=temp_yk(0) QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:232.1-234.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=$iopadmap$dout(7) D=temp_dout(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=$iopadmap$dout(6) D=temp_dout(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=$iopadmap$dout(5) D=temp_dout(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=$iopadmap$dout(4) D=temp_dout(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=$iopadmap$dout(3) D=temp_dout(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=$iopadmap$dout(2) D=temp_dout(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=$iopadmap$dout(1) D=temp_dout(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=$iopadmap$dout(0) D=temp_dout(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=finite_counter(6) D=count0_LUT4_O_I3_LUT4_I1_O(6) QCK=$iopadmap$clk QEN=iir_start_LUT4_I2_O QRT=temp_yk(0) QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:220.1-228.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=finite_counter(5) D=count0_LUT4_O_I3_LUT4_I1_O(5) QCK=$iopadmap$clk QEN=iir_start_LUT4_I2_O QRT=temp_yk(0) QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:220.1-228.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=finite_counter(4) D=count0_LUT4_O_I3_LUT4_I1_O(4) QCK=$iopadmap$clk QEN=iir_start_LUT4_I2_O QRT=temp_yk(0) QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:220.1-228.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=finite_counter(3) D=count0_LUT4_O_I3_LUT4_I1_O(3) QCK=$iopadmap$clk QEN=iir_start_LUT4_I2_O QRT=temp_yk(0) QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:220.1-228.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=finite_counter(2) D=count0_LUT4_O_I3_LUT4_I1_O(2) QCK=$iopadmap$clk QEN=iir_start_LUT4_I2_O QRT=temp_yk(0) QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:220.1-228.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=finite_counter(1) D=count0_LUT4_O_I3_LUT4_I1_O(1) QCK=$iopadmap$clk QEN=iir_start_LUT4_I2_O QRT=temp_yk(0) QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:220.1-228.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=finite_counter(0) D=count0_LUT4_O_I3_LUT4_I1_O(0) QCK=$iopadmap$clk QEN=iir_start_LUT4_I2_O QRT=temp_yk(0) QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:220.1-228.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=count0 I3=del_count0 O=$iopadmap$iir_done
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$iir_start I1=temp_a2_LUT4_O_I1 I2=iir_start_LUT4_I0_I2 I3=iir_start_LUT4_I0_I3 O=iir_start_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=obf_state(1) I1=obf_state(0) I2=obf_state(3) I3=obf_state(2) O=iir_start_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=obf_state(3) I1=obf_state(1) I2=obf_state(0) I3=obf_state(2) O=iir_start_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=temp_a2_LUT4_O_I1 I1=$iopadmap$iir_start I2=iir_start_LUT4_I0_I2 I3=iir_start_LUT4_I1_I3 O=iir_start_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=temp_yk(0) I1=iir_start_LUT4_I1_I3_LUT4_O_I1 I2=$iopadmap$start I3=obf_state(1) O=iir_start_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=temp_yk(0) I1=obf_state(2) I2=obf_state(0) I3=obf_state(3) O=iir_start_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=$iopadmap$iir_start I3=$iopadmap$reset O=iir_start_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=temp_yk(0) I1=obf_next_state_LUT4_O_I1 I2=obf_next_state(3) I3=obf_next_state_LUT4_O_I3 O=obf_next_state(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=temp_yk2_LUT4_O_I1 I1=count0 I2=obf_next_state_LUT4_O_1_I2 I3=obf_next_state_LUT4_O_1_I3 O=obf_next_state(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011101011111111
+.subckt LUT4 I0=count0 I1=obf_next_state_LUT4_O_1_I2 I2=obf_next_state_LUT4_O_1_I2_LUT4_I1_I2 I3=temp_utmp_LUT4_O_I3 O=obf_next_state_LUT4_O_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=count0 I1=obf_next_state_LUT4_O_1_I2 I2=obf_next_state_LUT4_O_1_I2_LUT4_I1_I2 I3=temp_ysum_LUT4_O_I3 O=obf_next_state_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_wait_counter_LUT4_O_I3 I3=obf_next_state_LUT4_O_I3 O=obf_next_state_LUT4_O_1_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=obf_state(1) I1=obf_state(0) I2=obf_state(3) I3=obf_state(2) O=obf_next_state_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=temp_yk(0) I1=iir_start_LUT4_I0_I2 I2=obf_next_state(2) I3=obf_next_state_LUT4_O_I3 O=obf_next_state_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=temp_yk(0) I1=obf_next_state_LUT4_O_2_I1 I2=obf_next_state(1) I3=obf_next_state_LUT4_O_I3 O=obf_next_state(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=temp_yk(0) I1=obf_next_state_LUT4_O_2_I1_LUT4_O_I1 I2=obf_next_state_LUT4_O_3_I1_LUT4_O_I2 I3=iir_start_LUT4_I0_O O=obf_next_state_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=temp_yk(0) I1=obf_next_state_LUT4_O_3_I1 I2=obf_next_state(0) I3=obf_next_state_LUT4_O_I3 O=obf_next_state(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=temp_yk(0) I1=obf_next_state_LUT4_O_3_I1_LUT4_O_I1 I2=obf_next_state_LUT4_O_3_I1_LUT4_O_I2 I3=iir_start_LUT4_I1_O O=obf_next_state_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=obf_state(2) I1=obf_state(1) I2=obf_state(0) I3=obf_state(3) O=obf_next_state_LUT4_O_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100001111111
+.subckt LUT4 I0=obf_state(1) I1=obf_state(0) I2=obf_state(3) I3=obf_state(2) O=obf_next_state_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011100001111
+.subckt LUT4 I0=obf_state(1) I1=obf_state(0) I2=obf_state(3) I3=obf_state(2) O=obf_next_state_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111110
+.subckt ff CQZ=obf_state(3) D=obf_next_state(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=obf_state(2) D=obf_next_state(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=obf_state(1) D=obf_next_state(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=obf_state(0) D=obf_next_state(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=temp_yk(0) QST=$iopadmap$reset
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt ff CQZ=$iopadmap$ready D=temp_ready QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(15) I3=$iopadmap$params(15) O=temp_a1(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(14) I3=$iopadmap$params(14) O=temp_a1(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(5) I3=$iopadmap$params(5) O=temp_a1(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(4) I3=$iopadmap$params(4) O=temp_a1(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(3) I3=$iopadmap$params(3) O=temp_a1(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(2) I3=$iopadmap$params(2) O=temp_a1(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(1) I3=$iopadmap$params(1) O=temp_a1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(0) I3=$iopadmap$params(0) O=temp_a1(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(13) I3=$iopadmap$params(13) O=temp_a1(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(12) I3=$iopadmap$params(12) O=temp_a1(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(11) I3=$iopadmap$params(11) O=temp_a1(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(10) I3=$iopadmap$params(10) O=temp_a1(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(9) I3=$iopadmap$params(9) O=temp_a1(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(8) I3=$iopadmap$params(8) O=temp_a1(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(7) I3=$iopadmap$params(7) O=temp_a1(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a1_LUT4_O_I1 I2=temp_a1(6) I3=$iopadmap$params(6) O=temp_a1(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=obf_state(3) I1=obf_state(1) I2=obf_state(2) I3=obf_state(0) O=temp_a1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(15) I3=$iopadmap$params(15) O=temp_a2(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(14) I3=$iopadmap$params(14) O=temp_a2(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(5) I3=$iopadmap$params(5) O=temp_a2(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(4) I3=$iopadmap$params(4) O=temp_a2(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(3) I3=$iopadmap$params(3) O=temp_a2(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(2) I3=$iopadmap$params(2) O=temp_a2(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(1) I3=$iopadmap$params(1) O=temp_a2(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(0) I3=$iopadmap$params(0) O=temp_a2(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(13) I3=$iopadmap$params(13) O=temp_a2(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(12) I3=$iopadmap$params(12) O=temp_a2(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(11) I3=$iopadmap$params(11) O=temp_a2(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(10) I3=$iopadmap$params(10) O=temp_a2(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(9) I3=$iopadmap$params(9) O=temp_a2(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(8) I3=$iopadmap$params(8) O=temp_a2(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(7) I3=$iopadmap$params(7) O=temp_a2(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_a2_LUT4_O_I1 I2=temp_a2(6) I3=$iopadmap$params(6) O=temp_a2(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=obf_state(3) I1=obf_state(0) I2=obf_state(2) I3=obf_state(1) O=temp_a2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(15) I3=$iopadmap$params(15) O=temp_b0(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(14) I3=$iopadmap$params(14) O=temp_b0(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(5) I3=$iopadmap$params(5) O=temp_b0(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(4) I3=$iopadmap$params(4) O=temp_b0(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(3) I3=$iopadmap$params(3) O=temp_b0(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(2) I3=$iopadmap$params(2) O=temp_b0(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(1) I3=$iopadmap$params(1) O=temp_b0(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(0) I3=$iopadmap$params(0) O=temp_b0(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(13) I3=$iopadmap$params(13) O=temp_b0(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(12) I3=$iopadmap$params(12) O=temp_b0(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(11) I3=$iopadmap$params(11) O=temp_b0(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(10) I3=$iopadmap$params(10) O=temp_b0(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(9) I3=$iopadmap$params(9) O=temp_b0(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(8) I3=$iopadmap$params(8) O=temp_b0(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(7) I3=$iopadmap$params(7) O=temp_b0(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b0_LUT4_O_I1 I2=temp_b0(6) I3=$iopadmap$params(6) O=temp_b0(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=obf_state(3) I1=obf_state(2) I2=obf_state(0) I3=obf_state(1) O=temp_b0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(15) I3=$iopadmap$params(15) O=temp_b1(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(14) I3=$iopadmap$params(14) O=temp_b1(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(5) I3=$iopadmap$params(5) O=temp_b1(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(4) I3=$iopadmap$params(4) O=temp_b1(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(3) I3=$iopadmap$params(3) O=temp_b1(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(2) I3=$iopadmap$params(2) O=temp_b1(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(1) I3=$iopadmap$params(1) O=temp_b1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(0) I3=$iopadmap$params(0) O=temp_b1(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(13) I3=$iopadmap$params(13) O=temp_b1(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(12) I3=$iopadmap$params(12) O=temp_b1(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(11) I3=$iopadmap$params(11) O=temp_b1(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(10) I3=$iopadmap$params(10) O=temp_b1(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(9) I3=$iopadmap$params(9) O=temp_b1(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(8) I3=$iopadmap$params(8) O=temp_b1(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(7) I3=$iopadmap$params(7) O=temp_b1(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b1_LUT4_O_I1 I2=temp_b1(6) I3=$iopadmap$params(6) O=temp_b1(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=obf_state(3) I1=obf_state(1) I2=obf_state(0) I3=obf_state(2) O=temp_b1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(15) I3=$iopadmap$params(15) O=temp_b2(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(14) I3=$iopadmap$params(14) O=temp_b2(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(5) I3=$iopadmap$params(5) O=temp_b2(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(4) I3=$iopadmap$params(4) O=temp_b2(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(3) I3=$iopadmap$params(3) O=temp_b2(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(2) I3=$iopadmap$params(2) O=temp_b2(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(1) I3=$iopadmap$params(1) O=temp_b2(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(0) I3=$iopadmap$params(0) O=temp_b2(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(13) I3=$iopadmap$params(13) O=temp_b2(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(12) I3=$iopadmap$params(12) O=temp_b2(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(11) I3=$iopadmap$params(11) O=temp_b2(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(10) I3=$iopadmap$params(10) O=temp_b2(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(9) I3=$iopadmap$params(9) O=temp_b2(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(8) I3=$iopadmap$params(8) O=temp_b2(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(7) I3=$iopadmap$params(7) O=temp_b2(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_b2_LUT4_O_I1 I2=temp_b2(6) I3=$iopadmap$params(6) O=temp_b2(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=obf_state(3) I1=obf_state(1) I2=obf_state(0) I3=obf_state(2) O=temp_b2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_dout_LUT4_O_I1 I2=temp_dout(7) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=temp_yk(0) I1=temp_dout_LUT4_O_1_I1 I2=temp_dout(6) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(25) I1=$iopadmap$dout(6) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_dout_LUT4_O_2_I1 I2=temp_dout(5) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(24) I1=$iopadmap$dout(5) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_dout_LUT4_O_3_I1 I2=temp_dout(4) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(23) I1=$iopadmap$dout(4) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_dout_LUT4_O_4_I1 I2=temp_dout(3) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(22) I1=$iopadmap$dout(3) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_dout_LUT4_O_5_I1 I2=temp_dout(2) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(21) I1=$iopadmap$dout(2) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_dout_LUT4_O_6_I1 I2=temp_dout(1) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(20) I1=$iopadmap$dout(1) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_dout_LUT4_O_7_I1 I2=temp_dout(0) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(19) I1=$iopadmap$dout(0) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=yk(26) I1=$iopadmap$dout(7) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_dout_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ready I3=temp_uk_LUT4_O_I1 O=temp_ready
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk1(7) I3=uk(7) O=temp_uk1(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk1(6) I3=uk(6) O=temp_uk1(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk1(5) I3=uk(5) O=temp_uk1(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk1(4) I3=uk(4) O=temp_uk1(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk1(3) I3=uk(3) O=temp_uk1(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk1(2) I3=uk(2) O=temp_uk1(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk1(1) I3=uk(1) O=temp_uk1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk1(0) I3=uk(0) O=temp_uk1(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk2(7) I3=uk1(7) O=temp_uk2(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk2(6) I3=uk1(6) O=temp_uk2(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk2(5) I3=uk1(5) O=temp_uk2(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk2(4) I3=uk1(4) O=temp_uk2(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk2(3) I3=uk1(3) O=temp_uk2(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk2(2) I3=uk1(2) O=temp_uk2(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk2(1) I3=uk1(1) O=temp_uk2(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_uk2(0) I3=uk1(0) O=temp_uk2(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_uk_LUT4_O_I1 I2=temp_uk(7) I3=temp_uk_LUT4_O_I3 O=temp_uk(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_uk_LUT4_O_I1 I2=temp_uk(6) I3=temp_uk_LUT4_O_1_I3 O=temp_uk(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=$iopadmap$start I2=uk(6) I3=$iopadmap$din(6) O=temp_uk_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_uk_LUT4_O_I1 I2=temp_uk(5) I3=temp_uk_LUT4_O_2_I3 O=temp_uk(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=$iopadmap$start I2=uk(5) I3=$iopadmap$din(5) O=temp_uk_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_uk_LUT4_O_I1 I2=temp_uk(4) I3=temp_uk_LUT4_O_3_I3 O=temp_uk(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=$iopadmap$start I2=uk(4) I3=$iopadmap$din(4) O=temp_uk_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_uk_LUT4_O_I1 I2=temp_uk(3) I3=temp_uk_LUT4_O_4_I3 O=temp_uk(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=$iopadmap$start I2=uk(3) I3=$iopadmap$din(3) O=temp_uk_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_uk_LUT4_O_I1 I2=temp_uk(2) I3=temp_uk_LUT4_O_5_I3 O=temp_uk(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=$iopadmap$start I2=uk(2) I3=$iopadmap$din(2) O=temp_uk_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_uk_LUT4_O_I1 I2=temp_uk(1) I3=temp_uk_LUT4_O_6_I3 O=temp_uk(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=$iopadmap$start I2=uk(1) I3=$iopadmap$din(1) O=temp_uk_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_uk_LUT4_O_I1 I2=temp_uk(0) I3=temp_uk_LUT4_O_7_I3 O=temp_uk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=$iopadmap$start I2=uk(0) I3=$iopadmap$din(0) O=temp_uk_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=obf_state(3) I1=obf_state(0) I2=obf_state(1) I3=obf_state(2) O=temp_uk_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=temp_yk(0) I1=$iopadmap$start I2=uk(7) I3=$iopadmap$din(7) O=temp_uk_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_utmp(12) I1=temp_utmp_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2 I3=temp_utmp_LUT4_O_I3 O=temp_utmp(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110010101010
+.subckt LUT4 I0=temp_utmp(22) I1=temp_utmp_LUT4_O_1_I1 I2=temp_utmp_LUT4_O_1_I2 I3=temp_utmp_LUT4_O_I3 O=temp_utmp(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110010101010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(13) I3=temp_utmp_LUT4_O_10_I3 O=temp_utmp(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_10_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I0 O=temp_utmp_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_I2_LUT4_O_I3 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2 O=temp_utmp_LUT4_O_10_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(11) I3=temp_utmp_LUT4_O_11_I3 O=temp_utmp(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_utmp_LUT4_O_12_I3_LUT4_O_I3 I1=temp_utmp_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_11_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_11_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000100001110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_12_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_12_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_11_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_I1_LUT4_O_I3 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0 O=temp_utmp_LUT4_O_11_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(10) I3=temp_utmp_LUT4_O_12_I3 O=temp_utmp(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_12_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_12_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_12_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_utmp_LUT4_O_12_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_12_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_12_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(9) I3=temp_utmp_LUT4_O_13_I3 O=temp_utmp(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(0) I3=uk1(7) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=b1(3) I3=uk1(4) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b1(2) I2=uk1(4) I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(3) I3=b1(4) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(0) I2=uk1(7) I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(2) I2=uk1(6) I3=b1(1) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(1) I3=b1(2) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=b2(5) I2=uk2(0) I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(0) I3=b1(1) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=uk1(5) I1=b1(1) I2=uk1(6) I3=b1(0) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b1(2) I3=uk1(4) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(4) I2=uk1(3) I3=b1(3) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=b1(1) I2=uk1(4) I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(2) I3=b1(3) O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111010101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I3 I2=temp_utmp_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(8) I3=temp_utmp_LUT4_O_14_I3 O=temp_utmp(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_utmp_LUT4_O_15_I3_LUT4_O_I3 I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_14_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_14_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(7) I3=temp_utmp_LUT4_O_15_I3 O=temp_utmp(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=uk1(5) I3=b1(0) O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=uk1(5) I1=b1(0) I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=b1(1) I3=uk1(4) O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(3) I2=uk1(3) I3=b1(2) O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(6) I3=temp_utmp_LUT4_O_16_I3 O=temp_utmp(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=uk1(4) O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_13_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I3 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1 I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I0 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_16_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(5) I3=temp_utmp_LUT4_O_17_I3 O=temp_utmp(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I0 I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0 I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I3 I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=uk1(0) I1=uk1(1) I2=b1(3) I3=b1(4) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=uk1(0) I1=b1(5) I2=uk1(1) I3=b1(4) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000001011
+.subckt LUT4 I0=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=uk2(3) I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=b2(0) I1=uk2(5) I2=b2(1) I3=uk2(4) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=uk2(3) I3=b2(2) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=uk2(3) I2=b2(1) I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(2) I1=b2(3) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=b2(0) I3=uk2(4) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=b2(5) I3=uk2(0) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(0) I3=b0(1) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=b0(0) I3=uk(5) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b0(3) I3=uk(2) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(5) I2=uk(1) I3=b0(4) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=b0(2) I2=uk(2) I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(3) I3=b0(4) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=uk2(0) I3=b2(4) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=uk1(4) I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=uk1(4) I1=b1(0) I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(0) I3=b1(1) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b1(0) I2=uk1(4) I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=temp_utmp_LUT4_O_15_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(1) I3=b1(2) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=uk1(2) I1=b1(2) I2=uk1(3) I3=b1(1) O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_utmp(4) I1=temp_utmp_LUT4_O_18_I1 I2=temp_utmp_LUT4_O_18_I2 I3=temp_utmp_LUT4_O_I3 O=temp_utmp(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110010101010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1 I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I0 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0 I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=uk2(3) I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110110000010
+.subckt LUT4 I0=b2(0) I1=uk2(4) I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=uk2(3) I2=b2(0) I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(1) I1=b2(2) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=uk2(3) I3=b2(1) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(2) I1=uk2(2) I2=b2(3) I3=uk2(1) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk2(0) I1=b2(4) I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=uk(3) I3=b0(0) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=uk(3) I1=b0(1) I2=uk(4) I3=b0(0) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=b0(2) I3=uk(2) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(4) I2=uk(1) I3=b0(3) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=b0(1) I2=uk(2) I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(2) I3=b0(3) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=uk2(0) I3=b2(3) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111010101011
+.subckt LUT4 I0=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=b1(3) I2=uk1(0) I3=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_I2 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=uk1(0) I1=b1(4) I2=uk1(1) I3=b1(3) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=uk1(2) I3=b1(0) O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_18_I2 I3=temp_utmp_LUT4_O_18_I1 O=temp_utmp_LUT4_O_17_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(3) I3=temp_utmp_LUT4_O_19_I3 O=temp_utmp(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I0 I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=b2(0) I1=uk2(3) I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=b2(0) I1=b2(1) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=b2(1) I1=uk2(2) I2=b2(2) I3=uk2(1) O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=b2(2) I2=uk2(0) I3=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=uk2(0) I1=b2(3) I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=uk(3) I1=b0(0) I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=b0(0) I2=uk(2) I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(1) I3=b0(2) O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=b0(1) I3=uk(2) O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(3) I2=uk(1) I3=b0(2) O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=uk(2) I3=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=uk1(2) I2=b1(0) I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_22_I2 I2=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=b1(2) O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_I2 I2=b1(3) I3=uk1(0) O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=uk1(2) I1=b1(1) I2=uk1(3) I3=b1(0) O=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_20_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_20_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_2_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_2_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_2_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I0 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=uk2(7) I2=b2(12) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=uk2(7) I3=b2(13) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=b0(15) I3=uk(5) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=uk(6) I1=b0(14) I2=uk(7) I3=b0(13) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(12) I3=b0(13) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=uk2(5) I3=b2(15) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=uk2(5) I2=b2(15) I3=uk2(7) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=uk2(6) I3=b2(14) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(13) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=uk2(6) I2=b2(13) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=b2(14) I1=uk2(5) I2=b2(15) I3=uk2(4) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b2(15) I3=uk2(3) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b0(15) I3=uk(4) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b0(14) I3=uk(5) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=uk(6) I1=b0(13) I2=uk(7) I3=b0(12) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(11) I3=b0(12) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b0(13) I3=uk(5) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=b0(13) I2=uk(5) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=uk(3) I1=b0(15) I2=uk(4) I3=b0(14) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=uk(6) I1=b0(12) I2=uk(7) I3=b0(11) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(10) I3=b0(11) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=uk(5) I3=b0(12) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=uk(2) I3=b0(15) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=uk(1) I1=b0(15) I2=uk(2) I3=b0(14) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=b0(11) I3=uk(5) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=uk(0) I3=b0(15) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b0(13) I3=uk(2) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=uk(2) I2=b0(15) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b0(14) I3=uk(1) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=uk(5) I1=b0(12) I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b0(14) I3=uk(3) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=uk1(4) I3=b1(15) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=uk1(4) I2=b1(15) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=uk1(7) I1=b1(12) I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(14) I3=uk1(3) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=uk1(7) I3=b1(12) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=b1(12) I2=uk1(5) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(13) I3=uk1(6) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=b1(15) I2=uk1(6) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(14) I3=uk1(5) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=b2(14) I1=uk2(3) I2=b2(15) I3=uk2(2) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=uk2(6) I3=b2(11) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(12) I1=uk2(5) I2=b2(13) I3=uk2(4) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=b2(15) I3=uk2(1) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=uk2(3) I3=b2(13) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b2(15) I2=uk2(3) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=uk2(2) I3=b2(14) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=b2(12) I1=uk2(6) I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=uk2(5) I3=b2(13) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=uk2(4) I3=b2(14) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(9) I3=b0(10) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=uk(6) I1=b0(11) I2=uk(7) I3=b0(10) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=b0(11) I2=uk(5) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=b0(13) I2=uk(4) I3=b0(12) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=b0(12) I2=uk(3) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b0(13) I3=uk(4) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=uk2(7) I3=b2(12) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=b2(12) I3=uk2(6) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=uk2(7) I2=b2(11) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=b2(10) I3=uk2(7) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=uk2(6) I2=b2(10) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(11) I1=uk2(5) I2=b2(12) I3=uk2(4) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=b2(11) I1=b2(12) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=uk1(1) I1=b2(9) I2=uk2(7) I3=b1(15) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=uk2(7) I3=b2(11) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=uk2(6) I2=b2(11) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=uk2(4) I2=b2(12) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(13) I2=uk1(7) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(13) I3=uk1(7) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(5) I1=b1(15) I2=uk1(6) I3=b1(14) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=b0(13) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=uk(6) I3=b0(15) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110001001100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b0(14) I3=uk(7) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=uk2(6) I3=b2(15) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010001000100
+.subckt LUT4 I0=temp_yk(0) I1=b0(15) I2=uk(5) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=uk1(6) I1=b1(15) I2=uk1(7) I3=b1(14) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=uk2(6) I2=uk2(7) I3=b2(14) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011111111111
+.subckt LUT4 I0=temp_yk(0) I1=uk2(7) I2=b2(13) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=uk1(6) I1=uk1(7) I2=b1(14) I3=b1(15) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b2(15) I2=uk2(6) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=uk1(7) I1=b1(15) I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=uk(7) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=b0(13) I1=uk(6) I2=b0(14) I3=b0(15) O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000001111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(21) I3=temp_utmp_LUT4_O_2_I3 O=temp_utmp(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_utmp(2) I1=temp_utmp_LUT4_O_20_I1 I2=temp_utmp_LUT4_O_20_I2 I3=temp_utmp_LUT4_O_I3 O=temp_utmp(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_20_I1 I3=temp_utmp_LUT4_O_20_I2 O=temp_utmp_LUT4_O_19_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_22_I2 I2=temp_utmp_LUT4_O_22_I1 I3=temp_utmp_LUT4_O_21_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_20_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_20_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=uk1(1) I1=b1(0) I2=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=b1(0) I3=uk1(2) O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b1(0) I1=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b1(2) I3=uk1(0) O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(1) I3=uk1(1) O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=b2(0) I3=uk2(1) O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=b2(0) I1=uk2(2) I2=b2(1) I3=uk2(1) O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=b2(1) I2=uk2(0) I3=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=b2(2) I3=uk2(0) O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(2) I1=b0(0) I2=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(0) I3=b0(1) O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=uk(0) I1=b0(2) I2=uk(1) I3=b0(1) O=temp_utmp_LUT4_O_20_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(1) I3=temp_utmp_LUT4_O_21_I3 O=temp_utmp(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_21_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_22_I2 I3=temp_utmp_LUT4_O_22_I1 O=temp_utmp_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=uk1(1) I1=b1(0) I2=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_21_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=b2(0) I1=uk2(1) I2=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b2(1) I3=uk2(0) O=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(1) I2=uk(1) I3=b0(0) O=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(0) I1=b0(0) I2=b2(0) I3=uk2(0) O=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_I2 I3=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(2) I3=uk1(1) O=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=temp_utmp_LUT4_O_19_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(1) I3=uk1(0) O=temp_utmp_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp(0) I1=temp_utmp_LUT4_O_22_I1 I2=temp_utmp_LUT4_O_22_I2 I3=temp_utmp_LUT4_O_I3 O=temp_utmp(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=uk(0) I1=b0(0) I2=b2(0) I3=uk2(0) O=temp_utmp_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(0) I3=uk1(0) O=temp_utmp_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_2_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_2_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_2_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0 O=temp_utmp_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_utmp_LUT4_O_3_I3_LUT4_O_I2 I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I0 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(20) I3=temp_utmp_LUT4_O_3_I3 O=temp_utmp(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_utmp_LUT4_O_3_I3_LUT4_O_I0 I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=temp_utmp_LUT4_O_4_I3_LUT4_O_I2 I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I3 I2=temp_utmp_LUT4_O_4_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_4_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_utmp_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(10) I3=uk1(7) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(15) I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(13) I3=uk1(4) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b1(12) I2=uk1(4) I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=b1(13) I2=uk1(2) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(10) I2=uk1(7) I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(12) I2=uk1(6) I3=b1(11) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(11) I3=b1(12) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=b2(10) I1=uk2(7) I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b2(15) I3=uk2(0) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(6) I1=b0(9) I2=uk(7) I3=b0(8) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b0(9) I2=uk(5) I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=b0(11) I2=uk(4) I3=b0(10) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(10) I3=b0(11) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=b2(14) I2=uk2(0) I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(7) I3=b0(8) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=uk2(6) I3=b2(10) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(15) I1=uk2(1) I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=uk2(3) I2=b2(12) I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=uk2(1) I2=b2(13) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=uk1(3) I1=b1(15) I2=uk1(4) I3=b1(14) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(11) I3=uk1(7) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=uk1(2) I3=b1(15) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(11) I2=uk1(7) I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(13) I2=uk1(6) I3=b1(12) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=uk(6) I1=b0(10) I2=uk(7) I3=b0(9) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b0(10) I2=uk(5) I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=b0(12) I2=uk(4) I3=b0(11) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(11) I3=b0(12) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=b2(15) I2=uk2(0) I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(8) I3=b0(9) O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(19) I3=temp_utmp_LUT4_O_4_I3 O=temp_utmp(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_utmp_LUT4_O_5_I3_LUT4_O_I3 I1=temp_utmp_LUT4_O_4_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_4_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_4_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000100001110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(18) I3=temp_utmp_LUT4_O_5_I3 O=temp_utmp(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(9) I3=uk1(7) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=b1(12) I3=uk1(4) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(14) I2=uk1(3) I3=b1(13) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b1(11) I2=uk1(4) I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(12) I3=b1(13) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(9) I2=uk1(7) I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(11) I2=uk1(6) I3=b1(10) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(10) I3=b1(11) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b2(14) I3=uk2(0) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(6) I1=b0(8) I2=uk(7) I3=b0(7) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b0(8) I2=uk(5) I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=b0(10) I2=uk(4) I3=b0(9) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(9) I3=b0(10) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=b2(13) I2=uk2(0) I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(6) I3=b0(7) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(9) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(10) I1=uk2(5) I2=b2(11) I3=uk2(4) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=uk2(3) I3=b2(12) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(13) I1=uk2(2) I2=b2(14) I3=uk2(1) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=uk2(3) I2=b2(11) I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(12) I1=b2(13) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=uk1(1) I1=b1(15) I2=b2(9) I3=uk2(7) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=uk2(6) I2=b2(9) I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(10) I1=b2(11) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=b2(8) I3=uk2(7) O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2 I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I0 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(17) I3=temp_utmp_LUT4_O_6_I3 O=temp_utmp(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I0 I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_7_I3_LUT4_O_I3 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_utmp_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(7) I3=uk1(7) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=b1(10) I3=uk1(4) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(12) I2=uk1(3) I3=b1(11) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=b1(9) I2=uk1(4) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=b1(11) I2=uk1(3) I3=b1(10) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(10) I3=b1(11) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(7) I2=uk1(7) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(9) I2=uk1(6) I3=b1(8) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(8) I3=b1(9) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b2(12) I3=uk2(0) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(6) I1=b0(6) I2=uk(7) I3=b0(5) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b0(6) I2=uk(5) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=b0(8) I2=uk(4) I3=b0(7) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(7) I3=b0(8) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=b2(11) I2=uk2(0) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(6) I1=b0(5) I2=uk(7) I3=b0(4) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(4) I3=b0(5) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(7) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(8) I1=uk2(5) I2=b2(9) I3=uk2(4) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=uk2(3) I3=b2(10) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(11) I1=uk2(2) I2=b2(12) I3=uk2(1) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=uk2(3) I2=b2(9) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(10) I1=b2(11) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(6) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(7) I1=uk2(5) I2=b2(8) I3=uk2(4) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=uk2(3) I3=b2(9) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(10) I1=uk2(2) I2=b2(11) I3=uk2(1) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=uk2(3) I2=b2(8) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(9) I1=uk2(2) I2=b2(10) I3=uk2(1) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=b2(9) I1=b2(10) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=b2(7) I1=uk2(7) I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(14) I3=uk1(0) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(13) I3=uk1(1) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=uk2(6) I2=b2(7) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(8) I1=b2(9) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=b2(6) I3=uk2(7) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=b2(6) I1=uk2(7) I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(13) I3=uk1(0) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(12) I3=uk1(1) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=uk2(6) I2=b2(6) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(7) I1=b2(8) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=b2(5) I3=uk2(7) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=b2(5) I1=uk2(7) I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(12) I3=uk1(0) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(11) I3=uk1(1) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=uk2(6) I2=b2(5) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(6) I1=uk2(5) I2=b2(7) I3=uk2(4) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=b2(6) I1=b2(7) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=b2(4) I3=uk2(7) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(11) I3=uk1(0) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(10) I3=uk1(1) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b0(9) I3=uk(5) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b0(12) I3=uk(2) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(14) I2=uk(1) I3=b0(13) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b0(11) I2=uk(2) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(12) I3=b0(13) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b0(8) I3=uk(5) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b0(11) I3=uk(2) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(13) I2=uk(1) I3=b0(12) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b0(10) I2=uk(2) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(11) I3=b0(12) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b0(10) I3=uk(5) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(15) I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b0(12) I2=uk(2) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=b0(13) I2=uk(0) I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(8) I3=uk1(7) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=b1(11) I3=uk1(4) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(13) I2=uk1(3) I3=b1(12) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b1(10) I2=uk1(4) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(11) I3=b1(12) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(8) I2=uk1(7) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(10) I2=uk1(6) I3=b1(9) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(9) I3=b1(10) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b2(13) I3=uk2(0) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(6) I1=b0(7) I2=uk(7) I3=b0(6) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b0(7) I2=uk(5) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=b0(9) I2=uk(4) I3=b0(8) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(8) I3=b0(9) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=b2(12) I2=uk2(0) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(5) I3=b0(6) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(8) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(9) I1=uk2(5) I2=b2(10) I3=uk2(4) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=uk2(3) I3=b2(11) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(12) I1=uk2(2) I2=b2(13) I3=uk2(1) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=uk2(3) I2=b2(10) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(11) I1=b2(12) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=b2(8) I1=uk2(7) I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(15) I3=uk1(0) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(14) I3=uk1(1) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=uk2(6) I2=b2(8) I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(9) I1=b2(10) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=b2(7) I3=uk2(7) O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(16) I3=temp_utmp_LUT4_O_7_I3 O=temp_utmp(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_utmp_LUT4_O_8_I3_LUT4_O_I3 I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_7_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_7_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(15) I3=temp_utmp_LUT4_O_8_I3 O=temp_utmp(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(6) I3=uk1(7) O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=b1(9) I3=uk1(4) O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b1(8) I2=uk1(4) I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(9) I3=b1(10) O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(6) I2=uk1(7) I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(8) I2=uk1(6) I3=b1(7) O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(7) I3=b1(8) O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_8_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3 I3=temp_utmp_LUT4_O_I2_LUT4_I0_O O=temp_utmp_LUT4_O_8_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I3 I2=temp_utmp(14) I3=temp_utmp_LUT4_O_9_I3 O=temp_utmp(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_utmp_LUT4_O_9_I3_LUT4_O_I0 I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000101111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_utmp_LUT4_O_10_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(5) I3=uk1(7) O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=b1(8) I3=uk1(4) O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(10) I2=uk1(3) I3=b1(9) O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b1(7) I2=uk1(4) I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(8) I3=b1(9) O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(5) I2=uk1(7) I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(7) I2=uk1(6) I3=b1(6) O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(6) I3=b1(7) O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_8_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0 I1=temp_utmp_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(1) I3=uk1(7) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=b1(4) I3=uk1(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(6) I2=uk1(3) I3=b1(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=b1(3) I2=uk1(4) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=b1(5) I2=uk1(3) I3=b1(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(4) I3=b1(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(1) I2=uk1(7) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(3) I2=uk1(6) I3=b1(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(2) I3=b1(3) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(1) I1=uk2(5) I2=b2(2) I3=uk2(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=uk2(3) I3=b2(3) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(4) I1=uk2(2) I2=b2(5) I3=uk2(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=uk2(3) I2=b2(2) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(3) I1=uk2(2) I2=b2(4) I3=uk2(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=b2(3) I1=b2(4) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(2) I1=uk2(5) I2=b2(3) I3=uk2(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=uk2(3) I3=b2(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(5) I1=uk2(2) I2=b2(6) I3=uk2(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=uk2(3) I2=b2(3) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(4) I1=b2(5) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b0(0) I3=uk(6) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b2(6) I3=uk2(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=b0(0) I2=uk(5) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=b0(2) I2=uk(4) I3=b0(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(1) I3=b0(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=b2(1) I1=uk2(7) I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(8) I3=uk1(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(7) I3=uk1(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=uk2(6) I2=b2(1) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(2) I1=b2(3) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=b2(0) I3=uk2(7) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=uk1(0) I1=uk1(1) I2=b1(4) I3=b1(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=uk1(0) I1=b1(6) I2=uk1(1) I3=b1(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=b2(0) I1=b2(1) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=uk1(0) I1=uk1(1) I2=b1(5) I3=b1(6) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=b2(0) I1=uk2(7) I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(7) I3=uk1(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(6) I3=uk1(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=uk2(6) I2=b2(0) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(1) I1=b2(2) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(5) I1=uk2(5) I2=b2(6) I3=uk2(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=uk2(3) I3=b2(7) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(8) I1=uk2(2) I2=b2(9) I3=uk2(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=uk2(3) I2=b2(6) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(7) I1=b2(8) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b2(10) I3=uk2(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(6) I1=b0(4) I2=uk(7) I3=b0(3) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=b0(4) I2=uk(5) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(5) I3=b0(6) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=b2(9) I2=uk2(0) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(2) I3=b0(3) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=b0(5) I3=uk(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(3) I1=b0(7) I2=uk(4) I3=b0(6) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b0(8) I3=uk(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(10) I2=uk(1) I3=b0(9) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b0(7) I2=uk(2) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(8) I3=b0(9) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b2(9) I3=uk2(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(6) I1=b0(3) I2=uk(7) I3=b0(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=b0(3) I2=uk(5) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(4) I3=b0(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=b2(8) I2=uk2(0) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(1) I3=b0(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=b0(4) I3=uk(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(3) I1=b0(6) I2=uk(4) I3=b0(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b0(7) I3=uk(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(9) I2=uk(1) I3=b0(8) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b0(6) I2=uk(2) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(7) I3=b0(8) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=b0(2) I3=uk(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b0(5) I3=uk(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(7) I2=uk(1) I3=b0(6) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b0(4) I2=uk(2) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(5) I3=b0(6) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I2=b0(1) I3=uk(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b0(4) I3=uk(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(6) I2=uk(1) I3=b0(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b0(3) I2=uk(2) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(4) I3=b0(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b0(3) I3=uk(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(3) I1=b0(5) I2=uk(4) I3=b0(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=b0(6) I3=uk(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(8) I2=uk(1) I3=b0(7) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b0(5) I2=uk(2) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(6) I3=b0(7) O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_12_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_12_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0 I1=temp_utmp_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_12_I3_LUT4_O_I3 I3=temp_utmp_LUT4_O_11_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b1(2) I3=uk1(7) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=b1(5) I3=uk1(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(7) I2=uk1(3) I3=b1(6) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b1(4) I2=uk1(4) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(5) I3=b1(6) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=b1(2) I2=uk1(7) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(4) I2=uk1(6) I3=b1(3) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(3) I3=b1(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010001
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=b0(1) I2=uk(5) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=b0(3) I2=uk(4) I3=b0(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(2) I3=b0(3) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=b2(7) I3=uk2(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(6) I1=b0(1) I2=uk(7) I3=b0(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(3) I1=uk2(5) I2=b2(4) I3=uk2(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=uk2(3) I3=b2(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(6) I1=uk2(2) I2=b2(7) I3=uk2(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=uk2(3) I2=b2(4) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(5) I1=b2(6) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=b2(2) I1=uk2(7) I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(9) I3=uk1(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(8) I3=uk1(1) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=uk2(6) I2=b2(2) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(3) I1=b2(4) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=b2(1) I3=uk2(7) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=b2(4) I1=uk2(7) I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=uk2(6) I2=b2(4) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(5) I1=b2(6) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=b2(3) I3=uk2(7) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=uk2(6) I3=b2(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=uk2(3) I3=b2(8) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=uk2(3) I2=b2(7) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(8) I1=b2(9) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=b2(11) I3=uk2(0) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=b0(5) I2=uk(5) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(6) I3=b0(7) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=b2(10) I2=uk2(0) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(6) I1=uk(7) I2=b0(3) I3=b0(4) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b0(6) I3=uk(5) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b0(9) I3=uk(2) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(11) I2=uk(1) I3=b0(10) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b0(8) I2=uk(2) I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(9) I3=b0(10) O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2 I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_I2_I3 I3=temp_utmp_LUT4_O_9_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_I0_O I1=temp_utmp_LUT4_O_9_I3_LUT4_O_I3 I2=temp_utmp_LUT4_O_8_I3_LUT4_O_I1 I3=temp_utmp_LUT4_O_7_I3_LUT4_O_I2 O=temp_utmp_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_I2_I3 O=temp_utmp_LUT4_O_9_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_utmp_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=b1(4) I2=uk1(7) I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(6) I2=uk1(6) I3=b1(5) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(5) I3=b1(6) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=b1(4) I3=uk1(7) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b1(7) I3=uk1(4) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(9) I2=uk1(3) I3=b1(8) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b1(6) I2=uk1(4) I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(7) I3=b1(8) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=b0(7) I3=uk(5) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=b0(10) I3=uk(2) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(0) I1=b0(12) I2=uk(1) I3=b0(11) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=b0(9) I2=uk(2) I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(0) I1=uk(1) I2=b0(10) I3=b0(11) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=b1(3) I3=uk1(7) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=b1(6) I3=uk1(4) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk1(2) I1=b1(8) I2=uk1(3) I3=b1(7) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=b1(5) I2=uk1(4) I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(2) I1=uk1(3) I2=b1(6) I3=b1(7) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=b1(3) I2=uk1(7) I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk1(5) I1=b1(5) I2=uk1(6) I3=b1(4) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk1(5) I1=uk1(6) I2=b1(4) I3=b1(5) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=b2(3) I1=uk2(7) I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(10) I3=uk1(0) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=b1(9) I3=uk1(1) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=uk2(6) I2=b2(3) I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(4) I1=b2(5) I2=uk2(4) I3=uk2(5) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=b2(2) I3=uk2(7) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=uk2(6) I3=b2(3) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(4) I1=uk2(5) I2=b2(5) I3=uk2(4) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=uk2(3) I3=b2(6) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=b2(7) I1=uk2(2) I2=b2(8) I3=uk2(1) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=uk2(3) I2=b2(5) I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=b2(6) I1=b2(7) I2=uk2(1) I3=uk2(2) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=b2(8) I3=uk2(0) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=uk(6) I1=b0(2) I2=uk(7) I3=b0(1) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=b0(2) I2=uk(5) I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=uk(3) I1=b0(4) I2=uk(4) I3=b0(3) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=uk(3) I1=uk(4) I2=b0(3) I3=b0(4) O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=b2(7) I2=uk2(0) I3=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=b0(1) I2=uk(7) I3=temp_utmp_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_utmp_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_utmp_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=obf_state(1) I1=obf_state(2) I2=obf_state(0) I3=obf_state(3) O=temp_utmp_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=temp_wait_counter_LUT4_O_I0 I1=obf_state(0) I2=temp_wait_counter(3) I3=temp_wait_counter_LUT4_O_I3 O=temp_wait_counter(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=temp_wait_counter_LUT4_O_1_I0 I1=obf_state(0) I2=temp_wait_counter(2) I3=temp_wait_counter_LUT4_O_I3 O=temp_wait_counter(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101111110000
+.subckt LUT4 I0=temp_yk(0) I1=wait_counter(2) I2=wait_counter(0) I3=wait_counter(1) O=temp_wait_counter_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_2_I1 I2=temp_wait_counter(1) I3=temp_wait_counter_LUT4_O_I3 O=temp_wait_counter(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I3_O I2=wait_counter(0) I3=wait_counter(1) O=temp_wait_counter_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=wait_counter(0) I1=obf_state(0) I2=temp_wait_counter(0) I3=temp_wait_counter_LUT4_O_I3 O=temp_wait_counter(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=wait_counter(1) I1=wait_counter(0) I2=wait_counter(2) I3=wait_counter(3) O=temp_wait_counter_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000111111110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_wait_counter_LUT4_O_I3 I3=obf_state(0) O=temp_wait_counter_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=obf_state(0) I3=temp_wait_counter_LUT4_O_I3 O=temp_wait_counter_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=obf_state(3) I2=obf_state(1) I3=obf_state(2) O=temp_wait_counter_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_I1 I2=temp_yk1(15) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_1_I1 I2=temp_yk1(14) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_10_I1 I2=temp_yk1(5) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(16) I1=yk1(5) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_11_I1 I2=temp_yk1(4) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(15) I1=yk1(4) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_12_I1 I2=temp_yk1(3) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(14) I1=yk1(3) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_13_I1 I2=temp_yk1(2) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(13) I1=yk1(2) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_14_I1 I2=temp_yk1(1) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(12) I1=yk1(1) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_15_I1 I2=temp_yk1(0) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(11) I1=yk1(0) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=yk(25) I1=yk1(14) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_2_I1 I2=temp_yk1(13) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(24) I1=yk1(13) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_3_I1 I2=temp_yk1(12) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(23) I1=yk1(12) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_4_I1 I2=temp_yk1(11) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(22) I1=yk1(11) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_5_I1 I2=temp_yk1(10) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(21) I1=yk1(10) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_6_I1 I2=temp_yk1(9) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(20) I1=yk1(9) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_7_I1 I2=temp_yk1(8) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(19) I1=yk1(8) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_8_I1 I2=temp_yk1(7) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(18) I1=yk1(7) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk1_LUT4_O_9_I1 I2=temp_yk1(6) I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=yk(17) I1=yk1(6) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=yk(26) I1=yk1(15) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(15) I3=yk1(15) O=temp_yk2(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(14) I3=yk1(14) O=temp_yk2(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(5) I3=yk1(5) O=temp_yk2(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(4) I3=yk1(4) O=temp_yk2(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(3) I3=yk1(3) O=temp_yk2(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(2) I3=yk1(2) O=temp_yk2(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(1) I3=yk1(1) O=temp_yk2(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(0) I3=yk1(0) O=temp_yk2(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(13) I3=yk1(13) O=temp_yk2(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(12) I3=yk1(12) O=temp_yk2(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(11) I3=yk1(11) O=temp_yk2(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(10) I3=yk1(10) O=temp_yk2(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(9) I3=yk1(9) O=temp_yk2(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(8) I3=yk1(8) O=temp_yk2(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(7) I3=yk1(7) O=temp_yk2(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk2_LUT4_O_I1 I2=temp_yk2(6) I3=yk1(6) O=temp_yk2(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_yk1_LUT4_O_I1_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I3_O O=temp_yk2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(26) I1=ysum(26) I2=temp_yk_LUT4_O_I2 I3=temp_wait_counter_LUT4_O_I3_LUT4_I2_O O=temp_yk(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(25) I3=temp_yk_LUT4_O_1_I3 O=temp_yk(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(16) I3=temp_yk_LUT4_O_10_I3 O=temp_yk(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(16) I2=ysum(16) I3=temp_yk_LUT4_O_10_I3_LUT4_O_I3 O=temp_yk_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=utmp(15) I2=ysum(15) I3=temp_yk_LUT4_O_11_I1_LUT4_O_I0 O=temp_yk_LUT4_O_10_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk_LUT4_O_11_I1 I2=temp_yk(15) I3=temp_wait_counter_LUT4_O_I3_LUT4_I2_O O=temp_yk(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=temp_yk_LUT4_O_11_I1_LUT4_O_I0 I1=ysum(15) I2=utmp(15) I3=temp_wait_counter_LUT4_O_I3_LUT4_I2_O O=temp_yk_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=temp_yk(0) I1=utmp(14) I2=ysum(14) I3=temp_yk_LUT4_O_12_I3_LUT4_O_I3 O=temp_yk_LUT4_O_11_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(14) I3=temp_yk_LUT4_O_12_I3 O=temp_yk(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(14) I2=ysum(14) I3=temp_yk_LUT4_O_12_I3_LUT4_O_I3 O=temp_yk_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=utmp(13) I2=ysum(13) I3=temp_yk_LUT4_O_13_I3_LUT4_O_I3 O=temp_yk_LUT4_O_12_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(13) I3=temp_yk_LUT4_O_13_I3 O=temp_yk(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(13) I2=ysum(13) I3=temp_yk_LUT4_O_13_I3_LUT4_O_I3 O=temp_yk_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=utmp(12) I2=ysum(12) I3=temp_yk_LUT4_O_14_I3_LUT4_O_I3 O=temp_yk_LUT4_O_13_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(12) I3=temp_yk_LUT4_O_14_I3 O=temp_yk(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(12) I2=ysum(12) I3=temp_yk_LUT4_O_14_I3_LUT4_O_I3 O=temp_yk_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=utmp(11) I2=ysum(11) I3=temp_yk_LUT4_O_15_I3_LUT4_O_I3 O=temp_yk_LUT4_O_14_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(11) I3=temp_yk_LUT4_O_15_I3 O=temp_yk(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(11) I2=ysum(11) I3=temp_yk_LUT4_O_15_I3_LUT4_O_I3 O=temp_yk_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=ysum(10) I1=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2 I3=utmp(10) O=temp_yk_LUT4_O_15_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=utmp(9) I3=ysum(9) O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=ysum(8) I2=utmp(8) I3=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=utmp(7) I3=ysum(7) O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=ysum(6) I2=utmp(6) I3=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=temp_yk(0) I1=utmp(5) I2=ysum(5) I3=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=temp_yk(0) I1=utmp(4) I2=ysum(4) I3=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=utmp(3) I3=ysum(3) O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=ysum(2) I2=utmp(2) I3=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=ysum(1) I1=utmp(1) I2=ysum(0) I3=utmp(0) O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=utmp(3) I3=ysum(3) O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=utmp(7) I3=ysum(7) O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=utmp(9) I3=ysum(9) O=temp_yk_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk_LUT4_O_I2_LUT4_O_I0 I1=utmp(22) I2=ysum(24) I3=ysum(25) O=temp_yk_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010010011011011
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(24) I3=temp_yk_LUT4_O_2_I3 O=temp_yk(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=ysum(24) I2=utmp(22) I3=temp_yk_LUT4_O_I2_LUT4_O_I0 O=temp_yk_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(23) I3=temp_yk_LUT4_O_3_I3 O=temp_yk(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk_LUT4_O_4_I3_LUT4_O_I3 I1=ysum(22) I2=utmp(22) I3=ysum(23) O=temp_yk_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001100011100111
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(22) I3=temp_yk_LUT4_O_4_I3 O=temp_yk(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(22) I2=ysum(22) I3=temp_yk_LUT4_O_4_I3_LUT4_O_I3 O=temp_yk_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=utmp(21) I2=ysum(21) I3=temp_yk_LUT4_O_5_I3_LUT4_O_I3 O=temp_yk_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(21) I3=temp_yk_LUT4_O_5_I3 O=temp_yk(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(21) I2=ysum(21) I3=temp_yk_LUT4_O_5_I3_LUT4_O_I3 O=temp_yk_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=utmp(20) I2=ysum(20) I3=temp_yk_LUT4_O_6_I3_LUT4_O_I3 O=temp_yk_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(20) I3=temp_yk_LUT4_O_6_I3 O=temp_yk(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(20) I2=ysum(20) I3=temp_yk_LUT4_O_6_I3_LUT4_O_I3 O=temp_yk_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=utmp(19) I2=ysum(19) I3=temp_yk_LUT4_O_7_I3_LUT4_O_I3 O=temp_yk_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(19) I3=temp_yk_LUT4_O_7_I3 O=temp_yk(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(19) I2=ysum(19) I3=temp_yk_LUT4_O_7_I3_LUT4_O_I3 O=temp_yk_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=utmp(18) I2=ysum(18) I3=temp_yk_LUT4_O_8_I3_LUT4_O_I3 O=temp_yk_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_wait_counter_LUT4_O_I3_LUT4_I2_O I2=temp_yk(18) I3=temp_yk_LUT4_O_8_I3 O=temp_yk(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=utmp(18) I2=ysum(18) I3=temp_yk_LUT4_O_8_I3_LUT4_O_I3 O=temp_yk_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=utmp(17) I2=ysum(17) I3=temp_yk_LUT4_O_9_I1_LUT4_O_I0 O=temp_yk_LUT4_O_8_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk_LUT4_O_9_I1 I2=temp_yk(17) I3=temp_wait_counter_LUT4_O_I3_LUT4_I2_O O=temp_yk(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=temp_yk_LUT4_O_9_I1_LUT4_O_I0 I1=ysum(17) I2=utmp(17) I3=temp_wait_counter_LUT4_O_I3_LUT4_I2_O O=temp_yk_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=temp_yk(0) I1=utmp(16) I2=ysum(16) I3=temp_yk_LUT4_O_10_I3_LUT4_O_I3 O=temp_yk_LUT4_O_9_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_yk_LUT4_O_I2_LUT4_O_I0 I1=ysum(24) I2=ysum(25) I3=utmp(22) O=temp_yk_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111001111111
+.subckt LUT4 I0=temp_yk_LUT4_O_4_I3_LUT4_O_I3 I1=ysum(22) I2=ysum(23) I3=utmp(22) O=temp_yk_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010000000
+.subckt LUT4 I0=temp_ysum(9) I1=temp_ysum_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2 I3=temp_ysum_LUT4_O_I3 O=temp_ysum(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110010101010
+.subckt LUT4 I0=temp_ysum(26) I1=temp_ysum_LUT4_O_1_I1 I2=temp_ysum_LUT4_O_1_I2 I3=temp_ysum_LUT4_O_I3 O=temp_ysum(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(17) I3=temp_ysum_LUT4_O_10_I3 O=temp_ysum(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I0 O=temp_ysum_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(16) I3=temp_ysum_LUT4_O_11_I3 O=temp_ysum(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_I0_O O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=yk2(9) I3=a2(8) O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_I0_O I3=temp_ysum_LUT4_O_12_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=temp_ysum(15) I1=temp_ysum_LUT4_O_12_I1 I2=temp_ysum_LUT4_O_12_I2 I3=temp_ysum_LUT4_O_I3 O=temp_ysum(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110010101010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_12_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I1 I3=temp_ysum_LUT4_O_13_I2 O=temp_ysum_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110000010
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2 I1=temp_ysum_LUT4_O_13_I1 I2=temp_ysum_LUT4_O_12_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_12_I2 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=temp_ysum_LUT4_O_12_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_I0_O O=temp_ysum_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=yk1(2) I3=a1(15) O=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum(14) I1=temp_ysum_LUT4_O_13_I1 I2=temp_ysum_LUT4_O_13_I2 I3=temp_ysum_LUT4_O_I3 O=temp_ysum(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=temp_ysum_LUT4_O_14_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_14_I3_LUT4_O_I0 I2=temp_ysum_LUT4_O_14_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_14_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=yk2(7) I3=a2(8) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk2(14) I1=a2(0) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(13) I3=yk2(1) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(12) I3=yk2(2) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=yk2(13) I3=a2(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=a2(4) I2=yk2(9) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=a2(5) I2=yk2(7) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(5) I1=a2(7) I2=yk2(6) I3=a2(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(5) I1=yk2(6) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a2(9) I2=yk2(5) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a2(9) I3=yk2(5) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(3) I1=a2(11) I2=yk2(4) I3=a2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(3) I1=yk2(4) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(8) I1=a2(8) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=a2(5) I3=yk2(11) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(15) I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(12) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=yk2(13) I2=a2(1) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk2(6) I3=a2(8) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=yk2(3) I1=a2(9) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=yk2(0) I1=a2(12) I2=yk2(12) I3=a2(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(1) I1=a2(11) I2=yk2(2) I3=a2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(0) I1=yk2(12) I2=a2(0) I3=a2(12) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=yk2(13) I1=a2(0) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(13) I3=yk2(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(12) I3=yk2(1) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=a2(4) I2=yk2(8) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=a2(5) I2=yk2(6) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(4) I1=a2(7) I2=yk2(5) I3=a2(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(4) I1=yk2(5) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a2(9) I2=yk2(4) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a2(9) I3=yk2(4) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(2) I1=a2(11) I2=yk2(3) I3=a2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(2) I1=yk2(3) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(7) I1=a2(8) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3 I2=a2(14) I3=yk2(1) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=a2(5) I2=yk2(9) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(7) I1=yk2(8) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=a2(14) I2=yk2(10) I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=a2(5) I3=yk2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(12) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(14) I2=yk2(13) I3=a2(2) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(11) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(12) I2=yk2(13) I3=a2(2) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=yk2(6) I1=a2(8) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a2(5) I3=yk2(9) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(7) I1=a2(7) I2=yk2(8) I3=a2(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(11) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(13) I2=yk2(12) I3=a2(2) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(10) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(11) I2=yk2(12) I3=a2(2) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=a2(4) I3=yk2(9) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=a2(5) I3=yk2(8) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(12) I2=yk2(11) I3=a2(2) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(9) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(10) I2=yk2(11) I3=a2(2) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=yk1(0) I3=yk1(1) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=a1(8) I3=yk1(4) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(5) I1=a1(7) I2=yk1(6) I3=a1(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=a1(5) I2=yk1(6) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(7) I1=a1(4) I2=yk1(11) I3=a1(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(7) I1=yk1(11) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=a1(8) I2=yk1(3) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(4) I1=yk1(5) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk1(0) I1=a1(13) I2=yk1(1) I3=a1(12) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(2) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(3) I1=a1(10) I2=yk1(4) I3=a1(9) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=a1(11) I2=yk1(1) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(2) I1=yk1(3) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=yk1(0) I3=a1(12) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(13) I3=a1(12) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(0) I1=a1(15) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=a1(8) I3=yk1(7) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=a1(5) I2=yk1(9) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(10) I1=yk1(14) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=a1(8) I2=yk1(6) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(7) I1=yk1(8) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a1(5) I3=yk1(9) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(10) I1=a1(4) I2=yk1(14) I3=a1(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=a1(1) I3=yk1(13) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(12) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(10) I1=yk1(11) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=yk1(0) I2=yk1(1) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk1(0) I3=a1(15) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=a1(8) I3=yk1(5) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(6) I1=a1(7) I2=yk1(7) I3=a1(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=a1(5) I2=yk1(7) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(8) I1=a1(4) I2=yk1(12) I3=a1(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(8) I1=yk1(12) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=a1(8) I2=yk1(4) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(5) I1=yk1(6) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(3) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(4) I1=a1(10) I2=yk1(5) I3=a1(9) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(2) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(3) I1=yk1(4) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a1(14) I2=yk1(0) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a1(14) I3=yk1(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(1) I1=a1(13) I2=yk1(2) I3=a1(12) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(2) I2=yk1(1) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(1) I1=a1(15) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I2 I1=temp_ysum_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_I0_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk2(8) I3=a2(8) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(12) I3=yk2(3) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(2) I1=a2(13) I2=yk2(15) I3=a2(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=yk2(14) I3=a2(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=yk2(0) I1=a2(14) I2=yk2(10) I3=a2(4) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=a2(5) I2=yk2(8) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(6) I1=a2(7) I2=yk2(7) I3=a2(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(6) I1=yk2(7) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a2(9) I2=yk2(6) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a2(9) I3=yk2(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(4) I1=a2(11) I2=yk2(5) I3=a2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(4) I1=yk2(5) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(9) I1=a2(8) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=a2(9) I2=yk2(7) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=a2(9) I3=yk2(7) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(5) I1=a2(11) I2=yk2(6) I3=a2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(5) I1=yk2(6) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I3 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I3 I1=temp_ysum_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_I0_I3 O=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk1(1) I3=a1(15) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=a1(8) I3=yk1(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(7) I1=a1(7) I2=yk1(8) I3=a1(6) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=a1(5) I2=yk1(8) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(9) I1=a1(4) I2=yk1(13) I3=a1(0) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(9) I1=yk1(13) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=a1(8) I2=yk1(5) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(6) I1=yk1(7) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=a1(11) I3=yk1(4) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(3) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(4) I1=yk1(5) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a1(14) I2=yk1(1) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a1(14) I3=yk1(1) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(2) I1=a1(13) I2=yk1(3) I3=a1(12) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(3) I2=yk1(2) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(2) I1=a1(15) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=a1(14) I2=yk1(2) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(3) I1=a1(13) I2=yk1(4) I3=a1(12) O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(4) I2=yk1(3) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(13) I3=temp_ysum_LUT4_O_14_I3 O=temp_ysum(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_14_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_14_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_14_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_14_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=temp_ysum_LUT4_O_16_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_16_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_15_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_14_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_14_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_14_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1 O=temp_ysum_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_14_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_14_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(12) I3=temp_ysum_LUT4_O_15_I3 O=temp_ysum(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_16_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_16_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_15_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3 I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(11) I3=temp_ysum_LUT4_O_16_I3 O=temp_ysum(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_16_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I1 I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_15_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk2(5) I3=a2(8) O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=a2(9) I2=yk2(3) I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=a2(11) I2=yk2(2) I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I0 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_16_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(10) I3=temp_ysum_LUT4_O_17_I3 O=temp_ysum(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=yk2(4) I3=a2(8) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(5) I1=a2(8) I2=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=a1(8) I3=yk1(3) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(4) I1=a1(7) I2=yk1(5) I3=a1(6) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=a1(5) I2=yk1(5) I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(6) I1=a1(4) I2=yk1(10) I3=a1(0) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(6) I1=yk1(10) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=a1(8) I2=yk1(2) I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(3) I1=yk1(4) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=a1(11) I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=yk1(0) I1=a1(12) I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=a1(11) I2=yk1(0) I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=a1(10) I2=yk1(2) I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=a1(11) I3=yk1(1) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(2) I1=a1(10) I2=yk1(3) I3=a1(9) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=a1(5) I3=yk1(8) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(12) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(10) I1=a1(3) I2=yk1(11) I3=a1(2) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(11) I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(9) I1=yk1(10) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(8) I3=temp_ysum_LUT4_O_18_I3 O=temp_ysum(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_I1_LUT4_O_I0 O=temp_ysum_LUT4_O_18_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(7) I3=temp_ysum_LUT4_O_19_I3 O=temp_ysum(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_19_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_19_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_19_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_19_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=temp_ysum_LUT4_O_19_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=temp_ysum_LUT4_O_19_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_19_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=yk2(9) I1=yk2(7) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=yk2(9) I1=yk2(10) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=yk2(10) I1=a2(13) I2=yk2(11) I3=a2(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=a2(9) I3=yk2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=yk2(14) I3=a2(10) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(11) I3=yk2(13) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(9) I3=yk2(15) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=yk2(8) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=yk2(10) I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk2(14) I1=a2(14) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001111101100
+.subckt LUT4 I0=yk2(13) I1=yk2(11) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=yk2(14) I1=yk2(13) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(12) I3=yk2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(13) I3=yk2(15) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=yk2(14) I1=a2(14) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=yk2(12) I1=a2(14) I2=a2(15) I3=yk2(13) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=yk2(12) I1=yk2(10) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=yk2(13) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=yk2(15) I3=a2(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(13) I3=yk2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=yk2(15) I3=a2(11) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=yk2(14) I1=yk2(15) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=yk2(10) I1=yk2(8) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(15) I3=yk2(9) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(14) I1=a2(11) I2=yk2(15) I3=a2(10) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(12) I1=a2(13) I2=yk2(13) I3=a2(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(11) I1=yk2(12) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=yk2(10) I1=yk2(11) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=yk2(11) I1=a2(13) I2=yk2(12) I3=a2(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(14) I1=a2(10) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=yk2(11) I1=yk2(9) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=yk2(15) I1=a2(11) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=a2(13) I3=yk2(13) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=yk2(12) I1=yk2(13) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=yk2(11) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=yk2(13) I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(15) I3=yk2(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=yk2(10) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=yk2(12) I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I1 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=temp_yk(0) I1=a2(14) I2=yk2(1) I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=yk2(0) I1=a2(15) I2=yk2(11) I3=a2(4) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(15) I3=yk2(11) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=yk2(9) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=yk2(11) I3=a2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(15) I3=yk2(10) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=yk2(15) I1=a2(14) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=yk2(13) I1=a2(14) I2=a2(15) I3=yk2(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=yk1(14) I1=a1(15) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=yk1(13) I3=a1(15) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=yk1(14) I1=a1(13) I2=yk1(15) I3=a1(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111000010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=yk1(12) I3=a1(15) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=yk1(15) I2=a1(11) I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(10) I3=yk1(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=yk1(12) I3=a1(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=yk1(12) I1=a1(14) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=a1(12) I2=yk1(12) I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(13) I3=yk1(13) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(12) I3=yk1(14) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=yk1(13) I1=a1(15) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=yk1(13) I1=a1(14) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=a1(14) I2=yk1(13) I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=a1(13) I2=yk1(15) I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=yk1(14) I1=a1(14) I2=yk1(15) I3=a1(13) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=yk1(13) I1=a1(14) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I2=yk1(15) I3=a1(11) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=yk1(14) I1=a1(13) I2=yk1(15) I3=a1(12) O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(12) I1=a1(15) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010001000101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_2_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_2_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_1_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(25) I3=temp_ysum_LUT4_O_2_I3 O=temp_ysum(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(6) I3=temp_ysum_LUT4_O_20_I3 O=temp_ysum(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I1_LUT4_I3_O I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=yk2(7) I1=a2(0) I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=yk2(2) I3=a2(4) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=a2(4) I3=yk2(3) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=a2(5) I3=yk2(2) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(4) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(6) I2=yk2(5) I3=a2(2) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(3) I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(4) I2=yk2(5) I3=a2(2) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=yk2(6) I3=a2(0) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=yk2(6) I1=a2(0) I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=temp_yk(0) I1=a2(14) I2=yk2(2) I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=yk2(1) I1=a2(15) I2=yk2(12) I3=a2(4) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(4) I3=yk2(1) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=yk2(0) I1=a2(5) I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I1 I1=a2(3) I2=yk2(1) I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(2) I2=yk2(3) I3=a2(2) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=a2(3) I3=yk2(2) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(4) I2=yk2(3) I3=a2(2) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I3 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I2 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=yk2(2) I1=a2(4) I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=yk2(0) I3=a2(5) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk2(0) I1=a2(6) I2=yk2(1) I3=a2(5) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(3) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(5) I2=yk2(4) I3=a2(2) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=a2(3) I2=yk2(2) I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(3) I2=yk2(4) I3=a2(2) O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3 I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I3_LUT4_I0_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=temp_ysum_LUT4_O_20_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(5) I3=temp_ysum_LUT4_O_21_I3 O=temp_ysum(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3 I2=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001100110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(0) I3=yk1(3) O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=yk1(0) I1=yk1(1) I2=a1(2) I3=a1(1) O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(1) I3=yk1(2) O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=yk1(0) I1=a1(3) I2=yk1(1) I3=a1(2) O=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I1_LUT4_I3_O I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=temp_ysum_LUT4_O_21_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O O=temp_ysum_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=yk2(0) I1=a2(8) I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_ysum_LUT4_O_22_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_22_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I1_LUT4_I3_O I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=temp_ysum_LUT4_O_21_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(4) I3=temp_ysum_LUT4_O_22_I3 O=temp_ysum(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_22_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_22_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I1_LUT4_I3_O I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I1_O O=temp_ysum_LUT4_O_22_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_23_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_22_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_22_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(3) I3=temp_ysum_LUT4_O_23_I3 O=temp_ysum(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_23_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I1_LUT4_I3_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=temp_ysum_LUT4_O_23_I3_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011001011110011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I0_O O=temp_ysum_LUT4_O_23_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=temp_ysum_LUT4_O_23_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I0_O I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=temp_ysum_LUT4_O_25_I3_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_1_O O=temp_ysum_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=a1(5) I3=yk1(1) O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(5) O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(3) I1=a1(3) I2=yk1(4) I3=a1(2) O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(4) I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(2) I1=yk1(3) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=yk1(1) I3=a1(4) O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(0) I3=yk1(5) O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(6) I3=yk1(0) O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(2) I3=temp_ysum_LUT4_O_24_I3 O=temp_ysum(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_24_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_25_I3_LUT4_O_I1 I1=temp_ysum_LUT4_O_25_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_25_I3_LUT4_O_I0 I3=temp_ysum_LUT4_O_25_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_25_I3_LUT4_O_I0 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I0_O I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_25_I3_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_1_O O=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_ysum_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3 I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_1_O I3=temp_ysum_LUT4_O_25_I3_LUT4_O_I0_LUT4_O_I1 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(0) I3=yk2(5) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I2 I2=yk1(2) I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I2 I2=yk1(2) I3=a1(0) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=a1(1) I3=yk1(3) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(1) I1=a1(3) I2=yk1(2) I3=a1(2) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=a1(3) I1=yk1(0) I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=yk1(0) I1=a1(4) I2=yk1(4) I3=a1(0) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(5) I3=yk1(0) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=yk1(1) I1=a1(4) I2=yk1(5) I3=a1(0) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(4) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(2) I1=a1(3) I2=yk1(3) I3=a1(2) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I1=a1(1) I2=yk1(3) I3=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(1) I1=yk1(2) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=yk1(0) I1=yk1(4) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_24_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(1) I3=temp_ysum_LUT4_O_25_I3 O=temp_ysum(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_25_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_25_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_25_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_25_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_25_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_25_I3_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_1_O O=temp_ysum_LUT4_O_25_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(0) I3=yk2(4) O=temp_ysum_LUT4_O_25_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O I2=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_25_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_25_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=yk2(2) I3=temp_ysum_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(0) I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=temp_ysum_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=yk2(2) I3=a2(0) O=temp_ysum_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_25_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(0) I3=temp_ysum_LUT4_O_26_I3 O=temp_ysum(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_21_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=a1(0) I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I2 I3=yk1(2) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111110011
+.subckt LUT4 I0=yk1(0) I1=yk1(1) I2=a1(1) I3=a1(0) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=yk1(0) I1=a1(2) I2=yk1(1) I3=a1(1) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=yk2(2) I3=a2(0) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111111111
+.subckt LUT4 I0=temp_yk(0) I1=yk2(1) I2=a2(1) I3=yk2(0) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=yk2(0) I1=a2(2) I2=a2(1) I3=yk2(1) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(3) I3=yk2(0) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=a2(1) I1=yk2(2) I2=yk2(1) I3=a2(2) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I1 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I2 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I3 O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I2 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I3 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I1 O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(4) I3=yk2(0) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=a2(1) I1=yk2(1) I2=yk2(2) I3=a2(2) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I1 I2=a2(3) I3=yk2(1) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(3) I2=yk2(2) I3=a2(2) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I0_O I2=temp_ysum_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=yk2(0) I1=a2(1) I2=yk2(1) I3=a2(2) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(0) I3=yk2(3) O=temp_ysum_LUT4_O_26_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_2_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_2_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=yk1(11) I3=a1(15) O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=a1(14) I2=yk1(11) I3=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(12) I1=a1(13) I2=yk1(13) I3=a1(12) O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=temp_ysum_LUT4_O_3_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(24) I3=temp_ysum_LUT4_O_3_I3 O=temp_ysum(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_3_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011001000001101
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=yk1(10) I3=a1(15) O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=yk1(11) I1=a1(15) I2=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(23) I3=temp_ysum_LUT4_O_4_I3 O=temp_ysum(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I3 O=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=yk1(9) I1=a1(15) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=a1(8) I2=yk1(14) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=a1(14) I3=yk1(10) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(15) I1=a1(9) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(11) I3=yk1(13) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(12) I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=a1(9) I2=yk1(13) I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=yk1(15) I3=a1(8) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=yk1(9) I3=a1(15) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=a1(14) I3=yk1(8) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(11) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(12) I1=a1(10) I2=yk1(13) I3=a1(9) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(10) I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(11) I1=yk1(12) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(12) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(13) I1=a1(10) I2=yk1(14) I3=a1(9) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(11) I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(12) I1=yk1(13) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=yk1(14) I1=a1(8) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=a1(14) I2=yk1(9) I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=a1(14) I3=yk1(9) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(10) I1=a1(13) I2=yk1(11) I3=a1(12) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(11) I2=yk1(10) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk1(14) I1=a1(11) I2=yk1(15) I3=a1(10) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=a1(14) I3=yk1(11) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=yk1(15) I3=a1(9) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=yk1(10) I1=a1(15) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=a1(14) I2=yk1(10) I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(11) I1=a1(13) I2=yk1(12) I3=a1(12) O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(12) I2=yk1(11) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I0_LUT4_I3_O I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_ysum_LUT4_O_6_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_5_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(22) I3=temp_ysum_LUT4_O_5_I3 O=temp_ysum(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_5_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=a2(9) I2=yk2(14) I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(12) I1=a2(11) I2=yk2(13) I3=a2(10) O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(12) I1=yk2(13) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I0_LUT4_I3_O O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(21) I3=temp_ysum_LUT4_O_6_I3 O=temp_ysum(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I0_LUT4_I3_O O=temp_ysum_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I0_LUT4_I3_O I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=yk2(15) I3=a2(8) O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_I2_O I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=yk1(8) I3=a1(15) O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum(20) I1=temp_ysum_LUT4_O_7_I1 I2=temp_ysum_LUT4_O_7_I2 I3=temp_ysum_LUT4_O_I3 O=temp_ysum(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1 I1=temp_ysum_LUT4_O_7_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_I2_I1 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_I2_I1 I2=temp_ysum_LUT4_O_7_I1 I3=temp_ysum_LUT4_O_7_I2 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I0 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_7_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110000010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=yk1(5) I3=a1(15) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=yk1(12) I1=yk1(13) I2=a1(4) I3=a1(5) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=a1(8) I3=yk1(10) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(11) I1=a1(7) I2=yk1(12) I3=a1(6) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=a1(8) I2=yk1(9) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(10) I1=yk1(11) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(8) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(9) I1=a1(10) I2=yk1(10) I3=a1(9) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(7) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(8) I1=yk1(9) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a1(14) I2=yk1(5) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a1(14) I3=yk1(5) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(6) I1=a1(13) I2=yk1(7) I3=a1(12) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(7) I2=yk1(6) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(6) I1=a1(15) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(8) I3=yk1(13) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=a1(6) I3=yk1(15) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=a1(8) I2=yk1(12) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=a1(6) I2=yk1(13) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=a1(5) I2=yk1(15) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk1(6) I3=a1(15) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=yk1(13) I1=yk1(14) I2=a1(4) I3=a1(5) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=a1(8) I3=yk1(11) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(12) I1=a1(7) I2=yk1(13) I3=a1(6) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=a1(8) I2=yk1(10) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(11) I1=yk1(12) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(9) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(10) I1=a1(10) I2=yk1(11) I3=a1(9) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(8) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(9) I1=yk1(10) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a1(14) I2=yk1(6) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a1(14) I3=yk1(6) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(7) I1=a1(13) I2=yk1(8) I3=a1(12) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(8) I2=yk1(7) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(7) I1=a1(15) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=yk1(14) I1=a1(8) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=yk1(15) I3=a1(6) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(7) I3=yk1(15) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk2(14) I3=a2(8) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=yk2(5) I1=a2(15) I2=yk2(6) I3=a2(14) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=a2(5) I2=yk2(14) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(12) I1=yk2(13) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=a2(14) I2=yk2(5) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(4) I1=yk2(15) I2=a2(4) I3=a2(15) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(8) I1=a2(13) I2=yk2(9) I3=a2(12) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(7) I1=yk2(8) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a2(9) I2=yk2(12) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a2(9) I3=yk2(12) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(10) I1=a2(11) I2=yk2(11) I3=a2(10) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(10) I1=yk2(11) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(7) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=yk2(9) I3=a2(14) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100110011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(15) I3=yk2(8) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=a2(7) I2=yk2(15) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000100010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=yk2(15) I1=a2(8) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=a2(9) I2=yk2(13) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=a2(9) I3=yk2(13) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(11) I1=a2(11) I2=yk2(12) I3=a2(10) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(11) I1=yk2(12) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_I2_O I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000101010000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_I2_O O=temp_ysum_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk1(7) I3=a1(15) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=yk1(14) I1=yk1(15) I2=a1(4) I3=a1(5) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=a1(8) I3=yk1(12) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(13) I1=a1(7) I2=yk1(14) I3=a1(6) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=a1(8) I2=yk1(11) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(12) I1=yk1(13) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(10) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(11) I1=a1(10) I2=yk1(12) I3=a1(9) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(9) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(10) I1=yk1(11) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a1(14) I2=yk1(7) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a1(14) I3=yk1(7) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(8) I1=a1(13) I2=yk1(9) I3=a1(12) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(9) I2=yk1(8) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=yk1(15) I2=a1(8) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(7) I3=yk1(14) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk1(8) I1=a1(15) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=a1(14) I2=yk1(8) I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(9) I1=a1(13) I2=yk1(10) I3=a1(12) O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(10) I2=yk1(9) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I0 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(19) I3=temp_ysum_LUT4_O_8_I3 O=temp_ysum(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=yk2(13) I3=a2(8) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=a2(14) I3=yk2(5) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(4) I1=a2(15) I2=yk2(15) I3=a2(4) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=a2(5) I2=yk2(13) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(11) I1=a2(7) I2=yk2(12) I3=a2(6) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(11) I1=yk2(12) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=a2(14) I2=yk2(4) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(3) I1=yk2(14) I2=a2(4) I3=a2(15) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(7) I1=a2(13) I2=yk2(8) I3=a2(12) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(6) I1=yk2(7) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a2(9) I2=yk2(11) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a2(9) I3=yk2(11) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(9) I1=a2(11) I2=yk2(10) I3=a2(10) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(9) I1=yk2(10) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(14) I1=a2(8) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a2(7) I3=yk2(15) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=yk2(6) I1=yk2(7) I2=a2(15) I3=a2(14) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=yk2(7) I1=a2(15) I2=yk2(8) I3=a2(14) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(9) I1=a2(13) I2=yk2(10) I3=a2(12) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(8) I1=yk2(9) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=yk2(12) I1=a2(8) I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk2(15) I1=a2(5) I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=a2(5) I2=yk2(15) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=a2(6) I2=yk2(13) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=yk2(13) I1=a2(7) I2=yk2(14) I3=a2(6) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a2(5) I3=yk2(14) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(12) I1=a2(7) I2=yk2(13) I3=a2(6) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=yk2(15) I3=a2(3) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=yk2(15) I2=a2(3) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(2) I3=yk2(14) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=a2(5) I3=yk2(13) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=yk2(14) I1=a2(3) I2=yk2(15) I3=a2(2) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=a2(5) I3=yk2(12) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=a2(1) I3=yk2(15) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(3) I3=yk2(13) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=yk2(12) I3=a2(8) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=a2(14) I3=yk2(4) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(3) I1=a2(15) I2=yk2(14) I3=a2(4) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=a2(5) I2=yk2(12) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(10) I1=a2(7) I2=yk2(11) I3=a2(6) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(10) I1=yk2(11) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=a2(14) I2=yk2(3) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(2) I1=a2(15) I2=yk2(13) I3=a2(4) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(2) I1=yk2(13) I2=a2(4) I3=a2(15) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(6) I1=a2(13) I2=yk2(7) I3=a2(12) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(5) I1=yk2(6) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=yk2(4) I1=yk2(5) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=yk2(5) I1=a2(13) I2=yk2(6) I3=a2(12) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=a2(9) I3=yk2(9) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=a2(9) I2=yk2(10) I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=a2(9) I3=yk2(10) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(8) I1=a2(11) I2=yk2(9) I3=a2(10) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(8) I1=yk2(9) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(13) I1=a2(8) I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk2(15) I1=a2(5) I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(7) I3=yk2(14) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(6) I3=yk2(15) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(6) I1=a2(15) I2=yk2(7) I3=a2(14) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(5) I1=yk2(6) I2=a2(15) I3=a2(14) O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I3 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I3 I2=temp_ysum(18) I3=temp_ysum_LUT4_O_9_I3 O=temp_ysum(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_11_I3_LUT4_O_I2 I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I3 I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000101000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=yk2(11) I3=a2(8) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=a2(14) I3=yk2(3) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=a2(5) I2=yk2(11) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(9) I1=a2(7) I2=yk2(10) I3=a2(6) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(9) I1=yk2(10) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=a2(9) I2=yk2(9) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(7) I1=a2(11) I2=yk2(8) I3=a2(10) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(7) I1=yk2(8) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=yk2(10) I3=a2(8) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3 I2=a2(14) I3=yk2(2) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=a2(5) I2=yk2(10) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(8) I1=a2(7) I2=yk2(9) I3=a2(6) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(8) I1=yk2(9) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(4) I1=a2(13) I2=yk2(5) I3=a2(12) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(3) I1=yk2(4) I2=a2(13) I3=a2(12) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=yk2(3) I1=a2(13) I2=yk2(4) I3=a2(12) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(12) I2=yk2(3) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=a2(0) I2=yk2(2) I3=temp_ysum_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a2(9) I2=yk2(8) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a2(9) I3=yk2(8) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(6) I1=a2(11) I2=yk2(7) I3=a2(10) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(6) I1=yk2(7) I2=a2(11) I3=a2(10) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(11) I1=a2(8) I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=yk2(10) I1=a2(8) I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I2_LUT4_I0_O I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=yk1(4) I3=a1(15) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=yk1(11) I1=yk1(12) I2=a1(4) I3=a1(5) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=a1(8) I3=yk1(9) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(10) I1=a1(7) I2=yk1(11) I3=a1(6) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=a1(8) I2=yk1(8) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(9) I1=yk1(10) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(7) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(8) I1=a1(10) I2=yk1(9) I3=a1(9) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(6) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(7) I1=yk1(8) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a1(14) I2=yk1(4) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a1(14) I3=yk1(4) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(5) I1=a1(13) I2=yk1(6) I3=a1(12) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(6) I2=yk1(5) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(5) I1=a1(15) I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(5) I3=yk1(15) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk1(3) I3=a1(15) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=a1(8) I3=yk1(8) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(9) I1=a1(7) I2=yk1(10) I3=a1(6) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=a1(5) I2=yk1(10) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(11) I1=a1(4) I2=yk1(15) I3=a1(0) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(11) I1=yk1(15) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=a1(8) I2=yk1(7) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(8) I1=a1(7) I2=yk1(9) I3=a1(6) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(8) I1=yk1(9) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(6) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(7) I1=a1(10) I2=yk1(8) I3=a1(9) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=a1(11) I2=yk1(5) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(6) I1=yk1(7) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=a1(14) I3=yk1(2) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=a1(11) I3=yk1(5) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(6) I1=a1(10) I2=yk1(7) I3=a1(9) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=a1(11) I2=yk1(4) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(5) I1=a1(10) I2=yk1(6) I3=a1(9) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(5) I1=yk1(6) I2=a1(9) I3=a1(10) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=a1(14) I2=yk1(3) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=a1(14) I3=yk1(3) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(4) I1=a1(13) I2=yk1(5) I3=a1(12) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=yk1(5) I2=yk1(4) I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(4) I1=a1(15) I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(14) I1=a1(5) I2=yk1(15) I3=a1(4) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=yk1(15) I3=a1(3) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=yk1(3) I1=a1(15) I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=yk1(15) I2=a1(3) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(2) I3=yk1(14) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=yk1(13) I1=a1(5) I2=yk1(14) I3=a1(4) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk1(12) I1=a1(5) I2=yk1(13) I3=a1(4) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(14) I1=a1(3) I2=yk1(15) I3=a1(2) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=yk1(15) I3=a1(1) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=a1(5) I3=yk1(10) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(14) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(12) I1=a1(3) I2=yk1(13) I3=a1(2) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=a1(1) I2=yk1(13) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(11) I1=a1(3) I2=yk1(12) I3=a1(2) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(11) I1=yk1(12) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk1(11) I1=a1(5) I2=yk1(12) I3=a1(4) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(15) I1=a1(1) I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(3) I3=yk1(13) O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(14) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=temp_yk(0) I1=a1(2) I2=yk1(12) I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3 I1=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3 I2=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=temp_ysum_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100100010
+.subckt LUT4 I0=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_7_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_9_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_19_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_19_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_19_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=a2(8) I3=yk2(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a2(4) I3=yk2(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=a2(5) I2=yk2(4) I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(2) I1=yk2(3) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a2(5) I3=yk2(5) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(3) I1=a2(7) I2=yk2(4) I3=a2(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(7) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(9) I2=yk2(8) I3=a2(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(6) I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(7) I2=yk2(8) I3=a2(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(9) I1=a2(0) I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=a2(4) I3=yk2(5) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a2(5) I3=yk2(4) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(2) I1=a2(7) I2=yk2(3) I3=a2(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(8) I2=yk2(7) I3=a2(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(5) I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(6) I2=yk2(7) I3=a2(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=a2(0) I2=yk2(8) I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=a2(4) I2=yk2(3) I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=yk2(0) I1=yk2(1) I2=a2(6) I3=a2(5) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(8) I3=yk2(1) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=yk2(0) I3=a2(8) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=yk2(7) I3=a2(0) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=a2(0) I3=yk2(8) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=a2(4) I3=yk2(4) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=a2(5) I3=yk2(3) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(5) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(7) I2=yk2(6) I3=a2(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(4) I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(5) I2=yk2(6) I3=a2(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_20_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=a1(9) I2=yk1(0) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(0) I1=a1(10) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=a1(5) I3=yk1(5) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(9) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(7) I1=a1(3) I2=yk1(8) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(8) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(6) I1=yk1(7) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk1(0) I1=a1(7) I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=a1(5) I2=yk1(1) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(2) I1=a1(4) I2=yk1(6) I3=a1(0) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk1(2) I1=yk1(6) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=a1(7) I2=yk1(0) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(6) I3=yk1(1) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=a1(8) I3=yk1(0) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(1) I1=a1(7) I2=yk1(2) I3=a1(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=a1(5) I2=yk1(2) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(3) I1=yk1(7) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a1(5) I3=yk1(3) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(4) I1=a1(4) I2=yk1(8) I3=a1(0) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(7) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(5) I1=a1(3) I2=yk1(6) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(6) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(4) I1=yk1(5) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a1(9) I3=yk1(0) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=a1(8) I3=yk1(1) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(2) I1=a1(7) I2=yk1(3) I3=a1(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=a1(5) I2=yk1(3) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(4) I1=yk1(8) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=a1(8) I2=yk1(0) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(1) I1=yk1(2) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a1(5) I3=yk1(4) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(5) I1=a1(4) I2=yk1(9) I3=a1(0) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(8) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(6) I1=a1(3) I2=yk1(7) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(7) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(5) I1=yk1(6) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk1(0) I1=a1(7) I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a1(5) I3=yk1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(3) I1=a1(4) I2=yk1(7) I3=a1(0) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(4) I1=a1(3) I2=yk1(5) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(5) I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(3) I1=yk1(4) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_23_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a1(8) I3=yk1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(3) I1=a1(7) I2=yk1(4) I3=a1(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=a1(5) I2=yk1(4) I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(5) I1=yk1(9) I2=a1(0) I3=a1(4) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=a1(8) I2=yk1(1) I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(2) I1=yk1(3) I2=a1(6) I3=a1(7) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=yk1(0) I1=a1(11) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=a1(10) I2=yk1(0) I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=yk1(1) I1=a1(10) I2=yk1(2) I3=a1(9) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=a1(5) I3=yk1(7) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(11) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(9) I1=a1(3) I2=yk1(10) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(10) I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(8) I1=yk1(9) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk1(0) I1=a1(10) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a1(9) I3=yk1(1) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_17_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=a1(5) I3=yk1(6) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a1(1) I3=yk1(10) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk1(8) I1=a1(3) I2=yk1(9) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a1(1) I2=yk1(9) I3=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk1(7) I1=yk1(8) I2=a1(3) I3=a1(2) O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I1_LUT4_O_I3 I3=temp_ysum_LUT4_O_I2 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=temp_ysum_LUT4_O_I2_LUT4_O_I3 I1=temp_ysum_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1 I3=temp_ysum_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=yk2(3) I3=a2(8) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=a2(0) I2=yk2(9) I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=a2(0) I3=yk2(10) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=yk2(0) I1=a2(10) I2=yk2(1) I3=a2(9) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_yk(0) I1=a2(4) I2=yk2(5) I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=a2(5) I2=yk2(3) I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(1) I1=a2(7) I2=yk2(2) I3=a2(6) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(1) I1=yk2(2) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(10) I3=yk2(1) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(4) I1=a2(8) I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=yk2(0) I3=a2(11) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=yk2(0) I1=a2(11) I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(9) I3=yk2(2) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=yk2(3) I1=a2(9) I2=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=a2(0) I2=yk2(11) I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=a2(4) I2=yk2(7) I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=a2(4) I3=yk2(8) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=a2(5) I3=yk2(7) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(9) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(11) I2=yk2(10) I3=a2(2) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(8) I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(9) I2=yk2(10) I3=a2(2) O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=temp_ysum_LUT4_O_I2_LUT4_O_I2 I2=temp_ysum_LUT4_O_I2_LUT4_O_I3 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=temp_ysum_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=a2(8) I2=yk2(2) I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=yk2(9) I1=a2(0) I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_yk(0) I2=a2(9) I3=yk2(0) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=temp_yk(0) I1=a2(4) I2=yk2(4) I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=a2(5) I2=yk2(2) I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(0) I1=a2(7) I2=yk2(1) I3=a2(6) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=yk2(0) I1=yk2(1) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=yk2(3) I1=a2(8) I2=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=a2(0) I2=yk2(10) I3=temp_ysum_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=a2(0) I3=yk2(11) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=a2(4) I2=yk2(6) I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=a2(4) I3=yk2(7) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=a2(5) I2=yk2(5) I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=yk2(3) I1=yk2(4) I2=a2(7) I3=a2(6) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_13_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=a2(5) I3=yk2(6) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=a2(3) I3=yk2(8) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=a2(1) I1=yk2(10) I2=yk2(9) I3=a2(2) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=a2(3) I2=yk2(7) I3=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=a2(1) I1=yk2(8) I2=yk2(9) I3=a2(2) O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_yk(0) I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=temp_ysum_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=temp_ysum_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=obf_state(1) I1=obf_state(0) I2=obf_state(2) I3=obf_state(3) O=temp_ysum_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=uk1(7) D=temp_uk1(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk1(6) D=temp_uk1(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk1(5) D=temp_uk1(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk1(4) D=temp_uk1(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk1(3) D=temp_uk1(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk1(2) D=temp_uk1(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk1(1) D=temp_uk1(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk1(0) D=temp_uk1(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk2(7) D=temp_uk2(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk2(6) D=temp_uk2(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk2(5) D=temp_uk2(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk2(4) D=temp_uk2(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk2(3) D=temp_uk2(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk2(2) D=temp_uk2(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk2(1) D=temp_uk2(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk2(0) D=temp_uk2(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk(7) D=temp_uk(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk(6) D=temp_uk(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk(5) D=temp_uk(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk(4) D=temp_uk(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk(3) D=temp_uk(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk(2) D=temp_uk(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk(1) D=temp_uk(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=uk(0) D=temp_uk(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(22) D=temp_utmp(22) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(21) D=temp_utmp(21) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(12) D=temp_utmp(12) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(11) D=temp_utmp(11) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(10) D=temp_utmp(10) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(9) D=temp_utmp(9) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(8) D=temp_utmp(8) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(7) D=temp_utmp(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(6) D=temp_utmp(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(5) D=temp_utmp(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(4) D=temp_utmp(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(3) D=temp_utmp(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(20) D=temp_utmp(20) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(2) D=temp_utmp(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(1) D=temp_utmp(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(0) D=temp_utmp(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(19) D=temp_utmp(19) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(18) D=temp_utmp(18) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(17) D=temp_utmp(17) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(16) D=temp_utmp(16) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(15) D=temp_utmp(15) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(14) D=temp_utmp(14) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=utmp(13) D=temp_utmp(13) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=wait_counter(1) I1=wait_counter(0) I2=wait_counter(2) I3=wait_counter(3) O=temp_yk1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=wait_counter(3) D=temp_wait_counter(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:212.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=wait_counter(2) D=temp_wait_counter(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:212.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=wait_counter(1) D=temp_wait_counter(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:212.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=wait_counter(0) D=temp_wait_counter(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:212.1-218.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(15) D=temp_yk1(15) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(14) D=temp_yk1(14) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(5) D=temp_yk1(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(4) D=temp_yk1(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(3) D=temp_yk1(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(2) D=temp_yk1(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(1) D=temp_yk1(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(0) D=temp_yk1(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(13) D=temp_yk1(13) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(12) D=temp_yk1(12) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(11) D=temp_yk1(11) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(10) D=temp_yk1(10) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(9) D=temp_yk1(9) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(8) D=temp_yk1(8) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(7) D=temp_yk1(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk1(6) D=temp_yk1(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(15) D=temp_yk2(15) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(14) D=temp_yk2(14) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(5) D=temp_yk2(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(4) D=temp_yk2(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(3) D=temp_yk2(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(2) D=temp_yk2(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(1) D=temp_yk2(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(0) D=temp_yk2(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(13) D=temp_yk2(13) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(12) D=temp_yk2(12) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(11) D=temp_yk2(11) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(10) D=temp_yk2(10) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(9) D=temp_yk2(9) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(8) D=temp_yk2(8) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(7) D=temp_yk2(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk2(6) D=temp_yk2(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(26) D=temp_yk(26) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(25) D=temp_yk(25) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(16) D=temp_yk(16) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(15) D=temp_yk(15) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(14) D=temp_yk(14) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(13) D=temp_yk(13) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(12) D=temp_yk(12) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(11) D=temp_yk(11) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(24) D=temp_yk(24) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(23) D=temp_yk(23) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(22) D=temp_yk(22) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(21) D=temp_yk(21) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(20) D=temp_yk(20) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(19) D=temp_yk(19) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(18) D=temp_yk(18) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=yk(17) D=temp_yk(17) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(26) D=temp_ysum(26) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(25) D=temp_ysum(25) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(16) D=temp_ysum(16) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(15) D=temp_ysum(15) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(14) D=temp_ysum(14) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(13) D=temp_ysum(13) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(12) D=temp_ysum(12) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(11) D=temp_ysum(11) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(10) D=temp_ysum(10) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(9) D=temp_ysum(9) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(8) D=temp_ysum(8) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(7) D=temp_ysum(7) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(24) D=temp_ysum(24) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(6) D=temp_ysum(6) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(5) D=temp_ysum(5) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(4) D=temp_ysum(4) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(3) D=temp_ysum(3) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(2) D=temp_ysum(2) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(1) D=temp_ysum(1) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(0) D=temp_ysum(0) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(23) D=temp_ysum(23) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(22) D=temp_ysum(22) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(21) D=temp_ysum(21) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(20) D=temp_ysum(20) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(19) D=temp_ysum(19) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(18) D=temp_ysum(18) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=ysum(17) D=temp_ysum(17) QCK=$iopadmap$clk QEN=$auto$hilomap.cc:39:hilomap_worker$18951 QRT=$iopadmap$reset QST=temp_yk(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/iir/rtl/iir.v:170.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.end
diff --git a/BENCHMARK/iir/rtl/iir.v b/BENCHMARK/iir/rtl/iir.v
new file mode 100644
index 0000000..c94a026
--- /dev/null
+++ b/BENCHMARK/iir/rtl/iir.v
@@ -0,0 +1,238 @@
+module iir (clk, reset, start, din, params, dout, ready,iir_start,iir_done);
+input clk, reset, start;
+input [7:0] din;
+input [15:0] params;
+output [7:0] dout;
+reg [7:0] dout;
+output ready;
+reg ready;
+reg temp_ready;
+reg [6:0] finite_counter;
+wire count0;
+input iir_start;
+output iir_done;
+wire iir_done;
+reg del_count0;
+
+reg [15:0] a1, a2, b0, b1, b2, yk1, yk2;
+reg [7:0] uk, uk1, uk2 ;
+reg [28:0] ysum ;
+reg [26:0] yk ;
+reg [22:0] utmp;
+reg [3:0] wait_counter ;
+// temporary variable
+wire [31:0] yo1, yo2;
+//wire [23:0] b0t, b1t, b2t;
+wire [22:0] b0t, b1t, b2t;
+wire [22:0] b0tpaj, b1tpaj, b2tpaj;
+
+reg [3:0] obf_state, obf_next_state ;
+
+reg [7:0] temp_uk, temp_uk1, temp_uk2 ;
+reg [15:0] temp_a1, temp_a2, temp_b0, temp_b1, temp_b2, temp_yk1, temp_yk2;
+reg [28:0] temp_ysum ;
+reg [26:0] temp_yk ;
+reg [22:0] temp_utmp;
+reg [7:0] temp_dout;
+reg [3:0] temp_wait_counter ;
+
+parameter 
+idle = 4'b0001 ,
+load_a2 = 4'b0010 ,
+load_b0 = 4'b0011 ,
+load_b1 = 4'b0100 ,
+load_b2 = 4'b0101 ,
+wait4_start = 4'b0110 , 
+latch_din = 4'b0111 ,
+compute_a = 4'b1000 ,
+compute_b = 4'b1001 ,
+compute_yk = 4'b1010 ,
+wait4_count = 4'b1011 ,
+latch_dout = 4'b1100 ;
+
+always @(obf_state or start or din or wait_counter or iir_start or count0) 
+begin
+	case (obf_state ) 
+		idle : 
+			begin
+				if (iir_start)
+					obf_next_state = load_a2 ;
+				else
+					obf_next_state = idle;
+				temp_a1 = params ; 
+			end
+		load_a2 :
+			begin
+				 obf_next_state = load_b0 ;
+				 temp_a2 = params ; 
+			end
+		load_b0 : 
+			begin
+				obf_next_state = load_b1 ;
+				temp_b0 = params ; 
+			end
+		load_b1 : 
+			begin
+				obf_next_state = load_b2 ;
+				temp_b1 = params ; 
+			end
+		load_b2 : 
+			begin
+				obf_next_state = wait4_start ;
+				temp_b2 = params ; 
+			end
+		wait4_start : 
+			begin
+				if (start)
+				begin
+					obf_next_state = latch_din ;
+					temp_uk = din ; 
+				end
+				else
+				begin
+					obf_next_state = wait4_start ;
+					temp_uk = uk;
+				end
+				temp_ready = wait4_start;
+			end
+		latch_din : 
+			begin
+				obf_next_state = compute_a ;
+			end
+		compute_a : 
+			begin
+				obf_next_state = compute_b ;
+
+				temp_ysum = yo1[31:3] + yo2[31:3];
+			end
+		compute_b : 
+			begin
+				obf_next_state = compute_yk ;
+
+//				temp_utmp = b0t[23:0] + b1t[23:0] + b2t[23:0];
+				temp_utmp = b0t + b1t + b2t;
+			end
+		compute_yk : 
+			begin
+				obf_next_state = wait4_count ;
+				temp_uk1 = uk ;
+				temp_uk2 = uk1 ;
+				temp_yk = ysum[26:0] + {utmp[22], utmp[22], utmp[22], utmp[22], utmp};
+				temp_wait_counter = 4 ;
+			end
+
+		wait4_count : 
+			begin
+				if (wait_counter==0 )
+				begin
+					obf_next_state = latch_dout ;
+
+					temp_dout = yk[26:19];
+					temp_yk1 = yk[26:11] ;
+					temp_yk2 = yk1 ;
+				end
+				else
+				begin
+					obf_next_state = wait4_count ; 
+					temp_dout = dout;
+					temp_yk1 = yk1;
+					//temp_yk2 = yk2;
+				end
+
+				temp_wait_counter = wait_counter - 1;
+			end
+		latch_dout : 
+				if (count0)
+					obf_next_state = idle;
+				else 
+					obf_next_state = wait4_start ;
+	endcase
+end 
+
+
+
+//assign yo1 = mul_tc_16_16(yk1, a1, clk);
+assign yo1 = yk1 * a1;
+//assign yo2 = mul_tc_16_16(yk2, a2, clk);
+assign yo2 = yk2*a2;
+//assign b0t = mul_tc_8_16(uk, b0, clk);
+//assign b1t = mul_tc_8_16(uk1, b1, clk);
+//assign b2t = mul_tc_8_16(uk2, b2, clk);
+assign b0t = uk*b0;
+assign b1t = uk1*b1;
+assign b2t = uk2*b2;
+// paj added to solve unused high order bit
+assign b0tpaj = b0t;
+assign b1tpaj = b1t;
+assign b2tpaj = b2t;
+
+// A COEFFICENTS
+always @(posedge clk or posedge reset) begin
+	if (reset ) begin
+		uk <= 0 ;
+		uk1 <= 0 ;
+		uk2 <= 0 ;
+		yk1 <= 0 ;
+		yk2 <= 0 ;
+		yk <= 0 ;
+		ysum <= 0 ;
+		utmp <= 0 ;
+		a1 <= 0 ;
+		a2 <= 0 ;
+		b0 <= 0 ;
+		b1 <= 0 ;
+		b2 <= 0 ;
+		dout <= 0 ;
+		obf_state <= idle ;
+		ready <= 0;
+	end
+	else begin
+		obf_state <= obf_next_state ;
+			uk1 <= temp_uk1;
+			uk2 <= temp_uk2;
+			yk <= temp_yk;
+			uk <= temp_uk ;
+			a1 <= temp_a1 ; 
+			a2 <= temp_a2 ; 
+			b0 <= temp_b0 ; 
+			b1 <= temp_b1 ; 
+			b2 <= temp_b2 ; 
+			ysum <= temp_ysum;
+			utmp <= temp_utmp;
+			dout <= temp_dout;
+			yk1 <= temp_yk1;
+			yk2 <= temp_yk2;
+			ready <= temp_ready;
+	end
+end
+
+// wait counter, count 4 clock after sum is calculated, to 
+// time outputs are ready, and filter is ready to accept next
+// input
+always @(posedge clk or posedge reset ) begin
+	if (reset )
+		wait_counter <= 0 ;
+	else begin
+		wait_counter <= temp_wait_counter ;
+	end
+end
+
+always @(posedge clk) begin
+	if (reset)
+		finite_counter<=100;
+	else 
+		if (iir_start) 
+			finite_counter<=finite_counter -1;
+		else 
+			finite_counter<=finite_counter;
+end
+
+assign count0=finite_counter==7'b0;
+
+always @(posedge clk) begin
+	del_count0 <= count0;
+end
+
+assign iir_done = (count0 && ~del_count0); 
+
+endmodule
diff --git a/BENCHMARK/jpeg_qnr/jpeg_qnr_yosys.blif b/BENCHMARK/jpeg_qnr/jpeg_qnr_yosys.blif
new file mode 100644
index 0000000..272050c
--- /dev/null
+++ b/BENCHMARK/jpeg_qnr/jpeg_qnr_yosys.blif
@@ -0,0 +1,4546 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model jpeg_qnr
+.inputs clk ena rst dstrb din(0) din(1) din(2) din(3) din(4) din(5) din(6) din(7) din(8) din(9) din(10) din(11) qnt_val(0) qnt_val(1) qnt_val(2) qnt_val(3) qnt_val(4) qnt_val(5) qnt_val(6) qnt_val(7)
+.outputs qnt_cnt(0) qnt_cnt(1) qnt_cnt(2) qnt_cnt(3) qnt_cnt(4) qnt_cnt(5) dout(0) dout(1) dout(2) dout(3) dout(4) dout(5) dout(6) dout(7) dout(8) dout(9) dout(10) douten
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_0 a=divider.d(10)
+.subckt in_buff A=clk Q=divider.clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(0) Q=divider.z(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(1) Q=divider.z(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(10) Q=divider.z(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(11) Q=divider.z(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(2) Q=divider.z(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(3) Q=divider.z(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(4) Q=divider.z(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(5) Q=divider.z(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(6) Q=divider.z(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(7) Q=divider.z(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(8) Q=divider.z(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=din(9) Q=divider.z(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=rq(1) Q=dout(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(2) Q=dout(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(11) Q=dout(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(3) Q=dout(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(4) Q=dout(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(5) Q=dout(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(6) Q=dout(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(7) Q=dout(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(8) Q=dout(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(9) Q=dout(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=rq(10) Q=dout(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=dep(15) Q=douten
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=dstrb Q=$iopadmap$dstrb
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=ena Q=divider.divider.ena
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=$iopadmap$qnt_cnt(0) Q=qnt_cnt(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$qnt_cnt(1) Q=qnt_cnt(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$qnt_cnt(2) Q=qnt_cnt(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$qnt_cnt(3) Q=qnt_cnt(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$qnt_cnt(4) Q=qnt_cnt(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$qnt_cnt(5) Q=qnt_cnt(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=qnt_val(0) Q=divider.d(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=qnt_val(1) Q=divider.d(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=qnt_val(2) Q=divider.d(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=qnt_val(3) Q=divider.d(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=qnt_val(4) Q=divider.d(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=qnt_val(5) Q=divider.d(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=qnt_val(6) Q=divider.d(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=qnt_val(7) Q=divider.d(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rst Q=$iopadmap$rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt ff CQZ=dep(14) D=dep(13) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(13) D=dep(12) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(4) D=dep(3) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(3) D=dep(2) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(2) D=dep(1) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(1) D=dep(0) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(0) D=$iopadmap$dstrb QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(12) D=dep(11) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(11) D=dep(10) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(10) D=dep(9) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(9) D=dep(8) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=dep(8) D=dep(7) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
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+.subckt ff CQZ=divider.divider.q_pipe[10](6) D=divider.divider.q_pipe[9](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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+.subckt ff CQZ=divider.divider.q_pipe[10](5) D=divider.divider.q_pipe[9](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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+.subckt ff CQZ=divider.divider.q_pipe[10](2) D=divider.divider.q_pipe[9](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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+.subckt ff CQZ=divider.divider.q_pipe[10](1) D=divider.divider.q_pipe[9](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
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+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
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+.subckt ff CQZ=divider.divider.q_pipe[11](9) D=divider.divider.q_pipe[10](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[11](7) D=divider.divider.q_pipe[10](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
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+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[11](6) D=divider.divider.q_pipe[10](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[11](5) D=divider.divider.q_pipe[10](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[11](4) D=divider.divider.q_pipe[10](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[11](3) D=divider.divider.q_pipe[10](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[11](2) D=divider.divider.q_pipe[10](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[11](1) D=divider.divider.q_pipe[10](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[1](0) D=divider.divider.q_pipe[1]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[1](24) O=divider.divider.q_pipe[1]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.q_pipe[2](1) D=divider.divider.q_pipe[1](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[2](0) D=divider.divider.q_pipe[2]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[2](24) O=divider.divider.q_pipe[2]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.q_pipe[3](2) D=divider.divider.q_pipe[2](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[3](1) D=divider.divider.q_pipe[2](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[3](0) D=divider.divider.q_pipe[3]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[3](24) O=divider.divider.q_pipe[3]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.q_pipe[4](3) D=divider.divider.q_pipe[3](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[4](2) D=divider.divider.q_pipe[3](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[4](1) D=divider.divider.q_pipe[3](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[4](0) D=divider.divider.q_pipe[4]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[4](24) O=divider.divider.q_pipe[4]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.q_pipe[5](4) D=divider.divider.q_pipe[4](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[5](3) D=divider.divider.q_pipe[4](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[5](2) D=divider.divider.q_pipe[4](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[5](1) D=divider.divider.q_pipe[4](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[5](0) D=divider.divider.q_pipe[5]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[5](24) O=divider.divider.q_pipe[5]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.q_pipe[6](5) D=divider.divider.q_pipe[5](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[6](4) D=divider.divider.q_pipe[5](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[6](3) D=divider.divider.q_pipe[5](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[6](2) D=divider.divider.q_pipe[5](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[6](1) D=divider.divider.q_pipe[5](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[6](0) D=divider.divider.q_pipe[6]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[6](24) O=divider.divider.q_pipe[6]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.q_pipe[7](6) D=divider.divider.q_pipe[6](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[7](5) D=divider.divider.q_pipe[6](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[7](4) D=divider.divider.q_pipe[6](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[7](3) D=divider.divider.q_pipe[6](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[7](2) D=divider.divider.q_pipe[6](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[7](1) D=divider.divider.q_pipe[6](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[7](0) D=divider.divider.q_pipe[7]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[7](24) O=divider.divider.q_pipe[7]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.q_pipe[8](7) D=divider.divider.q_pipe[7](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[8](6) D=divider.divider.q_pipe[7](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[8](5) D=divider.divider.q_pipe[7](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[8](4) D=divider.divider.q_pipe[7](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[8](3) D=divider.divider.q_pipe[7](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[8](2) D=divider.divider.q_pipe[7](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[8](1) D=divider.divider.q_pipe[7](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[8](0) D=divider.divider.q_pipe[8]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[8](24) O=divider.divider.q_pipe[8]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.q_pipe[9](8) D=divider.divider.q_pipe[8](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[9](7) D=divider.divider.q_pipe[8](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[9](6) D=divider.divider.q_pipe[8](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[9](5) D=divider.divider.q_pipe[8](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[9](4) D=divider.divider.q_pipe[8](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[9](3) D=divider.divider.q_pipe[8](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[9](2) D=divider.divider.q_pipe[8](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[9](1) D=divider.divider.q_pipe[8](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.q_pipe[9](0) D=divider.divider.q_pipe[9]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:162.2-165.58|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[9](24) O=divider.divider.q_pipe[9]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.s_pipe[10](24) D=divider.divider.s_pipe[10]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[10](23) D=divider.divider.s_pipe[10]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[10](14) D=divider.divider.s_pipe[10]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](13) I2=divider.divider.d_pipe[9](14) I3=divider.divider.s_pipe[10]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[10](13) D=divider.divider.s_pipe[10]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](12) I2=divider.divider.d_pipe[9](13) I3=divider.divider.s_pipe[10]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[9](12) I2=divider.divider.s_pipe[9](11) I3=divider.divider.s_pipe[9](24) O=divider.divider.s_pipe[10]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[10](12) D=divider.divider.s_pipe[10]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](11) I3=divider.divider.d_pipe[9](12) O=divider.divider.s_pipe[10]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[10](11) D=divider.divider.s_pipe[9](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[10](10) D=divider.divider.s_pipe[9](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](22) I3=divider.divider.s_pipe[10]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[10]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[10](22) D=divider.divider.s_pipe[10]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I0 I1=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[9](21) O=divider.divider.s_pipe[10]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.d_pipe[9](19) I1=divider.divider.s_pipe[9](18) I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[9](20) I3=divider.divider.s_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I1=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[9](20) I3=divider.divider.s_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=divider.divider.s_pipe[10](21) D=divider.divider.s_pipe[10]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I3 I1=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2 I2=divider.divider.s_pipe[9](20) I3=divider.divider.s_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001000111100
+.subckt ff CQZ=divider.divider.s_pipe[10](20) D=divider.divider.s_pipe[10]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](19) I2=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1 O=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[9](18) I3=divider.divider.d_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](24) I3=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I0 O=divider.divider.s_pipe[10]_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[10](19) D=divider.divider.s_pipe[10]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[9](24) I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](17) I3=divider.divider.d_pipe[9](18) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[9](17) I2=divider.divider.s_pipe[9](16) I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](17) I3=divider.divider.d_pipe[9](18) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[9](18) I3=divider.divider.s_pipe[9](17) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.s_pipe[9](16) I2=divider.divider.d_pipe[9](17) I3=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](17) I3=divider.divider.d_pipe[9](18) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](18) I3=divider.divider.d_pipe[9](19) O=divider.divider.s_pipe[10]_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[10](18) D=divider.divider.s_pipe[10]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](17) I2=divider.divider.d_pipe[9](18) I3=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](16) I2=divider.divider.d_pipe[9](17) I3=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](16) I2=divider.divider.d_pipe[9](17) I3=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[10]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=divider.divider.s_pipe[10](17) D=divider.divider.s_pipe[10]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](16) I2=divider.divider.d_pipe[9](17) I3=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[9](16) I1=divider.divider.s_pipe[9](15) I2=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.divider.d_pipe[9](16) I1=divider.divider.s_pipe[9](15) I2=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[10]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[10](16) D=divider.divider.s_pipe[10]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[9](16) I3=divider.divider.s_pipe[9](15) O=divider.divider.s_pipe[10]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](14) I3=divider.divider.d_pipe[9](15) O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](24) I2=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](14) I3=divider.divider.d_pipe[9](15) O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[10](15) D=divider.divider.s_pipe[10]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[9](24) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](13) I2=divider.divider.d_pipe[9](14) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=divider.divider.d_pipe[9](13) I1=divider.divider.s_pipe[9](12) I2=divider.divider.s_pipe[9](11) I3=divider.divider.d_pipe[9](12) O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9](13) I2=divider.divider.d_pipe[9](14) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.d_pipe[9](13) I1=divider.divider.s_pipe[9](12) I2=divider.divider.s_pipe[9](11) I3=divider.divider.d_pipe[9](12) O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[9](14) I2=divider.divider.s_pipe[9](13) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[9](14) I2=divider.divider.s_pipe[9](13) I3=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[10]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9](14) I3=divider.divider.d_pipe[9](15) O=divider.divider.s_pipe[10]_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[9](22) I2=divider.divider.s_pipe[9](24) I3=divider.divider.s_pipe[9](23) O=divider.divider.s_pipe[10]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111001000001
+.subckt LUT4 I0=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I1 I1=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I0 I2=divider.divider.s_pipe[10]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[9](21) O=divider.divider.s_pipe[10]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt ff CQZ=divider.divider.s_pipe[11](24) D=divider.divider.s_pipe[11]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[11](23) D=divider.divider.s_pipe[11]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[11](14) D=divider.divider.s_pipe[11]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](13) I2=divider.divider.d_pipe[10](14) I3=divider.divider.s_pipe[11]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I3=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 O=divider.divider.s_pipe[11]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[11](13) D=divider.divider.s_pipe[11]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](12) I2=divider.divider.d_pipe[10](13) I3=divider.divider.s_pipe[11]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[10](12) I2=divider.divider.s_pipe[10](11) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[11](12) D=divider.divider.s_pipe[11]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](11) I3=divider.divider.d_pipe[10](12) O=divider.divider.s_pipe[11]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[11](11) D=divider.divider.s_pipe[10](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](22) I2=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1 I3=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[11]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt ff CQZ=divider.divider.s_pipe[11](22) D=divider.divider.s_pipe[11]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](21) I2=divider.divider.s_pipe[11]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_2_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](20) I2=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=divider.divider.s_pipe[11]_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[10](19) I2=divider.divider.s_pipe[10](20) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=divider.divider.s_pipe[11](21) D=divider.divider.s_pipe[11]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](20) I3=divider.divider.s_pipe[11]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[10](19) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101111111111100
+.subckt ff CQZ=divider.divider.s_pipe[11](20) D=divider.divider.s_pipe[11]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[10](24) I3=divider.divider.s_pipe[10](19) O=divider.divider.s_pipe[11]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110010100011
+.subckt ff CQZ=divider.divider.s_pipe[11](19) D=divider.divider.s_pipe[11]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.d_pipe[10](19) I3=divider.divider.s_pipe[10](18) O=divider.divider.s_pipe[11]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](17) I3=divider.divider.d_pipe[10](18) O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.d_pipe[10](19) I1=divider.divider.s_pipe[10](18) I2=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](17) I3=divider.divider.d_pipe[10](18) O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.divider.d_pipe[10](19) I1=divider.divider.s_pipe[10](18) I2=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[11](18) D=divider.divider.s_pipe[11]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[10](24) I3=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](16) I2=divider.divider.d_pipe[10](17) I3=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](16) I2=divider.divider.d_pipe[10](17) I3=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[10](17) I2=divider.divider.s_pipe[10](16) I3=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[10](17) I2=divider.divider.s_pipe[10](16) I3=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](17) I3=divider.divider.d_pipe[10](18) O=divider.divider.s_pipe[11]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[11](17) D=divider.divider.s_pipe[11]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](16) I2=divider.divider.d_pipe[10](17) I3=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[10](16) I1=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=divider.divider.d_pipe[10](16) I1=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I2=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt ff CQZ=divider.divider.s_pipe[11](16) D=divider.divider.s_pipe[11]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[10](16) I3=divider.divider.s_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](14) I3=divider.divider.d_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[10](14) I2=divider.divider.s_pipe[10](13) I3=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](14) I3=divider.divider.d_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[10](24) I2=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[10](15) I3=divider.divider.s_pipe[10](14) O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.s_pipe[10](13) I2=divider.divider.d_pipe[10](14) I3=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](14) I3=divider.divider.d_pipe[10](15) O=divider.divider.s_pipe[11]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=divider.divider.s_pipe[11](15) D=divider.divider.s_pipe[11]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.d_pipe[10](15) I3=divider.divider.s_pipe[10](14) O=divider.divider.s_pipe[11]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[10](14) I2=divider.divider.s_pipe[10](13) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100000000
+.subckt LUT4 I0=divider.divider.d_pipe[10](13) I1=divider.divider.s_pipe[10](12) I2=divider.divider.s_pipe[10](11) I3=divider.divider.d_pipe[10](12) O=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.d_pipe[10](14) I2=divider.divider.s_pipe[10](13) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=divider.divider.d_pipe[10](13) I1=divider.divider.s_pipe[10](12) I2=divider.divider.s_pipe[10](11) I3=divider.divider.d_pipe[10](12) O=divider.divider.s_pipe[11]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[10](22) I3=divider.divider.s_pipe[10](23) O=divider.divider.s_pipe[11]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110111001010
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[10](19) I1=divider.divider.s_pipe[10](20) I2=divider.divider.s_pipe[10](21) I3=divider.divider.s_pipe[10](24) O=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=divider.divider.s_pipe[11]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=divider.divider.s_pipe[10](20) I3=divider.divider.s_pipe[10](21) O=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[10](24) I3=divider.divider.s_pipe[10](19) O=divider.divider.s_pipe[11]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=divider.divider.s_pipe[12](24) O=divider.divider.q_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=divider.divider.s_pipe[12](24) D=divider.divider.s_pipe[12]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[11](23) O=divider.divider.s_pipe[12]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=divider.divider.d_pipe[11](19) I1=divider.divider.s_pipe[11](18) I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100010111
+.subckt LUT4 I0=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=divider.divider.d_pipe[11](17) I2=divider.divider.s_pipe[11](16) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[11](15) I2=divider.divider.d_pipe[11](16) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=divider.divider.d_pipe[11](15) I1=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[11](14) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](13) I3=divider.divider.d_pipe[11](14) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=divider.divider.d_pipe[11](13) I2=divider.divider.s_pipe[11](12) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](11) I3=divider.divider.d_pipe[11](12) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](13) I3=divider.divider.d_pipe[11](14) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](17) I3=divider.divider.d_pipe[11](18) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](17) I3=divider.divider.d_pipe[11](18) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[11](21) I2=divider.divider.s_pipe[11](22) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[11](24) I2=divider.divider.s_pipe[11](19) I3=divider.divider.s_pipe[11](20) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=divider.divider.s_pipe[11](20) I1=divider.divider.s_pipe[11](19) I2=divider.divider.s_pipe[11](24) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=divider.divider.d_pipe[11](19) I1=divider.divider.s_pipe[11](18) I2=divider.divider.s_pipe[11](22) I3=divider.divider.s_pipe[11](21) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=divider.divider.s_pipe[11](17) I1=divider.divider.d_pipe[11](18) I2=divider.divider.d_pipe[11](19) I3=divider.divider.s_pipe[11](18) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000001011
+.subckt LUT4 I0=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=divider.divider.s_pipe[11](16) I2=divider.divider.d_pipe[11](17) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[11](16) I2=divider.divider.s_pipe[11](15) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[11](15) I2=divider.divider.s_pipe[11](14) I3=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.d_pipe[11](14) I1=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[11](13) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[11](12) I2=divider.divider.s_pipe[11](12) I3=divider.divider.s_pipe[11](11) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=divider.divider.s_pipe[11](11) I1=divider.divider.d_pipe[11](12) I2=divider.divider.s_pipe[11](12) I3=divider.divider.d_pipe[11](13) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[11](17) I3=divider.divider.d_pipe[11](18) O=divider.divider.s_pipe[12]_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=divider.divider.s_pipe[1](24) D=divider.divider.s_pipe[1]_ff_CQZ_D(12) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](23) D=divider.divider.s_pipe[1]_ff_CQZ_D(11) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](14) D=divider.divider.s_pipe[1]_ff_CQZ_D(2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](13) D=divider.divider.s_pipe[1]_ff_CQZ_D(1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](12) D=divider.divider.s_pipe[1]_ff_CQZ_D(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](11) D=divider.divider.s_pipe[0](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](10) D=divider.divider.s_pipe[0](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](9) D=divider.divider.s_pipe[0](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](8) D=divider.divider.s_pipe[0](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](7) D=divider.divider.s_pipe[0](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](6) D=divider.divider.s_pipe[0](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](5) D=divider.divider.s_pipe[0](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](22) D=divider.divider.s_pipe[1]_ff_CQZ_D(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](4) D=divider.divider.s_pipe[0](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](3) D=divider.divider.s_pipe[0](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](2) D=divider.divider.s_pipe[0](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](1) D=divider.divider.s_pipe[0](0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](21) D=divider.divider.s_pipe[1]_ff_CQZ_D(9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](20) D=divider.divider.s_pipe[1]_ff_CQZ_D(8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](19) D=divider.divider.s_pipe[1]_ff_CQZ_D(7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](18) D=divider.divider.s_pipe[1]_ff_CQZ_D(6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](17) D=divider.divider.s_pipe[1]_ff_CQZ_D(5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](16) D=divider.divider.s_pipe[1]_ff_CQZ_D(4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[1](15) D=divider.divider.s_pipe[1]_ff_CQZ_D(3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.id_LUT4_I0_O I1=divider.divider.s_pipe[0](22) I2=divider.divider.s_pipe[1]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[0](23) O=divider.divider.s_pipe[1]_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100010000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](22) I2=divider.divider.s_pipe[1]_ff_CQZ_D_LUT4_O_I2 I3=divider.id_LUT4_I0_O O=divider.divider.s_pipe[1]_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=divider.id_LUT4_I0_O I1=divider.divider.s_pipe[0](19) I2=divider.divider.s_pipe[0](20) I3=divider.divider.s_pipe[0](21) O=divider.divider.s_pipe[1]_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000001
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](20) I2=divider.divider.s_pipe[0](19) I3=divider.id_LUT4_I0_O O=divider.divider.s_pipe[1]_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[0](19) I3=divider.id_LUT4_I0_O O=divider.divider.s_pipe[1]_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](20) I2=divider.divider.s_pipe[0](19) I3=divider.divider.s_pipe[0](21) O=divider.divider.s_pipe[1]_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt ff CQZ=divider.divider.s_pipe[2](24) D=divider.divider.s_pipe[2]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](23) D=divider.divider.s_pipe[2]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](14) D=divider.divider.s_pipe[2]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](13) I2=divider.divider.d_pipe[1](14) I3=divider.divider.s_pipe[2]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[2](13) D=divider.divider.s_pipe[2]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](12) I2=divider.divider.d_pipe[1](13) I3=divider.divider.s_pipe[2]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[1](12) I2=divider.divider.s_pipe[1](11) I3=divider.divider.s_pipe[1](24) O=divider.divider.s_pipe[2]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[2](12) D=divider.divider.s_pipe[2]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](11) I3=divider.divider.d_pipe[1](12) O=divider.divider.s_pipe[2]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[2](11) D=divider.divider.s_pipe[1](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](10) D=divider.divider.s_pipe[1](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](9) D=divider.divider.s_pipe[1](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](8) D=divider.divider.s_pipe[1](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](7) D=divider.divider.s_pipe[1](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](6) D=divider.divider.s_pipe[1](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](5) D=divider.divider.s_pipe[1](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](22) I3=divider.divider.s_pipe[2]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[2]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[2](22) D=divider.divider.s_pipe[2]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](4) D=divider.divider.s_pipe[1](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](3) D=divider.divider.s_pipe[1](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[2](2) D=divider.divider.s_pipe[1](1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I0 I1=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[1](21) O=divider.divider.s_pipe[2]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.d_pipe[1](19) I1=divider.divider.s_pipe[1](18) I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[1](20) I3=divider.divider.s_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I1=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[1](20) I3=divider.divider.s_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=divider.divider.s_pipe[2](21) D=divider.divider.s_pipe[2]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I3 I1=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2 I2=divider.divider.s_pipe[1](20) I3=divider.divider.s_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001000111100
+.subckt ff CQZ=divider.divider.s_pipe[2](20) D=divider.divider.s_pipe[2]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](19) I2=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1 O=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[1](18) I3=divider.divider.d_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](24) I3=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I0 O=divider.divider.s_pipe[2]_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[2](19) D=divider.divider.s_pipe[2]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[1](24) I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](17) I3=divider.divider.d_pipe[1](18) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[1](17) I2=divider.divider.s_pipe[1](16) I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](17) I3=divider.divider.d_pipe[1](18) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[1](18) I3=divider.divider.s_pipe[1](17) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.s_pipe[1](16) I2=divider.divider.d_pipe[1](17) I3=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](17) I3=divider.divider.d_pipe[1](18) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](18) I3=divider.divider.d_pipe[1](19) O=divider.divider.s_pipe[2]_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[2](18) D=divider.divider.s_pipe[2]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](17) I2=divider.divider.d_pipe[1](18) I3=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](16) I2=divider.divider.d_pipe[1](17) I3=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](16) I2=divider.divider.d_pipe[1](17) I3=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[2]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=divider.divider.s_pipe[2](17) D=divider.divider.s_pipe[2]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](16) I2=divider.divider.d_pipe[1](17) I3=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[1](16) I1=divider.divider.s_pipe[1](15) I2=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.divider.d_pipe[1](16) I1=divider.divider.s_pipe[1](15) I2=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[2]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[2](16) D=divider.divider.s_pipe[2]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[1](16) I3=divider.divider.s_pipe[1](15) O=divider.divider.s_pipe[2]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](14) I3=divider.divider.d_pipe[1](15) O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](24) I2=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](14) I3=divider.divider.d_pipe[1](15) O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[2](15) D=divider.divider.s_pipe[2]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[1](24) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](13) I2=divider.divider.d_pipe[1](14) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=divider.divider.d_pipe[1](13) I1=divider.divider.s_pipe[1](12) I2=divider.divider.s_pipe[1](11) I3=divider.divider.d_pipe[1](12) O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[1](13) I2=divider.divider.d_pipe[1](14) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.d_pipe[1](13) I1=divider.divider.s_pipe[1](12) I2=divider.divider.s_pipe[1](11) I3=divider.divider.d_pipe[1](12) O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[1](14) I2=divider.divider.s_pipe[1](13) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[1](14) I2=divider.divider.s_pipe[1](13) I3=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[2]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[1](14) I3=divider.divider.d_pipe[1](15) O=divider.divider.s_pipe[2]_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[1](22) I2=divider.divider.s_pipe[1](24) I3=divider.divider.s_pipe[1](23) O=divider.divider.s_pipe[2]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110110000010
+.subckt LUT4 I0=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I1 I1=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I0 I2=divider.divider.s_pipe[2]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[1](21) O=divider.divider.s_pipe[2]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=divider.divider.s_pipe[3](24) D=divider.divider.s_pipe[3]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](23) D=divider.divider.s_pipe[3]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](14) D=divider.divider.s_pipe[3]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](13) I2=divider.divider.d_pipe[2](14) I3=divider.divider.s_pipe[3]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[3](13) D=divider.divider.s_pipe[3]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](12) I2=divider.divider.d_pipe[2](13) I3=divider.divider.s_pipe[3]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[2](12) I2=divider.divider.s_pipe[2](11) I3=divider.divider.s_pipe[2](24) O=divider.divider.s_pipe[3]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[3](12) D=divider.divider.s_pipe[3]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](11) I3=divider.divider.d_pipe[2](12) O=divider.divider.s_pipe[3]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[3](11) D=divider.divider.s_pipe[2](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](10) D=divider.divider.s_pipe[2](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](9) D=divider.divider.s_pipe[2](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](8) D=divider.divider.s_pipe[2](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](7) D=divider.divider.s_pipe[2](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](6) D=divider.divider.s_pipe[2](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](5) D=divider.divider.s_pipe[2](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2 I2=divider.divider.s_pipe[2](21) I3=divider.divider.s_pipe[2](22) O=divider.divider.s_pipe[3]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=divider.divider.s_pipe[3](22) D=divider.divider.s_pipe[3]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](4) D=divider.divider.s_pipe[2](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[3](3) D=divider.divider.s_pipe[2](2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](21) I2=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[3]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I1=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I2=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[2](20) I3=divider.divider.s_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=divider.divider.s_pipe[3](21) D=divider.divider.s_pipe[3]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I3 I1=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2 I2=divider.divider.s_pipe[2](20) I3=divider.divider.s_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001000111100
+.subckt ff CQZ=divider.divider.s_pipe[3](20) D=divider.divider.s_pipe[3]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](19) I2=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1 I2=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1 O=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[2](18) I3=divider.divider.d_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.d_pipe[2](19) I2=divider.divider.s_pipe[2](18) I3=divider.divider.s_pipe[2](24) O=divider.divider.s_pipe[3]_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000000000
+.subckt ff CQZ=divider.divider.s_pipe[3](19) D=divider.divider.s_pipe[3]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[2](24) I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](17) I2=divider.divider.d_pipe[2](18) I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](16) I2=divider.divider.d_pipe[2](17) I3=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[2](18) I3=divider.divider.s_pipe[2](17) O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.s_pipe[2](16) I2=divider.divider.d_pipe[2](17) I3=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](17) I3=divider.divider.d_pipe[2](18) O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](18) I3=divider.divider.d_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[3](18) D=divider.divider.s_pipe[3]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](17) I2=divider.divider.d_pipe[2](18) I3=divider.divider.s_pipe[3]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](16) I2=divider.divider.d_pipe[2](17) I3=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[3]_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt ff CQZ=divider.divider.s_pipe[3](17) D=divider.divider.s_pipe[3]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](16) I2=divider.divider.d_pipe[2](17) I3=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[2](16) I1=divider.divider.s_pipe[2](15) I2=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.divider.d_pipe[2](16) I1=divider.divider.s_pipe[2](15) I2=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[3]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[3](16) D=divider.divider.s_pipe[3]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[2](16) I3=divider.divider.s_pipe[2](15) O=divider.divider.s_pipe[3]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](14) I3=divider.divider.d_pipe[2](15) O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](14) I3=divider.divider.d_pipe[2](15) O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[3](15) D=divider.divider.s_pipe[3]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[2](24) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](13) I2=divider.divider.d_pipe[2](14) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=divider.divider.d_pipe[2](13) I1=divider.divider.s_pipe[2](12) I2=divider.divider.s_pipe[2](11) I3=divider.divider.d_pipe[2](12) O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](13) I2=divider.divider.d_pipe[2](14) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.d_pipe[2](13) I1=divider.divider.s_pipe[2](12) I2=divider.divider.s_pipe[2](11) I3=divider.divider.d_pipe[2](12) O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[2](14) I2=divider.divider.s_pipe[2](13) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[2](14) I2=divider.divider.s_pipe[2](13) I3=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](14) I3=divider.divider.d_pipe[2](15) O=divider.divider.s_pipe[3]_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[2](23) O=divider.divider.s_pipe[3]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.s_pipe[3]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.d_pipe[2](19) I2=divider.divider.s_pipe[2](18) I3=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[2](24) I2=divider.divider.s_pipe[2](20) I3=divider.divider.s_pipe[2](19) O=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[2](22) I3=divider.divider.s_pipe[2](21) O=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3]_ff_CQZ_2_D_LUT4_O_I2 I2=divider.divider.s_pipe[2](22) I3=divider.divider.s_pipe[2](21) O=divider.divider.s_pipe[3]_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=divider.divider.s_pipe[4](24) D=divider.divider.s_pipe[4]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[4](23) D=divider.divider.s_pipe[4]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[4](14) D=divider.divider.s_pipe[4]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](13) I2=divider.divider.d_pipe[3](14) I3=divider.divider.s_pipe[4]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I3=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 O=divider.divider.s_pipe[4]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[4](13) D=divider.divider.s_pipe[4]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](12) I2=divider.divider.d_pipe[3](13) I3=divider.divider.s_pipe[4]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[3](12) I2=divider.divider.s_pipe[3](11) I3=divider.divider.s_pipe[3](24) O=divider.divider.s_pipe[4]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[4](12) D=divider.divider.s_pipe[4]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](11) I3=divider.divider.d_pipe[3](12) O=divider.divider.s_pipe[4]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[4](11) D=divider.divider.s_pipe[3](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[4](10) D=divider.divider.s_pipe[3](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[4](9) D=divider.divider.s_pipe[3](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[4](8) D=divider.divider.s_pipe[3](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[4](7) D=divider.divider.s_pipe[3](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[4](6) D=divider.divider.s_pipe[3](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[4](5) D=divider.divider.s_pipe[3](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](22) I2=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I1 I3=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[4]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt ff CQZ=divider.divider.s_pipe[4](22) D=divider.divider.s_pipe[4]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[4](4) D=divider.divider.s_pipe[3](3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[3](21) O=divider.divider.s_pipe[4]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.d_pipe[3](19) I1=divider.divider.s_pipe[3](18) I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[3](20) I3=divider.divider.s_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[3](20) I3=divider.divider.s_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=divider.divider.s_pipe[4](21) D=divider.divider.s_pipe[4]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_4_D_LUT4_O_I3 I1=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[3](20) I3=divider.divider.s_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001000111100
+.subckt ff CQZ=divider.divider.s_pipe[4](20) D=divider.divider.s_pipe[4]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](19) I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[4]_ff_CQZ_4_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](24) I3=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I0 O=divider.divider.s_pipe[4]_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[4](19) D=divider.divider.s_pipe[4]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[3](24) I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110010100011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](17) I3=divider.divider.d_pipe[3](18) O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](17) I3=divider.divider.d_pipe[3](18) O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[3](18) I3=divider.divider.d_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](18) I3=divider.divider.d_pipe[3](19) O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[4](18) D=divider.divider.s_pipe[4]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[3](24) I3=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](16) I2=divider.divider.d_pipe[3](17) I3=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](16) I2=divider.divider.d_pipe[3](17) I3=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[3](17) I2=divider.divider.s_pipe[3](16) I3=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[3](17) I2=divider.divider.s_pipe[3](16) I3=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](17) I3=divider.divider.d_pipe[3](18) O=divider.divider.s_pipe[4]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[4](17) D=divider.divider.s_pipe[4]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](16) I2=divider.divider.d_pipe[3](17) I3=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[3](16) I1=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=divider.divider.d_pipe[3](16) I1=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I2=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt ff CQZ=divider.divider.s_pipe[4](16) D=divider.divider.s_pipe[4]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[3](16) I3=divider.divider.s_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](14) I3=divider.divider.d_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[3](14) I2=divider.divider.s_pipe[3](13) I3=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](14) I3=divider.divider.d_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](24) I2=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[3](15) I3=divider.divider.s_pipe[3](14) O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.s_pipe[3](13) I2=divider.divider.d_pipe[3](14) I3=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[3](14) I3=divider.divider.d_pipe[3](15) O=divider.divider.s_pipe[4]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=divider.divider.s_pipe[4](15) D=divider.divider.s_pipe[4]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.d_pipe[3](15) I3=divider.divider.s_pipe[3](14) O=divider.divider.s_pipe[4]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[3](14) I2=divider.divider.s_pipe[3](13) I3=divider.divider.s_pipe[3](24) O=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100000000
+.subckt LUT4 I0=divider.divider.d_pipe[3](13) I1=divider.divider.s_pipe[3](12) I2=divider.divider.s_pipe[3](11) I3=divider.divider.d_pipe[3](12) O=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.d_pipe[3](14) I2=divider.divider.s_pipe[3](13) I3=divider.divider.s_pipe[3](24) O=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=divider.divider.d_pipe[3](13) I1=divider.divider.s_pipe[3](12) I2=divider.divider.s_pipe[3](11) I3=divider.divider.d_pipe[3](12) O=divider.divider.s_pipe[4]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[3](23) I3=divider.divider.s_pipe[3](22) O=divider.divider.s_pipe[4]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110001011010
+.subckt LUT4 I0=divider.divider.s_pipe[3](19) I1=divider.divider.s_pipe[3](20) I2=divider.divider.s_pipe[3](21) I3=divider.divider.s_pipe[4]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O O=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[3](21) I2=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[4]_ff_CQZ_2_D_LUT4_O_I0 O=divider.divider.s_pipe[4]_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=divider.divider.s_pipe[5](24) D=divider.divider.s_pipe[5]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[5](23) D=divider.divider.s_pipe[5]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[5](14) D=divider.divider.s_pipe[5]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](13) I2=divider.divider.d_pipe[4](14) I3=divider.divider.s_pipe[5]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[5](13) D=divider.divider.s_pipe[5]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](12) I2=divider.divider.d_pipe[4](13) I3=divider.divider.s_pipe[5]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[4](12) I2=divider.divider.s_pipe[4](11) I3=divider.divider.s_pipe[4](24) O=divider.divider.s_pipe[5]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[5](12) D=divider.divider.s_pipe[5]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](11) I3=divider.divider.d_pipe[4](12) O=divider.divider.s_pipe[5]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[5](11) D=divider.divider.s_pipe[4](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[5](10) D=divider.divider.s_pipe[4](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[5](9) D=divider.divider.s_pipe[4](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[5](8) D=divider.divider.s_pipe[4](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[5](7) D=divider.divider.s_pipe[4](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[5](6) D=divider.divider.s_pipe[4](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[5](5) D=divider.divider.s_pipe[4](4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[4](21) I2=divider.divider.s_pipe[5]_ff_CQZ_1_D_LUT4_O_I2 I3=divider.divider.s_pipe[4](22) O=divider.divider.s_pipe[5]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[5]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[4](21) O=divider.divider.s_pipe[5]_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=divider.divider.s_pipe[5](22) D=divider.divider.s_pipe[5]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[5]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I0 I3=divider.divider.s_pipe[4](21) O=divider.divider.s_pipe[5]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](20) I3=divider.divider.s_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=divider.divider.s_pipe[5](21) D=divider.divider.s_pipe[5]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](20) I3=divider.divider.s_pipe[5]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[4](24) I1=divider.divider.s_pipe[5]_ff_CQZ_4_D_LUT4_O_I0 I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt ff CQZ=divider.divider.s_pipe[5](20) D=divider.divider.s_pipe[5]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.d_pipe[4](19) I1=divider.divider.s_pipe[4](18) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[5]_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[5](19) D=divider.divider.s_pipe[5]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[4](24) I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110010100011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](17) I3=divider.divider.d_pipe[4](18) O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](17) I3=divider.divider.d_pipe[4](18) O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[4](18) I3=divider.divider.d_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](18) I3=divider.divider.d_pipe[4](19) O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[5](18) D=divider.divider.s_pipe[5]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[4](24) I3=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](16) I2=divider.divider.d_pipe[4](17) I3=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](16) I2=divider.divider.d_pipe[4](17) I3=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[4](17) I2=divider.divider.s_pipe[4](16) I3=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[4](17) I2=divider.divider.s_pipe[4](16) I3=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](17) I3=divider.divider.d_pipe[4](18) O=divider.divider.s_pipe[5]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[5](17) D=divider.divider.s_pipe[5]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](16) I2=divider.divider.d_pipe[4](17) I3=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[4](16) I1=divider.divider.s_pipe[4](15) I2=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.divider.d_pipe[4](16) I1=divider.divider.s_pipe[4](15) I2=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[5]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[5](16) D=divider.divider.s_pipe[5]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[4](16) I3=divider.divider.s_pipe[4](15) O=divider.divider.s_pipe[5]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](14) I3=divider.divider.d_pipe[4](15) O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](24) I2=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](14) I3=divider.divider.d_pipe[4](15) O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[5](15) D=divider.divider.s_pipe[5]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[4](24) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](13) I2=divider.divider.d_pipe[4](14) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=divider.divider.d_pipe[4](13) I1=divider.divider.s_pipe[4](12) I2=divider.divider.s_pipe[4](11) I3=divider.divider.d_pipe[4](12) O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[4](13) I2=divider.divider.d_pipe[4](14) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.d_pipe[4](13) I1=divider.divider.s_pipe[4](12) I2=divider.divider.s_pipe[4](11) I3=divider.divider.d_pipe[4](12) O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[4](14) I2=divider.divider.s_pipe[4](13) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[4](14) I2=divider.divider.s_pipe[4](13) I3=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[5]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](14) I3=divider.divider.d_pipe[4](15) O=divider.divider.s_pipe[5]_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[4](23) O=divider.divider.s_pipe[5]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.s_pipe[5]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[4](19) I2=divider.divider.s_pipe[4](20) I3=divider.divider.s_pipe[4](24) O=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[4](22) I3=divider.divider.s_pipe[4](21) O=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.divider.s_pipe[4](21) I1=divider.divider.s_pipe[4](22) I2=divider.divider.s_pipe[5]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[5]_ff_CQZ_2_D_LUT4_O_I1 O=divider.divider.s_pipe[5]_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt ff CQZ=divider.divider.s_pipe[6](24) D=divider.divider.s_pipe[6]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[6](23) D=divider.divider.s_pipe[6]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[6](14) D=divider.divider.s_pipe[6]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](13) I2=divider.divider.d_pipe[5](14) I3=divider.divider.s_pipe[6]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I3=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 O=divider.divider.s_pipe[6]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[6](13) D=divider.divider.s_pipe[6]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](12) I2=divider.divider.d_pipe[5](13) I3=divider.divider.s_pipe[6]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[5](12) I2=divider.divider.s_pipe[5](11) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[6](12) D=divider.divider.s_pipe[6]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](11) I3=divider.divider.d_pipe[5](12) O=divider.divider.s_pipe[6]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[6](11) D=divider.divider.s_pipe[5](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[6](10) D=divider.divider.s_pipe[5](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[6](9) D=divider.divider.s_pipe[5](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[6](8) D=divider.divider.s_pipe[5](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[6](7) D=divider.divider.s_pipe[5](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[6](6) D=divider.divider.s_pipe[5](5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](22) I2=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I1 I3=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0 O=divider.divider.s_pipe[6]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt ff CQZ=divider.divider.s_pipe[6](22) D=divider.divider.s_pipe[6]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](21) I2=divider.divider.s_pipe[6]_ff_CQZ_2_D_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_2_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](20) I2=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I1 I3=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=divider.divider.s_pipe[6]_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O I1=divider.divider.s_pipe[5](20) I2=divider.divider.s_pipe[5](19) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=divider.divider.s_pipe[6](21) D=divider.divider.s_pipe[6]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I1 I2=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I2 I3=divider.divider.s_pipe[5](20) O=divider.divider.s_pipe[6]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](24) I3=divider.divider.s_pipe[5](19) O=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[5](19) I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O O=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt ff CQZ=divider.divider.s_pipe[6](20) D=divider.divider.s_pipe[6]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O I2=divider.divider.s_pipe[5](24) I3=divider.divider.s_pipe[5](19) O=divider.divider.s_pipe[6]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110010100011
+.subckt ff CQZ=divider.divider.s_pipe[6](19) D=divider.divider.s_pipe[6]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](18) I2=divider.divider.d_pipe[5](19) I3=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1 I2=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](17) I3=divider.divider.d_pipe[5](18) O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.divider.d_pipe[5](19) I1=divider.divider.s_pipe[5](18) I2=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1 I3=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I0 O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](17) I3=divider.divider.d_pipe[5](18) O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=divider.divider.s_pipe[6](18) D=divider.divider.s_pipe[6]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[5](24) I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](16) I2=divider.divider.d_pipe[5](17) I3=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](16) I2=divider.divider.d_pipe[5](17) I3=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[5](17) I2=divider.divider.s_pipe[5](16) I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[5](17) I2=divider.divider.s_pipe[5](16) I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.divider.d_pipe[5](19) I1=divider.divider.s_pipe[5](18) I2=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O I3=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](17) I3=divider.divider.d_pipe[5](18) O=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[6](17) D=divider.divider.s_pipe[6]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](16) I2=divider.divider.d_pipe[5](17) I3=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[5](16) I1=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=divider.divider.d_pipe[5](16) I1=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I2=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100000010
+.subckt ff CQZ=divider.divider.s_pipe[6](16) D=divider.divider.s_pipe[6]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[5](16) I3=divider.divider.s_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](14) I3=divider.divider.d_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[5](14) I2=divider.divider.s_pipe[5](13) I3=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](14) I3=divider.divider.d_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[5](24) I2=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.d_pipe[5](15) I3=divider.divider.s_pipe[5](14) O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.s_pipe[5](13) I2=divider.divider.d_pipe[5](14) I3=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[5](14) I3=divider.divider.d_pipe[5](15) O=divider.divider.s_pipe[6]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=divider.divider.s_pipe[6](15) D=divider.divider.s_pipe[6]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.d_pipe[5](15) I3=divider.divider.s_pipe[5](14) O=divider.divider.s_pipe[6]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0 I1=divider.divider.d_pipe[5](14) I2=divider.divider.s_pipe[5](13) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100000000
+.subckt LUT4 I0=divider.divider.d_pipe[5](13) I1=divider.divider.s_pipe[5](12) I2=divider.divider.s_pipe[5](11) I3=divider.divider.d_pipe[5](12) O=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0 I1=divider.divider.d_pipe[5](14) I2=divider.divider.s_pipe[5](13) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=divider.divider.d_pipe[5](13) I1=divider.divider.s_pipe[5](12) I2=divider.divider.s_pipe[5](11) I3=divider.divider.d_pipe[5](12) O=divider.divider.s_pipe[6]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[5](22) I3=divider.divider.s_pipe[5](23) O=divider.divider.s_pipe[6]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110111001010
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[6]_ff_CQZ_6_D_LUT4_O_I3_LUT4_I3_1_O_LUT4_I2_O O=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[5](20) I1=divider.divider.s_pipe[5](21) I2=divider.divider.s_pipe[5](19) I3=divider.divider.s_pipe[5](24) O=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=divider.divider.s_pipe[6]_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=divider.divider.s_pipe[6]_ff_CQZ_3_D_LUT4_O_I1 I2=divider.divider.s_pipe[5](20) I3=divider.divider.s_pipe[5](21) O=divider.divider.s_pipe[6]_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=divider.divider.s_pipe[7](24) D=divider.divider.s_pipe[7]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[7](23) D=divider.divider.s_pipe[7]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[7](14) D=divider.divider.s_pipe[7]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](13) I2=divider.divider.d_pipe[6](14) I3=divider.divider.s_pipe[7]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[7](13) D=divider.divider.s_pipe[7]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](12) I2=divider.divider.d_pipe[6](13) I3=divider.divider.s_pipe[7]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[6](12) I2=divider.divider.s_pipe[6](11) I3=divider.divider.s_pipe[6](24) O=divider.divider.s_pipe[7]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[7](12) D=divider.divider.s_pipe[7]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](11) I3=divider.divider.d_pipe[6](12) O=divider.divider.s_pipe[7]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[7](11) D=divider.divider.s_pipe[6](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[7](10) D=divider.divider.s_pipe[6](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[7](9) D=divider.divider.s_pipe[6](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[7](8) D=divider.divider.s_pipe[6](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[7](7) D=divider.divider.s_pipe[6](6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[6](21) I2=divider.divider.s_pipe[7]_ff_CQZ_1_D_LUT4_O_I2 I3=divider.divider.s_pipe[6](22) O=divider.divider.s_pipe[7]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[7]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[6](21) O=divider.divider.s_pipe[7]_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=divider.divider.s_pipe[7](22) D=divider.divider.s_pipe[7]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[7]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I0 I3=divider.divider.s_pipe[6](21) O=divider.divider.s_pipe[7]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](20) I3=divider.divider.s_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=divider.divider.s_pipe[7](21) D=divider.divider.s_pipe[7]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](20) I3=divider.divider.s_pipe[7]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[6](24) I1=divider.divider.s_pipe[7]_ff_CQZ_4_D_LUT4_O_I0 I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt ff CQZ=divider.divider.s_pipe[7](20) D=divider.divider.s_pipe[7]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.d_pipe[6](19) I1=divider.divider.s_pipe[6](18) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[7]_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[7](19) D=divider.divider.s_pipe[7]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[6](24) I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110010100011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](17) I3=divider.divider.d_pipe[6](18) O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](17) I3=divider.divider.d_pipe[6](18) O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[6](18) I3=divider.divider.d_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](18) I3=divider.divider.d_pipe[6](19) O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[7](18) D=divider.divider.s_pipe[7]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[6](24) I3=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](16) I2=divider.divider.d_pipe[6](17) I3=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](16) I2=divider.divider.d_pipe[6](17) I3=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[6](17) I2=divider.divider.s_pipe[6](16) I3=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[6](17) I2=divider.divider.s_pipe[6](16) I3=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](17) I3=divider.divider.d_pipe[6](18) O=divider.divider.s_pipe[7]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[7](17) D=divider.divider.s_pipe[7]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](16) I2=divider.divider.d_pipe[6](17) I3=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[6](16) I1=divider.divider.s_pipe[6](15) I2=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.divider.d_pipe[6](16) I1=divider.divider.s_pipe[6](15) I2=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[7]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[7](16) D=divider.divider.s_pipe[7]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[6](16) I3=divider.divider.s_pipe[6](15) O=divider.divider.s_pipe[7]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](14) I3=divider.divider.d_pipe[6](15) O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](24) I2=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](14) I3=divider.divider.d_pipe[6](15) O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[7](15) D=divider.divider.s_pipe[7]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[6](24) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](13) I2=divider.divider.d_pipe[6](14) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=divider.divider.d_pipe[6](13) I1=divider.divider.s_pipe[6](12) I2=divider.divider.s_pipe[6](11) I3=divider.divider.d_pipe[6](12) O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[6](13) I2=divider.divider.d_pipe[6](14) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.d_pipe[6](13) I1=divider.divider.s_pipe[6](12) I2=divider.divider.s_pipe[6](11) I3=divider.divider.d_pipe[6](12) O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[6](14) I2=divider.divider.s_pipe[6](13) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[6](14) I2=divider.divider.s_pipe[6](13) I3=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[7]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](14) I3=divider.divider.d_pipe[6](15) O=divider.divider.s_pipe[7]_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[6](23) O=divider.divider.s_pipe[7]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.s_pipe[7]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[6](19) I2=divider.divider.s_pipe[6](20) I3=divider.divider.s_pipe[6](24) O=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[6](22) I3=divider.divider.s_pipe[6](21) O=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.divider.s_pipe[6](21) I1=divider.divider.s_pipe[6](22) I2=divider.divider.s_pipe[7]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[7]_ff_CQZ_2_D_LUT4_O_I1 O=divider.divider.s_pipe[7]_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt ff CQZ=divider.divider.s_pipe[8](24) D=divider.divider.s_pipe[8]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[8](23) D=divider.divider.s_pipe[8]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[8](14) D=divider.divider.s_pipe[8]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](13) I2=divider.divider.d_pipe[7](14) I3=divider.divider.s_pipe[8]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[8](13) D=divider.divider.s_pipe[8]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](12) I2=divider.divider.d_pipe[7](13) I3=divider.divider.s_pipe[8]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[7](12) I2=divider.divider.s_pipe[7](11) I3=divider.divider.s_pipe[7](24) O=divider.divider.s_pipe[8]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[8](12) D=divider.divider.s_pipe[8]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](11) I3=divider.divider.d_pipe[7](12) O=divider.divider.s_pipe[8]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[8](11) D=divider.divider.s_pipe[7](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[8](10) D=divider.divider.s_pipe[7](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[8](9) D=divider.divider.s_pipe[7](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[8](8) D=divider.divider.s_pipe[7](7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[7](21) I2=divider.divider.s_pipe[8]_ff_CQZ_1_D_LUT4_O_I2 I3=divider.divider.s_pipe[7](22) O=divider.divider.s_pipe[8]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[8]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[7](21) O=divider.divider.s_pipe[8]_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=divider.divider.s_pipe[8](22) D=divider.divider.s_pipe[8]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[8]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I0 I3=divider.divider.s_pipe[7](21) O=divider.divider.s_pipe[8]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](20) I3=divider.divider.s_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=divider.divider.s_pipe[8](21) D=divider.divider.s_pipe[8]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](20) I3=divider.divider.s_pipe[8]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[7](24) I1=divider.divider.s_pipe[8]_ff_CQZ_4_D_LUT4_O_I0 I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt ff CQZ=divider.divider.s_pipe[8](20) D=divider.divider.s_pipe[8]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.d_pipe[7](19) I1=divider.divider.s_pipe[7](18) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[8]_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[8](19) D=divider.divider.s_pipe[8]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[7](24) I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110010100011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](17) I3=divider.divider.d_pipe[7](18) O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](17) I3=divider.divider.d_pipe[7](18) O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[7](18) I3=divider.divider.d_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](18) I3=divider.divider.d_pipe[7](19) O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[8](18) D=divider.divider.s_pipe[8]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[7](24) I3=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](16) I2=divider.divider.d_pipe[7](17) I3=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](16) I2=divider.divider.d_pipe[7](17) I3=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[7](17) I2=divider.divider.s_pipe[7](16) I3=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[7](17) I2=divider.divider.s_pipe[7](16) I3=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](17) I3=divider.divider.d_pipe[7](18) O=divider.divider.s_pipe[8]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[8](17) D=divider.divider.s_pipe[8]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](16) I2=divider.divider.d_pipe[7](17) I3=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[7](16) I1=divider.divider.s_pipe[7](15) I2=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.divider.d_pipe[7](16) I1=divider.divider.s_pipe[7](15) I2=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[8]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[8](16) D=divider.divider.s_pipe[8]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[7](16) I3=divider.divider.s_pipe[7](15) O=divider.divider.s_pipe[8]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](14) I3=divider.divider.d_pipe[7](15) O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](24) I2=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](14) I3=divider.divider.d_pipe[7](15) O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[8](15) D=divider.divider.s_pipe[8]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[7](24) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](13) I2=divider.divider.d_pipe[7](14) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=divider.divider.d_pipe[7](13) I1=divider.divider.s_pipe[7](12) I2=divider.divider.s_pipe[7](11) I3=divider.divider.d_pipe[7](12) O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[7](13) I2=divider.divider.d_pipe[7](14) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.d_pipe[7](13) I1=divider.divider.s_pipe[7](12) I2=divider.divider.s_pipe[7](11) I3=divider.divider.d_pipe[7](12) O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[7](14) I2=divider.divider.s_pipe[7](13) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[7](14) I2=divider.divider.s_pipe[7](13) I3=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[8]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](14) I3=divider.divider.d_pipe[7](15) O=divider.divider.s_pipe[8]_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[7](23) O=divider.divider.s_pipe[8]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.s_pipe[8]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[7](19) I2=divider.divider.s_pipe[7](20) I3=divider.divider.s_pipe[7](24) O=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[7](22) I3=divider.divider.s_pipe[7](21) O=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.divider.s_pipe[7](21) I1=divider.divider.s_pipe[7](22) I2=divider.divider.s_pipe[8]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[8]_ff_CQZ_2_D_LUT4_O_I1 O=divider.divider.s_pipe[8]_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt ff CQZ=divider.divider.s_pipe[9](24) D=divider.divider.s_pipe[9]_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[9](23) D=divider.divider.s_pipe[9]_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[9](14) D=divider.divider.s_pipe[9]_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](13) I2=divider.divider.d_pipe[8](14) I3=divider.divider.s_pipe[9]_ff_CQZ_10_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=divider.divider.s_pipe[9](13) D=divider.divider.s_pipe[9]_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](12) I2=divider.divider.d_pipe[8](13) I3=divider.divider.s_pipe[9]_ff_CQZ_11_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.d_pipe[8](12) I2=divider.divider.s_pipe[8](11) I3=divider.divider.s_pipe[8](24) O=divider.divider.s_pipe[9]_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=divider.divider.s_pipe[9](12) D=divider.divider.s_pipe[9]_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](11) I3=divider.divider.d_pipe[8](12) O=divider.divider.s_pipe[9]_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.s_pipe[9](11) D=divider.divider.s_pipe[8](10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[9](10) D=divider.divider.s_pipe[8](9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[9](9) D=divider.divider.s_pipe[8](8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[8](21) I2=divider.divider.s_pipe[9]_ff_CQZ_1_D_LUT4_O_I2 I3=divider.divider.s_pipe[8](22) O=divider.divider.s_pipe[9]_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I2=divider.divider.s_pipe[9]_ff_CQZ_2_D_LUT4_O_I1 I3=divider.divider.s_pipe[8](21) O=divider.divider.s_pipe[9]_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=divider.divider.s_pipe[9](22) D=divider.divider.s_pipe[9]_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I1=divider.divider.s_pipe[9]_ff_CQZ_2_D_LUT4_O_I1 I2=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I0 I3=divider.divider.s_pipe[8](21) O=divider.divider.s_pipe[9]_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](20) I3=divider.divider.s_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=divider.divider.s_pipe[9](21) D=divider.divider.s_pipe[9]_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](20) I3=divider.divider.s_pipe[9]_ff_CQZ_3_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[8](24) I1=divider.divider.s_pipe[9]_ff_CQZ_4_D_LUT4_O_I0 I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt ff CQZ=divider.divider.s_pipe[9](20) D=divider.divider.s_pipe[9]_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.d_pipe[8](19) I1=divider.divider.s_pipe[8](18) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[9]_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[9](19) D=divider.divider.s_pipe[9]_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1 I2=divider.divider.s_pipe[8](24) I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110010100011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](17) I3=divider.divider.d_pipe[8](18) O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](17) I3=divider.divider.d_pipe[8](18) O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[8](18) I3=divider.divider.d_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](18) I3=divider.divider.d_pipe[8](19) O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[9](18) D=divider.divider.s_pipe[9]_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I1 I2=divider.divider.s_pipe[8](24) I3=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](16) I2=divider.divider.d_pipe[8](17) I3=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](16) I2=divider.divider.d_pipe[8](17) I3=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 O=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I1=divider.divider.d_pipe[8](17) I2=divider.divider.s_pipe[8](16) I3=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 I1=divider.divider.d_pipe[8](17) I2=divider.divider.s_pipe[8](16) I3=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](17) I3=divider.divider.d_pipe[8](18) O=divider.divider.s_pipe[9]_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.divider.s_pipe[9](17) D=divider.divider.s_pipe[9]_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](16) I2=divider.divider.d_pipe[8](17) I3=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=divider.divider.d_pipe[8](16) I1=divider.divider.s_pipe[8](15) I2=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 O=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.divider.d_pipe[8](16) I1=divider.divider.s_pipe[8](15) I2=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 I3=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 O=divider.divider.s_pipe[9]_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt ff CQZ=divider.divider.s_pipe[9](16) D=divider.divider.s_pipe[9]_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1 I2=divider.divider.d_pipe[8](16) I3=divider.divider.s_pipe[8](15) O=divider.divider.s_pipe[9]_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](14) I3=divider.divider.d_pipe[8](15) O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](24) I2=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2 I3=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](14) I3=divider.divider.d_pipe[8](15) O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=divider.divider.s_pipe[9](15) D=divider.divider.s_pipe[9]_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_uu.v:153.2-156.60|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:125.2-134.3|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1 I2=divider.divider.s_pipe[8](24) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001101011100
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](13) I2=divider.divider.d_pipe[8](14) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=divider.divider.d_pipe[8](13) I1=divider.divider.s_pipe[8](12) I2=divider.divider.s_pipe[8](11) I3=divider.divider.d_pipe[8](12) O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[8](13) I2=divider.divider.d_pipe[8](14) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.divider.d_pipe[8](13) I1=divider.divider.s_pipe[8](12) I2=divider.divider.s_pipe[8](11) I3=divider.divider.d_pipe[8](12) O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I0_LUT4_O_I3 I1=divider.divider.d_pipe[8](14) I2=divider.divider.s_pipe[8](13) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I3 I1=divider.divider.d_pipe[8](14) I2=divider.divider.s_pipe[8](13) I3=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I3 O=divider.divider.s_pipe[9]_ff_CQZ_8_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](14) I3=divider.divider.d_pipe[8](15) O=divider.divider.s_pipe[9]_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I0 I1=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I1 I2=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I2 I3=divider.divider.s_pipe[8](23) O=divider.divider.s_pipe[9]_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111000
+.subckt LUT4 I0=divider.divider.s_pipe[9]_ff_CQZ_4_D_LUT4_O_I0 I1=divider.divider.s_pipe[8](19) I2=divider.divider.s_pipe[8](20) I3=divider.divider.s_pipe[8](24) O=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[8](22) I3=divider.divider.s_pipe[8](21) O=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=divider.divider.s_pipe[8](21) I1=divider.divider.s_pipe[8](22) I2=divider.divider.s_pipe[9]_ff_CQZ_5_D_LUT4_O_I3_LUT4_I2_O I3=divider.divider.s_pipe[9]_ff_CQZ_2_D_LUT4_O_I1 O=divider.divider.s_pipe[9]_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=divider.divider.d(7) I1=divider.divider.s_pipe[0](18) I2=divider.id_LUT4_I1_O I3=divider.id_LUT4_I3_1_O O=divider.id_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=divider.divider.d(1) I1=divider.divider.s_pipe[0](12) I2=divider.divider.s_pipe[0](11) I3=divider.divider.d(0) O=divider.id_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=divider.id_LUT4_I2_2_O I1=divider.divider.d(5) I2=divider.divider.s_pipe[0](16) I3=divider.id_LUT4_I3_2_O O=divider.id_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=divider.divider.s_pipe[0](11) I1=divider.divider.d(0) I2=divider.divider.d(1) I3=divider.divider.s_pipe[0](12) O=divider.divider.s_pipe[1]_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=divider.id_LUT4_I1_O I1=divider.id_LUT4_I3_1_O I2=divider.divider.d(7) I3=divider.divider.s_pipe[0](18) O=divider.divider.s_pipe[1]_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=divider.id_LUT4_I2_2_O I1=divider.divider.s_pipe[0](16) I2=divider.divider.d(5) I3=divider.id_LUT4_I3_2_O O=divider.divider.s_pipe[1]_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](15) I2=divider.divider.d(4) I3=divider.id_LUT4_I2_4_O O=divider.id_LUT4_I2_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](16) I2=divider.divider.d(5) I3=divider.id_LUT4_I2_2_O O=divider.divider.s_pipe[1]_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](14) I2=divider.divider.d(3) I3=divider.id_LUT4_I2_6_O O=divider.id_LUT4_I2_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](15) I2=divider.divider.d(4) I3=divider.id_LUT4_I2_4_O O=divider.divider.s_pipe[1]_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](13) I2=divider.divider.d(2) I3=divider.id_LUT4_I0_1_O O=divider.id_LUT4_I2_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](14) I2=divider.divider.d(3) I3=divider.id_LUT4_I2_6_O O=divider.divider.s_pipe[1]_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.s_pipe[0](13) I2=divider.divider.d(2) I3=divider.id_LUT4_I0_1_O O=divider.divider.s_pipe[1]_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[0](11) I3=divider.divider.d(0) O=divider.divider.s_pipe[1]_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[0](17) I3=divider.divider.d(6) O=divider.id_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.s_pipe[0](17) I3=divider.divider.d(6) O=divider.id_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=divider.divider.d(7) D=divider.d(7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.d(6) D=divider.d(6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.d(5) D=divider.d(5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.d(4) D=divider.d(4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.d(3) D=divider.d(3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.d(2) D=divider.d(2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.d(1) D=divider.d(1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.d(0) D=divider.d(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:100.2-102.17|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](23) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](22) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](13) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](12) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](11) D=divider.iz_ff_CQZ_12_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.iz_ff_CQZ_13_D_LUT4_O_I3 I2=divider.z(11) I3=divider.z(10) O=divider.iz_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=divider.divider.s_pipe[0](10) D=divider.iz_ff_CQZ_13_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.z(10) I2=divider.z(11) I3=divider.iz_ff_CQZ_13_D_LUT4_O_I3 O=divider.iz_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=divider.z(7) I1=divider.z(8) I2=divider.z(9) I3=divider.iz_ff_CQZ_16_D_LUT4_O_I3 O=divider.iz_ff_CQZ_13_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=divider.divider.s_pipe[0](9) D=divider.iz_ff_CQZ_14_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.z(9) I3=divider.iz_ff_CQZ_14_D_LUT4_O_I3 O=divider.iz_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=divider.z(8) I1=divider.z(7) I2=divider.iz_ff_CQZ_16_D_LUT4_O_I3 I3=divider.z(11) O=divider.iz_ff_CQZ_14_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt ff CQZ=divider.divider.s_pipe[0](8) D=divider.iz_ff_CQZ_15_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.iz_ff_CQZ_16_D_LUT4_O_I3 I1=divider.z(7) I2=divider.z(11) I3=divider.z(8) O=divider.iz_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111010000
+.subckt ff CQZ=divider.divider.s_pipe[0](7) D=divider.iz_ff_CQZ_16_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.z(7) I2=divider.z(11) I3=divider.iz_ff_CQZ_16_D_LUT4_O_I3 O=divider.iz_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=divider.z(4) I1=divider.z(5) I2=divider.z(6) I3=divider.iz_ff_CQZ_19_D_LUT4_O_I3 O=divider.iz_ff_CQZ_16_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=divider.divider.s_pipe[0](6) D=divider.iz_ff_CQZ_17_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.z(6) I3=divider.iz_ff_CQZ_17_D_LUT4_O_I3 O=divider.iz_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=divider.z(5) I1=divider.z(4) I2=divider.iz_ff_CQZ_19_D_LUT4_O_I3 I3=divider.z(11) O=divider.iz_ff_CQZ_17_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt ff CQZ=divider.divider.s_pipe[0](5) D=divider.iz_ff_CQZ_18_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.iz_ff_CQZ_19_D_LUT4_O_I3 I1=divider.z(4) I2=divider.z(11) I3=divider.z(5) O=divider.iz_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111010000
+.subckt ff CQZ=divider.divider.s_pipe[0](4) D=divider.iz_ff_CQZ_19_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.z(4) I2=divider.z(11) I3=divider.iz_ff_CQZ_19_D_LUT4_O_I3 O=divider.iz_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=divider.z(1) I1=divider.z(2) I2=divider.z(3) I3=divider.z(0) O=divider.iz_ff_CQZ_19_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=divider.divider.s_pipe[0](21) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](3) D=divider.iz_ff_CQZ_20_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.z(3) I3=divider.iz_ff_CQZ_20_D_LUT4_O_I3 O=divider.iz_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=divider.z(2) I1=divider.z(0) I2=divider.z(1) I3=divider.z(11) O=divider.iz_ff_CQZ_20_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt ff CQZ=divider.divider.s_pipe[0](2) D=divider.iz_ff_CQZ_21_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.z(1) I1=divider.z(0) I2=divider.z(11) I3=divider.z(2) O=divider.iz_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111100000
+.subckt ff CQZ=divider.divider.s_pipe[0](1) D=divider.iz_ff_CQZ_22_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.z(1) I2=divider.z(0) I3=divider.z(11) O=divider.iz_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt ff CQZ=divider.divider.s_pipe[0](0) D=divider.z(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](20) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](19) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](18) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](17) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](16) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](15) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.divider.s_pipe[0](14) D=divider.d(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:105.2-110.20|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.q(12) D=divider.q_ff_CQZ_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.q(11) D=divider.q_ff_CQZ_1_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.q(2) D=divider.q_ff_CQZ_10_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.divider.q(1) I1=divider.divider.q(0) I2=divider.spipe(13) I3=divider.divider.q(2) O=divider.q_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111100000
+.subckt ff CQZ=divider.q(1) D=divider.q_ff_CQZ_11_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.q(1) I2=divider.divider.q(0) I3=divider.spipe(13) O=divider.q_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt ff CQZ=divider.q(0) D=divider.divider.q(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.q(11) I3=divider.q_ff_CQZ_D_LUT4_O_I3 O=divider.q_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=divider.q(10) D=divider.q_ff_CQZ_2_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.q_ff_CQZ_3_D_LUT4_O_I3 I1=divider.divider.q(9) I2=divider.spipe(13) I3=divider.divider.q(10) O=divider.q_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111010000
+.subckt ff CQZ=divider.q(9) D=divider.q_ff_CQZ_3_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.q(9) I3=divider.q_ff_CQZ_3_D_LUT4_O_I3 O=divider.q_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=divider.divider.q(8) I1=divider.divider.q(7) I2=divider.q_ff_CQZ_5_D_LUT4_O_I3 I3=divider.spipe(13) O=divider.q_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011111111
+.subckt ff CQZ=divider.q(8) D=divider.q_ff_CQZ_4_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.q_ff_CQZ_5_D_LUT4_O_I3 I1=divider.divider.q(7) I2=divider.spipe(13) I3=divider.divider.q(8) O=divider.q_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111010000
+.subckt ff CQZ=divider.q(7) D=divider.q_ff_CQZ_5_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.q(7) I2=divider.spipe(13) I3=divider.q_ff_CQZ_5_D_LUT4_O_I3 O=divider.q_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=divider.divider.q(4) I1=divider.divider.q(5) I2=divider.divider.q(6) I3=divider.q_ff_CQZ_8_D_LUT4_O_I3 O=divider.q_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=divider.q(6) D=divider.q_ff_CQZ_6_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.q(6) I3=divider.q_ff_CQZ_6_D_LUT4_O_I3 O=divider.q_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=divider.divider.q(5) I1=divider.divider.q(4) I2=divider.q_ff_CQZ_8_D_LUT4_O_I3 I3=divider.spipe(13) O=divider.q_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt ff CQZ=divider.q(5) D=divider.q_ff_CQZ_7_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.q_ff_CQZ_8_D_LUT4_O_I3 I1=divider.divider.q(4) I2=divider.spipe(13) I3=divider.divider.q(5) O=divider.q_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111010000
+.subckt ff CQZ=divider.q(4) D=divider.q_ff_CQZ_8_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.divider.q(4) I2=divider.spipe(13) I3=divider.q_ff_CQZ_8_D_LUT4_O_I3 O=divider.q_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=divider.divider.q(1) I1=divider.divider.q(2) I2=divider.divider.q(3) I3=divider.divider.q(0) O=divider.q_ff_CQZ_8_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=divider.q(3) D=divider.q_ff_CQZ_9_D QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:137.2-148.9|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.divider.q(3) I3=divider.q_ff_CQZ_9_D_LUT4_O_I3 O=divider.q_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=divider.divider.q(2) I1=divider.divider.q(0) I2=divider.divider.q(1) I3=divider.spipe(13) O=divider.q_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.spipe(13) I2=divider.divider.q(11) I3=divider.q_ff_CQZ_D_LUT4_O_I3 O=divider.q_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=divider.divider.q(10) I1=divider.divider.q(9) I2=divider.q_ff_CQZ_3_D_LUT4_O_I3 I3=divider.spipe(13) O=divider.q_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011111111
+.subckt ff CQZ=divider.spipe(13) D=divider.spipe(12) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(12) D=divider.spipe(11) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(3) D=divider.spipe(2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(2) D=divider.spipe(1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(1) D=divider.spipe(0) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(0) D=divider.z(11) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(11) D=divider.spipe(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(10) D=divider.spipe(9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(9) D=divider.spipe(8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(8) D=divider.spipe(7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(7) D=divider.spipe(6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(6) D=divider.spipe(5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(5) D=divider.spipe(4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=divider.spipe(4) D=divider.spipe(3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:108.2-117.3|/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/div_su.v:114.2-121.7|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=dep(15) D=dep(14) QCK=divider.clk QEN=divider.divider.ena QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:137.2-146.10|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt LUT4 I0=dstrb_LUT4_I3_I2 I1=$iopadmap$qnt_cnt(4) I2=$iopadmap$dstrb I3=$iopadmap$qnt_cnt(5) O=dstrb_LUT4_I3_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=$iopadmap$dstrb I3=dstrb_LUT4_I2_1_I3 O=dstrb_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$qnt_cnt(0) I1=$iopadmap$qnt_cnt(1) I2=$iopadmap$qnt_cnt(2) I3=$iopadmap$qnt_cnt(3) O=dstrb_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=$iopadmap$qnt_cnt(0) I1=$iopadmap$qnt_cnt(1) I2=$iopadmap$dstrb I3=$iopadmap$qnt_cnt(2) O=dstrb_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=$iopadmap$dstrb I3=$iopadmap$qnt_cnt(0) O=dstrb_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=$iopadmap$dstrb I3=divider.divider.ena O=qnt_cnt_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=divider.d(10) I1=$iopadmap$qnt_cnt(4) I2=dstrb_LUT4_I3_I2 I3=$iopadmap$dstrb O=dstrb_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=divider.d(10) I1=$iopadmap$qnt_cnt(1) I2=$iopadmap$qnt_cnt(0) I3=$iopadmap$dstrb O=dstrb_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=$iopadmap$qnt_cnt(0) I1=$iopadmap$qnt_cnt(1) I2=$iopadmap$qnt_cnt(2) I3=$iopadmap$qnt_cnt(3) O=dstrb_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=$iopadmap$qnt_cnt(5) D=dstrb_LUT4_I3_O(5) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=$iopadmap$qnt_cnt(4) D=dstrb_LUT4_I3_O(4) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=$iopadmap$qnt_cnt(3) D=dstrb_LUT4_I3_O(3) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=$iopadmap$qnt_cnt(2) D=dstrb_LUT4_I3_O(2) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=$iopadmap$qnt_cnt(1) D=dstrb_LUT4_I3_O(1) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=$iopadmap$qnt_cnt(0) D=dstrb_LUT4_I3_O(0) QCK=divider.clk QEN=qnt_cnt_ff_CQZ_QEN QRT=rst_LUT4_I3_O QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:94.2-100.36|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:132.8-132.82"
+.subckt ff CQZ=rq(11) D=rq_ff_CQZ_D(11) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(10) D=rq_ff_CQZ_D(10) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(1) D=rq_ff_CQZ_D(1) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(9) D=rq_ff_CQZ_D(9) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(8) D=rq_ff_CQZ_D(8) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(7) D=rq_ff_CQZ_D(7) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(6) D=rq_ff_CQZ_D(6) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(5) D=rq_ff_CQZ_D(5) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(4) D=rq_ff_CQZ_D(4) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(3) D=rq_ff_CQZ_D(3) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=rq(2) D=rq_ff_CQZ_D(2) QCK=divider.clk QEN=divider.divider.ena QRT=divider.d(10) QST=divider.d(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/jpeg_qnr/rtl/jpeg_qnr.v:120.2-128.21|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=divider.q(12) I1=rq_ff_CQZ_D_LUT4_O_I1 I2=rq_ff_CQZ_D_LUT4_O_I2 I3=divider.q(11) O=rq_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O I1=rq_ff_CQZ_D_LUT4_O_I2 I2=divider.q(9) I3=divider.q(10) O=rq_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=divider.d(10) I1=divider.q(1) I2=divider.q(0) I3=divider.q(12) O=rq_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=divider.d(10) I1=divider.q(9) I2=rq_ff_CQZ_D_LUT4_O_I2 I3=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O O=rq_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.q(8) I3=rq_ff_CQZ_D_LUT4_O_3_I3 O=rq_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O I1=divider.q(5) I2=divider.q(6) I3=divider.q(7) O=rq_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O I1=divider.q(5) I2=divider.q(6) I3=divider.q(7) O=rq_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=divider.d(10) I1=divider.q(6) I2=divider.q(5) I3=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O O=rq_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.q(5) I3=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O O=rq_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=divider.d(10) I1=divider.q(4) I2=divider.q(3) I3=rq_ff_CQZ_D_LUT4_O_8_I3 O=rq_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.q(3) I3=rq_ff_CQZ_D_LUT4_O_8_I3 O=rq_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=divider.d(10) I1=divider.q(4) I2=divider.q(3) I3=rq_ff_CQZ_D_LUT4_O_8_I3 O=rq_ff_CQZ_D_LUT4_O_8_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=divider.q(12) I1=divider.q(1) I2=divider.q(2) I3=divider.q(0) O=rq_ff_CQZ_D_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=divider.q(12) I1=divider.q(1) I2=divider.q(0) I3=divider.q(2) O=rq_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=rq_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=divider.q(4) I2=divider.q(9) I3=divider.q(10) O=rq_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=divider.q(3) I1=divider.q(2) I2=divider.q(1) I3=divider.q(0) O=rq_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=divider.q(5) I1=divider.q(6) I2=divider.q(7) I3=divider.q(8) O=rq_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=divider.d(10) I1=divider.d(10) I2=divider.d(10) I3=$iopadmap$rst O=rst_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.end
diff --git a/BENCHMARK/jpeg_qnr/rtl/div_su.v b/BENCHMARK/jpeg_qnr/rtl/div_su.v
new file mode 100644
index 0000000..93c0d62
--- /dev/null
+++ b/BENCHMARK/jpeg_qnr/rtl/div_su.v
@@ -0,0 +1,157 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Non-restoring signed by unsigned divider                   ////
+////  Uses the non-restoring unsigned by unsigned divider        ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: div_su.v,v 1.3 2002-10-31 12:52:54 rherveille Exp $
+//
+//  $Date: 2002-10-31 12:52:54 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.2  2002/10/23 09:07:03  rherveille
+//               Improved many files.
+//               Fixed some bugs in Run-Length-Encoder.
+//               Removed dependency on ud_cnt and ro_cnt.
+//               Started (Motion)JPEG hardware encoder project.
+//
+
+//synopsys translate_off
+`include "timescale.v"
+//synopsys translate_on
+
+module div_su(clk, ena, z, d, q, s, div0, ovf);
+
+	//
+	// parameters
+	//
+	parameter z_width = 16;
+	parameter d_width = z_width /2;
+	
+	//
+	// inputs & outputs
+	//
+	input clk;              // system clock
+	input ena;              // clock enable
+
+	input  [z_width-1:0] z; // divident
+	input  [d_width-1:0] d; // divisor
+	output [d_width  :0] q; // quotient
+	output [d_width-1:0] s; // remainder
+	output div0;
+	output ovf;
+
+	reg [d_width :0] q;
+	reg [d_width-1:0] s;
+	reg div0;
+	reg ovf;
+
+	//
+	// variables
+	//
+	reg [z_width -1:0] iz;
+	reg [d_width -1:0] id;
+	reg [d_width +1:0] spipe;
+
+	wire [d_width -1:0] iq, is;
+	wire                idiv0, iovf;
+
+	//
+	// module body
+	//
+
+	// delay d
+	always @(posedge clk)
+	  if (ena)
+	    id <= #1 d;
+
+	// check z, take abs value
+	always @(posedge clk)
+	  if (ena)
+	    if (z[z_width-1])
+	       iz <= #1 ~z +1'h1;
+	    else
+	       iz <= #1 z;
+
+	// generate spipe (sign bit pipe)
+	integer n;
+	always @(posedge clk)
+	  if(ena)
+	  begin
+	      spipe[0] <= #1 z[z_width-1];
+
+	      for(n=1; n <= d_width+1; n=n+1)
+	         spipe[n] <= #1 spipe[n-1];
+	  end
+
+	// hookup non-restoring divider
+	div_uu #(z_width, d_width)
+	divider (
+		.clk(clk),
+		.ena(ena),
+		.z(iz),
+		.d(id),
+		.q(iq),
+		.s(is),
+		.div0(idiv0),
+		.ovf(iovf)
+	);
+
+	// correct divider results if 'd' was negative
+	always @(posedge clk)
+	  if(ena)
+	    if(spipe[d_width+1])
+	    begin
+	        q <= #1 (~iq) + 1'h1;
+	        s <= #1 (~is) + 1'h1;
+	    end
+	    else
+	    begin
+	        q <= #1 {1'b0, iq};
+	        s <= #1 {1'b0, is};
+	    end
+
+	// delay flags same as results
+	always @(posedge clk)
+	  if(ena)
+	  begin
+	      div0 <= #1 idiv0;
+	      ovf  <= #1 iovf;
+	  end
+endmodule
diff --git a/BENCHMARK/jpeg_qnr/rtl/div_uu.v b/BENCHMARK/jpeg_qnr/rtl/div_uu.v
new file mode 100644
index 0000000..1ee72c3
--- /dev/null
+++ b/BENCHMARK/jpeg_qnr/rtl/div_uu.v
@@ -0,0 +1,202 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Non-restoring unsinged divider                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: div_uu.v,v 1.3 2002-10-31 12:52:55 rherveille Exp $
+//
+//  $Date: 2002-10-31 12:52:55 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.2  2002/10/23 09:07:03  rherveille
+//               Improved many files.
+//               Fixed some bugs in Run-Length-Encoder.
+//               Removed dependency on ud_cnt and ro_cnt.
+//               Started (Motion)JPEG hardware encoder project.
+//
+
+//synopsys translate_off
+`include "timescale.v"
+//synopsys translate_on
+
+module div_uu(clk, ena, z, d, q, s, div0, ovf);
+
+	//
+	// parameters
+	//
+	parameter z_width = 16;
+	parameter d_width = z_width /2;
+	
+	//
+	// inputs & outputs
+	//
+	input clk;               // system clock
+	input ena;               // clock enable
+
+	input  [z_width -1:0] z; // divident
+	input  [d_width -1:0] d; // divisor
+	output [d_width -1:0] q; // quotient
+	reg [d_width-1:0] q;
+	output [d_width -1:0] s; // remainder
+	reg [d_width-1:0] s;
+	output div0;
+	reg div0;
+	output ovf;
+	reg ovf;
+
+	//	
+	// functions
+	//
+	function [z_width:0] gen_s;
+		input [z_width:0] si;
+		input [z_width:0] di;
+	begin
+	  if(si[z_width])
+	    gen_s = {si[z_width-1:0], 1'b0} + di;
+	  else
+	    gen_s = {si[z_width-1:0], 1'b0} - di;
+	end
+	endfunction
+
+	function [d_width-1:0] gen_q;
+		input [d_width-1:0] qi;
+		input [z_width:0] si;
+	begin
+	  gen_q = {qi[d_width-2:0], ~si[z_width]};
+	end
+	endfunction
+
+	function [d_width-1:0] assign_s;
+		input [z_width:0] si;
+		input [z_width:0] di;
+		reg [z_width:0] tmp;
+	begin
+	  if(si[z_width])
+	    tmp = si + di;
+	  else
+	    tmp = si;
+
+	  assign_s = tmp[z_width-1:z_width-4];
+	end
+	endfunction
+
+	//
+	// variables
+	//
+	reg [d_width-1:0] q_pipe  [d_width-1:0];
+	reg [z_width:0] s_pipe  [d_width:0];
+	reg [z_width:0] d_pipe  [d_width:0];
+
+	reg [d_width:0] div0_pipe, ovf_pipe;
+	//
+	// perform parameter checks
+	//
+	// synopsys translate_off
+	initial
+	begin
+	  if(d_width !== z_width / 2)
+	    $display("div.v parameter error (d_width != z_width/2).");
+	end
+	// synopsys translate_on
+
+	integer n0, n1, n2, n3;
+
+	// generate divisor (d) pipe
+	always @(d)
+	  d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
+
+	always @(posedge clk)
+	  if(ena)
+	    for(n0=1; n0 <= d_width; n0=n0+1)
+	       d_pipe[n0] <= #1 d_pipe[n0-1];
+
+	// generate internal remainder pipe
+	always @(z)
+	  s_pipe[0] <= z;
+
+	always @(posedge clk)
+	  if(ena)
+	    for(n1=1; n1 <= d_width; n1=n1+1)
+	       s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
+
+	// generate quotient pipe
+	always @(posedge clk)
+	  q_pipe[0] <= #1 0;
+
+	always @(posedge clk)
+	  if(ena)
+	    for(n2=1; n2 < d_width; n2=n2+1)
+	       q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
+
+
+	// flags (divide_by_zero, overflow)
+	always @(z or d)
+	begin
+	  ovf_pipe[0]  <= !(z[z_width-1:d_width] < d);
+	  div0_pipe[0] <= ~|d;
+	end
+
+	always @(posedge clk)
+	  if(ena)
+	    for(n3=1; n3 <= d_width; n3=n3+1)
+	    begin
+	        ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
+	        div0_pipe[n3] <= #1 div0_pipe[n3-1];
+	    end
+
+	// assign outputs
+	always @(posedge clk)
+	  if(ena)
+	    ovf <= #1 ovf_pipe[d_width];
+
+	always @(posedge clk)
+	  if(ena)
+	    div0 <= #1 div0_pipe[d_width];
+
+	always @(posedge clk)
+	  if(ena)
+	    q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
+
+	always @(posedge clk)
+	  if(ena)
+	    s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
+endmodule
+
+
+
diff --git a/BENCHMARK/jpeg_qnr/rtl/jpeg_qnr.v b/BENCHMARK/jpeg_qnr/rtl/jpeg_qnr.v
new file mode 100644
index 0000000..f7f9200
--- /dev/null
+++ b/BENCHMARK/jpeg_qnr/rtl/jpeg_qnr.v
@@ -0,0 +1,149 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  JPEG Quantization & Rounding Core                          ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: jpeg_qnr.v,v 1.3 2002-10-31 12:52:55 rherveille Exp $
+//
+//  $Date: 2002-10-31 12:52:55 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.2  2002/10/23 09:07:03  rherveille
+//               Improved many files.
+//               Fixed some bugs in Run-Length-Encoder.
+//               Removed dependency on ud_cnt and ro_cnt.
+//               Started (Motion)JPEG hardware encoder project.
+//
+
+//synopsys translate_off
+`include "timescale.v"
+//synopsys translate_on
+
+module jpeg_qnr(clk, ena, rst, dstrb, din, qnt_val, qnt_cnt, dout, douten);
+
+	//
+	// parameters
+	//
+	parameter d_width = 12;
+	parameter z_width = 2 * d_width;
+
+	//
+	// inputs & outputs
+	//
+	input clk;                    // system clock
+	input ena;                    // clock enable
+	input rst;                    // asynchronous active low reset
+
+	input                dstrb;   // present dstrb 1clk cycle before din
+	input  [d_width-1:0] din;     // data input
+	input  [ 7:0]        qnt_val; // quantization value
+
+	output [ 5:0]        qnt_cnt; // sample number (get quantization value qnt_cnt)
+	output [10:0]        dout;    // data output
+	output               douten;
+
+	//
+	// variables
+	//
+	wire [z_width-1:0] iz; // intermediate divident value
+	wire [d_width-1:0] id; // intermediate dividor value
+	wire [d_width  :0] iq; // intermediate result divider
+	reg  [d_width  :0] rq; // rounded q-value
+	reg  [d_width+3:0] dep;// data enable pipeline
+
+	// generate sample counter
+	reg  [5:0] qnt_cnt;
+	wire       dcnt     = &qnt_cnt;
+
+	always @(posedge clk or negedge rst)
+	  if (~rst)
+	     qnt_cnt <= #1 6'h0;
+	  else if (dstrb)
+	     qnt_cnt <= #1 6'h0;
+	  else if (ena)
+	     qnt_cnt <= #1 qnt_cnt + 6'h1;
+
+	// generate intermediate dividor/divident values
+	assign id = { {(d_width - 8){1'b0}}, qnt_val};
+	assign iz = { {(z_width - d_width){din[d_width-1]}}, din};
+
+	// hookup division unit
+	div_su #(z_width)
+	divider (
+		.clk(clk),
+		.ena(ena),
+		.z(iz),
+		.d(id),
+		.q(iq),
+		.s(),
+		.div0(),
+		.ovf()
+	);
+
+	// round result to the nearest integer
+	always @(posedge clk)
+	  if (ena)
+	    if (iq[0])
+	      if (iq[d_width])
+	         rq <= #1 iq - 1'h1;
+	      else
+	         rq <= #1 iq + 1'h1;
+	    else
+	       rq <= #1 iq;
+
+	// assign dout signal
+	assign dout = rq[d_width -1: d_width-11];
+
+
+	// generate data-out enable signal
+	// This is a pipeline, data is not dependant on sample-count
+	integer n;
+	always @(posedge clk or negedge rst)
+	  if (!rst)
+	     dep <= #1 0;
+	  else if(ena)
+	     begin
+	         dep[0] <= #1 dstrb;
+
+	         for (n=1; n <= d_width +3; n = n +1)
+	             dep[n] <= #1 dep[n-1];
+	     end
+
+	assign douten = dep[d_width +3];
+endmodule
diff --git a/BENCHMARK/multi_enc_decx2x4/multi_enc_decx2x4_yosys.blif b/BENCHMARK/multi_enc_decx2x4/multi_enc_decx2x4_yosys.blif
new file mode 100644
index 0000000..53eb701
--- /dev/null
+++ b/BENCHMARK/multi_enc_decx2x4/multi_enc_decx2x4_yosys.blif
@@ -0,0 +1,22985 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model multi_enc_decx2x4
+.inputs clock datain(0) datain(1) datain(2) datain(3) datain(4) datain(5) datain(6) datain(7) datain(8) datain(9) datain(10) datain(11) datain(12) datain(13) datain(14) datain(15) datain(16) datain(17) datain(18) datain(19) datain(20) datain(21) datain(22) datain(23) datain(24) datain(25) datain(26) datain(27) datain(28) datain(29) datain(30) datain(31) datain(32) datain(33) datain(34) datain(35) datain(36) datain(37) datain(38) datain(39) datain(40) datain(41) datain(42) datain(43) datain(44) datain(45) datain(46) datain(47) datain(48) datain(49) datain(50) datain(51) datain(52) datain(53) datain(54) datain(55) datain(56) datain(57) datain(58) datain(59) datain(60) datain(61) datain(62) datain(63) datain(64) datain(65) datain(66) datain(67) datain(68) datain(69) datain(70) datain(71) datain(72) datain(73) datain(74) datain(75) datain(76) datain(77) datain(78) datain(79) datain(80) datain(81) datain(82) datain(83) datain(84) datain(85) datain(86) datain(87) datain(88) datain(89) datain(90) datain(91) datain(92) datain(93) datain(94) datain(95) datain(96) datain(97) datain(98) datain(99) datain(100) datain(101) datain(102) datain(103) datain(104) datain(105) datain(106) datain(107) datain(108) datain(109) datain(110) datain(111) datain(112) datain(113) datain(114) datain(115) datain(116) datain(117) datain(118) datain(119) datain(120) datain(121) datain(122) datain(123) datain(124) datain(125) datain(126) datain(127) datain1(0) datain1(1) datain1(2) datain1(3) datain1(4) datain1(5) datain1(6) datain1(7) datain1(8) datain1(9) datain1(10) datain1(11) datain1(12) datain1(13) datain1(14) datain1(15) datain1(16) datain1(17) datain1(18) datain1(19) datain1(20) datain1(21) datain1(22) datain1(23) datain1(24) datain1(25) datain1(26) datain1(27) datain1(28) datain1(29) datain1(30) datain1(31) datain1(32) datain1(33) datain1(34) datain1(35) datain1(36) datain1(37) datain1(38) datain1(39) datain1(40) datain1(41) datain1(42) datain1(43) datain1(44) datain1(45) datain1(46) datain1(47) datain1(48) datain1(49) datain1(50) datain1(51) datain1(52) datain1(53) datain1(54) datain1(55) datain1(56) datain1(57) datain1(58) datain1(59) datain1(60) datain1(61) datain1(62) datain1(63) datain1(64) datain1(65) datain1(66) datain1(67) datain1(68) datain1(69) datain1(70) datain1(71) datain1(72) datain1(73) datain1(74) datain1(75) datain1(76) datain1(77) datain1(78) datain1(79) datain1(80) datain1(81) datain1(82) datain1(83) datain1(84) datain1(85) datain1(86) datain1(87) datain1(88) datain1(89) datain1(90) datain1(91) datain1(92) datain1(93) datain1(94) datain1(95) datain1(96) datain1(97) datain1(98) datain1(99) datain1(100) datain1(101) datain1(102) datain1(103) datain1(104) datain1(105) datain1(106) datain1(107) datain1(108) datain1(109) datain1(110) datain1(111) datain1(112) datain1(113) datain1(114) datain1(115) datain1(116) datain1(117) datain1(118) datain1(119) datain1(120) datain1(121) datain1(122) datain1(123) datain1(124) datain1(125) datain1(126) datain1(127) datain1_0(0) datain1_0(1) datain1_0(2) datain1_0(3) datain1_0(4) datain1_0(5) datain1_0(6) datain1_0(7) datain1_0(8) datain1_0(9) datain1_0(10) datain1_0(11) datain1_0(12) datain1_0(13) datain1_0(14) datain1_0(15) datain1_0(16) datain1_0(17) datain1_0(18) datain1_0(19) datain1_0(20) datain1_0(21) datain1_0(22) datain1_0(23) datain1_0(24) datain1_0(25) datain1_0(26) datain1_0(27) datain1_0(28) datain1_0(29) datain1_0(30) datain1_0(31) datain1_0(32) datain1_0(33) datain1_0(34) datain1_0(35) datain1_0(36) datain1_0(37) datain1_0(38) datain1_0(39) datain1_0(40) datain1_0(41) datain1_0(42) datain1_0(43) datain1_0(44) datain1_0(45) datain1_0(46) datain1_0(47) datain1_0(48) datain1_0(49) datain1_0(50) datain1_0(51) datain1_0(52) datain1_0(53) datain1_0(54) datain1_0(55) datain1_0(56) datain1_0(57) datain1_0(58) datain1_0(59) datain1_0(60) datain1_0(61) datain1_0(62) datain1_0(63) datain1_0(64) datain1_0(65) datain1_0(66) datain1_0(67) datain1_0(68) datain1_0(69) datain1_0(70) datain1_0(71) datain1_0(72) datain1_0(73) datain1_0(74) datain1_0(75) datain1_0(76) datain1_0(77) datain1_0(78) datain1_0(79) datain1_0(80) datain1_0(81) datain1_0(82) datain1_0(83) datain1_0(84) datain1_0(85) datain1_0(86) datain1_0(87) datain1_0(88) datain1_0(89) datain1_0(90) datain1_0(91) datain1_0(92) datain1_0(93) datain1_0(94) datain1_0(95) datain1_0(96) datain1_0(97) datain1_0(98) datain1_0(99) datain1_0(100) datain1_0(101) datain1_0(102) datain1_0(103) datain1_0(104) datain1_0(105) datain1_0(106) datain1_0(107) datain1_0(108) datain1_0(109) datain1_0(110) datain1_0(111) datain1_0(112) datain1_0(113) datain1_0(114) datain1_0(115) datain1_0(116) datain1_0(117) datain1_0(118) datain1_0(119) datain1_0(120) datain1_0(121) datain1_0(122) datain1_0(123) datain1_0(124) datain1_0(125) datain1_0(126) datain1_0(127) datain_0(0) datain_0(1) datain_0(2) datain_0(3) datain_0(4) datain_0(5) datain_0(6) datain_0(7) datain_0(8) datain_0(9) datain_0(10) datain_0(11) datain_0(12) datain_0(13) datain_0(14) datain_0(15) datain_0(16) datain_0(17) datain_0(18) datain_0(19) datain_0(20) datain_0(21) datain_0(22) datain_0(23) datain_0(24) datain_0(25) datain_0(26) datain_0(27) datain_0(28) datain_0(29) datain_0(30) datain_0(31) datain_0(32) datain_0(33) datain_0(34) datain_0(35) datain_0(36) datain_0(37) datain_0(38) datain_0(39) datain_0(40) datain_0(41) datain_0(42) datain_0(43) datain_0(44) datain_0(45) datain_0(46) datain_0(47) datain_0(48) datain_0(49) datain_0(50) datain_0(51) datain_0(52) datain_0(53) datain_0(54) datain_0(55) datain_0(56) datain_0(57) datain_0(58) datain_0(59) datain_0(60) datain_0(61) datain_0(62) datain_0(63) datain_0(64) datain_0(65) datain_0(66) datain_0(67) datain_0(68) datain_0(69) datain_0(70) datain_0(71) datain_0(72) datain_0(73) datain_0(74) datain_0(75) datain_0(76) datain_0(77) datain_0(78) datain_0(79) datain_0(80) datain_0(81) datain_0(82) datain_0(83) datain_0(84) datain_0(85) datain_0(86) datain_0(87) datain_0(88) datain_0(89) datain_0(90) datain_0(91) datain_0(92) datain_0(93) datain_0(94) datain_0(95) datain_0(96) datain_0(97) datain_0(98) datain_0(99) datain_0(100) datain_0(101) datain_0(102) datain_0(103) datain_0(104) datain_0(105) datain_0(106) datain_0(107) datain_0(108) datain_0(109) datain_0(110) datain_0(111) datain_0(112) datain_0(113) datain_0(114) datain_0(115) datain_0(116) datain_0(117) datain_0(118) datain_0(119) datain_0(120) datain_0(121) datain_0(122) datain_0(123) datain_0(124) datain_0(125) datain_0(126) datain_0(127) reset
+.outputs dataout(0) dataout(1) dataout(2) dataout(3) dataout(4) dataout(5) dataout(6) dataout(7) dataout(8) dataout(9) dataout(10) dataout(11) dataout(12) dataout(13) dataout(14) dataout(15) dataout(16) dataout(17) dataout(18) dataout(19) dataout(20) dataout(21) dataout(22) dataout(23) dataout(24) dataout(25) dataout(26) dataout(27) dataout(28) dataout(29) dataout(30) dataout(31) dataout(32) dataout(33) dataout(34) dataout(35) dataout(36) dataout(37) dataout(38) dataout(39) dataout(40) dataout(41) dataout(42) dataout(43) dataout(44) dataout(45) dataout(46) dataout(47) dataout(48) dataout(49) dataout(50) dataout(51) dataout(52) dataout(53) dataout(54) dataout(55) dataout(56) dataout(57) dataout(58) dataout(59) dataout(60) dataout(61) dataout(62) dataout(63) dataout(64) dataout(65) dataout(66) dataout(67) dataout(68) dataout(69) dataout(70) dataout(71) dataout(72) dataout(73) dataout(74) dataout(75) dataout(76) dataout(77) dataout(78) dataout(79) dataout(80) dataout(81) dataout(82) dataout(83) dataout(84) dataout(85) dataout(86) dataout(87) dataout(88) dataout(89) dataout(90) dataout(91) dataout(92) dataout(93) dataout(94) dataout(95) dataout(96) dataout(97) dataout(98) dataout(99) dataout(100) dataout(101) dataout(102) dataout(103) dataout(104) dataout(105) dataout(106) dataout(107) dataout(108) dataout(109) dataout(110) dataout(111) dataout(112) dataout(113) dataout(114) dataout(115) dataout(116) dataout(117) dataout(118) dataout(119) dataout(120) dataout(121) dataout(122) dataout(123) dataout(124) dataout(125) dataout(126) dataout(127) dataout1(0) dataout1(1) dataout1(2) dataout1(3) dataout1(4) dataout1(5) dataout1(6) dataout1(7) dataout1(8) dataout1(9) dataout1(10) dataout1(11) dataout1(12) dataout1(13) dataout1(14) dataout1(15) dataout1(16) dataout1(17) dataout1(18) dataout1(19) dataout1(20) dataout1(21) dataout1(22) dataout1(23) dataout1(24) dataout1(25) dataout1(26) dataout1(27) dataout1(28) dataout1(29) dataout1(30) dataout1(31) dataout1(32) dataout1(33) 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dataout1(110) dataout1(111) dataout1(112) dataout1(113) dataout1(114) dataout1(115) dataout1(116) dataout1(117) dataout1(118) dataout1(119) dataout1(120) dataout1(121) dataout1(122) dataout1(123) dataout1(124) dataout1(125) dataout1(126) dataout1(127) dataout1_0(0) dataout1_0(1) dataout1_0(2) dataout1_0(3) dataout1_0(4) dataout1_0(5) dataout1_0(6) dataout1_0(7) dataout1_0(8) dataout1_0(9) dataout1_0(10) dataout1_0(11) dataout1_0(12) dataout1_0(13) dataout1_0(14) dataout1_0(15) dataout1_0(16) dataout1_0(17) dataout1_0(18) dataout1_0(19) dataout1_0(20) dataout1_0(21) dataout1_0(22) dataout1_0(23) dataout1_0(24) dataout1_0(25) dataout1_0(26) dataout1_0(27) dataout1_0(28) dataout1_0(29) dataout1_0(30) dataout1_0(31) dataout1_0(32) dataout1_0(33) dataout1_0(34) dataout1_0(35) dataout1_0(36) dataout1_0(37) dataout1_0(38) dataout1_0(39) dataout1_0(40) dataout1_0(41) dataout1_0(42) dataout1_0(43) dataout1_0(44) dataout1_0(45) dataout1_0(46) dataout1_0(47) dataout1_0(48) dataout1_0(49) dataout1_0(50) dataout1_0(51) dataout1_0(52) dataout1_0(53) dataout1_0(54) dataout1_0(55) dataout1_0(56) dataout1_0(57) dataout1_0(58) dataout1_0(59) dataout1_0(60) dataout1_0(61) dataout1_0(62) dataout1_0(63) dataout1_0(64) dataout1_0(65) dataout1_0(66) dataout1_0(67) dataout1_0(68) dataout1_0(69) dataout1_0(70) dataout1_0(71) dataout1_0(72) dataout1_0(73) dataout1_0(74) dataout1_0(75) dataout1_0(76) dataout1_0(77) dataout1_0(78) dataout1_0(79) dataout1_0(80) dataout1_0(81) dataout1_0(82) dataout1_0(83) dataout1_0(84) dataout1_0(85) dataout1_0(86) dataout1_0(87) dataout1_0(88) dataout1_0(89) dataout1_0(90) dataout1_0(91) dataout1_0(92) dataout1_0(93) dataout1_0(94) dataout1_0(95) dataout1_0(96) dataout1_0(97) dataout1_0(98) dataout1_0(99) dataout1_0(100) dataout1_0(101) dataout1_0(102) dataout1_0(103) dataout1_0(104) dataout1_0(105) dataout1_0(106) dataout1_0(107) dataout1_0(108) dataout1_0(109) dataout1_0(110) dataout1_0(111) dataout1_0(112) dataout1_0(113) dataout1_0(114) dataout1_0(115) dataout1_0(116) dataout1_0(117) dataout1_0(118) dataout1_0(119) dataout1_0(120) dataout1_0(121) dataout1_0(122) dataout1_0(123) dataout1_0(124) dataout1_0(125) dataout1_0(126) dataout1_0(127) dataout_0(0) dataout_0(1) dataout_0(2) dataout_0(3) dataout_0(4) dataout_0(5) dataout_0(6) dataout_0(7) dataout_0(8) dataout_0(9) dataout_0(10) dataout_0(11) dataout_0(12) dataout_0(13) dataout_0(14) dataout_0(15) dataout_0(16) dataout_0(17) dataout_0(18) dataout_0(19) dataout_0(20) dataout_0(21) dataout_0(22) dataout_0(23) dataout_0(24) dataout_0(25) dataout_0(26) dataout_0(27) dataout_0(28) dataout_0(29) dataout_0(30) dataout_0(31) dataout_0(32) dataout_0(33) dataout_0(34) dataout_0(35) dataout_0(36) dataout_0(37) dataout_0(38) dataout_0(39) dataout_0(40) dataout_0(41) dataout_0(42) dataout_0(43) dataout_0(44) dataout_0(45) dataout_0(46) dataout_0(47) dataout_0(48) dataout_0(49) dataout_0(50) dataout_0(51) dataout_0(52) dataout_0(53) dataout_0(54) dataout_0(55) dataout_0(56) dataout_0(57) dataout_0(58) dataout_0(59) dataout_0(60) dataout_0(61) dataout_0(62) dataout_0(63) dataout_0(64) dataout_0(65) dataout_0(66) dataout_0(67) dataout_0(68) dataout_0(69) dataout_0(70) dataout_0(71) dataout_0(72) dataout_0(73) dataout_0(74) dataout_0(75) dataout_0(76) dataout_0(77) dataout_0(78) dataout_0(79) dataout_0(80) dataout_0(81) dataout_0(82) dataout_0(83) dataout_0(84) dataout_0(85) dataout_0(86) dataout_0(87) dataout_0(88) dataout_0(89) dataout_0(90) dataout_0(91) dataout_0(92) dataout_0(93) dataout_0(94) dataout_0(95) dataout_0(96) dataout_0(97) dataout_0(98) dataout_0(99) dataout_0(100) dataout_0(101) dataout_0(102) dataout_0(103) dataout_0(104) dataout_0(105) dataout_0(106) dataout_0(107) dataout_0(108) dataout_0(109) dataout_0(110) dataout_0(111) dataout_0(112) dataout_0(113) dataout_0(114) dataout_0(115) dataout_0(116) dataout_0(117) dataout_0(118) dataout_0(119) dataout_0(120) dataout_0(121) dataout_0(122) dataout_0(123) dataout_0(124) dataout_0(125) dataout_0(126) dataout_0(127)
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_1 a=$auto$hilomap.cc:39:hilomap_worker$237633
+.subckt logic_0 a=dataout1_0_net_0(108)
+.subckt in_buff A=clock Q=top_0.clock
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain(0) Q=top_0.datain(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1(0) Q=top_0.datain1(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(0) Q=top_1.datain1(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(1) Q=top_1.datain1(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(10) Q=top_1.datain1(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(100) Q=top_1.datain1(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(101) Q=top_1.datain1(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(102) Q=top_1.datain1(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(103) Q=top_1.datain1(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(104) Q=top_1.datain1(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(105) Q=top_1.datain1(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(106) Q=top_1.datain1(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(107) Q=top_1.datain1(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(108) Q=top_1.datain1(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(109) Q=top_1.datain1(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(11) Q=top_1.datain1(11)
+.attr module_not_derived 00000000000000000000000000000001
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+.subckt in_buff A=datain1_0(110) Q=top_1.datain1(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(111) Q=top_1.datain1(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(112) Q=top_1.datain1(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=datain1_0(113) Q=top_1.datain1(113)
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+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_67_I3 O=dataout1_0_net_0(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(65)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_9_I3 O=dataout1_0_net_0(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_6_I2 O=dataout1_0_net_0(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_91_I3 O=dataout1_0_net_0(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_9_I3 O=dataout1_0_net_0(123)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(126)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_75_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(81)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(94)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_98_I2 O=dataout1_0_net_0(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_6_I2 O=dataout1_0_net_0(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_99_I3 O=dataout1_0_net_0(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_89_I2 O=dataout1_0_net_0(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(71)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_67_I3 O=dataout1_0_net_0(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_93_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_91_I3 O=dataout1_0_net_0(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(96)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_9_I2 O=dataout1_0_net_0(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(64)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_3_I2 O=dataout1_0_net_0(116)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(84)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_99_I3 O=dataout1_0_net_0(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_6_I2 O=dataout1_0_net_0(120)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_3_I2 O=dataout1_0_net_0(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_9_I2 O=dataout1_0_net_0(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(68)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_99_I3 O=dataout1_0_net_0(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(70)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(66)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_7_I2 O=dataout1_0_net_0(117)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(75)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(73)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_67_I3 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(74)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(86)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_93_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_67_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(6) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(127)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(98)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(72)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_89_I2 O=dataout1_0_net_0(114)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_94_I3 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(62)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_67_I3 O=dataout1_0_net_0(122)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(5) I2=top_0.data_encout1(6) I3=top_0.data_encout1(4) O=dataout1_0_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(93)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(97)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_67_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(90)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(67)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_95_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(89)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_94_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_75_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_87_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(95)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_70_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_67_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(88)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_91_I3 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_61_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_61_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(91)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_67_I3 O=dataout1_0_net_0(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(0) I1=top_0.data_encout1(2) I2=top_0.data_encout1(1) I3=top_0.data_encout1(3) O=dataout1_0_LUT4_O_67_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(79)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_93_I3 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(83)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(0) I2=top_0.data_encout1(2) I3=top_0.data_encout1(3) O=dataout1_0_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(85)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I3 I3=dataout1_0_LUT4_O_70_I3 O=dataout1_0_net_0(78)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(0) I1=top_0.data_encout1(3) I2=top_0.data_encout1(1) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_70_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(121)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_94_I3 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(82)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(113)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_75_I3 O=dataout1_0_net_0(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(2) I3=top_0.data_encout1(0) O=dataout1_0_LUT4_O_75_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_89_I2 O=dataout1_0_net_0(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(63)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_95_I3 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(6) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(77)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_3_I2 O=dataout1_0_net_0(119)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_87_I2 O=dataout1_0_net_0(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_95_I3 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(99)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_7_I2 O=dataout1_0_net_0(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_87_I2 I3=dataout1_0_LUT4_O_87_I3 O=dataout1_0_net_0(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_87_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(6) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_87_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_8_I2 O=dataout1_0_net_0(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_89_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(3) I1=top_0.data_encout1(0) I2=top_0.data_encout1(2) I3=top_0.data_encout1(1) O=dataout1_0_LUT4_O_89_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(6) I2=top_0.data_encout1(4) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_9_I3 O=dataout1_0_net_0(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_4_I3 O=dataout1_0_net_0(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_91_I3 O=dataout1_0_net_0(118)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(3) I1=top_0.data_encout1(0) I2=top_0.data_encout1(1) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_91_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_3_I2 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(115)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_99_I3 I3=dataout1_0_LUT4_O_93_I3 O=dataout1_0_net_0(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(3) I1=top_0.data_encout1(2) I2=top_0.data_encout1(0) I3=top_0.data_encout1(1) O=dataout1_0_LUT4_O_93_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_6_I2 I3=dataout1_0_LUT4_O_94_I3 O=dataout1_0_net_0(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(5) I2=top_0.data_encout1(4) I3=top_0.data_encout1(6) O=dataout1_0_LUT4_O_94_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_4_I3 I3=dataout1_0_LUT4_O_95_I3 O=dataout1_0_net_0(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(1) I1=top_0.data_encout1(2) I2=top_0.data_encout1(0) I3=top_0.data_encout1(3) O=dataout1_0_LUT4_O_95_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_9_I2 I3=dataout1_0_LUT4_O_7_I2 O=dataout1_0_net_0(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_7_I2 I3=dataout1_0_LUT4_O_8_I3 O=dataout1_0_net_0(69)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_98_I2 I3=dataout1_0_LUT4_O_7_I3 O=dataout1_0_net_0(87)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1(3) I1=top_0.data_encout1(1) I2=top_0.data_encout1(0) I3=top_0.data_encout1(2) O=dataout1_0_LUT4_O_98_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_0_LUT4_O_8_I2 I3=dataout1_0_LUT4_O_99_I3 O=dataout1_0_net_0(61)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(5) I3=top_0.data_encout1(6) O=dataout1_0_LUT4_O_99_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1(4) I2=top_0.data_encout1(6) I3=top_0.data_encout1(5) O=dataout1_0_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1(2) I1=top_0.data_encout1(3) I2=top_0.data_encout1(0) I3=top_0.data_encout1(1) O=dataout1_0_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_LUT4_O_I1_LUT4_O_I1 I2=dataout1_0_LUT4_O_I1_LUT4_O_I2 I3=dataout1_0_LUT4_O_I1_LUT4_O_I3 O=dataout1_0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(8) I1=dataout1_0_net_0(5) I2=dataout1_0_net_0(66) I3=dataout1_0_net_0(70) O=dataout1_0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(86) I1=dataout1_0_net_0(74) I2=dataout1_0_net_0(73) I3=dataout1_0_net_0(75) O=dataout1_0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=dataout1_0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(42) I1=dataout1_0_net_0(57) I2=dataout1_0_net_0(38) I3=dataout1_0_net_0(35) O=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(104) I1=dataout1_0_net_0(127) I2=dataout1_0_net_0(107) I3=dataout1_0_net_0(45) O=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(114) I1=dataout1_0_net_0(72) I2=dataout1_0_net_0(98) I3=dataout1_0_net_0(111) O=dataout1_0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_LUT4_O_I2_LUT4_O_I1 I2=dataout1_0_LUT4_O_I2_LUT4_O_I2 I3=dataout1_0_net_0(80) O=dataout1_0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(112) I1=dataout1_0_net_0(48) I2=dataout1_0_net_0(64) I3=dataout1_0_net_0(96) O=dataout1_0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_LUT4_O_9_I2 I1=dataout1_0_LUT4_O_94_I3 I2=dataout1_0_LUT4_O_24_I2 I3=dataout1_0_LUT4_O_61_I2 O=dataout1_0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=top_0.data_encout1(1) I1=dataout1_0_LUT4_O_I3_LUT4_O_I1 I2=dataout1_0_LUT4_O_I3_LUT4_O_I2 I3=dataout1_0_LUT4_O_I3_LUT4_O_I3 O=dataout1_0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_LUT4_O_8_I2 I1=top_0.data_encout1(6) I2=dataout1_0_LUT4_O_6_I2 I3=top_0.data_encout1(0) O=dataout1_0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(25) I1=dataout1_0_net_0(65) I2=dataout1_0_net_0(61) I3=dataout1_0_net_0(101) O=dataout1_0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(69) I1=dataout1_0_net_0(21) I2=dataout1_0_net_0(105) I3=dataout1_0_net_0(40) O=dataout1_0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_2.data_encout1(0) I1=dataout1_LUT4_O_I1 I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_I3 O=dataout1_net_0(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_8_I2 O=dataout1_net_0(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_7_I2 O=dataout1_net_0(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(120)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_83_I3 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(78)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_97_I3 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(114)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_85_I3 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(83)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(127)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(99)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_75_I3 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(123)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(69)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_96_I2 O=dataout1_net_0(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_75_I3 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(126)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(77)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_97_I3 O=dataout1_net_0(66)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_83_I3 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_95_I2 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(62)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(97)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I3 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(117)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(116)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(68)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(67)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_89_I2 O=dataout1_net_0(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(115)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_85_I3 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(94)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(6) I3=top_2.data_encout1(4) O=dataout1_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(81)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I3 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(70)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_97_I3 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(91)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_85_I3 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(72)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_83_I3 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(118)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(65)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_7_I2 O=dataout1_net_0(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_96_I2 O=dataout1_net_0(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_89_I2 O=dataout1_net_0(93)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_4_I3 I3=dataout1_LUT4_O_8_I2 O=dataout1_net_0(73)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_85_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(85)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_97_I3 O=dataout1_net_0(98)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(6) I2=top_2.data_encout1(5) I3=top_2.data_encout1(4) O=dataout1_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_97_I3 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(113)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_6_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(96)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_64_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(64)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_64_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(71)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(79)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_97_I3 O=dataout1_net_0(82)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_95_I2 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(4) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(95)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(63)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(75)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_73_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(2) I1=top_2.data_encout1(3) I2=top_2.data_encout1(1) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_73_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(125)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_75_I3 O=dataout1_net_0(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(0) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(1) O=dataout1_LUT4_O_75_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(122)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_4_I3 O=dataout1_net_0(74)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_2_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(6) I2=top_2.data_encout1(4) I3=top_2.data_encout1(5) O=dataout1_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_8_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(121)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(90)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(86)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_83_I3 O=dataout1_net_0(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(3) I1=top_2.data_encout1(0) I2=top_2.data_encout1(1) I3=top_2.data_encout1(2) O=dataout1_LUT4_O_83_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(87)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_85_I3 O=dataout1_net_0(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(4) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_85_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_2_I3 O=dataout1_net_0(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_97_I3 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_89_I2 O=dataout1_net_0(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_89_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(61)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_89_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(4) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_9_I3 O=dataout1_net_0(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_I2 I3=dataout1_LUT4_O_7_I3 O=dataout1_net_0(88)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_6_I3 O=dataout1_net_0(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_8_I2 O=dataout1_net_0(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_93_I2 I3=dataout1_LUT4_O_95_I2 O=dataout1_net_0(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(2) I1=top_2.data_encout1(1) I2=top_2.data_encout1(3) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_93_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_8_I2 O=dataout1_net_0(89)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_95_I2 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(5) I2=top_2.data_encout1(4) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_95_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_96_I2 I3=dataout1_LUT4_O_8_I3 O=dataout1_net_0(119)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(3) I1=top_2.data_encout1(2) I2=top_2.data_encout1(1) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_96_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_9_I2 I3=dataout1_LUT4_O_97_I3 O=dataout1_net_0(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(2) I1=top_2.data_encout1(3) I2=top_2.data_encout1(0) I3=top_2.data_encout1(1) O=dataout1_LUT4_O_97_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_98_I2 I3=dataout1_LUT4_O_9_I2 O=dataout1_net_0(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1(2) I1=top_2.data_encout1(0) I2=top_2.data_encout1(3) I3=top_2.data_encout1(1) O=dataout1_LUT4_O_98_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout1_LUT4_O_7_I3 I3=dataout1_LUT4_O_I1 O=dataout1_net_0(84)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1(4) I2=top_2.data_encout1(5) I3=top_2.data_encout1(6) O=dataout1_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(3) I2=top_2.data_encout1(2) I3=top_2.data_encout1(0) O=dataout1_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(3) I2=top_2.data_encout1(0) I3=top_2.data_encout1(2) O=dataout1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_2.data_encout1(1) I1=top_2.data_encout1(2) I2=top_2.data_encout1(0) I3=top_2.data_encout1(3) O=dataout1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_2.data_encout1(1) I1=dataout1_LUT4_O_I3_LUT4_O_I1 I2=dataout1_LUT4_O_I3_LUT4_O_I2 I3=dataout1_LUT4_O_I3_LUT4_O_I3 O=dataout1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_net_0(112) I2=dataout1_net_0(96) I3=dataout1_net_0(64) O=dataout1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_net_0(80) I1=dataout1_net_0(49) I2=dataout1_net_0(113) I3=dataout1_net_0(16) O=dataout1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_net_0(32) I1=dataout1_net_0(17) I2=dataout1_net_0(48) I3=dataout1_net_0(1) O=dataout1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_0_LUT4_O_I2 I3=top_1.data_encout(1) O=dataout_0_net_0(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout_0_LUT4_O_1_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(127)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_85_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(117)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_85_I2 O=dataout_0_net_0(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_86_I2 O=dataout_0_net_0(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_87_I2 O=dataout_0_net_0(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_88_I2 O=dataout_0_net_0(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_89_I2 O=dataout_0_net_0(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_90_I2 O=dataout_0_net_0(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_1_I0 O=dataout_0_net_0(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_2_I0 O=dataout_0_net_0(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_3_I0 O=dataout_0_net_0(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_4_I0 O=dataout_0_net_0(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout_0_LUT4_O_86_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(116)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_5_I0 O=dataout_0_net_0(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_6_I0 O=dataout_0_net_0(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_7_I0 O=dataout_0_net_0(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_8_I0 O=dataout_0_net_0(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_9_I0 O=dataout_0_net_0(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_85_I2 O=dataout_0_net_0(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_86_I2 O=dataout_0_net_0(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_87_I2 O=dataout_0_net_0(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_88_I2 O=dataout_0_net_0(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=top_1.data_encout(5) I3=dataout_0_LUT4_O_89_I2 O=dataout_0_net_0(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout_0_LUT4_O_87_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(115)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_88_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(114)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_89_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(113)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_90_I2 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_1_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_2_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_3_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_4_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_2_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(126)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_5_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_6_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_7_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_8_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_9_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_85_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_86_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_87_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(99)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_88_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(98)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_89_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(97)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(0) I1=top_1.data_encout(3) I2=top_1.data_encout(1) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_3_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(125)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(6) I2=dataout_0_LUT4_O_90_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(96)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_1_I0 O=dataout_0_net_0(95)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_2_I0 O=dataout_0_net_0(94)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_3_I0 O=dataout_0_net_0(93)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_4_I0 O=dataout_0_net_0(91)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_5_I0 O=dataout_0_net_0(90)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_6_I0 O=dataout_0_net_0(89)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_7_I0 O=dataout_0_net_0(88)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_8_I0 O=dataout_0_net_0(87)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_9_I0 O=dataout_0_net_0(86)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_4_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(123)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_85_I2 O=dataout_0_net_0(85)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_86_I2 O=dataout_0_net_0(84)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_87_I2 O=dataout_0_net_0(83)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_88_I2 O=dataout_0_net_0(82)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_89_I2 O=dataout_0_net_0(81)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(5) I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_90_I2 O=dataout_0_net_0(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_1_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(79)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_2_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(78)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_3_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(77)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_4_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(75)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(2) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(1) O=dataout_0_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_5_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(122)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_5_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(74)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_6_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(73)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_7_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(72)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_8_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(71)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_9_I0 I3=top_1.data_encout(6) O=dataout_0_net_0(70)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_85_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(69)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_86_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(68)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_87_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(67)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_88_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(66)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_89_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(65)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(0) I1=top_1.data_encout(2) I2=top_1.data_encout(1) I3=top_1.data_encout(3) O=dataout_0_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_6_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(121)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(4) I1=top_1.data_encout(5) I2=dataout_0_LUT4_O_90_I2 I3=top_1.data_encout(6) O=dataout_0_net_0(64)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_1_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(63)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_2_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(62)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_3_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(61)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_4_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_5_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_6_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_7_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_8_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_9_I0 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(2) I2=top_1.data_encout(0) I3=top_1.data_encout(3) O=dataout_0_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_7_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(120)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_85_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_86_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_87_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_88_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_89_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=dataout_0_LUT4_O_90_I2 I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_1_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_2_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_3_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_4_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(0) I2=top_1.data_encout(2) I3=top_1.data_encout(3) O=dataout_0_LUT4_O_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout_0_LUT4_O_8_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(119)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_5_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_6_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_7_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_8_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_9_I0 I3=top_1.data_encout(5) O=dataout_0_net_0(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_85_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_85_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_86_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_86_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_87_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(3) I1=top_1.data_encout(2) I2=top_1.data_encout(0) I3=top_1.data_encout(1) O=dataout_0_LUT4_O_87_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_88_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(3) I1=top_1.data_encout(0) I2=top_1.data_encout(2) I3=top_1.data_encout(1) O=dataout_0_LUT4_O_88_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_89_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(2) I3=top_1.data_encout(0) O=dataout_0_LUT4_O_89_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout(3) I1=top_1.data_encout(1) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_9_I0 I1=top_1.data_encout(6) I2=top_1.data_encout(4) I3=top_1.data_encout(5) O=dataout_0_net_0(118)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(4) I2=dataout_0_LUT4_O_90_I2 I3=top_1.data_encout(5) O=dataout_0_net_0(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(1) I1=top_1.data_encout(3) I2=top_1.data_encout(0) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_90_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_1_I0 O=dataout_0_net_0(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_2_I0 O=dataout_0_net_0(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_3_I0 O=dataout_0_net_0(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_4_I0 O=dataout_0_net_0(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_5_I0 O=dataout_0_net_0(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_6_I0 O=dataout_0_net_0(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_7_I0 O=dataout_0_net_0(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_8_I0 O=dataout_0_net_0(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(6) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=dataout_0_LUT4_O_9_I0 O=dataout_0_net_0(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout(3) I1=top_1.data_encout(0) I2=top_1.data_encout(1) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout_0_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout(0) I2=top_1.data_encout(3) I3=top_1.data_encout(2) O=dataout_0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000000000010
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout(5) I2=top_1.data_encout(4) I3=top_1.data_encout(6) O=dataout_0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_3_I2 O=dataout_net_0(49)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(123)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_5_I2 O=dataout_net_0(56)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(96)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(66)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_97_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(70)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_4_I2 O=dataout_net_0(95)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_97_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(78)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(83)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(118)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(111)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_4_I2 O=dataout_net_0(63)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_81_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(106)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(100)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_81_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout_LUT4_O_119_I0 I1=dataout_LUT4_O_119_I1 I2=dataout_LUT4_O_119_I2 I3=dataout_LUT4_O_119_I3 O=dataout_net_0(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I3 O=dataout_LUT4_O_119_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_net_0(21) I1=dataout_net_0(106) I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout_LUT4_O_I3 I1=dataout_LUT4_O_81_I3 I2=dataout_LUT4_O_6_I3 I3=dataout_net_0(57) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_net_0(96) I1=dataout_net_0(80) I2=dataout_net_0(56) I3=dataout_net_0(48) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(34) I1=dataout_net_0(115) I2=dataout_net_0(84) I3=dataout_net_0(75) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_LUT4_O_80_I3 I1=dataout_LUT4_O_7_I2 I2=dataout_LUT4_O_81_I3 I3=dataout_net_0(100) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout_LUT4_O_I2 I1=dataout_LUT4_O_3_I2 I2=dataout_LUT4_O_81_I3 I3=dataout_net_0(78) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_net_0(105) I1=dataout_net_0(74) I2=dataout_net_0(51) I3=dataout_net_0(67) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(125) I1=dataout_net_0(99) I2=dataout_net_0(86) I3=dataout_net_0(81) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(94) I1=dataout_net_0(13) I2=dataout_net_0(55) I3=dataout_net_0(103) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(50) I1=dataout_net_0(5) I2=dataout_net_0(93) I3=dataout_net_0(127) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_net_0(68) I1=dataout_net_0(27) I2=dataout_net_0(37) I3=dataout_net_0(59) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(9) I1=dataout_net_0(17) I2=dataout_net_0(29) I3=dataout_net_0(25) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(89) I1=dataout_net_0(10) I2=dataout_net_0(98) I3=dataout_net_0(54) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(58) I1=dataout_net_0(121) I2=dataout_net_0(19) I3=dataout_net_0(31) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(63) I1=dataout_net_0(111) I2=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout_LUT4_O_I2 I1=dataout_LUT4_O_93_I2 I2=dataout_LUT4_O_98_I3 I3=dataout_net_0(65) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout_net_0(23) I1=dataout_net_0(95) I2=dataout_net_0(70) I3=dataout_net_0(66) O=dataout_LUT4_O_119_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout_net_0(88) I2=dataout_net_0(120) I3=dataout_net_0(112) O=dataout_LUT4_O_119_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout_net_0(72) I1=dataout_net_0(104) I2=dataout_net_0(16) I3=dataout_net_0(64) O=dataout_LUT4_O_119_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(32) I1=dataout_net_0(24) I2=dataout_net_0(40) I3=dataout_net_0(8) O=dataout_LUT4_O_119_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_LUT4_O_119_I1_LUT4_O_I0 I1=dataout_LUT4_O_119_I1_LUT4_O_I1 I2=dataout_LUT4_O_119_I1_LUT4_O_I2 I3=dataout_LUT4_O_119_I1_LUT4_O_I3 O=dataout_LUT4_O_119_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_net_0(102) I1=dataout_net_0(110) I2=dataout_net_0(119) I3=dataout_net_0(39) O=dataout_LUT4_O_119_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(41) I1=dataout_net_0(14) I2=dataout_net_0(30) I3=dataout_net_0(79) O=dataout_LUT4_O_119_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(97) I1=dataout_net_0(126) I2=dataout_net_0(90) I3=dataout_net_0(91) O=dataout_LUT4_O_119_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(85) I1=dataout_net_0(109) I2=dataout_net_0(73) I3=dataout_net_0(117) O=dataout_LUT4_O_119_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_LUT4_O_119_I2_LUT4_O_I0 I1=dataout_LUT4_O_119_I2_LUT4_O_I1 I2=dataout_LUT4_O_119_I2_LUT4_O_I2 I3=dataout_LUT4_O_119_I2_LUT4_O_I3 O=dataout_LUT4_O_119_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_net_0(45) I1=dataout_net_0(42) I2=dataout_net_0(52) I3=dataout_net_0(20) O=dataout_LUT4_O_119_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(116) I1=dataout_net_0(114) I2=dataout_net_0(35) I3=dataout_net_0(61) O=dataout_LUT4_O_119_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(87) I1=dataout_net_0(53) I2=dataout_net_0(107) I3=dataout_net_0(26) O=dataout_LUT4_O_119_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(4) I1=dataout_net_0(3) I2=dataout_net_0(33) I3=dataout_net_0(15) O=dataout_LUT4_O_119_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_LUT4_O_119_I3_LUT4_O_I0 I1=dataout_LUT4_O_119_I3_LUT4_O_I1 I2=dataout_LUT4_O_119_I3_LUT4_O_I2 I3=dataout_LUT4_O_119_I3_LUT4_O_I3 O=dataout_LUT4_O_119_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout_net_0(122) I1=dataout_net_0(77) I2=dataout_net_0(71) I3=dataout_net_0(69) O=dataout_LUT4_O_119_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(118) I1=dataout_net_0(123) I2=dataout_net_0(36) I3=dataout_net_0(101) O=dataout_LUT4_O_119_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(43) I1=dataout_net_0(38) I2=dataout_net_0(62) I3=dataout_net_0(47) O=dataout_LUT4_O_119_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout_net_0(113) I1=dataout_net_0(46) I2=dataout_net_0(49) I3=dataout_net_0(18) O=dataout_LUT4_O_119_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(69)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_97_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(71)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(77)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(122)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(46)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(107)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_8_I2 O=dataout_net_0(53)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(87)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_86_I2 O=dataout_net_0(61)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(114)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(116)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_9_I2 O=dataout_net_0(52)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(113)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(42)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(45)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(117)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_97_I3 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(73)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(109)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(85)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(91)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(90)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(126)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(97)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(2) I1=top_2.data_encout(1) I2=top_2.data_encout(3) I3=top_2.data_encout(0) O=dataout_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(4) I3=top_2.data_encout(6) O=dataout_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(47)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(79)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_81_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_96_I3 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(41)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I3 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_80_I3 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(119)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I3 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(110)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_6_I3 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(102)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(62)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(64)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(104)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(72)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(88)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_57_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(120)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_57_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(112)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(4) I3=top_2.data_encout(6) O=dataout_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_96_I3 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(121)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_89_I2 O=dataout_net_0(58)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(54)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(98)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(89)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I3 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(3) I2=top_2.data_encout(1) I3=top_2.data_encout(2) O=dataout_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(43)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_81_I3 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_7_I2 O=dataout_net_0(59)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_I3 O=dataout_net_0(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(68)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_4_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(127)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(93)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_5_I2 O=dataout_net_0(50)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_80_I3 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(103)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(2) I1=top_2.data_encout(0) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_8_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(101)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_80_I3 O=dataout_net_0(55)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(3) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(0) O=dataout_LUT4_O_80_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_81_I3 O=dataout_net_0(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(4) I3=top_2.data_encout(6) O=dataout_LUT4_O_81_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_5_I3 O=dataout_net_0(94)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_3_I2 O=dataout_net_0(81)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_98_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(86)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(99)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_86_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(125)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(1) I1=top_2.data_encout(2) I2=top_2.data_encout(0) I3=top_2.data_encout(3) O=dataout_LUT4_O_86_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(67)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_5_I2 O=dataout_net_0(51)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_89_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(74)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_89_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_2.data_encout(1) I1=top_2.data_encout(3) I2=top_2.data_encout(0) I3=top_2.data_encout(2) O=dataout_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(6) I3=top_2.data_encout(4) O=dataout_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_96_I3 I3=dataout_LUT4_O_8_I3 O=dataout_net_0(105)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_7_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(75)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_9_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(84)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_93_I2 I3=dataout_LUT4_O_3_I3 O=dataout_net_0(115)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(2) I1=top_2.data_encout(3) I2=top_2.data_encout(1) I3=top_2.data_encout(0) O=dataout_LUT4_O_93_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_9_I3 O=dataout_net_0(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I3 I3=dataout_LUT4_O_6_I3 O=dataout_net_0(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_5_I2 I3=dataout_LUT4_O_96_I3 O=dataout_net_0(57)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(2) I1=top_2.data_encout(1) I2=top_2.data_encout(0) I3=top_2.data_encout(3) O=dataout_LUT4_O_96_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_3_I2 I3=dataout_LUT4_O_97_I3 O=dataout_net_0(65)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(6) I2=top_2.data_encout(5) I3=top_2.data_encout(4) O=dataout_LUT4_O_97_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_I2 I3=dataout_LUT4_O_98_I3 O=dataout_net_0(82)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(6) I2=top_2.data_encout(4) I3=top_2.data_encout(5) O=dataout_LUT4_O_98_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=dataout_LUT4_O_99_I2 I3=dataout_LUT4_O_5_I2 O=dataout_net_0(48)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(1) I3=top_2.data_encout(3) O=dataout_LUT4_O_99_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(1) I2=top_2.data_encout(3) I3=top_2.data_encout(2) O=dataout_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(5) I2=top_2.data_encout(4) I3=top_2.data_encout(6) O=dataout_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_2.data_encout(0) I1=top_2.data_encout(2) I2=top_2.data_encout(3) I3=top_2.data_encout(1) O=dataout_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout(4) I2=top_2.data_encout(5) I3=top_2.data_encout(6) O=dataout_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=top_0.U011.datain(127) D=top_0.data_encin1_ff_CQZ_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(126) D=top_0.data_encin1_ff_CQZ_1_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(117) D=top_0.data_encin1_ff_CQZ_10_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(27) D=top_0.data_encin1_ff_CQZ_100_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(27) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_100_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(26) D=top_0.data_encin1_ff_CQZ_101_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(26) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_101_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(25) D=top_0.data_encin1_ff_CQZ_102_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(25) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_102_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(24) D=top_0.data_encin1_ff_CQZ_103_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(24) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_103_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(23) D=top_0.data_encin1_ff_CQZ_104_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(23) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_104_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(22) D=top_0.data_encin1_ff_CQZ_105_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(22) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_105_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(21) D=top_0.data_encin1_ff_CQZ_106_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(21) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_106_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(20) D=top_0.data_encin1_ff_CQZ_107_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(20) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_107_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(19) D=top_0.data_encin1_ff_CQZ_108_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(19) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_108_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(18) D=top_0.data_encin1_ff_CQZ_109_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(18) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_109_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(117) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(116) D=top_0.data_encin1_ff_CQZ_11_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(17) D=top_0.data_encin1_ff_CQZ_110_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(17) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_110_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(16) D=top_0.data_encin1_ff_CQZ_111_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(16) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_111_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(15) D=top_0.data_encin1_ff_CQZ_112_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(15) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_112_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(14) D=top_0.data_encin1_ff_CQZ_113_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(14) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_113_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(13) D=top_0.data_encin1_ff_CQZ_114_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(13) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_114_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(12) D=top_0.data_encin1_ff_CQZ_115_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(12) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_115_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(11) D=top_0.data_encin1_ff_CQZ_116_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(11) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_116_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(10) D=top_0.data_encin1_ff_CQZ_117_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(10) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_117_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(9) D=top_0.data_encin1_ff_CQZ_118_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(9) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_118_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(8) D=top_0.data_encin1_ff_CQZ_119_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(8) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_119_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(116) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(115) D=top_0.data_encin1_ff_CQZ_12_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(7) D=top_0.data_encin1_ff_CQZ_120_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(7) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_120_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(6) D=top_0.data_encin1_ff_CQZ_121_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(6) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_121_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(5) D=top_0.data_encin1_ff_CQZ_122_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(5) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_122_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(4) D=top_0.data_encin1_ff_CQZ_123_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(4) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_123_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(3) D=top_0.data_encin1_ff_CQZ_124_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(3) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_124_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(2) D=top_0.data_encin1_ff_CQZ_125_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(2) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_125_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(1) D=top_0.data_encin1_ff_CQZ_126_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(1) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_126_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(0) D=top_0.data_encin1_ff_CQZ_127_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(0) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_127_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(115) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(114) D=top_0.data_encin1_ff_CQZ_13_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(114) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(113) D=top_0.data_encin1_ff_CQZ_14_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(113) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(112) D=top_0.data_encin1_ff_CQZ_15_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(112) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(111) D=top_0.data_encin1_ff_CQZ_16_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(111) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(110) D=top_0.data_encin1_ff_CQZ_17_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(110) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(109) D=top_0.data_encin1_ff_CQZ_18_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(109) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(108) D=top_0.data_encin1_ff_CQZ_19_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(108) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(126) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(125) D=top_0.data_encin1_ff_CQZ_2_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(107) D=top_0.data_encin1_ff_CQZ_20_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(107) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(106) D=top_0.data_encin1_ff_CQZ_21_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(106) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(105) D=top_0.data_encin1_ff_CQZ_22_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(105) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(104) D=top_0.data_encin1_ff_CQZ_23_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(104) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(103) D=top_0.data_encin1_ff_CQZ_24_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(103) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(102) D=top_0.data_encin1_ff_CQZ_25_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(102) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(101) D=top_0.data_encin1_ff_CQZ_26_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(101) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(100) D=top_0.data_encin1_ff_CQZ_27_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(100) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(99) D=top_0.data_encin1_ff_CQZ_28_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(99) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(98) D=top_0.data_encin1_ff_CQZ_29_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(98) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(125) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(124) D=top_0.data_encin1_ff_CQZ_3_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(97) D=top_0.data_encin1_ff_CQZ_30_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(97) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(96) D=top_0.data_encin1_ff_CQZ_31_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(96) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(95) D=top_0.data_encin1_ff_CQZ_32_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(95) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_32_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(94) D=top_0.data_encin1_ff_CQZ_33_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(94) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_33_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(93) D=top_0.data_encin1_ff_CQZ_34_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(93) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_34_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(92) D=top_0.data_encin1_ff_CQZ_35_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(92) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_35_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(91) D=top_0.data_encin1_ff_CQZ_36_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(91) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_36_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(90) D=top_0.data_encin1_ff_CQZ_37_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(90) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_37_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(89) D=top_0.data_encin1_ff_CQZ_38_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(89) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_38_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(88) D=top_0.data_encin1_ff_CQZ_39_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(88) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_39_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(124) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(123) D=top_0.data_encin1_ff_CQZ_4_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(87) D=top_0.data_encin1_ff_CQZ_40_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(87) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_40_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(86) D=top_0.data_encin1_ff_CQZ_41_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(86) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_41_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(85) D=top_0.data_encin1_ff_CQZ_42_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(85) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_42_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(84) D=top_0.data_encin1_ff_CQZ_43_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(84) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_43_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(83) D=top_0.data_encin1_ff_CQZ_44_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(83) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_44_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(82) D=top_0.data_encin1_ff_CQZ_45_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(82) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_45_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(81) D=top_0.data_encin1_ff_CQZ_46_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(81) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_46_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(80) D=top_0.data_encin1_ff_CQZ_47_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(80) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_47_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(79) D=top_0.data_encin1_ff_CQZ_48_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(79) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_48_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(78) D=top_0.data_encin1_ff_CQZ_49_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(78) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_49_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(123) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(122) D=top_0.data_encin1_ff_CQZ_5_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(77) D=top_0.data_encin1_ff_CQZ_50_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(77) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_50_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(76) D=top_0.data_encin1_ff_CQZ_51_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(76) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_51_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(75) D=top_0.data_encin1_ff_CQZ_52_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(75) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_52_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(74) D=top_0.data_encin1_ff_CQZ_53_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(74) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_53_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(73) D=top_0.data_encin1_ff_CQZ_54_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(73) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_54_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(72) D=top_0.data_encin1_ff_CQZ_55_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(72) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_55_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(71) D=top_0.data_encin1_ff_CQZ_56_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(71) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_56_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(70) D=top_0.data_encin1_ff_CQZ_57_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(70) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_57_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(69) D=top_0.data_encin1_ff_CQZ_58_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(69) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_58_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(68) D=top_0.data_encin1_ff_CQZ_59_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(68) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_59_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(122) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(121) D=top_0.data_encin1_ff_CQZ_6_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(67) D=top_0.data_encin1_ff_CQZ_60_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(67) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_60_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(66) D=top_0.data_encin1_ff_CQZ_61_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(66) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_61_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(65) D=top_0.data_encin1_ff_CQZ_62_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(65) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_62_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(64) D=top_0.data_encin1_ff_CQZ_63_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(64) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_63_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(63) D=top_0.data_encin1_ff_CQZ_64_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(63) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_64_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(62) D=top_0.data_encin1_ff_CQZ_65_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(62) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_65_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(61) D=top_0.data_encin1_ff_CQZ_66_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(61) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_66_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(60) D=top_0.data_encin1_ff_CQZ_67_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(60) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_67_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(59) D=top_0.data_encin1_ff_CQZ_68_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(59) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_68_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(58) D=top_0.data_encin1_ff_CQZ_69_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(58) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_69_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(121) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(120) D=top_0.data_encin1_ff_CQZ_7_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(57) D=top_0.data_encin1_ff_CQZ_70_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(57) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_70_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(56) D=top_0.data_encin1_ff_CQZ_71_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(56) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_71_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(55) D=top_0.data_encin1_ff_CQZ_72_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(55) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_72_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(54) D=top_0.data_encin1_ff_CQZ_73_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(54) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_73_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(53) D=top_0.data_encin1_ff_CQZ_74_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(53) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_74_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(52) D=top_0.data_encin1_ff_CQZ_75_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(52) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_75_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(51) D=top_0.data_encin1_ff_CQZ_76_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(51) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_76_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(50) D=top_0.data_encin1_ff_CQZ_77_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(50) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_77_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(49) D=top_0.data_encin1_ff_CQZ_78_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(49) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_78_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(48) D=top_0.data_encin1_ff_CQZ_79_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(48) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_79_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(120) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(119) D=top_0.data_encin1_ff_CQZ_8_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(47) D=top_0.data_encin1_ff_CQZ_80_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(47) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_80_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(46) D=top_0.data_encin1_ff_CQZ_81_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(46) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_81_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(45) D=top_0.data_encin1_ff_CQZ_82_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(45) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_82_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(44) D=top_0.data_encin1_ff_CQZ_83_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(44) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_83_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(43) D=top_0.data_encin1_ff_CQZ_84_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(43) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_84_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(42) D=top_0.data_encin1_ff_CQZ_85_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(42) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_85_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(41) D=top_0.data_encin1_ff_CQZ_86_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(41) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_86_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(40) D=top_0.data_encin1_ff_CQZ_87_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(40) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_87_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(39) D=top_0.data_encin1_ff_CQZ_88_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(39) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_88_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(38) D=top_0.data_encin1_ff_CQZ_89_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(38) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_89_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(119) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(118) D=top_0.data_encin1_ff_CQZ_9_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U011.datain(37) D=top_0.data_encin1_ff_CQZ_90_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(37) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_90_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(36) D=top_0.data_encin1_ff_CQZ_91_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(36) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_91_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(35) D=top_0.data_encin1_ff_CQZ_92_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(35) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_92_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(34) D=top_0.data_encin1_ff_CQZ_93_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(34) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_93_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(33) D=top_0.data_encin1_ff_CQZ_94_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(33) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_94_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(32) D=top_0.data_encin1_ff_CQZ_95_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(32) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_95_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(31) D=top_0.data_encin1_ff_CQZ_96_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(31) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_96_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(30) D=top_0.data_encin1_ff_CQZ_97_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(30) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_97_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(29) D=top_0.data_encin1_ff_CQZ_98_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(29) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_98_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U011.datain(28) D=top_0.data_encin1_ff_CQZ_99_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(28) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_99_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(118) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain1(127) I3=top_0.reset O=top_0.data_encin1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(127) D=top_0.data_encin_ff_CQZ_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(126) D=top_0.data_encin_ff_CQZ_1_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(117) D=top_0.data_encin_ff_CQZ_10_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(27) D=top_0.data_encin_ff_CQZ_100_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(27) I3=top_0.reset O=top_0.data_encin_ff_CQZ_100_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(26) D=top_0.data_encin_ff_CQZ_101_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(26) I3=top_0.reset O=top_0.data_encin_ff_CQZ_101_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(25) D=top_0.data_encin_ff_CQZ_102_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(25) I3=top_0.reset O=top_0.data_encin_ff_CQZ_102_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(24) D=top_0.data_encin_ff_CQZ_103_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(24) I3=top_0.reset O=top_0.data_encin_ff_CQZ_103_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(23) D=top_0.data_encin_ff_CQZ_104_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(23) I3=top_0.reset O=top_0.data_encin_ff_CQZ_104_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(22) D=top_0.data_encin_ff_CQZ_105_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(22) I3=top_0.reset O=top_0.data_encin_ff_CQZ_105_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(21) D=top_0.data_encin_ff_CQZ_106_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(21) I3=top_0.reset O=top_0.data_encin_ff_CQZ_106_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(20) D=top_0.data_encin_ff_CQZ_107_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(20) I3=top_0.reset O=top_0.data_encin_ff_CQZ_107_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(19) D=top_0.data_encin_ff_CQZ_108_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(19) I3=top_0.reset O=top_0.data_encin_ff_CQZ_108_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(18) D=top_0.data_encin_ff_CQZ_109_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(18) I3=top_0.reset O=top_0.data_encin_ff_CQZ_109_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(117) I3=top_0.reset O=top_0.data_encin_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(116) D=top_0.data_encin_ff_CQZ_11_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(17) D=top_0.data_encin_ff_CQZ_110_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(17) I3=top_0.reset O=top_0.data_encin_ff_CQZ_110_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(16) D=top_0.data_encin_ff_CQZ_111_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(16) I3=top_0.reset O=top_0.data_encin_ff_CQZ_111_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(15) D=top_0.data_encin_ff_CQZ_112_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(15) I3=top_0.reset O=top_0.data_encin_ff_CQZ_112_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(14) D=top_0.data_encin_ff_CQZ_113_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(14) I3=top_0.reset O=top_0.data_encin_ff_CQZ_113_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(13) D=top_0.data_encin_ff_CQZ_114_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(13) I3=top_0.reset O=top_0.data_encin_ff_CQZ_114_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(12) D=top_0.data_encin_ff_CQZ_115_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(12) I3=top_0.reset O=top_0.data_encin_ff_CQZ_115_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(11) D=top_0.data_encin_ff_CQZ_116_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(11) I3=top_0.reset O=top_0.data_encin_ff_CQZ_116_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(10) D=top_0.data_encin_ff_CQZ_117_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(10) I3=top_0.reset O=top_0.data_encin_ff_CQZ_117_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(9) D=top_0.data_encin_ff_CQZ_118_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(9) I3=top_0.reset O=top_0.data_encin_ff_CQZ_118_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(8) D=top_0.data_encin_ff_CQZ_119_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(8) I3=top_0.reset O=top_0.data_encin_ff_CQZ_119_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(116) I3=top_0.reset O=top_0.data_encin_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(115) D=top_0.data_encin_ff_CQZ_12_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(7) D=top_0.data_encin_ff_CQZ_120_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(7) I3=top_0.reset O=top_0.data_encin_ff_CQZ_120_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(6) D=top_0.data_encin_ff_CQZ_121_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(6) I3=top_0.reset O=top_0.data_encin_ff_CQZ_121_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(5) D=top_0.data_encin_ff_CQZ_122_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(5) I3=top_0.reset O=top_0.data_encin_ff_CQZ_122_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(4) D=top_0.data_encin_ff_CQZ_123_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(4) I3=top_0.reset O=top_0.data_encin_ff_CQZ_123_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(3) D=top_0.data_encin_ff_CQZ_124_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(3) I3=top_0.reset O=top_0.data_encin_ff_CQZ_124_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(2) D=top_0.data_encin_ff_CQZ_125_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(2) I3=top_0.reset O=top_0.data_encin_ff_CQZ_125_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(1) D=top_0.data_encin_ff_CQZ_126_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(1) I3=top_0.reset O=top_0.data_encin_ff_CQZ_126_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(0) D=top_0.data_encin_ff_CQZ_127_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(0) I3=top_0.reset O=top_0.data_encin_ff_CQZ_127_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(115) I3=top_0.reset O=top_0.data_encin_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(114) D=top_0.data_encin_ff_CQZ_13_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(114) I3=top_0.reset O=top_0.data_encin_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(113) D=top_0.data_encin_ff_CQZ_14_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(113) I3=top_0.reset O=top_0.data_encin_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(112) D=top_0.data_encin_ff_CQZ_15_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(112) I3=top_0.reset O=top_0.data_encin_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(111) D=top_0.data_encin_ff_CQZ_16_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(111) I3=top_0.reset O=top_0.data_encin_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(110) D=top_0.data_encin_ff_CQZ_17_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(110) I3=top_0.reset O=top_0.data_encin_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(109) D=top_0.data_encin_ff_CQZ_18_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(109) I3=top_0.reset O=top_0.data_encin_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(108) D=top_0.data_encin_ff_CQZ_19_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(108) I3=top_0.reset O=top_0.data_encin_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(126) I3=top_0.reset O=top_0.data_encin_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(125) D=top_0.data_encin_ff_CQZ_2_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(107) D=top_0.data_encin_ff_CQZ_20_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(107) I3=top_0.reset O=top_0.data_encin_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(106) D=top_0.data_encin_ff_CQZ_21_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(106) I3=top_0.reset O=top_0.data_encin_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(105) D=top_0.data_encin_ff_CQZ_22_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(105) I3=top_0.reset O=top_0.data_encin_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(104) D=top_0.data_encin_ff_CQZ_23_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(104) I3=top_0.reset O=top_0.data_encin_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(103) D=top_0.data_encin_ff_CQZ_24_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(103) I3=top_0.reset O=top_0.data_encin_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(102) D=top_0.data_encin_ff_CQZ_25_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(102) I3=top_0.reset O=top_0.data_encin_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(101) D=top_0.data_encin_ff_CQZ_26_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(101) I3=top_0.reset O=top_0.data_encin_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(100) D=top_0.data_encin_ff_CQZ_27_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(100) I3=top_0.reset O=top_0.data_encin_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(99) D=top_0.data_encin_ff_CQZ_28_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(99) I3=top_0.reset O=top_0.data_encin_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(98) D=top_0.data_encin_ff_CQZ_29_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(98) I3=top_0.reset O=top_0.data_encin_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(125) I3=top_0.reset O=top_0.data_encin_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(124) D=top_0.data_encin_ff_CQZ_3_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(97) D=top_0.data_encin_ff_CQZ_30_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(97) I3=top_0.reset O=top_0.data_encin_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(96) D=top_0.data_encin_ff_CQZ_31_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(96) I3=top_0.reset O=top_0.data_encin_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(95) D=top_0.data_encin_ff_CQZ_32_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(95) I3=top_0.reset O=top_0.data_encin_ff_CQZ_32_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(94) D=top_0.data_encin_ff_CQZ_33_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(94) I3=top_0.reset O=top_0.data_encin_ff_CQZ_33_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(93) D=top_0.data_encin_ff_CQZ_34_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(93) I3=top_0.reset O=top_0.data_encin_ff_CQZ_34_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(92) D=top_0.data_encin_ff_CQZ_35_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(92) I3=top_0.reset O=top_0.data_encin_ff_CQZ_35_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(91) D=top_0.data_encin_ff_CQZ_36_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(91) I3=top_0.reset O=top_0.data_encin_ff_CQZ_36_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(90) D=top_0.data_encin_ff_CQZ_37_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(90) I3=top_0.reset O=top_0.data_encin_ff_CQZ_37_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(89) D=top_0.data_encin_ff_CQZ_38_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(89) I3=top_0.reset O=top_0.data_encin_ff_CQZ_38_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(88) D=top_0.data_encin_ff_CQZ_39_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(88) I3=top_0.reset O=top_0.data_encin_ff_CQZ_39_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(124) I3=top_0.reset O=top_0.data_encin_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(123) D=top_0.data_encin_ff_CQZ_4_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(87) D=top_0.data_encin_ff_CQZ_40_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(87) I3=top_0.reset O=top_0.data_encin_ff_CQZ_40_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(86) D=top_0.data_encin_ff_CQZ_41_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(86) I3=top_0.reset O=top_0.data_encin_ff_CQZ_41_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(85) D=top_0.data_encin_ff_CQZ_42_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(85) I3=top_0.reset O=top_0.data_encin_ff_CQZ_42_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(84) D=top_0.data_encin_ff_CQZ_43_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(84) I3=top_0.reset O=top_0.data_encin_ff_CQZ_43_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(83) D=top_0.data_encin_ff_CQZ_44_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(83) I3=top_0.reset O=top_0.data_encin_ff_CQZ_44_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(82) D=top_0.data_encin_ff_CQZ_45_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(82) I3=top_0.reset O=top_0.data_encin_ff_CQZ_45_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(81) D=top_0.data_encin_ff_CQZ_46_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(81) I3=top_0.reset O=top_0.data_encin_ff_CQZ_46_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(80) D=top_0.data_encin_ff_CQZ_47_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(80) I3=top_0.reset O=top_0.data_encin_ff_CQZ_47_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(79) D=top_0.data_encin_ff_CQZ_48_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(79) I3=top_0.reset O=top_0.data_encin_ff_CQZ_48_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(78) D=top_0.data_encin_ff_CQZ_49_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(78) I3=top_0.reset O=top_0.data_encin_ff_CQZ_49_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(123) I3=top_0.reset O=top_0.data_encin_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(122) D=top_0.data_encin_ff_CQZ_5_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(77) D=top_0.data_encin_ff_CQZ_50_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(77) I3=top_0.reset O=top_0.data_encin_ff_CQZ_50_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(76) D=top_0.data_encin_ff_CQZ_51_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(76) I3=top_0.reset O=top_0.data_encin_ff_CQZ_51_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(75) D=top_0.data_encin_ff_CQZ_52_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(75) I3=top_0.reset O=top_0.data_encin_ff_CQZ_52_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(74) D=top_0.data_encin_ff_CQZ_53_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(74) I3=top_0.reset O=top_0.data_encin_ff_CQZ_53_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(73) D=top_0.data_encin_ff_CQZ_54_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(73) I3=top_0.reset O=top_0.data_encin_ff_CQZ_54_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(72) D=top_0.data_encin_ff_CQZ_55_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(72) I3=top_0.reset O=top_0.data_encin_ff_CQZ_55_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(71) D=top_0.data_encin_ff_CQZ_56_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(71) I3=top_0.reset O=top_0.data_encin_ff_CQZ_56_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(70) D=top_0.data_encin_ff_CQZ_57_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(70) I3=top_0.reset O=top_0.data_encin_ff_CQZ_57_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(69) D=top_0.data_encin_ff_CQZ_58_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(69) I3=top_0.reset O=top_0.data_encin_ff_CQZ_58_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(68) D=top_0.data_encin_ff_CQZ_59_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(68) I3=top_0.reset O=top_0.data_encin_ff_CQZ_59_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(122) I3=top_0.reset O=top_0.data_encin_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(121) D=top_0.data_encin_ff_CQZ_6_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(67) D=top_0.data_encin_ff_CQZ_60_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(67) I3=top_0.reset O=top_0.data_encin_ff_CQZ_60_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(66) D=top_0.data_encin_ff_CQZ_61_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(66) I3=top_0.reset O=top_0.data_encin_ff_CQZ_61_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(65) D=top_0.data_encin_ff_CQZ_62_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(65) I3=top_0.reset O=top_0.data_encin_ff_CQZ_62_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(64) D=top_0.data_encin_ff_CQZ_63_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(64) I3=top_0.reset O=top_0.data_encin_ff_CQZ_63_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(63) D=top_0.data_encin_ff_CQZ_64_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(63) I3=top_0.reset O=top_0.data_encin_ff_CQZ_64_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(62) D=top_0.data_encin_ff_CQZ_65_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(62) I3=top_0.reset O=top_0.data_encin_ff_CQZ_65_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(61) D=top_0.data_encin_ff_CQZ_66_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(61) I3=top_0.reset O=top_0.data_encin_ff_CQZ_66_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(60) D=top_0.data_encin_ff_CQZ_67_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(60) I3=top_0.reset O=top_0.data_encin_ff_CQZ_67_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(59) D=top_0.data_encin_ff_CQZ_68_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(59) I3=top_0.reset O=top_0.data_encin_ff_CQZ_68_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(58) D=top_0.data_encin_ff_CQZ_69_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(58) I3=top_0.reset O=top_0.data_encin_ff_CQZ_69_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(121) I3=top_0.reset O=top_0.data_encin_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(120) D=top_0.data_encin_ff_CQZ_7_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(57) D=top_0.data_encin_ff_CQZ_70_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(57) I3=top_0.reset O=top_0.data_encin_ff_CQZ_70_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(56) D=top_0.data_encin_ff_CQZ_71_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(56) I3=top_0.reset O=top_0.data_encin_ff_CQZ_71_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(55) D=top_0.data_encin_ff_CQZ_72_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(55) I3=top_0.reset O=top_0.data_encin_ff_CQZ_72_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(54) D=top_0.data_encin_ff_CQZ_73_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(54) I3=top_0.reset O=top_0.data_encin_ff_CQZ_73_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(53) D=top_0.data_encin_ff_CQZ_74_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(53) I3=top_0.reset O=top_0.data_encin_ff_CQZ_74_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(52) D=top_0.data_encin_ff_CQZ_75_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(52) I3=top_0.reset O=top_0.data_encin_ff_CQZ_75_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(51) D=top_0.data_encin_ff_CQZ_76_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(51) I3=top_0.reset O=top_0.data_encin_ff_CQZ_76_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(50) D=top_0.data_encin_ff_CQZ_77_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(50) I3=top_0.reset O=top_0.data_encin_ff_CQZ_77_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(49) D=top_0.data_encin_ff_CQZ_78_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(49) I3=top_0.reset O=top_0.data_encin_ff_CQZ_78_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(48) D=top_0.data_encin_ff_CQZ_79_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(48) I3=top_0.reset O=top_0.data_encin_ff_CQZ_79_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(120) I3=top_0.reset O=top_0.data_encin_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(119) D=top_0.data_encin_ff_CQZ_8_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(47) D=top_0.data_encin_ff_CQZ_80_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(47) I3=top_0.reset O=top_0.data_encin_ff_CQZ_80_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(46) D=top_0.data_encin_ff_CQZ_81_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(46) I3=top_0.reset O=top_0.data_encin_ff_CQZ_81_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(45) D=top_0.data_encin_ff_CQZ_82_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(45) I3=top_0.reset O=top_0.data_encin_ff_CQZ_82_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(44) D=top_0.data_encin_ff_CQZ_83_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(44) I3=top_0.reset O=top_0.data_encin_ff_CQZ_83_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(43) D=top_0.data_encin_ff_CQZ_84_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(43) I3=top_0.reset O=top_0.data_encin_ff_CQZ_84_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(42) D=top_0.data_encin_ff_CQZ_85_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(42) I3=top_0.reset O=top_0.data_encin_ff_CQZ_85_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(41) D=top_0.data_encin_ff_CQZ_86_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(41) I3=top_0.reset O=top_0.data_encin_ff_CQZ_86_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(40) D=top_0.data_encin_ff_CQZ_87_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(40) I3=top_0.reset O=top_0.data_encin_ff_CQZ_87_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(39) D=top_0.data_encin_ff_CQZ_88_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(39) I3=top_0.reset O=top_0.data_encin_ff_CQZ_88_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(38) D=top_0.data_encin_ff_CQZ_89_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(38) I3=top_0.reset O=top_0.data_encin_ff_CQZ_89_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(119) I3=top_0.reset O=top_0.data_encin_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(118) D=top_0.data_encin_ff_CQZ_9_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.U01.datain(37) D=top_0.data_encin_ff_CQZ_90_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(37) I3=top_0.reset O=top_0.data_encin_ff_CQZ_90_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(36) D=top_0.data_encin_ff_CQZ_91_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(36) I3=top_0.reset O=top_0.data_encin_ff_CQZ_91_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(35) D=top_0.data_encin_ff_CQZ_92_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(35) I3=top_0.reset O=top_0.data_encin_ff_CQZ_92_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(34) D=top_0.data_encin_ff_CQZ_93_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(34) I3=top_0.reset O=top_0.data_encin_ff_CQZ_93_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(33) D=top_0.data_encin_ff_CQZ_94_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(33) I3=top_0.reset O=top_0.data_encin_ff_CQZ_94_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(32) D=top_0.data_encin_ff_CQZ_95_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(32) I3=top_0.reset O=top_0.data_encin_ff_CQZ_95_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(31) D=top_0.data_encin_ff_CQZ_96_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(31) I3=top_0.reset O=top_0.data_encin_ff_CQZ_96_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(30) D=top_0.data_encin_ff_CQZ_97_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(30) I3=top_0.reset O=top_0.data_encin_ff_CQZ_97_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(29) D=top_0.data_encin_ff_CQZ_98_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(29) I3=top_0.reset O=top_0.data_encin_ff_CQZ_98_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.U01.datain(28) D=top_0.data_encin_ff_CQZ_99_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:74.5-83.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(28) I3=top_0.reset O=top_0.data_encin_ff_CQZ_99_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(118) I3=top_0.reset O=top_0.data_encin_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.datain(127) I3=top_0.reset O=top_0.data_encin_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_0.data_encout1(6) D=top_0.data_encout1_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout1(5) D=top_0.data_encout1_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout1(4) D=top_0.data_encout1_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout1(3) D=top_0.data_encout1_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout1(2) D=top_0.data_encout1_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout1(1) D=top_0.data_encout1_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout1(0) D=top_0.data_encout1_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3 O=top_0.data_encout1_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.reset I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U011.datain(82) I1=top_0.U011.datain(81) I2=top_0.U011.datain(80) I3=top_0.U011.datain(83) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.U011.datain(52) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(53) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(86) I1=top_0.reset I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(87) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(26) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(27) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.U011.datain(25) I3=top_0.U011.datain(24) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.U011.datain(30) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(31) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(30) I3=top_0.U011.datain(31) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(19) I1=top_0.U011.datain(18) I2=top_0.U011.datain(17) I3=top_0.U011.datain(16) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U011.datain(27) I1=top_0.U011.datain(24) I2=top_0.U011.datain(26) I3=top_0.U011.datain(25) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(29) I3=top_0.U011.datain(28) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(91) I1=top_0.U011.datain(88) I2=top_0.U011.datain(90) I3=top_0.U011.datain(89) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U011.datain(92) I1=top_0.U011.datain(94) I2=top_0.U011.datain(93) I3=top_0.U011.datain(95) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3 O=top_0.data_encout1_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U011.datain(73) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(72) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(74) I3=top_0.U011.datain(75) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(79) I1=top_0.U011.datain(78) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(76) I3=top_0.U011.datain(77) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=top_0.U011.datain(9) I1=top_0.U011.datain(8) I2=top_0.U011.datain(11) I3=top_0.U011.datain(10) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010100
+.subckt LUT4 I0=top_0.U011.datain(12) I1=top_0.U011.datain(15) I2=top_0.U011.datain(14) I3=top_0.U011.datain(13) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(12) I3=top_0.U011.datain(13) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.U011.datain(29) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010111001111
+.subckt LUT4 I0=top_0.U011.datain(27) I1=top_0.U011.datain(26) I2=top_0.U011.datain(25) I3=top_0.U011.datain(24) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.U011.datain(28) I1=top_0.U011.datain(29) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(30) I3=top_0.U011.datain(31) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(28) I1=top_0.U011.datain(31) I2=top_0.U011.datain(30) I3=top_0.U011.datain(29) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(45) I3=top_0.U011.datain(44) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(43) I1=top_0.U011.datain(40) I2=top_0.U011.datain(42) I3=top_0.U011.datain(41) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(46) I3=top_0.U011.datain(47) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(76) I1=top_0.U011.datain(79) I2=top_0.U011.datain(77) I3=top_0.U011.datain(78) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.U011.datain(75) I1=top_0.U011.datain(72) I2=top_0.U011.datain(74) I3=top_0.U011.datain(73) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(111) I3=top_0.U011.datain(110) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(109) I3=top_0.U011.datain(108) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(107) I1=top_0.U011.datain(104) I2=top_0.U011.datain(106) I3=top_0.U011.datain(105) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U011.datain(103) I1=top_0.U011.datain(102) I2=top_0.U011.datain(101) I3=top_0.U011.datain(100) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(110) I3=top_0.U011.datain(111) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.U011.datain(31) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.U011.datain(30) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(92) I1=top_0.U011.datain(95) I2=top_0.U011.datain(93) I3=top_0.U011.datain(94) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(76) I1=top_0.U011.datain(78) I2=top_0.U011.datain(77) I3=top_0.U011.datain(79) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(74) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.U011.datain(75) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.U011.datain(75) I3=top_0.U011.datain(74) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(73) I3=top_0.U011.datain(72) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(76) I1=top_0.U011.datain(79) I2=top_0.U011.datain(78) I3=top_0.U011.datain(77) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.U011.datain(27) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.U011.datain(26) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(42) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.U011.datain(43) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(41) I3=top_0.U011.datain(40) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(106) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(107) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3 O=top_0.data_encout1_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(68) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.U011.datain(69) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.U011.datain(67) I1=top_0.U011.datain(66) I2=top_0.U011.datain(65) I3=top_0.U011.datain(64) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(7) I1=top_0.U011.datain(6) I2=top_0.U011.datain(5) I3=top_0.U011.datain(4) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.U011.datain(21) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.U011.datain(20) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.U011.datain(22) I3=top_0.U011.datain(23) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D(6) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0 O=top_0.data_encout1_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_0.reset I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=top_0.U011.datain(19) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.U011.datain(18) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_0.U011.datain(7) I1=top_0.U011.datain(6) I2=top_0.U011.datain(5) I3=top_0.U011.datain(4) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U011.datain(3) I1=top_0.U011.datain(1) I2=top_0.U011.datain(0) I3=top_0.U011.datain(2) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(10) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(11) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(67) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.U011.datain(66) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(64) I3=top_0.U011.datain(65) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(87) I1=top_0.U011.datain(86) I2=top_0.U011.datain(85) I3=top_0.U011.datain(84) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(70) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(71) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_0.U011.datain(68) I3=top_0.U011.datain(69) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=top_0.U011.datain(86) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(87) I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(86) I3=top_0.U011.datain(87) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(84) I3=top_0.U011.datain(85) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(83) I1=top_0.U011.datain(82) I2=top_0.U011.datain(81) I3=top_0.U011.datain(80) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.U011.datain(23) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.U011.datain(22) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(23) I3=top_0.U011.datain(22) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.U011.datain(20) I3=top_0.U011.datain(21) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=top_0.U011.datain(7) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I3=top_0.U011.datain(6) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(14) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.U011.datain(15) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3 O=top_0.data_encout1_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=top_0.U011.datain(89) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(88) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U011.datain(93) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(92) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U011.datain(92) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(93) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(94) I3=top_0.U011.datain(95) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(91) I3=top_0.U011.datain(90) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.U011.datain(89) I3=top_0.U011.datain(88) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(90) I3=top_0.U011.datain(91) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I2=top_0.reset I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(88) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.U011.datain(89) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(90) I3=top_0.U011.datain(91) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U011.datain(92) I1=top_0.U011.datain(95) I2=top_0.U011.datain(94) I3=top_0.U011.datain(93) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U011.datain(83) I1=top_0.U011.datain(82) I2=top_0.U011.datain(81) I3=top_0.U011.datain(80) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011101001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(84) I3=top_0.U011.datain(85) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(86) I3=top_0.U011.datain(87) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(98) I3=top_0.U011.datain(99) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(96) I3=top_0.U011.datain(97) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(109) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.U011.datain(108) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U011.datain(104) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(105) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(103) I1=top_0.U011.datain(102) I2=top_0.U011.datain(101) I3=top_0.U011.datain(100) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(102) I3=top_0.U011.datain(103) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_0.reset I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111111111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(112) I3=top_0.U011.datain(113) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=top_0.U011.datain(117) I1=top_0.U011.datain(116) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001111111111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3 O=top_0.data_encout1_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(23) I1=top_0.U011.datain(22) I2=top_0.U011.datain(21) I3=top_0.U011.datain(20) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(16) I3=top_0.U011.datain(17) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(19) I3=top_0.U011.datain(18) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_0.U011.datain(10) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(11) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(8) I1=top_0.U011.datain(9) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.U011.datain(1) I1=top_0.U011.datain(0) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.U011.datain(3) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(71) I3=top_0.U011.datain(70) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(15) I3=top_0.U011.datain(14) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(12) I1=top_0.U011.datain(13) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.U011.datain(8) I1=top_0.U011.datain(11) I2=top_0.U011.datain(10) I3=top_0.U011.datain(9) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U011.datain(6) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(7) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=top_0.U011.datain(4) I3=top_0.U011.datain(5) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I0_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=top_0.reset O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.U011.datain(28) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I3=top_0.U011.datain(29) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I0_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(27) I1=top_0.U011.datain(24) I2=top_0.U011.datain(26) I3=top_0.U011.datain(25) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(77) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.U011.datain(76) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_0.U011.datain(78) I3=top_0.U011.datain(79) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(73) I3=top_0.U011.datain(72) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_0.U011.datain(3) I1=top_0.U011.datain(2) I2=top_0.U011.datain(1) I3=top_0.U011.datain(0) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U011.datain(7) I1=top_0.U011.datain(6) I2=top_0.U011.datain(4) I3=top_0.U011.datain(5) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(12) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(13) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.U011.datain(14) I3=top_0.U011.datain(15) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(21) I3=top_0.U011.datain(20) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D(6) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(84) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(85) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=top_0.U011.datain(68) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(69) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(70) I3=top_0.U011.datain(71) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_0.U011.datain(64) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(65) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(64) I3=top_0.U011.datain(65) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(66) I3=top_0.U011.datain(67) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(71) I1=top_0.U011.datain(70) I2=top_0.U011.datain(69) I3=top_0.U011.datain(68) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(83) I1=top_0.U011.datain(82) I2=top_0.U011.datain(80) I3=top_0.U011.datain(81) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D(6) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(81) I1=top_0.U011.datain(80) I2=top_0.U011.datain(83) I3=top_0.U011.datain(82) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=top_0.U011.datain(19) I1=top_0.U011.datain(18) I2=top_0.U011.datain(17) I3=top_0.U011.datain(16) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(19) I1=top_0.U011.datain(18) I2=top_0.U011.datain(16) I3=top_0.U011.datain(17) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(8) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(9) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(10) I3=top_0.U011.datain(11) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(3) I1=top_0.U011.datain(0) I2=top_0.U011.datain(1) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=top_0.U011.datain(2) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(54) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(55) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.U011.datain(119) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.U011.datain(118) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(38) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.U011.datain(39) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.U011.datain(103) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.U011.datain(102) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(100) I3=top_0.U011.datain(101) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(99) I1=top_0.U011.datain(98) I2=top_0.U011.datain(97) I3=top_0.U011.datain(96) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(36) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_0.U011.datain(37) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(35) I1=top_0.U011.datain(33) I2=top_0.U011.datain(32) I3=top_0.U011.datain(34) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.U011.datain(99) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.U011.datain(98) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.U011.datain(48) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(49) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(48) I3=top_0.U011.datain(49) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(50) I3=top_0.U011.datain(51) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(55) I1=top_0.U011.datain(54) I2=top_0.U011.datain(53) I3=top_0.U011.datain(52) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(113) I3=top_0.U011.datain(112) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(114) I3=top_0.U011.datain(115) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(34) I3=top_0.U011.datain(35) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(33) I3=top_0.U011.datain(32) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.U011.datain(96) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(97) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(108) I1=top_0.U011.datain(111) I2=top_0.U011.datain(110) I3=top_0.U011.datain(109) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.U011.datain(98) I3=top_0.U011.datain(99) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(59) I1=top_0.U011.datain(56) I2=top_0.U011.datain(58) I3=top_0.U011.datain(57) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(50) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.U011.datain(51) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.U011.datain(43) I3=top_0.U011.datain(42) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(47) I3=top_0.U011.datain(46) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(125) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.U011.datain(124) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_0.U011.datain(58) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.U011.datain(59) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_0.U011.datain(58) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(62) I3=top_0.U011.datain(63) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(124) I1=top_0.U011.datain(127) I2=top_0.U011.datain(125) I3=top_0.U011.datain(126) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(38) I3=top_0.U011.datain(39) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(103) I1=top_0.U011.datain(102) I2=top_0.U011.datain(100) I3=top_0.U011.datain(101) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(37) I3=top_0.U011.datain(36) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(38) I3=top_0.U011.datain(39) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(44) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.U011.datain(45) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(46) I3=top_0.U011.datain(47) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(56) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.U011.datain(57) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(61) I3=top_0.U011.datain(60) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U011.datain(59) I1=top_0.U011.datain(63) I2=top_0.U011.datain(62) I3=top_0.U011.datain(58) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(41) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.U011.datain(40) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(42) I3=top_0.U011.datain(43) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(44) I1=top_0.U011.datain(47) I2=top_0.U011.datain(46) I3=top_0.U011.datain(45) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.U011.datain(50) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(51) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(48) I3=top_0.U011.datain(49) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(115) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(39) I3=top_0.U011.datain(38) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(36) I3=top_0.U011.datain(37) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(63) I3=top_0.U011.datain(62) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(124) I1=top_0.U011.datain(126) I2=top_0.U011.datain(125) I3=top_0.U011.datain(127) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(58) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(59) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(57) I3=top_0.U011.datain(56) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U011.datain(60) I1=top_0.U011.datain(63) I2=top_0.U011.datain(62) I3=top_0.U011.datain(61) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(50) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(51) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(55) I3=top_0.U011.datain(54) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(52) I3=top_0.U011.datain(53) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(118) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(119) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(107) I3=top_0.U011.datain(106) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(105) I3=top_0.U011.datain(104) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(119) I1=top_0.U011.datain(118) I2=top_0.U011.datain(117) I3=top_0.U011.datain(116) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(114) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_0.U011.datain(115) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.U011.datain(97) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.U011.datain(96) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(102) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(103) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(66) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(67) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(98) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(99) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.U011.datain(96) I3=top_0.U011.datain(97) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(32) I3=top_0.U011.datain(33) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(34) I1=top_0.U011.datain(33) I2=top_0.U011.datain(32) I3=top_0.U011.datain(35) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.U011.datain(53) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.U011.datain(52) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(52) I3=top_0.U011.datain(53) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(54) I3=top_0.U011.datain(55) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(51) I1=top_0.U011.datain(50) I2=top_0.U011.datain(49) I3=top_0.U011.datain(48) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=top_0.U011.datain(116) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111111111
+.subckt LUT4 I0=top_0.U011.datain(119) I1=top_0.U011.datain(118) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001111111111111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(116) I3=top_0.U011.datain(117) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U011.datain(116) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(117) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(115) I1=top_0.U011.datain(114) I2=top_0.U011.datain(113) I3=top_0.U011.datain(112) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(118) I3=top_0.U011.datain(119) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U011.datain(61) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(60) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(61) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.U011.datain(60) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U011.datain(57) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(56) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U011.datain(120) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=top_0.U011.datain(121) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U011.datain(122) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.U011.datain(123) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(123) I3=top_0.U011.datain(122) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.U011.datain(121) I3=top_0.U011.datain(120) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U011.datain(125) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(124) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U011.datain(127) I3=top_0.U011.datain(126) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(123) I1=top_0.U011.datain(120) I2=top_0.U011.datain(122) I3=top_0.U011.datain(121) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U011.datain(121) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(120) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(122) I3=top_0.U011.datain(123) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U011.datain(124) I1=top_0.U011.datain(126) I2=top_0.U011.datain(127) I3=top_0.U011.datain(125) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U011.datain(109) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U011.datain(108) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.U011.datain(110) I3=top_0.U011.datain(111) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U011.datain(105) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U011.datain(104) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(106) I3=top_0.U011.datain(107) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U011.datain(41) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.U011.datain(40) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.U011.datain(45) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U011.datain(44) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U011.datain(35) I1=top_0.U011.datain(34) I2=top_0.U011.datain(33) I3=top_0.U011.datain(32) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U011.datain(39) I1=top_0.U011.datain(38) I2=top_0.U011.datain(37) I3=top_0.U011.datain(36) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=top_0.U011.datain(115) I1=top_0.U011.datain(114) I2=top_0.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(112) I3=top_0.U011.datain(113) O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U011.datain(48) I3=top_0.data_encout1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=top_0.data_encout(6) D=top_0.data_encout_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout(5) D=top_0.data_encout_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout(4) D=top_0.data_encout_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout(3) D=top_0.data_encout_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout(2) D=top_0.data_encout_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout(1) D=top_0.data_encout_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_0.data_encout(0) D=top_0.data_encout_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3 O=top_0.data_encout_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.U01.datain(75) I3=top_0.U01.datain(74) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.U01.datain(71) I1=top_0.U01.datain(70) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(68) I3=top_0.U01.datain(69) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(77) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(76) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(79) I3=top_0.U01.datain(78) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=top_0.U01.datain(14) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.U01.datain(15) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(13) I3=top_0.U01.datain(12) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111111111
+.subckt LUT4 I0=top_0.U01.datain(12) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_0.U01.datain(13) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(15) I3=top_0.U01.datain(14) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=top_0.U01.datain(9) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(8) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.U01.datain(10) I3=top_0.U01.datain(11) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U01.datain(13) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I2=top_0.U01.datain(12) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(8) I1=top_0.U01.datain(10) I2=top_0.U01.datain(9) I3=top_0.U01.datain(11) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(11) I1=top_0.U01.datain(8) I2=top_0.U01.datain(9) I3=top_0.U01.datain(10) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(9) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.U01.datain(8) O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3 O=top_0.data_encout_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2 I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100001011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(125) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.U01.datain(124) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(61) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.U01.datain(60) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(63) I3=top_0.U01.datain(62) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U01.datain(4) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3 I2=top_0.U01.datain(5) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(18) I3=top_0.U01.datain(19) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I2=top_0.U01.datain(16) I3=top_0.U01.datain(17) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.U01.datain(19) I1=top_0.U01.datain(18) I2=top_0.U01.datain(17) I3=top_0.U01.datain(16) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=top_0.U01.datain(19) I1=top_0.U01.datain(18) I2=top_0.U01.datain(17) I3=top_0.U01.datain(16) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(23) I1=top_0.U01.datain(22) I2=top_0.U01.datain(21) I3=top_0.U01.datain(20) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010110
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(28) I1=top_0.U01.datain(31) I2=top_0.U01.datain(30) I3=top_0.U01.datain(29) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(27) I1=top_0.U01.datain(24) I2=top_0.U01.datain(26) I3=top_0.U01.datain(25) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I1=top_0.U01.datain(4) I2=top_0.U01.datain(5) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001110000000000
+.subckt LUT4 I0=top_0.U01.datain(7) I1=top_0.U01.datain(6) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.U01.datain(3) I1=top_0.U01.datain(2) I2=top_0.U01.datain(1) I3=top_0.U01.datain(0) O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3 O=top_0.data_encout_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.U01.datain(99) I3=top_0.U01.datain(98) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(35) I3=top_0.U01.datain(34) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.U01.datain(96) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(97) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(96) I3=top_0.U01.datain(97) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(98) I3=top_0.U01.datain(99) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.U01.datain(102) I2=top_0.U01.datain(101) I3=top_0.U01.datain(100) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(34) I2=top_0.U01.datain(35) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_0.U01.datain(32) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(33) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(33) I1=top_0.U01.datain(32) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(34) I3=top_0.U01.datain(35) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(39) I1=top_0.U01.datain(38) I2=top_0.U01.datain(37) I3=top_0.U01.datain(36) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(33) I1=top_0.U01.datain(32) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(37) I1=top_0.U01.datain(36) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(43) I1=top_0.U01.datain(40) I2=top_0.U01.datain(42) I3=top_0.U01.datain(41) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(41) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.U01.datain(107) I2=top_0.U01.datain(106) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=top_0.U01.datain(106) I3=top_0.U01.datain(107) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(105) I3=top_0.U01.datain(104) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(96) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.U01.datain(115) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.U01.datain(114) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(114) I3=top_0.U01.datain(115) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(113) I3=top_0.U01.datain(112) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(119) I1=top_0.U01.datain(118) I2=top_0.U01.datain(116) I3=top_0.U01.datain(117) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(49) I3=top_0.U01.datain(48) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(50) I3=top_0.U01.datain(51) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_0.U01.datain(44) I1=top_0.U01.datain(47) I2=top_0.U01.datain(46) I3=top_0.U01.datain(45) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(40) I1=top_0.U01.datain(43) I2=top_0.U01.datain(42) I3=top_0.U01.datain(41) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(45) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(44) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(46) I3=top_0.U01.datain(47) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U01.datain(41) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(40) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(42) I3=top_0.U01.datain(43) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(104) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(105) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(109) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(108) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(111) I3=top_0.U01.datain(110) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U01.datain(107) I1=top_0.U01.datain(104) I2=top_0.U01.datain(106) I3=top_0.U01.datain(105) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(105) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(104) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(106) I3=top_0.U01.datain(107) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U01.datain(108) I1=top_0.U01.datain(110) I2=top_0.U01.datain(109) I3=top_0.U01.datain(111) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I1=top_0.U01.datain(107) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(43) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(121) I1=top_0.U01.datain(125) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101011001111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(127) I3=top_0.U01.datain(126) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(121) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=top_0.U01.datain(120) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.U01.datain(122) I3=top_0.U01.datain(123) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(59) I1=top_0.U01.datain(62) I2=top_0.U01.datain(60) I3=top_0.U01.datain(56) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=top_0.U01.datain(61) I1=top_0.U01.datain(63) I2=top_0.U01.datain(58) I3=top_0.U01.datain(57) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(123) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.U01.datain(122) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(59) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(58) O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3 O=top_0.data_encout_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(51) I1=top_0.U01.datain(50) I2=top_0.U01.datain(49) I3=top_0.U01.datain(48) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=top_0.U01.datain(35) I2=top_0.U01.datain(34) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=top_0.U01.datain(47) I2=top_0.U01.datain(46) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(69) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I0 I3=top_0.U01.datain(68) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.U01.datain(102) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(100) I3=top_0.U01.datain(101) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.U01.datain(102) I2=top_0.U01.datain(101) I3=top_0.U01.datain(100) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_0.U01.datain(39) I2=top_0.U01.datain(38) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.U01.datain(95) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.U01.datain(94) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(31) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U01.datain(30) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(30) I3=top_0.U01.datain(31) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(29) I3=top_0.U01.datain(28) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(127) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(126) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(123) I1=top_0.U01.datain(120) I2=top_0.U01.datain(121) I3=top_0.U01.datain(122) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(125) I3=top_0.U01.datain(124) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(60) I1=top_0.U01.datain(61) I2=top_0.U01.datain(63) I3=top_0.U01.datain(62) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.U01.datain(59) I1=top_0.U01.datain(56) I2=top_0.U01.datain(58) I3=top_0.U01.datain(57) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.U01.datain(47) I1=top_0.U01.datain(46) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(45) I3=top_0.U01.datain(44) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(109) I3=top_0.U01.datain(108) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(110) I3=top_0.U01.datain(111) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(76) I1=top_0.U01.datain(77) I2=top_0.U01.datain(79) I3=top_0.U01.datain(78) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(68) I3=top_0.U01.datain(69) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(67) I1=top_0.U01.datain(66) I2=top_0.U01.datain(65) I3=top_0.U01.datain(64) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(70) I3=top_0.U01.datain(71) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=top_0.U01.datain(119) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(118) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(115) I1=top_0.U01.datain(114) I2=top_0.U01.datain(112) I3=top_0.U01.datain(113) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(118) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(119) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(117) I3=top_0.U01.datain(116) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(52) I3=top_0.U01.datain(53) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U01.datain(51) I1=top_0.U01.datain(50) I2=top_0.U01.datain(48) I3=top_0.U01.datain(49) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(54) I3=top_0.U01.datain(55) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(15) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(14) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.U01.datain(39) I1=top_0.U01.datain(38) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.U01.datain(102) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(7) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.U01.datain(6) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(5) I1=top_0.U01.datain(4) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=top_0.U01.datain(20) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(23) I1=top_0.U01.datain(22) I2=top_0.U01.datain(21) I3=top_0.U01.datain(20) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(83) I1=top_0.U01.datain(82) I2=top_0.U01.datain(80) I3=top_0.U01.datain(81) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(87) I1=top_0.U01.datain(86) I2=top_0.U01.datain(85) I3=top_0.U01.datain(84) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(117) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(116) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(55) I1=top_0.U01.datain(54) I2=top_0.U01.datain(53) I3=top_0.U01.datain(52) O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3 O=top_0.data_encout_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(66) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(67) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(98) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.U01.datain(99) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(96) I3=top_0.U01.datain(97) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(34) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.U01.datain(35) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I1=top_0.U01.datain(2) I2=top_0.U01.datain(3) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001110000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_0.U01.datain(19) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O I3=top_0.U01.datain(18) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(74) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(75) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(73) I3=top_0.U01.datain(72) O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.U01.datain(42) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(106) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3 O=top_0.data_encout_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(71) I3=top_0.U01.datain(70) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.U01.datain(46) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_0.U01.datain(47) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(76) I1=top_0.U01.datain(78) I2=top_0.U01.datain(77) I3=top_0.U01.datain(79) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.U01.datain(6) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(7) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.U01.datain(38) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=top_0.U01.datain(39) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.U01.datain(102) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.U01.datain(103) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(68) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(69) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(77) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.U01.datain(76) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(109) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_0.U01.datain(108) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(45) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_0.U01.datain(44) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(103) I1=top_0.U01.datain(102) I2=top_0.U01.datain(100) I3=top_0.U01.datain(101) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(99) I1=top_0.U01.datain(98) I2=top_0.U01.datain(97) I3=top_0.U01.datain(96) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(39) I1=top_0.U01.datain(38) I2=top_0.U01.datain(36) I3=top_0.U01.datain(37) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(35) I1=top_0.U01.datain(34) I2=top_0.U01.datain(33) I3=top_0.U01.datain(32) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(39) I1=top_0.U01.datain(38) I2=top_0.U01.datain(37) I3=top_0.U01.datain(36) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.U01.datain(67) I3=top_0.U01.datain(66) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=top_0.U01.datain(2) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(3) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(1) I1=top_0.U01.datain(0) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=top_0.U01.datain(18) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(19) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100000001111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(64) I3=top_0.U01.datain(65) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(75) I1=top_0.U01.datain(72) I2=top_0.U01.datain(74) I3=top_0.U01.datain(73) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(76) I1=top_0.U01.datain(78) I2=top_0.U01.datain(77) I3=top_0.U01.datain(79) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(64) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(65) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(65) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(64) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(66) I3=top_0.U01.datain(67) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U01.datain(71) I1=top_0.U01.datain(70) I2=top_0.U01.datain(69) I3=top_0.U01.datain(68) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(19) I1=top_0.U01.datain(18) I2=top_0.U01.datain(16) I3=top_0.U01.datain(17) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(11) I1=top_0.U01.datain(8) I2=top_0.U01.datain(10) I3=top_0.U01.datain(9) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(12) I1=top_0.U01.datain(14) I2=top_0.U01.datain(13) I3=top_0.U01.datain(15) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(7) I1=top_0.U01.datain(6) I2=top_0.U01.datain(5) I3=top_0.U01.datain(4) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(3) I1=top_0.U01.datain(2) I2=top_0.U01.datain(0) I3=top_0.U01.datain(1) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=top_0.U01.datain(72) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U01.datain(73) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(73) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(72) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(74) I3=top_0.U01.datain(75) O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101000000
+.subckt LUT4 I0=top_0.U01.datain(95) I1=top_0.U01.datain(94) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(93) I3=top_0.U01.datain(92) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(91) I1=top_0.U01.datain(88) I2=top_0.U01.datain(89) I3=top_0.U01.datain(90) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000111111111
+.subckt LUT4 I0=top_0.U01.datain(92) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_0.U01.datain(93) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(94) I3=top_0.U01.datain(95) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.U01.datain(91) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(90) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(89) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(88) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.U01.datain(93) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_0.U01.datain(92) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(83) I1=top_0.U01.datain(82) I2=top_0.U01.datain(80) I3=top_0.U01.datain(81) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(83) I1=top_0.U01.datain(82) I2=top_0.U01.datain(80) I3=top_0.U01.datain(81) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(122) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(123) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(121) I3=top_0.U01.datain(120) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(124) I1=top_0.U01.datain(125) I2=top_0.U01.datain(126) I3=top_0.U01.datain(127) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(58) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(59) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(57) I3=top_0.U01.datain(56) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(60) I1=top_0.U01.datain(62) I2=top_0.U01.datain(61) I3=top_0.U01.datain(63) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(114) I3=top_0.U01.datain(115) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(113) I3=top_0.U01.datain(112) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(51) I1=top_0.U01.datain(50) I2=top_0.U01.datain(48) I3=top_0.U01.datain(49) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(55) I1=top_0.U01.datain(54) I2=top_0.U01.datain(53) I3=top_0.U01.datain(52) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.U01.datain(113) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(112) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(113) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(112) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(111) I3=top_0.U01.datain(110) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I2_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(29) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(28) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.U01.datain(30) I3=top_0.U01.datain(31) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(116) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.U01.datain(117) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(118) I3=top_0.U01.datain(119) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(55) I1=top_0.U01.datain(54) I2=top_0.U01.datain(52) I3=top_0.U01.datain(53) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(87) I1=top_0.U01.datain(86) I2=top_0.U01.datain(84) I3=top_0.U01.datain(85) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(23) I1=top_0.U01.datain(22) I2=top_0.U01.datain(20) I3=top_0.U01.datain(21) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_1_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.U01.datain(60) I1=top_0.U01.datain(62) I2=top_0.U01.datain(61) I3=top_0.U01.datain(63) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(55) I3=top_0.U01.datain(54) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.U01.datain(94) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_0.U01.datain(95) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.U01.datain(30) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(31) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(86) I1=top_0.U01.datain(84) I2=top_0.U01.datain(85) I3=top_0.U01.datain(87) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(22) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(23) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(20) I3=top_0.U01.datain(21) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.U01.datain(29) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.U01.datain(28) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_0.U01.datain(25) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(24) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(26) I3=top_0.U01.datain(27) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O_LUT4_I0_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I3=top_0.reset O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I0_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=top_0.U01.datain(126) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=top_0.U01.datain(127) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(56) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_0.U01.datain(57) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(58) I3=top_0.U01.datain(59) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(89) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.U01.datain(88) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_0.U01.datain(90) I3=top_0.U01.datain(91) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.U01.datain(26) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_0.U01.datain(27) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I2=top_0.reset I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(27) I1=top_0.U01.datain(24) I2=top_0.U01.datain(26) I3=top_0.U01.datain(25) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(82) I1=top_0.U01.datain(80) I2=top_0.U01.datain(81) I3=top_0.U01.datain(83) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.U01.datain(114) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.U01.datain(115) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(51) I3=top_0.U01.datain(50) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(87) I1=top_0.U01.datain(86) I2=top_0.U01.datain(84) I3=top_0.U01.datain(85) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.U01.datain(83) I1=top_0.U01.datain(80) I2=top_0.U01.datain(81) I3=top_0.U01.datain(82) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.U01.datain(90) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.U01.datain(91) I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(89) I3=top_0.U01.datain(88) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=top_0.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(92) I1=top_0.U01.datain(95) I2=top_0.U01.datain(94) I3=top_0.U01.datain(93) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.U01.datain(27) I3=top_0.U01.datain(26) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3_LUT4_I2_O O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I0_I2_LUT4_O_I2_LUT4_O_I1 I2=top_0.U01.datain(25) I3=top_0.U01.datain(24) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I3=top_0.U01.datain(22) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=top_0.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.U01.datain(87) I1=top_0.U01.datain(84) I2=top_0.U01.datain(85) I3=top_0.U01.datain(86) O=top_0.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=top_1.U011.datain(127) D=top_1.data_encin1_ff_CQZ_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(126) D=top_1.data_encin1_ff_CQZ_1_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(117) D=top_1.data_encin1_ff_CQZ_10_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(27) D=top_1.data_encin1_ff_CQZ_100_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(27) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_100_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(26) D=top_1.data_encin1_ff_CQZ_101_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(26) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_101_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(25) D=top_1.data_encin1_ff_CQZ_102_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(25) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_102_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(24) D=top_1.data_encin1_ff_CQZ_103_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(24) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_103_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(23) D=top_1.data_encin1_ff_CQZ_104_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(23) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_104_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(22) D=top_1.data_encin1_ff_CQZ_105_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(22) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_105_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(21) D=top_1.data_encin1_ff_CQZ_106_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(21) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_106_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(20) D=top_1.data_encin1_ff_CQZ_107_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(20) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_107_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(19) D=top_1.data_encin1_ff_CQZ_108_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(19) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_108_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(18) D=top_1.data_encin1_ff_CQZ_109_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(18) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_109_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(117) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(116) D=top_1.data_encin1_ff_CQZ_11_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(17) D=top_1.data_encin1_ff_CQZ_110_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(17) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_110_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(16) D=top_1.data_encin1_ff_CQZ_111_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(16) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_111_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(15) D=top_1.data_encin1_ff_CQZ_112_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(15) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_112_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(14) D=top_1.data_encin1_ff_CQZ_113_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(14) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_113_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(13) D=top_1.data_encin1_ff_CQZ_114_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(13) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_114_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(12) D=top_1.data_encin1_ff_CQZ_115_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(12) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_115_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(11) D=top_1.data_encin1_ff_CQZ_116_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(11) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_116_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(10) D=top_1.data_encin1_ff_CQZ_117_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(10) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_117_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(9) D=top_1.data_encin1_ff_CQZ_118_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(9) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_118_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(8) D=top_1.data_encin1_ff_CQZ_119_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(8) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_119_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(116) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(115) D=top_1.data_encin1_ff_CQZ_12_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(7) D=top_1.data_encin1_ff_CQZ_120_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(7) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_120_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(6) D=top_1.data_encin1_ff_CQZ_121_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(6) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_121_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(5) D=top_1.data_encin1_ff_CQZ_122_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(5) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_122_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(4) D=top_1.data_encin1_ff_CQZ_123_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(4) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_123_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(3) D=top_1.data_encin1_ff_CQZ_124_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(3) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_124_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(2) D=top_1.data_encin1_ff_CQZ_125_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(2) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_125_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(1) D=top_1.data_encin1_ff_CQZ_126_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(1) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_126_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(0) D=top_1.data_encin1_ff_CQZ_127_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(0) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_127_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(115) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(114) D=top_1.data_encin1_ff_CQZ_13_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(114) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(113) D=top_1.data_encin1_ff_CQZ_14_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(113) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(112) D=top_1.data_encin1_ff_CQZ_15_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(112) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(111) D=top_1.data_encin1_ff_CQZ_16_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(111) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(110) D=top_1.data_encin1_ff_CQZ_17_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(110) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(109) D=top_1.data_encin1_ff_CQZ_18_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(109) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(108) D=top_1.data_encin1_ff_CQZ_19_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(108) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(126) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(125) D=top_1.data_encin1_ff_CQZ_2_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(107) D=top_1.data_encin1_ff_CQZ_20_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(107) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(106) D=top_1.data_encin1_ff_CQZ_21_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(106) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(105) D=top_1.data_encin1_ff_CQZ_22_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(105) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(104) D=top_1.data_encin1_ff_CQZ_23_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(104) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(103) D=top_1.data_encin1_ff_CQZ_24_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(103) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(102) D=top_1.data_encin1_ff_CQZ_25_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(102) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(101) D=top_1.data_encin1_ff_CQZ_26_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(101) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(100) D=top_1.data_encin1_ff_CQZ_27_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(100) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(99) D=top_1.data_encin1_ff_CQZ_28_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(99) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(98) D=top_1.data_encin1_ff_CQZ_29_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(98) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(125) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(124) D=top_1.data_encin1_ff_CQZ_3_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(97) D=top_1.data_encin1_ff_CQZ_30_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(97) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(96) D=top_1.data_encin1_ff_CQZ_31_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(96) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(95) D=top_1.data_encin1_ff_CQZ_32_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(95) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_32_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(94) D=top_1.data_encin1_ff_CQZ_33_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(94) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_33_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(93) D=top_1.data_encin1_ff_CQZ_34_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(93) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_34_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(92) D=top_1.data_encin1_ff_CQZ_35_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(92) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_35_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(91) D=top_1.data_encin1_ff_CQZ_36_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(91) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_36_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(90) D=top_1.data_encin1_ff_CQZ_37_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(90) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_37_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(89) D=top_1.data_encin1_ff_CQZ_38_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(89) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_38_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(88) D=top_1.data_encin1_ff_CQZ_39_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(88) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_39_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(124) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(123) D=top_1.data_encin1_ff_CQZ_4_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(87) D=top_1.data_encin1_ff_CQZ_40_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(87) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_40_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(86) D=top_1.data_encin1_ff_CQZ_41_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(86) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_41_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(85) D=top_1.data_encin1_ff_CQZ_42_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(85) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_42_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(84) D=top_1.data_encin1_ff_CQZ_43_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(84) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_43_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(83) D=top_1.data_encin1_ff_CQZ_44_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(83) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_44_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(82) D=top_1.data_encin1_ff_CQZ_45_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(82) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_45_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(81) D=top_1.data_encin1_ff_CQZ_46_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(81) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_46_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(80) D=top_1.data_encin1_ff_CQZ_47_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(80) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_47_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(79) D=top_1.data_encin1_ff_CQZ_48_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(79) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_48_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(78) D=top_1.data_encin1_ff_CQZ_49_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(78) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_49_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(123) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(122) D=top_1.data_encin1_ff_CQZ_5_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(77) D=top_1.data_encin1_ff_CQZ_50_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(77) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_50_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(76) D=top_1.data_encin1_ff_CQZ_51_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(76) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_51_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(75) D=top_1.data_encin1_ff_CQZ_52_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(75) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_52_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(74) D=top_1.data_encin1_ff_CQZ_53_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(74) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_53_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(73) D=top_1.data_encin1_ff_CQZ_54_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(73) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_54_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(72) D=top_1.data_encin1_ff_CQZ_55_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(72) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_55_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(71) D=top_1.data_encin1_ff_CQZ_56_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(71) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_56_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(70) D=top_1.data_encin1_ff_CQZ_57_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(70) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_57_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(69) D=top_1.data_encin1_ff_CQZ_58_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(69) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_58_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(68) D=top_1.data_encin1_ff_CQZ_59_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(68) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_59_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(122) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(121) D=top_1.data_encin1_ff_CQZ_6_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(67) D=top_1.data_encin1_ff_CQZ_60_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(67) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_60_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(66) D=top_1.data_encin1_ff_CQZ_61_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(66) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_61_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(65) D=top_1.data_encin1_ff_CQZ_62_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(65) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_62_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(64) D=top_1.data_encin1_ff_CQZ_63_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(64) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_63_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(63) D=top_1.data_encin1_ff_CQZ_64_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(63) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_64_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(62) D=top_1.data_encin1_ff_CQZ_65_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(62) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_65_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(61) D=top_1.data_encin1_ff_CQZ_66_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(61) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_66_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(60) D=top_1.data_encin1_ff_CQZ_67_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(60) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_67_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(59) D=top_1.data_encin1_ff_CQZ_68_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(59) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_68_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(58) D=top_1.data_encin1_ff_CQZ_69_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(58) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_69_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(121) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(120) D=top_1.data_encin1_ff_CQZ_7_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(57) D=top_1.data_encin1_ff_CQZ_70_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(57) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_70_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(56) D=top_1.data_encin1_ff_CQZ_71_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(56) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_71_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(55) D=top_1.data_encin1_ff_CQZ_72_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(55) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_72_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(54) D=top_1.data_encin1_ff_CQZ_73_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(54) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_73_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(53) D=top_1.data_encin1_ff_CQZ_74_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(53) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_74_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(52) D=top_1.data_encin1_ff_CQZ_75_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(52) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_75_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(51) D=top_1.data_encin1_ff_CQZ_76_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(51) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_76_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(50) D=top_1.data_encin1_ff_CQZ_77_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(50) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_77_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(49) D=top_1.data_encin1_ff_CQZ_78_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(49) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_78_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(48) D=top_1.data_encin1_ff_CQZ_79_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(48) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_79_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(120) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(119) D=top_1.data_encin1_ff_CQZ_8_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(47) D=top_1.data_encin1_ff_CQZ_80_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(47) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_80_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(46) D=top_1.data_encin1_ff_CQZ_81_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(46) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_81_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(45) D=top_1.data_encin1_ff_CQZ_82_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(45) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_82_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(44) D=top_1.data_encin1_ff_CQZ_83_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(44) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_83_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(43) D=top_1.data_encin1_ff_CQZ_84_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(43) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_84_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(42) D=top_1.data_encin1_ff_CQZ_85_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(42) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_85_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(41) D=top_1.data_encin1_ff_CQZ_86_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(41) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_86_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(40) D=top_1.data_encin1_ff_CQZ_87_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(40) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_87_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(39) D=top_1.data_encin1_ff_CQZ_88_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(39) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_88_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(38) D=top_1.data_encin1_ff_CQZ_89_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(38) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_89_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(119) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(118) D=top_1.data_encin1_ff_CQZ_9_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U011.datain(37) D=top_1.data_encin1_ff_CQZ_90_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(37) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_90_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(36) D=top_1.data_encin1_ff_CQZ_91_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(36) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_91_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(35) D=top_1.data_encin1_ff_CQZ_92_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(35) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_92_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(34) D=top_1.data_encin1_ff_CQZ_93_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(34) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_93_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(33) D=top_1.data_encin1_ff_CQZ_94_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(33) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_94_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(32) D=top_1.data_encin1_ff_CQZ_95_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(32) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_95_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(31) D=top_1.data_encin1_ff_CQZ_96_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(31) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_96_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(30) D=top_1.data_encin1_ff_CQZ_97_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(30) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_97_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(29) D=top_1.data_encin1_ff_CQZ_98_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(29) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_98_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U011.datain(28) D=top_1.data_encin1_ff_CQZ_99_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:66.3-79.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(28) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_99_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(118) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain1(127) I3=top_0.reset O=top_1.data_encin1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(127) D=top_1.data_encin_ff_CQZ_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(126) D=top_1.data_encin_ff_CQZ_1_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(117) D=top_1.data_encin_ff_CQZ_10_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(27) D=top_1.data_encin_ff_CQZ_100_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(27) I3=top_0.reset O=top_1.data_encin_ff_CQZ_100_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(26) D=top_1.data_encin_ff_CQZ_101_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(26) I3=top_0.reset O=top_1.data_encin_ff_CQZ_101_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(25) D=top_1.data_encin_ff_CQZ_102_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(25) I3=top_0.reset O=top_1.data_encin_ff_CQZ_102_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(24) D=top_1.data_encin_ff_CQZ_103_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(24) I3=top_0.reset O=top_1.data_encin_ff_CQZ_103_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(23) D=top_1.data_encin_ff_CQZ_104_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(23) I3=top_0.reset O=top_1.data_encin_ff_CQZ_104_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(22) D=top_1.data_encin_ff_CQZ_105_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(22) I3=top_0.reset O=top_1.data_encin_ff_CQZ_105_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(21) D=top_1.data_encin_ff_CQZ_106_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(21) I3=top_0.reset O=top_1.data_encin_ff_CQZ_106_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(20) D=top_1.data_encin_ff_CQZ_107_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(20) I3=top_0.reset O=top_1.data_encin_ff_CQZ_107_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(19) D=top_1.data_encin_ff_CQZ_108_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(19) I3=top_0.reset O=top_1.data_encin_ff_CQZ_108_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(18) D=top_1.data_encin_ff_CQZ_109_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(18) I3=top_0.reset O=top_1.data_encin_ff_CQZ_109_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(117) I3=top_0.reset O=top_1.data_encin_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(116) D=top_1.data_encin_ff_CQZ_11_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(17) D=top_1.data_encin_ff_CQZ_110_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(17) I3=top_0.reset O=top_1.data_encin_ff_CQZ_110_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(16) D=top_1.data_encin_ff_CQZ_111_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(16) I3=top_0.reset O=top_1.data_encin_ff_CQZ_111_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(15) D=top_1.data_encin_ff_CQZ_112_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(15) I3=top_0.reset O=top_1.data_encin_ff_CQZ_112_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(14) D=top_1.data_encin_ff_CQZ_113_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(14) I3=top_0.reset O=top_1.data_encin_ff_CQZ_113_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(13) D=top_1.data_encin_ff_CQZ_114_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(13) I3=top_0.reset O=top_1.data_encin_ff_CQZ_114_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(12) D=top_1.data_encin_ff_CQZ_115_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(12) I3=top_0.reset O=top_1.data_encin_ff_CQZ_115_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(11) D=top_1.data_encin_ff_CQZ_116_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(11) I3=top_0.reset O=top_1.data_encin_ff_CQZ_116_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(10) D=top_1.data_encin_ff_CQZ_117_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(10) I3=top_0.reset O=top_1.data_encin_ff_CQZ_117_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(9) D=top_1.data_encin_ff_CQZ_118_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(9) I3=top_0.reset O=top_1.data_encin_ff_CQZ_118_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(8) D=top_1.data_encin_ff_CQZ_119_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(8) I3=top_0.reset O=top_1.data_encin_ff_CQZ_119_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(116) I3=top_0.reset O=top_1.data_encin_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(115) D=top_1.data_encin_ff_CQZ_12_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(7) D=top_1.data_encin_ff_CQZ_120_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(7) I3=top_0.reset O=top_1.data_encin_ff_CQZ_120_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(6) D=top_1.data_encin_ff_CQZ_121_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(6) I3=top_0.reset O=top_1.data_encin_ff_CQZ_121_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(5) D=top_1.data_encin_ff_CQZ_122_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(5) I3=top_0.reset O=top_1.data_encin_ff_CQZ_122_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(4) D=top_1.data_encin_ff_CQZ_123_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(4) I3=top_0.reset O=top_1.data_encin_ff_CQZ_123_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(3) D=top_1.data_encin_ff_CQZ_124_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(3) I3=top_0.reset O=top_1.data_encin_ff_CQZ_124_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(2) D=top_1.data_encin_ff_CQZ_125_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(2) I3=top_0.reset O=top_1.data_encin_ff_CQZ_125_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(1) D=top_1.data_encin_ff_CQZ_126_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(1) I3=top_0.reset O=top_1.data_encin_ff_CQZ_126_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(0) D=top_1.data_encin_ff_CQZ_127_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(0) I3=top_0.reset O=top_1.data_encin_ff_CQZ_127_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(115) I3=top_0.reset O=top_1.data_encin_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(114) D=top_1.data_encin_ff_CQZ_13_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(114) I3=top_0.reset O=top_1.data_encin_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(113) D=top_1.data_encin_ff_CQZ_14_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(113) I3=top_0.reset O=top_1.data_encin_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(112) D=top_1.data_encin_ff_CQZ_15_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(112) I3=top_0.reset O=top_1.data_encin_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(111) D=top_1.data_encin_ff_CQZ_16_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(111) I3=top_0.reset O=top_1.data_encin_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(110) D=top_1.data_encin_ff_CQZ_17_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(110) I3=top_0.reset O=top_1.data_encin_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(109) D=top_1.data_encin_ff_CQZ_18_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(109) I3=top_0.reset O=top_1.data_encin_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(108) D=top_1.data_encin_ff_CQZ_19_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(108) I3=top_0.reset O=top_1.data_encin_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(126) I3=top_0.reset O=top_1.data_encin_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(125) D=top_1.data_encin_ff_CQZ_2_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(107) D=top_1.data_encin_ff_CQZ_20_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(107) I3=top_0.reset O=top_1.data_encin_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(106) D=top_1.data_encin_ff_CQZ_21_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(106) I3=top_0.reset O=top_1.data_encin_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(105) D=top_1.data_encin_ff_CQZ_22_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(105) I3=top_0.reset O=top_1.data_encin_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(104) D=top_1.data_encin_ff_CQZ_23_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(104) I3=top_0.reset O=top_1.data_encin_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(103) D=top_1.data_encin_ff_CQZ_24_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(103) I3=top_0.reset O=top_1.data_encin_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(102) D=top_1.data_encin_ff_CQZ_25_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(102) I3=top_0.reset O=top_1.data_encin_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(101) D=top_1.data_encin_ff_CQZ_26_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(101) I3=top_0.reset O=top_1.data_encin_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(100) D=top_1.data_encin_ff_CQZ_27_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(100) I3=top_0.reset O=top_1.data_encin_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(99) D=top_1.data_encin_ff_CQZ_28_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(99) I3=top_0.reset O=top_1.data_encin_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(98) D=top_1.data_encin_ff_CQZ_29_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(98) I3=top_0.reset O=top_1.data_encin_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(125) I3=top_0.reset O=top_1.data_encin_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(124) D=top_1.data_encin_ff_CQZ_3_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(97) D=top_1.data_encin_ff_CQZ_30_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(97) I3=top_0.reset O=top_1.data_encin_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(96) D=top_1.data_encin_ff_CQZ_31_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(96) I3=top_0.reset O=top_1.data_encin_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(95) D=top_1.data_encin_ff_CQZ_32_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(95) I3=top_0.reset O=top_1.data_encin_ff_CQZ_32_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(94) D=top_1.data_encin_ff_CQZ_33_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(94) I3=top_0.reset O=top_1.data_encin_ff_CQZ_33_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(93) D=top_1.data_encin_ff_CQZ_34_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(93) I3=top_0.reset O=top_1.data_encin_ff_CQZ_34_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(92) D=top_1.data_encin_ff_CQZ_35_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(92) I3=top_0.reset O=top_1.data_encin_ff_CQZ_35_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(91) D=top_1.data_encin_ff_CQZ_36_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(91) I3=top_0.reset O=top_1.data_encin_ff_CQZ_36_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(90) D=top_1.data_encin_ff_CQZ_37_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(90) I3=top_0.reset O=top_1.data_encin_ff_CQZ_37_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(89) D=top_1.data_encin_ff_CQZ_38_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(89) I3=top_0.reset O=top_1.data_encin_ff_CQZ_38_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(88) D=top_1.data_encin_ff_CQZ_39_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(88) I3=top_0.reset O=top_1.data_encin_ff_CQZ_39_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(124) I3=top_0.reset O=top_1.data_encin_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(123) D=top_1.data_encin_ff_CQZ_4_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(87) D=top_1.data_encin_ff_CQZ_40_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(87) I3=top_0.reset O=top_1.data_encin_ff_CQZ_40_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(86) D=top_1.data_encin_ff_CQZ_41_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(86) I3=top_0.reset O=top_1.data_encin_ff_CQZ_41_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(85) D=top_1.data_encin_ff_CQZ_42_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(85) I3=top_0.reset O=top_1.data_encin_ff_CQZ_42_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(84) D=top_1.data_encin_ff_CQZ_43_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(84) I3=top_0.reset O=top_1.data_encin_ff_CQZ_43_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(83) D=top_1.data_encin_ff_CQZ_44_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(83) I3=top_0.reset O=top_1.data_encin_ff_CQZ_44_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(82) D=top_1.data_encin_ff_CQZ_45_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(82) I3=top_0.reset O=top_1.data_encin_ff_CQZ_45_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(81) D=top_1.data_encin_ff_CQZ_46_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(81) I3=top_0.reset O=top_1.data_encin_ff_CQZ_46_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(80) D=top_1.data_encin_ff_CQZ_47_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(80) I3=top_0.reset O=top_1.data_encin_ff_CQZ_47_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(79) D=top_1.data_encin_ff_CQZ_48_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(79) I3=top_0.reset O=top_1.data_encin_ff_CQZ_48_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(78) D=top_1.data_encin_ff_CQZ_49_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(78) I3=top_0.reset O=top_1.data_encin_ff_CQZ_49_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(123) I3=top_0.reset O=top_1.data_encin_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(122) D=top_1.data_encin_ff_CQZ_5_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(77) D=top_1.data_encin_ff_CQZ_50_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(77) I3=top_0.reset O=top_1.data_encin_ff_CQZ_50_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(76) D=top_1.data_encin_ff_CQZ_51_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(76) I3=top_0.reset O=top_1.data_encin_ff_CQZ_51_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(75) D=top_1.data_encin_ff_CQZ_52_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(75) I3=top_0.reset O=top_1.data_encin_ff_CQZ_52_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(74) D=top_1.data_encin_ff_CQZ_53_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(74) I3=top_0.reset O=top_1.data_encin_ff_CQZ_53_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(73) D=top_1.data_encin_ff_CQZ_54_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(73) I3=top_0.reset O=top_1.data_encin_ff_CQZ_54_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(72) D=top_1.data_encin_ff_CQZ_55_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(72) I3=top_0.reset O=top_1.data_encin_ff_CQZ_55_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(71) D=top_1.data_encin_ff_CQZ_56_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(71) I3=top_0.reset O=top_1.data_encin_ff_CQZ_56_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(70) D=top_1.data_encin_ff_CQZ_57_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(70) I3=top_0.reset O=top_1.data_encin_ff_CQZ_57_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(69) D=top_1.data_encin_ff_CQZ_58_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(69) I3=top_0.reset O=top_1.data_encin_ff_CQZ_58_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(68) D=top_1.data_encin_ff_CQZ_59_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(68) I3=top_0.reset O=top_1.data_encin_ff_CQZ_59_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(122) I3=top_0.reset O=top_1.data_encin_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(121) D=top_1.data_encin_ff_CQZ_6_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(67) D=top_1.data_encin_ff_CQZ_60_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(67) I3=top_0.reset O=top_1.data_encin_ff_CQZ_60_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(66) D=top_1.data_encin_ff_CQZ_61_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(66) I3=top_0.reset O=top_1.data_encin_ff_CQZ_61_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(65) D=top_1.data_encin_ff_CQZ_62_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(65) I3=top_0.reset O=top_1.data_encin_ff_CQZ_62_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(64) D=top_1.data_encin_ff_CQZ_63_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(64) I3=top_0.reset O=top_1.data_encin_ff_CQZ_63_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(63) D=top_1.data_encin_ff_CQZ_64_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(63) I3=top_0.reset O=top_1.data_encin_ff_CQZ_64_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(62) D=top_1.data_encin_ff_CQZ_65_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(62) I3=top_0.reset O=top_1.data_encin_ff_CQZ_65_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(61) D=top_1.data_encin_ff_CQZ_66_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(61) I3=top_0.reset O=top_1.data_encin_ff_CQZ_66_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(60) D=top_1.data_encin_ff_CQZ_67_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(60) I3=top_0.reset O=top_1.data_encin_ff_CQZ_67_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(59) D=top_1.data_encin_ff_CQZ_68_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(59) I3=top_0.reset O=top_1.data_encin_ff_CQZ_68_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(58) D=top_1.data_encin_ff_CQZ_69_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(58) I3=top_0.reset O=top_1.data_encin_ff_CQZ_69_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(121) I3=top_0.reset O=top_1.data_encin_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(120) D=top_1.data_encin_ff_CQZ_7_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(57) D=top_1.data_encin_ff_CQZ_70_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(57) I3=top_0.reset O=top_1.data_encin_ff_CQZ_70_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(56) D=top_1.data_encin_ff_CQZ_71_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(56) I3=top_0.reset O=top_1.data_encin_ff_CQZ_71_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(55) D=top_1.data_encin_ff_CQZ_72_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(55) I3=top_0.reset O=top_1.data_encin_ff_CQZ_72_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(54) D=top_1.data_encin_ff_CQZ_73_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(54) I3=top_0.reset O=top_1.data_encin_ff_CQZ_73_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(53) D=top_1.data_encin_ff_CQZ_74_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(53) I3=top_0.reset O=top_1.data_encin_ff_CQZ_74_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(52) D=top_1.data_encin_ff_CQZ_75_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(52) I3=top_0.reset O=top_1.data_encin_ff_CQZ_75_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(51) D=top_1.data_encin_ff_CQZ_76_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(51) I3=top_0.reset O=top_1.data_encin_ff_CQZ_76_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(50) D=top_1.data_encin_ff_CQZ_77_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(50) I3=top_0.reset O=top_1.data_encin_ff_CQZ_77_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(49) D=top_1.data_encin_ff_CQZ_78_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(49) I3=top_0.reset O=top_1.data_encin_ff_CQZ_78_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(48) D=top_1.data_encin_ff_CQZ_79_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(48) I3=top_0.reset O=top_1.data_encin_ff_CQZ_79_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(120) I3=top_0.reset O=top_1.data_encin_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(119) D=top_1.data_encin_ff_CQZ_8_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(47) D=top_1.data_encin_ff_CQZ_80_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(47) I3=top_0.reset O=top_1.data_encin_ff_CQZ_80_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(46) D=top_1.data_encin_ff_CQZ_81_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(46) I3=top_0.reset O=top_1.data_encin_ff_CQZ_81_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(45) D=top_1.data_encin_ff_CQZ_82_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(45) I3=top_0.reset O=top_1.data_encin_ff_CQZ_82_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(44) D=top_1.data_encin_ff_CQZ_83_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(44) I3=top_0.reset O=top_1.data_encin_ff_CQZ_83_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(43) D=top_1.data_encin_ff_CQZ_84_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(43) I3=top_0.reset O=top_1.data_encin_ff_CQZ_84_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(42) D=top_1.data_encin_ff_CQZ_85_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(42) I3=top_0.reset O=top_1.data_encin_ff_CQZ_85_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(41) D=top_1.data_encin_ff_CQZ_86_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(41) I3=top_0.reset O=top_1.data_encin_ff_CQZ_86_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(40) D=top_1.data_encin_ff_CQZ_87_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(40) I3=top_0.reset O=top_1.data_encin_ff_CQZ_87_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(39) D=top_1.data_encin_ff_CQZ_88_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(39) I3=top_0.reset O=top_1.data_encin_ff_CQZ_88_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(38) D=top_1.data_encin_ff_CQZ_89_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(38) I3=top_0.reset O=top_1.data_encin_ff_CQZ_89_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(119) I3=top_0.reset O=top_1.data_encin_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(118) D=top_1.data_encin_ff_CQZ_9_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.U01.datain(37) D=top_1.data_encin_ff_CQZ_90_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(37) I3=top_0.reset O=top_1.data_encin_ff_CQZ_90_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(36) D=top_1.data_encin_ff_CQZ_91_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(36) I3=top_0.reset O=top_1.data_encin_ff_CQZ_91_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(35) D=top_1.data_encin_ff_CQZ_92_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(35) I3=top_0.reset O=top_1.data_encin_ff_CQZ_92_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(34) D=top_1.data_encin_ff_CQZ_93_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(34) I3=top_0.reset O=top_1.data_encin_ff_CQZ_93_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(33) D=top_1.data_encin_ff_CQZ_94_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(33) I3=top_0.reset O=top_1.data_encin_ff_CQZ_94_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(32) D=top_1.data_encin_ff_CQZ_95_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(32) I3=top_0.reset O=top_1.data_encin_ff_CQZ_95_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(31) D=top_1.data_encin_ff_CQZ_96_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(31) I3=top_0.reset O=top_1.data_encin_ff_CQZ_96_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(30) D=top_1.data_encin_ff_CQZ_97_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(30) I3=top_0.reset O=top_1.data_encin_ff_CQZ_97_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(29) D=top_1.data_encin_ff_CQZ_98_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(29) I3=top_0.reset O=top_1.data_encin_ff_CQZ_98_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.U01.datain(28) D=top_1.data_encin_ff_CQZ_99_D QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v:86.5-95.10|/home/tpagarani/git/yosys-testing/Designs/multi_enc_decx2x4/rtl/topenc_decx2.v:33.2-46.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(28) I3=top_0.reset O=top_1.data_encin_ff_CQZ_99_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(118) I3=top_0.reset O=top_1.data_encin_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.datain(127) I3=top_0.reset O=top_1.data_encin_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=top_1.data_encout1(6) D=top_1.data_encout1_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout1(5) D=top_1.data_encout1_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout1(4) D=top_1.data_encout1_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout1(3) D=top_1.data_encout1_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout1(2) D=top_1.data_encout1_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout1(1) D=top_1.data_encout1_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout1(0) D=top_1.data_encout1_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001011111111
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3 O=top_1.data_encout1_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U011.datain(39) I1=top_1.U011.datain(38) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.U011.datain(103) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_1.U011.datain(102) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I2=top_1.U011.datain(96) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2 I1=top_1.U011.datain(119) I2=top_1.U011.datain(118) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_1.U011.datain(122) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(123) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.U011.datain(107) I3=top_1.U011.datain(106) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.U011.datain(104) I1=top_1.U011.datain(105) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U011.datain(108) I1=top_1.U011.datain(111) I2=top_1.U011.datain(110) I3=top_1.U011.datain(109) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U011.datain(97) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.U011.datain(96) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.U011.datain(97) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(99) I1=top_1.U011.datain(98) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(105) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(104) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(108) I3=top_1.U011.datain(109) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U011.datain(81) I1=top_1.U011.datain(80) I2=top_1.U011.datain(83) I3=top_1.U011.datain(82) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=top_1.U011.datain(82) I1=top_1.U011.datain(81) I2=top_1.U011.datain(80) I3=top_1.U011.datain(83) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(112) I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.U011.datain(113) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 I3=top_1.U011.datain(112) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2 I2=top_1.U011.datain(114) I3=top_1.U011.datain(115) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=top_1.U011.datain(67) I1=top_1.U011.datain(66) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U011.datain(71) I1=top_1.U011.datain(70) I2=top_1.U011.datain(69) I3=top_1.U011.datain(68) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(100) I3=top_1.U011.datain(101) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_1.U011.datain(98) I3=top_1.U011.datain(99) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(98) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.U011.datain(99) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(96) I3=top_1.U011.datain(97) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(67) I3=top_1.U011.datain(66) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(64) I3=top_1.U011.datain(65) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(117) I1=top_0.reset I2=top_1.U011.datain(116) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(121) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(120) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(109) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.U011.datain(108) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(110) I3=top_1.U011.datain(111) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(104) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.U011.datain(105) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(106) I3=top_1.U011.datain(107) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(95) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=top_1.U011.datain(94) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(93) I3=top_1.U011.datain(92) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(55) I1=top_1.U011.datain(53) I2=top_1.U011.datain(52) I3=top_1.U011.datain(54) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(118) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.U011.datain(119) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(116) I3=top_1.U011.datain(117) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U011.datain(117) I1=top_1.U011.datain(116) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U011.datain(115) I1=top_1.U011.datain(114) I2=top_1.U011.datain(113) I3=top_1.U011.datain(112) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=top_1.U011.datain(87) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.U011.datain(86) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(65) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=top_1.U011.datain(64) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1_LUT4_O_I3_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=top_1.U011.datain(99) I3=top_1.U011.datain(98) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3 O=top_1.data_encout1_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(56) I1=top_0.reset I2=top_1.U011.datain(57) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(89) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.U011.datain(88) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(90) I3=top_1.U011.datain(91) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(92) I1=top_1.U011.datain(95) I2=top_1.U011.datain(94) I3=top_1.U011.datain(93) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U011.datain(24) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I3=top_1.U011.datain(25) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(26) I3=top_1.U011.datain(27) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(16) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.U011.datain(17) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(18) I3=top_1.U011.datain(19) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(17) I1=top_0.reset I2=top_1.U011.datain(16) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(60) I1=top_0.reset I2=top_1.U011.datain(61) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.U011.datain(62) I3=top_1.U011.datain(63) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(28) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I3=top_1.U011.datain(29) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(30) I3=top_1.U011.datain(31) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(24) I1=top_1.U011.datain(27) I2=top_1.U011.datain(26) I3=top_1.U011.datain(25) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(3) I1=top_1.U011.datain(2) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(7) I1=top_1.U011.datain(6) I2=top_1.U011.datain(5) I3=top_1.U011.datain(4) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U011.datain(3) I1=top_1.U011.datain(2) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I2=top_1.U011.datain(3) I3=top_1.U011.datain(2) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(0) I3=top_1.U011.datain(1) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(18) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.U011.datain(19) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(16) I3=top_1.U011.datain(17) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(19) I1=top_1.U011.datain(18) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(23) I1=top_1.U011.datain(22) I2=top_1.U011.datain(21) I3=top_1.U011.datain(20) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(28) I1=top_1.U011.datain(31) I2=top_1.U011.datain(30) I3=top_1.U011.datain(29) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=top_1.U011.datain(49) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_1.U011.datain(48) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_1.U011.datain(35) I3=top_1.U011.datain(34) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(39) I1=top_1.U011.datain(38) I2=top_1.U011.datain(37) I3=top_1.U011.datain(36) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=top_1.U011.datain(50) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_1.U011.datain(51) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.U011.datain(25) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(24) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(28) I3=top_1.U011.datain(29) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.U011.datain(89) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(88) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2 I2=top_1.U011.datain(92) I3=top_1.U011.datain(93) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U011.datain(90) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(91) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(89) I3=top_1.U011.datain(88) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(58) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.U011.datain(59) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U011.datain(26) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(27) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(25) I3=top_1.U011.datain(24) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=top_1.U011.datain(95) I2=top_1.U011.datain(94) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=top_1.U011.datain(90) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(91) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(83) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(82) I1=top_1.U011.datain(81) I2=top_0.reset I3=top_1.U011.datain(80) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3 O=top_1.data_encout1_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_1.U011.datain(12) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=top_1.U011.datain(12) I1=top_1.U011.datain(9) I2=top_1.U011.datain(8) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=top_1.U011.datain(12) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(13) I2=top_1.U011.datain(14) I3=top_1.U011.datain(15) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(73) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(72) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(8) I1=top_1.U011.datain(10) I2=top_1.U011.datain(9) I3=top_1.U011.datain(11) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_1.U011.datain(31) I1=top_0.reset I2=top_1.U011.datain(30) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_1.U011.datain(47) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O I3=top_1.U011.datain(46) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1 I2=top_1.U011.datain(45) I3=top_1.U011.datain(44) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3 O=top_1.data_encout1_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_1.U011.datain(53) I1=top_0.reset I2=top_1.U011.datain(52) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U011.datain(85) I1=top_1.U011.datain(84) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(86) I3=top_1.U011.datain(87) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U011.datain(23) I1=top_1.U011.datain(22) I2=top_1.U011.datain(21) I3=top_1.U011.datain(20) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.U011.datain(5) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O I3=top_1.U011.datain(4) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(4) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(5) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(6) I3=top_1.U011.datain(7) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(37) I1=top_0.reset I2=top_1.U011.datain(36) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(38) I3=top_1.U011.datain(39) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_1.U011.datain(34) I3=top_1.U011.datain(35) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(71) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.U011.datain(70) I1=top_1.U011.datain(69) I2=top_0.reset I3=top_1.U011.datain(68) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(101) I1=top_0.reset I2=top_1.U011.datain(100) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3 O=top_1.data_encout1_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U011.datain(72) I1=top_1.U011.datain(75) I2=top_1.U011.datain(73) I3=top_1.U011.datain(74) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(90) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.U011.datain(91) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.U011.datain(27) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I3=top_1.U011.datain(26) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(8) I1=top_1.U011.datain(11) I2=top_1.U011.datain(9) I3=top_1.U011.datain(10) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(19) I1=top_0.reset I2=top_1.U011.datain(18) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(2) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I3=top_1.U011.datain(3) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(22) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.U011.datain(23) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(6) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O I3=top_1.U011.datain(7) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(70) I2=top_0.reset I3=top_1.U011.datain(71) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_I3_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3 O=top_1.data_encout1_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=top_1.U011.datain(85) I3=top_1.U011.datain(84) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(23) I1=top_1.U011.datain(22) I2=top_1.U011.datain(20) I3=top_1.U011.datain(21) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(19) I1=top_1.U011.datain(18) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(8) I1=top_1.U011.datain(11) I2=top_1.U011.datain(10) I3=top_1.U011.datain(9) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(14) I3=top_1.U011.datain(15) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(13) I2=top_0.reset I3=top_1.U011.datain(12) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(71) I1=top_1.U011.datain(70) I2=top_1.U011.datain(68) I3=top_1.U011.datain(69) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I3 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(45) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=top_1.U011.datain(44) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.U011.datain(76) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_1.U011.datain(48) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(49) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=top_1.U011.datain(50) I3=top_1.U011.datain(51) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(80) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(81) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(82) I3=top_1.U011.datain(83) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(72) I1=top_1.U011.datain(74) I2=top_1.U011.datain(73) I3=top_1.U011.datain(75) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.U011.datain(76) I1=top_1.U011.datain(79) I2=top_1.U011.datain(78) I3=top_1.U011.datain(77) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=top_1.U011.datain(42) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(43) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.U011.datain(72) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(73) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(74) I3=top_1.U011.datain(75) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=top_1.U011.datain(64) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(65) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(66) I3=top_1.U011.datain(67) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(67) I1=top_1.U011.datain(66) I2=top_1.U011.datain(65) I3=top_1.U011.datain(64) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(83) I1=top_1.U011.datain(82) I2=top_1.U011.datain(81) I3=top_1.U011.datain(80) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U011.datain(32) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_1.U011.datain(33) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(3) I1=top_1.U011.datain(2) I2=top_1.U011.datain(0) I3=top_1.U011.datain(1) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(8) I1=top_0.reset I2=top_1.U011.datain(9) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(10) I3=top_1.U011.datain(11) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(106) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.U011.datain(107) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2 I3=top_1.U011.datain(77) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010001000
+.subckt LUT4 I0=top_1.U011.datain(72) I1=top_1.U011.datain(75) I2=top_1.U011.datain(74) I3=top_1.U011.datain(73) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2 I2=top_1.U011.datain(76) I3=top_1.U011.datain(77) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I2=top_1.U011.datain(78) I3=top_1.U011.datain(79) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(79) I3=top_1.U011.datain(78) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(78) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 I3=top_1.U011.datain(79) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I2=top_1.U011.datain(77) I3=top_1.U011.datain(76) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U011.datain(46) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(47) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(111) I3=top_1.U011.datain(110) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(109) I3=top_1.U011.datain(108) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(104) I1=top_1.U011.datain(107) I2=top_1.U011.datain(106) I3=top_1.U011.datain(105) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=top_1.U011.datain(30) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(31) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(29) I3=top_1.U011.datain(28) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U011.datain(94) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(95) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U011.datain(38) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(39) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.U011.datain(37) I1=top_1.U011.datain(36) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U011.datain(102) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(103) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=top_1.U011.datain(86) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(87) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(84) I3=top_1.U011.datain(85) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=top_1.U011.datain(14) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(15) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(15) I1=top_0.reset I2=top_1.U011.datain(14) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(13) I3=top_1.U011.datain(12) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(70) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(71) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(68) I3=top_1.U011.datain(69) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_1.U011.datain(6) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_I3_I0_LUT4_O_I3_LUT4_I2_O I2=top_1.U011.datain(7) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I2=top_1.U011.datain(4) I3=top_1.U011.datain(5) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(23) I3=top_1.U011.datain(22) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(20) I3=top_1.U011.datain(21) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I3=top_0.reset O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(93) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2 I3=top_1.U011.datain(92) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(94) I3=top_1.U011.datain(95) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(88) I1=top_1.U011.datain(91) I2=top_1.U011.datain(90) I3=top_1.U011.datain(89) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I2_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U011.datain(124) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.U011.datain(125) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(124) I3=top_1.U011.datain(125) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(127) I3=top_1.U011.datain(126) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(120) I1=top_1.U011.datain(123) I2=top_1.U011.datain(122) I3=top_1.U011.datain(121) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I0 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(112) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.U011.datain(113) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(52) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(53) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(52) I3=top_1.U011.datain(53) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(54) I3=top_1.U011.datain(55) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(63) I3=top_1.U011.datain(62) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.U011.datain(60) I1=top_1.U011.datain(61) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U011.datain(56) I1=top_1.U011.datain(59) I2=top_1.U011.datain(58) I3=top_1.U011.datain(57) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2 I2=top_1.U011.datain(119) I3=top_1.U011.datain(118) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(54) I1=top_1.U011.datain(53) I2=top_1.U011.datain(52) I3=top_1.U011.datain(55) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.U011.datain(126) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.U011.datain(127) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(125) I3=top_1.U011.datain(124) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_1.U011.datain(37) I3=top_1.U011.datain(36) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.U011.datain(100) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(101) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(102) I3=top_1.U011.datain(103) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U011.datain(59) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_1.U011.datain(58) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(57) I3=top_1.U011.datain(56) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U011.datain(123) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.U011.datain(122) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_1.U011.datain(116) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3 I2=top_1.U011.datain(117) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(117) I1=top_1.U011.datain(116) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(124) I1=top_1.U011.datain(126) I2=top_1.U011.datain(125) I3=top_1.U011.datain(127) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(118) I3=top_1.U011.datain(119) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(114) I1=top_1.U011.datain(113) I2=top_1.U011.datain(112) I3=top_1.U011.datain(115) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.U011.datain(51) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(50) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=top_1.U011.datain(50) I3=top_1.U011.datain(51) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(48) I3=top_1.U011.datain(49) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U011.datain(60) I1=top_1.U011.datain(63) I2=top_1.U011.datain(62) I3=top_1.U011.datain(61) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I3_O I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U011.datain(113) I1=top_1.U011.datain(112) I2=top_1.U011.datain(115) I3=top_1.U011.datain(114) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.U011.datain(35) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100001100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U011.datain(34) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(32) I3=top_1.U011.datain(33) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.U011.datain(45) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.U011.datain(44) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1 I2=top_1.U011.datain(46) I3=top_1.U011.datain(47) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(40) I3=top_1.U011.datain(41) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=top_1.U011.datain(57) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(56) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U011.datain(58) I3=top_1.U011.datain(59) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_1.U011.datain(60) I3=top_1.U011.datain(61) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U011.datain(127) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.U011.datain(126) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(63) I1=top_0.reset I2=top_1.U011.datain(62) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I0 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U011.datain(40) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_1.U011.datain(41) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_1.U011.datain(42) I3=top_1.U011.datain(43) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=top_1.U011.datain(43) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O_LUT4_I2_1_O_LUT4_I2_O I3=top_1.U011.datain(42) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U011.datain(40) I1=top_1.U011.datain(41) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U011.datain(44) I1=top_1.U011.datain(47) I2=top_1.U011.datain(46) I3=top_1.U011.datain(45) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=top_1.U011.datain(120) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=top_1.U011.datain(121) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(122) I3=top_1.U011.datain(123) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U011.datain(110) I3=top_1.U011.datain(111) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_1.U011.datain(33) I1=top_0.reset I2=top_1.U011.datain(32) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U011.datain(40) I1=top_1.U011.datain(43) I2=top_1.U011.datain(42) I3=top_1.U011.datain(41) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U011.datain(34) I3=top_1.U011.datain(35) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0_LUT4_I1_I0 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I1 I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I0 I2=top_1.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U011.datain(122) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U011.datain(123) I3=top_1.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U011.datain(121) I3=top_1.U011.datain(120) O=top_1.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=top_1.data_encout(6) D=top_1.data_encout_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout(5) D=top_1.data_encout_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout(4) D=top_1.data_encout_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout(3) D=top_1.data_encout_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout(2) D=top_1.data_encout_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout(1) D=top_1.data_encout_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_1.data_encout(0) D=top_1.data_encout_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3 O=top_1.data_encout_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(123) I3=top_1.U01.datain(122) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(63) I3=top_1.U01.datain(62) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(61) I3=top_1.U01.datain(60) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(110) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(111) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(109) I3=top_1.U01.datain(108) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(104) I1=top_1.U01.datain(107) I2=top_1.U01.datain(106) I3=top_1.U01.datain(105) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_1.U01.datain(98) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_1.U01.datain(99) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(35) I2=top_0.reset I3=top_1.U01.datain(34) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(32) I3=top_1.U01.datain(33) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(102) I1=top_1.U01.datain(101) I2=top_1.U01.datain(100) I3=top_1.U01.datain(103) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.U01.datain(39) I1=top_0.reset I2=top_1.U01.datain(38) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(36) I3=top_1.U01.datain(37) O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011101110000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3 O=top_1.data_encout_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=top_1.U01.datain(49) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.U01.datain(48) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U01.datain(51) I1=top_1.U01.datain(50) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U01.datain(114) I1=top_1.U01.datain(113) I2=top_1.U01.datain(112) I3=top_1.U01.datain(115) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(118) I3=top_1.U01.datain(119) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(115) I1=top_1.U01.datain(113) I2=top_1.U01.datain(112) I3=top_1.U01.datain(114) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(80) I1=top_1.U01.datain(83) I2=top_1.U01.datain(81) I3=top_1.U01.datain(82) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(87) I1=top_1.U01.datain(86) I2=top_1.U01.datain(85) I3=top_1.U01.datain(84) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(61) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(60) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(62) I3=top_1.U01.datain(63) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(51) I1=top_0.reset I2=top_1.U01.datain(50) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(48) I3=top_1.U01.datain(49) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(51) I3=top_1.U01.datain(50) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(52) I3=top_1.U01.datain(53) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(60) I1=top_1.U01.datain(63) I2=top_1.U01.datain(62) I3=top_1.U01.datain(61) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U01.datain(56) I1=top_1.U01.datain(59) I2=top_1.U01.datain(58) I3=top_1.U01.datain(57) O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3 O=top_1.data_encout_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=top_1.U01.datain(25) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(24) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(26) I3=top_1.U01.datain(27) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(28) I1=top_1.U01.datain(31) I2=top_1.U01.datain(30) I3=top_1.U01.datain(29) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(28) I3=top_1.U01.datain(29) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(30) I3=top_1.U01.datain(31) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.U01.datain(57) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(56) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(60) I3=top_1.U01.datain(61) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_1.U01.datain(40) I1=top_0.reset I2=top_1.U01.datain(41) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=top_1.U01.datain(42) I3=top_1.U01.datain(43) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(56) I1=top_0.reset I2=top_1.U01.datain(57) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(58) I3=top_1.U01.datain(59) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_I2_I0 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(122) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(123) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(121) I3=top_1.U01.datain(120) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(88) I1=top_0.reset I2=top_1.U01.datain(89) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(90) I3=top_1.U01.datain(91) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(24) I1=top_0.reset I2=top_1.U01.datain(25) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.U01.datain(72) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(73) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(72) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.U01.datain(73) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(75) I3=top_1.U01.datain(74) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(79) I1=top_1.U01.datain(78) I2=top_1.U01.datain(77) I3=top_1.U01.datain(76) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=top_1.U01.datain(41) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(40) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(44) I3=top_1.U01.datain(45) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_1.U01.datain(13) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(12) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(59) I1=top_0.reset I2=top_1.U01.datain(58) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(91) I1=top_0.reset I2=top_1.U01.datain(90) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(89) I3=top_1.U01.datain(88) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(26) I2=top_0.reset I3=top_1.U01.datain(27) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(25) I3=top_1.U01.datain(24) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3 O=top_1.data_encout_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(5) I1=top_1.U01.datain(4) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.U01.datain(7) I1=top_1.U01.datain(6) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(4) I3=top_1.U01.datain(5) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(3) I1=top_1.U01.datain(2) I2=top_1.U01.datain(1) I3=top_1.U01.datain(0) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(8) I1=top_1.U01.datain(11) I2=top_1.U01.datain(9) I3=top_1.U01.datain(10) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(69) I1=top_1.U01.datain(71) I2=top_1.U01.datain(70) I3=top_1.U01.datain(68) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110110000
+.subckt LUT4 I0=top_1.U01.datain(37) I1=top_1.U01.datain(36) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(38) I3=top_1.U01.datain(39) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=top_1.U01.datain(119) I1=top_1.U01.datain(118) I2=top_1.U01.datain(116) I3=top_1.U01.datain(117) O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(21) I1=top_0.reset I2=top_1.U01.datain(20) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(53) I1=top_0.reset I2=top_1.U01.datain(52) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3 O=top_1.data_encout_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_1.U01.datain(43) I1=top_0.reset I2=top_1.U01.datain(42) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_1.U01.datain(66) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 I2=top_1.U01.datain(67) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(69) I1=top_1.U01.datain(68) I2=top_1.U01.datain(71) I3=top_1.U01.datain(70) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U01.datain(67) I1=top_0.reset I2=top_1.U01.datain(66) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(64) I3=top_1.U01.datain(65) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U01.datain(75) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(74) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(72) I3=top_1.U01.datain(73) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_1.U01.datain(11) I1=top_1.U01.datain(9) I2=top_1.U01.datain(10) I3=top_1.U01.datain(8) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.U01.datain(11) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I3=top_1.U01.datain(10) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.U01.datain(9) I3=top_1.U01.datain(8) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(19) I1=top_1.U01.datain(18) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.U01.datain(16) I1=top_1.U01.datain(17) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(2) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_1.U01.datain(3) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U01.datain(35) I1=top_0.reset I2=top_1.U01.datain(34) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(63) I1=top_0.reset I2=top_1.U01.datain(62) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(50) I3=top_1.U01.datain(51) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(54) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.U01.datain(55) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U01.datain(47) I1=top_1.U01.datain(46) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.U01.datain(79) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_1.U01.datain(78) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U01.datain(77) I1=top_1.U01.datain(76) I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.U01.datain(74) I1=top_1.U01.datain(73) I2=top_1.U01.datain(72) I3=top_1.U01.datain(75) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(30) I2=top_0.reset I3=top_1.U01.datain(31) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U01.datain(23) I1=top_0.reset I2=top_1.U01.datain(22) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U01.datain(7) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(6) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(14) I2=top_0.reset I3=top_1.U01.datain(15) O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3 O=top_1.data_encout_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=top_1.U01.datain(30) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(31) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.U01.datain(28) I1=top_1.U01.datain(29) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U01.datain(24) I1=top_1.U01.datain(27) I2=top_1.U01.datain(26) I3=top_1.U01.datain(25) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(47) I3=top_1.U01.datain(46) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.U01.datain(44) I1=top_1.U01.datain(45) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U01.datain(86) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(87) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.U01.datain(38) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_1.U01.datain(39) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(20) I3=top_1.U01.datain(21) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(23) I2=top_0.reset I3=top_1.U01.datain(22) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(15) I2=top_0.reset I3=top_1.U01.datain(14) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(13) I3=top_1.U01.datain(12) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(6) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(7) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(27) I3=top_1.U01.datain(26) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(58) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(59) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(57) I3=top_1.U01.datain(56) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(75) I2=top_0.reset I3=top_1.U01.datain(74) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(3) I3=top_1.U01.datain(2) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(19) I3=top_1.U01.datain(18) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(10) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(11) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(80) I1=top_1.U01.datain(82) I2=top_1.U01.datain(81) I3=top_1.U01.datain(83) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(48) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.U01.datain(49) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(80) I1=top_0.reset I2=top_1.U01.datain(81) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=top_1.U01.datain(82) I3=top_1.U01.datain(83) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(92) I1=top_1.U01.datain(95) I2=top_1.U01.datain(94) I3=top_1.U01.datain(93) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000011111111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(18) I3=top_1.U01.datain(19) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(17) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(16) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.U01.datain(17) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(16) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(18) I3=top_1.U01.datain(19) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(23) I1=top_1.U01.datain(22) I2=top_1.U01.datain(21) I3=top_1.U01.datain(20) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(3) I1=top_1.U01.datain(2) I2=top_1.U01.datain(0) I3=top_1.U01.datain(1) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(0) I3=top_1.U01.datain(1) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(7) I1=top_1.U01.datain(6) I2=top_1.U01.datain(5) I3=top_1.U01.datain(4) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U01.datain(12) I1=top_1.U01.datain(15) I2=top_1.U01.datain(13) I3=top_1.U01.datain(14) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U01.datain(8) I1=top_1.U01.datain(11) I2=top_1.U01.datain(10) I3=top_1.U01.datain(9) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_1.U01.datain(32) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(33) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U01.datain(33) I1=top_0.reset I2=top_1.U01.datain(32) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(34) I3=top_1.U01.datain(35) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(39) I1=top_1.U01.datain(38) I2=top_1.U01.datain(37) I3=top_1.U01.datain(36) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(34) I3=top_1.U01.datain(35) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(40) I1=top_1.U01.datain(43) I2=top_1.U01.datain(42) I3=top_1.U01.datain(41) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U01.datain(44) I1=top_1.U01.datain(47) I2=top_1.U01.datain(46) I3=top_1.U01.datain(45) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=top_1.U01.datain(12) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(13) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(14) I3=top_1.U01.datain(15) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(22) I3=top_1.U01.datain(23) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(16) I1=top_1.U01.datain(19) I2=top_1.U01.datain(18) I3=top_1.U01.datain(17) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(21) I3=top_1.U01.datain(20) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(22) I3=top_1.U01.datain(23) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(69) I1=top_1.U01.datain(68) I2=top_1.U01.datain(71) I3=top_1.U01.datain(70) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.U01.datain(69) I1=top_1.U01.datain(68) I2=top_1.U01.datain(70) I3=top_1.U01.datain(71) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.U01.datain(68) I1=top_1.U01.datain(71) I2=top_1.U01.datain(70) I3=top_1.U01.datain(69) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(5) I3=top_1.U01.datain(4) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=top_1.U01.datain(36) I1=top_1.U01.datain(37) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_I1_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(28) I1=top_0.reset I2=top_1.U01.datain(29) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=top_1.U01.datain(44) I1=top_0.reset I2=top_1.U01.datain(45) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.U01.datain(46) I3=top_1.U01.datain(47) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(76) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(77) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=top_1.U01.datain(78) I3=top_1.U01.datain(79) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_1.U01.datain(54) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(55) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0_LUT4_O_I1 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(53) I3=top_1.U01.datain(52) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(54) I3=top_1.U01.datain(55) O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(84) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(85) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U01.datain(87) I1=top_1.U01.datain(86) I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=top_1.U01.datain(42) I1=top_1.U01.datain(43) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=top_1.U01.datain(40) I1=top_1.U01.datain(41) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U01.datain(106) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(107) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U01.datain(107) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O I3=top_1.U01.datain(106) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(105) I3=top_1.U01.datain(104) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(108) I1=top_1.U01.datain(111) I2=top_1.U01.datain(110) I3=top_1.U01.datain(109) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(101) I1=top_1.U01.datain(100) I2=top_1.U01.datain(103) I3=top_1.U01.datain(102) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(96) I3=top_1.U01.datain(97) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U01.datain(103) I1=top_1.U01.datain(102) I2=top_1.U01.datain(101) I3=top_1.U01.datain(100) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011101001
+.subckt LUT4 I0=top_1.U01.datain(103) I1=top_1.U01.datain(102) I2=top_1.U01.datain(100) I3=top_1.U01.datain(101) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(92) I1=top_0.reset I2=top_1.U01.datain(93) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=top_1.U01.datain(94) I3=top_1.U01.datain(95) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.reset I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(125) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=top_1.U01.datain(124) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(118) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.U01.datain(119) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.U01.datain(119) I1=top_1.U01.datain(118) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(116) I3=top_1.U01.datain(117) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(115) I1=top_1.U01.datain(114) I2=top_1.U01.datain(113) I3=top_1.U01.datain(112) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U01.datain(87) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.U01.datain(86) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.U01.datain(85) I1=top_1.U01.datain(84) I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U01.datain(80) I1=top_1.U01.datain(83) I2=top_1.U01.datain(82) I3=top_1.U01.datain(81) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=top_1.U01.datain(121) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=top_1.U01.datain(120) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(121) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=top_1.U01.datain(120) O=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(122) I3=top_1.U01.datain(123) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(124) I1=top_1.U01.datain(126) I2=top_1.U01.datain(127) I3=top_1.U01.datain(125) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=top_1.U01.datain(124) I3=top_1.U01.datain(125) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(127) I3=top_1.U01.datain(126) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(120) I1=top_1.U01.datain(123) I2=top_1.U01.datain(122) I3=top_1.U01.datain(121) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(93) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(92) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=top_1.U01.datain(88) I3=top_1.U01.datain(89) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(105) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(104) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.U01.datain(108) I3=top_1.U01.datain(109) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(127) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_1.U01.datain(126) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(95) I3=top_1.U01.datain(94) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(93) I3=top_1.U01.datain(92) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(88) I1=top_1.U01.datain(91) I2=top_1.U01.datain(90) I3=top_1.U01.datain(89) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.U01.datain(104) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O I3=top_1.U01.datain(105) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(106) I3=top_1.U01.datain(107) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(98) I3=top_1.U01.datain(99) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(96) I3=top_1.U01.datain(97) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I0_I1_LUT4_O_I3_LUT4_I3_1_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_1_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U01.datain(103) I1=top_1.U01.datain(102) I2=top_1.U01.datain(101) I3=top_1.U01.datain(100) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(97) I2=top_0.reset I3=top_1.U01.datain(96) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(96) I2=top_0.reset I3=top_1.U01.datain(97) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100010000
+.subckt LUT4 I0=top_1.U01.datain(111) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O I3=top_1.U01.datain(110) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I1_LUT4_O_I3 I2=top_1.U01.datain(66) I3=top_1.U01.datain(67) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.U01.datain(65) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=top_1.U01.datain(64) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U01.datain(77) I1=top_1.U01.datain(76) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I2_O_LUT4_I3_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(109) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(108) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(110) I3=top_1.U01.datain(111) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(90) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_1.U01.datain(91) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(64) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_1.U01.datain(65) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I0_LUT4_O_I2 I2=top_1.U01.datain(66) I3=top_1.U01.datain(67) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_1.U01.datain(78) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(79) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I0 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_0.reset I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=top_1.U01.datain(95) I1=top_0.reset I2=top_1.U01.datain(94) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(127) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.U01.datain(126) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.U01.datain(125) I3=top_1.U01.datain(124) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_1.U01.datain(81) I1=top_0.reset I2=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_1.U01.datain(80) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_1.U01.datain(85) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_1.U01.datain(84) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I1_LUT4_O_I1 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_1.U01.datain(99) I1=top_0.reset I2=top_1.U01.datain(98) I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_1.U01.datain(119) I1=top_1.U01.datain(118) I2=top_1.U01.datain(117) I3=top_1.U01.datain(116) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=top_1.U01.datain(119) I3=top_1.U01.datain(118) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(113) I3=top_1.U01.datain(112) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I0_O I3=top_1.U01.datain(118) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.U01.datain(112) I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_1.U01.datain(113) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_1.data_encout_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I0_O_LUT4_I3_1_O I1=top_1.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_O_I1 I2=top_1.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.U01.datain(114) I3=top_1.U01.datain(115) O=top_1.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=top_2.data_encin1(7) D=top_2.data_encin1_ff_CQZ_D(7) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin1(6) D=top_2.data_encin1_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin1(5) D=top_2.data_encin1_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin1(4) D=top_2.data_encin1_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin1(3) D=top_2.data_encin1_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin1(2) D=top_2.data_encin1_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin1(1) D=top_2.data_encin1_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin1(0) D=top_2.data_encin1_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3 O=top_2.data_encin1_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001110111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(0) I3=top_1.data_encout1(1) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=top_0.reset I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(1) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D(0) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 I3=top_1.data_encout1(3) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D(0) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(3) I3=top_1.data_encout1(2) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt LUT4 I0=top_1.data_encout1(0) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100001011
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_2_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(2) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3 O=top_2.data_encin1_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout1(1) I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I1=top_1.data_encout1(1) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(3) I3=top_1.data_encout1(2) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(2) I2=top_1.data_encout1(1) I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(1) I2=top_1.data_encout1(0) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(6) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100010001111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(1) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I2=top_1.data_encout1(1) I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(5) I2=top_1.data_encout1(4) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2 I2=top_0.reset I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(1) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(2) I3=top_1.data_encout1(3) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=top_1.data_encout1(0) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1(1) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encin1_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=top_0.reset I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D(1) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_0.reset I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111111111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D(0) I1=top_1.data_encout1(3) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(1) I2=top_0.reset I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(6) I3=top_1.data_encout1(5) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I1 I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=top_1.data_encout1(0) I1=top_1.data_encout1(1) I2=top_1.data_encout1(2) I3=top_1.data_encout1(3) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(3) I3=top_1.data_encout1(2) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I3 I3=top_1.data_encout1(1) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I1=top_1.data_encout1(2) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(1) I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(4) I2=top_1.data_encout1(5) I3=top_1.data_encout1(6) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(1) I2=top_1.data_encout1(0) I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_1.data_encout1(0) I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_0.reset I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I3=top_0.reset O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I3 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin1_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(6) I2=top_1.data_encout1(4) I3=top_1.data_encout1(5) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_1.data_encout1(1) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I2=top_1.data_encout1(3) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_1.data_encout1(1) I3=top_1.data_encout1(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 I2=top_1.data_encout1(0) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I2=top_1.data_encout1(0) I3=top_1.data_encout1(1) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111011000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_1.data_encout1(6) I2=top_1.data_encout1(5) I3=top_1.data_encout1(4) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=top_2.data_encin1_ff_CQZ_D(0) O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_1.data_encout1(1) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1_LUT4_O_I2 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_3_I3_LUT4_I2_I1_LUT4_O_I2_LUT4_I1_O I2=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011111111
+.subckt LUT4 I0=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin1_ff_CQZ_D(0) I3=top_2.data_encin1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encin1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=top_2.data_encin(7) D=top_2.data_encin_ff_CQZ_D(7) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin(6) D=top_2.data_encin_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin(5) D=top_2.data_encin_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin(4) D=top_2.data_encin_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin(3) D=top_2.data_encin_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin(2) D=top_2.data_encin_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin(1) D=top_2.data_encin_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encin(0) D=top_2.data_encin_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2 I3=top_0.data_encout(1) O=top_2.data_encin_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001110111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(3) I3=top_0.data_encout(2) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000111111111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 I2=top_0.data_encout(0) I3=top_0.data_encout(1) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011101000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(0) I3=top_0.data_encout(1) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_O I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011101110000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=top_0.data_encout(0) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011111111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=top_0.data_encout(2) I3=top_0.data_encout(3) O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100111011100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_0.reset O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3 O=top_2.data_encin_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(0) I3=top_0.data_encout(1) O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=top_0.data_encout(2) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I2=top_0.data_encout(3) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010011111111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I3_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=top_0.data_encout(1) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I2=top_0.reset I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I1 I2=top_0.data_encout(1) I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101011001111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I3_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(2) I3=top_0.data_encout(3) O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encin_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 I1=top_0.data_encout(2) I2=top_0.data_encout(3) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011101010101
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(6) I2=top_0.data_encout(5) I3=top_0.data_encout(4) O=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3 O=top_2.data_encin_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_0.data_encout(6) O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_0.data_encout(1) I1=top_0.data_encout(0) I2=top_0.data_encout(3) I3=top_0.data_encout(2) O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_0.data_encout(1) I1=top_0.data_encout(0) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(4) I2=top_0.data_encout(5) I3=top_0.data_encout(6) O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3 O=top_2.data_encin_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(6) I2=top_0.data_encout(4) I3=top_0.data_encout(5) O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O I3=top_0.reset O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(5) I2=top_0.data_encout(6) I3=top_0.data_encout(4) O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 I1=top_0.data_encout(6) I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I2 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1_LUT4_O_I2 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100010001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3 O=top_2.data_encin_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(3) I2=top_0.data_encout(2) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I2=top_0.data_encout(3) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(1) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I0_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=top_0.data_encout(0) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(6) I2=top_0.data_encout(5) I3=top_0.data_encout(4) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I0_LUT4_I3_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(3) I3=top_0.data_encout(2) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(4) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=top_0.data_encout(4) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=top_0.data_encout(4) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=top_0.reset I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(6) I3=top_0.data_encout(5) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(3) I3=top_0.data_encout(2) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_0.data_encout(3) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I2=top_0.data_encout(2) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100001100000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(1) I3=top_0.data_encout(0) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=top_0.data_encout(1) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I1 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=top_0.data_encout(2) I3=top_0.data_encout(3) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I0_LUT4_O_I0 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I3_LUT4_I3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(3) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.data_encout(2) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.data_encout(4) I2=top_0.data_encout(6) I3=top_0.data_encout(5) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_0.data_encout(6) I3=top_2.data_encin_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I2 O=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=top_0.data_encout(2) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I3=top_0.data_encout(3) O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_2_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I0_LUT4_I3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=top_2.data_encin_ff_CQZ_D_LUT4_O_3_I1 O=top_2.data_encin_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=top_2.data_encout1(6) D=top_2.data_encout1_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout1(5) D=top_2.data_encout1_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout1(4) D=top_2.data_encout1_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout1(3) D=top_2.data_encout1_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout1(2) D=top_2.data_encout1_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout1(1) D=top_2.data_encout1_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout1(0) D=top_2.data_encout1_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3 O=top_2.data_encout1_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010011111111
+.subckt LUT4 I0=top_2.data_encin1(0) I1=top_2.data_encin1(3) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=top_2.data_encin1(0) I1=top_2.data_encin1(1) I2=top_2.data_encin1(2) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000101011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(7) I2=top_2.data_encin1(6) I3=top_2.data_encin1(4) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(1) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 I3=top_2.data_encin1(0) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin1(6) I1=top_0.reset I2=top_2.data_encin1(7) I3=top_2.data_encin1(4) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 I2=top_2.data_encin1(5) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_2.data_encin1(5) I1=top_2.data_encin1(4) I2=top_2.data_encin1(7) I3=top_2.data_encin1(6) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0 I1=top_0.reset I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3 O=top_2.data_encout1_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_2.data_encin1(2) I1=top_2.data_encin1(1) I2=top_2.data_encin1(0) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101111111111
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=top_2.data_encin1(6) I1=top_2.data_encin1(7) I2=top_2.data_encin1(5) I3=top_2.data_encin1(4) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I2 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_I1_O I1=top_2.data_encin1(3) I2=top_0.reset I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000101
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3_LUT4_O_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3 O=top_2.data_encout1_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encin1(0) I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=top_2.data_encin1(0) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(2) I2=top_2.data_encin1(1) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin1(7) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001101011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(0) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_I3_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1 O=top_2.data_encout1_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2 I3=top_2.data_encin1(2) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(0) I3=top_2.data_encin1(1) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(1) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encin1(2) I1=top_2.data_encin1(0) I2=top_2.data_encin1(1) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(2) I2=top_2.data_encin1(3) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 I2=top_2.data_encin1(2) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(1) I3=top_2.data_encin1(0) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I0 I2=top_0.reset I3=top_2.data_encin1(1) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(0) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(2) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3 O=top_2.data_encout1_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_0.reset I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 I2=top_0.reset I3=top_2.data_encin1(7) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111110001
+.subckt LUT4 I0=top_2.data_encin1(0) I1=top_2.data_encin1(2) I2=top_2.data_encin1(1) I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I0 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(2) I2=top_2.data_encin1(3) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(2) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I2 I3=top_2.data_encin1(3) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001110101111
+.subckt LUT4 I0=top_2.data_encin1(6) I1=top_2.data_encin1(5) I2=top_2.data_encin1(4) I3=top_2.data_encin1(7) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111110000000
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I0_LUT4_O_I1 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin1(0) I1=top_2.data_encin1(3) I2=top_2.data_encin1(1) I3=top_2.data_encin1(2) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I1=top_2.data_encin1(5) I2=top_2.data_encin1(4) I3=top_2.data_encin1(6) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(0) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 O=top_2.data_encout1_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(7) I3=top_0.reset O=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I2_LUT4_I1_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1_LUT4_I1_O O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0 I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=top_2.data_encin1(4) I1=top_2.data_encin1(7) I2=top_2.data_encin1(6) I3=top_2.data_encin1(5) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin1(5) I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(0) I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_6_I3 I3=top_2.data_encin1(5) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin1(4) I2=top_2.data_encin1(7) I3=top_2.data_encin1(5) O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I3_O I2=top_2.data_encout1_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3_LUT4_I1_O I3=top_2.data_encout1_ff_CQZ_D_LUT4_O_I2_LUT4_I1_I3 O=top_2.data_encout1_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt ff CQZ=top_2.data_encout(6) D=top_2.data_encout_ff_CQZ_D(6) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout(5) D=top_2.data_encout_ff_CQZ_D(5) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout(4) D=top_2.data_encout_ff_CQZ_D(4) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout(3) D=top_2.data_encout_ff_CQZ_D(3) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout(2) D=top_2.data_encout_ff_CQZ_D(2) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout(1) D=top_2.data_encout_ff_CQZ_D(1) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=top_2.data_encout(0) D=top_2.data_encout_ff_CQZ_D(0) QCK=top_0.clock QEN=$auto$hilomap.cc:39:hilomap_worker$237633 QRT=dataout1_0_net_0(108) QST=dataout1_0_net_0(108)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1 I2=top_2.data_encin(6) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011111111
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3 O=top_2.data_encout_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010011111111
+.subckt LUT4 I0=top_2.data_encin(3) I1=top_2.data_encin(0) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0 I1=top_2.data_encin(1) I2=top_2.data_encin(2) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I2_O O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100000111111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000111111111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3 O=top_2.data_encout_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1 I2=top_0.reset I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin(5) I2=top_2.data_encin(6) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin(5) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I1=top_2.data_encin(5) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2 I3=top_2.data_encin(6) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000011010101
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encin(1) I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin(4) I2=top_2.data_encin(7) I3=top_2.data_encin(5) O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin(5) O=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3 O=top_2.data_encout_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=top_2.data_encin(7) O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin(3) I1=top_2.data_encin(1) I2=top_2.data_encin(0) I3=top_2.data_encin(2) O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0 I1=top_2.data_encin(7) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_0.reset I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encin(1) I2=top_2.data_encin(2) I3=top_2.data_encin(3) O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101011000000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I0 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3 O=top_2.data_encout_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111111111111
+.subckt LUT4 I0=top_2.data_encin(7) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_2.data_encin(1) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1 I2=top_0.reset I3=top_2.data_encin(7) O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1 I2=top_2.data_encin(1) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encin(2) I2=top_2.data_encin(3) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000011111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_0.reset I1=top_2.data_encin(7) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=top_2.data_encin(2) I1=top_2.data_encin(1) I2=top_2.data_encin(3) I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encin(7) I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encin(0) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1 O=top_2.data_encout_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O I1=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encin(3) I2=top_2.data_encin(2) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I3=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3 O=top_2.data_encout_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=top_2.data_encin(0) I2=top_0.reset I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encin(1) I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin(7) I1=top_2.data_encin(4) I2=top_2.data_encin(5) I3=top_2.data_encin(6) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I2=top_0.reset I3=top_2.data_encin(7) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_2.data_encin(2) I1=top_2.data_encin(0) I2=top_2.data_encin(3) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encin(7) I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101111
+.subckt LUT4 I0=top_2.data_encin(1) I1=top_2.data_encin(2) I2=top_2.data_encin(3) I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I3 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=top_0.reset I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000111111111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I1_LUT4_I2_O I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=top_2.data_encin(7) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=top_2.data_encin(3) I1=top_2.data_encin(2) I2=top_2.data_encin(0) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encin(0) I1=top_2.data_encin(2) I2=top_2.data_encin(3) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=top_2.data_encin(7) I3=top_2.data_encin(1) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_2.data_encin(0) I1=top_0.reset I2=top_2.data_encin(3) I3=top_2.data_encin(2) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin(1) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin(0) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin(3) I3=top_2.data_encin(2) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin(7) I3=top_2.data_encin(4) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101111110000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I2_LUT4_O_I1 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I2_LUT4_I0_O I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I0_LUT4_O_I0 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_3_I3_LUT4_O_I0_LUT4_O_I2 I3=top_0.reset O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=top_2.data_encin(6) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=dataout1_0_net_0(108) I2=top_2.data_encin(5) I3=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=dataout1_0_net_0(108) I1=top_2.data_encin(4) I2=top_2.data_encin(7) I3=top_2.data_encin(6) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=top_2.data_encout_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I1=top_2.data_encout_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I2=top_2.data_encin(6) I3=top_2.data_encin(7) O=top_2.data_encout_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.end
diff --git a/BENCHMARK/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v b/BENCHMARK/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v
new file mode 100644
index 0000000..717c0a6
--- /dev/null
+++ b/BENCHMARK/multi_enc_decx2x4/rtl/TOP_multi_enc_decx2x4.v
@@ -0,0 +1,110 @@
+//////////////////////////////////////////////////////////////////////
+// Created by SmartDesign Tue Jan 16 17:22:21 2018
+// Version: v11.8 11.8.0.26
+//////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 100ps
+
+// TOP_multi_enc_decx2x4
+module  multi_enc_decx2x4(
+    // Inputs
+    clock,
+    datain,
+    datain1,
+    datain1_0,
+    datain_0,
+    reset,
+    // Outputs
+    dataout,
+    dataout1,
+    dataout1_0,
+    dataout_0
+);
+
+//--------------------------------------------------------------------
+// Input
+//--------------------------------------------------------------------
+input          clock;
+input  [127:0] datain;
+input  [127:0] datain1;
+input  [127:0] datain1_0;
+input  [127:0] datain_0;
+input          reset;
+//--------------------------------------------------------------------
+// Output
+//--------------------------------------------------------------------
+output [127:0] dataout;
+output [127:0] dataout1;
+output [127:0] dataout1_0;
+output [127:0] dataout_0;
+//--------------------------------------------------------------------
+// Nets
+//--------------------------------------------------------------------
+wire           clock;
+wire   [127:0] datain;
+wire   [127:0] datain1;
+wire   [127:0] datain1_0;
+wire   [127:0] datain_0;
+wire   [127:0] dataout_net_0;
+wire   [127:0] dataout1_net_0;
+wire   [127:0] dataout1_0_net_0;
+wire   [127:0] dataout_0_net_0;
+wire           reset;
+wire   [127:0] top_0_dataout;
+wire   [127:0] top_1_dataout1;
+wire   [127:0] dataout_net_1;
+wire   [127:0] dataout1_net_1;
+wire   [127:0] dataout1_0_net_1;
+wire   [127:0] dataout_0_net_1;
+//--------------------------------------------------------------------
+// Top level output port assignments
+//--------------------------------------------------------------------
+assign dataout_net_1     = dataout_net_0;
+assign dataout[127:0]    = dataout_net_1;
+assign dataout1_net_1    = dataout1_net_0;
+assign dataout1[127:0]   = dataout1_net_1;
+assign dataout1_0_net_1  = dataout1_0_net_0;
+assign dataout1_0[127:0] = dataout1_0_net_1;
+assign dataout_0_net_1   = dataout_0_net_0;
+assign dataout_0[127:0]  = dataout_0_net_1;
+//--------------------------------------------------------------------
+// Component instances
+//--------------------------------------------------------------------
+//--------top
+top top_0(
+        // Inputs
+        .clock    ( clock ),
+        .reset    ( reset ),
+        .datain   ( datain ),
+        .datain1  ( datain1 ),
+        // Outputs
+        .dataout  ( top_0_dataout ),
+        .dataout1 ( dataout1_0_net_0 ) 
+        );
+
+//--------top
+top top_1(
+        // Inputs
+        .clock    ( clock ),
+        .reset    ( reset ),
+        .datain   ( datain_0 ),
+        .datain1  ( datain1_0 ),
+        // Outputs
+        .dataout  ( dataout_0_net_0 ),
+        .dataout1 ( top_1_dataout1 ) 
+        );
+
+//--------top
+top top_2(
+        // Inputs
+        .clock    ( clock ),
+        .reset    ( reset ),
+        .datain   ( top_0_dataout ),
+        .datain1  ( top_1_dataout1 ),
+        // Outputs
+        .dataout  ( dataout_net_0 ),
+        .dataout1 ( dataout1_net_0 ) 
+        );
+
+
+endmodule
diff --git a/BENCHMARK/multi_enc_decx2x4/rtl/decoder.v b/BENCHMARK/multi_enc_decx2x4/rtl/decoder.v
new file mode 100644
index 0000000..eb397a8
--- /dev/null
+++ b/BENCHMARK/multi_enc_decx2x4/rtl/decoder.v
@@ -0,0 +1,147 @@
+module decoder128(datain,dataout);
+
+input [6:0] datain;
+output [127:0] dataout;
+reg [127:0] dataout;
+
+always @(datain)
+
+begin
+
+	case (datain)
+	
+		7'b0000000: dataout  <=  128'h00000000000000000000000000000001;
+		7'b0000001: dataout  <=  128'h00000000000000000000000000000002;
+		7'b0000010: dataout  <=  128'h00000000000000000000000000000004;
+		7'b0000011: dataout  <=  128'h00000000000000000000000000000008;
+		7'b0000100: dataout  <=  128'h00000000000000000000000000000010;
+		7'b0000101: dataout  <=  128'h00000000000000000000000000000020;
+		7'b0000110: dataout  <=  128'h00000000000000000000000000000040;
+		7'b0000111: dataout	 <=  128'h00000000000000000000000000000080;
+		7'b0001000: dataout  <=  128'h00000000000000000000000000000100;
+		7'b0001001: dataout  <=  128'h00000000000000000000000000000200;
+		7'b0001010: dataout  <=  128'h00000000000000000000000000000400;
+		7'b0001011: dataout  <=  128'h00000000000000000000000000000800;
+		7'b0001100: dataout  <=  128'h00000000000000000000000000001000;
+		7'b0001101: dataout  <=  128'h00000000000000000000000000002000;
+		7'b0001110: dataout  <=  128'h00000000000000000000000000004000;
+		7'b0001111: dataout	 <=  128'h00000000000000000000000000008000; 		
+    7'b0010000: dataout  <=  128'h00000000000000000000000000010000;
+		7'b0010001: dataout  <=  128'h00000000000000000000000000020000;
+		7'b0010010: dataout  <=  128'h00000000000000000000000000040000;
+		7'b0010011: dataout  <=  128'h00000000000000000000000000080000;
+		7'b0010100: dataout  <=  128'h00000000000000000000000000100000;
+		7'b0010101: dataout  <=  128'h00000000000000000000000000200000;
+		7'b0010110: dataout  <=  128'h00000000000000000000000000400000;
+		7'b0010111: dataout  <=  128'h00000000000000000000000000800000;
+		7'b0011000: dataout	 <=  128'h00000000000000000000000001000000;
+		7'b0011001: dataout  <=  128'h00000000000000000000000002000000;
+		7'b0011010: dataout  <=  128'h00000000000000000000000004000000;
+		7'b0011011: dataout  <=  128'h00000000000000000000000008000000;
+		7'b0011100: dataout  <=  128'h00000000000000000000000010000000;
+		7'b0011101: dataout  <=  128'h00000000000000000000000020000000;
+		7'b0011110: dataout  <=  128'h00000000000000000000000040000000;
+		7'b0011111: dataout  <=  128'h00000000000000000000000080000000;                                        
+	  7'b0100000: dataout  <=  128'h00000000000000000000000100000000;                  
+	  7'b0100001: dataout  <=  128'h00000000000000000000000200000000;
+	  7'b0100010: dataout  <=  128'h00000000000000000000000400000000;
+	  7'b0100011: dataout  <=  128'h00000000000000000000000800000000;
+	  7'b0100100: dataout  <=  128'h00000000000000000000001000000000;
+	  7'b0100101: dataout  <=  128'h00000000000000000000002000000000;
+	  7'b0100110: dataout  <=  128'h00000000000000000000004000000000;
+	  7'b0100111: dataout  <=  128'h00000000000000000000008000000000;
+	  7'b0101000: dataout  <=  128'h00000000000000000000010000000000;
+	  7'b0101001: dataout  <=  128'h00000000000000000000020000000000;
+	  7'b0101010: dataout  <=  128'h00000000000000000000040000000000;
+	  7'b0101011: dataout  <=  128'h00000000000000000000080000000000;
+	  7'b0101100: dataout  <=  128'h00000000000000000000100000000000;
+	  7'b0101101: dataout  <=  128'h00000000000000000000200000000000;
+	  7'b0101110: dataout  <=  128'h00000000000000000000400000000000;
+	  7'b0101111: dataout  <=  128'h00000000000000000000800000000000;                                                                  
+	  7'b0110000: dataout  <=  128'h00000000000000000001000000000000;
+	  7'b0110001: dataout  <=  128'h00000000000000000002000000000000;
+	  7'b0110010: dataout  <=  128'h00000000000000000004000000000000;
+	  7'b0110011: dataout  <=  128'h00000000000000000008000000000000;
+	  7'b0110100: dataout  <=  128'h00000000000000000010000000000000;
+	  7'b0110101: dataout  <=  128'h00000000000000000020000000000000;
+	  7'b0110110: dataout  <=  128'h00000000000000000040000000000000;
+	  7'b0110111: dataout  <=  128'h00000000000000000080000000000000;
+	  7'b0111000: dataout  <=  128'h00000000000000000100000000000000;
+	  7'b0111001: dataout  <=  128'h00000000000000000200000000000000;
+	  7'b0111010: dataout  <=  128'h00000000000000000400000000000000;
+	  7'b0111011: dataout  <=  128'h00000000000000000800000000000000;
+	  7'b0111100: dataout  <=  128'h00000000000000001000000000000000;                  
+	  7'b0111101: dataout  <=  128'h00000000000000002000000000000000;                  
+	  7'b0111110: dataout  <=  128'h00000000000000004000000000000000;                  
+	  7'b0111111: dataout  <=  128'h00000000000000008000000000000000;                  
+	  7'b1000000: dataout  <=  128'h00000000000000010000000000000000;                   
+	  7'b1000001: dataout  <=  128'h00000000000000020000000000000000;                   
+	  7'b1000010: dataout  <=  128'h00000000000000040000000000000000;
+    7'b1000011: dataout  <=  128'h00000000000000080000000000000000;
+    7'b1000100: dataout  <=  128'h00000000000000100000000000000000;
+    7'b1000101: dataout  <=  128'h00000000000000200000000000000000;
+    7'b1000110: dataout  <=  128'h00000000000000400000000000000000;
+    7'b1000111: dataout  <=  128'h00000000000000800000000000000000;
+    7'b1001000: dataout  <=  128'h00000000000001000000000000000000;
+    7'b1001001: dataout  <=  128'h00000000000002000000000000000000;
+    7'b1001010: dataout  <=  128'h00000000000004000000000000000000;
+    7'b1001011: dataout  <=  128'h00000000000008000000000000000000;
+    7'b1001100: dataout  <=  128'h00000000000010000000000000000000;
+    7'b1001101: dataout  <=  128'h00000000000020000000000000000000;
+    7'b1001110: dataout  <=  128'h00000000000040000000000000000000;
+    7'b1001111: dataout  <=  128'h00000000000080000000000000000000;
+    7'b1010000: dataout  <=  128'h00000000000100000000000000000000;
+    7'b1010001: dataout  <=  128'h00000000000200000000000000000000;
+    7'b1010010: dataout  <=  128'h00000000000400000000000000000000;
+    7'b1010011: dataout  <=  128'h00000000000800000000000000000000;
+    7'b1010100: dataout  <=  128'h00000000001000000000000000000000;
+    7'b1010101: dataout  <=  128'h00000000002000000000000000000000;
+    7'b1010110: dataout  <=  128'h00000000004000000000000000000000;
+    7'b1010111: dataout  <=  128'h00000000008000000000000000000000;
+    7'b1011000: dataout  <=  128'h00000000010000000000000000000000;
+    7'b1011001: dataout  <=  128'h00000000020000000000000000000000;
+    7'b1011010: dataout  <=  128'h00000000040000000000000000000000;
+    7'b1011011: dataout  <=  128'h00000000080000000000000000000000;
+    7'b1011100: dataout  <=  128'h00000000100000000000000000000000;
+    7'b1011101: dataout  <=  128'h00000000200000000000000000000000;
+    7'b1011110: dataout  <=  128'h00000000400000000000000000000000;
+    7'b1011111: dataout  <=  128'h00000000800000000000000000000000;
+    7'b1100000: dataout  <=  128'h00000001000000000000000000000000;
+    7'b1100001: dataout  <=  128'h00000002000000000000000000000000;
+    7'b1100010: dataout  <=  128'h00000004000000000000000000000000;
+    7'b1100011: dataout  <=  128'h00000008000000000000000000000000;
+    7'b1100100: dataout  <=  128'h00000010000000000000000000000000;
+    7'b1100101: dataout  <=  128'h00000020000000000000000000000000;
+    7'b1100110: dataout  <=  128'h00000040000000000000000000000000;
+    7'b1100111: dataout  <=  128'h00000080000000000000000000000000;
+    7'b1101000: dataout  <=  128'h00000100000000000000000000000000;
+    7'b1101001: dataout  <=  128'h00000200000000000000000000000000;
+    7'b1101010: dataout  <=  128'h00000400000000000000000000000000;
+    7'b1101011: dataout  <=  128'h00000800000000000000000000000000;
+    7'b1101100: dataout  <=  128'h00001000000000000000000000000000;
+    7'b1101101: dataout  <=  128'h00002000000000000000000000000000;
+    7'b1101110: dataout  <=  128'h00004000000000000000000000000000;
+    7'b1101111: dataout  <=  128'h00008000000000000000000000000000;
+    7'b1110000: dataout  <=  128'h00010000000000000000000000000000;
+    7'b1110001: dataout  <=  128'h00020000000000000000000000000000;
+    7'b1110010: dataout  <=  128'h00040000000000000000000000000000;
+    7'b1110011: dataout  <=  128'h00080000000000000000000000000000;
+    7'b1110100: dataout  <=  128'h00100000000000000000000000000000;
+    7'b1110101: dataout  <=  128'h00200000000000000000000000000000;
+    7'b1110110: dataout  <=  128'h00400000000000000000000000000000;
+    7'b1110111: dataout  <=  128'h00800000000000000000000000000000;
+    7'b1111000: dataout  <=  128'h01000000000000000000000000000000;
+    7'b1111001: dataout  <=  128'h02000000000000000000000000000000;
+    7'b1111010: dataout  <=  128'h04000000000000000000000000000000;
+    7'b1111011: dataout  <=  128'h08000000000000000000000000000000;
+    7'b1111100: dataout  <=  128'h10000000000000000000000000000000;
+    7'b1111101: dataout  <=  128'h20000000000000000000000000000000;
+    7'b1111110: dataout  <=  128'h40000000000000000000000000000000;
+    7'b1111111:  dataout  <=  128'h80000000000000000000000000000000;
+    
+    
+    
+    default: dataout<=128'h0;
+		endcase
+end
+endmodule
diff --git a/BENCHMARK/multi_enc_decx2x4/rtl/encoder.v b/BENCHMARK/multi_enc_decx2x4/rtl/encoder.v
new file mode 100644
index 0000000..f2ac744
--- /dev/null
+++ b/BENCHMARK/multi_enc_decx2x4/rtl/encoder.v
@@ -0,0 +1,149 @@
+module encoder128(datain,dataout);
+
+input [127:0] datain;
+output [6:0] dataout;  
+reg [6:0] dataout;
+
+always @(datain)
+
+begin
+
+	case (datain)
+	
+         128'h00000000000000000000000000000001 :   dataout<=7'b0000000;
+         128'h00000000000000000000000000000002 :   dataout<=7'b0000001;
+         128'h00000000000000000000000000000004 :   dataout<=7'b0000010;
+         128'h00000000000000000000000000000008 :   dataout<=7'b0000011;
+         128'h00000000000000000000000000000010 :   dataout<=7'b0000100;
+         128'h00000000000000000000000000000020 :   dataout<=7'b0000101;
+         128'h00000000000000000000000000000040 :   dataout<=7'b0000110;
+         128'h00000000000000000000000000000080 :   dataout<=7'b0000111;
+         128'h00000000000000000000000000000100 :   dataout<=7'b0001000;
+         128'h00000000000000000000000000000200 :   dataout<=7'b0001001;
+         128'h00000000000000000000000000000400 :   dataout<=7'b0001010;
+         128'h00000000000000000000000000000800 :   dataout<=7'b0001011;
+         128'h00000000000000000000000000001000 :   dataout<=7'b0001000;
+         128'h00000000000000000000000000002000 :   dataout<=7'b0001101;
+         128'h00000000000000000000000000004000 :   dataout<=7'b0001110;
+         128'h00000000000000000000000000008000 :   dataout<=7'b0001111;
+         128'h00000000000000000000000000010000 :   dataout<=7'b0010000;
+         128'h00000000000000000000000000020000 :   dataout<=7'b0010001;
+         128'h00000000000000000000000000040000 :   dataout<=7'b0010010;
+         128'h00000000000000000000000000080000 :   dataout<=7'b0010011;
+         128'h00000000000000000000000000100000 :   dataout<=7'b0010100;
+         128'h00000000000000000000000000200000 :   dataout<=7'b0010101;
+         128'h00000000000000000000000000400000 :   dataout<=7'b0010110;
+         128'h00000000000000000000000000800000 :   dataout<=7'b0010111;
+         128'h00000000000000000000000001000000 :   dataout<=7'b0011000;
+         128'h00000000000000000000000002000000 :   dataout<=7'b0011001;
+         128'h00000000000000000000000004000000 :   dataout<=7'b0011010;
+         128'h00000000000000000000000008000000 :   dataout<=7'b0011011;
+         128'h00000000000000000000000010000000 :   dataout<=7'b0011000;
+         128'h00000000000000000000000020000000 :   dataout<=7'b0011101;
+         128'h00000000000000000000000040000000 :   dataout<=7'b0011110;
+         128'h00000000000000000000000080000000 :   dataout<=7'b0011111;
+   
+         128'h00000000000000000000000100000000 :   dataout<=7'b0100000;
+         128'h00000000000000000000000200000000 :   dataout<=7'b0100001;
+         128'h00000000000000000000000400000000 :   dataout<=7'b0100010;
+         128'h00000000000000000000000800000000 :   dataout<=7'b0100011;
+         128'h00000000000000000000001000000000 :   dataout<=7'b0100100;
+         128'h00000000000000000000002000000000 :   dataout<=7'b0100101;
+         128'h00000000000000000000004000000000 :   dataout<=7'b0100110;
+         128'h00000000000000000000008000000000 :   dataout<=7'b0100111;
+         128'h00000000000000000000010000000000 :   dataout<=7'b0101000;
+         128'h00000000000000000000020000000000 :   dataout<=7'b0101001;
+         128'h00000000000000000000040000000000 :   dataout<=7'b0101010;
+         128'h00000000000000000000080000000000 :   dataout<=7'b0101011;
+         128'h00000000000000000000100000000000 :   dataout<=7'b0101000;
+         128'h00000000000000000000200000000000 :   dataout<=7'b0101101;
+         128'h00000000000000000000400000000000 :   dataout<=7'b0101110;
+         128'h00000000000000000000800000000000 :   dataout<=7'b0101111;
+         128'h00000000000000000001000000000000 :   dataout<=7'b0110000;
+         128'h00000000000000000002000000000000 :   dataout<=7'b0110001;
+         128'h00000000000000000004000000000000 :   dataout<=7'b0110010;
+         128'h00000000000000000008000000000000 :   dataout<=7'b0110011;
+         128'h00000000000000000010000000000000 :   dataout<=7'b0110100;
+         128'h00000000000000000020000000000000 :   dataout<=7'b0110101;
+         128'h00000000000000000040000000000000 :   dataout<=7'b0110110;
+         128'h00000000000000000080000000000000 :   dataout<=7'b0110111;
+         128'h00000000000000000100000000000000 :   dataout<=7'b0111000;
+         128'h00000000000000000200000000000000 :   dataout<=7'b0111001;
+         128'h00000000000000000400000000000000 :   dataout<=7'b0111010;
+         128'h00000000000000000800000000000000 :   dataout<=7'b0111011;
+         128'h00000000000000001000000000000000 :   dataout<=7'b0111000;
+         128'h00000000000000002000000000000000 :   dataout<=7'b0111101;
+         128'h00000000000000004000000000000000 :   dataout<=7'b0111110;
+         128'h00000000000000008000000000000000 :   dataout<=7'b0111111;
+    
+         128'h00000000000000010000000000000000 :   dataout<=7'b1000000;
+         128'h00000000000000020000000000000000 :   dataout<=7'b1000001;
+         128'h00000000000000040000000000000000 :   dataout<=7'b1000010;
+         128'h00000000000000080000000000000000 :   dataout<=7'b1000011;
+         128'h00000000000000100000000000000000 :   dataout<=7'b1000100;
+         128'h00000000000000200000000000000000 :   dataout<=7'b1000101;
+         128'h00000000000000400000000000000000 :   dataout<=7'b1000110;
+         128'h00000000000000800000000000000000 :   dataout<=7'b1000111;
+         128'h00000000000001000000000000000000 :   dataout<=7'b1001000;
+         128'h00000000000002000000000000000000 :   dataout<=7'b1001001;
+         128'h00000000000004000000000000000000 :   dataout<=7'b1001010;
+         128'h00000000000008000000000000000000 :   dataout<=7'b1001011;
+         128'h00000000000010000000000000000000 :   dataout<=7'b1001000;
+         128'h00000000000020000000000000000000 :   dataout<=7'b1001101;
+         128'h00000000000040000000000000000000 :   dataout<=7'b1001110;
+         128'h00000000000080000000000000000000 :   dataout<=7'b1001111;
+         128'h00000000000100000000000000000000 :   dataout<=7'b1010000;
+         128'h00000000000200000000000000000000 :   dataout<=7'b1010001;
+         128'h00000000000400000000000000000000 :   dataout<=7'b1010010;
+         128'h00000000000800000000000000000000 :   dataout<=7'b1010011;
+         128'h00000000001000000000000000000000 :   dataout<=7'b1010100;
+         128'h00000000002000000000000000000000 :   dataout<=7'b1010101;
+         128'h00000000004000000000000000000000 :   dataout<=7'b1010110;
+         128'h00000000008000000000000000000000 :   dataout<=7'b1010111;
+         128'h00000000010000000000000000000000 :   dataout<=7'b1011000;
+         128'h00000000020000000000000000000000 :   dataout<=7'b1011001;
+         128'h00000000040000000000000000000000 :   dataout<=7'b1011010;
+         128'h00000000080000000000000000000000 :   dataout<=7'b1011011;
+         128'h00000000100000000000000000000000 :   dataout<=7'b1011000;
+         128'h00000000200000000000000000000000 :   dataout<=7'b1011101;
+         128'h00000000400000000000000000000000 :   dataout<=7'b1011110;
+         128'h00000000800000000000000000000000 :   dataout<=7'b1011111;
+   
+         128'h00000001000000000000000000000000 :   dataout<=7'b1100000;
+         128'h00000002000000000000000000000000 :   dataout<=7'b1100001;
+         128'h00000004000000000000000000000000 :   dataout<=7'b1100010;
+         128'h00000008000000000000000000000000 :   dataout<=7'b1100011;
+         128'h00000010000000000000000000000000 :   dataout<=7'b1100100;
+         128'h00000020000000000000000000000000 :   dataout<=7'b1100101;
+         128'h00000040000000000000000000000000 :   dataout<=7'b1100110;
+         128'h00000080000000000000000000000000 :   dataout<=7'b1100111;
+         128'h00000100000000000000000000000000 :   dataout<=7'b1101000;
+         128'h00000200000000000000000000000000 :   dataout<=7'b1101001;
+         128'h00000400000000000000000000000000 :   dataout<=7'b1101010;
+         128'h00000800000000000000000000000000 :   dataout<=7'b1101011;
+         128'h00001000000000000000000000000000 :   dataout<=7'b1101000;
+         128'h00002000000000000000000000000000 :   dataout<=7'b1101101;
+         128'h00004000000000000000000000000000 :   dataout<=7'b1101110;
+         128'h00008000000000000000000000000000 :   dataout<=7'b1101111;
+         128'h00010000000000000000000000000000 :   dataout<=7'b1110000;
+         128'h00020000000000000000000000000000 :   dataout<=7'b1110001;
+         128'h00040000000000000000000000000000 :   dataout<=7'b1110010;
+         128'h00080000000000000000000000000000 :   dataout<=7'b1110011;
+         128'h00100000000000000000000000000000 :   dataout<=7'b1110100;
+         128'h00200000000000000000000000000000 :   dataout<=7'b1110101;
+         128'h00400000000000000000000000000000 :   dataout<=7'b1110110;
+         128'h00800000000000000000000000000000 :   dataout<=7'b1110111;
+         128'h01000000000000000000000000000000 :   dataout<=7'b1111000;
+         128'h02000000000000000000000000000000 :   dataout<=7'b1111001;
+         128'h04000000000000000000000000000000 :   dataout<=7'b1111010;
+         128'h08000000000000000000000000000000 :   dataout<=7'b1111011;
+         128'h10000000000000000000000000000000 :   dataout<=7'b1111000;
+         128'h20000000000000000000000000000000 :   dataout<=7'b1111101;
+         128'h40000000000000000000000000000000 :   dataout<=7'b1111110;
+         128'h80000000000000000000000000000000 :   dataout<=7'b1111111;
+   
+
+    default: dataout<=7'b0000000;
+		endcase
+end
+endmodule
diff --git a/BENCHMARK/multi_enc_decx2x4/rtl/topenc_decx2.v b/BENCHMARK/multi_enc_decx2x4/rtl/topenc_decx2.v
new file mode 100644
index 0000000..866f8fc
--- /dev/null
+++ b/BENCHMARK/multi_enc_decx2x4/rtl/topenc_decx2.v
@@ -0,0 +1,104 @@
+
+module top(clock,reset,datain,dataout,datain1,dataout1);
+
+
+input clock,reset;
+
+input [127:0] datain;
+output [127:0] dataout;
+                          
+input [127:0] datain1;   
+output [127:0] dataout1; 
+                          
+wire [6:0] enc_out;
+reg  [127:0] data_encin;
+reg  [6:0] data_encout;
+
+wire [6:0] enc_out1;
+reg  [127:0] data_encin1;
+reg  [6:0] data_encout1;
+
+
+
+
+
+encoder128 U01(.datain(data_encin),.dataout(enc_out));
+decoder128 U02(.datain(data_encout),.dataout(dataout));
+
+encoder128 U011(.datain(data_encin1),.dataout(enc_out1));
+decoder128 U021(.datain(data_encout1),.dataout(dataout1));
+
+
+
+	always @(posedge clock)
+		
+		begin
+		
+			if (reset)
+			
+				data_encin <= 127'h00000;
+				
+			else
+			
+				data_encin <= datain;
+				
+				
+		end
+		
+		
+	always @(posedge clock)
+		
+		begin
+		
+			if (reset)
+			
+				data_encout <= 7'h0;
+				
+			else
+			
+				data_encout<= enc_out;
+				
+				
+		end
+			
+			
+			
+		always @(posedge clock)
+		
+		begin
+		
+			if (reset)
+			
+				data_encin1 <= 127'h00000;
+				
+			else
+			
+				data_encin1 <= datain1;
+				
+				
+		end
+		
+		
+	always @(posedge clock)
+		
+		begin
+		
+			if (reset)
+			
+				data_encout1 <= 7'h0;
+				
+			else
+			
+				data_encout1<= enc_out1;
+				
+				
+		end		
+			
+			
+			
+			
+			
+			
+			
+endmodule
+
diff --git a/BENCHMARK/rs_decoder_1/rs_decoder_1_yosys.blif b/BENCHMARK/rs_decoder_1/rs_decoder_1_yosys.blif
new file mode 100644
index 0000000..49423a7
--- /dev/null
+++ b/BENCHMARK/rs_decoder_1/rs_decoder_1_yosys.blif
@@ -0,0 +1,8213 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model rs_decoder_1
+.inputs x(0) x(1) x(2) x(3) x(4) enable k(0) k(1) k(2) k(3) k(4) clk clrn
+.outputs error(0) error(1) error(2) error(3) error(4) with_error valid
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_1 a=$auto$hilomap.cc:39:hilomap_worker$25858
+.subckt logic_0 a=x0.shift
+.subckt in_buff A=clk Q=x0.clk
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=clrn Q=x0.clrn
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=enable Q=$iopadmap$enable
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=x2.error(0) Q=error(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=x2.error(1) Q=error(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=x2.error(2) Q=error(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=x2.error(3) Q=error(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=x2.error(4) Q=error(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=k(0) Q=$iopadmap$k(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=k(1) Q=$iopadmap$k(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=k(2) Q=$iopadmap$k(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=k(3) Q=$iopadmap$k(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=k(4) Q=$iopadmap$k(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=$iopadmap$valid Q=valid
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=temp Q=with_error
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=x(0) Q=$iopadmap$x(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=x(1) Q=$iopadmap$x(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=x(2) Q=$iopadmap$x(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=x(3) Q=$iopadmap$x(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=x(4) Q=$iopadmap$x(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt ff CQZ=x1.enable D=syn_shift_ff_CQZ_D QCK=x0.clk QEN=berl_enable_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=with_error_LUT4_I3_1_O I1=berl_enable_ff_CQZ_QEN_LUT4_O_I1 I2=enable_LUT4_I0_1_O I3=syn_enable_ff_CQZ_D O=berl_enable_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=x2.load I1=x2.search I2=x2.shorten I3=x0.clrn O=chien_load_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011111111
+.subckt LUT4 I0=x2.search I1=x2.load I2=x2.shorten I3=x0.clrn O=chien_load_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010011111111
+.subckt ff CQZ=x2.load D=chien_load_ff_CQZ_D QCK=x0.clk QEN=chien_load_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=with_error_LUT4_I3_1_O O=chien_load_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O I2=enable_LUT4_I2_I3 I3=chien_load_ff_CQZ_QEN_LUT4_O_I3 O=chien_load_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=enable_LUT4_I2_I3 I1=x2.search I2=chien_load_ff_CQZ_QEN_LUT4_O_I3 I3=enable_LUT4_I2_I1_LUT4_O_I3 O=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=x1.phase0 I1=count(3) I2=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=enable_LUT4_I2_I1_LUT4_O_I2 O=chien_load_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=x0.shift I1=count(1) I2=count(0) I3=count(2) O=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=x2.search D=chien_search_ff_CQZ_D QCK=x0.clk QEN=chien_search_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.phase12 I1=x2.load I2=chien_search_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=chien_search_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=length2(2) I1=length2(1) I2=chien_search_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=x2.search O=chien_search_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=x0.shift I1=length2(0) I2=length2(4) I3=length2(3) O=chien_search_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O I3=enable_LUT4_I2_I1_LUT4_O_I2 O=chien_search_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=count(3) D=count_ff_CQZ_D(3) QCK=x0.clk QEN=count_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=count(2) D=count_ff_CQZ_D(2) QCK=x0.clk QEN=count_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=count(1) D=count_ff_CQZ_D(1) QCK=x0.clk QEN=count_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=count(0) D=count_ff_CQZ_D(0) QCK=x0.clk QEN=count_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=count_ff_CQZ_D_LUT4_O_I2 I3=chien_load_ff_CQZ_D O=count_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=count(0) I1=count(1) I2=count(2) I3=chien_load_ff_CQZ_D O=count_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100011111111
+.subckt LUT4 I0=x0.shift I1=chien_load_ff_CQZ_D I2=count(1) I3=count(0) O=count_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=count(0) I3=chien_load_ff_CQZ_D O=count_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=count(0) I1=count(2) I2=count(1) I3=count(3) O=count_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=$iopadmap$enable I1=enable_LUT4_I0_I1 I2=x0.clrn I3=enable_LUT4_I2_I1 O=shorten_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=$iopadmap$enable I1=syn_shift I2=x0.enable I3=x0.clrn O=enable_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001011111111
+.subckt LUT4 I0=x1.phase12 I1=x2.load I2=x1.enable I3=enable_LUT4_I0_1_O O=enable_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=with_error_LUT4_I3_1_O I3=enable_LUT4_I0_1_O O=enable_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=enable_LUT4_I0_I1_LUT4_O_I1 I2=x2.shorten I3=length2(4) O=enable_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=length0(4) I1=enable_LUT4_I0_I1_LUT4_O_I1 I2=length2(4) I3=with_error_LUT4_I3_1_O O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010111000011
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(4) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(3) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_I3 O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(2) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3 O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=x0.shift I1=with_error_LUT4_I3_1_O I2=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3_LUT4_O_I2 I3=length0(2) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=x0.shift I1=length2(2) I2=length2(0) I3=length2(1) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(1) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_2_I3 O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=length0(1) I1=length2(1) I2=length2(0) I3=with_error_LUT4_I3_1_O O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010100111100
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=$iopadmap$k(0) I3=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_3_I3 O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=x0.shift I1=with_error_LUT4_I3_1_O I2=length2(0) I3=length0(0) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=x0.shift I1=with_error_LUT4_I3_1_O I2=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_I3_LUT4_O_I2 I3=length0(3) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=length2(1) I1=length2(2) I2=length2(0) I3=length2(3) O=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000001
+.subckt LUT4 I0=length2(1) I1=length2(2) I2=length2(3) I3=length2(0) O=enable_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=x0.shift I1=enable_LUT4_I2_I1 I2=$iopadmap$enable I3=enable_LUT4_I2_I3 O=enable_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=enable_LUT4_I2_I3 I1=x2.search I2=enable_LUT4_I2_I1_LUT4_O_I2 I3=enable_LUT4_I2_I1_LUT4_O_I3 O=enable_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=x1.phase12 I1=x2.load I2=with_error_LUT4_I3_O_LUT4_I1_I2 I3=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O O=enable_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=x0.enable I1=syn_shift I2=x0.clrn I3=$iopadmap$enable O=enable_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1 I2=error_LUT4_O_I2 I3=error_LUT4_O_I3 O=x2.error(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1 I2=error_LUT4_O_1_I2 I3=error_LUT4_O_1_I3 O=x2.error(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I1 I2=error_LUT4_O_2_I2 I3=error_LUT4_O_4_I3 O=error_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I3_LUT4_O_I2 I2=error_LUT4_O_I3_LUT4_O_I0 I3=error_LUT4_O_I3_LUT4_O_I1 O=error_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=error_LUT4_O_4_I3 I1=error_LUT4_O_2_I1 I2=error_LUT4_O_2_I2 I3=error_LUT4_O_I1 O=x2.error(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_3_I3_LUT4_O_I1 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=error_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O I1=error_LUT4_O_2_I2_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2 I3=error_LUT4_O_3_I3_LUT4_O_I3 O=error_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100001110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_2_I2_LUT4_O_I1 I3=error_LUT4_O_2_I2_LUT4_O_I2 O=error_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x2.o4(2) I1=x2.o5(2) I2=x2.o6(2) I3=x2.o7(2) O=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.o0(2) I1=x2.o1(2) I2=x2.o8(2) I3=x2.o9(2) O=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.o2(2) I1=x2.o3(2) I2=x2.o10(2) I3=x2.o11(2) O=error_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_3_I3_LUT4_O_I1 I3=error_LUT4_O_2_I2_LUT4_O_I2 O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=x2.load I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I0 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011111
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=x2.load I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(2) I3=x2.load O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=s9(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1 I3=error_LUT4_O_3_I3 O=x2.error(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O I1=error_LUT4_O_3_I3_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=error_LUT4_O_3_I3_LUT4_O_I3 O=error_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100001110111
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x2.o0(1) I1=x2.o1(1) I2=x2.o9(1) I3=x2.o10(1) O=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.o5(1) I1=x2.o6(1) I2=x2.o7(1) I3=x2.o8(1) O=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x2.o2(1) I1=x2.o3(1) I2=x2.o4(1) I3=x2.o11(1) O=error_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x2.o4(0) I1=x2.o5(0) I2=x2.o6(0) I3=x2.o9(0) O=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.o0(0) I1=x2.o1(0) I2=x2.o7(0) I3=x2.o8(0) O=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.o2(0) I1=x2.o3(0) I2=x2.o10(0) I3=x2.o11(0) O=error_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1 I3=error_LUT4_O_4_I3 O=x2.error(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=x2.l1(2) I2=x2.l3(2) I3=x2.l11(2) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x2.l9(2) I2=x2.l7(2) I3=x2.l5(2) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=x2.l10(2) I2=x2.l2(2) I3=x2.l0(2) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=D0(2) I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=x0.shift I1=x2.l8(2) I2=x2.l6(2) I3=x2.l4(2) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=D0(0) I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=x0.shift I1=x2.l8(0) I2=x2.l6(0) I3=x2.l4(0) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=x2.l10(0) I2=x2.l2(0) I3=x2.l0(0) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=x2.l1(0) I2=x2.l3(0) I3=x2.l11(0) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x2.l9(0) I2=x2.l7(0) I3=x2.l5(0) O=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=x2.l1(3) I2=x2.l3(3) I3=x2.l11(3) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x2.l9(3) I2=x2.l7(3) I3=x2.l5(3) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=x2.l10(3) I2=x2.l2(3) I3=x2.l0(3) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=D0(3) I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=x0.shift I1=x2.l8(3) I2=x2.l6(3) I3=x2.l4(3) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=D0(4) I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=x0.shift I1=x2.l8(4) I2=x2.l6(4) I3=x2.l4(4) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=x2.l10(4) I2=x2.l2(4) I3=x2.l0(4) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=x2.l1(4) I2=x2.l3(4) I3=x2.l11(4) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x2.l9(4) I2=x2.l7(4) I3=x2.l5(4) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x2.l1(1) I2=x2.l3(1) I3=x2.l11(1) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x2.l9(1) I2=x2.l7(1) I3=x2.l5(1) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=x2.l10(1) I2=x2.l2(1) I3=x2.l0(1) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=D0(1) I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=x2.search O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001110101010
+.subckt LUT4 I0=x0.shift I1=x2.l8(1) I2=x2.l6(1) I3=x2.l4(1) O=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=error_LUT4_O_3_I3_LUT4_O_I3 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_3_I3_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111000000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111010
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111101110
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=x2.load I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I1=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I1=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I2=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=error_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_3_I3_LUT4_O_I3 I2=error_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111010111111
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011111110000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100001110
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O_LUT4_I0_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x2.load I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_I0_LUT4_I2_O_LUT4_I0_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.A0_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.l0_ff_CQZ_4_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_3_I3_LUT4_O_I3 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O O=error_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x2.load I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(4) I3=x2.load O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100110000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I1=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010010110000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=error_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=error_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=x2.o4(4) I2=x2.o5(4) I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=x2.o6(4) I3=x2.o9(4) O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.o2(4) I1=x2.o3(4) I2=x2.o10(4) I3=x2.o11(4) O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.o1(4) I1=x2.o0(4) I2=x2.o7(4) I3=x2.o8(4) O=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=error_LUT4_O_I3_LUT4_O_I0 I1=error_LUT4_O_I3_LUT4_O_I1 I2=error_LUT4_O_I3_LUT4_O_I2 I3=error_LUT4_O_1_I2 O=error_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100001000101011
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=error_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_O O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=x2.o4(3) I1=x2.o5(3) I2=x2.o6(3) I3=x2.o7(3) O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.o2(3) I1=x2.o3(3) I2=x2.o10(3) I3=x2.o11(3) O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.o0(3) I1=x2.o1(3) I2=x2.o8(3) I3=x2.o9(3) O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_3_I3_LUT4_O_I3 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=error_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=error_LUT4_O_4_I3 O=error_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=error_LUT4_O_2_I2_LUT4_O_I1 I3=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=error_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=length0(4) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(4) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=length0(3) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(3) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=length0(2) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(2) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=length0(1) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(1) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=length0(0) D=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(0) QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=length2(4) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(4) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=length2(3) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(3) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=length2(2) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(2) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=length2(1) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(1) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=length2(0) D=enable_LUT4_I0_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O(0) QCK=x0.clk QEN=chien_load_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=phase(11) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(10) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(1) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(9) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(8) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(7) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(6) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(5) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(4) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(3) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=phase(2) I2=x0.clrn I3=x1.enable O=phase_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.phase0_LUT4_I3_O O=phase_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=phase(11) D=phase_LUT4_I1_O(11) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(10) D=phase_LUT4_I1_O(10) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(1) D=phase_LUT4_I1_O(1) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(9) D=phase_LUT4_I1_O(9) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(8) D=phase_LUT4_I1_O(8) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(7) D=phase_LUT4_I1_O(7) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(6) D=phase_LUT4_I1_O(6) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(5) D=phase_LUT4_I1_O(5) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(4) D=phase_LUT4_I1_O(4) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(3) D=phase_LUT4_I1_O(3) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=phase(2) D=phase_LUT4_I1_O(2) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.shorten D=shorten_ff_CQZ_D QCK=x0.clk QEN=shorten_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.shift I3=x0.clrn O=shorten_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=x0.enable D=syn_enable_ff_CQZ_D QCK=x0.clk QEN=$auto$hilomap.cc:39:hilomap_worker$25858 QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=syn_enable_ff_CQZ_D_LUT4_O_I0 I1=syn_enable_ff_CQZ_D_LUT4_O_I1 I2=$iopadmap$k(3) I3=syn_enable_ff_CQZ_D_LUT4_O_I3 O=syn_enable_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=x0.shift I1=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=enable_LUT4_I3_O O=syn_enable_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=length0(4) I3=$iopadmap$k(4) O=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=x0.shift I1=$iopadmap$k(2) I2=length0(2) I3=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=length0(3) I2=length0(2) I3=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=length0(0) I1=length0(1) I2=$iopadmap$k(1) I3=$iopadmap$k(0) O=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111011010111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_D I3=syn_enable_ff_CQZ_D_LUT4_O_I1 O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=syn_shift_ff_CQZ_D I2=length0(4) I3=syn_enable_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=x0.shift I1=syn_shift_ff_CQZ_D I2=length0(2) I3=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=x0.shift I1=syn_shift_ff_CQZ_D I2=length0(1) I3=length0(0) O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_D I3=length0(0) O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=length0(3) I2=length0(2) I3=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=syn_enable_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=length0(1) I3=length0(0) O=syn_enable_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_D I3=enable_LUT4_I3_O O=syn_enable_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=x0.init D=enable_LUT4_I3_O QCK=x0.clk QEN=enable_LUT4_I0_1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=syn_shift_LUT4_I3_I1 I2=x1.phase0 I3=syn_shift O=syn_shift_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x0.init I3=x0.enable O=syn_shift_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=syn_shift D=syn_shift_ff_CQZ_D QCK=x0.clk QEN=syn_shift_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x0.enable O=syn_shift_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_QEN_LUT4_O_I2 I3=syn_enable_ff_CQZ_D O=syn_shift_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_shift_ff_CQZ_QEN_LUT4_O_I2 I3=enable_LUT4_I3_O O=syn_shift_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=u(4) D=u_ff_CQZ_D(4) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=u(3) D=u_ff_CQZ_D(3) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=u(2) D=u_ff_CQZ_D(2) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=u(1) D=u_ff_CQZ_D(1) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=u(0) D=u_ff_CQZ_D(0) QCK=x0.clk QEN=enable_LUT4_I2_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.search I3=x2.shorten O=$iopadmap$valid
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=temp O=with_error_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=temp O=with_error_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=with_error_LUT4_I3_O_LUT4_I3_I2 I1=with_error_LUT4_I3_O I2=with_error_LUT4_I3_O_LUT4_I1_I2 I3=chien_load_ff_CQZ_QEN_LUT4_O_I3 O=syn_shift_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=enable_LUT4_I0_1_O I3=with_error_LUT4_I3_1_O O=with_error_LUT4_I3_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=with_error_LUT4_I3_O I3=enable_LUT4_I0_1_O O=with_error_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=with_error_LUT4_I3_O_LUT4_I2_O I1=with_error_LUT4_I3_O_LUT4_I3_I2 I2=enable_LUT4_I2_I3 I3=syn_enable_ff_CQZ_D_LUT4_O_I3 O=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=syn_enable_ff_CQZ_D_LUT4_O_I3 I3=with_error_LUT4_I3_O_LUT4_I2_O O=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=enable_LUT4_I2_I1_LUT4_O_I2 I1=x1.phase0 I2=enable_LUT4_I2_I3 I3=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I3_O O=count_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=x2.load I1=x1.phase12 I2=with_error_LUT4_I3_O_LUT4_I3_I2 I3=with_error_LUT4_I3_O O=berl_enable_ff_CQZ_QEN_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010001000
+.subckt LUT4 I0=count(3) I1=count(0) I2=count(2) I3=count(1) O=with_error_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=with_error_LUT4_O_I0 I1=with_error_LUT4_O_I1 I2=with_error_LUT4_O_I2 I3=syn_shift O=temp
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=with_error_LUT4_O_I0_LUT4_O_I0 I1=with_error_LUT4_O_I0_LUT4_O_I1 I2=with_error_LUT4_O_I0_LUT4_O_I2 I3=with_error_LUT4_O_I0_LUT4_O_I3 O=with_error_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=s1(0) I1=s1(3) I2=s2(1) I3=s2(4) O=with_error_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s5(1) I1=s5(2) I2=s9(1) I3=s9(2) O=with_error_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s1(4) I1=s2(0) I2=s2(2) I3=s2(3) O=with_error_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s1(1) I1=s1(2) I2=s10(0) I3=s10(1) O=with_error_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=with_error_LUT4_O_I1_LUT4_O_I0 I1=with_error_LUT4_O_I1_LUT4_O_I1 I2=with_error_LUT4_O_I1_LUT4_O_I2 I3=with_error_LUT4_O_I1_LUT4_O_I3 O=with_error_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=with_error_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=s7(2) I1=s7(3) I2=s7(4) I3=s8(0) O=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s6(3) I1=s6(4) I2=s7(0) I3=s7(1) O=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s9(0) I1=s9(3) I2=s9(4) I3=s10(2) O=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s8(1) I1=s8(2) I2=s8(3) I3=s8(4) O=with_error_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s0(1) I1=s0(2) I2=s0(3) I3=s0(4) O=with_error_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s11(2) I1=s11(3) I2=s11(4) I3=s0(0) O=with_error_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s10(3) I1=s10(4) I2=s11(0) I3=s11(1) O=with_error_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=with_error_LUT4_O_I2_LUT4_O_I0 I1=with_error_LUT4_O_I2_LUT4_O_I1 I2=with_error_LUT4_O_I2_LUT4_O_I2 I3=with_error_LUT4_O_I2_LUT4_O_I3 O=with_error_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=s3(4) I1=s4(0) I2=s4(1) I3=s4(2) O=with_error_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s3(0) I1=s3(1) I2=s3(2) I3=s3(3) O=with_error_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s5(4) I1=s6(0) I2=s6(1) I3=s6(2) O=with_error_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=s4(3) I1=s4(4) I2=s5(0) I3=s5(3) O=with_error_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=s0(4) D=x0.y0_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s0(3) D=x0.y0_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(3) I1=x0.init I2=x0.y0_ff_CQZ_1_D_LUT4_O_I2 I3=x0.clrn O=x0.y0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y0_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I0 I1=s1(3) I2=x0.init I3=x0.enable O=x0.y0_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s0(2) I3=u(3) O=x0.y0_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=s0(2) D=x0.y0_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y0_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s1(2) I3=x0.y0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y0_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s0(4) I2=s0(1) I3=u(2) O=x0.y0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=s0(1) D=x0.y0_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y0_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y0_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s1(1) I2=x0.init I3=x0.enable O=x0.y0_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s0(0) I3=u(1) O=x0.y0_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=s0(0) D=x0.y0_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y0_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y0_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s1(0) I2=x0.init I3=x0.enable O=x0.y0_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s0(4) I3=u(0) O=x0.y0_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=u(4) I1=x0.init I2=x0.y0_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x0.y0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=s1(4) I2=x0.init I3=x0.enable O=x0.y0_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s0(3) I3=u(4) O=x0.y0_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=s10(4) D=x0.y10_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s10(3) D=x0.y10_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y10_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s11(3) I3=x0.y10_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s10(1) I2=u(3) I3=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt ff CQZ=s10(2) D=x0.y10_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y10_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=x0.y10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=s11(2) O=x0.y10_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=u(2) I1=s10(0) I2=s10(1) I3=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt ff CQZ=s10(1) D=x0.y10_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y10_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s11(1) I3=x0.y10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(1) I1=s10(0) I2=s10(1) I3=s10(4) O=x0.y10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s10(0) D=x0.y10_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y10_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s11(0) I3=x0.y10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(0) I1=s10(0) I2=s10(3) I3=s10(4) O=x0.y10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=u(4) I1=x0.init I2=x0.y10_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x0.y10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=s11(4) I2=x0.init I3=x0.enable O=x0.y10_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=u(4) I3=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=x0.shift I1=s10(4) I2=s10(3) I3=s10(2) O=x0.y10_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=s11(4) D=x0.y11_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s11(3) D=x0.y11_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y11_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y11_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s0(3) I3=x0.y11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s11(4) I2=u(3) I3=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=s11(2) D=x0.y11_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(2) I1=x0.init I2=x0.y11_ff_CQZ_2_D_LUT4_O_I2 I3=x0.clrn O=x0.y11_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0 I1=s0(2) I2=x0.init I3=x0.enable O=x0.y11_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=u(2) I3=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=s11(0) I1=s11(1) I2=s11(2) I3=s11(3) O=x0.y11_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt ff CQZ=s11(1) D=x0.y11_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y11_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y11_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s0(1) I3=x0.y11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s11(0) I2=u(1) I3=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x0.y11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=s11(0) D=x0.y11_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y11_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y11_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s0(0) I3=x0.y11_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y11_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s11(2) I2=u(0) I3=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x0.y11_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x0.y11_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y11_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=s0(4) O=x0.y11_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=u(4) I1=s11(1) I2=s11(2) I3=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s11(4) I3=s11(3) O=x0.y11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=s1(4) D=x0.y1_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s1(3) D=x0.y1_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y1_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y1_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=s2(3) I3=x0.enable O=x0.y1_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(3) I1=s1(1) I2=s1(4) I3=x0.enable O=x0.y1_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=s1(2) D=x0.y1_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y1_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s2(2) I3=x0.y1_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y1_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s1(3) I2=s1(0) I3=u(2) O=x0.y1_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=s1(1) D=x0.y1_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y1_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y1_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s2(1) I2=x0.init I3=x0.enable O=x0.y1_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s1(4) I3=u(1) O=x0.y1_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=s1(0) D=x0.y1_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y1_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y1_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s2(0) I2=x0.init I3=x0.enable O=x0.y1_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s1(3) I3=u(0) O=x0.y1_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=u(4) I1=x0.init I2=x0.y1_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x0.y1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=s2(4) I2=x0.init I3=x0.enable O=x0.y1_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s1(2) I3=u(4) O=x0.y1_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=s2(4) D=x0.y2_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s2(3) D=x0.y2_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y2_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y2_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=s3(3) I3=x0.enable O=x0.y2_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(3) I1=s2(0) I2=s2(3) I3=x0.enable O=x0.y2_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=s2(2) D=x0.y2_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y2_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y2_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 I2=s3(2) I3=x0.enable O=x0.y2_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(2) I1=s2(2) I2=s2(4) I3=x0.enable O=x0.y2_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=s2(1) D=x0.y2_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y2_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y2_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s3(1) I2=x0.init I3=x0.enable O=x0.y2_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s2(3) I3=u(1) O=x0.y2_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=s2(0) D=x0.y2_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y2_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y2_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s3(0) I2=x0.init I3=x0.enable O=x0.y2_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s2(2) I3=u(0) O=x0.y2_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x0.y2_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s3(4) I3=x0.y2_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y2_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s2(4) I2=s2(1) I3=u(4) O=x0.y2_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=s3(4) D=x0.y3_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s3(3) D=x0.y3_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y3_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y3_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=s4(3) I3=x0.enable O=x0.y3_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(3) I1=s3(2) I2=s3(4) I3=x0.enable O=x0.y3_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=s3(2) D=x0.y3_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y3_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s4(2) I3=x0.y3_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y3_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(2) I1=s3(1) I2=s3(3) I3=s3(4) O=x0.y3_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s3(1) D=x0.y3_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y3_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y3_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s4(1) I2=x0.init I3=x0.enable O=x0.y3_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s3(2) I3=u(1) O=x0.y3_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=s3(0) D=x0.y3_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y3_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y3_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s4(0) I2=x0.init I3=x0.enable O=x0.y3_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=s3(4) I2=s3(1) I3=u(0) O=x0.y3_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.y3_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=s4(4) I3=x0.enable O=x0.y3_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(4) I1=s3(0) I2=s3(3) I3=x0.enable O=x0.y3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=s4(4) D=x0.y4_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s4(3) D=x0.y4_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y4_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s5(3) I3=x0.y4_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y4_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(3) I1=s4(1) I2=s4(3) I3=s4(4) O=x0.y4_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s4(2) D=x0.y4_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y4_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s5(2) I3=x0.y4_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y4_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(2) I1=s4(0) I2=s4(2) I3=s4(3) O=x0.y4_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s4(1) D=x0.y4_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y4_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y4_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s5(1) I2=x0.init I3=x0.enable O=x0.y4_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=s4(4) I2=s4(1) I3=u(1) O=x0.y4_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt ff CQZ=s4(0) D=x0.y4_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(0) I1=x0.init I2=x0.y4_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x0.y4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y4_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0 I1=s5(0) I2=x0.init I3=x0.enable O=x0.y4_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=s4(3) I2=s4(0) I3=u(0) O=x0.y4_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.y4_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=s5(4) I3=x0.enable O=x0.y4_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(4) I1=s4(2) I2=s4(4) I3=x0.enable O=x0.y4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=s5(4) D=x0.y5_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s5(3) D=x0.y5_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y5_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s6(3) I3=x0.y5_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y5_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(3) I1=s5(0) I2=s5(2) I3=s5(3) O=x0.y5_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s5(2) D=x0.y5_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y5_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s6(2) I3=x0.y5_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y5_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s5(2) I2=s5(1) I3=u(2) O=x0.y5_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=s5(1) D=x0.y5_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=u(1) I1=x0.init I2=x0.y5_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x0.y5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.y5_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=s6(1) I2=x0.init I3=x0.enable O=x0.y5_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=x0.shift I1=s5(3) I2=s5(0) I3=u(1) O=x0.y5_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt ff CQZ=s5(0) D=x0.y5_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y5_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I1 I2=s6(0) I3=x0.enable O=x0.y5_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(0) I1=s5(2) I2=s5(4) I3=x0.enable O=x0.y5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=x0.y5_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s6(4) I3=x0.y5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y5_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(4) I1=s5(1) I2=s5(3) I3=s5(4) O=x0.y5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s6(4) D=x0.y6_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s6(3) D=x0.y6_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y6_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y6_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=s7(3) I3=x0.enable O=x0.y6_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(3) I1=s6(1) I2=s6(2) I3=x0.enable O=x0.y6_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=s6(2) D=x0.y6_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y6_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s7(2) I3=x0.y6_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y6_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(2) I1=s6(0) I2=s6(1) I3=s6(4) O=x0.y6_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s6(1) D=x0.y6_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y6_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I2=s7(1) I3=x0.enable O=x0.y6_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(1) I1=s6(2) I2=s6(4) I3=x0.enable O=x0.y6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=s6(0) D=x0.y6_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y6_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s7(0) I3=x0.y6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y6_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(0) I1=s6(1) I2=s6(3) I3=s6(4) O=x0.y6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.y6_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s7(4) I3=x0.y6_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y6_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(4) I1=s6(0) I2=s6(2) I3=s6(3) O=x0.y6_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s7(4) D=x0.y7_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s7(3) D=x0.y7_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y7_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s8(3) I3=x0.y7_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y7_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(3) I1=s7(0) I2=s7(1) I3=s7(4) O=x0.y7_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s7(2) D=x0.y7_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y7_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s8(2) I3=x0.y7_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y7_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(2) I1=s7(0) I2=s7(3) I3=s7(4) O=x0.y7_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s7(1) D=x0.y7_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y7_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s8(1) I3=x0.y7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y7_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(1) I1=s7(1) I2=s7(3) I3=s7(4) O=x0.y7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s7(0) D=x0.y7_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y7_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s8(0) I3=x0.y7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y7_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(0) I1=s7(0) I2=s7(2) I3=s7(3) O=x0.y7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.y7_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y7_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=s8(4) I3=x0.enable O=x0.y7_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(4) I1=s7(1) I2=s7(2) I3=x0.enable O=x0.y7_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=s8(4) D=x0.y8_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s8(3) D=x0.y8_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y8_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s9(3) I3=x0.y8_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y8_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(3) I1=s8(0) I2=s8(3) I3=s8(4) O=x0.y8_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s8(2) D=x0.y8_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y8_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s9(2) I3=x0.y8_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x0.y8_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(2) I1=s8(2) I2=s8(3) I3=s8(4) O=x0.y8_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s8(1) D=x0.y8_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y8_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s9(1) I3=x0.y8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y8_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(1) I1=s8(0) I2=s8(2) I3=s8(3) O=x0.y8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s8(0) D=x0.y8_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y8_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.y8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I1 I2=s9(0) I3=x0.enable O=x0.y8_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=u(0) I1=s8(1) I2=s8(2) I3=x0.enable O=x0.y8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=x0.y8_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s9(4) I3=x0.y8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y8_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(4) I1=s8(0) I2=s8(1) I3=s8(4) O=x0.y8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s9(4) D=x0.y9_ff_CQZ_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=s9(3) D=x0.y9_ff_CQZ_1_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y9_ff_CQZ_1_D_LUT4_O_I0 I1=u(3) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s10(3) I3=x0.y9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x0.y9_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(3) I1=s9(2) I2=s9(3) I3=s9(4) O=x0.y9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=s9(2) D=x0.y9_ff_CQZ_2_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y9_ff_CQZ_2_D_LUT4_O_I0 I1=u(2) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=x0.y9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=s10(2) O=x0.y9_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=u(2) I1=s9(2) I2=s9(3) I3=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x0.y9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt ff CQZ=s9(1) D=x0.y9_ff_CQZ_3_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y9_ff_CQZ_3_D_LUT4_O_I0 I1=u(1) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s10(1) I3=x0.y9_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x0.y9_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s9(2) I2=s9(1) I3=u(1) O=x0.y9_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=s9(0) D=x0.y9_ff_CQZ_4_D QCK=x0.clk QEN=syn_shift_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:47.12-47.107|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:1347.2-1409.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.y9_ff_CQZ_4_D_LUT4_O_I0 I1=u(0) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s10(0) I3=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x0.y9_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=x0.shift I1=s9(0) I2=u(0) I3=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s9(4) I3=s9(1) O=x0.y9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x0.y9_ff_CQZ_D_LUT4_O_I0 I1=u(4) I2=x0.init I3=x0.clrn O=x0.y9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=x0.shift I1=x0.enable I2=s10(4) I3=x0.y9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x0.y9_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=u(4) I1=s9(0) I2=s9(3) I3=s9(4) O=x0.y9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt ff CQZ=x1.A0(4) D=x1.A0_ff_CQZ_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A0(3) D=x1.A0_ff_CQZ_1_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.A0_ff_CQZ_1_D_LUT4_O_I0 I1=x1.A10(3) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0 I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I2=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I1=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 I2=x1.A0_ff_CQZ_4_D_LUT4_O_I0 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=s9(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s9(3) I3=x1.phase0 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(3) I3=x1.lambda3(3) O=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x1.A0(2) D=x1.A0_ff_CQZ_2_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.A0_ff_CQZ_2_D_LUT4_O_I0 I1=x1.A10(2) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x1.A0_ff_CQZ_4_D_LUT4_O_I0 I1=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 I2=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x1.A0_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 O=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(2) I3=x1.lambda3(2) O=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x1.A0(1) D=x1.A0_ff_CQZ_3_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I1 I1=x1.A10(1) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt ff CQZ=x1.A0(0) D=x1.A0_ff_CQZ_4_D QCK=x0.clk QEN=x1.A0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.A0_ff_CQZ_4_D_LUT4_O_I0 I1=x1.A10(0) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x1.D_ff_CQZ_D_LUT4_O_I3 I1=x1.A10(4) I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.A0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x1.B0_ff_CQZ_D_LUT4_O_I2 I1=x1.phase12 I2=x1.phase0 I3=x1.enable O=x1.A0_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111111111
+.subckt ff CQZ=x1.A10(4) D=x1.A10_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A10(3) D=x1.A10_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(3) I3=x1.enable O=x1.A10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A10(2) D=x1.A10_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(2) I3=x1.enable O=x1.A10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A10(1) D=x1.A10_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(1) I3=x1.enable O=x1.A10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A10(0) D=x1.A10_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(0) I3=x1.enable O=x1.A10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A9(4) I3=x1.enable O=x1.A10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A1(4) D=x1.A1_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A1(3) D=x1.A1_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(3) I3=x1.enable O=x1.A1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A1(2) D=x1.A1_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(2) I3=x1.enable O=x1.A1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A1(1) D=x1.A1_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(1) I3=x1.enable O=x1.A1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A1(0) D=x1.A1_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(0) I3=x1.enable O=x1.A1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A0(4) I3=x1.enable O=x1.A1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A2(4) D=x1.A2_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A2(3) D=x1.A2_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(3) I3=x1.enable O=x1.A2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A2(2) D=x1.A2_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(2) I3=x1.enable O=x1.A2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A2(1) D=x1.A2_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(1) I3=x1.enable O=x1.A2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A2(0) D=x1.A2_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(0) I3=x1.enable O=x1.A2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A1(4) I3=x1.enable O=x1.A2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A3(4) D=x1.A3_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A3(3) D=x1.A3_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(3) I3=x1.enable O=x1.A3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A3(2) D=x1.A3_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(2) I3=x1.enable O=x1.A3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A3(1) D=x1.A3_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(1) I3=x1.enable O=x1.A3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A3(0) D=x1.A3_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(0) I3=x1.enable O=x1.A3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A2(4) I3=x1.enable O=x1.A3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A4(4) D=x1.A4_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A4(3) D=x1.A4_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(3) I3=x1.enable O=x1.A4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A4(2) D=x1.A4_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(2) I3=x1.enable O=x1.A4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A4(1) D=x1.A4_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(1) I3=x1.enable O=x1.A4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A4(0) D=x1.A4_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(0) I3=x1.enable O=x1.A4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A3(4) I3=x1.enable O=x1.A4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A5(4) D=x1.A5_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A5(3) D=x1.A5_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(3) I3=x1.enable O=x1.A5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A5(2) D=x1.A5_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(2) I3=x1.enable O=x1.A5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A5(1) D=x1.A5_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(1) I3=x1.enable O=x1.A5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A5(0) D=x1.A5_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(0) I3=x1.enable O=x1.A5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A4(4) I3=x1.enable O=x1.A5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A6(4) D=x1.A6_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A6(3) D=x1.A6_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(3) I3=x1.enable O=x1.A6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A6(2) D=x1.A6_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(2) I3=x1.enable O=x1.A6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A6(1) D=x1.A6_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(1) I3=x1.enable O=x1.A6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A6(0) D=x1.A6_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(0) I3=x1.enable O=x1.A6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A5(4) I3=x1.enable O=x1.A6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A7(4) D=x1.A7_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A7(3) D=x1.A7_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(3) I3=x1.enable O=x1.A7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A7(2) D=x1.A7_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(2) I3=x1.enable O=x1.A7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A7(1) D=x1.A7_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(1) I3=x1.enable O=x1.A7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A7(0) D=x1.A7_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(0) I3=x1.enable O=x1.A7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A6(4) I3=x1.enable O=x1.A7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A8(4) D=x1.A8_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A8(3) D=x1.A8_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(3) I3=x1.enable O=x1.A8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A8(2) D=x1.A8_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(2) I3=x1.enable O=x1.A8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A8(1) D=x1.A8_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(1) I3=x1.enable O=x1.A8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A8(0) D=x1.A8_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(0) I3=x1.enable O=x1.A8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A7(4) I3=x1.enable O=x1.A8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A9(4) D=x1.A9_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.A9(3) D=x1.A9_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(3) I3=x1.enable O=x1.A9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A9(2) D=x1.A9_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(2) I3=x1.enable O=x1.A9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A9(1) D=x1.A9_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(1) I3=x1.enable O=x1.A9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.A9(0) D=x1.A9_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(0) I3=x1.enable O=x1.A9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.A8(4) I3=x1.enable O=x1.A9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B0(4) D=x1.B0_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B0(3) D=x1.B0_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.B0_ff_CQZ_1_D_LUT4_O_I3 O=x1.B0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x1.phase12 I1=x1.B10(3) I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.B0_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt ff CQZ=x1.B0(2) D=x1.B0_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.B0_ff_CQZ_2_D_LUT4_O_I3 O=x1.B0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x1.phase12 I1=x1.B10(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I1 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.B0_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt ff CQZ=x1.B0(1) D=x1.B0_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.B0_ff_CQZ_3_D_LUT4_O_I3 O=x1.B0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x1.phase12 I1=x1.B10(1) I2=x1.D_ff_CQZ_3_D_LUT4_O_I0 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.B0_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt ff CQZ=x1.B0(0) D=x1.B0_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.B0_ff_CQZ_4_D_LUT4_O_I3 O=x1.B0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=x1.phase12 I1=x1.B10(0) I2=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.B0_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=x1.B0_ff_CQZ_D_LUT4_O_I0 I1=x1.B0_ff_CQZ_D_LUT4_O_I1 I2=x1.B0_ff_CQZ_D_LUT4_O_I2 I3=x1.enable O=x1.B0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 O=x1.B0_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B10(4) I3=x1.phase12 O=x1.B0_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=x1.B10(4) D=x1.B10_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B10(3) D=x1.B10_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(3) I3=x1.enable O=x1.B10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B10(2) D=x1.B10_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(2) I3=x1.enable O=x1.B10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B10(1) D=x1.B10_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(1) I3=x1.enable O=x1.B10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B10(0) D=x1.B10_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(0) I3=x1.enable O=x1.B10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B9(4) I3=x1.enable O=x1.B10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B1(4) D=x1.B1_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B1(3) D=x1.B1_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(3) I3=x1.enable O=x1.B1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B1(2) D=x1.B1_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(2) I3=x1.enable O=x1.B1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B1(1) D=x1.B1_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(1) I3=x1.enable O=x1.B1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B1(0) D=x1.B1_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(0) I3=x1.enable O=x1.B1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B0(4) I3=x1.enable O=x1.B1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B2(4) D=x1.B2_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B2(3) D=x1.B2_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(3) I3=x1.enable O=x1.B2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B2(2) D=x1.B2_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(2) I3=x1.enable O=x1.B2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B2(1) D=x1.B2_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(1) I3=x1.enable O=x1.B2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B2(0) D=x1.B2_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(0) I3=x1.enable O=x1.B2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B1(4) I3=x1.enable O=x1.B2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B3(4) D=x1.B3_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B3(3) D=x1.B3_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(3) I3=x1.enable O=x1.B3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B3(2) D=x1.B3_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(2) I3=x1.enable O=x1.B3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B3(1) D=x1.B3_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(1) I3=x1.enable O=x1.B3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B3(0) D=x1.B3_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(0) I3=x1.enable O=x1.B3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B2(4) I3=x1.enable O=x1.B3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B4(4) D=x1.B4_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B4(3) D=x1.B4_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(3) I3=x1.enable O=x1.B4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B4(2) D=x1.B4_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(2) I3=x1.enable O=x1.B4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B4(1) D=x1.B4_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(1) I3=x1.enable O=x1.B4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B4(0) D=x1.B4_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(0) I3=x1.enable O=x1.B4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B3(4) I3=x1.enable O=x1.B4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B5(4) D=x1.B5_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B5(3) D=x1.B5_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(3) I3=x1.enable O=x1.B5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B5(2) D=x1.B5_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(2) I3=x1.enable O=x1.B5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B5(1) D=x1.B5_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(1) I3=x1.enable O=x1.B5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B5(0) D=x1.B5_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(0) I3=x1.enable O=x1.B5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B4(4) I3=x1.enable O=x1.B5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B6(4) D=x1.B6_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B6(3) D=x1.B6_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(3) I3=x1.enable O=x1.B6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B6(2) D=x1.B6_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(2) I3=x1.enable O=x1.B6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B6(1) D=x1.B6_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(1) I3=x1.enable O=x1.B6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B6(0) D=x1.B6_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(0) I3=x1.enable O=x1.B6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B5(4) I3=x1.enable O=x1.B6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B7(4) D=x1.B7_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B7(3) D=x1.B7_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(3) I3=x1.enable O=x1.B7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B7(2) D=x1.B7_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(2) I3=x1.enable O=x1.B7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B7(1) D=x1.B7_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(1) I3=x1.enable O=x1.B7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B7(0) D=x1.B7_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(0) I3=x1.enable O=x1.B7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B6(4) I3=x1.enable O=x1.B7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B8(4) D=x1.B8_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B8(3) D=x1.B8_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(3) I3=x1.enable O=x1.B8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B8(2) D=x1.B8_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(2) I3=x1.enable O=x1.B8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B8(1) D=x1.B8_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(1) I3=x1.enable O=x1.B8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B8(0) D=x1.B8_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(0) I3=x1.enable O=x1.B8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B7(4) I3=x1.enable O=x1.B8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B9(4) D=x1.B9_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.B9(3) D=x1.B9_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(3) I3=x1.enable O=x1.B9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B9(2) D=x1.B9_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(2) I3=x1.enable O=x1.B9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B9(1) D=x1.B9_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(1) I3=x1.enable O=x1.B9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.B9(0) D=x1.B9_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(0) I3=x1.enable O=x1.B9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.B8(4) I3=x1.enable O=x1.B9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=D0(4) D=x1.D_ff_CQZ_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D0(3) D=x1.D_ff_CQZ_1_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.D_ff_CQZ_1_D_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3 O=x1.D_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0 O=x1.D_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=x1.lambda9(2) I2=s3(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=s3(0) I3=x1.lambda9(4) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110111011101
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(1) I3=s3(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=s3(1) I1=x1.lambda9(2) I2=s3(3) I3=x1.lambda9(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111101110101
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(3) I3=s3(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=x1.lambda9(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=x1.lambda11(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda11(1) I3=s1(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=x1.lambda11(1) I2=x1.lambda11(2) I3=s1(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=s1(1) I1=x1.lambda11(2) I2=s1(3) I3=x1.lambda11(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111101110101
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda11(3) I3=s1(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.lambda11(2) I2=s1(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0 O=x1.D_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=x1.lambda10(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x0.shift I1=x1.lambda10(2) I2=s2(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=s2(0) I1=x1.lambda10(3) I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=s2(0) I3=x1.lambda10(3) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda10(2) I3=s2(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=s2(2) I1=x1.lambda10(1) I2=s2(3) I3=x1.lambda10(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s2(1) I1=s2(2) I2=x1.lambda10(0) I3=x1.lambda10(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=s4(1) I1=x1.lambda8(2) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=s5(0) I1=x1.lambda7(3) I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=x1.lambda7(2) I3=s5(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=s5(1) I1=s5(2) I2=x1.lambda7(0) I3=x1.lambda7(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=x0.shift I1=x1.lambda7(2) I2=s5(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=x1.lambda7(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=s7(0) I1=x1.lambda5(4) I2=s7(2) I3=x1.lambda5(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s7(3) I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=s7(1) I1=x1.lambda5(0) I2=x1.lambda5(2) I3=x1.lambda5(1) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=s7(1) I1=x1.lambda5(3) I2=s7(4) I3=x1.lambda5(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=x1.lambda5(2) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(1) I3=s7(2) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010110001001111
+.subckt LUT4 I0=s7(1) I1=x1.lambda5(2) I2=s7(3) I3=x1.lambda5(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(3) I3=s7(0) O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.lambda5(2) I2=s7(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=D0(2) D=x1.D_ff_CQZ_2_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I0 I1=x1.D_ff_CQZ_2_D_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I2 I3=x0.clrn O=x1.D_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=x1.A0_ff_CQZ_2_D_LUT4_O_I0 I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_2_D_LUT4_O_I0 O=x1.D_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=s3(0) I1=x1.lambda9(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=x0.shift I1=x1.lambda9(1) I2=s3(0) I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=s3(1) I1=x1.lambda9(1) I2=s3(2) I3=x1.lambda9(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x1.lambda8(1) I2=s4(1) I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=s2(0) I1=x1.lambda10(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=s2(0) I1=s2(1) I2=x1.lambda10(0) I3=x1.lambda10(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=s2(1) I1=x1.lambda10(1) I2=s2(2) I3=x1.lambda10(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=s4(1) I3=x1.lambda8(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=s4(0) I1=x1.lambda8(2) I2=s4(2) I3=x1.lambda8(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=s8(0) I1=x1.lambda4(2) I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I1 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=s7(0) I1=x1.lambda5(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=x0.shift I1=x1.lambda5(1) I2=s7(0) I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=s7(1) I1=x1.lambda5(1) I2=s7(2) I3=x1.lambda5(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=s5(0) I1=x1.lambda7(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=s5(0) I1=s5(1) I2=x1.lambda7(0) I3=x1.lambda7(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=s5(1) I1=x1.lambda7(1) I2=s5(2) I3=x1.lambda7(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s6(0) I1=s6(1) I2=x1.lambda6(0) I3=x1.lambda6(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=x1.lambda6(1) I1=s6(1) I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(2) I3=s6(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=s6(1) I1=x1.lambda6(1) I2=s6(2) I3=x1.lambda6(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(0) I3=x2.load O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=s11(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(2) I3=x1.lambda1(2) O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=s11(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0 O=x1.D_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=s1(0) I1=x1.lambda11(2) I2=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=x0.shift I1=x1.lambda11(1) I2=s1(0) I3=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda11(0) I3=s1(1) O=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=s1(1) I1=x1.lambda11(1) I2=s1(2) I3=x1.lambda11(0) O=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt ff CQZ=D0(1) D=x1.D_ff_CQZ_3_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0 I1=x1.D_ff_CQZ_3_D_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I2 I3=x0.clrn O=x1.D_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s11(0) I3=x1.phase0 O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(1) I3=x1.lambda1(1) O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(1) I3=x2.load O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s11(1) I3=x1.phase0 O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(0) I3=x1.lambda1(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 I1=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s9(0) I3=x1.phase0 O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(1) I3=x1.lambda3(1) O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s9(1) I3=x1.phase0 O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(0) I3=x1.lambda3(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0 I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=s3(0) I1=x1.lambda9(1) I2=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=s1(0) I1=x1.lambda11(1) I2=x1.D_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=s2(0) I1=x1.lambda10(1) I2=s2(1) I3=x1.lambda10(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(0) I3=s3(1) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=s7(0) I1=x1.lambda5(1) I2=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(0) I3=s7(1) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=s8(0) I1=x1.lambda4(1) I2=s8(1) I3=x1.lambda4(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s4(0) I1=x1.lambda8(1) I2=s4(1) I3=x1.lambda8(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s6(0) I1=x1.lambda6(1) I2=s6(1) I3=x1.lambda6(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s5(0) I1=x1.lambda7(1) I2=s5(1) I3=x1.lambda7(0) O=x1.D_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt ff CQZ=D0(0) D=x1.D_ff_CQZ_4_D QCK=x0.clk QEN=x1.D_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.D_ff_CQZ_4_D_LUT4_O_I3 O=x1.D_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I1=x1.A0_ff_CQZ_4_D_LUT4_O_I0 I2=x1.D_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_4_D_LUT4_O_I1 I2=x1.lambda4(0) I3=s8(0) O=x1.D_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.D_ff_CQZ_D_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I3 O=x1.D_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0 I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=x0.shift I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=x0.shift I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=s11(4) I1=x1.phase0 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.shift I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I0_O_LUT4_I2_1_O I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(4) I3=x1.lambda1(4) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_O I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=s8(0) I1=x1.lambda4(4) I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1 I1=s8(1) I2=x1.lambda4(2) I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.lambda4(3) I3=s8(1) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=s8(3) I1=x1.lambda4(1) I2=s8(4) I3=x1.lambda4(0) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s8(2) I3=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=s8(3) I1=x1.lambda4(0) I2=x1.lambda4(1) I3=x1.lambda4(2) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3 I2=s8(0) I3=x1.lambda4(3) O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000011101111
+.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.A0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=s9(4) I1=x1.phase0 I2=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=x0.shift I1=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=s9(2) I3=x1.phase0 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.omega11(4) I3=x1.lambda3(4) O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 I3=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=x0.shift I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0 I1=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x1.D_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.phase0 O=x1.D_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=x1.L_LUT4_I2_O I1=x1.L(2) I2=count(3) I3=x1.L_LUT4_I1_I3 O=x1.B0_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=x0.shift I1=x1.L_LUT4_I1_I3_LUT4_O_I1 I2=D0(1) I3=D0(0) O=x1.L_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=x0.shift I1=D0(4) I2=D0(3) I3=D0(2) O=x1.L_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=count(2) I1=count(1) I2=x1.L(1) I3=x1.L(0) O=x1.L_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt ff CQZ=x1.L(2) D=x1.L_ff_CQZ_D QCK=x0.clk QEN=x1.L_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.L(1) D=x1.L_ff_CQZ_1_D QCK=x0.clk QEN=x1.L_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.L_ff_CQZ_1_D_LUT4_O_I0 I1=count(1) I2=x1.L(1) I3=x0.clrn O=x1.L_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=count(0) I3=x1.L(0) O=x1.L_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=x1.L(0) D=x1.L_ff_CQZ_2_D QCK=x0.clk QEN=x1.L_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:541.2-557.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.L(0) I3=count(0) O=x1.L_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.L_ff_CQZ_D_LUT4_O_I3 O=x1.L_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x1.L_ff_CQZ_1_D_LUT4_O_I0 I1=count(1) I2=x1.L(1) I3=x1.L_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=x1.L_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001100011100111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.L(2) I3=count(2) O=x1.L_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.phase0 I3=x1.B0_ff_CQZ_D_LUT4_O_I2 O=x1.L_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt ff CQZ=x1.lambda0(4) D=x1.lambda0_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda0(3) D=x1.lambda0_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_1_D_LUT4_O_I0 I1=x1.phase12 I2=x1.lambda11(3) I3=x1.enable O=x1.lambda0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 O=x1.lambda0_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt ff CQZ=x1.lambda0(2) D=x1.lambda0_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0 I1=x1.phase12 I2=x1.lambda11(2) I3=x1.enable O=x1.lambda0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt ff CQZ=x1.lambda0(1) D=x1.lambda0_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0 I1=x1.phase12 I2=x1.lambda11(1) I3=x1.enable O=x1.lambda0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000110000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(1) I3=s0(1) O=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.B10(1) I3=x1.lambda0(1) O=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x1.lambda0(0) D=x1.lambda0_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.phase12 I1=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1 I2=x1.lambda11(0) I3=x1.enable O=x1.lambda0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010011111111
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1 I1=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1 I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I3 O=x1.D_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=s5(0) I1=x1.lambda7(0) I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(0) I3=s4(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=s6(0) I1=x1.lambda6(0) I2=s7(0) I3=x1.lambda5(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s1(0) I1=x1.lambda11(0) I2=s2(0) I3=x1.lambda10(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(0) I3=s3(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I3_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1 O=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.B10(0) I3=x1.lambda0(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(0) I3=s0(0) O=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0 I1=x1.phase12 I2=x1.lambda11(4) I3=x1.enable O=x1.lambda0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 I1=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I2=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110110010
+.subckt LUT4 I0=s6(1) I1=s6(2) I2=x1.lambda6(1) I3=x1.lambda6(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda6(0) I3=s6(4) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=s6(0) I1=x1.lambda6(4) I2=s6(3) I3=x1.lambda6(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s6(1) I1=x1.lambda6(3) I2=s6(2) I3=x1.lambda6(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=s5(0) I1=x1.lambda7(4) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.lambda7(1) I2=x1.lambda7(2) I3=s5(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=s5(3) I1=x1.lambda7(1) I2=s5(4) I3=x1.lambda7(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.lambda7(2) I2=x1.lambda7(3) I3=s5(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=s5(2) I1=x1.lambda7(1) I2=s5(3) I3=x1.lambda7(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=s5(0) I3=x1.lambda7(3) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=x1.lambda10(2) I2=x1.lambda10(3) I3=s2(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I0_O I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=s1(0) I1=x1.lambda11(4) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda11(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011110001000
+.subckt LUT4 I0=s1(1) I1=s1(3) I2=x1.lambda11(2) I3=s1(4) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=s1(1) I1=x1.lambda11(3) I2=s1(3) I3=x1.lambda11(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s2(3) I1=x1.lambda10(1) I2=s2(4) I3=x1.lambda10(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s2(0) I1=x1.lambda10(4) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2 I3=s2(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011110001000
+.subckt LUT4 I0=s2(3) I1=x1.lambda10(0) I2=x1.lambda10(1) I3=x1.lambda10(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I1=x1.lambda9(0) I2=x1.lambda9(1) I3=s3(3) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=x1.lambda9(2) I3=s3(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=s3(1) I1=x1.lambda9(3) I2=s3(4) I3=x1.lambda9(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=s4(1) I3=x1.lambda8(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=x1.lambda8(1) I3=s4(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=x0.shift I1=x1.lambda8(2) I2=s4(2) I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=s4(3) I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=s4(0) I1=x1.lambda8(0) I2=x1.lambda8(3) I3=x1.lambda8(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=s4(0) I1=x1.lambda8(4) I2=s4(4) I3=x1.lambda8(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(3) I3=s4(1) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=x1.lambda8(1) I2=x1.lambda8(2) I3=s4(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=s4(0) I1=x1.lambda8(3) I2=s4(3) I3=x1.lambda8(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=s0(3) I1=D0(3) I2=x1.phase0 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.B10(3) I3=x1.lambda0(3) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.B10(2) I3=x1.lambda0(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_I3_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(2) I3=s0(2) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I1=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=x0.shift I1=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=s0(4) I1=D0(4) I2=x1.phase0 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=s0(3) I1=D0(3) I2=x1.phase0 I3=x1.lambda0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x1.lambda0(4) I1=x1.B10(4) I2=x1.phase0 I3=x1.lambda0_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I3 O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x1.lambda10(4) D=x1.lambda10_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda10(3) D=x1.lambda10_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(3) I3=x1.enable O=x1.lambda10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda10(2) D=x1.lambda10_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(2) I3=x1.enable O=x1.lambda10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda10(1) D=x1.lambda10_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(1) I3=x1.enable O=x1.lambda10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda10(0) D=x1.lambda10_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(0) I3=x1.enable O=x1.lambda10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda9(4) I3=x1.enable O=x1.lambda10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda11(4) D=x1.lambda11_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda11(3) D=x1.lambda11_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(3) I3=x1.enable O=x1.lambda11_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda11(2) D=x1.lambda11_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(2) I3=x1.enable O=x1.lambda11_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda11(1) D=x1.lambda11_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(1) I3=x1.enable O=x1.lambda11_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda11(0) D=x1.lambda11_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(0) I3=x1.enable O=x1.lambda11_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda10(4) I3=x1.enable O=x1.lambda11_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda1(4) D=x1.lambda1_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda1(3) D=x1.lambda1_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(3) I3=x1.enable O=x1.lambda1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda1(2) D=x1.lambda1_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(2) I3=x1.enable O=x1.lambda1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda1(1) D=x1.lambda1_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(1) I3=x1.enable O=x1.lambda1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda1(0) D=x1.lambda1_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(0) I3=x1.enable O=x1.lambda1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda0(4) I3=x1.enable O=x1.lambda1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda2(4) D=x1.lambda2_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda2(3) D=x1.lambda2_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(3) I3=x1.enable O=x1.lambda2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda2(2) D=x1.lambda2_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(2) I3=x1.enable O=x1.lambda2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda2(1) D=x1.lambda2_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(1) I3=x1.enable O=x1.lambda2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda2(0) D=x1.lambda2_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(0) I3=x1.enable O=x1.lambda2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda1(4) I3=x1.enable O=x1.lambda2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda3(4) D=x1.lambda3_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda3(3) D=x1.lambda3_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(3) I3=x1.enable O=x1.lambda3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda3(2) D=x1.lambda3_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(2) I3=x1.enable O=x1.lambda3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda3(1) D=x1.lambda3_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(1) I3=x1.enable O=x1.lambda3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda3(0) D=x1.lambda3_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(0) I3=x1.enable O=x1.lambda3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda2(4) I3=x1.enable O=x1.lambda3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda4(4) D=x1.lambda4_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda4(3) D=x1.lambda4_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(3) I3=x1.enable O=x1.lambda4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda4(2) D=x1.lambda4_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(2) I3=x1.enable O=x1.lambda4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda4(1) D=x1.lambda4_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(1) I3=x1.enable O=x1.lambda4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda4(0) D=x1.lambda4_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(0) I3=x1.enable O=x1.lambda4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda3(4) I3=x1.enable O=x1.lambda4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda5(4) D=x1.lambda5_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda5(3) D=x1.lambda5_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(3) I3=x1.enable O=x1.lambda5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda5(2) D=x1.lambda5_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(2) I3=x1.enable O=x1.lambda5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda5(1) D=x1.lambda5_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(1) I3=x1.enable O=x1.lambda5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda5(0) D=x1.lambda5_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(0) I3=x1.enable O=x1.lambda5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda4(4) I3=x1.enable O=x1.lambda5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda6(4) D=x1.lambda6_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda6(3) D=x1.lambda6_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(3) I3=x1.enable O=x1.lambda6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda6(2) D=x1.lambda6_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(2) I3=x1.enable O=x1.lambda6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda6(1) D=x1.lambda6_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(1) I3=x1.enable O=x1.lambda6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda6(0) D=x1.lambda6_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(0) I3=x1.enable O=x1.lambda6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda5(4) I3=x1.enable O=x1.lambda6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda7(4) D=x1.lambda7_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda7(3) D=x1.lambda7_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(3) I3=x1.enable O=x1.lambda7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda7(2) D=x1.lambda7_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(2) I3=x1.enable O=x1.lambda7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda7(1) D=x1.lambda7_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(1) I3=x1.enable O=x1.lambda7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda7(0) D=x1.lambda7_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(0) I3=x1.enable O=x1.lambda7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(4) I3=x1.enable O=x1.lambda7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda8(4) D=x1.lambda8_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda8(3) D=x1.lambda8_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(3) I3=x1.enable O=x1.lambda8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda8(2) D=x1.lambda8_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(2) I3=x1.enable O=x1.lambda8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda8(1) D=x1.lambda8_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(1) I3=x1.enable O=x1.lambda8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda8(0) D=x1.lambda8_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(0) I3=x1.enable O=x1.lambda8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda7(4) I3=x1.enable O=x1.lambda8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda9(4) D=x1.lambda9_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.lambda9(3) D=x1.lambda9_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(3) I3=x1.enable O=x1.lambda9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda9(2) D=x1.lambda9_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(2) I3=x1.enable O=x1.lambda9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda9(1) D=x1.lambda9_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(1) I3=x1.enable O=x1.lambda9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.lambda9(0) D=x1.lambda9_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(0) I3=x1.enable O=x1.lambda9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda8(4) I3=x1.enable O=x1.lambda9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega0(4) D=x1.omega0_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega0(3) D=x1.omega0_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.omega0_ff_CQZ_1_D_LUT4_O_I0 I1=x1.phase12 I2=x1.omega11(3) I3=x1.enable O=x1.omega0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=x1.lambda0_ff_CQZ_1_D_LUT4_O_I0 I1=x1.omega0_ff_CQZ_1_D_LUT4_O_I0 I2=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I2 I3=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3 O=x1.D_ff_CQZ_1_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=s6(3) I1=x1.lambda6(0) I2=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2 I3=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2 I1=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3 I2=s6(3) I3=x1.lambda6(0) O=x1.lambda0_ff_CQZ_D_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2 I3=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=s6(1) I1=x1.lambda6(2) I2=s6(2) I3=x1.lambda6(1) O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.lambda6(3) I3=s6(0) O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=x1.D_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 O=x1.omega0_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt ff CQZ=x1.omega0(2) D=x1.omega0_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.omega0_ff_CQZ_2_D_LUT4_O_I0 I1=x1.phase12 I2=x1.omega11(2) I3=x1.enable O=x1.omega0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=x1.omega0_ff_CQZ_4_D_LUT4_O_I1 I1=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 I2=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O O=x1.omega0_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x1.lambda2(2) I1=x1.A10(2) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x1.omega0(1) D=x1.omega0_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.omega0_ff_CQZ_3_D_LUT4_O_I0 I1=x1.phase12 I2=x1.omega11(1) I3=x1.enable O=x1.omega0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(2) I3=s10(2) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(1) I3=s10(1) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.A10(0) I3=x1.lambda2(0) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.A10(1) I3=x1.lambda2(1) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=D0(0) I3=s10(0) O=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x1.omega0(0) D=x1.omega0_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.phase12 I1=x1.omega0_ff_CQZ_4_D_LUT4_O_I1 I2=x1.omega11(0) I3=x1.enable O=x1.omega0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010011111111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_4_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x1.phase12 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1 I2=x1.omega11(4) I3=x1.enable O=x1.omega0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=s8(0) I1=x1.lambda4(3) I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.lambda4(2) I3=s8(1) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=s8(2) I1=x1.lambda4(1) I2=s8(3) I3=x1.lambda4(0) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=s8(1) I1=s8(2) I2=x1.lambda4(0) I3=x1.lambda4(1) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=x0.shift I1=x1.lambda4(2) I2=s8(0) I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=s8(1) I1=x1.lambda4(1) I2=s8(2) I3=x1.lambda4(0) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I1 I2=x1.lambda4(2) I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=s8(0) I1=s8(1) I2=x1.lambda4(0) I3=x1.lambda4(1) O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=x1.lambda2(3) I1=x1.A10(3) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=s10(3) I1=D0(3) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x1.lambda2(2) I1=x1.A10(2) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O I3=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I1=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O I2=x1.omega0_ff_CQZ_4_D_LUT4_O_I1 I3=x1.omega0_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I1 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3_LUT4_I3_O O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=s10(3) I1=D0(3) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x1.lambda2(2) I1=x1.A10(2) I2=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 I3=x1.phase0 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=s10(4) I1=D0(4) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x1.lambda2(3) I1=x1.A10(3) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I2=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=x1.lambda2(4) I1=x1.A10(4) I2=x1.phase0 I3=x1.omega0_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x1.omega0_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x1.omega10(4) D=x1.omega10_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega10(3) D=x1.omega10_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(3) I3=x1.enable O=x1.omega10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega10(2) D=x1.omega10_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(2) I3=x1.enable O=x1.omega10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega10(1) D=x1.omega10_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(1) I3=x1.enable O=x1.omega10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega10(0) D=x1.omega10_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(0) I3=x1.enable O=x1.omega10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega9(4) I3=x1.enable O=x1.omega10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega11(4) D=x1.omega11_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega11(3) D=x1.omega11_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(3) I3=x1.enable O=x1.omega11_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega11(2) D=x1.omega11_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(2) I3=x1.enable O=x1.omega11_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega11(1) D=x1.omega11_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(1) I3=x1.enable O=x1.omega11_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega11(0) D=x1.omega11_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(0) I3=x1.enable O=x1.omega11_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega10(4) I3=x1.enable O=x1.omega11_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega1(4) D=x1.omega1_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega1(3) D=x1.omega1_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(3) I3=x1.enable O=x1.omega1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega1(2) D=x1.omega1_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(2) I3=x1.enable O=x1.omega1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega1(1) D=x1.omega1_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(1) I3=x1.enable O=x1.omega1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega1(0) D=x1.omega1_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(0) I3=x1.enable O=x1.omega1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega0(4) I3=x1.enable O=x1.omega1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega2(4) D=x1.omega2_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega2(3) D=x1.omega2_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(3) I3=x1.enable O=x1.omega2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega2(2) D=x1.omega2_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(2) I3=x1.enable O=x1.omega2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega2(1) D=x1.omega2_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(1) I3=x1.enable O=x1.omega2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega2(0) D=x1.omega2_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(0) I3=x1.enable O=x1.omega2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega1(4) I3=x1.enable O=x1.omega2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega3(4) D=x1.omega3_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega3(3) D=x1.omega3_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(3) I3=x1.enable O=x1.omega3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega3(2) D=x1.omega3_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(2) I3=x1.enable O=x1.omega3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega3(1) D=x1.omega3_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(1) I3=x1.enable O=x1.omega3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega3(0) D=x1.omega3_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(0) I3=x1.enable O=x1.omega3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega2(4) I3=x1.enable O=x1.omega3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega4(4) D=x1.omega4_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega4(3) D=x1.omega4_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(3) I3=x1.enable O=x1.omega4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega4(2) D=x1.omega4_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(2) I3=x1.enable O=x1.omega4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega4(1) D=x1.omega4_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(1) I3=x1.enable O=x1.omega4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega4(0) D=x1.omega4_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(0) I3=x1.enable O=x1.omega4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega3(4) I3=x1.enable O=x1.omega4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega5(4) D=x1.omega5_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega5(3) D=x1.omega5_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(3) I3=x1.enable O=x1.omega5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega5(2) D=x1.omega5_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(2) I3=x1.enable O=x1.omega5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega5(1) D=x1.omega5_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(1) I3=x1.enable O=x1.omega5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega5(0) D=x1.omega5_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(0) I3=x1.enable O=x1.omega5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega4(4) I3=x1.enable O=x1.omega5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega6(4) D=x1.omega6_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega6(3) D=x1.omega6_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(3) I3=x1.enable O=x1.omega6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega6(2) D=x1.omega6_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(2) I3=x1.enable O=x1.omega6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega6(1) D=x1.omega6_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(1) I3=x1.enable O=x1.omega6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega6(0) D=x1.omega6_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(0) I3=x1.enable O=x1.omega6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega5(4) I3=x1.enable O=x1.omega6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega7(4) D=x1.omega7_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega7(3) D=x1.omega7_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(3) I3=x1.enable O=x1.omega7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega7(2) D=x1.omega7_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(2) I3=x1.enable O=x1.omega7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega7(1) D=x1.omega7_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(1) I3=x1.enable O=x1.omega7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega7(0) D=x1.omega7_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(0) I3=x1.enable O=x1.omega7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega6(4) I3=x1.enable O=x1.omega7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega8(4) D=x1.omega8_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega8(3) D=x1.omega8_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(3) I3=x1.enable O=x1.omega8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega8(2) D=x1.omega8_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(2) I3=x1.enable O=x1.omega8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega8(1) D=x1.omega8_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(1) I3=x1.enable O=x1.omega8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega8(0) D=x1.omega8_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(0) I3=x1.enable O=x1.omega8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega7(4) I3=x1.enable O=x1.omega8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega9(4) D=x1.omega9_ff_CQZ_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x1.omega9(3) D=x1.omega9_ff_CQZ_1_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(3) I3=x1.enable O=x1.omega9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega9(2) D=x1.omega9_ff_CQZ_2_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(2) I3=x1.enable O=x1.omega9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega9(1) D=x1.omega9_ff_CQZ_3_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(1) I3=x1.enable O=x1.omega9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=x1.omega9(0) D=x1.omega9_ff_CQZ_4_D QCK=x0.clk QEN=x1.phase0_LUT4_I3_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:48.13-48.141|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:341.2-539.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(0) I3=x1.enable O=x1.omega9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.omega8(4) I3=x1.enable O=x1.omega9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x1.enable I3=x1.phase0 O=x1.phase0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt ff CQZ=x1.phase0 D=phase_LUT4_I1_O(0) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.clrn I2=x1.enable I3=x1.phase12 O=phase_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt ff CQZ=x1.phase12 D=phase_LUT4_I1_O(12) QCK=x0.clk QEN=with_error_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:52.2-129.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a0(4) D=x2.a0_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a0(3) D=x2.a0_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a0(3) I1=alpha(3) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a0(2) D=x2.a0_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a0(2) I1=alpha(2) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a0(1) D=x2.a0_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a0(1) I1=alpha(1) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a0(0) D=x2.a0_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a0(0) I1=alpha(0) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a0(4) I1=alpha(4) I2=x2.shorten I3=x0.clrn O=x2.a0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a10(4) D=x2.a10_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a10(3) D=x2.a10_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a10_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a9(3) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 O=x2.a10_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=x2.a10(2) D=x2.a10_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a10_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a9(2) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 I3=x2.a10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=x2.a10(1) D=x2.a10_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a10_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a9(1) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a10(1) I1=x2.l10(1) I2=x2.shorten I3=x2.a10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l10(2) I3=x2.a10(2) O=x2.a10_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.a10(0) D=x2.a10_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a10_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a9(0) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a10(0) I1=x2.l10(0) I2=x2.shorten I3=x2.a10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110001010011
+.subckt LUT4 I0=x2.a10(1) I1=x2.l10(1) I2=x2.shorten I3=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 O=x2.a10_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110001010011
+.subckt LUT4 I0=x2.a10_ff_CQZ_D_LUT4_O_I0 I1=x2.a9(4) I2=x2.shorten I3=x0.clrn O=x2.a10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a10_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l10(4) I3=x2.a10(4) O=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.a10(0) I1=x2.l10(0) I2=x2.shorten I3=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l10(3) I3=x2.a10(3) O=x2.a10_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=alpha(4) D=x2.a11_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=alpha(3) D=x2.a11_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a11_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a10(3) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a11_ff_CQZ_D_LUT4_O_I0 O=x2.a11_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l11(1) I3=alpha(1) O=x2.a11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=alpha(2) D=x2.a11_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a11_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a10(2) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I2=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a11_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt ff CQZ=alpha(1) D=x2.a11_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a11_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a10(1) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a11_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=alpha(0) I1=x2.l11(0) I2=x2.shorten I3=x2.a11_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 O=x2.a11_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=alpha(0) D=x2.a11_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a11_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a10(0) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a11_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a11_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=alpha(0) I1=x2.l11(0) I2=x2.shorten I3=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.a11_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x2.a11_ff_CQZ_D_LUT4_O_I0 I1=x2.a10(4) I2=x2.shorten I3=x0.clrn O=x2.a11_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a11_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l11(4) I3=alpha(4) O=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=alpha(2) I1=x2.l11(2) I2=x2.shorten I3=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l11(3) I3=alpha(3) O=x2.a11_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.a1(4) D=x2.a1_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a1(3) D=x2.a1_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a1(2) I1=x2.a0(3) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a1(2) D=x2.a1_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a1_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a0(2) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a1(1) I1=x2.l1(1) I2=x2.shorten I3=x2.l1_ff_CQZ_4_D_LUT4_O_I0 O=x2.a1_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a1(1) D=x2.a1_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a1(0) I1=x2.a0(1) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a1(0) D=x2.a1_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a1(4) I1=x2.a0(0) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a1(3) I1=x2.a0(4) I2=x2.shorten I3=x0.clrn O=x2.a1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a2(4) D=x2.a2_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a2(3) D=x2.a2_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a2_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a1(3) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a2(1) I1=x2.l2(1) I2=x2.shorten I3=x2.l2_ff_CQZ_3_D_LUT4_O_I0 O=x2.a2_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a2(2) D=x2.a2_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a2_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a1(2) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a2(0) I1=x2.l2(0) I2=x2.shorten I3=x2.l2_ff_CQZ_4_D_LUT4_O_I0 O=x2.a2_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a2(1) D=x2.a2_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a2(4) I1=x2.a1(1) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a2(0) D=x2.a2_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a2(3) I1=x2.a1(0) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a2(2) I1=x2.a1(4) I2=x2.shorten I3=x0.clrn O=x2.a2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a3(4) D=x2.a3_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a3(3) D=x2.a3_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a3_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a2(3) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a3(0) I1=x2.l3(0) I2=x2.shorten I3=x2.l3_ff_CQZ_3_D_LUT4_O_I0 O=x2.a3_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a3(2) D=x2.a3_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a3_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a2(2) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 I3=x2.l3_ff_CQZ_4_D_LUT4_O_I0 O=x2.a3_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=x2.a3(1) D=x2.a3_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a3(3) I1=x2.a2(1) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a3(0) D=x2.a3_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a3(2) I1=x2.a2(0) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a3_ff_CQZ_D_LUT4_O_I0 I1=x2.a2(4) I2=x2.shorten I3=x0.clrn O=x2.a3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a3(1) I1=x2.l3(1) I2=x2.shorten I3=x2.a3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a3_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l3(4) I3=x2.a3(4) O=x2.a3_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.a4(4) D=x2.a4_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a4(3) D=x2.a4_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a4_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a3(3) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.l4_ff_CQZ_3_D_LUT4_O_I0 I3=x2.a4_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a4_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=x2.a4(2) D=x2.a4_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a4_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a3(2) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a4_ff_CQZ_4_D_LUT4_O_I0 O=x2.a4_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=x2.a4(1) D=x2.a4_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a4(2) I1=x2.a3(1) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.a4(0) D=x2.a4_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a4_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a3(0) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a4(1) I1=x2.l4(1) I2=x2.shorten I3=x2.a4_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a4_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l4(4) I3=x2.a4(4) O=x2.a4_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.a4_ff_CQZ_D_LUT4_O_I0 I1=x2.a3(4) I2=x2.shorten I3=x0.clrn O=x2.a4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a4(0) I1=x2.l4(0) I2=x2.shorten I3=x2.a4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a4_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l4(3) I3=x2.a4(3) O=x2.a4_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.a5(4) D=x2.a5_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a5(3) D=x2.a5_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a5_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a4(3) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a5_ff_CQZ_3_D_LUT4_O_I0 O=x2.a5_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=x2.a5(2) D=x2.a5_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a5_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a4(2) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a5(2) I1=x2.l5(2) I2=x2.shorten I3=x2.a5_ff_CQZ_4_D_LUT4_O_I0 O=x2.a5_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a5(1) D=x2.a5_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a5_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a4(1) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a5(1) I1=x2.l5(1) I2=x2.shorten I3=x2.a5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a5_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a5(0) D=x2.a5_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a5_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a4(0) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a5(0) I1=x2.l5(0) I2=x2.shorten I3=x2.a5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a5_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l5(3) I3=x2.a5(3) O=x2.a5_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.a5_ff_CQZ_D_LUT4_O_I0 I1=x2.a4(4) I2=x2.shorten I3=x0.clrn O=x2.a5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a5(2) I1=x2.l5(2) I2=x2.shorten I3=x2.a5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a5_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l5(4) I3=x2.a5(4) O=x2.a5_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.a6(4) D=x2.a6_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a6(3) D=x2.a6_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a6_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a5(3) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a6_ff_CQZ_3_D_LUT4_O_I0 O=x2.a6_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=x2.a6(2) D=x2.a6_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a6_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a5(2) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a6(1) I1=x2.l6(1) I2=x2.shorten I3=x2.a6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a6(1) D=x2.a6_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a6_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a5(1) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a6(0) I1=x2.l6(0) I2=x2.shorten I3=x2.a6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l6(3) I3=x2.a6(3) O=x2.a6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.a6(0) D=x2.a6_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a6_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a5(0) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a6(4) I1=x2.l6(4) I2=x2.shorten I3=x2.a6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l6(2) I3=x2.a6(2) O=x2.a6_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.a6_ff_CQZ_D_LUT4_O_I0 I1=x2.a5(4) I2=x2.shorten I3=x0.clrn O=x2.a6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a6(4) I1=x2.l6(4) I2=x2.shorten I3=x2.a6_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x2.a6(1) I1=x2.l6(1) I2=x2.shorten I3=x2.a6_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a6_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a7(4) D=x2.a7_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a7(3) D=x2.a7_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a7_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a6(3) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I2 O=x2.a7_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=x2.a7(2) D=x2.a7_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a7_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a6(2) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a7_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x2.a7(0) I1=x2.l7(0) I2=x2.shorten I3=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I2 O=x2.a7_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a7(1) D=x2.a7_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a7_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a6(1) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l7(2) I3=x2.a7(2) O=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l7(4) I3=x2.a7(4) O=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.a7(0) D=x2.a7_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a7_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a6(0) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110011111111
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l7(1) I3=x2.a7(1) O=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.a7(3) I1=x2.l7(3) I2=x2.shorten I3=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x2.a7_ff_CQZ_D_LUT4_O_I0 I1=x2.a6(4) I2=x2.shorten I3=x0.clrn O=x2.a7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a7(3) I1=x2.l7(3) I2=x2.shorten I3=x2.a7_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a7_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x2.a7(0) I1=x2.l7(0) I2=x2.shorten I3=x2.a7_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x2.a7_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a8(4) D=x2.a8_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a8(3) D=x2.a8_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a8_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a7(3) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a8(0) I1=x2.l8(0) I2=x2.shorten I3=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110001010011
+.subckt ff CQZ=x2.a8(2) D=x2.a8_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a8_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a7(2) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a8(4) I1=x2.l8(4) I2=x2.shorten I3=x2.a8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a8(1) D=x2.a8_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a8_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a7(1) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l8(3) I3=x2.a8(3) O=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.a8(4) I1=x2.l8(4) I2=x2.shorten I3=x2.a8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110001010011
+.subckt ff CQZ=x2.a8(0) D=x2.a8_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a8_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a7(0) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a8(2) I1=x2.l8(2) I2=x2.shorten I3=x2.a8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x2.a8(0) I1=x2.l8(0) I2=x2.shorten I3=x2.a8_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x2.a8_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x2.a8_ff_CQZ_D_LUT4_O_I0 I1=x2.a7(4) I2=x2.shorten I3=x0.clrn O=x2.a8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a8(2) I1=x2.l8(2) I2=x2.shorten I3=x2.a8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a8_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l8(1) I3=x2.a8(1) O=x2.a8_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.a9(4) D=x2.a9_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.a9(3) D=x2.a9_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a9_ff_CQZ_1_D_LUT4_O_I0 I1=x2.a8(3) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l9(0) I3=x2.a9(0) O=x2.a9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.a9(2) D=x2.a9_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a9_ff_CQZ_2_D_LUT4_O_I0 I1=x2.a8(2) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=x2.a9(3) I1=x2.l9(3) I2=x2.shorten I3=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 O=x2.a9_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110001010011
+.subckt ff CQZ=x2.a9(1) D=x2.a9_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a9_ff_CQZ_3_D_LUT4_O_I0 I1=x2.a8(1) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 I3=x2.a9_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x2.a9(3) I1=x2.l9(3) I2=x2.shorten I3=x2.a9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 O=x2.a9_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.a9(0) D=x2.a9_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I1_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a9_ff_CQZ_4_D_LUT4_O_I0 I1=x2.a8(0) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=x2.a9(1) I1=x2.l9(1) I2=x2.shorten I3=x2.a9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l9(2) I3=x2.a9(2) O=x2.a9_ff_CQZ_4_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.a9_ff_CQZ_D_LUT4_O_I0 I1=x2.a8(4) I2=x2.shorten I3=x0.clrn O=x2.a9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=x2.a9_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l9(4) I3=x2.a9(4) O=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.a9(1) I1=x2.l9(1) I2=x2.shorten I3=x2.a9_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 O=x2.a9_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001110101100
+.subckt ff CQZ=x2.l0(4) D=x2.l0_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l0(3) D=x2.l0_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.l0_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l0_ff_CQZ_1_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0 I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=x0.shift I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I2=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I1=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I3 I2=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3 I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=s11(2) I1=x1.phase0 I2=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I2 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=error_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=alpha(3) I3=x2.load O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=s11(3) I3=x1.phase0 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I1 I3=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I0 O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=error_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=x1.D_ff_CQZ_3_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=x1.D_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x0.shift I1=x1.phase0 I2=x1.lambda11(3) I3=x1.lambda1(3) O=x2.l0_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a0(3) I3=x2.l0(3) O=x2.l0_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt ff CQZ=x2.l0(2) D=x2.l0_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.search I1=x1.D_ff_CQZ_2_D_LUT4_O_I1 I2=x2.l0_ff_CQZ_2_D_LUT4_O_I2 I3=x0.clrn O=x2.l0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=x2.a0(2) I1=x2.l0(2) I2=x2.shorten I3=x2.search O=x2.l0_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l0(1) D=x2.l0_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x1.D_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l0_ff_CQZ_3_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l0(1) I3=x2.a0(1) O=x2.l0_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=x2.l0(0) D=x2.l0_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.search I1=x2.l0_ff_CQZ_4_D_LUT4_O_I1 I2=x2.l0_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x2.l0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x2.a0(0) I1=x2.l0(0) I2=x2.shorten I3=x2.search O=x2.l0_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.search I1=x1.B0_ff_CQZ_D_LUT4_O_I0 I2=x2.l0_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x2.l0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x2.a0(4) I1=x2.l0(4) I2=x2.shorten I3=x2.search O=x2.l0_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l10(4) D=x2.l10_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l10(3) D=x2.l10_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a10_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l9(3) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt ff CQZ=x2.l10(2) D=x2.l10_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a10_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l9(2) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l10(1) D=x2.l10_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a10_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l9(1) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l10(0) D=x2.l10_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a10_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l9(0) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a10_ff_CQZ_D_LUT4_O_I0 I1=x2.l9(4) I2=x2.search I3=x0.clrn O=x2.l10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l11(4) D=x2.l11_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l11(3) D=x2.l11_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a11_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l10(3) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l11(2) D=x2.l11_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a11_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l10(2) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l11(1) D=x2.l11_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a11_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l10(1) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l11(0) D=x2.l11_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a11_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l10(0) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a11_ff_CQZ_D_LUT4_O_I0 I1=x2.l10(4) I2=x2.search I3=x0.clrn O=x2.l11_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l1(4) D=x2.l1_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l1(3) D=x2.l1_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.l0(3) I1=x2.l1_ff_CQZ_1_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a1(2) I3=x2.l1(2) O=x2.l1_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt ff CQZ=x2.l1(2) D=x2.l1_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a1_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l0(2) I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l1(1) D=x2.l1_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.l0(1) I1=x2.l1_ff_CQZ_3_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a1(0) I3=x2.l1(0) O=x2.l1_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt ff CQZ=x2.l1(0) D=x2.l1_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.l1_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l0(0) I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l1(4) I3=x2.a1(4) O=x2.l1_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.l0(4) I1=x2.l1_ff_CQZ_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a1(3) I3=x2.l1(3) O=x2.l1_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt ff CQZ=x2.l2(4) D=x2.l2_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l2(3) D=x2.l2_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a2_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l1(3) I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l2(2) D=x2.l2_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a2_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l1(2) I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l2(1) D=x2.l2_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.l2_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l1(1) I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l2(4) I3=x2.a2(4) O=x2.l2_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.l2(0) D=x2.l2_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.l2_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l1(0) I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l2(3) I3=x2.a2(3) O=x2.l2_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.l1(4) I1=x2.l2_ff_CQZ_D_LUT4_O_I1 I2=x2.search I3=x0.clrn O=x2.l2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.a2(2) I3=x2.l2(2) O=x2.l2_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt ff CQZ=x2.l3(4) D=x2.l3_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l3(3) D=x2.l3_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a3_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l2(3) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l3(2) D=x2.l3_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a3_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l2(2) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l3(1) D=x2.l3_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.l3_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l2(1) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l3(3) I3=x2.a3(3) O=x2.l3_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.l3(0) D=x2.l3_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.l3_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l2(0) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l3(2) I3=x2.a3(2) O=x2.l3_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=x2.a3_ff_CQZ_D_LUT4_O_I0 I1=x2.l2(4) I2=x2.search I3=x0.clrn O=x2.l3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l4(4) D=x2.l4_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l4(3) D=x2.l4_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a4_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l3(3) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l4(2) D=x2.l4_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a4_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l3(2) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l4(1) D=x2.l4_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.l4_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l3(1) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x2.shorten I2=x2.l4(2) I3=x2.a4(2) O=x2.l4_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=x2.l4(0) D=x2.l4_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a4_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l3(0) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a4_ff_CQZ_D_LUT4_O_I0 I1=x2.l3(4) I2=x2.search I3=x0.clrn O=x2.l4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l5(4) D=x2.l5_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l5(3) D=x2.l5_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a5_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l4(3) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l5(2) D=x2.l5_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a5_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l4(2) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l5(1) D=x2.l5_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a5_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l4(1) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l5(0) D=x2.l5_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a5_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l4(0) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a5_ff_CQZ_D_LUT4_O_I0 I1=x2.l4(4) I2=x2.search I3=x0.clrn O=x2.l5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l6(4) D=x2.l6_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l6(3) D=x2.l6_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a6_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l5(3) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l6(2) D=x2.l6_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a6_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l5(2) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l6(1) D=x2.l6_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a6_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l5(1) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l6(0) D=x2.l6_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a6_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l5(0) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a6_ff_CQZ_D_LUT4_O_I0 I1=x2.l5(4) I2=x2.search I3=x0.clrn O=x2.l6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l7(4) D=x2.l7_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l7(3) D=x2.l7_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a7_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l6(3) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l7(2) D=x2.l7_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a7_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l6(2) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l7(1) D=x2.l7_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a7_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l6(1) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l7(0) D=x2.l7_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a7_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l6(0) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x2.a7_ff_CQZ_D_LUT4_O_I0 I1=x2.l6(4) I2=x2.search I3=x0.clrn O=x2.l7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l8(4) D=x2.l8_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l8(3) D=x2.l8_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a8_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l7(3) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l8(2) D=x2.l8_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a8_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l7(2) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l8(1) D=x2.l8_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a8_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l7(1) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l8(0) D=x2.l8_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a8_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l7(0) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a8_ff_CQZ_D_LUT4_O_I0 I1=x2.l7(4) I2=x2.search I3=x0.clrn O=x2.l8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l9(4) D=x2.l9_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.l9(3) D=x2.l9_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a9_ff_CQZ_1_D_LUT4_O_I0 I1=x2.l8(3) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l9(2) D=x2.l9_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a9_ff_CQZ_2_D_LUT4_O_I0 I1=x2.l8(2) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l9(1) D=x2.l9_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a9_ff_CQZ_3_D_LUT4_O_I0 I1=x2.l8(1) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.l9(0) D=x2.l9_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.a9_ff_CQZ_4_D_LUT4_O_I0 I1=x2.l8(0) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.a9_ff_CQZ_D_LUT4_O_I0 I1=x2.l8(4) I2=x2.search I3=x0.clrn O=x2.l9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.o0(4) D=x2.o0_ff_CQZ_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o0(3) D=x2.o0_ff_CQZ_1_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.A0_ff_CQZ_1_D_LUT4_O_I0 O=x2.o0_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=x2.o0(2) D=x2.o0_ff_CQZ_2_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.A0_ff_CQZ_2_D_LUT4_O_I0 O=x2.o0_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=x2.o0(1) D=x2.o0_ff_CQZ_3_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.D_ff_CQZ_3_D_LUT4_O_I1 O=x2.o0_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=x2.o0(0) D=x2.o0_ff_CQZ_4_D QCK=x0.clk QEN=x2.o0_ff_CQZ_QEN QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.A0_ff_CQZ_4_D_LUT4_O_I0 O=x2.o0_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x1.D_ff_CQZ_D_LUT4_O_I3 O=x2.o0_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=chien_load_LUT4_I1_O I2=x0.clrn I3=x2.shorten O=x2.o0_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt ff CQZ=x2.o10(4) D=x2.o10_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o10(3) D=x2.o10_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o10_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o9(3) I2=x2.search I3=x0.clrn O=x2.o10_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o10(4) I2=x2.o10(3) I3=x2.o10(2) O=x2.o10_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o10(2) D=x2.o10_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o10_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o9(2) I2=x2.search I3=x0.clrn O=x2.o10_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.o10(1) I3=x2.o10_ff_CQZ_1_D_LUT4_O_I0 O=x2.o10_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=x2.o10(1) D=x2.o10_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o10_ff_CQZ_3_D_LUT4_O_I3 O=x2.o10_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o9(1) I1=x2.o10(1) I2=x2.o10(2) I3=x2.search O=x2.o10_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o10(0) D=x2.o10_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o10_ff_CQZ_4_D_LUT4_O_I0 I1=x2.o9(0) I2=x2.search I3=x0.clrn O=x2.o10_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o10(4) I2=x2.o10(1) I3=x2.o10(0) O=x2.o10_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x2.search I1=x2.o9(4) I2=x2.o10_ff_CQZ_D_LUT4_O_I2 I3=x0.clrn O=x2.o10_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x2.o10(0) I1=x2.o10(3) I2=x2.o10(4) I3=x2.search O=x2.o10_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=x2.o11(4) D=x2.o11_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o11(3) D=x2.o11_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o11_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o10(3) I2=x2.search I3=x0.clrn O=x2.o11_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x2.o11(1) I3=x2.o11_ff_CQZ_D_LUT4_O_I0 O=x2.o11_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=x2.o11(2) D=x2.o11_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.search I1=x2.o10(2) I2=x2.o11_ff_CQZ_2_D_LUT4_O_I2 I3=x0.clrn O=x2.o11_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x2.o11_ff_CQZ_D_LUT4_O_I0 I1=x2.o11(0) I2=x2.o11(1) I3=x2.search O=x2.o11_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=x2.o11(1) D=x2.o11_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o11_ff_CQZ_3_D_LUT4_O_I0 I1=x2.o10(1) I2=x2.search I3=x0.clrn O=x2.o11_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o11(1) I2=x2.o11(0) I3=x2.o11(4) O=x2.o11_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o11(0) D=x2.o11_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o11_ff_CQZ_4_D_LUT4_O_I0 I1=x2.o10(0) I2=x2.search I3=x0.clrn O=x2.o11_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o11(3) I2=x2.o11(0) I3=x2.o11(4) O=x2.o11_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x2.o11_ff_CQZ_D_LUT4_O_I0 I1=x2.o10(4) I2=x2.search I3=x0.clrn O=x2.o11_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o11(3) I2=x2.o11(2) I3=x2.o11(4) O=x2.o11_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt ff CQZ=x2.o1(4) D=x2.o1_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o1(3) D=x2.o1_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o1(2) I1=x2.o0(3) I2=x2.search I3=x0.clrn O=x2.o1_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.o1(2) D=x2.o1_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o1_ff_CQZ_2_D_LUT4_O_I3 O=x2.o1_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o0(2) I1=x2.o1(4) I2=x2.o1(1) I3=x2.search O=x2.o1_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o1(1) D=x2.o1_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o1(0) I1=x2.o0(1) I2=x2.search I3=x0.clrn O=x2.o1_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.o1(0) D=x2.o1_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o1(4) I1=x2.o0(0) I2=x2.search I3=x0.clrn O=x2.o1_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.o1(3) I1=x2.o0(4) I2=x2.search I3=x0.clrn O=x2.o1_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.o2(4) D=x2.o2_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o2(3) D=x2.o2_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o2_ff_CQZ_1_D_LUT4_O_I3 O=x2.o2_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o1(3) I1=x2.o2(4) I2=x2.o2(1) I3=x2.search O=x2.o2_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o2(2) D=x2.o2_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o2_ff_CQZ_2_D_LUT4_O_I3 O=x2.o2_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o1(2) I1=x2.o2(3) I2=x2.o2(0) I3=x2.search O=x2.o2_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o2(1) D=x2.o2_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o2(4) I1=x2.o1(1) I2=x2.search I3=x0.clrn O=x2.o2_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.o2(0) D=x2.o2_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o2(3) I1=x2.o1(0) I2=x2.search I3=x0.clrn O=x2.o2_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x2.o2(2) I1=x2.o1(4) I2=x2.search I3=x0.clrn O=x2.o2_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.o3(4) D=x2.o3_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o3(3) D=x2.o3_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o3_ff_CQZ_1_D_LUT4_O_I3 O=x2.o3_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o2(3) I1=x2.o3(3) I2=x2.o3(0) I3=x2.search O=x2.o3_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o3(2) D=x2.o3_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o3_ff_CQZ_2_D_LUT4_O_I3 O=x2.o3_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o2(2) I1=x2.o3(2) I2=x2.o3(4) I3=x2.search O=x2.o3_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o3(1) D=x2.o3_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o3(3) I1=x2.o2(1) I2=x2.search I3=x0.clrn O=x2.o3_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.o3(0) D=x2.o3_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o3(2) I1=x2.o2(0) I2=x2.search I3=x0.clrn O=x2.o3_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o3_ff_CQZ_D_LUT4_O_I3 O=x2.o3_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o2(4) I1=x2.o3(1) I2=x2.o3(4) I3=x2.search O=x2.o3_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o4(4) D=x2.o4_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o4(3) D=x2.o4_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o4_ff_CQZ_1_D_LUT4_O_I3 O=x2.o4_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o3(3) I1=x2.o4(2) I2=x2.o4(4) I3=x2.search O=x2.o4_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o4(2) D=x2.o4_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o4_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o3(2) I2=x2.search I3=x0.clrn O=x2.o4_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o4(4) I2=x2.o4(3) I3=x2.o4(1) O=x2.o4_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o4(1) D=x2.o4_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o4(2) I1=x2.o3(1) I2=x2.search I3=x0.clrn O=x2.o4_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt ff CQZ=x2.o4(0) D=x2.o4_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o4_ff_CQZ_4_D_LUT4_O_I3 O=x2.o4_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o3(0) I1=x2.o4(1) I2=x2.o4(4) I3=x2.search O=x2.o4_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o4_ff_CQZ_D_LUT4_O_I3 O=x2.o4_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o3(4) I1=x2.o4(0) I2=x2.o4(3) I3=x2.search O=x2.o4_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o5(4) D=x2.o5_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o5(3) D=x2.o5_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o5_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o4(3) I2=x2.search I3=x0.clrn O=x2.o5_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o5(4) I2=x2.o5(3) I3=x2.o5(1) O=x2.o5_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o5(2) D=x2.o5_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o5_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o4(2) I2=x2.search I3=x0.clrn O=x2.o5_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o5(3) I2=x2.o5(2) I3=x2.o5(0) O=x2.o5_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o5(1) D=x2.o5_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o5_ff_CQZ_3_D_LUT4_O_I3 O=x2.o5_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o4(1) I1=x2.o5(1) I2=x2.o5(4) I3=x2.search O=x2.o5_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o5(0) D=x2.o5_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o5_ff_CQZ_4_D_LUT4_O_I3 O=x2.o5_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o4(0) I1=x2.o5(0) I2=x2.o5(3) I3=x2.search O=x2.o5_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o5_ff_CQZ_D_LUT4_O_I3 O=x2.o5_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o4(4) I1=x2.o5(2) I2=x2.o5(4) I3=x2.search O=x2.o5_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o6(4) D=x2.o6_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o6(3) D=x2.o6_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o6_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o5(3) I2=x2.search I3=x0.clrn O=x2.o6_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o6(3) I2=x2.o6(2) I3=x2.o6(0) O=x2.o6_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o6(2) D=x2.o6_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o6_ff_CQZ_2_D_LUT4_O_I3 O=x2.o6_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o5(2) I1=x2.o6(1) I2=x2.o6(2) I3=x2.search O=x2.o6_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o6(1) D=x2.o6_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o6_ff_CQZ_3_D_LUT4_O_I3 O=x2.o6_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o5(1) I1=x2.o6(0) I2=x2.o6(3) I3=x2.search O=x2.o6_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o6(0) D=x2.o6_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o6_ff_CQZ_4_D_LUT4_O_I3 O=x2.o6_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o5(0) I1=x2.o6(2) I2=x2.o6(4) I3=x2.search O=x2.o6_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt LUT4 I0=x2.o6_ff_CQZ_D_LUT4_O_I0 I1=x2.o5(4) I2=x2.search I3=x0.clrn O=x2.o6_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o6(4) I2=x2.o6(3) I3=x2.o6(1) O=x2.o6_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o7(4) D=x2.o7_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o7(3) D=x2.o7_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o7_ff_CQZ_1_D_LUT4_O_I3 O=x2.o7_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o6(3) I1=x2.o7(1) I2=x2.o7(2) I3=x2.search O=x2.o7_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o7(2) D=x2.o7_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o7_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o6(2) I2=x2.search I3=x0.clrn O=x2.o7_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o7(4) I2=x2.o7(1) I3=x2.o7(0) O=x2.o7_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o7(1) D=x2.o7_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o7_ff_CQZ_3_D_LUT4_O_I3 O=x2.o7_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o6(1) I1=x2.o7(2) I2=x2.o7(4) I3=x2.search O=x2.o7_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o7(0) D=x2.o7_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.search I1=x2.o6(0) I2=x2.o7_ff_CQZ_4_D_LUT4_O_I2 I3=x0.clrn O=x2.o7_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x2.o7(1) I1=x2.o7(3) I2=x2.o7(4) I3=x2.search O=x2.o7_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=x2.o7_ff_CQZ_D_LUT4_O_I0 I1=x2.o6(4) I2=x2.search I3=x0.clrn O=x2.o7_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o7(3) I2=x2.o7(2) I3=x2.o7(0) O=x2.o7_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o8(4) D=x2.o8_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o8(3) D=x2.o8_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.search I1=x2.o7(3) I2=x2.o8_ff_CQZ_1_D_LUT4_O_I2 I3=x0.clrn O=x2.o8_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=x2.o8(0) I1=x2.o8(1) I2=x2.o8(4) I3=x2.search O=x2.o8_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt ff CQZ=x2.o8(2) D=x2.o8_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o8_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o7(2) I2=x2.search I3=x0.clrn O=x2.o8_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o8(4) I2=x2.o8(3) I3=x2.o8(0) O=x2.o8_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o8(1) D=x2.o8_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o8_ff_CQZ_3_D_LUT4_O_I0 I1=x2.o7(1) I2=x2.search I3=x0.clrn O=x2.o8_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o8(4) I2=x2.o8(3) I3=x2.o8(1) O=x2.o8_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o8(0) D=x2.o8_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o8_ff_CQZ_4_D_LUT4_O_I0 I1=x2.o7(0) I2=x2.search I3=x0.clrn O=x2.o8_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o8(3) I2=x2.o8(2) I3=x2.o8(0) O=x2.o8_ff_CQZ_4_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o8_ff_CQZ_D_LUT4_O_I3 O=x2.o8_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o7(4) I1=x2.o8(1) I2=x2.o8(2) I3=x2.search O=x2.o8_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt ff CQZ=x2.o9(4) D=x2.o9_ff_CQZ_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=x2.o9(3) D=x2.o9_ff_CQZ_1_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o9_ff_CQZ_1_D_LUT4_O_I0 I1=x2.o8(3) I2=x2.search I3=x0.clrn O=x2.o9_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o9(4) I2=x2.o9(3) I3=x2.o9(0) O=x2.o9_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o9(2) D=x2.o9_ff_CQZ_2_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o9_ff_CQZ_2_D_LUT4_O_I0 I1=x2.o8(2) I2=x2.search I3=x0.clrn O=x2.o9_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o9(4) I2=x2.o9(3) I3=x2.o9(2) O=x2.o9_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o9(1) D=x2.o9_ff_CQZ_3_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x2.o9_ff_CQZ_3_D_LUT4_O_I0 I1=x2.o8(1) I2=x2.search I3=x0.clrn O=x2.o9_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o9(3) I2=x2.o9(2) I3=x2.o9(0) O=x2.o9_ff_CQZ_3_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=x2.o9(0) D=x2.o9_ff_CQZ_4_D QCK=x0.clk QEN=chien_load_LUT4_I0_O QRT=x0.shift QST=x0.shift
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:49.14-49.100|/home/tpagarani/git/yosys-testing/Designs/rs_decoder_1/rtl/rs_decoder_1.v:962.2-1084.5|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=x0.clrn I3=x2.o9_ff_CQZ_4_D_LUT4_O_I3 O=x2.o9_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=x2.o8(0) I1=x2.o9(1) I2=x2.o9(2) I3=x2.search O=x2.o9_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001101010101
+.subckt LUT4 I0=x2.o9_ff_CQZ_D_LUT4_O_I0 I1=x2.o8(4) I2=x2.search I3=x0.clrn O=x2.o9_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=x0.shift I1=x2.o9(4) I2=x2.o9(1) I3=x2.o9(0) O=x2.o9_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(4) I3=x0.clrn O=u_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(3) I3=x0.clrn O=u_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(2) I3=x0.clrn O=u_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(1) I3=x0.clrn O=u_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=x0.shift I1=x0.shift I2=$iopadmap$x(0) I3=x0.clrn O=u_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.end
diff --git a/BENCHMARK/rs_decoder_1/rtl/rs_decoder_1.v b/BENCHMARK/rs_decoder_1/rtl/rs_decoder_1.v
new file mode 100644
index 0000000..7079022
--- /dev/null
+++ b/BENCHMARK/rs_decoder_1/rtl/rs_decoder_1.v
@@ -0,0 +1,1412 @@
+// -------------------------------------------------------------------------
+//Reed-Solomon decoder
+//Copyright (C) Wed May 22 09:59:27 2002
+//by Ming-Han Lei(hendrik@humanistic.org)
+//
+//This program is free software; you can redistribute it and/or
+//modify it under the terms of the GNU Lesser General Public License
+//as published by the Free Software Foundation; either version 2
+//of the License, or (at your option) any later version.
+//
+//This program is distributed in the hope that it will be useful,
+//but WITHOUT ANY WARRANTY; without even the implied warranty of
+//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//GNU Lesser General Public License for more details.
+//
+//You should have received a copy of the GNU Lesser General Public License
+//along with this program; if not, write to the Free Software
+//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+// --------------------------------------------------------------------------
+
+module rs_decoder_1(x, error, with_error, enable, valid, k, clk, clrn);
+	input enable, clk, clrn;
+	input [4:0] k, x;
+	output [4:0] error;
+	wire [4:0] error;
+	output with_error, valid;
+	reg valid;
+	wire with_error;
+
+	wire [4:0] s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
+	wire [4:0] lambda, omega, alpha;
+	reg [3:0] count;
+	reg [12:0] phase;
+	wire [4:0] D0, D1, DI;
+	//reg [4:0] D, D2;
+	wire [4:0] D, D2;
+	reg [4:0] u, length0, length2;
+	wire [4:0] length1, length3;
+	reg syn_enable, syn_init, syn_shift, berl_enable;
+	reg chien_search, chien_load, shorten;
+
+	always @ (chien_search or shorten)
+		valid = chien_search & ~shorten;
+
+	wire bit1;
+	assign bit1 = syn_shift&phase[0];
+	rsdec_syn x0 (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, u, syn_enable, bit1, syn_init, clk, clrn);
+	rsdec_berl x1 (lambda, omega, s0, s11, s10, s9, s8, s7, s6, s5, s4, s3, s2, s1, D0, D2, count, phase[0], phase[12], berl_enable, clk, clrn);
+	rsdec_chien x2 (error, alpha, lambda, omega, D1, DI, chien_search, chien_load, shorten, clk, clrn);
+	inverse x3 (DI, D);
+
+	always @ (posedge clk)// or negedge clrn)
+	begin
+		if (~clrn)
+		begin
+			syn_enable <= 0;
+			syn_shift <= 0;
+			berl_enable <= 0;
+			chien_search <= 1;
+			chien_load <= 0;
+			length0 <= 0;
+			length2 <= 31 - k;
+			count <= -1;
+			phase <= 1;
+			u <= 0;
+			shorten <= 1;
+			syn_init <= 0;
+		end
+		else
+		begin
+			if (enable & ~syn_enable & ~syn_shift)
+			begin
+				syn_enable <= 1;
+				syn_init <= 1;
+			end
+			else if (syn_enable)
+			begin
+				length0 <= length1;
+				syn_init <= 0;
+				if (length1 == k)
+				begin
+					syn_enable <= 0;
+					syn_shift <= 1;
+					berl_enable <= 1;
+				end
+			end
+			else if (berl_enable & with_error)
+			begin
+				if (phase[0])
+				begin
+					count <= count + 1;
+					if (count == 11)
+					begin
+						syn_shift <= 0;
+						length0 <= 0;
+						chien_load <= 1;
+						length2 <= length0;
+					end
+				end
+				phase <= {phase[11:0], phase[12]};
+			end
+			else if (berl_enable & ~with_error)
+				if (&count)
+				begin
+					syn_shift <= 0;
+					length0 <= 0;
+					berl_enable <= 0;
+				end
+				else
+					phase <= {phase[11:0], phase[12]};
+			else if (chien_load & phase[12])
+			begin
+				berl_enable <= 0;
+				chien_load <= 0;
+				chien_search <= 1;
+				count <= -1;
+				phase <= 1;
+			end
+			else if (chien_search)
+			begin
+				length2 <= length3;
+				if (length3 == 0)
+					chien_search <= 0;
+			end
+			else if (enable) u <= x;
+			else if (shorten == 1 && length2 == 0)
+				shorten <= 0;
+		end
+	end
+
+//	always @ (chien_search or D0 or D1)
+//		if (chien_search) D = D1;
+//		else D = D0;
+	assign D = chien_search ? D1 : D0;
+
+//	always @ (DI or alpha or chien_load)
+//		if (chien_load) D2 = alpha;
+//		else D2 = DI;
+	assign D2 = chien_load ? alpha : DI;
+
+	assign length1 = length0 + 1;
+	assign length3 = length2 - 1;
+//	always @ (syn_shift or s0 or s1 or s2 or s3 or s4 or s5 or s6 or s7 or s8 or s9 or s10 or s11)
+//		if (syn_shift && (s0 | s1 | s2 | s3 | s4 | s5 | s6 | s7 | s8 | s9 | s10 | s11)!= 0)
+//			with_error = 1;
+//		else with_error = 0;
+wire temp;
+	assign temp = syn_shift && (s0 | s1 | s2 | s3 | s4 | s5 | s6 | s7 | s8 | s9 | s10 | s11);
+	assign with_error = temp != 0 ? 1'b1 : 1'b0;
+
+endmodule
+
+// -------------------------------------------------------------------------
+//The inverse lookup table for Galois field
+//Copyright (C) Tue Apr  2 17:21:59 2002
+//by Ming-Han Lei(hendrik@humanistic.org)
+//
+//This program is free software; you can redistribute it and/or
+//modify it under the terms of the GNU Lesser General Public License
+//as published by the Free Software Foundation; either version 2
+//of the License, or (at your option) any later version.
+//
+//This program is distributed in the hope that it will be useful,
+//but WITHOUT ANY WARRANTY; without even the implied warranty of
+//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//GNU Lesser General Public License for more details.
+//
+//You should have received a copy of the GNU Lesser General Public License
+//along with this program; if not, write to the Free Software
+//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+// --------------------------------------------------------------------------
+
+module inverse(y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	case (x) // synopsys full_case parallel_case
+		1: y = 1; // 0 -> 31
+		2: y = 18; // 1 -> 30
+		4: y = 9; // 2 -> 29
+		8: y = 22; // 3 -> 28
+		16: y = 11; // 4 -> 27
+		5: y = 23; // 5 -> 26
+		10: y = 25; // 6 -> 25
+		20: y = 30; // 7 -> 24
+		13: y = 15; // 8 -> 23
+		26: y = 21; // 9 -> 22
+		17: y = 24; // 10 -> 21
+		7: y = 12; // 11 -> 20
+		14: y = 6; // 12 -> 19
+		28: y = 3; // 13 -> 18
+		29: y = 19; // 14 -> 17
+		31: y = 27; // 15 -> 16
+		27: y = 31; // 16 -> 15
+		19: y = 29; // 17 -> 14
+		3: y = 28; // 18 -> 13
+		6: y = 14; // 19 -> 12
+		12: y = 7; // 20 -> 11
+		24: y = 17; // 21 -> 10
+		21: y = 26; // 22 -> 9
+		15: y = 13; // 23 -> 8
+		30: y = 20; // 24 -> 7
+		25: y = 10; // 25 -> 6
+		23: y = 5; // 26 -> 5
+		11: y = 16; // 27 -> 4
+		22: y = 8; // 28 -> 3
+		9: y = 4; // 29 -> 2
+		18: y = 2; // 30 -> 1
+	endcase
+endmodule
+
+// -------------------------------------------------------------------------
+//Berlekamp circuit for Reed-Solomon decoder
+//Copyright (C) Tue Apr  2 17:21:42 2002
+//by Ming-Han Lei(hendrik@humanistic.org)
+//
+//This program is free software; you can redistribute it and/or
+//modify it under the terms of the GNU Lesser General Public License
+//as published by the Free Software Foundation; either version 2
+//of the License, or (at your option) any later version.
+//
+//This program is distributed in the hope that it will be useful,
+//but WITHOUT ANY WARRANTY; without even the implied warranty of
+//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//GNU Lesser General Public License for more details.
+//
+//You should have received a copy of the GNU Lesser General Public License
+//along with this program; if not, write to the Free Software
+//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+// --------------------------------------------------------------------------
+
+module rsdec_berl (lambda_out, omega_out, syndrome0, syndrome1, syndrome2, syndrome3, syndrome4, syndrome5, syndrome6, syndrome7, syndrome8, syndrome9, syndrome10, syndrome11, 
+		D, DI, count, phase0, phase12, enable, clk, clrn);
+	input clk, clrn, enable, phase0, phase12;
+	input [4:0] syndrome0;
+	input [4:0] syndrome1;
+	input [4:0] syndrome2;
+	input [4:0] syndrome3;
+	input [4:0] syndrome4;
+	input [4:0] syndrome5;
+	input [4:0] syndrome6;
+	input [4:0] syndrome7;
+	input [4:0] syndrome8;
+	input [4:0] syndrome9;
+	input [4:0] syndrome10;
+	input [4:0] syndrome11;
+	input [4:0] DI;
+	input [3:0] count;
+	output [4:0] lambda_out;
+	output [4:0] omega_out;
+	reg [4:0] lambda_out;
+	reg [4:0] omega_out;
+	output [4:0] D;
+	reg [4:0] D;
+
+	reg init, delta;
+	reg [2:0] L;
+	reg [4:0] lambda0;
+	reg [4:0] lambda1;
+	reg [4:0] lambda2;
+	reg [4:0] lambda3;
+	reg [4:0] lambda4;
+	reg [4:0] lambda5;
+	reg [4:0] lambda6;
+	reg [4:0] lambda7;
+	reg [4:0] lambda8;
+	reg [4:0] lambda9;
+	reg [4:0] lambda10;
+	reg [4:0] lambda11;
+	reg [4:0] B0;
+	reg [4:0] B1;
+	reg [4:0] B2;
+	reg [4:0] B3;
+	reg [4:0] B4;
+	reg [4:0] B5;
+	reg [4:0] B6;
+	reg [4:0] B7;
+	reg [4:0] B8;
+	reg [4:0] B9;
+	reg [4:0] B10;
+	reg [4:0] omega0;
+	reg [4:0] omega1;
+	reg [4:0] omega2;
+	reg [4:0] omega3;
+	reg [4:0] omega4;
+	reg [4:0] omega5;
+	reg [4:0] omega6;
+	reg [4:0] omega7;
+	reg [4:0] omega8;
+	reg [4:0] omega9;
+	reg [4:0] omega10;
+	reg [4:0] omega11;
+	reg [4:0] A0;
+	reg [4:0] A1;
+	reg [4:0] A2;
+	reg [4:0] A3;
+	reg [4:0] A4;
+	reg [4:0] A5;
+	reg [4:0] A6;
+	reg [4:0] A7;
+	reg [4:0] A8;
+	reg [4:0] A9;
+	reg [4:0] A10;
+
+	wire [4:0] tmp0;
+	wire [4:0] tmp1;
+	wire [4:0] tmp2;
+	wire [4:0] tmp3;
+	wire [4:0] tmp4;
+	wire [4:0] tmp5;
+	wire [4:0] tmp6;
+	wire [4:0] tmp7;
+	wire [4:0] tmp8;
+	wire [4:0] tmp9;
+	wire [4:0] tmp10;
+	wire [4:0] tmp11;
+
+	always @ (tmp1) lambda_out = tmp1;
+	always @ (tmp3) omega_out = tmp3;
+
+	always @ (L or D or count)
+		// delta = (D != 0 && 2*L <= i);
+		if (D != 0 && count >= {L, 1'b0}) delta = 1;
+		else delta = 0;
+
+	rsdec_berl_multiply x0 (tmp0, B10, D, lambda0, syndrome0, phase0);
+	rsdec_berl_multiply x1 (tmp1, lambda11, DI, lambda1, syndrome1, phase0);
+	rsdec_berl_multiply x2 (tmp2, A10, D, lambda2, syndrome2, phase0);
+	rsdec_berl_multiply x3 (tmp3, omega11, DI, lambda3, syndrome3, phase0);
+	multiply x4 (tmp4, lambda4, syndrome4);
+	multiply x5 (tmp5, lambda5, syndrome5);
+	multiply x6 (tmp6, lambda6, syndrome6);
+	multiply x7 (tmp7, lambda7, syndrome7);
+	multiply x8 (tmp8, lambda8, syndrome8);
+	multiply x9 (tmp9, lambda9, syndrome9);
+	multiply x10 (tmp10, lambda10, syndrome10);
+	multiply x11 (tmp11, lambda11, syndrome11);
+
+	always @ (posedge clk)// or negedge clrn)
+	begin
+		// for (j = t-1; j >=0; j--)
+		//	if (j != 0) lambda[j] += D * B[j-1];
+/*		if (~clrn)
+		begin
+			lambda0 <= 0;
+			lambda1 <= 0;
+			lambda2 <= 0;
+			lambda3 <= 0;
+			lambda4 <= 0;
+			lambda5 <= 0;
+			lambda6 <= 0;
+			lambda7 <= 0;
+			lambda8 <= 0;
+			lambda9 <= 0;
+			lambda10 <= 0;
+			lambda11 <= 0;
+			B0 <= 0;
+			B1 <= 0;
+			B2 <= 0;
+			B3 <= 0;
+			B4 <= 0;
+			B5 <= 0;
+			B6 <= 0;
+			B7 <= 0;
+			B8 <= 0;
+			B9 <= 0;
+			B10 <= 0;
+			omega0 <= 0;
+			omega1 <= 0;
+			omega2 <= 0;
+			omega3 <= 0;
+			omega4 <= 0;
+			omega5 <= 0;
+			omega6 <= 0;
+			omega7 <= 0;
+			omega8 <= 0;
+			omega9 <= 0;
+			omega10 <= 0;
+			omega11 <= 0;
+			A0 <= 0;
+			A1 <= 0;
+			A2 <= 0;
+			A3 <= 0;
+			A4 <= 0;
+			A5 <= 0;
+			A6 <= 0;
+			A7 <= 0;
+			A8 <= 0;
+			A9 <= 0;
+			A10 <= 0;
+//			for (j = 0; j < 12; j = j + 1) lambda[j] <= 0;
+//			for (j = 0; j < 11; j = j + 1) B[j] <= 0;
+//			for (j = 0; j < 12; j = j + 1) omega[j] <= 0;
+//			for (j = 0; j < 11; j = j + 1) A[j] <= 0;
+		end
+		else*/ if (~enable)
+		begin
+			lambda0 <= 1;
+			lambda1 <= 0;
+			lambda2 <= 0;
+			lambda3 <= 0;
+			lambda4 <= 0;
+			lambda5 <= 0;
+			lambda6 <= 0;
+			lambda7 <= 0;
+			lambda8 <= 0;
+			lambda9 <= 0;
+			lambda10 <= 0;
+			lambda11 <= 0;
+			//for (j = 1; j < 12; j = j +1) lambda[j] <= 0;
+			B0 <= 1;
+			B1 <= 0;
+			B2 <= 0;
+			B3 <= 0;
+			B4 <= 0;
+			B5 <= 0;
+			B6 <= 0;
+			B7 <= 0;
+			B8 <= 0;
+			B9 <= 0;
+			B10 <= 0;
+			//for (j = 1; j < 11; j = j +1) B[j] <= 0;
+			omega0 <= 1;
+			omega1 <= 0;
+			omega2 <= 0;
+			omega3 <= 0;
+			omega4 <= 0;
+			omega5 <= 0;
+			omega6 <= 0;
+			omega7 <= 0;
+			omega8 <= 0;
+			omega9 <= 0;
+			omega10 <= 0;
+			omega11 <= 0;
+			//for (j = 1; j < 12; j = j +1) omega[j] <= 0;
+			A0 <= 0;
+			A1 <= 0;
+			A2 <= 0;
+			A3 <= 0;
+			A4 <= 0;
+			A5 <= 0;
+			A6 <= 0;
+			A7 <= 0;
+			A8 <= 0;
+			A9 <= 0;
+			A10 <= 0;
+			//for (j = 0; j < 11; j = j + 1) A[j] <= 0;
+		end
+		else
+		begin
+			if (~phase0)
+			begin
+				if (~phase12) lambda0 <= lambda11 ^ tmp0;
+				else lambda0 <= lambda11;
+				//for (j = 1; j < 12; j = j + 1)
+					//lambda[j] <= lambda[j-1];
+				lambda1 <= lambda0;
+				lambda2 <= lambda1;
+				lambda3 <= lambda2;
+				lambda4 <= lambda3;
+				lambda5 <= lambda4;
+				lambda6 <= lambda5;
+				lambda7 <= lambda6;
+				lambda8 <= lambda7;
+				lambda9 <= lambda8;
+				lambda10 <= lambda9;
+				lambda11 <= lambda10;
+//			end
+
+		// for (j = t-1; j >=0; j--)
+		//	if (delta) B[j] = lambda[j] *DI;
+		//	else if (j != 0) B[j] = B[j-1];
+		//	else B[j] = 0;
+//			if (~phase0)
+//			begin
+				if (delta)	B0 <= tmp1;
+				else if (~phase12) B0 <= B10;
+				else B0 <= 0;
+				//for (j = 1; j < 11; j = j + 1)
+				//	B[j] <= B[j-1];
+				B1 <= B0;
+				B2 <= B1;
+				B3 <= B2;
+				B4 <= B3;
+				B5 <= B4;
+				B6 <= B5;
+				B7 <= B6;
+				B8 <= B7;
+				B9 <= B8;
+				B10 <= B9;
+//			end
+
+		// for (j = t-1; j >=0; j--)
+		//	if (j != 0) omega[j] += D * A[j-1];
+//			if (~phase0)
+//			begin
+				if (~phase12) omega0 <= omega11 ^ tmp2;
+				else omega0 <= omega11;
+				//for (j = 1; j < 12; j = j + 1)
+				//	omega[j] <= omega[j-1];
+				omega1 <= omega0;
+				omega2 <= omega1;
+				omega3 <= omega2;
+				omega4 <= omega3;
+				omega5 <= omega4;
+				omega6 <= omega5;
+				omega7 <= omega6;
+				omega8 <= omega7;
+				omega9 <= omega8;
+				omega10 <= omega9;
+				omega11 <= omega10;
+//			end
+
+		// for (j = t-1; j >=0; j--)
+		//	if (delta) A[j] = omega[j] *DI;
+		//	else if (j != 0) A[j] = A[j-1];
+		//	else A[j] = 0;
+//			if (~phase0)
+//			begin
+				if (delta)	A0 <= tmp3;
+				else if (~phase12) A0 <= A10;
+				//for (j = 1; j < 11; j = j + 1)
+				//	A[j] <= A[j-1];
+				A1 <= A0;
+				A2 <= A1;
+				A3 <= A2;
+				A4 <= A3;
+				A5 <= A4;
+				A6 <= A5;
+				A7 <= A6;
+				A8 <= A7;
+				A9 <= A8;
+				A10 <= A9;
+//			end
+			end
+		end
+	end
+
+	always @ (posedge clk)// or negedge clrn)
+	begin
+		if (~clrn)
+		begin
+			L <= 0;
+			D <= 0;
+		end
+		else
+		begin
+		// if (delta) L = i - L + 1;
+			if ((phase0 & delta) && (count != -1)) L <= count - L + 1;
+		//for (D = j = 0; j < t; j = j + 1)
+		//	D += lambda[j] * syndrome[t-j-1];
+			if (phase0)
+				D <= tmp0 ^ tmp1 ^ tmp2 ^ tmp3 ^ tmp4 ^ tmp5 ^ tmp6 ^ tmp7 ^ tmp8 ^ tmp9 ^ tmp10 ^ tmp11;
+		end
+	end
+	
+endmodule
+
+
+module rsdec_berl_multiply (y, a, b, c, d, e);
+	input [4:0] a, b, c, d;
+	input e;
+	output [4:0] y;
+	wire [4:0] y;
+	reg [4:0] p, q;
+
+	always @ (a or c or e)
+		if (e) p = c;
+		else p = a;
+	always @ (b or d or e)
+		if (e) q = d;
+		else q = b;
+
+	multiply x0 (y, p, q);
+
+endmodule
+
+module multiply (y, a, b);
+	input [4:0] a, b;
+	output [4:0] y;
+	reg [9:0] tempy;
+	wire [4:0] y;
+
+	assign y = tempy[4:0];
+
+	always @(a or b)
+	begin
+		tempy = a * b;
+	end
+/*
+	always @ (a or b)
+	begin
+		y[0] = (a[0] & b[0]) ^ (a[1] & b[4]) ^ (a[2] & b[3]) ^ (a[3] & b[2]) ^ (a[4] & b[1]) ^ (a[4] & b[4]);
+		y[1] = (a[0] & b[1]) ^ (a[1] & b[0]) ^ (a[2] & b[4]) ^ (a[3] & b[3]) ^ (a[4] & b[2]);
+		y[2] = (a[0] & b[2]) ^ (a[1] & b[1]) ^ (a[1] & b[4]) ^ (a[2] & b[0]) ^ (a[2] & b[3]) ^ (a[3] & b[2]) ^ (a[3] & b[4]) ^ (a[4] & b[1]) ^ (a[4] & b[3]) ^ (a[4] & b[4]);
+		y[3] = (a[0] & b[3]) ^ (a[1] & b[2]) ^ (a[2] & b[1]) ^ (a[2] & b[4]) ^ (a[3] & b[0]) ^ (a[3] & b[3]) ^ (a[4] & b[2]) ^ (a[4] & b[4]);
+		y[4] = (a[0] & b[4]) ^ (a[1] & b[3]) ^ (a[2] & b[2]) ^ (a[3] & b[1]) ^ (a[3] & b[4]) ^ (a[4] & b[0]) ^ (a[4] & b[3]);
+	endi 
+*/
+endmodule
+
+// -------------------------------------------------------------------------
+//Chien-Forney search circuit for Reed-Solomon decoder
+//Copyright (C) Tue Apr  2 17:21:51 2002
+//by Ming-Han Lei(hendrik@humanistic.org)
+//
+//This program is free software; you can redistribute it and/or
+//modify it under the terms of the GNU Lesser General Public License
+//as published by the Free Software Foundation; either version 2
+//of the License, or (at your option) any later version.
+//
+//This program is distributed in the hope that it will be useful,
+//but WITHOUT ANY WARRANTY; without even the implied warranty of
+//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//GNU Lesser General Public License for more details.
+//
+//You should have received a copy of the GNU Lesser General Public License
+//along with this program; if not, write to the Free Software
+//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+// --------------------------------------------------------------------------
+
+module rsdec_chien_scale0 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[0];
+		y[1] = x[1];
+		y[2] = x[2];
+		y[3] = x[3];
+		y[4] = x[4];
+	end
+endmodule
+
+module rsdec_chien_scale1 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[4];
+		y[1] = x[0];
+		y[2] = x[1] ^ x[4];
+		y[3] = x[2];
+		y[4] = x[3];
+	end
+endmodule
+
+module rsdec_chien_scale2 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[3];
+		y[1] = x[4];
+		y[2] = x[0] ^ x[3];
+		y[3] = x[1] ^ x[4];
+		y[4] = x[2];
+	end
+endmodule
+
+module rsdec_chien_scale3 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[2];
+		y[1] = x[3];
+		y[2] = x[2] ^ x[4];
+		y[3] = x[0] ^ x[3];
+		y[4] = x[1] ^ x[4];
+	end
+endmodule
+
+module rsdec_chien_scale4 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[1] ^ x[4];
+		y[1] = x[2];
+		y[2] = x[1] ^ x[3] ^ x[4];
+		y[3] = x[2] ^ x[4];
+		y[4] = x[0] ^ x[3];
+	end
+endmodule
+
+module rsdec_chien_scale5 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[0] ^ x[3];
+		y[1] = x[1] ^ x[4];
+		y[2] = x[0] ^ x[2] ^ x[3];
+		y[3] = x[1] ^ x[3] ^ x[4];
+		y[4] = x[2] ^ x[4];
+	end
+endmodule
+
+module rsdec_chien_scale6 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[2] ^ x[4];
+		y[1] = x[0] ^ x[3];
+		y[2] = x[1] ^ x[2];
+		y[3] = x[0] ^ x[2] ^ x[3];
+		y[4] = x[1] ^ x[3] ^ x[4];
+	end
+endmodule
+
+module rsdec_chien_scale7 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[1] ^ x[3] ^ x[4];
+		y[1] = x[2] ^ x[4];
+		y[2] = x[0] ^ x[1] ^ x[4];
+		y[3] = x[1] ^ x[2];
+		y[4] = x[0] ^ x[2] ^ x[3];
+	end
+endmodule
+
+module rsdec_chien_scale8 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[0] ^ x[2] ^ x[3];
+		y[1] = x[1] ^ x[3] ^ x[4];
+		y[2] = x[0] ^ x[3] ^ x[4];
+		y[3] = x[0] ^ x[1] ^ x[4];
+		y[4] = x[1] ^ x[2];
+	end
+endmodule
+
+module rsdec_chien_scale9 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[1] ^ x[2];
+		y[1] = x[0] ^ x[2] ^ x[3];
+		y[2] = x[2] ^ x[3] ^ x[4];
+		y[3] = x[0] ^ x[3] ^ x[4];
+		y[4] = x[0] ^ x[1] ^ x[4];
+	end
+endmodule
+
+module rsdec_chien_scale10 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[0] ^ x[1] ^ x[4];
+		y[1] = x[1] ^ x[2];
+		y[2] = x[1] ^ x[2] ^ x[3] ^ x[4];
+		y[3] = x[2] ^ x[3] ^ x[4];
+		y[4] = x[0] ^ x[3] ^ x[4];
+	end
+endmodule
+
+module rsdec_chien_scale11 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+
+	always @ (x)
+	begin
+		y[0] = x[0] ^ x[3] ^ x[4];
+		y[1] = x[0] ^ x[1] ^ x[4];
+		y[2] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4];
+		y[3] = x[1] ^ x[2] ^ x[3] ^ x[4];
+		y[4] = x[2] ^ x[3] ^ x[4];
+	end
+endmodule
+
+module rsdec_chien (error, alpha, lambda, omega, even, D, search, load, shorten, clk, clrn);
+	input clk, clrn, load, search, shorten;
+	input [4:0] D;
+	input [4:0] lambda;
+	input [4:0] omega;
+	output [4:0] even, error;
+	output [4:0] alpha;
+	reg [4:0] even, error;
+	reg [4:0] alpha;
+
+	wire [4:0] scale0;
+	wire [4:0] scale1;
+	wire [4:0] scale2;
+	wire [4:0] scale3;
+	wire [4:0] scale4;
+	wire [4:0] scale5;
+	wire [4:0] scale6;
+	wire [4:0] scale7;
+	wire [4:0] scale8;
+	wire [4:0] scale9;
+	wire [4:0] scale10;
+	wire [4:0] scale11;
+	wire [4:0] scale12;
+	wire [4:0] scale13;
+	wire [4:0] scale14;
+	wire [4:0] scale15;
+	wire [4:0] scale16;
+	wire [4:0] scale17;
+	wire [4:0] scale18;
+	wire [4:0] scale19;
+	wire [4:0] scale20;
+	wire [4:0] scale21;
+	wire [4:0] scale22;
+	wire [4:0] scale23;
+	reg [4:0] data0;
+	reg [4:0] data1;
+	reg [4:0] data2;
+	reg [4:0] data3;
+	reg [4:0] data4;
+	reg [4:0] data5;
+	reg [4:0] data6;
+	reg [4:0] data7;
+	reg [4:0] data8;
+	reg [4:0] data9;
+	reg [4:0] data10;
+	reg [4:0] data11;
+	reg [4:0] a0;
+	reg [4:0] a1;
+	reg [4:0] a2;
+	reg [4:0] a3;
+	reg [4:0] a4;
+	reg [4:0] a5;
+	reg [4:0] a6;
+	reg [4:0] a7;
+	reg [4:0] a8;
+	reg [4:0] a9;
+	reg [4:0] a10;
+	reg [4:0] a11;
+	reg [4:0] l0;
+	reg [4:0] l1;
+	reg [4:0] l2;
+	reg [4:0] l3;
+	reg [4:0] l4;
+	reg [4:0] l5;
+	reg [4:0] l6;
+	reg [4:0] l7;
+	reg [4:0] l8;
+	reg [4:0] l9;
+	reg [4:0] l10;
+	reg [4:0] l11;
+	reg [4:0] o0;
+	reg [4:0] o1;
+	reg [4:0] o2;
+	reg [4:0] o3;
+	reg [4:0] o4;
+	reg [4:0] o5;
+	reg [4:0] o6;
+	reg [4:0] o7;
+	reg [4:0] o8;
+	reg [4:0] o9;
+	reg [4:0] o10;
+	reg [4:0] o11;
+	reg [4:0] odd, numerator;
+	wire [4:0] tmp;
+
+	rsdec_chien_scale0 x0 (scale0, data0);
+	rsdec_chien_scale1 x1 (scale1, data1);
+	rsdec_chien_scale2 x2 (scale2, data2);
+	rsdec_chien_scale3 x3 (scale3, data3);
+	rsdec_chien_scale4 x4 (scale4, data4);
+	rsdec_chien_scale5 x5 (scale5, data5);
+	rsdec_chien_scale6 x6 (scale6, data6);
+	rsdec_chien_scale7 x7 (scale7, data7);
+	rsdec_chien_scale8 x8 (scale8, data8);
+	rsdec_chien_scale9 x9 (scale9, data9);
+	rsdec_chien_scale10 x10 (scale10, data10);
+	rsdec_chien_scale11 x11 (scale11, data11);
+	rsdec_chien_scale0 x12 (scale12, o0);
+	rsdec_chien_scale1 x13 (scale13, o1);
+	rsdec_chien_scale2 x14 (scale14, o2);
+	rsdec_chien_scale3 x15 (scale15, o3);
+	rsdec_chien_scale4 x16 (scale16, o4);
+	rsdec_chien_scale5 x17 (scale17, o5);
+	rsdec_chien_scale6 x18 (scale18, o6);
+	rsdec_chien_scale7 x19 (scale19, o7);
+	rsdec_chien_scale8 x20 (scale20, o8);
+	rsdec_chien_scale9 x21 (scale21, o9);
+	rsdec_chien_scale10 x22 (scale22, o10);
+	rsdec_chien_scale11 x23 (scale23, o11);
+
+	always @ (shorten or a0 or l0)
+		if (shorten) data0 = a0;
+		else data0 = l0;
+
+	always @ (shorten or a1 or l1)
+		if (shorten) data1 = a1;
+		else data1 = l1;
+
+	always @ (shorten or a2 or l2)
+		if (shorten) data2 = a2;
+		else data2 = l2;
+
+	always @ (shorten or a3 or l3)
+		if (shorten) data3 = a3;
+		else data3 = l3;
+
+	always @ (shorten or a4 or l4)
+		if (shorten) data4 = a4;
+		else data4 = l4;
+
+	always @ (shorten or a5 or l5)
+		if (shorten) data5 = a5;
+		else data5 = l5;
+
+	always @ (shorten or a6 or l6)
+		if (shorten) data6 = a6;
+		else data6 = l6;
+
+	always @ (shorten or a7 or l7)
+		if (shorten) data7 = a7;
+		else data7 = l7;
+
+	always @ (shorten or a8 or l8)
+		if (shorten) data8 = a8;
+		else data8 = l8;
+
+	always @ (shorten or a9 or l9)
+		if (shorten) data9 = a9;
+		else data9 = l9;
+
+	always @ (shorten or a10 or l10)
+		if (shorten) data10 = a10;
+		else data10 = l10;
+
+	always @ (shorten or a11 or l11)
+		if (shorten) data11 = a11;
+		else data11 = l11;
+
+	always @ (posedge clk)// or negedge clrn)
+	begin
+		if (~clrn)
+		begin
+			l0 <= 0;
+			l1 <= 0;
+			l2 <= 0;
+			l3 <= 0;
+			l4 <= 0;
+			l5 <= 0;
+			l6 <= 0;
+			l7 <= 0;
+			l8 <= 0;
+			l9 <= 0;
+			l10 <= 0;
+			l11 <= 0;
+			o0 <= 0;
+			o1 <= 0;
+			o2 <= 0;
+			o3 <= 0;
+			o4 <= 0;
+			o5 <= 0;
+			o6 <= 0;
+			o7 <= 0;
+			o8 <= 0;
+			o9 <= 0;
+			o10 <= 0;
+			o11 <= 0;
+			a0 <= 1;
+			a1 <= 1;
+			a2 <= 1;
+			a3 <= 1;
+			a4 <= 1;
+			a5 <= 1;
+			a6 <= 1;
+			a7 <= 1;
+			a8 <= 1;
+			a9 <= 1;
+			a10 <= 1;
+			a11 <= 1;
+		end
+		else if (shorten)
+		begin
+			a0 <= scale0;
+			a1 <= scale1;
+			a2 <= scale2;
+			a3 <= scale3;
+			a4 <= scale4;
+			a5 <= scale5;
+			a6 <= scale6;
+			a7 <= scale7;
+			a8 <= scale8;
+			a9 <= scale9;
+			a10 <= scale10;
+			a11 <= scale11;
+		end
+		else if (search)
+		begin
+			l0 <= scale0;
+			l1 <= scale1;
+			l2 <= scale2;
+			l3 <= scale3;
+			l4 <= scale4;
+			l5 <= scale5;
+			l6 <= scale6;
+			l7 <= scale7;
+			l8 <= scale8;
+			l9 <= scale9;
+			l10 <= scale10;
+			l11 <= scale11;
+			o0 <= scale12;
+			o1 <= scale13;
+			o2 <= scale14;
+			o3 <= scale15;
+			o4 <= scale16;
+			o5 <= scale17;
+			o6 <= scale18;
+			o7 <= scale19;
+			o8 <= scale20;
+			o9 <= scale21;
+			o10 <= scale22;
+			o11 <= scale23;
+		end
+		else if (load)
+		begin
+			l0 <= lambda;
+			l1 <= l0;
+			l2 <= l1;
+			l3 <= l2;
+			l4 <= l3;
+			l5 <= l4;
+			l6 <= l5;
+			l7 <= l6;
+			l8 <= l7;
+			l9 <= l8;
+			l10 <= l9;
+			l11 <= l10;
+			o0 <= omega;
+			o1 <= o0;
+			o2 <= o1;
+			o3 <= o2;
+			o4 <= o3;
+			o5 <= o4;
+			o6 <= o5;
+			o7 <= o6;
+			o8 <= o7;
+			o9 <= o8;
+			o10 <= o9;
+			o11 <= o10;
+			a0 <= a11;
+			a1 <= a0;
+			a2 <= a1;
+			a3 <= a2;
+			a4 <= a3;
+			a5 <= a4;
+			a6 <= a5;
+			a7 <= a6;
+			a8 <= a7;
+			a9 <= a8;
+			a10 <= a9;
+			a11 <= a10;
+		end
+	end
+
+	always @ (l0 or l2 or l4 or l6 or l8 or l10)
+		even = l0 ^ l2 ^ l4 ^ l6 ^ l8 ^ l10;
+
+	always @ (l1 or l3 or l5 or l7 or l9 or l11)
+		odd = l1 ^ l3 ^ l5 ^ l7 ^ l9 ^ l11;
+
+	always @ (o0 or o1 or o2 or o3 or o4 or o5 or o6 or o7 or o8 or o9 or o10 or o11)
+		numerator = o0 ^ o1 ^ o2 ^ o3 ^ o4 ^ o5 ^ o6 ^ o7 ^ o8 ^ o9 ^ o10 ^ o11;
+
+	multiply m0 (tmp, numerator, D);
+
+	always @ (even or odd or tmp)
+		if (even == odd) error = tmp;
+		else error = 0;
+
+	always @ (a11) alpha = a11;
+
+endmodule
+
+// -------------------------------------------------------------------------
+//Syndrome generator circuit in Reed-Solomon Decoder
+//Copyright (C) Tue Apr  2 17:22:07 2002
+//by Ming-Han Lei(hendrik@humanistic.org)
+//
+//This program is free software; you can redistribute it and/or
+//modify it under the terms of the GNU Lesser General Public License
+//as published by the Free Software Foundation; either version 2
+//of the License, or (at your option) any later version.
+//
+//This program is distributed in the hope that it will be useful,
+//but WITHOUT ANY WARRANTY; without even the implied warranty of
+//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//GNU General Public License for more details.
+//
+//You should have received a copy of the GNU Lesser General Public License
+//along with this program; if not, write to the Free Software
+//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+// --------------------------------------------------------------------------
+
+module rsdec_syn_m0 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[4];
+		y[1] = x[0];
+		y[2] = x[1] ^ x[4];
+		y[3] = x[2];
+		y[4] = x[3];
+	end
+endmodule
+
+module rsdec_syn_m1 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[3];
+		y[1] = x[4];
+		y[2] = x[0] ^ x[3];
+		y[3] = x[1] ^ x[4];
+		y[4] = x[2];
+	end
+endmodule
+
+module rsdec_syn_m2 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[2];
+		y[1] = x[3];
+		y[2] = x[2] ^ x[4];
+		y[3] = x[0] ^ x[3];
+		y[4] = x[1] ^ x[4];
+	end
+endmodule
+
+module rsdec_syn_m3 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[1] ^ x[4];
+		y[1] = x[2];
+		y[2] = x[1] ^ x[3] ^ x[4];
+		y[3] = x[2] ^ x[4];
+		y[4] = x[0] ^ x[3];
+	end
+endmodule
+
+module rsdec_syn_m4 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[0] ^ x[3];
+		y[1] = x[1] ^ x[4];
+		y[2] = x[0] ^ x[2] ^ x[3];
+		y[3] = x[1] ^ x[3] ^ x[4];
+		y[4] = x[2] ^ x[4];
+	end
+endmodule
+
+module rsdec_syn_m5 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[2] ^ x[4];
+		y[1] = x[0] ^ x[3];
+		y[2] = x[1] ^ x[2];
+		y[3] = x[0] ^ x[2] ^ x[3];
+		y[4] = x[1] ^ x[3] ^ x[4];
+	end
+endmodule
+
+module rsdec_syn_m6 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[1] ^ x[3] ^ x[4];
+		y[1] = x[2] ^ x[4];
+		y[2] = x[0] ^ x[1] ^ x[4];
+		y[3] = x[1] ^ x[2];
+		y[4] = x[0] ^ x[2] ^ x[3];
+	end
+endmodule
+
+module rsdec_syn_m7 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[0] ^ x[2] ^ x[3];
+		y[1] = x[1] ^ x[3] ^ x[4];
+		y[2] = x[0] ^ x[3] ^ x[4];
+		y[3] = x[0] ^ x[1] ^ x[4];
+		y[4] = x[1] ^ x[2];
+	end
+endmodule
+
+module rsdec_syn_m8 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[1] ^ x[2];
+		y[1] = x[0] ^ x[2] ^ x[3];
+		y[2] = x[2] ^ x[3] ^ x[4];
+		y[3] = x[0] ^ x[3] ^ x[4];
+		y[4] = x[0] ^ x[1] ^ x[4];
+	end
+endmodule
+
+module rsdec_syn_m9 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[0] ^ x[1] ^ x[4];
+		y[1] = x[1] ^ x[2];
+		y[2] = x[1] ^ x[2] ^ x[3] ^ x[4];
+		y[3] = x[2] ^ x[3] ^ x[4];
+		y[4] = x[0] ^ x[3] ^ x[4];
+	end
+endmodule
+
+module rsdec_syn_m10 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[0] ^ x[3] ^ x[4];
+		y[1] = x[0] ^ x[1] ^ x[4];
+		y[2] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4];
+		y[3] = x[1] ^ x[2] ^ x[3] ^ x[4];
+		y[4] = x[2] ^ x[3] ^ x[4];
+	end
+endmodule
+
+module rsdec_syn_m11 (y, x);
+	input [4:0] x;
+	output [4:0] y;
+	reg [4:0] y;
+	always @ (x)
+	begin
+		y[0] = x[2] ^ x[3] ^ x[4];
+		y[1] = x[0] ^ x[3] ^ x[4];
+		y[2] = x[0] ^ x[1] ^ x[2] ^ x[3];
+		y[3] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4];
+		y[4] = x[1] ^ x[2] ^ x[3] ^ x[4];
+	end
+endmodule
+
+module rsdec_syn (y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, u, enable, shift, init, clk, clrn);
+	input [4:0] u;
+	input clk, clrn, shift, init, enable;
+	output [4:0] y0;
+	output [4:0] y1;
+	output [4:0] y2;
+	output [4:0] y3;
+	output [4:0] y4;
+	output [4:0] y5;
+	output [4:0] y6;
+	output [4:0] y7;
+	output [4:0] y8;
+	output [4:0] y9;
+	output [4:0] y10;
+	output [4:0] y11;
+	reg [4:0] y0;
+	reg [4:0] y1;
+	reg [4:0] y2;
+	reg [4:0] y3;
+	reg [4:0] y4;
+	reg [4:0] y5;
+	reg [4:0] y6;
+	reg [4:0] y7;
+	reg [4:0] y8;
+	reg [4:0] y9;
+	reg [4:0] y10;
+	reg [4:0] y11;
+
+	wire [4:0] scale0;
+	wire [4:0] scale1;
+	wire [4:0] scale2;
+	wire [4:0] scale3;
+	wire [4:0] scale4;
+	wire [4:0] scale5;
+	wire [4:0] scale6;
+	wire [4:0] scale7;
+	wire [4:0] scale8;
+	wire [4:0] scale9;
+	wire [4:0] scale10;
+	wire [4:0] scale11;
+
+	rsdec_syn_m0 m0 (scale0, y0);
+	rsdec_syn_m1 m1 (scale1, y1);
+	rsdec_syn_m2 m2 (scale2, y2);
+	rsdec_syn_m3 m3 (scale3, y3);
+	rsdec_syn_m4 m4 (scale4, y4);
+	rsdec_syn_m5 m5 (scale5, y5);
+	rsdec_syn_m6 m6 (scale6, y6);
+	rsdec_syn_m7 m7 (scale7, y7);
+	rsdec_syn_m8 m8 (scale8, y8);
+	rsdec_syn_m9 m9 (scale9, y9);
+	rsdec_syn_m10 m10 (scale10, y10);
+	rsdec_syn_m11 m11 (scale11, y11);
+
+	always @ (posedge clk)// or negedge clrn)
+	begin
+		if (~clrn)
+		begin
+			y0 <= 0;
+			y1 <= 0;
+			y2 <= 0;
+			y3 <= 0;
+			y4 <= 0;
+			y5 <= 0;
+			y6 <= 0;
+			y7 <= 0;
+			y8 <= 0;
+			y9 <= 0;
+			y10 <= 0;
+			y11 <= 0;
+		end
+		else if (init)
+		begin
+			y0 <= u;
+			y1 <= u;
+			y2 <= u;
+			y3 <= u;
+			y4 <= u;
+			y5 <= u;
+			y6 <= u;
+			y7 <= u;
+			y8 <= u;
+			y9 <= u;
+			y10 <= u;
+			y11 <= u;
+		end
+		else if (enable)
+		begin
+			y0 <= scale0 ^ u;
+			y1 <= scale1 ^ u;
+			y2 <= scale2 ^ u;
+			y3 <= scale3 ^ u;
+			y4 <= scale4 ^ u;
+			y5 <= scale5 ^ u;
+			y6 <= scale6 ^ u;
+			y7 <= scale7 ^ u;
+			y8 <= scale8 ^ u;
+			y9 <= scale9 ^ u;
+			y10 <= scale10 ^ u;
+			y11 <= scale11 ^ u;
+		end
+		else if (shift)
+		begin
+			y0 <= y1;
+			y1 <= y2;
+			y2 <= y3;
+			y3 <= y4;
+			y4 <= y5;
+			y5 <= y6;
+			y6 <= y7;
+			y7 <= y8;
+			y8 <= y9;
+			y9 <= y10;
+			y10 <= y11;
+			y11 <= y0;
+		end
+	end
+
+endmodule
+
diff --git a/BENCHMARK/sdc_controller/rtl/bistable_domain_cross.v b/BENCHMARK/sdc_controller/rtl/bistable_domain_cross.v
new file mode 100644
index 0000000..b0c0be4
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/bistable_domain_cross.v
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// bistable_domain_cross.v                                      ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Clock synchronisation beetween two clock domains.            ////
+//// Assumption is that input signal duration has to be at least  ////
+//// one clk_b clock period.                                      //// 
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+module bistable_domain_cross(
+    rst,
+    clk_a,
+    in,
+    clk_b,
+    out
+);
+parameter width = 1;
+input rst;
+input clk_a;
+input [width-1:0] in;
+input clk_b;
+output [width-1:0] out;
+
+// We use a two-stages shift-register to synchronize in to the clk_b clock domain
+reg [width-1:0] sync_clk_b [1:0];
+always @(posedge clk_b or posedge rst)
+begin
+    if (rst == 1) begin
+        sync_clk_b[0] <= 0;
+        sync_clk_b[1] <= 0;
+    end else begin
+        sync_clk_b[0] <= in;
+        sync_clk_b[1] <= sync_clk_b[0];
+    end
+end
+
+assign out = sync_clk_b[1];  // new signal synchronized to (=ready to be used in) clk_b domain
+
+endmodule 
diff --git a/BENCHMARK/sdc_controller/rtl/edge_detect.v b/BENCHMARK/sdc_controller/rtl/edge_detect.v
new file mode 100644
index 0000000..99f14be
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/edge_detect.v
@@ -0,0 +1,64 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// edge_detect.v                                                ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Signal edge detection. If input signal transitions between   ////
+//// two states, output signal is generated for one clock cycle.  ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+module edge_detect (
+    input rst,
+    input clk, 
+    input sig,
+    output rise,
+    output fall
+);
+
+reg [1:0] sig_reg;
+
+always @(posedge clk or posedge rst)
+    if (rst == 1'b1)
+        sig_reg <= 2'b00;
+    else
+        sig_reg <= {sig_reg[0], sig};
+
+assign rise = sig_reg[0] == 1'b1 && sig_reg[1] == 1'b0 ? 1'b1 : 1'b0;
+assign fall = sig_reg[0] == 1'b0 && sig_reg[1] == 1'b1 ? 1'b1 : 1'b0;
+
+endmodule
\ No newline at end of file
diff --git a/BENCHMARK/sdc_controller/rtl/generic_dpram.v b/BENCHMARK/sdc_controller/rtl/generic_dpram.v
new file mode 100644
index 0000000..02ff9b7
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/generic_dpram.v
@@ -0,0 +1,501 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Generic Dual-Port Synchronous RAM                           ////
+////                                                              ////
+////  This file is part of memory library available from          ////
+////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
+////                                                              ////
+////  Description                                                 ////
+////  This block is a wrapper with common dual-port               ////
+////  synchronous memory interface for different                  ////
+////  types of ASIC and FPGA RAMs. Beside universal memory        ////
+////  interface it also provides behavioral model of generic      ////
+////  dual-port synchronous RAM.                                  ////
+////  It also contains a fully synthesizeable model for FPGAs.    ////
+////  It should be used in all OPENCORES designs that want to be  ////
+////  portable accross different target technologies and          ////
+////  independent of target memory.                               ////
+////                                                              ////
+////  Supported ASIC RAMs are:                                    ////
+////  - Artisan Dual-Port Sync RAM                                ////
+////  - Avant! Two-Port Sync RAM (*)                              ////
+////  - Virage 2-port Sync RAM                                    ////
+////                                                              ////
+////  Supported FPGA RAMs are:                                    ////
+////  - Generic FPGA (VENDOR_FPGA)                                ////
+////    Tested RAMs: Altera, Xilinx                               ////
+////    Synthesis tools: LeonardoSpectrum, Synplicity             ////
+////  - Xilinx (VENDOR_XILINX)                                    ////
+////  - Altera (VENDOR_ALTERA)                                    ////
+////                                                              ////
+////  To Do:                                                      ////
+////   - fix Avant!                                               ////
+////   - add additional RAMs (VS etc)                             ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Richard Herveille, richard@asics.ws                   ////
+////      - Damjan Lampret, lampret@opencores.org                 ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3  2001/11/09 00:34:18  samg
+// minor changes: unified with all common rams
+//
+// Revision 1.2  2001/11/08 19:11:31  samg
+// added valid checks to behvioral model
+//
+// Revision 1.1.1.1  2001/09/14 09:57:10  rherveille
+// Major cleanup.
+// Files are now compliant to Altera & Xilinx memories.
+// Memories are now compatible, i.e. drop-in replacements.
+// Added synthesizeable generic FPGA description.
+// Created "generic_memories" cvs entry.
+//
+// Revision 1.1.1.2  2001/08/21 13:09:27  damjan
+// *** empty log message ***
+//
+// Revision 1.1  2001/08/20 18:23:20  damjan
+// Initial revision
+//
+// Revision 1.1  2001/08/09 13:39:33  lampret
+// Major clean-up.
+//
+// Revision 1.2  2001/07/30 05:38:02  lampret
+// Adding empty directories required by HDL coding guidelines
+//
+//
+
+//`include "timescale.v"
+
+`define VENDOR_FPGA
+//`define VENDOR_XILINX
+//`define VENDOR_ALTERA
+
+module generic_dpram(
+	// Generic synchronous dual-port RAM interface
+	rclk, rrst, rce, oe, raddr, do,
+	wclk, wrst, wce, we, waddr, di
+);
+
+	//
+	// Default address and data buses width
+	//
+	parameter aw = 5;  // number of bits in address-bus
+	parameter dw = 16; // number of bits in data-bus
+
+	//
+	// Generic synchronous double-port RAM interface
+	//
+	// read port
+	input           rclk;  // read clock, rising edge trigger
+	input           rrst;  // read port reset, active high
+	input           rce;   // read port chip enable, active high
+	input           oe;	   // output enable, active high
+	input  [aw-1:0] raddr; // read address
+	output [dw-1:0] do;    // data output
+
+	// write port
+	input          wclk;  // write clock, rising edge trigger
+	input          wrst;  // write port reset, active high
+	input          wce;   // write port chip enable, active high
+	input          we;    // write enable, active high
+	input [aw-1:0] waddr; // write address
+	input [dw-1:0] di;    // data input
+
+	//
+	// Module body
+	//
+
+`ifdef VENDOR_FPGA
+	//
+	// Instantiation synthesizeable FPGA memory
+	//
+	// This code has been tested using LeonardoSpectrum and Synplicity.
+	// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
+	//
+	reg [dw-1:0] mem [(1<<aw) -1:0]; //pragma attribute mem block_ram false
+	reg [aw-1:0] ra;                 // register read address
+
+	// read operation
+	always @(posedge rclk)
+	  if (rce)
+	    ra <= raddr;
+
+	assign do = mem[ra];
+
+	// write operation
+	always@(posedge wclk)
+		if (we && wce)
+			mem[waddr] <= di;
+
+`else
+
+`ifdef VENDOR_XILINX
+	//
+	// Instantiation of FPGA memory:
+	//
+	// Virtex/Spartan2 BlockRAMs
+	//
+	xilinx_ram_dp xilinx_ram(
+		// read port
+		.CLKA(rclk),
+		.RSTA(rrst),
+		.ENA(rce),
+		.ADDRA(raddr),
+		.DIA( {dw{1'b0}} ),
+		.WEA(1'b0),
+		.DOA(do),
+
+		// write port
+		.CLKB(wclk),
+		.RSTB(wrst),
+		.ENB(wce),
+		.ADDRB(waddr),
+		.DIB(di),
+		.WEB(we),
+		.DOB()
+	);
+
+	defparam
+		xilinx_ram.dwidth = dw,
+		xilinx_ram.awidth = aw;
+
+`else
+
+`ifdef VENDOR_ALTERA
+	//
+	// Instantiation of FPGA memory:
+	//
+	// Altera FLEX/APEX EABs
+	//
+	altera_ram_dp altera_ram(
+		// read port
+		.rdclock(rclk),
+		.rdclocken(rce),
+		.rdaddress(raddr),
+		.q(do),
+
+		// write port
+		.wrclock(wclk),
+		.wrclocken(wce),
+		.wren(we),
+		.wraddress(waddr),
+		.data(di)
+	);
+
+	defparam
+		altera_ram.dwidth = dw,
+		altera_ram.awidth = aw;
+
+`else
+
+`ifdef VENDOR_ARTISAN
+
+	//
+	// Instantiation of ASIC memory:
+	//
+	// Artisan Synchronous Double-Port RAM (ra2sh)
+	//
+	art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
+		// read port
+		.qa(do),
+		.clka(rclk),
+		.cena(~rce),
+		.wena(1'b1),
+		.aa(raddr),
+		.da( {dw{1'b0}} ),
+		.oena(~oe),
+
+		// write port
+		.qb(),
+		.clkb(wclk),
+		.cenb(~wce),
+		.wenb(~we),
+		.ab(waddr),
+		.db(di),
+		.oenb(1'b1)
+	);
+
+`else
+
+`ifdef VENDOR_AVANT
+
+	//
+	// Instantiation of ASIC memory:
+	//
+	// Avant! Asynchronous Two-Port RAM
+	//
+	avant_atp avant_atp(
+		.web(~we),
+		.reb(),
+		.oeb(~oe),
+		.rcsb(),
+		.wcsb(),
+		.ra(raddr),
+		.wa(waddr),
+		.di(di),
+		.do(do)
+	);
+
+`else
+
+`ifdef VENDOR_VIRAGE
+
+	//
+	// Instantiation of ASIC memory:
+	//
+	// Virage Synchronous 2-port R/W RAM
+	//
+	virage_stp virage_stp(
+		// read port
+		.CLKA(rclk),
+		.MEA(rce_a),
+		.ADRA(raddr),
+		.DA( {dw{1'b0}} ),
+		.WEA(1'b0),
+		.OEA(oe),
+		.QA(do),
+
+		// write port
+		.CLKB(wclk),
+		.MEB(wce),
+		.ADRB(waddr),
+		.DB(di),
+		.WEB(we),
+		.OEB(1'b1),
+		.QB()
+	);
+
+`else
+
+	//
+	// Generic dual-port synchronous RAM model
+	//
+
+	//
+	// Generic RAM's registers and wires
+	//
+	reg	[dw-1:0]	mem [(1<<aw)-1:0]; // RAM content
+	reg	[dw-1:0]	do_reg;            // RAM data output register
+
+	//
+	// Data output drivers
+	//
+	assign do = (oe & rce) ? do_reg : {dw{1'bz}};
+
+	// read operation
+	always @(posedge rclk)
+		if (rce)
+          		do_reg <= (we && (waddr==raddr)) ? {dw{1'b x}} : mem[raddr];
+
+	// write operation
+	always @(posedge wclk)
+		if (wce && we)
+			mem[waddr] <= di;
+
+
+	// Task prints range of memory
+	// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
+	task print_ram;
+	input [aw-1:0] start;
+	input [aw-1:0] finish;
+	integer rnum;
+  	begin
+    		for (rnum=start;rnum<=finish;rnum=rnum+1)
+      			$display("Addr %h = %h",rnum,mem[rnum]);
+  	end
+	endtask
+
+`endif // !VENDOR_VIRAGE
+`endif // !VENDOR_AVANT
+`endif // !VENDOR_ARTISAN
+`endif // !VENDOR_ALTERA
+`endif // !VENDOR_XILINX
+`endif // !VENDOR_FPGA
+
+endmodule
+
+//
+// Black-box modules
+//
+
+`ifdef VENDOR_ALTERA
+	module altera_ram_dp(
+		data,
+		wraddress,
+		rdaddress,
+		wren,
+		wrclock,
+		wrclocken,
+		rdclock,
+		rdclocken,
+		q) /* synthesis black_box */;
+
+		parameter awidth = 7;
+		parameter dwidth = 8;
+
+		input [dwidth -1:0] data;
+		input [awidth -1:0] wraddress;
+		input [awidth -1:0] rdaddress;
+		input               wren;
+		input               wrclock;
+		input               wrclocken;
+		input               rdclock;
+		input               rdclocken;
+		output [dwidth -1:0] q;
+
+		// synopsis translate_off
+		// exemplar translate_off
+
+		syn_dpram_rowr #(
+			"UNUSED",
+			dwidth,
+			awidth,
+			1 << awidth
+		)
+		altera_dpram_model (
+			// read port
+			.RdClock(rdclock),
+			.RdClken(rdclocken),
+			.RdAddress(rdaddress),
+			.RdEn(1'b1),
+			.Q(q),
+
+			// write port
+			.WrClock(wrclock),
+			.WrClken(wrclocken),
+			.WrAddress(wraddress),
+			.WrEn(wren),
+			.Data(data)
+		);
+
+		// exemplar translate_on
+		// synopsis translate_on
+
+	endmodule
+`endif // VENDOR_ALTERA
+
+`ifdef VENDOR_XILINX
+	module xilinx_ram_dp (
+		ADDRA,
+		CLKA,
+		ADDRB,
+		CLKB,
+		DIA,
+		WEA,
+		DIB,
+		WEB,
+		ENA,
+		ENB,
+		RSTA,
+		RSTB,
+		DOA,
+		DOB) /* synthesis black_box */ ;
+
+	parameter awidth = 7;
+	parameter dwidth = 8;
+
+	// port_a
+	input               CLKA;
+	input               RSTA;
+	input               ENA;
+	input [awidth-1:0]  ADDRA;
+	input [dwidth-1:0]  DIA;
+	input               WEA;
+	output [dwidth-1:0] DOA;
+
+	// port_b
+	input               CLKB;
+	input               RSTB;
+	input               ENB;
+	input [awidth-1:0]  ADDRB;
+	input [dwidth-1:0]  DIB;
+	input               WEB;
+	output [dwidth-1:0] DOB;
+
+	// insert simulation model
+
+
+	// synopsys translate_off
+	// exemplar translate_off
+
+	C_MEM_DP_BLOCK_V1_0 #(
+		awidth,
+		awidth,
+		1,
+		1,
+		"0",
+		1 << awidth,
+		1 << awidth,
+		1,
+		1,
+		1,
+		1,
+		1,
+		1,
+		1,
+		1,
+		1,
+		1,
+		1,
+		1,
+		1,
+		"",
+		16,
+		0,
+		0,
+		1,
+		1,
+		1,
+		1,
+		dwidth,
+		dwidth)
+	xilinx_dpram_model (
+		.ADDRA(ADDRA),
+		.CLKA(CLKA),
+		.ADDRB(ADDRB),
+		.CLKB(CLKB),
+		.DIA(DIA),
+		.WEA(WEA),
+		.DIB(DIB),
+		.WEB(WEB),
+		.ENA(ENA),
+		.ENB(ENB),
+		.RSTA(RSTA),
+		.RSTB(RSTB),
+		.DOA(DOA),
+		.DOB(DOB));
+
+		// exemplar translate_on
+		// synopsys translate_on
+
+	endmodule
+`endif // VENDOR_XILINX
diff --git a/BENCHMARK/sdc_controller/rtl/generic_fifo_dc_gray.v b/BENCHMARK/sdc_controller/rtl/generic_fifo_dc_gray.v
new file mode 100644
index 0000000..9797c54
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/generic_fifo_dc_gray.v
@@ -0,0 +1,324 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Universal FIFO Dual Clock, gray encoded                    ////
+////                                                             ////
+////                                                             ////
+////  Author: Rudolf Usselmann                                   ////
+////          rudi@asics.ws                                      ////
+////                                                             ////
+////                                                             ////
+////  D/L from: http://www.opencores.org/cores/generic_fifos/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
+////                         www.asics.ws                        ////
+////                         rudi@asics.ws                       ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+
+
+//  CVS Log
+//
+//  $Id: generic_fifo_dc_gray.v,v 1.2 2004-01-13 09:11:55 rudi Exp $
+//
+//  $Date: 2004-01-13 09:11:55 $
+//  $Revision: 1.2 $
+//  $Author: rudi $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: not supported by cvs2svn $
+//               Revision 1.1  2003/10/14 09:34:41  rudi
+//               Dual clock FIFO Gray Code encoded version.
+//
+//
+//
+//
+//
+
+
+//`include "timescale.v"
+
+/*
+
+Description
+===========
+
+I/Os
+----
+rd_clk	Read Port Clock
+wr_clk	Write Port Clock
+rst	low active, either sync. or async. master reset (see below how to select)
+clr	synchronous clear (just like reset but always synchronous), high active
+re	read enable, synchronous, high active
+we	read enable, synchronous, high active
+din	Data Input
+dout	Data Output
+
+full	Indicates the FIFO is full (driven at the rising edge of wr_clk)
+empty	Indicates the FIFO is empty (driven at the rising edge of rd_clk)
+
+wr_level	indicates the FIFO level:
+		2'b00	0-25%	 full
+		2'b01	25-50%	 full
+		2'b10	50-75%	 full
+		2'b11	%75-100% full
+
+rd_level	indicates the FIFO level:
+		2'b00	0-25%	 empty
+		2'b01	25-50%	 empty
+		2'b10	50-75%	 empty
+		2'b11	%75-100% empty
+
+Status Timing
+-------------
+All status outputs are registered. They are asserted immediately
+as the full/empty condition occurs, however, there is a 2 cycle
+delay before they are de-asserted once the condition is not true
+anymore.
+
+Parameters
+----------
+The FIFO takes 2 parameters:
+dw	Data bus width
+aw	Address bus width (Determines the FIFO size by evaluating 2^aw)
+
+Synthesis Results
+-----------------
+In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 97 LUTs and runs
+at about 113 MHz (IO insertion disabled). 
+
+Misc
+----
+This design assumes you will do appropriate status checking externally.
+
+IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
+empty will place the FIFO in an undefined state.
+
+*/
+
+
+module generic_fifo_dc_gray(	rd_clk, wr_clk, rst, clr, din, we,
+		dout, re, full, empty, wr_level, rd_level );
+
+parameter dw=16;
+parameter aw=8;
+
+input			rd_clk, wr_clk, rst, clr;
+input	[dw-1:0]	din;
+input			we;
+output	[dw-1:0]	dout;
+input			re;
+output			full; 
+output			empty;
+output	[1:0]		wr_level;
+output	[1:0]		rd_level;
+
+////////////////////////////////////////////////////////////////////
+//
+// Local Wires
+//
+
+reg	[aw:0]		wp_bin, wp_gray;
+reg	[aw:0]		rp_bin, rp_gray;
+reg	[aw:0]		wp_s, rp_s;
+reg			full, empty;
+
+wire	[aw:0]		wp_bin_next, wp_gray_next;
+wire	[aw:0]		rp_bin_next, rp_gray_next;
+
+wire	[aw:0]		wp_bin_x, rp_bin_x;
+reg	[aw-1:0]	d1, d2;
+
+reg			rd_rst, wr_rst;
+reg			rd_rst_r, wr_rst_r;
+reg			rd_clr, wr_clr;
+reg			rd_clr_r, wr_clr_r;
+
+////////////////////////////////////////////////////////////////////
+//
+// Reset Logic
+//
+
+always @(posedge rd_clk or negedge rst)
+	if(!rst)	rd_rst <= 1'b0;
+	else
+	if(rd_rst_r)	rd_rst <= 1'b1;		// Release Reset
+
+always @(posedge rd_clk or negedge rst)
+	if(!rst)	rd_rst_r <= 1'b0;
+	else		rd_rst_r <= 1'b1;
+
+always @(posedge wr_clk or negedge rst)
+	if(!rst)	wr_rst <= 1'b0;
+	else
+	if(wr_rst_r)	wr_rst <= 1'b1;		// Release Reset
+
+always @(posedge wr_clk or negedge rst)
+	if(!rst)	wr_rst_r <= 1'b0;
+	else		wr_rst_r <= 1'b1;
+
+always @(posedge rd_clk or posedge clr)
+	if(clr)		rd_clr <= 1'b1;
+	else
+	if(!rd_clr_r)	rd_clr <= 1'b0;		// Release Clear
+
+always @(posedge rd_clk or posedge clr)
+	if(clr)		rd_clr_r <= 1'b1;
+	else		rd_clr_r <= 1'b0;
+
+always @(posedge wr_clk or posedge clr)
+	if(clr)		wr_clr <= 1'b1;
+	else
+	if(!wr_clr_r)	wr_clr <= 1'b0;		// Release Clear
+
+always @(posedge wr_clk or posedge clr)
+	if(clr)		wr_clr_r <= 1'b1;
+	else		wr_clr_r <= 1'b0;
+
+////////////////////////////////////////////////////////////////////
+//
+// Memory Block
+//
+
+generic_dpram  #(aw,dw) u0(
+	.rclk(		rd_clk		),
+	.rrst(		!rd_rst		),
+	.rce(		1'b1		),
+	.oe(		1'b1		),
+	.raddr(		rp_bin[aw-1:0]	),
+	.do(		dout		),
+	.wclk(		wr_clk		),
+	.wrst(		!wr_rst		),
+	.wce(		1'b1		),
+	.we(		we		),
+	.waddr(		wp_bin[aw-1:0]	),
+	.di(		din		)
+	);
+
+////////////////////////////////////////////////////////////////////
+//
+// Read/Write Pointers Logic
+//
+
+always @(posedge wr_clk)
+	if(!wr_rst)	wp_bin <= {aw+1{1'b0}};
+	else
+	if(wr_clr)	wp_bin <= {aw+1{1'b0}};
+	else
+	if(we)		wp_bin <= wp_bin_next;
+
+always @(posedge wr_clk)
+	if(!wr_rst)	wp_gray <= {aw+1{1'b0}};
+	else
+	if(wr_clr)	wp_gray <= {aw+1{1'b0}};
+	else
+	if(we)		wp_gray <= wp_gray_next;
+
+assign wp_bin_next  = wp_bin + {{aw{1'b0}},1'b1};
+assign wp_gray_next = wp_bin_next ^ {1'b0, wp_bin_next[aw:1]};
+
+always @(posedge rd_clk)
+	if(!rd_rst)	rp_bin <= {aw+1{1'b0}};
+	else
+	if(rd_clr)	rp_bin <= {aw+1{1'b0}};
+	else
+	if(re)		rp_bin <= rp_bin_next;
+
+always @(posedge rd_clk)
+	if(!rd_rst)	rp_gray <= {aw+1{1'b0}};
+	else
+	if(rd_clr)	rp_gray <= {aw+1{1'b0}};
+	else
+	if(re)		rp_gray <= rp_gray_next;
+
+assign rp_bin_next  = rp_bin + {{aw{1'b0}},1'b1};
+assign rp_gray_next = rp_bin_next ^ {1'b0, rp_bin_next[aw:1]};
+
+////////////////////////////////////////////////////////////////////
+//
+// Synchronization Logic
+//
+
+// write pointer
+always @(posedge rd_clk)	wp_s <= wp_gray;
+
+// read pointer
+always @(posedge wr_clk)	rp_s <= rp_gray;
+
+////////////////////////////////////////////////////////////////////
+//
+// Registered Full & Empty Flags
+//
+
+assign wp_bin_x = wp_s ^ {1'b0, wp_bin_x[aw:1]};	// convert gray to binary
+assign rp_bin_x = rp_s ^ {1'b0, rp_bin_x[aw:1]};	// convert gray to binary
+
+always @(posedge rd_clk)
+        empty <= (wp_s == rp_gray) | (re & (wp_s == rp_gray_next));
+
+always @(posedge wr_clk)
+        full <= ((wp_bin[aw-1:0] == rp_bin_x[aw-1:0]) & (wp_bin[aw] != rp_bin_x[aw])) |
+        (we & (wp_bin_next[aw-1:0] == rp_bin_x[aw-1:0]) & (wp_bin_next[aw] != rp_bin_x[aw]));
+
+////////////////////////////////////////////////////////////////////
+//
+// Registered Level Indicators
+//
+reg	[1:0]		wr_level;
+reg	[1:0]		rd_level;
+reg	[aw-1:0]	wp_bin_xr, rp_bin_xr;
+reg			full_rc;
+reg			full_wc;
+
+always @(posedge wr_clk)	full_wc <= full;
+always @(posedge wr_clk)	rp_bin_xr <=  ~rp_bin_x[aw-1:0] + {{aw-1{1'b0}}, 1'b1};
+always @(posedge wr_clk)	d1 <= wp_bin[aw-1:0] + rp_bin_xr[aw-1:0];
+
+always @(posedge wr_clk)	wr_level <= {d1[aw-1] | full | full_wc, d1[aw-2] | full | full_wc};
+
+always @(posedge rd_clk)	wp_bin_xr <=  ~wp_bin_x[aw-1:0];
+always @(posedge rd_clk)	d2 <= rp_bin[aw-1:0] + wp_bin_xr[aw-1:0];
+
+always @(posedge rd_clk)	full_rc <= full;
+always @(posedge rd_clk)	rd_level <= full_rc ? 2'h0 : {d2[aw-1] | empty, d2[aw-2] | empty};
+
+////////////////////////////////////////////////////////////////////
+//
+// Sanity Check
+//
+
+// synopsys translate_off
+//always @(posedge wr_clk)
+//	if(we && full)
+//		$display("%m WARNING: Writing while fifo is FULL (%t)",$time);
+
+//always @(posedge rd_clk)
+//	if(re && empty)
+//		$display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
+// synopsys translate_on
+
+endmodule
+
diff --git a/BENCHMARK/sdc_controller/rtl/monostable_domain_cross.v b/BENCHMARK/sdc_controller/rtl/monostable_domain_cross.v
new file mode 100644
index 0000000..c775fb8
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/monostable_domain_cross.v
@@ -0,0 +1,78 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// monostable_domain_cross.v                                    ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Clock synchronisation beetween two clock domains.            ////
+//// Assumption is that input signal duration is always           //// 
+//// one clk_a clock period. If that is true output signal        ////
+//// duration is always one clk_b clock period.                   ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+module monostable_domain_cross(
+    input rst,
+    input clk_a,
+    input in, 
+    input clk_b,
+    output out
+);
+
+// this changes level when the in is seen in clk_a
+reg toggle_clk_a;
+always @(posedge clk_a or posedge rst)
+begin
+    if (rst)
+        toggle_clk_a <= 0;
+    else
+        toggle_clk_a <= toggle_clk_a ^ in;
+end
+
+// which can then be sync-ed to clk_b
+reg [2:0] sync_clk_b;
+always @(posedge clk_b or posedge rst)
+begin
+    if (rst)
+        sync_clk_b <= 0;
+    else
+        sync_clk_b <= {sync_clk_b[1:0], toggle_clk_a};
+end
+
+// and recreate the flag in clk_b
+assign out = (sync_clk_b[2] ^ sync_clk_b[1]);
+
+endmodule 
diff --git a/BENCHMARK/sdc_controller/rtl/sd_clock_divider.v b/BENCHMARK/sdc_controller/rtl/sd_clock_divider.v
new file mode 100644
index 0000000..a458992
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_clock_divider.v
@@ -0,0 +1,79 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// sd_clock_divider.v                                           ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Control of sd card clock rate                                ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// Based on original work by                                    ////
+////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
+////                                                              ////
+////     Copyright (C) 2009 Authors                               ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+module sd_clock_divider (
+           input CLK,
+           input [7:0] DIVIDER,
+           input RST,
+           output SD_CLK
+       );
+
+reg [7:0] ClockDiv;
+reg SD_CLK_O;
+
+//assign SD_CLK = DIVIDER[7] ? CLK : SD_CLK_O;
+assign SD_CLK = SD_CLK_O;
+
+always @(posedge CLK or posedge RST)
+begin
+    if (RST) begin
+        ClockDiv <= 8'b0000_0000;
+        SD_CLK_O <= 0;
+    end
+    else if (ClockDiv == DIVIDER) begin
+        ClockDiv <= 0;
+        SD_CLK_O <= ~SD_CLK_O;
+    end else begin
+        ClockDiv <= ClockDiv + 8'h1;
+        SD_CLK_O <= SD_CLK_O;
+    end
+end
+
+endmodule
+
+
diff --git a/BENCHMARK/sdc_controller/rtl/sd_cmd_master.v b/BENCHMARK/sdc_controller/rtl/sd_cmd_master.v
new file mode 100644
index 0000000..cc70787
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_cmd_master.v
@@ -0,0 +1,245 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// sd_cmd_master.v                                              ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// State machine resposible for controlling command transfers   ////
+//// on 1-bit sd card command interface                           ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// Based on original work by                                    ////
+////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
+////                                                              ////
+////     Copyright (C) 2009 Authors                               ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+`include "sd_defines.h"
+
+module sd_cmd_master(
+           input sd_clk,
+           input rst,
+           input start_i,
+           input int_status_rst_i,
+           output [1:0] setting_o,
+           output reg start_xfr_o,
+           output reg go_idle_o,
+           output reg  [39:0] cmd_o,
+           input [119:0] response_i,
+           input crc_ok_i,
+           input index_ok_i,
+           input finish_i,
+           input busy_i, //direct signal from data sd data input (data[0])
+           //input card_detect,
+           input [31:0] argument_i,
+           input [`CMD_REG_SIZE-1:0] command_i,
+           input [15:0] timeout_i,
+           output [`INT_CMD_SIZE-1:0] int_status_o,
+           output reg [31:0] response_0_o,
+           output reg [31:0] response_1_o,
+           output reg [31:0] response_2_o,
+           output reg [31:0] response_3_o
+       );
+
+//-----------Types--------------------------------------------------------
+reg [15:0] timeout_reg;
+reg crc_check;
+reg index_check;
+reg busy_check;
+reg expect_response;
+reg long_response;
+reg [`INT_CMD_SIZE-1:0] int_status_reg;
+//reg card_present;
+//reg [3:0]debounce;
+reg [15:0] watchdog;
+parameter SIZE = 2;
+reg [SIZE-1:0] state;
+reg [SIZE-1:0] next_state;
+parameter IDLE       = 2'b00;
+parameter EXECUTE    = 2'b01;
+parameter BUSY_CHECK = 2'b10;
+
+assign setting_o[1:0] = {long_response, expect_response};
+assign int_status_o = state == IDLE ? int_status_reg : 5'h0;
+
+//---------------Input ports---------------
+
+// always @ (posedge sd_clk or posedge rst   )
+// begin
+//     if (rst) begin
+//         debounce<=0;
+//         card_present<=0;
+//     end
+//     else begin
+//         if (!card_detect) begin//Card present
+//             if (debounce!=4'b1111)
+//                 debounce<=debounce+1'b1;
+//         end
+//         else
+//             debounce<=0;
+// 
+//         if (debounce==4'b1111)
+//             card_present<=1'b1;
+//         else
+//             card_present<=1'b0;
+//     end
+// end
+
+always @(state or start_i or finish_i or go_idle_o or busy_check or busy_i)
+begin: FSM_COMBO
+    case(state)
+        IDLE: begin
+            if (start_i)
+                next_state <= EXECUTE;
+            else
+                next_state <= IDLE;
+        end
+        EXECUTE: begin
+            if ((finish_i && !busy_check) || go_idle_o)
+                next_state <= IDLE;
+            else if (finish_i && busy_check)
+                next_state <= BUSY_CHECK;
+            else
+                next_state <= EXECUTE;
+        end
+        BUSY_CHECK: begin
+            if (!busy_i)
+                next_state <= IDLE;
+            else
+                next_state <= BUSY_CHECK;
+        end
+        default: next_state <= IDLE;
+    endcase
+end
+
+always @(posedge sd_clk or posedge rst)
+begin: FSM_SEQ
+    if (rst) begin
+        state <= IDLE;
+    end
+    else begin
+        state <= next_state;
+    end
+end
+
+always @(posedge sd_clk or posedge rst)
+begin
+    if (rst) begin
+        crc_check <= 0;
+        response_0_o <= 0;
+        response_1_o <= 0;
+        response_2_o <= 0;
+        response_3_o <= 0;
+        int_status_reg <= 0;
+        expect_response <= 0;
+        long_response <= 0;
+        cmd_o <= 0;
+        start_xfr_o <= 0;
+        index_check <= 0;
+        busy_check <= 0;
+        watchdog <= 0;
+        timeout_reg <= 0;
+        go_idle_o <= 0;
+    end
+    else begin
+        case(state)
+            IDLE: begin
+                go_idle_o <= 0;
+                index_check <= command_i[`CMD_IDX_CHECK];
+                crc_check <= command_i[`CMD_CRC_CHECK];
+                busy_check <= command_i[`CMD_BUSY_CHECK];
+                if (command_i[`CMD_RESPONSE_CHECK]  == 2'b10 || command_i[`CMD_RESPONSE_CHECK] == 2'b11) begin
+                    expect_response <=  1;
+                    long_response <= 1;
+                end
+                else if (command_i[`CMD_RESPONSE_CHECK] == 2'b01) begin
+                    expect_response <= 1;
+                    long_response <= 0;
+                end
+                else begin
+                    expect_response <= 0;
+                    long_response <= 0;
+                end
+                cmd_o[39:38] <= 2'b01;
+                cmd_o[37:32] <= command_i[`CMD_INDEX];  //CMD_INDEX
+                cmd_o[31:0] <= argument_i; //CMD_Argument
+                timeout_reg <= timeout_i;
+                watchdog <= 0;
+                if (start_i) begin
+                    start_xfr_o <= 1;
+                    int_status_reg <= 0;
+                end
+            end
+            EXECUTE: begin
+                start_xfr_o <= 0;
+                watchdog <= watchdog + 16'd1;
+                if (watchdog > timeout_reg) begin
+                    int_status_reg[`INT_CMD_CTE] <= 1;
+                    int_status_reg[`INT_CMD_EI] <= 1;
+                    go_idle_o <= 1;
+                end
+                //Incoming New Status
+                else begin //if ( req_in_int == 1) begin
+                    if (finish_i) begin //Data avaible
+                        if (crc_check & !crc_ok_i) begin
+                            int_status_reg[`INT_CMD_CCRCE] <= 1;
+                            int_status_reg[`INT_CMD_EI] <= 1;
+                        end
+                        if (index_check & !index_ok_i) begin
+                            int_status_reg[`INT_CMD_CIE] <= 1;
+                            int_status_reg[`INT_CMD_EI] <= 1;
+                        end
+                        int_status_reg[`INT_CMD_CC] <= 1;
+                        if (expect_response != 0) begin
+                            response_0_o <= response_i[119:88];
+                            response_1_o <= response_i[87:56];
+                            response_2_o <= response_i[55:24];
+                            response_3_o <= {response_i[23:0], 8'h00};
+                        end
+                        // end
+                    end ////Data avaible
+                end //Status change
+            end //EXECUTE state
+            BUSY_CHECK: begin
+                start_xfr_o <= 0;
+                go_idle_o <= 0;
+            end
+        endcase
+        if (int_status_rst_i)
+            int_status_reg <= 0;
+    end
+end
+
+endmodule
diff --git a/BENCHMARK/sdc_controller/rtl/sd_cmd_serial_host.v b/BENCHMARK/sdc_controller/rtl/sd_cmd_serial_host.v
new file mode 100644
index 0000000..9dcb7bf
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_cmd_serial_host.v
@@ -0,0 +1,336 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// sd_cmd_serial_host.v                                         ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Module resposible for sending and receiving commands         ////
+//// through 1-bit sd card command interface                      ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// Based on original work by                                    ////
+////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
+////                                                              ////
+////     Copyright (C) 2009 Authors                               ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+module sd_cmd_serial_host (
+           sd_clk,
+           rst,
+           setting_i,
+           cmd_i,
+           start_i,
+           response_o,
+           crc_ok_o,
+           index_ok_o,
+           finish_o,
+           cmd_dat_i,
+           cmd_out_o,
+           cmd_oe_o
+       );
+
+//---------------Input ports---------------
+input sd_clk;
+input rst;
+input [1:0] setting_i;
+input [39:0] cmd_i;
+input start_i;
+input cmd_dat_i;
+//---------------Output ports---------------
+output reg [119:0] response_o;
+output reg finish_o;
+output reg crc_ok_o;
+output reg index_ok_o;
+output reg cmd_oe_o;
+output reg cmd_out_o;
+
+//-------------Internal Constant-------------
+parameter INIT_DELAY = 4;
+parameter BITS_TO_SEND = 48;
+parameter CMD_SIZE = 40;
+parameter RESP_SIZE = 128;
+
+//---------------Internal variable-----------
+reg cmd_dat_reg;
+integer resp_len;
+reg with_response;
+reg [CMD_SIZE-1:0] cmd_buff;
+reg [RESP_SIZE-1:0] resp_buff;
+integer resp_idx;
+//CRC
+reg crc_rst;
+reg [6:0]crc_in;
+wire [6:0] crc_val;
+reg crc_enable;
+reg crc_bit;
+reg crc_ok;
+//-Internal Counterns
+integer counter;
+//-State Machine
+parameter STATE_SIZE = 10;
+parameter
+    INIT = 7'h00,
+    IDLE = 7'h01,
+    SETUP_CRC = 7'h02,
+    WRITE = 7'h04,
+    READ_WAIT = 7'h08,
+    READ = 7'h10,
+    FINISH_WR = 7'h20,
+    FINISH_WO = 7'h40;
+reg [STATE_SIZE-1:0] state;
+reg [STATE_SIZE-1:0] next_state;
+//Misc
+`define cmd_idx  (CMD_SIZE-1-counter) 
+
+//sd cmd input pad register
+always @(posedge sd_clk)
+    cmd_dat_reg <= cmd_dat_i;
+
+//------------------------------------------
+sd_crc_7 CRC_7(
+             crc_bit,
+             crc_enable,
+             sd_clk,
+             crc_rst,
+             crc_val);
+
+//------------------------------------------
+always @(state or counter or start_i or with_response or cmd_dat_reg or resp_len)
+begin: FSM_COMBO
+    case(state)
+        INIT: begin
+            if (counter >= INIT_DELAY) begin
+                next_state <= IDLE;
+            end
+            else begin
+                next_state <= INIT;
+            end
+        end
+        IDLE: begin
+            if (start_i) begin
+                next_state <= SETUP_CRC;
+            end
+            else begin
+                next_state <= IDLE;
+            end
+        end
+        SETUP_CRC:
+            next_state <= WRITE;
+        WRITE:
+            if (counter >= BITS_TO_SEND && with_response) begin
+                next_state <= READ_WAIT;
+            end
+            else if (counter >= BITS_TO_SEND) begin
+                next_state <= FINISH_WO;
+            end
+            else begin
+                next_state <= WRITE;
+            end
+        READ_WAIT:
+            if (!cmd_dat_reg) begin
+                next_state <= READ;
+            end
+            else begin
+                next_state <= READ_WAIT;
+            end
+        FINISH_WO:
+            next_state <= IDLE;
+        READ:
+            if (counter >= resp_len+8) begin
+                next_state <= FINISH_WR;
+            end
+            else begin
+                next_state <= READ;
+            end
+        FINISH_WR:
+            next_state <= IDLE;
+        default: 
+            next_state <= INIT;
+    endcase
+end
+
+always @(posedge sd_clk or posedge rst)
+begin: COMMAND_DECODER
+    if (rst) begin
+        resp_len <= 0;
+        with_response <= 0;
+        cmd_buff <= 0;
+    end
+    else begin
+        if (start_i == 1) begin
+            resp_len <= setting_i[1] ? 127 : 39;
+            with_response <= setting_i[0];
+            cmd_buff <= cmd_i;
+        end
+    end
+end
+
+//----------------Seq logic------------
+always @(posedge sd_clk or posedge rst)
+begin: FSM_SEQ
+    if (rst) begin
+        state <= INIT;
+    end
+    else begin
+        state <= next_state;
+    end
+end
+
+//-------------OUTPUT_LOGIC-------
+always @(posedge sd_clk or posedge rst)
+begin: FSM_OUT
+    if (rst) begin
+        crc_enable <= 0;
+        resp_idx <= 0;
+        cmd_oe_o <= 1;
+        cmd_out_o <= 1;
+        resp_buff <= 0;
+        finish_o <= 0;
+        crc_rst <= 1;
+        crc_bit <= 0;
+        crc_in <= 0;
+        response_o <= 0;
+        index_ok_o <= 0;
+        crc_ok_o <= 0;
+        crc_ok <= 0;
+        counter <= 0;
+    end
+    else begin
+        case(state)
+            INIT: begin
+                counter <= counter+1;
+                cmd_oe_o <= 1;
+                cmd_out_o <= 1;
+            end
+            IDLE: begin
+                cmd_oe_o <= 0;      //Put CMD to Z
+                counter <= 0;
+                crc_rst <= 1;
+                crc_enable <= 0;
+                response_o <= 0;
+                resp_idx <= 0;
+                crc_ok_o <= 0;
+                index_ok_o <= 0;
+                finish_o <= 0;
+            end
+            SETUP_CRC: begin
+                crc_rst <= 0;
+                crc_enable <= 1;
+                crc_bit <= cmd_buff[`cmd_idx];
+            end
+            WRITE: begin
+                if (counter < BITS_TO_SEND-8) begin  // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit
+                    cmd_oe_o <= 1;
+                    cmd_out_o <= cmd_buff[`cmd_idx];
+                    if (counter < BITS_TO_SEND-9) begin //1 step ahead
+                        crc_bit <= cmd_buff[`cmd_idx-1];
+                    end else begin
+                        crc_enable <= 0;
+                    end
+                end
+                else if (counter < BITS_TO_SEND-1) begin
+                    cmd_oe_o <= 1;
+                    crc_enable <= 0;
+                    cmd_out_o <= crc_val[BITS_TO_SEND-counter-2];
+                end
+                else if (counter == BITS_TO_SEND-1) begin
+                    cmd_oe_o <= 1;
+                    cmd_out_o <= 1'b1;
+                end
+                else begin
+                    cmd_oe_o <= 0;
+                    cmd_out_o <= 1'b1;
+                end
+                counter <= counter+1;
+            end
+            READ_WAIT: begin
+                crc_enable <= 0;
+                crc_rst <= 1;
+                counter <= 1;
+                cmd_oe_o <= 0;
+                resp_buff[RESP_SIZE-1] <= cmd_dat_reg;
+            end
+            FINISH_WO: begin
+                finish_o <= 1;
+                crc_enable <= 0;
+                crc_rst <= 1;
+                counter <= 0;
+                cmd_oe_o <= 0;
+            end
+            READ: begin
+                crc_rst <= 0;
+                crc_enable <= (resp_len != RESP_SIZE-1 || counter > 7);
+                cmd_oe_o <= 0;
+                if (counter <= resp_len) begin
+                    if (counter < 8) //1+1+6 (S,T,Index)
+                        resp_buff[RESP_SIZE-1-counter] <= cmd_dat_reg;
+                    else begin
+                        resp_idx <= resp_idx + 1;
+                        resp_buff[RESP_SIZE-9-resp_idx] <= cmd_dat_reg;
+                    end
+                    crc_bit <= cmd_dat_reg;
+                end
+                else if (counter-resp_len <= 7) begin
+                    crc_in[(resp_len+7)-(counter)] <= cmd_dat_reg;
+                    crc_enable <= 0;
+                end
+                else begin
+                    crc_enable <= 0;
+                    if (crc_in == crc_val) crc_ok <= 1;
+                    else crc_ok <= 0;
+                end
+                counter <= counter + 1;
+            end
+            FINISH_WR: begin
+                if (cmd_buff[37:32] == resp_buff[125:120])
+                    index_ok_o <= 1;
+                else
+                    index_ok_o <= 0;
+                crc_ok_o <= crc_ok;
+                finish_o <= 1;
+                crc_enable <= 0;
+                crc_rst <= 1;
+                counter <= 0;
+                cmd_oe_o <= 0;
+                response_o <= resp_buff[119:0];
+            end
+        endcase
+    end
+end
+
+endmodule
+
+
diff --git a/BENCHMARK/sdc_controller/rtl/sd_controller_wb.v b/BENCHMARK/sdc_controller/rtl/sd_controller_wb.v
new file mode 100644
index 0000000..e92ed51
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_controller_wb.v
@@ -0,0 +1,195 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// sd_controller_wb.v                                           ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Wishbone interface responsible for comunication with core    ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// Based on original work by                                    ////
+////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
+////                                                              ////
+////     Copyright (C) 2009 Authors                               ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+`include "sd_defines.h"
+
+module sd_controller_wb(
+           // WISHBONE slave
+           wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
+           wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
+           cmd_start,
+           data_int_rst,
+           cmd_int_rst,
+           argument_reg,
+           command_reg,
+           response_0_reg,
+           response_1_reg,
+           response_2_reg,
+           response_3_reg,
+           software_reset_reg,
+           timeout_reg,
+           block_size_reg,
+           controll_setting_reg,
+           cmd_int_status_reg,
+           cmd_int_enable_reg,
+           clock_divider_reg,
+           block_count_reg,
+           dma_addr_reg,
+           data_int_status_reg,
+           data_int_enable_reg
+       );
+
+// WISHBONE common
+input wb_clk_i;     // WISHBONE clock
+input wb_rst_i;     // WISHBONE reset
+input [31:0] wb_dat_i;     // WISHBONE data input
+output reg [31:0] wb_dat_o;     // WISHBONE data output
+// WISHBONE error output
+
+// WISHBONE slave
+input [7:0] wb_adr_i;     // WISHBONE address input
+input [3:0] wb_sel_i;     // WISHBONE byte select input
+input wb_we_i;      // WISHBONE write enable input
+input wb_cyc_i;     // WISHBONE cycle input
+input wb_stb_i;     // WISHBONE strobe input
+output reg wb_ack_o;     // WISHBONE acknowledge output
+output reg cmd_start;
+//Buss accessible registers
+output reg [31:0] argument_reg;
+output reg [`CMD_REG_SIZE-1:0] command_reg;
+input wire [31:0] response_0_reg;
+input wire [31:0] response_1_reg;
+input wire [31:0] response_2_reg;
+input wire [31:0] response_3_reg;
+output reg [0:0] software_reset_reg;
+output reg [15:0] timeout_reg;
+output reg [`BLKSIZE_W-1:0] block_size_reg;
+output reg [15:0] controll_setting_reg;
+input wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
+output reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
+output reg [7:0] clock_divider_reg;
+input  wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
+output reg [`INT_DATA_SIZE-1:0] data_int_enable_reg;
+//Register Controll
+output reg data_int_rst;
+output reg cmd_int_rst;
+output reg [`BLKCNT_W-1:0]block_count_reg;
+output reg [31:0] dma_addr_reg;
+
+parameter voltage_controll_reg  = `SUPPLY_VOLTAGE_mV;
+parameter capabilies_reg = 16'b0000_0000_0000_0000;
+
+always @(posedge wb_clk_i or posedge wb_rst_i)
+begin
+    if (wb_rst_i)begin
+        argument_reg <= 0;
+        command_reg <= 0;
+        software_reset_reg <= 0;
+        timeout_reg <= 0;
+        block_size_reg <= `RESET_BLOCK_SIZE;
+        controll_setting_reg <= 0;
+        cmd_int_enable_reg <= 0;
+        clock_divider_reg <= `RESET_CLK_DIV;
+        wb_ack_o <= 0;
+        cmd_start <= 0;
+        data_int_rst <= 0;
+        data_int_enable_reg <= 0;
+        cmd_int_rst <= 0;
+        block_count_reg <= 0;
+        dma_addr_reg <= 0;
+    end
+    else
+    begin
+        cmd_start <= 1'b0;
+        data_int_rst <= 0;
+        cmd_int_rst <= 0;
+        if ((wb_stb_i & wb_cyc_i) || wb_ack_o)begin
+            if (wb_we_i) begin
+                case (wb_adr_i)
+                    `argument: begin
+                        argument_reg <= wb_dat_i;
+                        cmd_start <= 1'b1;
+                    end
+                    `command: command_reg <= wb_dat_i[`CMD_REG_SIZE-1:0];
+                    `reset: software_reset_reg <= wb_dat_i[0];
+                    `timeout: timeout_reg  <=  wb_dat_i[15:0];
+                    `blksize: block_size_reg <= wb_dat_i[`BLKSIZE_W-1:0];
+                    `controller: controll_setting_reg <= wb_dat_i[15:0];
+                    `cmd_iser: cmd_int_enable_reg <= wb_dat_i[4:0];
+                    `cmd_isr: cmd_int_rst <= 1;
+                    `clock_d: clock_divider_reg <= wb_dat_i[7:0];
+                    `data_isr: data_int_rst <= 1;
+                    `data_iser: data_int_enable_reg <= wb_dat_i[`INT_DATA_SIZE-1:0];
+                    `dst_src_addr: dma_addr_reg <= wb_dat_i;
+                    `blkcnt: block_count_reg <= wb_dat_i[`BLKCNT_W-1:0];
+                endcase
+            end
+            wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
+        end
+    end
+end
+
+always @(posedge wb_clk_i or posedge wb_rst_i)begin
+    if (wb_rst_i == 1)
+        wb_dat_o <= 0;
+    else
+        if (wb_stb_i & wb_cyc_i) begin //CS
+            case (wb_adr_i)
+                `argument: wb_dat_o <= argument_reg;
+                `command: wb_dat_o <= command_reg;
+                `resp0: wb_dat_o <= response_0_reg;
+                `resp1: wb_dat_o <= response_1_reg;
+                `resp2: wb_dat_o <= response_2_reg;
+                `resp3: wb_dat_o <= response_3_reg;
+                `controller: wb_dat_o <= controll_setting_reg;
+                `blksize: wb_dat_o <= block_size_reg;
+                `voltage: wb_dat_o <= voltage_controll_reg;
+                `reset: wb_dat_o <= software_reset_reg;
+                `timeout: wb_dat_o <= timeout_reg;
+                `cmd_isr: wb_dat_o <= cmd_int_status_reg;
+                `cmd_iser: wb_dat_o <= cmd_int_enable_reg;
+                `clock_d: wb_dat_o <= clock_divider_reg;
+                `capa: wb_dat_o <= capabilies_reg;
+                `data_isr: wb_dat_o <= data_int_status_reg;
+                `blkcnt: wb_dat_o <= block_count_reg;
+                `data_iser: wb_dat_o <= data_int_enable_reg;
+                `dst_src_addr: wb_dat_o <= dma_addr_reg;
+            endcase
+        end
+end
+
+endmodule
diff --git a/BENCHMARK/sdc_controller/rtl/sd_crc_16.v b/BENCHMARK/sdc_controller/rtl/sd_crc_16.v
new file mode 100644
index 0000000..d398aa7
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_crc_16.v
@@ -0,0 +1,43 @@
+// ==========================================================================
+// CRC Generation Unit - Linear Feedback Shift Register implementation
+// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
+// ==========================================================================
+module sd_crc_16(BITVAL, ENABLE, BITSTRB, CLEAR, CRC);
+   input        BITVAL;                            // Next input bit
+   input        ENABLE;                            // Enable calculation
+   input        BITSTRB;                           // Current bit valid (Clock)
+   input        CLEAR;                             // Init CRC value
+   output [15:0] CRC;                               // Current output CRC value
+
+   reg    [15:0] CRC;                               // We need output registers
+   wire         inv;
+   
+   assign inv = BITVAL ^ CRC[15];                   // XOR required?
+   
+   always @(posedge BITSTRB or posedge CLEAR) begin
+      if (CLEAR) begin
+         CRC <= 0;                                  // Init before calculation
+         end
+      else begin
+         if (ENABLE == 1) begin
+             CRC[15] <= CRC[14];
+             CRC[14] <= CRC[13];
+             CRC[13] <= CRC[12];
+             CRC[12] <= CRC[11] ^ inv;
+             CRC[11] <= CRC[10];
+             CRC[10] <= CRC[9];
+             CRC[9] <= CRC[8];
+             CRC[8] <= CRC[7];
+             CRC[7] <= CRC[6];
+             CRC[6] <= CRC[5];
+             CRC[5] <= CRC[4] ^ inv;
+             CRC[4] <= CRC[3];
+             CRC[3] <= CRC[2];
+             CRC[2] <= CRC[1];
+             CRC[1] <= CRC[0];
+             CRC[0] <= inv;
+             end
+         end
+      end
+   
+endmodule
\ No newline at end of file
diff --git a/BENCHMARK/sdc_controller/rtl/sd_crc_7.v b/BENCHMARK/sdc_controller/rtl/sd_crc_7.v
new file mode 100644
index 0000000..fee434e
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_crc_7.v
@@ -0,0 +1,34 @@
+// ==========================================================================
+// CRC Generation Unit - Linear Feedback Shift Register implementation
+// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
+// ==========================================================================
+module sd_crc_7(BITVAL, ENABLE, BITSTRB, CLEAR, CRC);
+   input        BITVAL;                            // Next input bit
+   input        ENABLE;                            // Enable calculation
+   input        BITSTRB;                           // Current bit valid (Clock)
+   input        CLEAR;                             // Init CRC value
+   output [6:0] CRC;                               // Current output CRC value
+
+   reg    [6:0] CRC;                               // We need output registers
+   wire         inv;
+   
+   assign inv = BITVAL ^ CRC[6];                   // XOR required?
+   
+   always @(posedge BITSTRB or posedge CLEAR) begin
+      if (CLEAR) begin
+         CRC <= 0;                                  // Init before calculation
+         end
+      else begin
+         if (ENABLE == 1) begin
+             CRC[6] <= CRC[5];
+             CRC[5] <= CRC[4];
+             CRC[4] <= CRC[3];
+             CRC[3] <= CRC[2] ^ inv;
+             CRC[2] <= CRC[1];
+             CRC[1] <= CRC[0];
+             CRC[0] <= inv;
+             end
+         end
+      end
+   
+endmodule
\ No newline at end of file
diff --git a/BENCHMARK/sdc_controller/rtl/sd_data_master.v b/BENCHMARK/sdc_controller/rtl/sd_data_master.v
new file mode 100644
index 0000000..56cfe9b
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_data_master.v
@@ -0,0 +1,209 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// sd_data_master.v                                             ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// State machine resposible for controlling data transfers      ////
+//// on 4-bit sd card data interface                              ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// Based on original work by                                    ////
+////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
+////                                                              ////
+////     Copyright (C) 2009 Authors                               ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+`include "sd_defines.h"
+
+module sd_data_master (
+           input sd_clk,
+           input rst,
+           input start_tx_i,
+           input start_rx_i,
+           //Output to SD-Host Reg
+           output reg d_write_o,
+           output reg d_read_o,
+           //To fifo filler
+           output reg start_tx_fifo_o,
+           output reg start_rx_fifo_o,
+           input tx_fifo_empty_i,
+           input tx_fifo_full_i,
+           input rx_fifo_full_i,
+           //SD-DATA_Host
+           input xfr_complete_i,
+           input crc_ok_i,
+           //status output
+           output reg [`INT_DATA_SIZE-1:0] int_status_o,
+           input int_status_rst_i
+       );
+
+reg tx_cycle;
+parameter SIZE = 3;
+reg [SIZE-1:0] state;
+reg [SIZE-1:0] next_state;
+parameter IDLE          = 3'b000;
+parameter START_TX_FIFO = 3'b001;
+parameter START_RX_FIFO = 3'b010;
+parameter DATA_TRANSFER = 3'b100;
+
+reg trans_done;
+
+always @(state or start_tx_i or start_rx_i or tx_fifo_full_i or xfr_complete_i or trans_done)
+begin: FSM_COMBO
+    case(state)
+        IDLE: begin
+            if (start_tx_i == 1) begin
+                next_state <= START_TX_FIFO;
+            end
+            else if (start_rx_i == 1) begin
+                next_state <= START_RX_FIFO;
+            end
+            else begin
+                next_state <= IDLE;
+            end
+        end
+        START_TX_FIFO: begin
+            if (tx_fifo_full_i == 1 && xfr_complete_i == 0)
+                next_state <= DATA_TRANSFER;
+            else
+                next_state <= START_TX_FIFO;
+        end
+        START_RX_FIFO: begin
+            if (xfr_complete_i == 0)
+                next_state <= DATA_TRANSFER;
+            else
+                next_state <= START_RX_FIFO;
+        end
+        DATA_TRANSFER: begin
+            if (trans_done)
+                next_state <= IDLE;
+            else
+                next_state <= DATA_TRANSFER;
+        end
+        default: next_state <= IDLE;
+    endcase
+end
+
+//----------------Seq logic------------
+always @(posedge sd_clk or posedge rst)
+begin: FSM_SEQ
+    if (rst) begin
+        state <= IDLE;
+    end
+    else begin
+        state <= next_state;
+    end
+end
+
+//Output logic-----------------
+always @(posedge sd_clk or posedge rst)
+begin
+    if (rst) begin
+        start_tx_fifo_o <= 0;
+        start_rx_fifo_o <= 0;
+        d_write_o <= 0;
+        d_read_o <= 0;
+        trans_done <= 0;
+        tx_cycle <= 0;
+        int_status_o <= 0;
+    end
+    else begin
+        case(state)
+            IDLE: begin
+                start_tx_fifo_o <= 0;
+                start_rx_fifo_o <= 0;
+                d_write_o <= 0;
+                d_read_o <= 0;
+                trans_done <= 0;
+                tx_cycle <= 0;
+            end
+            START_RX_FIFO: begin
+                start_rx_fifo_o <= 1;
+                start_tx_fifo_o <= 0;
+                tx_cycle <= 0;
+                d_read_o <= 1;
+            end
+            START_TX_FIFO:  begin
+                start_rx_fifo_o <= 0;
+                start_tx_fifo_o <= 1;
+                tx_cycle <= 1;
+                if (tx_fifo_full_i == 1)
+                    d_write_o <= 1;
+            end
+            DATA_TRANSFER: begin
+                d_read_o <= 0;
+                d_write_o <= 0;
+                if (tx_cycle) begin
+                    if (tx_fifo_empty_i) begin
+                        if (!trans_done)
+                            int_status_o[`INT_DATA_CFE] <= 1;
+                        trans_done <= 1;
+                        //stop sd_data_serial_host
+                        d_write_o <= 1;
+                        d_read_o <= 1;
+                    end
+                end
+                else begin
+                    if (rx_fifo_full_i) begin
+                        if (!trans_done)
+                            int_status_o[`INT_DATA_CFE] <= 1;
+                        trans_done <= 1;
+                        //stop sd_data_serial_host
+                        d_write_o <= 1;
+                        d_read_o <= 1;
+                    end
+                end
+                if (xfr_complete_i) begin //Transfer complete
+                    d_write_o <= 0;
+                    d_read_o <= 0;
+                    trans_done <= 1;
+                    if (!crc_ok_i)  begin //Wrong CRC and Data line free.
+                        if (!trans_done)
+                            int_status_o[`INT_DATA_CCRCE] <= 1;
+                    end
+                    else if (crc_ok_i) begin //Data Line free
+                        if (!trans_done)
+                            int_status_o[`INT_DATA_CC] <= 1;
+                    end
+                end
+            end
+        endcase
+        if (int_status_rst_i)
+            int_status_o<=0;
+    end
+end
+
+endmodule
diff --git a/BENCHMARK/sdc_controller/rtl/sd_data_serial_host.v b/BENCHMARK/sdc_controller/rtl/sd_data_serial_host.v
new file mode 100644
index 0000000..0b16e65
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_data_serial_host.v
@@ -0,0 +1,374 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// sd_data_serial_host.v                                        ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Module resposible for sending and receiving data through     ////
+//// 4-bit sd card data interface                                 ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// Based on original work by                                    ////
+////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
+////                                                              ////
+////     Copyright (C) 2009 Authors                               ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+`include "sd_defines.h"
+
+module sd_data_serial_host(
+           input sd_clk,
+           input rst,
+           //Tx Fifo
+           input [31:0] data_in,
+           output reg rd,
+           //Rx Fifo
+           output reg [31:0] data_out,
+           output reg we,
+           //tristate data
+           output reg DAT_oe_o,
+           output reg[3:0] DAT_dat_o,
+           input [3:0] DAT_dat_i,
+           //Controll signals
+           input [`BLKSIZE_W-1:0] blksize,
+           input bus_4bit,
+           input [`BLKCNT_W-1:0] blkcnt,
+           input [1:0] start,
+           output sd_data_busy,
+           output busy,
+           output reg crc_ok
+       );
+
+reg [3:0] DAT_dat_reg;
+reg [`BLKSIZE_W-1+3:0] data_cycles;
+reg bus_4bit_reg;
+//CRC16
+reg [3:0] crc_in;
+reg crc_en;
+reg crc_rst;
+wire [15:0] crc_out [3:0];
+reg [15:0] transf_cnt;
+parameter SIZE = 6;
+reg [SIZE-1:0] state;
+reg [SIZE-1:0] next_state;
+parameter IDLE       = 6'b000001;
+parameter WRITE_DAT  = 6'b000010;
+parameter WRITE_CRC  = 6'b000100;
+parameter WRITE_BUSY = 6'b001000;
+parameter READ_WAIT  = 6'b010000;
+parameter READ_DAT   = 6'b100000;
+reg [2:0] crc_status;
+reg busy_int;
+reg [`BLKCNT_W-1:0] blkcnt_reg;
+reg next_block;
+wire start_bit;
+reg [4:0] crc_c;
+reg [3:0] last_din;
+reg [2:0] crc_s ;
+reg [4:0] data_send_index;
+
+//sd data input pad register
+always @(posedge sd_clk)
+    DAT_dat_reg <= DAT_dat_i;
+
+genvar i;
+generate
+    for(i=0; i<4; i=i+1) begin: CRC_16_gen
+        sd_crc_16 CRC_16_i (crc_in[i],crc_en, sd_clk, crc_rst, crc_out[i]);
+    end
+endgenerate
+
+assign busy = (state != IDLE);
+assign start_bit = !DAT_dat_reg[0];
+assign sd_data_busy = !DAT_dat_reg[0];
+
+always @(state or start or start_bit or  transf_cnt or data_cycles or crc_status or crc_ok or busy_int or next_block)
+begin: FSM_COMBO
+    case(state)
+        IDLE: begin
+            if (start == 2'b01)
+                next_state <= WRITE_DAT;
+            else if  (start == 2'b10)
+                next_state <= READ_WAIT;
+            else
+                next_state <= IDLE;
+        end
+        WRITE_DAT: begin
+            if (transf_cnt >= data_cycles+21 && start_bit)
+                next_state <= WRITE_CRC;
+            else if (start == 2'b11)
+                next_state <= IDLE;
+            else
+                next_state <= WRITE_DAT;
+        end
+        WRITE_CRC: begin
+            if (crc_status == 3)
+                next_state <= WRITE_BUSY;
+            else
+                next_state <= WRITE_CRC;
+        end
+        WRITE_BUSY: begin
+            if (!busy_int && next_block && crc_ok)
+                next_state <= WRITE_DAT;
+            else if (!busy_int)
+                next_state <= IDLE;
+            else
+                next_state <= WRITE_BUSY;
+        end
+        READ_WAIT: begin
+            if (start_bit)
+                next_state <= READ_DAT;
+            else
+                next_state <= READ_WAIT;
+        end
+        READ_DAT: begin
+            if (transf_cnt == data_cycles+17 && next_block && crc_ok)
+                next_state <= READ_WAIT;
+            else if (transf_cnt == data_cycles+17)
+                next_state <= IDLE;
+            else if (start == 2'b11)
+                next_state <= IDLE;
+            else
+                next_state <= READ_DAT;
+        end
+        default: next_state <= IDLE;
+    endcase
+end
+
+always @(posedge sd_clk or posedge rst)
+begin: FSM_OUT
+    if (rst) begin
+        state <= IDLE;
+        DAT_oe_o <= 0;
+        crc_en <= 0;
+        crc_rst <= 1;
+        transf_cnt <= 0;
+        crc_c <= 15;
+        rd <= 0;
+        last_din <= 0;
+        crc_c <= 0;
+        crc_in <= 0;
+        DAT_dat_o <= 0;
+        crc_status <= 0;
+        crc_s <= 0;
+        we <= 0;
+        data_out <= 0;
+        crc_ok <= 0;
+        busy_int <= 0;
+        data_send_index <= 0;
+        next_block <= 0;
+        blkcnt_reg <= 0;
+        data_cycles <= 0;
+        bus_4bit_reg <= 0;      
+    end
+    else begin
+        state <= next_state;
+        case(state)
+            IDLE: begin
+                DAT_oe_o <= 0;
+                DAT_dat_o <= 4'b1111;
+                crc_en <= 0;
+                crc_rst <= 1;
+                transf_cnt <= 0;
+                crc_c <= 16;
+                crc_status <= 0;
+                crc_s <= 0;
+                we <= 0;
+                rd <= 0;
+                data_send_index <= 0;
+                next_block <= 0;
+                blkcnt_reg <= blkcnt;
+                data_cycles <= (bus_4bit ? (blksize << 1) : (blksize << 3));
+                bus_4bit_reg <= bus_4bit;
+            end
+            WRITE_DAT: begin
+                crc_ok <= 0;
+                transf_cnt <= transf_cnt + 16'h1;
+                next_block <= 0;
+                rd <= 0;
+                if (transf_cnt == 1) begin
+                    crc_rst <= 0;
+                    crc_en <= 1;
+                    if (bus_4bit_reg) begin
+                        last_din <= data_in[31:28];
+                        crc_in <= data_in[31:28];
+                    end
+                    else begin
+                        last_din <= {3'h7, data_in[31]};
+                        crc_in <= {3'h7, data_in[31]};
+                    end
+                    DAT_oe_o <= 1;
+                    DAT_dat_o <= bus_4bit_reg ? 4'h0 : 4'he;
+                    data_send_index <= 1;
+                end
+                else if ((transf_cnt >= 2) && (transf_cnt <= data_cycles+1)) begin
+                    DAT_oe_o<=1;
+                    if (bus_4bit_reg) begin
+                        last_din <= {
+                            data_in[31-(data_send_index[2:0]<<2)], 
+                            data_in[30-(data_send_index[2:0]<<2)], 
+                            data_in[29-(data_send_index[2:0]<<2)], 
+                            data_in[28-(data_send_index[2:0]<<2)]
+                            };
+                        crc_in <= {
+                            data_in[31-(data_send_index[2:0]<<2)], 
+                            data_in[30-(data_send_index[2:0]<<2)], 
+                            data_in[29-(data_send_index[2:0]<<2)], 
+                            data_in[28-(data_send_index[2:0]<<2)]
+                            };
+                        if (data_send_index[2:0] == 3'h5/*not 7 - read delay !!!*/) begin
+                            rd <= 1;
+                        end
+                        if (data_send_index[2:0] == 3'h7) begin
+                            data_send_index <= 0;
+                        end
+                        else
+                            data_send_index<=data_send_index + 5'h1;
+                    end
+                    else begin
+                        last_din <= {3'h7, data_in[31-data_send_index]};
+                        crc_in <= {3'h7, data_in[31-data_send_index]};
+                        if (data_send_index == 29/*not 31 - read delay !!!*/) begin
+                            rd <= 1;
+                        end
+                        if (data_send_index == 31) begin
+                            data_send_index <= 0;
+                        end
+                        else
+                            data_send_index<=data_send_index + 5'h1;
+                    end
+                    DAT_dat_o<= last_din;
+                    if (transf_cnt == data_cycles+1)
+                        crc_en<=0;
+                end
+                else if (transf_cnt > data_cycles+1 & crc_c!=0) begin
+                    crc_en <= 0;
+                    crc_c <= crc_c - 5'h1;
+                    DAT_oe_o <= 1;
+                    DAT_dat_o[0] <= crc_out[0][crc_c-1];
+                    if (bus_4bit_reg)
+                        DAT_dat_o[3:1] <= {crc_out[3][crc_c-1], crc_out[2][crc_c-1], crc_out[1][crc_c-1]};
+                    else
+                        DAT_dat_o[3:1] <= {3'h7};
+                end
+                else if (transf_cnt == data_cycles+18) begin
+                    DAT_oe_o <= 1;
+                    DAT_dat_o <= 4'hf;
+                end
+                else if (transf_cnt >= data_cycles+19) begin
+                    DAT_oe_o <= 0;
+                end
+            end
+            WRITE_CRC: begin
+                DAT_oe_o <= 0;
+                if (crc_status < 3)
+                    crc_s[crc_status] <= DAT_dat_reg[0];
+                crc_status <= crc_status + 3'h1;
+                busy_int <= 1;
+            end
+            WRITE_BUSY: begin
+                if (crc_s == 3'b010)
+                    crc_ok <= 1;
+                else
+                    crc_ok <= 0;
+                busy_int <= !DAT_dat_reg[0];
+                next_block <= (blkcnt_reg != 0);
+                if (next_state != WRITE_BUSY) begin
+                    blkcnt_reg <= blkcnt_reg - `BLKCNT_W'h1;
+                    crc_rst <= 1;
+                    crc_c <= 16;
+                    crc_status <= 0;
+                end
+                transf_cnt <= 0;
+            end
+            READ_WAIT: begin
+                DAT_oe_o <= 0;
+                crc_rst <= 0;
+                crc_en <= 1;
+                crc_in <= 0;
+                crc_c <= 15;// end
+                next_block <= 0;
+                transf_cnt <= 0;
+            end
+            READ_DAT: begin
+                if (transf_cnt < data_cycles) begin
+                    if (bus_4bit_reg) begin
+                        we <= (transf_cnt[2:0] == 7);
+                        data_out[31-(transf_cnt[2:0]<<2)] <= DAT_dat_reg[3];
+                        data_out[30-(transf_cnt[2:0]<<2)] <= DAT_dat_reg[2];
+                        data_out[29-(transf_cnt[2:0]<<2)] <= DAT_dat_reg[1];
+                        data_out[28-(transf_cnt[2:0]<<2)] <= DAT_dat_reg[0];
+                    end
+                    else begin
+                        we <= (transf_cnt[4:0] == 31);
+                        data_out[31-transf_cnt[4:0]] <= DAT_dat_reg[0];
+                    end
+                    crc_in <= DAT_dat_reg;
+                    crc_ok <= 1;
+                    transf_cnt <= transf_cnt + 16'h1;
+                end
+                else if (transf_cnt <= data_cycles+16) begin
+                    transf_cnt <= transf_cnt + 16'h1;
+                    crc_en <= 0;
+                    last_din <= DAT_dat_reg;
+                    we<=0;
+                    if (transf_cnt > data_cycles) begin
+                        crc_c <= crc_c - 5'h1;
+                        if  (crc_out[0][crc_c] != last_din[0])
+                            crc_ok <= 0;
+                        if  (crc_out[1][crc_c] != last_din[1] && bus_4bit_reg)
+                            crc_ok<=0;
+                        if  (crc_out[2][crc_c] != last_din[2] && bus_4bit_reg)
+                            crc_ok <= 0;
+                        if  (crc_out[3][crc_c] != last_din[3] && bus_4bit_reg)
+                            crc_ok <= 0;
+                        if (crc_c == 0) begin
+                            next_block <= (blkcnt_reg != 0);
+                            blkcnt_reg <= blkcnt_reg - `BLKCNT_W'h1;
+                            crc_rst <= 1;
+                        end
+                    end
+                end
+            end
+        endcase
+    end
+end
+
+endmodule
+
+
+
+
+
diff --git a/BENCHMARK/sdc_controller/rtl/sd_data_xfer_trig.v b/BENCHMARK/sdc_controller/rtl/sd_data_xfer_trig.v
new file mode 100644
index 0000000..c10ff86
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_data_xfer_trig.v
@@ -0,0 +1,126 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// sd_data_xfer_trig.v                                          ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Module resposible for triggering data transfer based on      ////
+//// command transfer completition code                           ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+`include "sd_defines.h" 
+
+module sd_data_xfer_trig (
+           input sd_clk,
+           input rst,
+           input cmd_with_data_start_i,
+           input r_w_i,
+           input [`INT_CMD_SIZE-1:0] cmd_int_status_i,
+           output reg start_tx_o,
+           output reg start_rx_o
+       );
+
+reg r_w_reg;
+parameter SIZE = 2;
+reg [SIZE-1:0] state;
+reg [SIZE-1:0] next_state;
+parameter IDLE             = 2'b00;
+parameter WAIT_FOR_CMD_INT = 2'b01;
+parameter TRIGGER_XFER     = 2'b10;
+
+always @(state or cmd_with_data_start_i or r_w_i or cmd_int_status_i)
+begin: FSM_COMBO
+    case(state)
+        IDLE: begin
+            if (cmd_with_data_start_i & r_w_i)
+                next_state <= TRIGGER_XFER;
+            else if (cmd_with_data_start_i)
+                next_state <= WAIT_FOR_CMD_INT;
+            else
+                next_state <= IDLE;
+        end
+        WAIT_FOR_CMD_INT: begin
+            if (cmd_int_status_i[`INT_CMD_CC])
+                next_state <= TRIGGER_XFER;
+            else if (cmd_int_status_i[`INT_CMD_EI])
+                next_state <= IDLE;
+            else
+                next_state <= WAIT_FOR_CMD_INT;
+        end
+        TRIGGER_XFER: begin
+            next_state <= IDLE;
+        end
+        default: next_state <= IDLE;
+    endcase
+end
+
+always @(posedge sd_clk or posedge rst)
+begin: FSM_SEQ
+    if (rst) begin
+        state <= IDLE;
+    end
+    else begin
+        state <= next_state;
+    end
+end
+
+always @(posedge sd_clk or posedge rst)
+begin
+    if (rst) begin
+        start_tx_o <= 0;
+        start_rx_o <= 0;
+        r_w_reg <= 0;
+    end
+    else begin
+        case(state)
+            IDLE: begin
+                start_tx_o <= 0;
+                start_rx_o <= 0;
+                r_w_reg <= r_w_i;
+            end
+            WAIT_FOR_CMD_INT: begin
+                start_tx_o <= 0;
+                start_rx_o <= 0;
+            end
+            TRIGGER_XFER: begin
+                start_tx_o <= ~r_w_reg;
+                start_rx_o <= r_w_reg;
+            end
+        endcase
+    end
+end
+
+endmodule
\ No newline at end of file
diff --git a/BENCHMARK/sdc_controller/rtl/sd_fifo_filler.v b/BENCHMARK/sdc_controller/rtl/sd_fifo_filler.v
new file mode 100644
index 0000000..f750ef6
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sd_fifo_filler.v
@@ -0,0 +1,148 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// sd_fifo_filler.v                                             ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Fifo interface between sd card and wishbone clock domains    ////
+//// and DMA engine eble to write/read to/from CPU memory         ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// Based on original work by                                    ////
+////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
+////                                                              ////
+////     Copyright (C) 2009 Authors                               ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+module sd_fifo_filler(
+           input wb_clk,
+           input rst,
+           //WB Signals
+           output [31:0] wbm_adr_o,
+           output wbm_we_o,
+           output [31:0] wbm_dat_o,
+           input [31:0] wbm_dat_i,
+           output wbm_cyc_o,
+           output wbm_stb_o,
+           input wbm_ack_i,
+           //Data Master Control signals
+           input en_rx_i,
+           input en_tx_i,
+           input [31:0] adr_i,
+           //Data Serial signals
+           input sd_clk,
+           input [31:0] dat_i,
+           output [31:0] dat_o,
+           input wr_i,
+           input rd_i,
+           output sd_full_o,
+           output sd_empty_o,
+           output wb_full_o,
+           output wb_empty_o
+       );
+
+`define FIFO_MEM_ADR_SIZE 4
+`define MEM_OFFSET 4
+
+wire reset_fifo;
+wire fifo_rd;
+reg [31:0] offset;
+reg fifo_rd_ack;
+reg fifo_rd_reg;
+
+assign fifo_rd = wbm_cyc_o & wbm_ack_i;
+assign reset_fifo = !en_rx_i & !en_tx_i;
+
+assign wbm_we_o = en_rx_i & !wb_empty_o;
+assign wbm_cyc_o = en_rx_i ? en_rx_i & !wb_empty_o : en_tx_i & !wb_full_o;
+assign wbm_stb_o = en_rx_i ? wbm_cyc_o & fifo_rd_ack : wbm_cyc_o;
+
+generic_fifo_dc_gray #(
+    .dw(32), 
+    .aw(`FIFO_MEM_ADR_SIZE)
+    ) generic_fifo_dc_gray0 (
+    .rd_clk(wb_clk),
+    .wr_clk(sd_clk), 
+    .rst(!(rst | reset_fifo)), 
+    .clr(1'b0), 
+    .din(dat_i), 
+    .we(wr_i),
+    .dout(wbm_dat_o), 
+    .re(en_rx_i & wbm_cyc_o & wbm_ack_i), 
+    .full(sd_full_o), 
+    .empty(wb_empty_o), 
+    .wr_level(), 
+    .rd_level() 
+    );
+    
+generic_fifo_dc_gray #(
+    .dw(32), 
+    .aw(`FIFO_MEM_ADR_SIZE)
+    ) generic_fifo_dc_gray1 (
+    .rd_clk(sd_clk),
+    .wr_clk(wb_clk), 
+    .rst(!(rst | reset_fifo)), 
+    .clr(1'b0), 
+    .din(wbm_dat_i), 
+    .we(en_tx_i & wbm_cyc_o & wbm_stb_o & wbm_ack_i),
+    .dout(dat_o), 
+    .re(rd_i), 
+    .full(wb_full_o), 
+    .empty(sd_empty_o), 
+    .wr_level(), 
+    .rd_level() 
+    );
+
+assign wbm_adr_o = adr_i+offset;
+
+always @(posedge wb_clk or posedge rst)
+    if (rst) begin
+        offset <= 0;
+        fifo_rd_reg <= 0;
+        fifo_rd_ack <= 1;
+    end
+    else begin
+        fifo_rd_reg <= fifo_rd;
+        fifo_rd_ack <= fifo_rd_reg | !fifo_rd;
+        if (wbm_cyc_o & wbm_stb_o & wbm_ack_i)
+            offset <= offset + `MEM_OFFSET;
+        else if (reset_fifo)
+            offset <= 0;
+    end
+
+endmodule
+
+
diff --git a/BENCHMARK/sdc_controller/rtl/sdc_controller.v b/BENCHMARK/sdc_controller/rtl/sdc_controller.v
new file mode 100644
index 0000000..58de16b
--- /dev/null
+++ b/BENCHMARK/sdc_controller/rtl/sdc_controller.v
@@ -0,0 +1,411 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// WISHBONE SD Card Controller IP Core                          ////
+////                                                              ////
+//// sdc_controller.v                                             ////
+////                                                              ////
+//// This file is part of the WISHBONE SD Card                    ////
+//// Controller IP Core project                                   ////
+//// http://opencores.org/project,sd_card_controller              ////
+////                                                              ////
+//// Description                                                  ////
+//// Top level entity.                                            ////
+//// This core is based on the "sd card controller" project from  ////
+//// http://opencores.org/project,sdcard_mass_storage_controller  ////
+//// but has been largely rewritten. A lot of effort has been     ////
+//// made to make the core more generic and easily usable         ////
+//// with OSs like Linux.                                         ////
+//// - data transfer commands are not fixed                       ////
+//// - data transfer block size is configurable                   ////
+//// - multiple block transfer support                            ////
+//// - R2 responses (136 bit) support                             ////
+////                                                              ////
+//// Author(s):                                                   ////
+////     - Marek Czerski, ma.czerski@gmail.com                    ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2013 Authors                                   ////
+////                                                              ////
+//// Based on original work by                                    ////
+////     Adam Edvardsson (adam.edvardsson@orsoc.se)               ////
+////                                                              ////
+////     Copyright (C) 2009 Authors                               ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE. See the GNU Lesser General Public License for more  ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+`include "sd_defines.h"
+
+module sdc_controller(
+           // WISHBONE common
+           wb_clk_i, 
+           wb_rst_i, 
+           // WISHBONE slave
+           wb_dat_i, 
+           wb_dat_o,
+           wb_adr_i, 
+           wb_sel_i, 
+           wb_we_i, 
+           wb_cyc_i, 
+           wb_stb_i, 
+           wb_ack_o,
+           // WISHBONE master
+           m_wb_dat_o,
+           m_wb_dat_i,
+           m_wb_adr_o, 
+           m_wb_sel_o, 
+           m_wb_we_o,
+           m_wb_cyc_o,
+           m_wb_stb_o, 
+           m_wb_ack_i,
+           m_wb_cti_o, 
+           m_wb_bte_o,
+           //SD BUS
+           sd_cmd_dat_i, 
+           sd_cmd_out_o, 
+           sd_cmd_oe_o, 
+           //card_detect,
+           sd_dat_dat_i, 
+           sd_dat_out_o, 
+           sd_dat_oe_o, 
+           sd_clk_o_pad,
+           sd_clk_i_pad,
+           int_cmd, 
+           int_data
+       );
+
+input wb_clk_i;
+input wb_rst_i;
+input [31:0] wb_dat_i;
+output [31:0] wb_dat_o;
+//input card_detect;
+input [7:0] wb_adr_i;
+input [3:0] wb_sel_i;
+input wb_we_i;
+input wb_cyc_i;
+input wb_stb_i;
+output wb_ack_o;
+output [31:0] m_wb_adr_o;
+output [3:0] m_wb_sel_o;
+output m_wb_we_o;
+input [31:0] m_wb_dat_i;
+output [31:0] m_wb_dat_o;
+output m_wb_cyc_o;
+output m_wb_stb_o;
+input m_wb_ack_i;
+output [2:0] m_wb_cti_o;
+output [1:0] m_wb_bte_o;
+input wire [3:0] sd_dat_dat_i;
+output wire [3:0] sd_dat_out_o;
+output wire sd_dat_oe_o;
+input wire sd_cmd_dat_i;
+output wire sd_cmd_out_o;
+output wire sd_cmd_oe_o;
+output sd_clk_o_pad;
+input wire sd_clk_i_pad;
+output int_cmd, int_data;
+
+//SD clock
+wire sd_clk_o; //Sd_clk used in the system
+
+wire go_idle;
+wire cmd_start_wb_clk;
+wire cmd_start_sd_clk;
+wire cmd_start;
+wire [1:0] cmd_setting;
+wire cmd_start_tx;
+wire [39:0] cmd;
+wire [119:0] cmd_response;
+wire cmd_crc_ok;
+wire cmd_index_ok;
+wire cmd_finish;
+
+wire d_write;
+wire d_read;
+wire [31:0] data_in_rx_fifo;
+wire [31:0] data_out_tx_fifo;
+wire start_tx_fifo;
+wire start_rx_fifo;
+wire tx_fifo_empty;
+wire tx_fifo_full;
+wire rx_fifo_full;
+wire sd_data_busy;
+wire data_busy;
+wire data_crc_ok;
+wire rd_fifo;
+wire we_fifo;
+
+wire data_start_rx;
+wire data_start_tx;
+wire cmd_int_rst_wb_clk;
+wire cmd_int_rst_sd_clk;
+wire cmd_int_rst;
+wire data_int_rst_wb_clk;
+wire data_int_rst_sd_clk;
+wire data_int_rst;
+
+//wb accessible registers
+wire [31:0] argument_reg_wb_clk;
+wire [`CMD_REG_SIZE-1:0] command_reg_wb_clk;
+wire [15:0] timeout_reg_wb_clk;
+wire [0:0] software_reset_reg_wb_clk;
+wire [31:0] response_0_reg_wb_clk;
+wire [31:0] response_1_reg_wb_clk;
+wire [31:0] response_2_reg_wb_clk;
+wire [31:0] response_3_reg_wb_clk;
+wire [`BLKSIZE_W-1:0] block_size_reg_wb_clk;
+wire [15:0] controll_setting_reg_wb_clk;
+wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg_wb_clk;
+wire [`INT_DATA_SIZE-1:0] data_int_status_reg_wb_clk;
+wire [`INT_CMD_SIZE-1:0] cmd_int_enable_reg_wb_clk;
+wire [`INT_DATA_SIZE-1:0] data_int_enable_reg_wb_clk;
+wire [`BLKCNT_W-1:0] block_count_reg_wb_clk;
+wire [31:0] dma_addr_reg_wb_clk;
+wire [7:0] clock_divider_reg_wb_clk;
+
+wire [31:0] argument_reg_sd_clk;
+wire [`CMD_REG_SIZE-1:0] command_reg_sd_clk;
+wire [15:0] timeout_reg_sd_clk;
+wire [0:0] software_reset_reg_sd_clk;
+wire [31:0] response_0_reg_sd_clk;
+wire [31:0] response_1_reg_sd_clk;
+wire [31:0] response_2_reg_sd_clk;
+wire [31:0] response_3_reg_sd_clk;
+wire [`BLKSIZE_W-1:0] block_size_reg_sd_clk;
+wire [15:0] controll_setting_reg_sd_clk;
+wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg_sd_clk;
+wire [2:0] data_int_status_reg_sd_clk;
+wire [`INT_CMD_SIZE-1:0] cmd_int_enable_reg_sd_clk;
+wire [2:0] data_int_enable_reg_sd_clk;
+wire [`BLKCNT_W-1:0] block_count_reg_sd_clk;
+wire [31:0] dma_addr_reg_sd_clk;
+wire [7:0] clock_divider_reg_sd_clk;
+
+sd_clock_divider clock_divider0(
+                     .CLK (sd_clk_i_pad),
+                     .DIVIDER (clock_divider_reg_sd_clk),
+                     .RST  (wb_rst_i),
+                     .SD_CLK  (sd_clk_o)
+                 );
+
+assign sd_clk_o_pad  = sd_clk_o ;
+
+sd_cmd_master sd_cmd_master0(
+           .sd_clk       (sd_clk_o),
+           .rst          (wb_rst_i | software_reset_reg_sd_clk[0]),
+           .start_i      (cmd_start_sd_clk),
+           .int_status_rst_i(cmd_int_rst_sd_clk),
+           .setting_o    (cmd_setting),
+           .start_xfr_o  (cmd_start_tx),
+           .go_idle_o    (go_idle),
+           .cmd_o        (cmd),
+           .response_i   (cmd_response),
+           .crc_ok_i     (cmd_crc_ok),
+           .index_ok_i   (cmd_index_ok),
+           .busy_i       (sd_data_busy),
+           .finish_i     (cmd_finish),
+           //input card_detect,
+           .argument_i   (argument_reg_sd_clk),
+           .command_i    (command_reg_sd_clk),
+           .timeout_i    (timeout_reg_sd_clk),
+           .int_status_o (cmd_int_status_reg_sd_clk),
+           .response_0_o (response_0_reg_sd_clk),
+           .response_1_o (response_1_reg_sd_clk),
+           .response_2_o (response_2_reg_sd_clk),
+           .response_3_o (response_3_reg_sd_clk)
+       );
+       
+sd_cmd_serial_host cmd_serial_host0(
+                       .sd_clk     (sd_clk_o),
+                       .rst        (wb_rst_i | software_reset_reg_sd_clk[0] | go_idle),
+                       .setting_i  (cmd_setting),
+                       .cmd_i      (cmd),
+                       .start_i    (cmd_start_tx),
+                       .finish_o   (cmd_finish),
+                       .response_o (cmd_response),
+                       .crc_ok_o   (cmd_crc_ok),
+                       .index_ok_o (cmd_index_ok),
+                       .cmd_dat_i  (sd_cmd_dat_i),
+                       .cmd_out_o  (sd_cmd_out_o),
+                       .cmd_oe_o   (sd_cmd_oe_o)
+                   );
+                   
+sd_data_master sd_data_master0(
+           .sd_clk           (sd_clk_o),
+           .rst              (wb_rst_i | software_reset_reg_sd_clk[0]),
+           .start_tx_i       (data_start_tx),
+           .start_rx_i       (data_start_rx),
+           .d_write_o        (d_write),
+           .d_read_o         (d_read),
+           .start_tx_fifo_o  (start_tx_fifo),
+           .start_rx_fifo_o  (start_rx_fifo),
+           .tx_fifo_empty_i  (tx_fifo_empty),
+           .tx_fifo_full_i   (tx_fifo_full),
+           .rx_fifo_full_i   (rx_fifo_full),
+           .xfr_complete_i   (!data_busy),
+           .crc_ok_i         (data_crc_ok),
+           .int_status_o     (data_int_status_reg_sd_clk),
+           .int_status_rst_i (data_int_rst_sd_clk)
+       );
+
+sd_data_serial_host sd_data_serial_host0(
+                        .sd_clk         (sd_clk_o),
+                        .rst            (wb_rst_i | software_reset_reg_sd_clk[0]),
+                        .data_in        (data_out_tx_fifo),
+                        .rd             (rd_fifo),
+                        .data_out       (data_in_rx_fifo),
+                        .we             (we_fifo),
+                        .DAT_oe_o       (sd_dat_oe_o),
+                        .DAT_dat_o      (sd_dat_out_o),
+                        .DAT_dat_i      (sd_dat_dat_i),
+                        .blksize        (block_size_reg_sd_clk),
+                        .bus_4bit       (controll_setting_reg_sd_clk[0]),
+                        .blkcnt         (block_count_reg_sd_clk),
+                        .start          ({d_read, d_write}),
+                        .sd_data_busy   (sd_data_busy),
+                        .busy           (data_busy),
+                        .crc_ok         (data_crc_ok)
+                    );
+       
+sd_fifo_filler sd_fifo_filler0(
+            .wb_clk    (wb_clk_i),
+            .rst       (wb_rst_i | software_reset_reg_sd_clk[0]),
+            .wbm_adr_o (m_wb_adr_o),
+            .wbm_we_o  (m_wb_we_o),
+            .wbm_dat_o (m_wb_dat_o),
+            .wbm_dat_i (m_wb_dat_i),
+            .wbm_cyc_o (m_wb_cyc_o),
+            .wbm_stb_o (m_wb_stb_o),
+            .wbm_ack_i (m_wb_ack_i),
+            .en_rx_i   (start_rx_fifo),
+            .en_tx_i   (start_tx_fifo),
+            .adr_i     (dma_addr_reg_sd_clk),
+            .sd_clk    (sd_clk_o),
+            .dat_i     (data_in_rx_fifo),
+            .dat_o     (data_out_tx_fifo),
+            .wr_i      (we_fifo),
+            .rd_i      (rd_fifo),
+            .sd_empty_o   (tx_fifo_empty),
+            .sd_full_o   (rx_fifo_full),
+            .wb_empty_o   (),
+            .wb_full_o    (tx_fifo_full)
+        );
+        
+sd_data_xfer_trig sd_data_xfer_trig0 (
+           .sd_clk                (sd_clk_o),
+           .rst                   (wb_rst_i | software_reset_reg_sd_clk[0]),
+           .cmd_with_data_start_i (cmd_start_sd_clk & (command_reg_sd_clk[`CMD_WITH_DATA] != 2'b00)),
+           .r_w_i                 (command_reg_sd_clk[`CMD_WITH_DATA] == 2'b01),
+           .cmd_int_status_i      (cmd_int_status_reg_sd_clk),
+           .start_tx_o            (data_start_tx),
+           .start_rx_o            (data_start_rx)
+       );
+
+sd_controller_wb sd_controller_wb0(
+                     .wb_clk_i                       (wb_clk_i),
+                     .wb_rst_i                       (wb_rst_i),
+                     .wb_dat_i                       (wb_dat_i),
+                     .wb_dat_o                       (wb_dat_o),
+                     .wb_adr_i                       (wb_adr_i),
+                     .wb_sel_i                       (wb_sel_i),
+                     .wb_we_i                        (wb_we_i),
+                     .wb_stb_i                       (wb_stb_i),
+                     .wb_cyc_i                       (wb_cyc_i),
+                     .wb_ack_o                       (wb_ack_o),
+                     .cmd_start                      (cmd_start),
+                     .data_int_rst                   (data_int_rst),
+                     .cmd_int_rst                    (cmd_int_rst),
+                     .argument_reg                   (argument_reg_wb_clk),
+                     .command_reg                    (command_reg_wb_clk),
+                     .response_0_reg                 (response_0_reg_wb_clk),
+                     .response_1_reg                 (response_1_reg_wb_clk),
+                     .response_2_reg                 (response_2_reg_wb_clk),
+                     .response_3_reg                 (response_3_reg_wb_clk),
+                     .software_reset_reg             (software_reset_reg_wb_clk),
+                     .timeout_reg                    (timeout_reg_wb_clk),
+                     .block_size_reg                 (block_size_reg_wb_clk),
+                     .controll_setting_reg           (controll_setting_reg_wb_clk),
+                     .cmd_int_status_reg             (cmd_int_status_reg_wb_clk),
+                     .cmd_int_enable_reg             (cmd_int_enable_reg_wb_clk),
+                     .clock_divider_reg              (clock_divider_reg_wb_clk),
+                     .block_count_reg                (block_count_reg_wb_clk),
+                     .dma_addr_reg                   (dma_addr_reg_wb_clk),
+                     .data_int_status_reg            (data_int_status_reg_wb_clk),
+                     .data_int_enable_reg            (data_int_enable_reg_wb_clk)
+                 );
+
+//clock domain crossing regiters
+//assign cmd_start_sd_clk = cmd_start_wb_clk;
+//assign data_int_rst_sd_clk = data_int_rst_wb_clk;
+//assign cmd_int_rst_sd_clk = cmd_int_rst_wb_clk;
+//assign argument_reg_sd_clk = argument_reg_wb_clk;
+//assign command_reg_sd_clk = command_reg_wb_clk;
+//assign response_0_reg_wb_clk = response_0_reg_sd_clk;
+//assign response_1_reg_wb_clk = response_1_reg_sd_clk;
+//assign response_2_reg_wb_clk = response_2_reg_sd_clk;
+//assign response_3_reg_wb_clk = response_3_reg_sd_clk;
+//assign software_reset_reg_sd_clk = software_reset_reg_wb_clk;
+//assign timeout_reg_sd_clk = timeout_reg_wb_clk;
+//assign block_size_reg_sd_clk = block_size_reg_wb_clk;
+//assign controll_setting_reg_sd_clk = controll_setting_reg_wb_clk;
+//assign cmd_int_status_reg_wb_clk = cmd_int_status_reg_sd_clk;
+//assign cmd_int_enable_reg_sd_clk = cmd_int_enable_reg_wb_clk;
+//assign clock_divider_reg_sd_clk = clock_divider_reg_wb_clk;
+//assign block_count_reg_sd_clk = block_count_reg_wb_clk;
+//assign dma_addr_reg_sd_clk = dma_addr_reg_wb_clk;
+//assign data_int_status_reg_wb_clk = data_int_status_reg_sd_clk;
+//assign data_int_enable_reg_sd_clk = data_int_enable_reg_wb_clk;
+
+edge_detect cmd_start_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(cmd_start), .rise(cmd_start_wb_clk), .fall());
+edge_detect data_int_rst_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(data_int_rst), .rise(data_int_rst_wb_clk), .fall());
+edge_detect cmd_int_rst_edge(.rst(wb_rst_i), .clk(wb_clk_i), .sig(cmd_int_rst), .rise(cmd_int_rst_wb_clk), .fall());
+monostable_domain_cross cmd_start_cross(wb_rst_i, wb_clk_i, cmd_start_wb_clk, sd_clk_o, cmd_start_sd_clk);
+monostable_domain_cross data_int_rst_cross(wb_rst_i, wb_clk_i, data_int_rst_wb_clk, sd_clk_o, data_int_rst_sd_clk);
+monostable_domain_cross cmd_int_rst_cross(wb_rst_i, wb_clk_i, cmd_int_rst_wb_clk, sd_clk_o, cmd_int_rst_sd_clk);
+bistable_domain_cross #(32) argument_reg_cross(wb_rst_i, wb_clk_i, argument_reg_wb_clk, sd_clk_o, argument_reg_sd_clk);
+bistable_domain_cross #(`CMD_REG_SIZE) command_reg_cross(wb_rst_i, wb_clk_i, command_reg_wb_clk, sd_clk_o, command_reg_sd_clk);
+bistable_domain_cross #(32) response_0_reg_cross(wb_rst_i, sd_clk_o, response_0_reg_sd_clk, wb_clk_i, response_0_reg_wb_clk);
+bistable_domain_cross #(32) response_1_reg_cross(wb_rst_i, sd_clk_o, response_1_reg_sd_clk, wb_clk_i, response_1_reg_wb_clk);
+bistable_domain_cross #(32) response_2_reg_cross(wb_rst_i, sd_clk_o, response_2_reg_sd_clk, wb_clk_i, response_2_reg_wb_clk);
+bistable_domain_cross #(32) response_3_reg_cross(wb_rst_i, sd_clk_o, response_3_reg_sd_clk, wb_clk_i, response_3_reg_wb_clk);
+bistable_domain_cross software_reset_reg_cross(wb_rst_i, wb_clk_i, software_reset_reg_wb_clk, sd_clk_o, software_reset_reg_sd_clk);
+bistable_domain_cross #(16) timeout_reg_cross(wb_rst_i, wb_clk_i, timeout_reg_wb_clk, sd_clk_o, timeout_reg_sd_clk);
+bistable_domain_cross #(`BLKSIZE_W) block_size_reg_cross(wb_rst_i, wb_clk_i, block_size_reg_wb_clk, sd_clk_o, block_size_reg_sd_clk);
+bistable_domain_cross #(16) controll_setting_reg_cross(wb_rst_i, wb_clk_i, controll_setting_reg_wb_clk, sd_clk_o, controll_setting_reg_sd_clk);
+bistable_domain_cross #(`INT_CMD_SIZE) cmd_int_status_reg_cross(wb_rst_i, sd_clk_o, cmd_int_status_reg_sd_clk, wb_clk_i, cmd_int_status_reg_wb_clk);
+bistable_domain_cross #(`INT_CMD_SIZE) cmd_int_enable_reg_cross(wb_rst_i, wb_clk_i, cmd_int_enable_reg_wb_clk, sd_clk_o, cmd_int_enable_reg_sd_clk);
+bistable_domain_cross #(8) clock_divider_reg_cross(wb_rst_i, wb_clk_i, clock_divider_reg_wb_clk, sd_clk_i_pad, clock_divider_reg_sd_clk);
+bistable_domain_cross #(`BLKCNT_W) block_count_reg_cross(wb_rst_i, wb_clk_i, block_count_reg_wb_clk, sd_clk_o, block_count_reg_sd_clk);
+bistable_domain_cross #(32) dma_addr_reg_cross(wb_rst_i, wb_clk_i, dma_addr_reg_wb_clk, sd_clk_o, dma_addr_reg_sd_clk);
+bistable_domain_cross #(`INT_DATA_SIZE) data_int_status_reg_cross(wb_rst_i, sd_clk_o, data_int_status_reg_sd_clk, wb_clk_i, data_int_status_reg_wb_clk);
+bistable_domain_cross #(`INT_DATA_SIZE) data_int_enable_reg_cross(wb_rst_i, wb_clk_i, data_int_enable_reg_wb_clk, sd_clk_o, data_int_enable_reg_sd_clk);
+
+assign m_wb_cti_o = 3'b000;
+assign m_wb_bte_o = 2'b00;
+
+assign int_cmd =  |(cmd_int_status_reg_wb_clk & cmd_int_enable_reg_wb_clk);
+assign int_data =  |(data_int_status_reg_wb_clk & data_int_enable_reg_wb_clk);
+
+assign m_wb_sel_o = 4'b1111;
+
+endmodule
diff --git a/BENCHMARK/sdc_controller/sdc_controller_yosys.blif b/BENCHMARK/sdc_controller/sdc_controller_yosys.blif
new file mode 100644
index 0000000..66a0864
--- /dev/null
+++ b/BENCHMARK/sdc_controller/sdc_controller_yosys.blif
@@ -0,0 +1,24835 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model sdc_controller
+.inputs wb_clk_i wb_rst_i wb_dat_i(0) wb_dat_i(1) wb_dat_i(2) wb_dat_i(3) wb_dat_i(4) wb_dat_i(5) wb_dat_i(6) wb_dat_i(7) wb_dat_i(8) wb_dat_i(9) wb_dat_i(10) wb_dat_i(11) wb_dat_i(12) wb_dat_i(13) wb_dat_i(14) wb_dat_i(15) wb_dat_i(16) wb_dat_i(17) wb_dat_i(18) wb_dat_i(19) wb_dat_i(20) wb_dat_i(21) wb_dat_i(22) wb_dat_i(23) wb_dat_i(24) wb_dat_i(25) wb_dat_i(26) wb_dat_i(27) wb_dat_i(28) wb_dat_i(29) wb_dat_i(30) wb_dat_i(31) wb_adr_i(0) wb_adr_i(1) wb_adr_i(2) wb_adr_i(3) wb_adr_i(4) wb_adr_i(5) wb_adr_i(6) wb_adr_i(7) wb_sel_i(0) wb_sel_i(1) wb_sel_i(2) wb_sel_i(3) wb_we_i wb_cyc_i wb_stb_i m_wb_dat_i(0) m_wb_dat_i(1) m_wb_dat_i(2) m_wb_dat_i(3) m_wb_dat_i(4) m_wb_dat_i(5) m_wb_dat_i(6) m_wb_dat_i(7) m_wb_dat_i(8) m_wb_dat_i(9) m_wb_dat_i(10) m_wb_dat_i(11) m_wb_dat_i(12) m_wb_dat_i(13) m_wb_dat_i(14) m_wb_dat_i(15) m_wb_dat_i(16) m_wb_dat_i(17) m_wb_dat_i(18) m_wb_dat_i(19) m_wb_dat_i(20) m_wb_dat_i(21) m_wb_dat_i(22) m_wb_dat_i(23) m_wb_dat_i(24) m_wb_dat_i(25) m_wb_dat_i(26) m_wb_dat_i(27) m_wb_dat_i(28) m_wb_dat_i(29) m_wb_dat_i(30) m_wb_dat_i(31) m_wb_ack_i sd_cmd_dat_i sd_dat_dat_i(0) sd_dat_dat_i(1) sd_dat_dat_i(2) sd_dat_dat_i(3) sd_clk_i_pad
+.outputs wb_dat_o(0) wb_dat_o(1) wb_dat_o(2) wb_dat_o(3) wb_dat_o(4) wb_dat_o(5) wb_dat_o(6) wb_dat_o(7) wb_dat_o(8) wb_dat_o(9) wb_dat_o(10) wb_dat_o(11) wb_dat_o(12) wb_dat_o(13) wb_dat_o(14) wb_dat_o(15) wb_dat_o(16) wb_dat_o(17) wb_dat_o(18) wb_dat_o(19) wb_dat_o(20) wb_dat_o(21) wb_dat_o(22) wb_dat_o(23) wb_dat_o(24) wb_dat_o(25) wb_dat_o(26) wb_dat_o(27) wb_dat_o(28) wb_dat_o(29) wb_dat_o(30) wb_dat_o(31) wb_ack_o m_wb_dat_o(0) m_wb_dat_o(1) m_wb_dat_o(2) m_wb_dat_o(3) m_wb_dat_o(4) m_wb_dat_o(5) m_wb_dat_o(6) m_wb_dat_o(7) m_wb_dat_o(8) m_wb_dat_o(9) m_wb_dat_o(10) m_wb_dat_o(11) m_wb_dat_o(12) m_wb_dat_o(13) m_wb_dat_o(14) m_wb_dat_o(15) m_wb_dat_o(16) m_wb_dat_o(17) m_wb_dat_o(18) m_wb_dat_o(19) m_wb_dat_o(20) m_wb_dat_o(21) m_wb_dat_o(22) m_wb_dat_o(23) m_wb_dat_o(24) m_wb_dat_o(25) m_wb_dat_o(26) m_wb_dat_o(27) m_wb_dat_o(28) m_wb_dat_o(29) m_wb_dat_o(30) m_wb_dat_o(31) m_wb_adr_o(0) m_wb_adr_o(1) m_wb_adr_o(2) m_wb_adr_o(3) m_wb_adr_o(4) m_wb_adr_o(5) m_wb_adr_o(6) m_wb_adr_o(7) m_wb_adr_o(8) m_wb_adr_o(9) m_wb_adr_o(10) m_wb_adr_o(11) m_wb_adr_o(12) m_wb_adr_o(13) m_wb_adr_o(14) m_wb_adr_o(15) m_wb_adr_o(16) m_wb_adr_o(17) m_wb_adr_o(18) m_wb_adr_o(19) m_wb_adr_o(20) m_wb_adr_o(21) m_wb_adr_o(22) m_wb_adr_o(23) m_wb_adr_o(24) m_wb_adr_o(25) m_wb_adr_o(26) m_wb_adr_o(27) m_wb_adr_o(28) m_wb_adr_o(29) m_wb_adr_o(30) m_wb_adr_o(31) m_wb_sel_o(0) m_wb_sel_o(1) m_wb_sel_o(2) m_wb_sel_o(3) m_wb_we_o m_wb_cyc_o m_wb_stb_o m_wb_cti_o(0) m_wb_cti_o(1) m_wb_cti_o(2) m_wb_bte_o(0) m_wb_bte_o(1) sd_cmd_out_o sd_cmd_oe_o sd_dat_out_o(0) sd_dat_out_o(1) sd_dat_out_o(2) sd_dat_out_o(3) sd_dat_oe_o sd_clk_o_pad int_cmd int_data
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_1 a=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe
+.subckt logic_0 a=sd_data_serial_host0.busy
+.subckt out_buff A=$iopadmap$int_cmd Q=int_cmd
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$int_data Q=int_data
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=m_wb_ack_i Q=sd_fifo_filler0.wbm_ack_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(0) Q=m_wb_adr_o(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(1) Q=m_wb_adr_o(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(10) Q=m_wb_adr_o(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(11) Q=m_wb_adr_o(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(12) Q=m_wb_adr_o(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(13) Q=m_wb_adr_o(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(14) Q=m_wb_adr_o(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(15) Q=m_wb_adr_o(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(16) Q=m_wb_adr_o(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(17) Q=m_wb_adr_o(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(18) Q=m_wb_adr_o(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(19) Q=m_wb_adr_o(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(2) Q=m_wb_adr_o(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(20) Q=m_wb_adr_o(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(21) Q=m_wb_adr_o(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(22) Q=m_wb_adr_o(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(23) Q=m_wb_adr_o(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(24) Q=m_wb_adr_o(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(25) Q=m_wb_adr_o(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(26) Q=m_wb_adr_o(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(27) Q=m_wb_adr_o(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(28) Q=m_wb_adr_o(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(29) Q=m_wb_adr_o(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(3) Q=m_wb_adr_o(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(30) Q=m_wb_adr_o(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(31) Q=m_wb_adr_o(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(4) Q=m_wb_adr_o(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(5) Q=m_wb_adr_o(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(6) Q=m_wb_adr_o(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(7) Q=m_wb_adr_o(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(8) Q=m_wb_adr_o(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_adr_o(9) Q=m_wb_adr_o(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_bte_o(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_bte_o(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_cti_o(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_cti_o(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_data_serial_host0.busy Q=m_wb_cti_o(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=sd_fifo_filler0.wbm_cyc_o Q=m_wb_cyc_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=m_wb_dat_i(0) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(1) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(10) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(11) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(12) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(13) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(14) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(15) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(16) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(17) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(18) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=m_wb_dat_i(19) Q=sd_fifo_filler0.generic_fifo_dc_gray1.din(19)
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+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](18) D=argument_reg_cross.in(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](17) D=argument_reg_cross.in(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](16) D=argument_reg_cross.in(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](15) D=argument_reg_cross.in(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](14) D=argument_reg_cross.in(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](13) D=argument_reg_cross.in(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](12) D=argument_reg_cross.in(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](29) D=argument_reg_cross.in(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](11) D=argument_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](10) D=argument_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](9) D=argument_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](8) D=argument_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](7) D=argument_reg_cross.in(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](6) D=argument_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](5) D=argument_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](4) D=argument_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](3) D=argument_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](2) D=argument_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](28) D=argument_reg_cross.in(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](1) D=argument_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](0) D=argument_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](27) D=argument_reg_cross.in(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](26) D=argument_reg_cross.in(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](25) D=argument_reg_cross.in(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](24) D=argument_reg_cross.in(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](23) D=argument_reg_cross.in(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.sync_clk_b[0](22) D=argument_reg_cross.in(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(31) D=argument_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(30) D=argument_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(21) D=argument_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(20) D=argument_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(19) D=argument_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(18) D=argument_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(17) D=argument_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(16) D=argument_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(15) D=argument_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(14) D=argument_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(13) D=argument_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(12) D=argument_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(29) D=argument_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(11) D=argument_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(10) D=argument_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(9) D=argument_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(8) D=argument_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(7) D=argument_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(6) D=argument_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(5) D=argument_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(4) D=argument_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(3) D=argument_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(2) D=argument_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(28) D=argument_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(1) D=argument_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(0) D=argument_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(27) D=argument_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(26) D=argument_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(25) D=argument_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(24) D=argument_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(23) D=argument_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=argument_reg_cross.out(22) D=argument_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:385.29-385.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](15) D=block_count_reg_cross.in(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](14) D=block_count_reg_cross.in(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](5) D=block_count_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](4) D=block_count_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](3) D=block_count_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](2) D=block_count_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](1) D=block_count_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](0) D=block_count_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](13) D=block_count_reg_cross.in(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](12) D=block_count_reg_cross.in(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](11) D=block_count_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](10) D=block_count_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](9) D=block_count_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](8) D=block_count_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](7) D=block_count_reg_cross.in(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.sync_clk_b[0](6) D=block_count_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(15) D=block_count_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(14) D=block_count_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(5) D=block_count_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(4) D=block_count_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(3) D=block_count_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(2) D=block_count_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(1) D=block_count_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(0) D=block_count_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(13) D=block_count_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(12) D=block_count_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(11) D=block_count_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(10) D=block_count_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(9) D=block_count_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(8) D=block_count_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(7) D=block_count_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_count_reg_cross.out(6) D=block_count_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:398.29-398.128|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](11) D=block_size_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](10) D=block_size_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](1) D=block_size_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](0) D=block_size_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](9) D=block_size_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](8) D=block_size_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](7) D=block_size_reg_cross.in(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](6) D=block_size_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](5) D=block_size_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](4) D=block_size_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](3) D=block_size_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.sync_clk_b[0](2) D=block_size_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(11) D=block_size_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(10) D=block_size_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(1) D=block_size_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(0) D=block_size_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(9) D=block_size_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(8) D=block_size_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(7) D=block_size_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(6) D=block_size_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(5) D=block_size_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(4) D=block_size_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(3) D=block_size_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=block_size_reg_cross.out(2) D=block_size_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:393.29-393.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.ClockDiv(7) D=clock_divider0.ClockDiv_ff_CQZ_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.ClockDiv(6) D=clock_divider0.ClockDiv_ff_CQZ_1_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=clock_divider0.ClockDiv(6) I2=clock_divider0.ClockDiv_ff_CQZ_D_LUT4_O_I0 I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=clock_divider0.ClockDiv(5) D=clock_divider0.ClockDiv_ff_CQZ_2_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=clock_divider0.ClockDiv_ff_CQZ_3_D_LUT4_O_I2 I1=clock_divider0.ClockDiv(4) I2=clock_divider0.SD_CLK_O_ff_CQZ_QEN I3=clock_divider0.ClockDiv(5) O=clock_divider0.ClockDiv_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=clock_divider0.ClockDiv(4) D=clock_divider0.ClockDiv_ff_CQZ_3_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=clock_divider0.ClockDiv(4) I2=clock_divider0.ClockDiv_ff_CQZ_3_D_LUT4_O_I2 I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=clock_divider0.ClockDiv(0) I1=clock_divider0.ClockDiv(1) I2=clock_divider0.ClockDiv(2) I3=clock_divider0.ClockDiv(3) O=clock_divider0.ClockDiv_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=clock_divider0.ClockDiv(3) D=clock_divider0.ClockDiv_ff_CQZ_4_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=clock_divider0.ClockDiv_ff_CQZ_4_D_LUT4_O_I2 I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=clock_divider0.ClockDiv(0) I1=clock_divider0.ClockDiv(1) I2=clock_divider0.ClockDiv(2) I3=clock_divider0.ClockDiv(3) O=clock_divider0.ClockDiv_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=clock_divider0.ClockDiv(2) D=clock_divider0.ClockDiv_ff_CQZ_5_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=clock_divider0.ClockDiv(0) I1=clock_divider0.ClockDiv(1) I2=clock_divider0.SD_CLK_O_ff_CQZ_QEN I3=clock_divider0.ClockDiv(2) O=clock_divider0.ClockDiv_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=clock_divider0.ClockDiv(1) D=clock_divider0.ClockDiv_ff_CQZ_6_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=clock_divider0.ClockDiv(1) I2=clock_divider0.ClockDiv(0) I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=clock_divider0.ClockDiv(0) D=clock_divider0.ClockDiv_ff_CQZ_7_D QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=clock_divider0.ClockDiv(0) I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN O=clock_divider0.ClockDiv_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=clock_divider0.ClockDiv_ff_CQZ_D_LUT4_O_I0 I1=clock_divider0.ClockDiv(6) I2=clock_divider0.SD_CLK_O_ff_CQZ_QEN I3=clock_divider0.ClockDiv(7) O=clock_divider0.ClockDiv_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=clock_divider0.ClockDiv(5) I2=clock_divider0.ClockDiv(4) I3=clock_divider0.ClockDiv_ff_CQZ_3_D_LUT4_O_I2 O=clock_divider0.ClockDiv_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=argument_reg_cross.clk_b D=clock_divider0.SD_CLK_O_ff_CQZ_D QCK=clock_divider0.CLK QEN=clock_divider0.SD_CLK_O_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:204.18-209.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_clock_divider.v:62.1-75.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.busy I3=argument_reg_cross.clk_b O=clock_divider0.SD_CLK_O_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt LUT4 I0=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I0 I1=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I1 I2=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I2 I3=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I3 O=clock_divider0.SD_CLK_O_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=clock_divider0.ClockDiv(1) I1=clock_divider0.DIVIDER(1) I2=clock_divider0.ClockDiv(6) I3=clock_divider0.DIVIDER(6) O=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=clock_divider0.ClockDiv(4) I1=clock_divider0.DIVIDER(4) I2=clock_divider0.ClockDiv(5) I3=clock_divider0.DIVIDER(5) O=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=clock_divider0.ClockDiv(0) I1=clock_divider0.DIVIDER(0) I2=clock_divider0.ClockDiv(3) I3=clock_divider0.DIVIDER(3) O=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=clock_divider0.ClockDiv(2) I1=clock_divider0.DIVIDER(2) I2=clock_divider0.ClockDiv(7) I3=clock_divider0.DIVIDER(7) O=clock_divider0.SD_CLK_O_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](7) D=clock_divider_reg_cross.in(7) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](6) D=clock_divider_reg_cross.in(6) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](5) D=clock_divider_reg_cross.in(5) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](4) D=clock_divider_reg_cross.in(4) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](3) D=clock_divider_reg_cross.in(3) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](2) D=clock_divider_reg_cross.in(2) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](1) D=clock_divider_reg_cross.in(1) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider_reg_cross.sync_clk_b[0](0) D=clock_divider_reg_cross.in(0) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.DIVIDER(7) D=clock_divider_reg_cross.sync_clk_b[0](7) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.DIVIDER(6) D=clock_divider_reg_cross.sync_clk_b[0](6) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.DIVIDER(5) D=clock_divider_reg_cross.sync_clk_b[0](5) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.DIVIDER(4) D=clock_divider_reg_cross.sync_clk_b[0](4) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.DIVIDER(3) D=clock_divider_reg_cross.sync_clk_b[0](3) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.DIVIDER(2) D=clock_divider_reg_cross.sync_clk_b[0](2) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.DIVIDER(1) D=clock_divider_reg_cross.sync_clk_b[0](1) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=clock_divider0.DIVIDER(0) D=clock_divider_reg_cross.sync_clk_b[0](0) QCK=clock_divider0.CLK QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:397.28-397.137|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=cmd_int_rst_cross.sync_clk_b(1) I3=cmd_int_rst_cross.sync_clk_b(2) O=sd_cmd_master0.int_status_reg_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=cmd_int_rst_cross.sync_clk_b(2) D=cmd_int_rst_cross.sync_clk_b(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:384.25-384.112|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_rst_cross.sync_clk_b(1) D=cmd_int_rst_cross.sync_clk_b(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:384.25-384.112|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_rst_cross.sync_clk_b(0) D=cmd_int_rst_cross.toggle_clk_a QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:384.25-384.112|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_int_rst_cross.toggle_clk_a I2=cmd_int_rst_edge.sig_reg(0) I3=cmd_int_rst_edge.sig_reg(1) O=cmd_int_rst_cross.toggle_clk_a_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt ff CQZ=cmd_int_rst_cross.toggle_clk_a D=cmd_int_rst_cross.toggle_clk_a_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:384.25-384.112|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:57.1-63.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_rst_edge.sig_reg(1) D=cmd_int_rst_edge.sig_reg(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:381.13-381.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_rst_edge.sig_reg(0) D=cmd_int_rst_edge.sig QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:381.13-381.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(4) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(3) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(2) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(1) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg(0) I3=sd_cmd_master0.state_LUT4_I2_1_O O=cmd_int_status_reg_cross.in(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](4) D=cmd_int_status_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](3) D=cmd_int_status_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](2) D=cmd_int_status_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](1) D=cmd_int_status_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_status_reg_cross.sync_clk_b[0](0) D=cmd_int_status_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_status_reg_cross.out(4) D=cmd_int_status_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_status_reg_cross.out(3) D=cmd_int_status_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_status_reg_cross.out(2) D=cmd_int_status_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_status_reg_cross.out(1) D=cmd_int_status_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_int_status_reg_cross.out(0) D=cmd_int_status_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:395.28-395.136|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(6) D=cmd_serial_host0.CRC_7.CRC(5) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(5) D=cmd_serial_host0.CRC_7.CRC(4) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(4) D=cmd_serial_host0.CRC_7.CRC(3) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(3) D=cmd_serial_host0.CRC_7.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(2) D=cmd_serial_host0.CRC_7.CRC(1) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(1) D=cmd_serial_host0.CRC_7.CRC(0) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.CRC_7.CRC(0) D=cmd_serial_host0.CRC_7.inv QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.CRC_7.ENABLE QRT=cmd_serial_host0.CRC_7.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_7.v:17.4-32.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:123.10-128.22|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.CRC_7.CRC(2) I3=cmd_serial_host0.CRC_7.inv O=cmd_serial_host0.CRC_7.CRC_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.CRC_7.BITVAL I3=cmd_serial_host0.CRC_7.CRC(6) O=cmd_serial_host0.CRC_7.inv
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(39) D=cmd(39) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(38) D=cmd(38) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(29) D=cmd(29) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(28) D=cmd(28) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(27) D=cmd(27) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(26) D=cmd(26) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(25) D=cmd(25) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(24) D=cmd(24) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(23) D=cmd(23) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(22) D=cmd(22) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(21) D=cmd(21) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(20) D=cmd(20) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(37) D=cmd(37) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(19) D=cmd(19) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(18) D=cmd(18) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(17) D=cmd(17) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(16) D=cmd(16) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(15) D=cmd(15) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(14) D=cmd(14) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(13) D=cmd(13) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(12) D=cmd(12) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(11) D=cmd(11) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(10) D=cmd(10) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(36) D=cmd(36) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(9) D=cmd(9) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(8) D=cmd(8) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(7) D=cmd(7) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(6) D=cmd(6) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(5) D=cmd(5) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(4) D=cmd(4) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(3) D=cmd(3) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(2) D=cmd(2) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(1) D=cmd(1) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(0) D=cmd(0) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(35) D=cmd(35) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(34) D=cmd(34) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(33) D=cmd(33) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(32) D=cmd(32) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(31) D=cmd(31) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_buff(30) D=cmd(30) QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.cmd_dat_reg D=cmd_serial_host0.cmd_dat_i QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:119.1-120.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=cmd_serial_host0.cmd_oe_o D=cmd_serial_host0.cmd_oe_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=cmd_serial_host0.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_oe_o_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.cmd_oe_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_O I2=cmd_serial_host0.next_state_LUT4_O_3_I2 I3=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O O=cmd_serial_host0.cmd_oe_o_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=cmd_serial_host0.cmd_out_o D=cmd_serial_host0.cmd_out_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=cmd_serial_host0.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100001111
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111110011111010
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(23) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(15) I1=cmd_serial_host0.cmd_buff(31) I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(7) I1=cmd_serial_host0.cmd_buff(39) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(5) I1=cmd_serial_host0.cmd_buff(37) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_buff(21) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(29) I3=cmd_serial_host0.cmd_buff(13) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(18) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.cmd_buff(34) I3=cmd_serial_host0.cmd_buff(2) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(26) I3=cmd_serial_host0.cmd_buff(10) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(14) I1=cmd_serial_host0.cmd_buff(30) I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(22) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.cmd_buff(38) I3=cmd_serial_host0.cmd_buff(6) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(19) I2=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(3) I1=cmd_serial_host0.cmd_buff(35) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(2) I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(2) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(17) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(9) I1=cmd_serial_host0.cmd_buff(25) I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(1) I1=cmd_serial_host0.cmd_buff(33) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(31) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.counter(22) I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.counter(19) I3=cmd_serial_host0.counter(17) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cmd_serial_host0.counter(18) I1=cmd_serial_host0.counter(16) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cmd_serial_host0.counter(24) I1=cmd_serial_host0.counter(25) I2=cmd_serial_host0.counter(26) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(30) I2=cmd_serial_host0.counter(29) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(5) I1=cmd_serial_host0.CRC_7.CRC(6) I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(0) I1=cmd_serial_host0.CRC_7.CRC(4) I2=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I1=cmd_serial_host0.CRC_7.CRC(2) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=cmd_serial_host0.counter(1) I1=cmd_serial_host0.CRC_7.CRC(3) I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN O=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.state(4) I2=cmd_serial_host0.state(6) I3=cmd_serial_host0.state(5) O=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt ff CQZ=cmd_serial_host0.counter(31) D=cmd_serial_host0.counter_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.counter(30) D=cmd_serial_host0.counter_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.counter(21) D=cmd_serial_host0.counter_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter_ff_CQZ_10_D_LUT4_O_I3 O=cmd_serial_host0.counter_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.counter_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=cmd_serial_host0.counter(20) D=cmd_serial_host0.counter_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(20) O=cmd_serial_host0.counter_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=cmd_serial_host0.counter(19) D=cmd_serial_host0.counter_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=cmd_serial_host0.counter(18) D=cmd_serial_host0.counter_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_I2 I3=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(18) I3=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.counter(19) I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cmd_serial_host0.counter(17) D=cmd_serial_host0.counter_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(17) I2=cmd_serial_host0.counter_ff_CQZ_14_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(17) I3=cmd_serial_host0.counter_ff_CQZ_14_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2 I1=cmd_serial_host0.counter(14) I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.counter_ff_CQZ_14_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cmd_serial_host0.counter(16) D=cmd_serial_host0.counter_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_16_D_LUT4_O_I2 I1=cmd_serial_host0.counter(15) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.counter_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=cmd_serial_host0.counter(15) D=cmd_serial_host0.counter_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(15) I2=cmd_serial_host0.counter_ff_CQZ_16_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_19_D_LUT4_O_I2 I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.counter(13) I3=cmd_serial_host0.counter(14) O=cmd_serial_host0.counter_ff_CQZ_16_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cmd_serial_host0.counter(14) D=cmd_serial_host0.counter_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(14) I2=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.counter(9) O=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.counter(11) I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.counter(13) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.counter_ff_CQZ_17_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cmd_serial_host0.counter(13) D=cmd_serial_host0.counter_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_19_D_LUT4_O_I2 I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(13) O=cmd_serial_host0.counter_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=cmd_serial_host0.counter(12) D=cmd_serial_host0.counter_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.counter_ff_CQZ_19_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.counter(11) I3=cmd_serial_host0.counter_ff_CQZ_21_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_19_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(30) I2=cmd_serial_host0.counter_ff_CQZ_D_LUT4_O_I0 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=cmd_serial_host0.counter(29) D=cmd_serial_host0.counter_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.counter(11) D=cmd_serial_host0.counter_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_21_D_LUT4_O_I2 I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(11) O=cmd_serial_host0.counter_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=cmd_serial_host0.counter(10) D=cmd_serial_host0.counter_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.counter_ff_CQZ_21_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(9) I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_21_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.counter(9) D=cmd_serial_host0.counter_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(9) O=cmd_serial_host0.counter_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=cmd_serial_host0.counter(8) D=cmd_serial_host0.counter_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=cmd_serial_host0.counter(7) D=cmd_serial_host0.counter_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(7) I2=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2 I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I0_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000000100000000
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I0_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=cmd_serial_host0.counter(13) I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=cmd_serial_host0.counter(22) I3=cmd_serial_host0.counter(27) O=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(6) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_24_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.counter(6) D=cmd_serial_host0.counter_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.counter_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=cmd_serial_host0.counter(5) D=cmd_serial_host0.counter_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=cmd_serial_host0.counter(4) D=cmd_serial_host0.counter_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(4) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(4) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.counter(3) D=cmd_serial_host0.counter_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=cmd_serial_host0.counter(2) D=cmd_serial_host0.counter_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(2) I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_3_D_LUT4_O_I2 I1=cmd_serial_host0.counter(28) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(29) O=cmd_serial_host0.counter_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=cmd_serial_host0.counter(28) D=cmd_serial_host0.counter_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.counter(1) D=cmd_serial_host0.counter_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=cmd_serial_host0.counter(0) D=cmd_serial_host0.counter_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(28) I2=cmd_serial_host0.counter_ff_CQZ_3_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=cmd_serial_host0.counter(27) D=cmd_serial_host0.counter_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter_ff_CQZ_4_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(27) O=cmd_serial_host0.counter_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.counter_ff_CQZ_4_D_LUT4_O_I1 I3=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.counter(24) I1=cmd_serial_host0.counter(25) I2=cmd_serial_host0.counter(26) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.counter_ff_CQZ_4_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cmd_serial_host0.counter(26) D=cmd_serial_host0.counter_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_6_D_LUT4_O_I2 I1=cmd_serial_host0.counter(25) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(26) O=cmd_serial_host0.counter_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=cmd_serial_host0.counter(25) D=cmd_serial_host0.counter_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(25) I2=cmd_serial_host0.counter_ff_CQZ_6_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_9_D_LUT4_O_I2 I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.counter(24) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.counter_ff_CQZ_6_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cmd_serial_host0.counter(24) D=cmd_serial_host0.counter_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.counter(23) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(24) O=cmd_serial_host0.counter_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt ff CQZ=cmd_serial_host0.counter(23) D=cmd_serial_host0.counter_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(23) I2=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_O I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt ff CQZ=cmd_serial_host0.counter(22) D=cmd_serial_host0.counter_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.counter_ff_CQZ_9_D_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O O=cmd_serial_host0.counter_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_13_D_LUT4_O_I2_LUT4_I3_1_O I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.counter_ff_CQZ_9_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.counter_ff_CQZ_D_LUT4_O_I0 I1=cmd_serial_host0.counter(30) I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.counter(31) O=cmd_serial_host0.counter_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(29) I2=cmd_serial_host0.counter(28) I3=cmd_serial_host0.counter_ff_CQZ_3_D_LUT4_O_I2 O=cmd_serial_host0.counter_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.CRC_7.BITVAL D=cmd_serial_host0.crc_bit_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_bit_ff_CQZ_QEN QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=cmd_serial_host0.counter(1) I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111100010001
+.subckt LUT4 I0=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.counter_ff_CQZ_29_D_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(28) I3=cmd_serial_host0.cmd_buff(12) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_buff(20) I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.cmd_buff(36) I3=cmd_serial_host0.cmd_buff(4) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(3) I2=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(4) I2=cmd_serial_host0.cmd_buff(24) I3=cmd_serial_host0.cmd_buff(8) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.cmd_buff(16) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(0) I1=cmd_serial_host0.cmd_buff(32) I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.cmd_buff(23) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.cmd_buff(39) I3=cmd_serial_host0.cmd_buff(7) O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(15) I1=cmd_serial_host0.cmd_buff(31) I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.crc_bit_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_bit_ff_CQZ_QEN_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.crc_bit_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0 I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_I2_O O=cmd_serial_host0.crc_bit_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt ff CQZ=cmd_serial_host0.CRC_7.ENABLE D=cmd_serial_host0.crc_enable_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_enable_ff_CQZ_QEN QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_oe_o_ff_CQZ_D_LUT4_O_I1 I3=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I1=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(11) I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.resp_len(13) I3=cmd_serial_host0.resp_len(14) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cmd_serial_host0.resp_len(7) I1=cmd_serial_host0.resp_len(8) I2=cmd_serial_host0.resp_len(9) I3=cmd_serial_host0.resp_len(10) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cmd_serial_host0.resp_len(19) I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.resp_len(21) I3=cmd_serial_host0.resp_len(22) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cmd_serial_host0.resp_len(15) I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.resp_len(17) I3=cmd_serial_host0.resp_len(18) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(3) I1=cmd_serial_host0.resp_len(4) I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.resp_len(6) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(27) I1=cmd_serial_host0.resp_len(28) I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.resp_len(30) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cmd_serial_host0.resp_len(23) I1=cmd_serial_host0.resp_len(24) I2=cmd_serial_host0.resp_len(25) I3=cmd_serial_host0.resp_len(26) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cmd_serial_host0.resp_len(31) I1=cmd_serial_host0.resp_len(0) I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.resp_len(2) O=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_I2_O I2=cmd_serial_host0.crc_rst_ff_CQZ_D I3=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O O=cmd_serial_host0.crc_enable_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101011110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.counter(4) I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.counter(4) I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000000000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.counter(14) I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=cmd_serial_host0.counter(9) I1=cmd_serial_host0.counter(11) I2=cmd_serial_host0.counter(12) I3=cmd_serial_host0.counter(13) O=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=cmd_serial_host0.crc_in(6) D=cmd_serial_host0.crc_in_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.crc_in(5) D=cmd_serial_host0.crc_in_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(5) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2 O=cmd_serial_host0.crc_in_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011001100
+.subckt ff CQZ=cmd_serial_host0.crc_in(4) D=cmd_serial_host0.crc_in_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(4) I2=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt ff CQZ=cmd_serial_host0.crc_in(3) D=cmd_serial_host0.crc_in_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(3) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011001100
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I3=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(1) I1=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_in_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001100010000100
+.subckt ff CQZ=cmd_serial_host0.crc_in(2) D=cmd_serial_host0.crc_in_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(2) I2=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt ff CQZ=cmd_serial_host0.crc_in(1) D=cmd_serial_host0.crc_in_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(1) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011001100
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I3=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=cmd_serial_host0.resp_len(1) O=cmd_serial_host0.crc_in_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000000101100000
+.subckt ff CQZ=cmd_serial_host0.crc_in(0) D=cmd_serial_host0.crc_in_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1 I2=cmd_serial_host0.crc_in(0) I3=cmd_serial_host0.cmd_dat_reg O=cmd_serial_host0.crc_in_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110011001010
+.subckt LUT4 I0=cmd_serial_host0.counter(2) I1=cmd_serial_host0.resp_len(2) I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=cmd_serial_host0.counter(0) I1=cmd_serial_host0.resp_len(0) I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(1) I2=cmd_serial_host0.resp_len(0) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(0) I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I3 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(3) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.resp_len(2) I1=cmd_serial_host0.counter(3) I2=cmd_serial_host0.resp_len(3) I3=cmd_serial_host0.counter(2) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(7) I3=cmd_serial_host0.counter(7) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3_LUT4_O_I3 I1=cmd_serial_host0.resp_len(8) I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011100010000
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I0 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I2_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_O I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I3_O I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=cmd_serial_host0.resp_len(2) I1=cmd_serial_host0.counter(2) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.resp_len(3) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.crc_in(6) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.resp_len(1) I2=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100011000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(2) I3=cmd_serial_host0.counter(2) O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.resp_len(0) O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(0) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.crc_ok_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.crc_ok D=cmd_serial_host0.crc_ok_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(0) I1=cmd_serial_host0.crc_in(0) I2=cmd_serial_host0.CRC_7.CRC(5) I3=cmd_serial_host0.crc_in(5) O=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(2) I1=cmd_serial_host0.crc_in(2) I2=cmd_serial_host0.CRC_7.CRC(6) I3=cmd_serial_host0.crc_in(6) O=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_in(4) I3=cmd_serial_host0.CRC_7.CRC(4) O=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=cmd_serial_host0.CRC_7.CRC(3) I1=cmd_serial_host0.crc_in(3) I2=cmd_serial_host0.crc_in(1) I3=cmd_serial_host0.CRC_7.CRC(1) O=cmd_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.resp_len(22) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100111100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(23) I3=cmd_serial_host0.resp_len(23) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0 I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011100010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(20) I2=cmd_serial_host0.resp_len(20) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(19) I3=cmd_serial_host0.counter(19) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(20) I3=cmd_serial_host0.counter(20) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101111110100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O_LUT4_I3_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(19) I1=cmd_serial_host0.resp_len(18) I2=cmd_serial_host0.counter(19) I3=cmd_serial_host0.counter(18) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(20) I3=cmd_serial_host0.resp_len(20) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(23) I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.counter(23) I3=cmd_serial_host0.counter(22) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=cmd_serial_host0.resp_len(21) I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.counter(21) I3=cmd_serial_host0.counter(20) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(20) I3=cmd_serial_host0.counter(20) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101111010111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.resp_len(19) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(18) I2=cmd_serial_host0.counter(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(21) I3=cmd_serial_host0.resp_len(21) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.counter(14) I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100111100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.resp_len(15) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(13) I3=cmd_serial_host0.counter(13) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.counter(12) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101101111110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(13) I3=cmd_serial_host0.resp_len(13) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(11) I3=cmd_serial_host0.counter(11) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.counter(24) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101101111110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(25) I3=cmd_serial_host0.resp_len(25) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(25) I1=cmd_serial_host0.resp_len(24) I2=cmd_serial_host0.counter(25) I3=cmd_serial_host0.counter(24) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(24) I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.counter(12) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011100010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.counter(14) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=cmd_serial_host0.resp_len(14) I2=cmd_serial_host0.counter(14) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011100010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=cmd_serial_host0.counter(15) I1=cmd_serial_host0.resp_len(15) I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1 I2=cmd_serial_host0.counter(16) I3=cmd_serial_host0.resp_len(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100011101110
+.subckt LUT4 I0=cmd_serial_host0.counter(15) I1=cmd_serial_host0.resp_len(15) I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(17) I3=cmd_serial_host0.counter(17) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2_LUT4_O_I3 I1=cmd_serial_host0.resp_len(18) I2=cmd_serial_host0.counter(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011100010000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0_LUT4_I0_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I0_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I0_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_I0_LUT4_I0_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I0_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.counter(18) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(19) I3=cmd_serial_host0.resp_len(19) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.counter(22) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.resp_len(27) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(26) I3=cmd_serial_host0.counter(26) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.counter(27) I1=cmd_serial_host0.resp_len(27) I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O_LUT4_I1_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I0_O_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=cmd_serial_host0.counter(22) I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000011111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(22) I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(21) I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(24) I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.counter(24) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I0 I1=cmd_serial_host0.resp_len(24) I2=cmd_serial_host0.counter(24) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011100010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(24) I2=cmd_serial_host0.resp_len(24) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(23) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_I2_I3 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=cmd_serial_host0.counter(25) I1=cmd_serial_host0.resp_len(25) I2=cmd_serial_host0.resp_len(26) I3=cmd_serial_host0.counter(26) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110110000
+.subckt LUT4 I0=cmd_serial_host0.counter(25) I1=cmd_serial_host0.resp_len(25) I2=cmd_serial_host0.resp_len(26) I3=cmd_serial_host0.counter(26) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.resp_len(18) I2=cmd_serial_host0.counter(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(17) I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.counter(17) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101101111110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=cmd_serial_host0.counter(10) I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000011111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.counter(12) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0_LUT4_O_I0_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I0_I3 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O_LUT4_I3_1_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I0_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_1_O_LUT4_I3_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010010000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(9) I3=cmd_serial_host0.counter(9) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000000000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(8) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101111010111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(3) I2=cmd_serial_host0.resp_len(3) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=cmd_serial_host0.counter(14) I1=cmd_serial_host0.resp_len(14) I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(3) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(7) I1=cmd_serial_host0.resp_len(6) I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=cmd_serial_host0.counter(5) I1=cmd_serial_host0.resp_len(5) I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(6) I3=cmd_serial_host0.resp_len(6) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3 I2=cmd_serial_host0.resp_len(6) I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=cmd_serial_host0.counter(6) I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I2=cmd_serial_host0.resp_len(6) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I2_O_LUT4_I0_1_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000011111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.resp_len(7) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I3 I1=cmd_serial_host0.resp_len(26) I2=cmd_serial_host0.counter(26) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(3) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.crc_in_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=cmd_serial_host0.resp_len(27) I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.resp_len(1) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.counter(29) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001100110010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I0 I1=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=cmd_serial_host0.counter(30) I1=cmd_serial_host0.resp_len(30) I2=cmd_serial_host0.resp_len(31) I3=cmd_serial_host0.counter(31) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I1_1_O_LUT4_I0_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(30) I3=cmd_serial_host0.resp_len(30) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=cmd_serial_host0.counter(27) I3=cmd_serial_host0.resp_len(27) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100110010000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_I0_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I1 I2=cmd_serial_host0.resp_len(27) I3=cmd_serial_host0.counter(27) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I3 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I1_O_LUT4_I2_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 I1=cmd_serial_host0.resp_len(8) I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(28) I3=cmd_serial_host0.resp_len(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(29) I3=cmd_serial_host0.resp_len(29) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.resp_len(27) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(26) I2=cmd_serial_host0.counter(26) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=cmd_serial_host0.resp_len(29) I1=cmd_serial_host0.resp_len(28) I2=cmd_serial_host0.counter(29) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101111010111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(31) I3=cmd_serial_host0.resp_len(31) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(30) I2=cmd_serial_host0.resp_len(30) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.resp_len(31) I1=cmd_serial_host0.counter(31) I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000100010
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111111111111
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_O I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000000000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(9) I3=cmd_serial_host0.resp_len(9) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(13) I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.counter(13) I3=cmd_serial_host0.counter(12) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=cmd_serial_host0.resp_len(15) I1=cmd_serial_host0.resp_len(14) I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.counter(14) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0 I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(9) I1=cmd_serial_host0.resp_len(8) I2=cmd_serial_host0.counter(9) I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=cmd_serial_host0.resp_len(11) I1=cmd_serial_host0.resp_len(10) I2=cmd_serial_host0.counter(11) I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(10) I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(11) I3=cmd_serial_host0.resp_len(11) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(12) I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(14) I3=cmd_serial_host0.resp_len(14) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_I2_O O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(16) I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(17) I3=cmd_serial_host0.resp_len(17) O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt ff CQZ=cmd_serial_host0.crc_ok_o D=cmd_serial_host0.crc_ok_LUT4_I2_O QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.CRC_7.CLEAR D=cmd_serial_host0.crc_rst_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_rst_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=cmd_serial_host0.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_I3_O I3=cmd_serial_host0.crc_rst_ff_CQZ_D O=cmd_serial_host0.crc_rst_ff_CQZ_D_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_I2_O I3=cmd_serial_host0.crc_rst_ff_CQZ_D O=cmd_serial_host0.crc_rst_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=cmd_serial_host0.finish_o D=cmd_serial_host0.finish_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_5_I3 I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.finish_o_ff_CQZ_D O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_5_I3 I3=cmd_serial_host0.finish_o_ff_CQZ_D O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_3_I2 I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O O=cmd_serial_host0.crc_rst_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=cmd_serial_host0.state(4) I1=cmd_serial_host0.state(5) I2=cmd_serial_host0.state(6) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.finish_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=cmd_serial_host0.state(6) I1=cmd_serial_host0.state(4) I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.state(5) O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=cmd_serial_host0.state(5) I1=cmd_serial_host0.state(6) I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.state(4) O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1 I2=cmd_serial_host0.state(2) I3=cmd_serial_host0.state(3) O=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=cmd_serial_host0.index_ok_o D=cmd_serial_host0.index_ok_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O I1=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I2 I3=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I3 O=cmd_serial_host0.index_ok_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(34) I1=cmd_serial_host0.resp_buff(122) I2=cmd_serial_host0.cmd_buff(37) I3=cmd_serial_host0.resp_buff(125) O=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(33) I1=cmd_serial_host0.resp_buff(121) I2=cmd_serial_host0.cmd_buff(36) I3=cmd_serial_host0.resp_buff(124) O=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(32) I1=cmd_serial_host0.resp_buff(120) I2=cmd_serial_host0.cmd_buff(35) I3=cmd_serial_host0.resp_buff(123) O=cmd_serial_host0.index_ok_o_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I2=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.with_response O=cmd_serial_host0.next_state(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.counter(31) I1=cmd_serial_host0.next_state_LUT4_O_1_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0 I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.next_state(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(31) I3=cmd_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(30) I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.next_state_LUT4_O_3_I2 O=cmd_serial_host0.next_state(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I1 I2=cmd_serial_host0.counter(30) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.counter(29) I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(28) I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(27) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.counter(26) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(26) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.resp_len(25) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.resp_len(23) I3=cmd_serial_host0.resp_len(24) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.counter(25) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011100010001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(25) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(24) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.resp_len(23) I3=cmd_serial_host0.resp_len(24) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000011111111
+.subckt LUT4 I0=cmd_serial_host0.counter(21) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_len(21) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(21) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.resp_len(19) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(17) I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.counter(20) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100011101110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(20) I2=cmd_serial_host0.resp_len(19) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.counter(15) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.counter(14) I3=cmd_serial_host0.resp_len(14) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cmd_serial_host0.counter(13) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=cmd_serial_host0.resp_len(13) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111101
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.counter(14) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.resp_len(10) I2=cmd_serial_host0.counter(11) I3=cmd_serial_host0.resp_len(11) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cmd_serial_host0.counter(10) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111101
+.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(7) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.resp_len(9) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(9) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(7) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.counter(8) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=cmd_serial_host0.counter(7) I1=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=cmd_serial_host0.resp_len(7) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(7) I2=cmd_serial_host0.counter(8) I3=cmd_serial_host0.resp_len(8) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(6) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cmd_serial_host0.resp_len(3) I1=cmd_serial_host0.resp_len(4) I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.counter(5) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(3) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.crc_in_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(4) I3=cmd_serial_host0.resp_len(3) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=cmd_serial_host0.resp_len(3) I1=cmd_serial_host0.resp_len(4) I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.resp_len(5) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cmd_serial_host0.resp_len(3) I1=cmd_serial_host0.resp_len(4) I2=cmd_serial_host0.resp_len(5) I3=cmd_serial_host0.resp_len(6) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(7) I2=cmd_serial_host0.resp_len(7) I3=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=cmd_serial_host0.crc_enable_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=cmd_serial_host0.resp_len(7) I2=cmd_serial_host0.resp_len(8) I3=cmd_serial_host0.resp_len(9) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(10) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=cmd_serial_host0.counter(10) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.counter(12) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_len(12) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.resp_len(15) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(11) I2=cmd_serial_host0.resp_len(10) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.resp_len(10) I2=cmd_serial_host0.resp_len(11) I3=cmd_serial_host0.counter(11) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=cmd_serial_host0.counter(13) I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(12) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=cmd_serial_host0.counter(12) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(13) I2=cmd_serial_host0.resp_len(14) I3=cmd_serial_host0.resp_len(15) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=cmd_serial_host0.counter(16) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.counter(16) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_len(16) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111101
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.resp_len(17) I3=cmd_serial_host0.counter(17) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.resp_len(16) I2=cmd_serial_host0.counter(17) I3=cmd_serial_host0.resp_len(17) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.counter(18) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010010000001
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.counter(19) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I3=cmd_serial_host0.resp_len(19) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(18) I2=cmd_serial_host0.resp_len(18) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=cmd_serial_host0.counter(22) I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(21) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=cmd_serial_host0.counter(21) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=cmd_serial_host0.counter(22) I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=cmd_serial_host0.resp_len(22) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111101
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.resp_len(23) I3=cmd_serial_host0.counter(23) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(24) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=cmd_serial_host0.resp_len(22) I2=cmd_serial_host0.counter(23) I3=cmd_serial_host0.resp_len(23) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(27) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_len(27) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(26) I2=cmd_serial_host0.resp_len(25) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=cmd_serial_host0.resp_len(29) I2=cmd_serial_host0.counter(29) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I2=cmd_serial_host0.resp_len(28) I3=cmd_serial_host0.counter(28) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(27) I2=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.counter(27) O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_len(30) I2=cmd_serial_host0.resp_len(29) I3=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(31) I2=cmd_serial_host0.resp_len(31) I3=cmd_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.counter(31) I3=cmd_serial_host0.next_state_LUT4_O_1_I1 O=cmd_serial_host0.next_state_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_3_I1 I2=cmd_serial_host0.next_state_LUT4_O_3_I2 I3=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O O=cmd_serial_host0.next_state(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=cmd_serial_host0.state(2) I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1 I2=cmd_serial_host0.state(3) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cmd_serial_host0.state(3) I1=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1 I2=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 I3=cmd_serial_host0.state(2) O=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.state(1) I3=cmd_serial_host0.state(0) O=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_4_I1 I2=cmd_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_I1_O I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O O=cmd_serial_host0.next_state(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_4_I1 I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.state(0) I1=cmd_serial_host0.state(3) I2=cmd_serial_host0.state(2) I3=cmd_serial_host0.state(1) O=cmd_serial_host0.next_state_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.start_i I3=cmd_serial_host0.next_state_LUT4_O_5_I3 O=cmd_serial_host0.next_state(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_5_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_5_I3 I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.state(3) I1=cmd_serial_host0.state(1) I2=cmd_serial_host0.state(2) I3=cmd_serial_host0.state(0) O=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1 I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_I3_1_O I3=cmd_serial_host0.next_state(1) O=cmd_serial_host0.next_state(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_QEN_LUT4_O_I3 I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.counter(31) I3=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(31) I2=cmd_serial_host0.counter(3) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=cmd_serial_host0.counter(4) I1=cmd_serial_host0.counter(5) I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(31) I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=cmd_serial_host0.counter(5) I3=cmd_serial_host0.counter(4) O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(7) I3=cmd_serial_host0.counter(6) O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(3) I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 O=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt ff CQZ=cmd_serial_host0.resp_buff(125) D=cmd_serial_host0.resp_buff_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(124) D=cmd_serial_host0.resp_buff_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(115) D=cmd_serial_host0.resp_buff_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(25) D=cmd_serial_host0.resp_buff_ff_CQZ_100_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(25) I2=cmd_serial_host0.resp_buff_ff_CQZ_100_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_100_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_100_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(24) D=cmd_serial_host0.resp_buff_ff_CQZ_101_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(24) I3=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_101_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(23) D=cmd_serial_host0.resp_buff_ff_CQZ_102_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(23) I3=cmd_serial_host0.resp_buff_ff_CQZ_102_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_102_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(23) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_102_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(22) D=cmd_serial_host0.resp_buff_ff_CQZ_103_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(22) I2=cmd_serial_host0.resp_buff_ff_CQZ_103_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_103_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_103_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(21) D=cmd_serial_host0.resp_buff_ff_CQZ_104_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(21) I3=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_104_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_104_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(20) D=cmd_serial_host0.resp_buff_ff_CQZ_105_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(20) I2=cmd_serial_host0.resp_buff_ff_CQZ_105_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_105_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_105_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(19) D=cmd_serial_host0.resp_buff_ff_CQZ_106_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(19) I3=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_106_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(19) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(18) D=cmd_serial_host0.resp_buff_ff_CQZ_107_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(18) I2=cmd_serial_host0.resp_buff_ff_CQZ_107_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_107_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_107_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(17) D=cmd_serial_host0.resp_buff_ff_CQZ_108_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(17) I2=cmd_serial_host0.resp_buff_ff_CQZ_108_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_108_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_106_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_108_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(16) D=cmd_serial_host0.resp_buff_ff_CQZ_109_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(16) I3=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_109_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_buff(115) I3=cmd_serial_host0.resp_buff_ff_CQZ_10_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(115) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(114) D=cmd_serial_host0.resp_buff_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(15) D=cmd_serial_host0.resp_buff_ff_CQZ_110_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(15) I3=cmd_serial_host0.resp_buff_ff_CQZ_110_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_110_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(15) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_110_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(14) D=cmd_serial_host0.resp_buff_ff_CQZ_111_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(14) I2=cmd_serial_host0.resp_buff_ff_CQZ_111_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_111_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_111_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(13) D=cmd_serial_host0.resp_buff_ff_CQZ_112_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(13) I3=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_112_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_112_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(12) D=cmd_serial_host0.resp_buff_ff_CQZ_113_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(12) I2=cmd_serial_host0.resp_buff_ff_CQZ_113_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_113_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_113_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(11) D=cmd_serial_host0.resp_buff_ff_CQZ_114_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(11) I3=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_114_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(11) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(10) D=cmd_serial_host0.resp_buff_ff_CQZ_115_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(10) I2=cmd_serial_host0.resp_buff_ff_CQZ_115_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_115_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_115_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(9) D=cmd_serial_host0.resp_buff_ff_CQZ_116_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(9) I2=cmd_serial_host0.resp_buff_ff_CQZ_116_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_116_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_114_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_116_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(8) D=cmd_serial_host0.resp_buff_ff_CQZ_117_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(8) I3=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_117_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(7) D=cmd_serial_host0.resp_buff_ff_CQZ_118_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(7) I3=cmd_serial_host0.resp_buff_ff_CQZ_118_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_118_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(7) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_118_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(6) D=cmd_serial_host0.resp_buff_ff_CQZ_119_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(6) I2=cmd_serial_host0.resp_buff_ff_CQZ_119_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_119_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_119_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(114) I2=cmd_serial_host0.resp_buff_ff_CQZ_11_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_11_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(113) D=cmd_serial_host0.resp_buff_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(5) D=cmd_serial_host0.resp_buff_ff_CQZ_120_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_120_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_120_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(4) D=cmd_serial_host0.resp_buff_ff_CQZ_121_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(4) I2=cmd_serial_host0.resp_buff_ff_CQZ_121_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_121_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_121_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(3) D=cmd_serial_host0.resp_buff_ff_CQZ_122_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_122_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(3) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(2) D=cmd_serial_host0.resp_buff_ff_CQZ_123_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(2) I2=cmd_serial_host0.resp_buff_ff_CQZ_123_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_123_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_123_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(1) D=cmd_serial_host0.resp_buff_ff_CQZ_124_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_124_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_124_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_122_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_124_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(0) D=cmd_serial_host0.resp_buff_ff_CQZ_125_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(0) I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(7) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O I1=cmd_serial_host0.resp_idx(7) I2=cmd_serial_host0.resp_idx(8) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=cmd_serial_host0.resp_idx(6) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=cmd_serial_host0.resp_idx(6) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100000000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_117_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_109_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_101_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(6) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(5) I2=cmd_serial_host0.resp_idx(4) I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0 I1=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(27) I3=cmd_serial_host0.resp_idx(31) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(30) I2=cmd_serial_host0.resp_idx(29) I3=cmd_serial_host0.resp_idx(28) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=cmd_serial_host0.resp_idx(9) I1=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(15) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(17) I3=cmd_serial_host0.resp_idx(16) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(20) I2=cmd_serial_host0.resp_idx(19) I3=cmd_serial_host0.resp_idx(18) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx(8) I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_idx(6) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(113) I2=cmd_serial_host0.resp_buff_ff_CQZ_12_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_12_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(112) D=cmd_serial_host0.resp_buff_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_buff(112) I3=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_idx(3) O=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(112) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(111) D=cmd_serial_host0.resp_buff_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(111) I3=cmd_serial_host0.resp_buff_ff_CQZ_14_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(111) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_14_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(110) D=cmd_serial_host0.resp_buff_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(110) I2=cmd_serial_host0.resp_buff_ff_CQZ_15_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_15_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(109) D=cmd_serial_host0.resp_buff_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(109) I3=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_16_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(108) D=cmd_serial_host0.resp_buff_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(108) I2=cmd_serial_host0.resp_buff_ff_CQZ_17_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_17_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(107) D=cmd_serial_host0.resp_buff_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(107) I3=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(107) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(106) D=cmd_serial_host0.resp_buff_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(106) I2=cmd_serial_host0.resp_buff_ff_CQZ_19_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_19_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(124) O=cmd_serial_host0.resp_buff_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010001000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1 I2=cmd_serial_host0.counter_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I2=cmd_serial_host0.cmd_buff(19) I3=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=cmd_serial_host0.cmd_buff(11) I1=cmd_serial_host0.cmd_buff(27) I2=cmd_serial_host0.counter(4) I3=cmd_serial_host0.counter(3) O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(1) I2=cmd_serial_host0.counter(0) I3=cmd_serial_host0.counter(2) O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(123) D=cmd_serial_host0.resp_buff_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(105) D=cmd_serial_host0.resp_buff_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(105) I2=cmd_serial_host0.resp_buff_ff_CQZ_20_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_18_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_20_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(104) D=cmd_serial_host0.resp_buff_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(104) I2=cmd_serial_host0.resp_buff_ff_CQZ_21_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_21_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(103) D=cmd_serial_host0.resp_buff_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_buff(103) I3=cmd_serial_host0.resp_buff_ff_CQZ_22_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(103) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_22_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(102) D=cmd_serial_host0.resp_buff_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(102) I2=cmd_serial_host0.resp_buff_ff_CQZ_23_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_23_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(101) D=cmd_serial_host0.resp_buff_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_buff(101) I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(3) I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt ff CQZ=cmd_serial_host0.resp_buff(100) D=cmd_serial_host0.resp_buff_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(100) I2=cmd_serial_host0.resp_buff_ff_CQZ_25_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_25_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(99) D=cmd_serial_host0.resp_buff_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_buff(99) I3=cmd_serial_host0.resp_buff_ff_CQZ_26_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(99) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_26_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(98) D=cmd_serial_host0.resp_buff_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(98) I2=cmd_serial_host0.resp_buff_ff_CQZ_27_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_27_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(97) D=cmd_serial_host0.resp_buff_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(97) I2=cmd_serial_host0.resp_buff_ff_CQZ_28_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_28_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(96) D=cmd_serial_host0.resp_buff_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(96) I3=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(123) I3=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.cmd_dat_reg O=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(123) I2=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I3=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt ff CQZ=cmd_serial_host0.resp_buff(122) D=cmd_serial_host0.resp_buff_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(95) D=cmd_serial_host0.resp_buff_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(95) I3=cmd_serial_host0.resp_buff_ff_CQZ_30_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(95) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_30_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(94) D=cmd_serial_host0.resp_buff_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(94) I2=cmd_serial_host0.resp_buff_ff_CQZ_31_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_31_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(93) D=cmd_serial_host0.resp_buff_ff_CQZ_32_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(93) I3=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_32_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_32_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(92) D=cmd_serial_host0.resp_buff_ff_CQZ_33_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(92) I2=cmd_serial_host0.resp_buff_ff_CQZ_33_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_33_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_33_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(91) D=cmd_serial_host0.resp_buff_ff_CQZ_34_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(91) I3=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_34_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_29_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(91) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(90) D=cmd_serial_host0.resp_buff_ff_CQZ_35_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(90) I2=cmd_serial_host0.resp_buff_ff_CQZ_35_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_35_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_35_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(89) D=cmd_serial_host0.resp_buff_ff_CQZ_36_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(89) I2=cmd_serial_host0.resp_buff_ff_CQZ_36_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_36_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_34_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_36_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(88) D=cmd_serial_host0.resp_buff_ff_CQZ_37_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(88) I3=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_37_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(87) D=cmd_serial_host0.resp_buff_ff_CQZ_38_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(87) I3=cmd_serial_host0.resp_buff_ff_CQZ_38_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_38_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(87) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_38_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(86) D=cmd_serial_host0.resp_buff_ff_CQZ_39_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(86) I2=cmd_serial_host0.resp_buff_ff_CQZ_39_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_39_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_39_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(122) O=cmd_serial_host0.resp_buff_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.CRC_7.CRC(1) I3=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.cmd_out_o_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.counter(0) I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.counter(1) O=cmd_serial_host0.resp_buff_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(121) D=cmd_serial_host0.resp_buff_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(85) D=cmd_serial_host0.resp_buff_ff_CQZ_40_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(85) I3=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_40_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_40_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(84) D=cmd_serial_host0.resp_buff_ff_CQZ_41_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(84) I2=cmd_serial_host0.resp_buff_ff_CQZ_41_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_41_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_41_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(83) D=cmd_serial_host0.resp_buff_ff_CQZ_42_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(83) I3=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_42_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_37_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(83) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(82) D=cmd_serial_host0.resp_buff_ff_CQZ_43_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(82) I2=cmd_serial_host0.resp_buff_ff_CQZ_43_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_43_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_43_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(81) D=cmd_serial_host0.resp_buff_ff_CQZ_44_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(81) I2=cmd_serial_host0.resp_buff_ff_CQZ_44_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_44_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_42_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_44_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(80) D=cmd_serial_host0.resp_buff_ff_CQZ_45_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(80) I3=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_45_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(79) D=cmd_serial_host0.resp_buff_ff_CQZ_46_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(79) I3=cmd_serial_host0.resp_buff_ff_CQZ_46_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_46_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(79) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_46_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(78) D=cmd_serial_host0.resp_buff_ff_CQZ_47_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(78) I2=cmd_serial_host0.resp_buff_ff_CQZ_47_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_47_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_47_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(77) D=cmd_serial_host0.resp_buff_ff_CQZ_48_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(77) I3=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_48_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_48_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(76) D=cmd_serial_host0.resp_buff_ff_CQZ_49_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(76) I2=cmd_serial_host0.resp_buff_ff_CQZ_49_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_49_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_49_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(121) O=cmd_serial_host0.resp_buff_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0 I1=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(2) I3=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.counter(1) I3=cmd_serial_host0.counter(0) O=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(120) D=cmd_serial_host0.resp_buff_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(75) D=cmd_serial_host0.resp_buff_ff_CQZ_50_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(75) I3=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_50_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_45_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(75) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(74) D=cmd_serial_host0.resp_buff_ff_CQZ_51_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(74) I2=cmd_serial_host0.resp_buff_ff_CQZ_51_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_51_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_51_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(73) D=cmd_serial_host0.resp_buff_ff_CQZ_52_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(73) I2=cmd_serial_host0.resp_buff_ff_CQZ_52_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_52_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_50_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_52_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(72) D=cmd_serial_host0.resp_buff_ff_CQZ_53_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(72) I3=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_53_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(71) D=cmd_serial_host0.resp_buff_ff_CQZ_54_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(71) I3=cmd_serial_host0.resp_buff_ff_CQZ_54_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_54_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(71) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_54_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(70) D=cmd_serial_host0.resp_buff_ff_CQZ_55_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(70) I2=cmd_serial_host0.resp_buff_ff_CQZ_55_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_55_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_55_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(69) D=cmd_serial_host0.resp_buff_ff_CQZ_56_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(69) I3=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_56_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_56_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(68) D=cmd_serial_host0.resp_buff_ff_CQZ_57_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(68) I2=cmd_serial_host0.resp_buff_ff_CQZ_57_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_57_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_57_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(67) D=cmd_serial_host0.resp_buff_ff_CQZ_58_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(67) I3=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_58_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_53_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(67) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(66) D=cmd_serial_host0.resp_buff_ff_CQZ_59_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(66) I2=cmd_serial_host0.resp_buff_ff_CQZ_59_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_59_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_59_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_5_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(120) O=cmd_serial_host0.resp_buff_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=cmd_serial_host0.counter(31) I1=cmd_serial_host0.counter_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.resp_buff_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(119) D=cmd_serial_host0.resp_buff_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(65) D=cmd_serial_host0.resp_buff_ff_CQZ_60_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(65) I2=cmd_serial_host0.resp_buff_ff_CQZ_60_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_60_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_58_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_60_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(64) D=cmd_serial_host0.resp_buff_ff_CQZ_61_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(64) I3=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_61_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(63) D=cmd_serial_host0.resp_buff_ff_CQZ_62_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(63) I3=cmd_serial_host0.resp_buff_ff_CQZ_62_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_62_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(63) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_62_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(62) D=cmd_serial_host0.resp_buff_ff_CQZ_63_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(62) I2=cmd_serial_host0.resp_buff_ff_CQZ_63_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_63_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_63_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(61) D=cmd_serial_host0.resp_buff_ff_CQZ_64_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(61) I3=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_64_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_64_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(60) D=cmd_serial_host0.resp_buff_ff_CQZ_65_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(60) I2=cmd_serial_host0.resp_buff_ff_CQZ_65_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_65_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_65_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(59) D=cmd_serial_host0.resp_buff_ff_CQZ_66_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(59) I3=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_66_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_61_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(59) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(58) D=cmd_serial_host0.resp_buff_ff_CQZ_67_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(58) I2=cmd_serial_host0.resp_buff_ff_CQZ_67_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_67_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_67_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(57) D=cmd_serial_host0.resp_buff_ff_CQZ_68_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(57) I2=cmd_serial_host0.resp_buff_ff_CQZ_68_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_68_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_66_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_68_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(56) D=cmd_serial_host0.resp_buff_ff_CQZ_69_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(56) I3=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_69_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_6_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(119) I3=cmd_serial_host0.cmd_dat_reg O=cmd_serial_host0.resp_buff_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(118) D=cmd_serial_host0.resp_buff_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(55) D=cmd_serial_host0.resp_buff_ff_CQZ_70_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(55) I3=cmd_serial_host0.resp_buff_ff_CQZ_70_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_70_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(55) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_70_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(54) D=cmd_serial_host0.resp_buff_ff_CQZ_71_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(54) I2=cmd_serial_host0.resp_buff_ff_CQZ_71_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_71_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_71_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(53) D=cmd_serial_host0.resp_buff_ff_CQZ_72_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(53) I3=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_72_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_72_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(52) D=cmd_serial_host0.resp_buff_ff_CQZ_73_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(52) I2=cmd_serial_host0.resp_buff_ff_CQZ_73_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_73_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_73_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(51) D=cmd_serial_host0.resp_buff_ff_CQZ_74_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(51) I3=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_74_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_69_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(51) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(50) D=cmd_serial_host0.resp_buff_ff_CQZ_75_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(50) I2=cmd_serial_host0.resp_buff_ff_CQZ_75_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_75_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_75_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(49) D=cmd_serial_host0.resp_buff_ff_CQZ_76_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(49) I2=cmd_serial_host0.resp_buff_ff_CQZ_76_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_76_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_74_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_76_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(48) D=cmd_serial_host0.resp_buff_ff_CQZ_77_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(48) I3=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_77_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(47) D=cmd_serial_host0.resp_buff_ff_CQZ_78_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(47) I3=cmd_serial_host0.resp_buff_ff_CQZ_78_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_78_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(47) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_78_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(46) D=cmd_serial_host0.resp_buff_ff_CQZ_79_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(46) I2=cmd_serial_host0.resp_buff_ff_CQZ_79_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_79_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_79_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(118) I2=cmd_serial_host0.resp_buff_ff_CQZ_7_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_7_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(117) D=cmd_serial_host0.resp_buff_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(45) D=cmd_serial_host0.resp_buff_ff_CQZ_80_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(45) I3=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_80_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_80_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(44) D=cmd_serial_host0.resp_buff_ff_CQZ_81_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(44) I2=cmd_serial_host0.resp_buff_ff_CQZ_81_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_81_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_81_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(43) D=cmd_serial_host0.resp_buff_ff_CQZ_82_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(43) I3=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_82_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_77_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(43) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(42) D=cmd_serial_host0.resp_buff_ff_CQZ_83_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(42) I2=cmd_serial_host0.resp_buff_ff_CQZ_83_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_83_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_83_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(41) D=cmd_serial_host0.resp_buff_ff_CQZ_84_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(41) I2=cmd_serial_host0.resp_buff_ff_CQZ_84_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_84_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_82_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_84_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(40) D=cmd_serial_host0.resp_buff_ff_CQZ_85_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(40) I3=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_85_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_O_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(39) D=cmd_serial_host0.resp_buff_ff_CQZ_86_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(39) I3=cmd_serial_host0.resp_buff_ff_CQZ_86_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_86_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(39) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_86_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(38) D=cmd_serial_host0.resp_buff_ff_CQZ_87_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(38) I2=cmd_serial_host0.resp_buff_ff_CQZ_87_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_87_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_87_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(37) D=cmd_serial_host0.resp_buff_ff_CQZ_88_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(37) I3=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_88_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_88_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(36) D=cmd_serial_host0.resp_buff_ff_CQZ_89_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(36) I2=cmd_serial_host0.resp_buff_ff_CQZ_89_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_89_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_89_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(117) I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(3) O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(4) I3=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101100000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(116) D=cmd_serial_host0.resp_buff_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_buff(35) D=cmd_serial_host0.resp_buff_ff_CQZ_90_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(35) I3=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_90_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_85_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(35) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(34) D=cmd_serial_host0.resp_buff_ff_CQZ_91_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(34) I2=cmd_serial_host0.resp_buff_ff_CQZ_91_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_91_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_91_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(33) D=cmd_serial_host0.resp_buff_ff_CQZ_92_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(33) I2=cmd_serial_host0.resp_buff_ff_CQZ_92_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_92_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(1) I2=cmd_serial_host0.resp_buff_ff_CQZ_90_D_LUT4_O_I1 I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_92_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(32) D=cmd_serial_host0.resp_buff_ff_CQZ_93_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(32) I3=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_93_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_13_D_LUT4_O_I0 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_1_O_LUT4_I3_1_O_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(31) D=cmd_serial_host0.resp_buff_ff_CQZ_94_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(31) I3=cmd_serial_host0.resp_buff_ff_CQZ_94_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_94_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(31) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_94_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(30) D=cmd_serial_host0.resp_buff_ff_CQZ_95_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(30) I2=cmd_serial_host0.resp_buff_ff_CQZ_95_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_95_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_95_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(29) D=cmd_serial_host0.resp_buff_ff_CQZ_96_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(29) I3=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_96_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0 I3=cmd_serial_host0.resp_idx(2) O=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_96_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(28) D=cmd_serial_host0.resp_buff_ff_CQZ_97_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(28) I2=cmd_serial_host0.resp_buff_ff_CQZ_97_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_97_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 O=cmd_serial_host0.resp_buff_ff_CQZ_97_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(27) D=cmd_serial_host0.resp_buff_ff_CQZ_98_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(27) I3=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_98_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(1) I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_93_D_LUT4_O_I0 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1 I2=cmd_serial_host0.resp_buff(27) I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I0 O=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_buff(26) D=cmd_serial_host0.resp_buff_ff_CQZ_99_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(26) I2=cmd_serial_host0.resp_buff_ff_CQZ_99_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_99_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_98_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(0) I3=cmd_serial_host0.resp_idx(1) O=cmd_serial_host0.resp_buff_ff_CQZ_99_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.cmd_dat_reg I1=cmd_serial_host0.resp_buff(116) I2=cmd_serial_host0.resp_buff_ff_CQZ_9_D_LUT4_O_I2 I3=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_buff_ff_CQZ_9_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.resp_buff(125) O=cmd_serial_host0.resp_buff_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I1 I3=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_buff_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.crc_enable_ff_CQZ_QEN_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=cmd_serial_host0.counter(2) O=cmd_serial_host0.resp_buff_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=cmd_serial_host0.resp_idx(31) D=cmd_serial_host0.resp_idx_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_idx(30) D=cmd_serial_host0.resp_idx_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_idx(21) D=cmd_serial_host0.resp_idx_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(21) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(20) D=cmd_serial_host0.resp_idx_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(20) I3=cmd_serial_host0.resp_idx_ff_CQZ_11_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_idx(17) I2=cmd_serial_host0.resp_idx(18) I3=cmd_serial_host0.resp_idx(19) O=cmd_serial_host0.resp_idx_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(19) D=cmd_serial_host0.resp_idx_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.resp_idx_ff_CQZ_12_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_idx(17) I2=cmd_serial_host0.resp_idx(18) I3=cmd_serial_host0.resp_idx(19) O=cmd_serial_host0.resp_idx_ff_CQZ_12_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=cmd_serial_host0.resp_idx(18) D=cmd_serial_host0.resp_idx_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O I1=cmd_serial_host0.resp_idx(17) I2=cmd_serial_host0.resp_idx(18) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(17) D=cmd_serial_host0.resp_idx_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(17) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O O=cmd_serial_host0.resp_idx_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(16) D=cmd_serial_host0.resp_idx_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(15) I2=cmd_serial_host0.resp_idx(16) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(15) D=cmd_serial_host0.resp_idx_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(15) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(16) I2=cmd_serial_host0.resp_idx(15) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx(17) I1=cmd_serial_host0.resp_idx(18) I2=cmd_serial_host0.resp_idx(19) I3=cmd_serial_host0.resp_idx(20) O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(10) I2=cmd_serial_host0.resp_idx(9) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=cmd_serial_host0.resp_idx(15) I3=cmd_serial_host0.resp_idx(16) O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx(11) I1=cmd_serial_host0.resp_idx(12) I2=cmd_serial_host0.resp_idx(13) I3=cmd_serial_host0.resp_idx(14) O=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(14) D=cmd_serial_host0.resp_idx_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_18_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(13) I2=cmd_serial_host0.resp_idx(14) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(13) D=cmd_serial_host0.resp_idx_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(13) I3=cmd_serial_host0.resp_idx_ff_CQZ_18_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(12) I2=cmd_serial_host0.resp_idx(11) I3=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_18_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(12) D=cmd_serial_host0.resp_idx_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(11) I2=cmd_serial_host0.resp_idx(12) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I0 I1=cmd_serial_host0.resp_idx(29) I2=cmd_serial_host0.resp_idx(30) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(29) D=cmd_serial_host0.resp_idx_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_idx(11) D=cmd_serial_host0.resp_idx_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(11) I3=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(10) D=cmd_serial_host0.resp_idx_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O I1=cmd_serial_host0.resp_idx(9) I2=cmd_serial_host0.resp_idx(10) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(9) D=cmd_serial_host0.resp_idx_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(9) I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(8) D=cmd_serial_host0.resp_idx_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(7) I2=cmd_serial_host0.resp_idx(8) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(7) D=cmd_serial_host0.resp_idx_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(7) I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(8) I2=cmd_serial_host0.resp_idx(7) I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(10) I2=cmd_serial_host0.resp_idx(9) I3=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_20_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(6) D=cmd_serial_host0.resp_idx_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_25_D_LUT4_O_I0 I1=cmd_serial_host0.resp_idx(5) I2=cmd_serial_host0.resp_idx(6) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(6) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.resp_idx_ff_CQZ_25_D_LUT4_O_I0 O=cmd_serial_host0.resp_idx_ff_CQZ_24_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(4) I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_25_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(5) D=cmd_serial_host0.resp_idx_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(4) I2=cmd_serial_host0.resp_idx(5) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(4) D=cmd_serial_host0.resp_idx_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(4) I3=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_27_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(3) D=cmd_serial_host0.resp_idx_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(2) I2=cmd_serial_host0.resp_idx(3) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(2) D=cmd_serial_host0.resp_idx_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(2) I3=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(1) I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_idx_ff_CQZ_29_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(29) I3=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I0 O=cmd_serial_host0.resp_idx_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(28) D=cmd_serial_host0.resp_idx_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_idx(1) D=cmd_serial_host0.resp_idx_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(1) I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_idx_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(0) D=cmd_serial_host0.resp_idx_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.resp_idx(0) O=cmd_serial_host0.resp_idx_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(28) I3=cmd_serial_host0.resp_idx_ff_CQZ_3_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(28) I3=cmd_serial_host0.resp_idx_ff_CQZ_3_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(27) I3=cmd_serial_host0.resp_idx_ff_CQZ_4_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(27) D=cmd_serial_host0.resp_idx_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(27) I3=cmd_serial_host0.resp_idx_ff_CQZ_4_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(26) I3=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(26) D=cmd_serial_host0.resp_idx_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(26) I3=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0 I1=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1 I2=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(26) O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=cmd_serial_host0.resp_idx(15) O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O I1=cmd_serial_host0.resp_idx(7) I2=cmd_serial_host0.resp_idx(8) I3=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0 O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(8) I2=cmd_serial_host0.resp_idx(7) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(22) I2=cmd_serial_host0.resp_idx(21) I3=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(25) I2=cmd_serial_host0.resp_idx(24) I3=cmd_serial_host0.resp_idx(23) O=cmd_serial_host0.resp_idx_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(25) D=cmd_serial_host0.resp_idx_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I3=cmd_serial_host0.resp_idx_ff_CQZ_6_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_8_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(23) I2=cmd_serial_host0.resp_idx(24) I3=cmd_serial_host0.resp_idx(25) O=cmd_serial_host0.resp_idx_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=cmd_serial_host0.resp_idx(24) D=cmd_serial_host0.resp_idx_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_8_D_LUT4_O_I3 I1=cmd_serial_host0.resp_idx(23) I2=cmd_serial_host0.resp_idx(24) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(23) D=cmd_serial_host0.resp_idx_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O I2=cmd_serial_host0.resp_idx(23) I3=cmd_serial_host0.resp_idx_ff_CQZ_8_D_LUT4_O_I3 O=cmd_serial_host0.resp_idx_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(22) I2=cmd_serial_host0.resp_idx(21) I3=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_8_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=cmd_serial_host0.resp_idx(22) D=cmd_serial_host0.resp_idx_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I1_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_I3_O I1=cmd_serial_host0.resp_idx(21) I2=cmd_serial_host0.resp_idx(22) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I0 I1=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(31) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_1_O O=cmd_serial_host0.resp_idx_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1 I1=cmd_serial_host0.resp_idx(31) I2=cmd_serial_host0.resp_idx(27) I3=cmd_serial_host0.resp_idx(28) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O I1=cmd_serial_host0.resp_idx(21) I2=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_I2 I3=cmd_serial_host0.resp_idx(26) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101110110000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx(22) I1=cmd_serial_host0.resp_idx(23) I2=cmd_serial_host0.resp_idx(24) I3=cmd_serial_host0.resp_idx(25) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0 I1=cmd_serial_host0.resp_idx_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2 I2=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I2 I3=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O O=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0_LUT4_O_I1 I2=cmd_serial_host0.resp_idx(10) I3=cmd_serial_host0.resp_idx(9) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=cmd_serial_host0.resp_idx(11) I1=cmd_serial_host0.resp_idx(12) I2=cmd_serial_host0.resp_idx(13) I3=cmd_serial_host0.resp_idx(14) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.resp_idx(8) I2=cmd_serial_host0.resp_idx(7) I3=cmd_serial_host0.resp_buff_ff_CQZ_125_D_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_I3_LUT4_I3_O O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1_LUT4_I0_O_LUT4_I0_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_idx(30) I3=cmd_serial_host0.resp_idx(29) O=cmd_serial_host0.resp_idx_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_serial_host0.resp_len(31) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(30) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(21) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(20) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(19) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(18) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(17) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(16) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(15) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(14) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(13) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(12) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(29) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(11) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(10) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(9) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(8) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(7) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(6) D=sd_cmd_master0.long_response QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(5) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(4) D=sd_cmd_master0.long_response QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(3) D=sd_cmd_master0.long_response QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(28) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(27) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(26) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(25) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(24) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(23) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_serial_host0.resp_len(22) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(119) D=cmd_serial_host0.response_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(118) D=cmd_serial_host0.response_o_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(109) D=cmd_serial_host0.response_o_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(19) D=cmd_serial_host0.response_o_ff_CQZ_100_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(19) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_100_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(18) D=cmd_serial_host0.response_o_ff_CQZ_101_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(18) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_101_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(17) D=cmd_serial_host0.response_o_ff_CQZ_102_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(17) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_102_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(16) D=cmd_serial_host0.response_o_ff_CQZ_103_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(16) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_103_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(15) D=cmd_serial_host0.response_o_ff_CQZ_104_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(15) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_104_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(14) D=cmd_serial_host0.response_o_ff_CQZ_105_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(14) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_105_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(13) D=cmd_serial_host0.response_o_ff_CQZ_106_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(13) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_106_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(12) D=cmd_serial_host0.response_o_ff_CQZ_107_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(12) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_107_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(11) D=cmd_serial_host0.response_o_ff_CQZ_108_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(11) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_108_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(10) D=cmd_serial_host0.response_o_ff_CQZ_109_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(10) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_109_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(109) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(108) D=cmd_serial_host0.response_o_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(9) D=cmd_serial_host0.response_o_ff_CQZ_110_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(9) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_110_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(8) D=cmd_serial_host0.response_o_ff_CQZ_111_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(8) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_111_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(7) D=cmd_serial_host0.response_o_ff_CQZ_112_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(7) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_112_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(6) D=cmd_serial_host0.response_o_ff_CQZ_113_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(6) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_113_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(5) D=cmd_serial_host0.response_o_ff_CQZ_114_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(5) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_114_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(4) D=cmd_serial_host0.response_o_ff_CQZ_115_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(4) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_115_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(3) D=cmd_serial_host0.response_o_ff_CQZ_116_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(3) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_116_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(2) D=cmd_serial_host0.response_o_ff_CQZ_117_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(2) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_117_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(1) D=cmd_serial_host0.response_o_ff_CQZ_118_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(1) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_118_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(0) D=cmd_serial_host0.response_o_ff_CQZ_119_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(0) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_119_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(108) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(107) D=cmd_serial_host0.response_o_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(107) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(106) D=cmd_serial_host0.response_o_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(106) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(105) D=cmd_serial_host0.response_o_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(105) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(104) D=cmd_serial_host0.response_o_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(104) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(103) D=cmd_serial_host0.response_o_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(103) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(102) D=cmd_serial_host0.response_o_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(102) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(101) D=cmd_serial_host0.response_o_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(101) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(100) D=cmd_serial_host0.response_o_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(100) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(118) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(117) D=cmd_serial_host0.response_o_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(99) D=cmd_serial_host0.response_o_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(99) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(98) D=cmd_serial_host0.response_o_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(98) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(97) D=cmd_serial_host0.response_o_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(97) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(96) D=cmd_serial_host0.response_o_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(96) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(95) D=cmd_serial_host0.response_o_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(95) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(94) D=cmd_serial_host0.response_o_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(94) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(93) D=cmd_serial_host0.response_o_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(93) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(92) D=cmd_serial_host0.response_o_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(92) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(91) D=cmd_serial_host0.response_o_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(91) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(90) D=cmd_serial_host0.response_o_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(90) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(117) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(116) D=cmd_serial_host0.response_o_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(89) D=cmd_serial_host0.response_o_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(89) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(88) D=cmd_serial_host0.response_o_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(88) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(87) D=cmd_serial_host0.response_o_ff_CQZ_32_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(87) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_32_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(86) D=cmd_serial_host0.response_o_ff_CQZ_33_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(86) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_33_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(85) D=cmd_serial_host0.response_o_ff_CQZ_34_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(85) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_34_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(84) D=cmd_serial_host0.response_o_ff_CQZ_35_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(84) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_35_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(83) D=cmd_serial_host0.response_o_ff_CQZ_36_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(83) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_36_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(82) D=cmd_serial_host0.response_o_ff_CQZ_37_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(82) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_37_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(81) D=cmd_serial_host0.response_o_ff_CQZ_38_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(81) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_38_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(80) D=cmd_serial_host0.response_o_ff_CQZ_39_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(80) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_39_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(116) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(115) D=cmd_serial_host0.response_o_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(79) D=cmd_serial_host0.response_o_ff_CQZ_40_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(79) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_40_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(78) D=cmd_serial_host0.response_o_ff_CQZ_41_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(78) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_41_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(77) D=cmd_serial_host0.response_o_ff_CQZ_42_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(77) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_42_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(76) D=cmd_serial_host0.response_o_ff_CQZ_43_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(76) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_43_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(75) D=cmd_serial_host0.response_o_ff_CQZ_44_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(75) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_44_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(74) D=cmd_serial_host0.response_o_ff_CQZ_45_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(74) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_45_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(73) D=cmd_serial_host0.response_o_ff_CQZ_46_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(73) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_46_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(72) D=cmd_serial_host0.response_o_ff_CQZ_47_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(72) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_47_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(71) D=cmd_serial_host0.response_o_ff_CQZ_48_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(71) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_48_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(70) D=cmd_serial_host0.response_o_ff_CQZ_49_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(70) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_49_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(115) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(114) D=cmd_serial_host0.response_o_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(69) D=cmd_serial_host0.response_o_ff_CQZ_50_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(69) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_50_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(68) D=cmd_serial_host0.response_o_ff_CQZ_51_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(68) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_51_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(67) D=cmd_serial_host0.response_o_ff_CQZ_52_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(67) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_52_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(66) D=cmd_serial_host0.response_o_ff_CQZ_53_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(66) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_53_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(65) D=cmd_serial_host0.response_o_ff_CQZ_54_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(65) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_54_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(64) D=cmd_serial_host0.response_o_ff_CQZ_55_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(64) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_55_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(63) D=cmd_serial_host0.response_o_ff_CQZ_56_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(63) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_56_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(62) D=cmd_serial_host0.response_o_ff_CQZ_57_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(62) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_57_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(61) D=cmd_serial_host0.response_o_ff_CQZ_58_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(61) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_58_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(60) D=cmd_serial_host0.response_o_ff_CQZ_59_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(60) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_59_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(114) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(113) D=cmd_serial_host0.response_o_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(59) D=cmd_serial_host0.response_o_ff_CQZ_60_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(59) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_60_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(58) D=cmd_serial_host0.response_o_ff_CQZ_61_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(58) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_61_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(57) D=cmd_serial_host0.response_o_ff_CQZ_62_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(57) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_62_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(56) D=cmd_serial_host0.response_o_ff_CQZ_63_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(56) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_63_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(55) D=cmd_serial_host0.response_o_ff_CQZ_64_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(55) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_64_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(54) D=cmd_serial_host0.response_o_ff_CQZ_65_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(54) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_65_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(53) D=cmd_serial_host0.response_o_ff_CQZ_66_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(53) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_66_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(52) D=cmd_serial_host0.response_o_ff_CQZ_67_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(52) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_67_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(51) D=cmd_serial_host0.response_o_ff_CQZ_68_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(51) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_68_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(50) D=cmd_serial_host0.response_o_ff_CQZ_69_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(50) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_69_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(113) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(112) D=cmd_serial_host0.response_o_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(49) D=cmd_serial_host0.response_o_ff_CQZ_70_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(49) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_70_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(48) D=cmd_serial_host0.response_o_ff_CQZ_71_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(48) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_71_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(47) D=cmd_serial_host0.response_o_ff_CQZ_72_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(47) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_72_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(46) D=cmd_serial_host0.response_o_ff_CQZ_73_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(46) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_73_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(45) D=cmd_serial_host0.response_o_ff_CQZ_74_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(45) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_74_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(44) D=cmd_serial_host0.response_o_ff_CQZ_75_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(44) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_75_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(43) D=cmd_serial_host0.response_o_ff_CQZ_76_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(43) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_76_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(42) D=cmd_serial_host0.response_o_ff_CQZ_77_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(42) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_77_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(41) D=cmd_serial_host0.response_o_ff_CQZ_78_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(41) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_78_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(40) D=cmd_serial_host0.response_o_ff_CQZ_79_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(40) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_79_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(112) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(111) D=cmd_serial_host0.response_o_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(39) D=cmd_serial_host0.response_o_ff_CQZ_80_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(39) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_80_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(38) D=cmd_serial_host0.response_o_ff_CQZ_81_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(38) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_81_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(37) D=cmd_serial_host0.response_o_ff_CQZ_82_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(37) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_82_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(36) D=cmd_serial_host0.response_o_ff_CQZ_83_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(36) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_83_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(35) D=cmd_serial_host0.response_o_ff_CQZ_84_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(35) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_84_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(34) D=cmd_serial_host0.response_o_ff_CQZ_85_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(34) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_85_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(33) D=cmd_serial_host0.response_o_ff_CQZ_86_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(33) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_86_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(32) D=cmd_serial_host0.response_o_ff_CQZ_87_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(32) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_87_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(31) D=cmd_serial_host0.response_o_ff_CQZ_88_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(31) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_88_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(30) D=cmd_serial_host0.response_o_ff_CQZ_89_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(30) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_89_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(111) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(110) D=cmd_serial_host0.response_o_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_response(29) D=cmd_serial_host0.response_o_ff_CQZ_90_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(29) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_90_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(28) D=cmd_serial_host0.response_o_ff_CQZ_91_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(28) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_91_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(27) D=cmd_serial_host0.response_o_ff_CQZ_92_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(27) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_92_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(26) D=cmd_serial_host0.response_o_ff_CQZ_93_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(26) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_93_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(25) D=cmd_serial_host0.response_o_ff_CQZ_94_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(25) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_94_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(24) D=cmd_serial_host0.response_o_ff_CQZ_95_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(24) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_95_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(23) D=cmd_serial_host0.response_o_ff_CQZ_96_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(23) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_96_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(22) D=cmd_serial_host0.response_o_ff_CQZ_97_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(22) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_97_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(21) D=cmd_serial_host0.response_o_ff_CQZ_98_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(21) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_98_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_response(20) D=cmd_serial_host0.response_o_ff_CQZ_99_D QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.next_state_LUT4_O_5_I3_LUT4_I2_O QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:213.1-332.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(20) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_99_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(110) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=cmd_serial_host0.resp_buff(119) I3=cmd_serial_host0.finish_o_ff_CQZ_D_LUT4_O_I3_LUT4_I2_O O=cmd_serial_host0.response_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.go_idle_o I3=sd_cmd_master0.rst O=cmd_serial_host0.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cmd_serial_host0.state(6) D=cmd_serial_host0.next_state(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_serial_host0.state(5) D=cmd_serial_host0.next_state(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_serial_host0.state(4) D=cmd_serial_host0.next_state(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_serial_host0.state(3) D=cmd_serial_host0.next_state(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_serial_host0.state(2) D=cmd_serial_host0.next_state(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_serial_host0.state(1) D=cmd_serial_host0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_serial_host0.state(0) D=cmd_serial_host0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:202.1-210.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=cmd_serial_host0.next_state_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_I3_O I1=cmd_serial_host0.with_response I2=cmd_serial_host0.cmd_dat_reg I3=cmd_serial_host0.next_state_LUT4_O_3_I2 O=cmd_serial_host0.next_state_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt ff CQZ=cmd_serial_host0.with_response D=sd_cmd_master0.expect_response QCK=argument_reg_cross.clk_b QEN=cmd_serial_host0.start_i QRT=cmd_serial_host0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:238.20-251.21|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_serial_host.v:185.1-199.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_start_cross.sync_clk_b(2) D=cmd_start_cross.sync_clk_b(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:382.25-382.106|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_start_cross.sync_clk_b(1) D=cmd_start_cross.sync_clk_b(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:382.25-382.106|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_start_cross.sync_clk_b(0) D=cmd_start_cross.toggle_clk_a QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:382.25-382.106|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_start_cross.toggle_clk_a I2=cmd_start_edge.sig_reg(0) I3=cmd_start_edge.sig_reg(1) O=cmd_start_cross.toggle_clk_a_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt ff CQZ=cmd_start_cross.toggle_clk_a D=cmd_start_cross.toggle_clk_a_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:382.25-382.106|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:57.1-63.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_start_edge.sig_reg(1) D=cmd_start_edge.sig_reg(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:379.13-379.110|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=cmd_start_edge.sig_reg(0) D=cmd_start_edge.sig QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:379.13-379.110|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](13) D=command_reg_cross.in(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](12) D=command_reg_cross.in(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](2) D=command_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](1) D=command_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](0) D=command_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](11) D=command_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](10) D=command_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](9) D=command_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](8) D=command_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](6) D=command_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](5) D=command_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](4) D=command_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.sync_clk_b[0](3) D=command_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(13) D=command_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(12) D=command_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(2) D=command_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(1) D=command_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(0) D=command_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(11) D=command_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(10) D=command_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(9) D=command_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(8) D=command_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(6) D=command_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(5) D=command_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(4) D=command_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.out(3) D=command_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:386.29-386.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=controll_setting_reg_cross.sync_clk_b[0](0) D=controll_setting_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:394.29-394.143|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=data_int_rst_cross.sync_clk_b(1) I3=data_int_rst_cross.sync_clk_b(2) O=sd_data_master0.trans_done_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt ff CQZ=data_int_rst_cross.sync_clk_b(2) D=data_int_rst_cross.sync_clk_b(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:383.25-383.115|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_rst_cross.sync_clk_b(1) D=data_int_rst_cross.sync_clk_b(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:383.25-383.115|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_rst_cross.sync_clk_b(0) D=data_int_rst_cross.toggle_clk_a QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:383.25-383.115|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:67.1-73.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=data_int_rst_cross.toggle_clk_a I2=data_int_rst_edge.sig_reg(0) I3=data_int_rst_edge.sig_reg(1) O=data_int_rst_cross.toggle_clk_a_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt ff CQZ=data_int_rst_cross.toggle_clk_a D=data_int_rst_cross.toggle_clk_a_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:383.25-383.115|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/monostable_domain_cross.v:57.1-63.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_rst_edge.sig_reg(1) D=data_int_rst_edge.sig_reg(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:380.13-380.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_rst_edge.sig_reg(0) D=data_int_rst_edge.sig QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:380.13-380.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/edge_detect.v:55.1-59.38|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_status_reg_cross.sync_clk_b[0](2) D=data_int_status_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_status_reg_cross.sync_clk_b[0](1) D=data_int_status_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_status_reg_cross.sync_clk_b[0](0) D=data_int_status_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_status_reg_cross.out(2) D=data_int_status_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_status_reg_cross.out(1) D=data_int_status_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=data_int_status_reg_cross.out(0) D=data_int_status_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:400.28-400.139|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](31) D=dma_addr_reg_cross.in(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](30) D=dma_addr_reg_cross.in(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](21) D=dma_addr_reg_cross.in(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](20) D=dma_addr_reg_cross.in(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](19) D=dma_addr_reg_cross.in(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](18) D=dma_addr_reg_cross.in(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](17) D=dma_addr_reg_cross.in(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](16) D=dma_addr_reg_cross.in(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](15) D=dma_addr_reg_cross.in(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](14) D=dma_addr_reg_cross.in(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](13) D=dma_addr_reg_cross.in(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](12) D=dma_addr_reg_cross.in(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](29) D=dma_addr_reg_cross.in(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](11) D=dma_addr_reg_cross.in(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](10) D=dma_addr_reg_cross.in(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](9) D=dma_addr_reg_cross.in(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](8) D=dma_addr_reg_cross.in(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](7) D=dma_addr_reg_cross.in(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](6) D=dma_addr_reg_cross.in(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](5) D=dma_addr_reg_cross.in(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](4) D=dma_addr_reg_cross.in(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](3) D=dma_addr_reg_cross.in(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](2) D=dma_addr_reg_cross.in(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](28) D=dma_addr_reg_cross.in(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](1) D=dma_addr_reg_cross.in(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](0) D=dma_addr_reg_cross.in(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](27) D=dma_addr_reg_cross.in(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](26) D=dma_addr_reg_cross.in(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](25) D=dma_addr_reg_cross.in(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](24) D=dma_addr_reg_cross.in(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](23) D=dma_addr_reg_cross.in(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.sync_clk_b[0](22) D=dma_addr_reg_cross.in(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(31) D=dma_addr_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(30) D=dma_addr_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(21) D=dma_addr_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(20) D=dma_addr_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(19) D=dma_addr_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(18) D=dma_addr_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(17) D=dma_addr_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(16) D=dma_addr_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(15) D=dma_addr_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(14) D=dma_addr_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(13) D=dma_addr_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(12) D=dma_addr_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(29) D=dma_addr_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(11) D=dma_addr_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(10) D=dma_addr_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(9) D=dma_addr_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(8) D=dma_addr_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(7) D=dma_addr_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(6) D=dma_addr_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(5) D=dma_addr_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(4) D=dma_addr_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(3) D=dma_addr_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(2) D=dma_addr_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(28) D=dma_addr_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(1) D=dma_addr_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(0) D=dma_addr_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(27) D=dma_addr_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(26) D=dma_addr_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(25) D=dma_addr_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(24) D=dma_addr_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(23) D=dma_addr_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=dma_addr_reg_cross.out(22) D=dma_addr_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:399.29-399.119|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=cmd_int_status_reg_cross.out(0) I1=cmd_int_enable_reg_cross.in(0) I2=int_cmd_LUT4_O_I2 I3=int_cmd_LUT4_O_I3 O=$iopadmap$int_cmd
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111111
+.subckt LUT4 I0=cmd_int_status_reg_cross.out(1) I1=cmd_int_enable_reg_cross.in(1) I2=cmd_int_status_reg_cross.out(4) I3=cmd_int_enable_reg_cross.in(4) O=int_cmd_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=cmd_int_status_reg_cross.out(2) I1=cmd_int_enable_reg_cross.in(2) I2=cmd_int_status_reg_cross.out(3) I3=cmd_int_enable_reg_cross.in(3) O=int_cmd_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=int_data_LUT4_O_I1 I2=data_int_status_reg_cross.out(2) I3=data_int_enable_reg_cross.in(2) O=$iopadmap$int_data
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt LUT4 I0=data_int_status_reg_cross.out(0) I1=data_int_enable_reg_cross.in(0) I2=data_int_status_reg_cross.out(1) I3=data_int_enable_reg_cross.in(1) O=int_data_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.offset(0) I3=dma_addr_reg_cross.out(0) O=sd_fifo_filler0.wbm_adr_o(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_2_I3 I1=sd_fifo_filler0.offset(30) I2=dma_addr_reg_cross.out(30) I3=m_wb_adr_o_LUT4_O_1_I3 O=sd_fifo_filler0.wbm_adr_o(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_10_I0 I1=m_wb_adr_o_LUT4_O_10_I1 I2=sd_fifo_filler0.offset(22) I3=dma_addr_reg_cross.out(22) O=sd_fifo_filler0.wbm_adr_o(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_12_I3 I1=sd_fifo_filler0.offset(20) I2=dma_addr_reg_cross.out(20) I3=m_wb_adr_o_LUT4_O_10_I0_LUT4_O_I3 O=m_wb_adr_o_LUT4_O_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(21) I3=sd_fifo_filler0.offset(21) O=m_wb_adr_o_LUT4_O_10_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(21) I3=sd_fifo_filler0.offset(21) O=m_wb_adr_o_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(21) I2=sd_fifo_filler0.offset(21) I3=m_wb_adr_o_LUT4_O_11_I3 O=sd_fifo_filler0.wbm_adr_o(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(20) I2=sd_fifo_filler0.offset(20) I3=m_wb_adr_o_LUT4_O_12_I3 O=m_wb_adr_o_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(20) I2=sd_fifo_filler0.offset(20) I3=m_wb_adr_o_LUT4_O_12_I3 O=sd_fifo_filler0.wbm_adr_o(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_fifo_filler0.offset(19) I1=dma_addr_reg_cross.out(19) I2=m_wb_adr_o_LUT4_O_13_I0 I3=m_wb_adr_o_LUT4_O_13_I1 O=m_wb_adr_o_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_13_I0 I1=m_wb_adr_o_LUT4_O_13_I1 I2=sd_fifo_filler0.offset(19) I3=dma_addr_reg_cross.out(19) O=sd_fifo_filler0.wbm_adr_o(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_15_I3 I1=sd_fifo_filler0.offset(17) I2=dma_addr_reg_cross.out(17) I3=m_wb_adr_o_LUT4_O_14_I3 O=m_wb_adr_o_LUT4_O_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(18) I3=sd_fifo_filler0.offset(18) O=m_wb_adr_o_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_15_I3 I1=sd_fifo_filler0.offset(17) I2=dma_addr_reg_cross.out(17) I3=m_wb_adr_o_LUT4_O_14_I3 O=sd_fifo_filler0.wbm_adr_o(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(18) I3=sd_fifo_filler0.offset(18) O=m_wb_adr_o_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(17) I2=sd_fifo_filler0.offset(17) I3=m_wb_adr_o_LUT4_O_15_I3 O=sd_fifo_filler0.wbm_adr_o(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_fifo_filler0.offset(16) I1=dma_addr_reg_cross.out(16) I2=m_wb_adr_o_LUT4_O_16_I0 I3=m_wb_adr_o_LUT4_O_16_I1 O=m_wb_adr_o_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_16_I0 I1=m_wb_adr_o_LUT4_O_16_I1 I2=sd_fifo_filler0.offset(16) I3=dma_addr_reg_cross.out(16) O=sd_fifo_filler0.wbm_adr_o(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_18_I3 I1=sd_fifo_filler0.offset(14) I2=dma_addr_reg_cross.out(14) I3=m_wb_adr_o_LUT4_O_16_I0_LUT4_O_I3 O=m_wb_adr_o_LUT4_O_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(15) I3=sd_fifo_filler0.offset(15) O=m_wb_adr_o_LUT4_O_16_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(15) I3=sd_fifo_filler0.offset(15) O=m_wb_adr_o_LUT4_O_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(15) I2=sd_fifo_filler0.offset(15) I3=m_wb_adr_o_LUT4_O_17_I3 O=sd_fifo_filler0.wbm_adr_o(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(14) I2=sd_fifo_filler0.offset(14) I3=m_wb_adr_o_LUT4_O_18_I3 O=m_wb_adr_o_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(14) I2=sd_fifo_filler0.offset(14) I3=m_wb_adr_o_LUT4_O_18_I3 O=sd_fifo_filler0.wbm_adr_o(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_fifo_filler0.offset(13) I1=dma_addr_reg_cross.out(13) I2=m_wb_adr_o_LUT4_O_19_I0 I3=m_wb_adr_o_LUT4_O_19_I1 O=m_wb_adr_o_LUT4_O_18_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_19_I0 I1=m_wb_adr_o_LUT4_O_19_I1 I2=sd_fifo_filler0.offset(13) I3=dma_addr_reg_cross.out(13) O=sd_fifo_filler0.wbm_adr_o(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_21_I3 I1=sd_fifo_filler0.offset(11) I2=dma_addr_reg_cross.out(11) I3=m_wb_adr_o_LUT4_O_20_I3 O=m_wb_adr_o_LUT4_O_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(12) I3=sd_fifo_filler0.offset(12) O=m_wb_adr_o_LUT4_O_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(31) I3=sd_fifo_filler0.offset(31) O=m_wb_adr_o_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(30) I2=sd_fifo_filler0.offset(30) I3=m_wb_adr_o_LUT4_O_2_I3 O=sd_fifo_filler0.wbm_adr_o(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_21_I3 I1=sd_fifo_filler0.offset(11) I2=dma_addr_reg_cross.out(11) I3=m_wb_adr_o_LUT4_O_20_I3 O=sd_fifo_filler0.wbm_adr_o(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(12) I3=sd_fifo_filler0.offset(12) O=m_wb_adr_o_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(11) I2=sd_fifo_filler0.offset(11) I3=m_wb_adr_o_LUT4_O_21_I3 O=sd_fifo_filler0.wbm_adr_o(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_fifo_filler0.offset(10) I1=dma_addr_reg_cross.out(10) I2=m_wb_adr_o_LUT4_O_22_I0 I3=m_wb_adr_o_LUT4_O_22_I1 O=m_wb_adr_o_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_22_I0 I1=m_wb_adr_o_LUT4_O_22_I1 I2=sd_fifo_filler0.offset(10) I3=dma_addr_reg_cross.out(10) O=sd_fifo_filler0.wbm_adr_o(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_24_I3 I1=sd_fifo_filler0.offset(8) I2=dma_addr_reg_cross.out(8) I3=m_wb_adr_o_LUT4_O_22_I0_LUT4_O_I3 O=m_wb_adr_o_LUT4_O_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(9) I3=sd_fifo_filler0.offset(9) O=m_wb_adr_o_LUT4_O_22_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(9) I3=sd_fifo_filler0.offset(9) O=m_wb_adr_o_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(9) I2=sd_fifo_filler0.offset(9) I3=m_wb_adr_o_LUT4_O_23_I3 O=sd_fifo_filler0.wbm_adr_o(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(8) I2=sd_fifo_filler0.offset(8) I3=m_wb_adr_o_LUT4_O_24_I3 O=m_wb_adr_o_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(8) I2=sd_fifo_filler0.offset(8) I3=m_wb_adr_o_LUT4_O_24_I3 O=sd_fifo_filler0.wbm_adr_o(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_fifo_filler0.offset(7) I1=dma_addr_reg_cross.out(7) I2=m_wb_adr_o_LUT4_O_25_I0 I3=m_wb_adr_o_LUT4_O_25_I1 O=m_wb_adr_o_LUT4_O_24_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_25_I0 I1=m_wb_adr_o_LUT4_O_25_I1 I2=sd_fifo_filler0.offset(7) I3=dma_addr_reg_cross.out(7) O=sd_fifo_filler0.wbm_adr_o(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_27_I3 I1=sd_fifo_filler0.offset(5) I2=dma_addr_reg_cross.out(5) I3=m_wb_adr_o_LUT4_O_26_I3 O=m_wb_adr_o_LUT4_O_25_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(6) I3=sd_fifo_filler0.offset(6) O=m_wb_adr_o_LUT4_O_25_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_27_I3 I1=sd_fifo_filler0.offset(5) I2=dma_addr_reg_cross.out(5) I3=m_wb_adr_o_LUT4_O_26_I3 O=sd_fifo_filler0.wbm_adr_o(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(6) I3=sd_fifo_filler0.offset(6) O=m_wb_adr_o_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(5) I2=sd_fifo_filler0.offset(5) I3=m_wb_adr_o_LUT4_O_27_I3 O=sd_fifo_filler0.wbm_adr_o(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_fifo_filler0.offset(4) I1=dma_addr_reg_cross.out(4) I2=m_wb_adr_o_LUT4_O_28_I0 I3=m_wb_adr_o_LUT4_O_28_I1 O=m_wb_adr_o_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_28_I0 I1=m_wb_adr_o_LUT4_O_28_I1 I2=sd_fifo_filler0.offset(4) I3=dma_addr_reg_cross.out(4) O=sd_fifo_filler0.wbm_adr_o(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_30_I3 I1=sd_fifo_filler0.offset(2) I2=dma_addr_reg_cross.out(2) I3=m_wb_adr_o_LUT4_O_29_I3 O=m_wb_adr_o_LUT4_O_28_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(3) I3=sd_fifo_filler0.offset(3) O=m_wb_adr_o_LUT4_O_28_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_30_I3 I1=sd_fifo_filler0.offset(2) I2=dma_addr_reg_cross.out(2) I3=m_wb_adr_o_LUT4_O_29_I3 O=sd_fifo_filler0.wbm_adr_o(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(3) I3=sd_fifo_filler0.offset(3) O=m_wb_adr_o_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_fifo_filler0.offset(29) I1=dma_addr_reg_cross.out(29) I2=m_wb_adr_o_LUT4_O_3_I0 I3=m_wb_adr_o_LUT4_O_3_I1 O=m_wb_adr_o_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_3_I0 I1=m_wb_adr_o_LUT4_O_3_I1 I2=sd_fifo_filler0.offset(29) I3=dma_addr_reg_cross.out(29) O=sd_fifo_filler0.wbm_adr_o(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(2) I2=sd_fifo_filler0.offset(2) I3=m_wb_adr_o_LUT4_O_30_I3 O=sd_fifo_filler0.wbm_adr_o(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=dma_addr_reg_cross.out(1) I1=sd_fifo_filler0.offset(1) I2=dma_addr_reg_cross.out(0) I3=sd_fifo_filler0.offset(0) O=m_wb_adr_o_LUT4_O_30_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=dma_addr_reg_cross.out(0) I1=sd_fifo_filler0.offset(0) I2=dma_addr_reg_cross.out(1) I3=sd_fifo_filler0.offset(1) O=sd_fifo_filler0.wbm_adr_o(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_5_I3 I1=sd_fifo_filler0.offset(27) I2=dma_addr_reg_cross.out(27) I3=m_wb_adr_o_LUT4_O_4_I3 O=m_wb_adr_o_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(28) I3=sd_fifo_filler0.offset(28) O=m_wb_adr_o_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_5_I3 I1=sd_fifo_filler0.offset(27) I2=dma_addr_reg_cross.out(27) I3=m_wb_adr_o_LUT4_O_4_I3 O=sd_fifo_filler0.wbm_adr_o(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(28) I3=sd_fifo_filler0.offset(28) O=m_wb_adr_o_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(27) I2=sd_fifo_filler0.offset(27) I3=m_wb_adr_o_LUT4_O_5_I3 O=sd_fifo_filler0.wbm_adr_o(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(26) I2=sd_fifo_filler0.offset(26) I3=m_wb_adr_o_LUT4_O_6_I3 O=m_wb_adr_o_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(26) I2=sd_fifo_filler0.offset(26) I3=m_wb_adr_o_LUT4_O_6_I3 O=sd_fifo_filler0.wbm_adr_o(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=sd_fifo_filler0.offset(25) I1=dma_addr_reg_cross.out(25) I2=m_wb_adr_o_LUT4_O_7_I0 I3=m_wb_adr_o_LUT4_O_7_I1 O=m_wb_adr_o_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_7_I0 I1=m_wb_adr_o_LUT4_O_7_I1 I2=sd_fifo_filler0.offset(25) I3=dma_addr_reg_cross.out(25) O=sd_fifo_filler0.wbm_adr_o(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_9_I3 I1=sd_fifo_filler0.offset(23) I2=dma_addr_reg_cross.out(23) I3=m_wb_adr_o_LUT4_O_8_I3 O=m_wb_adr_o_LUT4_O_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(24) I3=sd_fifo_filler0.offset(24) O=m_wb_adr_o_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=m_wb_adr_o_LUT4_O_9_I3 I1=sd_fifo_filler0.offset(23) I2=dma_addr_reg_cross.out(23) I3=m_wb_adr_o_LUT4_O_8_I3 O=sd_fifo_filler0.wbm_adr_o(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=dma_addr_reg_cross.out(24) I3=sd_fifo_filler0.offset(24) O=m_wb_adr_o_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=dma_addr_reg_cross.out(23) I2=sd_fifo_filler0.offset(23) I3=m_wb_adr_o_LUT4_O_9_I3 O=sd_fifo_filler0.wbm_adr_o(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=sd_fifo_filler0.offset(22) I1=m_wb_adr_o_LUT4_O_10_I1 I2=m_wb_adr_o_LUT4_O_10_I0 I3=dma_addr_reg_cross.out(22) O=m_wb_adr_o_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_rx_fifo_o I2=sd_fifo_filler0.generic_fifo_dc_gray0.empty I3=m_wb_stb_o_LUT4_O_I2 O=sd_fifo_filler0.wbm_cyc_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111010
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I0 I1=m_wb_dat_o_LUT4_O_1_I1 I2=m_wb_dat_o_LUT4_O_1_I2 I3=m_wb_dat_o_LUT4_O_1_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_10_I2 I3=m_wb_dat_o_LUT4_O_10_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](21) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](21) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](21) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](21) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](21) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](21) O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](21) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](21) O=m_wb_dat_o_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](21) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](21) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](21) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](21) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](21) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](21) O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](21) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](21) O=m_wb_dat_o_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_11_I0 I1=m_wb_dat_o_LUT4_O_11_I1 I2=m_wb_dat_o_LUT4_O_11_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_11_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_11_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](20) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](20) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_11_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](20) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](20) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_11_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_11_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_11_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](20) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](20) O=m_wb_dat_o_LUT4_O_11_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](20) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](20) O=m_wb_dat_o_LUT4_O_11_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](20) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](20) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](20) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](20) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](20) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](20) O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](20) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](20) O=m_wb_dat_o_LUT4_O_11_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_12_I2 I3=m_wb_dat_o_LUT4_O_12_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](19) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](19) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](19) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](19) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](19) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](19) O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](19) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](19) O=m_wb_dat_o_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](19) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](19) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](19) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](19) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](19) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](19) O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](19) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](19) O=m_wb_dat_o_LUT4_O_12_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_13_I2 I3=m_wb_dat_o_LUT4_O_13_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](18) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](18) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](18) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](18) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](18) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](18) O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](18) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](18) O=m_wb_dat_o_LUT4_O_13_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](18) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](18) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](18) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](18) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](18) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](18) O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](18) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](18) O=m_wb_dat_o_LUT4_O_13_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_14_I2 I3=m_wb_dat_o_LUT4_O_14_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](17) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](17) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](17) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](17) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](17) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](17) O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](17) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](17) O=m_wb_dat_o_LUT4_O_14_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](17) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](17) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](17) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](17) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](17) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](17) O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](17) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](17) O=m_wb_dat_o_LUT4_O_14_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_15_I2 I3=m_wb_dat_o_LUT4_O_15_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](16) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](16) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](16) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](16) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](16) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](16) O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](16) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](16) O=m_wb_dat_o_LUT4_O_15_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](16) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](16) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](16) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](16) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](16) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](16) O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](16) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](16) O=m_wb_dat_o_LUT4_O_15_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_16_I2 I3=m_wb_dat_o_LUT4_O_16_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](15) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](15) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](15) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](15) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](15) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](15) O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](15) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](15) O=m_wb_dat_o_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_16_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](15) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](15) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](15) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](15) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](15) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](15) O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](15) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](15) O=m_wb_dat_o_LUT4_O_16_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_17_I2 I3=m_wb_dat_o_LUT4_O_17_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](14) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](14) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](14) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](14) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](14) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](14) O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](14) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](14) O=m_wb_dat_o_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](14) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](14) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](14) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](14) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](14) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](14) O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](14) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](14) O=m_wb_dat_o_LUT4_O_17_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I0 I1=m_wb_dat_o_LUT4_O_18_I1 I2=m_wb_dat_o_LUT4_O_18_I2 I3=m_wb_dat_o_LUT4_O_18_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_18_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](13) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](13) O=m_wb_dat_o_LUT4_O_18_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](13) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](13) O=m_wb_dat_o_LUT4_O_18_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_18_I1_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](13) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](13) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_18_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](13) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](13) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_18_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_18_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](13) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](13) O=m_wb_dat_o_LUT4_O_18_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](13) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](13) O=m_wb_dat_o_LUT4_O_18_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_18_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_18_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_18_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](13) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](13) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_18_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](13) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](13) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_18_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_19_I2 I3=m_wb_dat_o_LUT4_O_19_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](12) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](12) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](12) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](12) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](12) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](12) O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](12) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](12) O=m_wb_dat_o_LUT4_O_19_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_19_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](12) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](12) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](12) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](12) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](12) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](12) O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](12) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](12) O=m_wb_dat_o_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_1_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](30) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](30) O=m_wb_dat_o_LUT4_O_1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](30) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](30) O=m_wb_dat_o_LUT4_O_1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_1_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](30) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](30) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](30) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](30) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_1_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](30) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](30) O=m_wb_dat_o_LUT4_O_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](30) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](30) O=m_wb_dat_o_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_1_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_1_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](30) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](30) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](30) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](30) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_2_I2 I3=m_wb_dat_o_LUT4_O_2_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_20_I0 I1=m_wb_dat_o_LUT4_O_20_I1 I2=m_wb_dat_o_LUT4_O_20_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_20_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_20_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](11) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](11) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_20_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](11) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](11) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_20_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_20_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_20_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](11) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](11) O=m_wb_dat_o_LUT4_O_20_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](11) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](11) O=m_wb_dat_o_LUT4_O_20_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](11) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](11) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](11) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](11) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](11) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](11) O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](11) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](11) O=m_wb_dat_o_LUT4_O_20_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_21_I2 I3=m_wb_dat_o_LUT4_O_21_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](10) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](10) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](10) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](10) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](10) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](10) O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](10) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](10) O=m_wb_dat_o_LUT4_O_21_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](10) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](10) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](10) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](10) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](10) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](10) O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](10) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](10) O=m_wb_dat_o_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_22_I2 I3=m_wb_dat_o_LUT4_O_22_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](9) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](9) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](9) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](9) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](9) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](9) O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](9) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](9) O=m_wb_dat_o_LUT4_O_22_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_22_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](9) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](9) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](9) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](9) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](9) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](9) O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](9) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](9) O=m_wb_dat_o_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I0 I1=m_wb_dat_o_LUT4_O_23_I1 I2=m_wb_dat_o_LUT4_O_23_I2 I3=m_wb_dat_o_LUT4_O_23_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_23_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](8) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](8) O=m_wb_dat_o_LUT4_O_23_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](8) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](8) O=m_wb_dat_o_LUT4_O_23_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_23_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](8) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](8) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_23_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](8) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](8) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_23_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_23_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](8) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](8) O=m_wb_dat_o_LUT4_O_23_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](8) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](8) O=m_wb_dat_o_LUT4_O_23_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_23_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_23_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](8) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](8) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_23_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](8) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](8) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_23_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_24_I2 I3=m_wb_dat_o_LUT4_O_24_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](7) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](7) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](7) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](7) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](7) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](7) O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](7) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](7) O=m_wb_dat_o_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_24_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](7) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](7) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](7) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](7) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](7) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](7) O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](7) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](7) O=m_wb_dat_o_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_25_I2 I3=m_wb_dat_o_LUT4_O_25_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](6) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](6) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](6) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](6) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](6) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](6) O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](6) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](6) O=m_wb_dat_o_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_25_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](6) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](6) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](6) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](6) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](6) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](6) O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](6) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](6) O=m_wb_dat_o_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I0 I1=m_wb_dat_o_LUT4_O_26_I1 I2=m_wb_dat_o_LUT4_O_26_I2 I3=m_wb_dat_o_LUT4_O_26_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_26_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_26_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](5) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](5) O=m_wb_dat_o_LUT4_O_26_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](5) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](5) O=m_wb_dat_o_LUT4_O_26_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_26_I1_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_26_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](5) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](5) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_26_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](5) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](5) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_26_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_26_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](5) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](5) O=m_wb_dat_o_LUT4_O_26_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](5) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](5) O=m_wb_dat_o_LUT4_O_26_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_26_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_26_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](5) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](5) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_26_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](5) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](5) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_26_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_27_I0 I1=m_wb_dat_o_LUT4_O_27_I1 I2=m_wb_dat_o_LUT4_O_27_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_27_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_27_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_27_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_27_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_27_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_27_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_27_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_27_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](4) O=m_wb_dat_o_LUT4_O_27_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](4) O=m_wb_dat_o_LUT4_O_27_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_27_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](4) O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](4) O=m_wb_dat_o_LUT4_O_27_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_28_I2 I3=m_wb_dat_o_LUT4_O_28_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](3) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](3) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](3) O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](3) O=m_wb_dat_o_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_28_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](3) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](3) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](3) O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](3) O=m_wb_dat_o_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_29_I2 I3=m_wb_dat_o_LUT4_O_29_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](2) O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](2) O=m_wb_dat_o_LUT4_O_29_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](2) O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](2) O=m_wb_dat_o_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](29) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](29) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](29) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](29) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](29) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](29) O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](29) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](29) O=m_wb_dat_o_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](29) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](29) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](29) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](29) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](29) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](29) O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](29) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](29) O=m_wb_dat_o_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_3_I0 I1=m_wb_dat_o_LUT4_O_3_I1 I2=m_wb_dat_o_LUT4_O_3_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I0 I1=m_wb_dat_o_LUT4_O_30_I1 I2=m_wb_dat_o_LUT4_O_30_I2 I3=m_wb_dat_o_LUT4_O_30_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_30_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_30_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](1) O=m_wb_dat_o_LUT4_O_30_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](1) O=m_wb_dat_o_LUT4_O_30_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_30_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_30_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](1) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_30_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](1) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_30_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_30_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_30_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](1) O=m_wb_dat_o_LUT4_O_30_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](1) O=m_wb_dat_o_LUT4_O_30_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_30_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_30_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_30_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](1) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_30_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](1) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_30_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_31_I2 I3=m_wb_dat_o_LUT4_O_31_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](0) O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](0) O=m_wb_dat_o_LUT4_O_31_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_31_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](0) O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](0) O=m_wb_dat_o_LUT4_O_31_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_3_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_3_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](28) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](28) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](28) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](28) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_3_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_3_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](28) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](28) O=m_wb_dat_o_LUT4_O_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](28) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](28) O=m_wb_dat_o_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](28) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](28) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](28) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](28) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](28) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](28) O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](28) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](28) O=m_wb_dat_o_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_4_I0 I1=m_wb_dat_o_LUT4_O_4_I1 I2=m_wb_dat_o_LUT4_O_4_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_4_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_4_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](27) O=m_wb_dat_o_LUT4_O_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](27) O=m_wb_dat_o_LUT4_O_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_4_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_4_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](27) O=m_wb_dat_o_LUT4_O_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](27) O=m_wb_dat_o_LUT4_O_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](27) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](27) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](27) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](27) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](27) O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](27) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](27) O=m_wb_dat_o_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_5_I2 I3=m_wb_dat_o_LUT4_O_5_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](26) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](26) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](26) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](26) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](26) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](26) O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](26) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](26) O=m_wb_dat_o_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](26) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](26) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](26) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](26) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](26) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](26) O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](26) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](26) O=m_wb_dat_o_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_dat_o_LUT4_O_7_I3 I2=m_wb_dat_o_LUT4_O_6_I2 I3=m_wb_dat_o_LUT4_O_6_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](25) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](25) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](25) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](25) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](25) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](25) O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](25) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](25) O=m_wb_dat_o_LUT4_O_6_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](25) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](25) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](25) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](25) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](25) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](25) O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](25) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](25) O=m_wb_dat_o_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_7_I0 I1=m_wb_dat_o_LUT4_O_7_I1 I2=m_wb_dat_o_LUT4_O_7_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_7_I0_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I0_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](24) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](24) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_7_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](24) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](24) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_7_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_7_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](24) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](24) O=m_wb_dat_o_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](24) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](24) O=m_wb_dat_o_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](24) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](24) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](24) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](24) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](24) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](24) O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](24) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](24) O=m_wb_dat_o_LUT4_O_7_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I2=m_wb_dat_o_LUT4_O_8_I2 I3=m_wb_dat_o_LUT4_O_8_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](23) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](23) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](23) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](23) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](23) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](23) O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](23) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](23) O=m_wb_dat_o_LUT4_O_8_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I1 I2=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](23) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](23) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](23) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](23) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I2=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2 I3=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I3 O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](23) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](23) O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](23) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](23) O=m_wb_dat_o_LUT4_O_8_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I0 I1=m_wb_dat_o_LUT4_O_9_I1 I2=m_wb_dat_o_LUT4_O_9_I2 I3=m_wb_dat_o_LUT4_O_9_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.dout(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_9_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](22) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](22) O=m_wb_dat_o_LUT4_O_9_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](22) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](22) O=m_wb_dat_o_LUT4_O_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_9_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](22) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](22) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_9_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](22) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](22) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_9_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_9_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](22) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](22) O=m_wb_dat_o_LUT4_O_9_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](22) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](22) O=m_wb_dat_o_LUT4_O_9_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_9_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_9_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](22) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](22) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_9_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](22) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](22) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_9_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I0_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ O=m_wb_dat_o_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](31) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](31) O=m_wb_dat_o_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](31) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](31) O=m_wb_dat_o_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I1_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](31) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](31) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](31) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](31) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I2_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](31) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](31) O=m_wb_dat_o_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](31) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](31) O=m_wb_dat_o_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=m_wb_dat_o_LUT4_O_I3_LUT4_O_I0 I1=m_wb_dat_o_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ I3=m_wb_dat_o_LUT4_O_7_I3 O=m_wb_dat_o_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](31) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](31) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ O=m_wb_dat_o_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](31) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](31) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ O=m_wb_dat_o_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.wbm_ack_i I3=sd_fifo_filler0.wbm_stb_o O=m_wb_stb_o_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.empty I1=sd_fifo_filler0.fifo_rd_ack I2=m_wb_stb_o_LUT4_O_I2 I3=sd_data_master0.start_rx_fifo_o O=sd_fifo_filler0.wbm_stb_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.wbm_we_o I3=sd_fifo_filler0.wbm_ack_i O=m_wb_we_o_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I2=sd_fifo_filler0.wbm_ack_i I3=sd_fifo_filler0.wbm_we_o O=m_wb_we_o_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110000000000000
+.subckt LUT4 I0=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) I3=m_wb_we_o_LUT4_I3_O O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 O=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) O=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.start_rx_fifo_o I3=sd_fifo_filler0.generic_fifo_dc_gray0.empty O=sd_fifo_filler0.wbm_we_o
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](31) D=response_0_reg_cross.in(31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](30) D=response_0_reg_cross.in(30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](21) D=response_0_reg_cross.in(21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](20) D=response_0_reg_cross.in(20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](19) D=response_0_reg_cross.in(19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](18) D=response_0_reg_cross.in(18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](17) D=response_0_reg_cross.in(17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](16) D=response_0_reg_cross.in(16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](15) D=response_0_reg_cross.in(15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](14) D=response_0_reg_cross.in(14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](13) D=response_0_reg_cross.in(13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](12) D=response_0_reg_cross.in(12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](29) D=response_0_reg_cross.in(29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](11) D=response_0_reg_cross.in(11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](10) D=response_0_reg_cross.in(10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](9) D=response_0_reg_cross.in(9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](8) D=response_0_reg_cross.in(8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](7) D=response_0_reg_cross.in(7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](6) D=response_0_reg_cross.in(6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](5) D=response_0_reg_cross.in(5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](4) D=response_0_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](3) D=response_0_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](2) D=response_0_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](28) D=response_0_reg_cross.in(28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](1) D=response_0_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](0) D=response_0_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](27) D=response_0_reg_cross.in(27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](26) D=response_0_reg_cross.in(26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](25) D=response_0_reg_cross.in(25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](24) D=response_0_reg_cross.in(24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](23) D=response_0_reg_cross.in(23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.sync_clk_b[0](22) D=response_0_reg_cross.in(22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(31) D=response_0_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(30) D=response_0_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(21) D=response_0_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(20) D=response_0_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(19) D=response_0_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(18) D=response_0_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(17) D=response_0_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(16) D=response_0_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(15) D=response_0_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(14) D=response_0_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(13) D=response_0_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(12) D=response_0_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(29) D=response_0_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(11) D=response_0_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(10) D=response_0_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(9) D=response_0_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(8) D=response_0_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(7) D=response_0_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(6) D=response_0_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(5) D=response_0_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(4) D=response_0_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(3) D=response_0_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(2) D=response_0_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(28) D=response_0_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(1) D=response_0_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(0) D=response_0_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(27) D=response_0_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(26) D=response_0_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(25) D=response_0_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(24) D=response_0_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(23) D=response_0_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_0_reg_cross.out(22) D=response_0_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:387.29-387.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](31) D=response_1_reg_cross.in(31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](30) D=response_1_reg_cross.in(30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](21) D=response_1_reg_cross.in(21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](20) D=response_1_reg_cross.in(20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](19) D=response_1_reg_cross.in(19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](18) D=response_1_reg_cross.in(18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](17) D=response_1_reg_cross.in(17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](16) D=response_1_reg_cross.in(16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](15) D=response_1_reg_cross.in(15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](14) D=response_1_reg_cross.in(14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](13) D=response_1_reg_cross.in(13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](12) D=response_1_reg_cross.in(12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](29) D=response_1_reg_cross.in(29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](11) D=response_1_reg_cross.in(11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](10) D=response_1_reg_cross.in(10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](9) D=response_1_reg_cross.in(9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](8) D=response_1_reg_cross.in(8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](7) D=response_1_reg_cross.in(7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](6) D=response_1_reg_cross.in(6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](5) D=response_1_reg_cross.in(5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](4) D=response_1_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](3) D=response_1_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](2) D=response_1_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](28) D=response_1_reg_cross.in(28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](1) D=response_1_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](0) D=response_1_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](27) D=response_1_reg_cross.in(27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](26) D=response_1_reg_cross.in(26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](25) D=response_1_reg_cross.in(25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](24) D=response_1_reg_cross.in(24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](23) D=response_1_reg_cross.in(23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.sync_clk_b[0](22) D=response_1_reg_cross.in(22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(31) D=response_1_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(30) D=response_1_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(21) D=response_1_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(20) D=response_1_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(19) D=response_1_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(18) D=response_1_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(17) D=response_1_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(16) D=response_1_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(15) D=response_1_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(14) D=response_1_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(13) D=response_1_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(12) D=response_1_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(29) D=response_1_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(11) D=response_1_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(10) D=response_1_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(9) D=response_1_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(8) D=response_1_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(7) D=response_1_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(6) D=response_1_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(5) D=response_1_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(4) D=response_1_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(3) D=response_1_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(2) D=response_1_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(28) D=response_1_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(1) D=response_1_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(0) D=response_1_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(27) D=response_1_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(26) D=response_1_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(25) D=response_1_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(24) D=response_1_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(23) D=response_1_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_1_reg_cross.out(22) D=response_1_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:388.29-388.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](31) D=response_2_reg_cross.in(31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](30) D=response_2_reg_cross.in(30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](21) D=response_2_reg_cross.in(21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](20) D=response_2_reg_cross.in(20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](19) D=response_2_reg_cross.in(19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](18) D=response_2_reg_cross.in(18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](17) D=response_2_reg_cross.in(17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](16) D=response_2_reg_cross.in(16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](15) D=response_2_reg_cross.in(15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](14) D=response_2_reg_cross.in(14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](13) D=response_2_reg_cross.in(13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](12) D=response_2_reg_cross.in(12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](29) D=response_2_reg_cross.in(29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](11) D=response_2_reg_cross.in(11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](10) D=response_2_reg_cross.in(10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](9) D=response_2_reg_cross.in(9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](8) D=response_2_reg_cross.in(8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](7) D=response_2_reg_cross.in(7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](6) D=response_2_reg_cross.in(6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](5) D=response_2_reg_cross.in(5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](4) D=response_2_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](3) D=response_2_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](2) D=response_2_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](28) D=response_2_reg_cross.in(28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](1) D=response_2_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](0) D=response_2_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](27) D=response_2_reg_cross.in(27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](26) D=response_2_reg_cross.in(26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](25) D=response_2_reg_cross.in(25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](24) D=response_2_reg_cross.in(24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](23) D=response_2_reg_cross.in(23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.sync_clk_b[0](22) D=response_2_reg_cross.in(22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(31) D=response_2_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(30) D=response_2_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(21) D=response_2_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(20) D=response_2_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(19) D=response_2_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(18) D=response_2_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(17) D=response_2_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(16) D=response_2_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(15) D=response_2_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(14) D=response_2_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(13) D=response_2_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(12) D=response_2_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(29) D=response_2_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(11) D=response_2_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(10) D=response_2_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(9) D=response_2_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(8) D=response_2_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(7) D=response_2_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(6) D=response_2_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(5) D=response_2_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(4) D=response_2_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(3) D=response_2_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(2) D=response_2_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(28) D=response_2_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(1) D=response_2_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(0) D=response_2_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(27) D=response_2_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(26) D=response_2_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(25) D=response_2_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(24) D=response_2_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(23) D=response_2_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_2_reg_cross.out(22) D=response_2_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:389.29-389.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](31) D=response_3_reg_cross.in(31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](30) D=response_3_reg_cross.in(30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](21) D=response_3_reg_cross.in(21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](20) D=response_3_reg_cross.in(20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](19) D=response_3_reg_cross.in(19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](18) D=response_3_reg_cross.in(18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](17) D=response_3_reg_cross.in(17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](16) D=response_3_reg_cross.in(16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](15) D=response_3_reg_cross.in(15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](14) D=response_3_reg_cross.in(14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](13) D=response_3_reg_cross.in(13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](12) D=response_3_reg_cross.in(12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](29) D=response_3_reg_cross.in(29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](11) D=response_3_reg_cross.in(11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](10) D=response_3_reg_cross.in(10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](9) D=response_3_reg_cross.in(9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](8) D=response_3_reg_cross.in(8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](7) D=response_3_reg_cross.in(7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](6) D=response_3_reg_cross.in(6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](5) D=response_3_reg_cross.in(5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](4) D=response_3_reg_cross.in(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](3) D=response_3_reg_cross.in(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](2) D=response_3_reg_cross.in(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](28) D=response_3_reg_cross.in(28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](1) D=response_3_reg_cross.in(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](0) D=response_3_reg_cross.in(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](27) D=response_3_reg_cross.in(27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](26) D=response_3_reg_cross.in(26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](25) D=response_3_reg_cross.in(25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](24) D=response_3_reg_cross.in(24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](23) D=response_3_reg_cross.in(23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.sync_clk_b[0](22) D=response_3_reg_cross.in(22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(31) D=response_3_reg_cross.sync_clk_b[0](31) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(30) D=response_3_reg_cross.sync_clk_b[0](30) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(21) D=response_3_reg_cross.sync_clk_b[0](21) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(20) D=response_3_reg_cross.sync_clk_b[0](20) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(19) D=response_3_reg_cross.sync_clk_b[0](19) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(18) D=response_3_reg_cross.sync_clk_b[0](18) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(17) D=response_3_reg_cross.sync_clk_b[0](17) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(16) D=response_3_reg_cross.sync_clk_b[0](16) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(15) D=response_3_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(14) D=response_3_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(13) D=response_3_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(12) D=response_3_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(29) D=response_3_reg_cross.sync_clk_b[0](29) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(11) D=response_3_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(10) D=response_3_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(9) D=response_3_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(8) D=response_3_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(7) D=response_3_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(6) D=response_3_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(5) D=response_3_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(4) D=response_3_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(3) D=response_3_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(2) D=response_3_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(28) D=response_3_reg_cross.sync_clk_b[0](28) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(1) D=response_3_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(0) D=response_3_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(27) D=response_3_reg_cross.sync_clk_b[0](27) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(26) D=response_3_reg_cross.sync_clk_b[0](26) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(25) D=response_3_reg_cross.sync_clk_b[0](25) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(24) D=response_3_reg_cross.sync_clk_b[0](24) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(23) D=response_3_reg_cross.sync_clk_b[0](23) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=response_3_reg_cross.out(22) D=response_3_reg_cross.sync_clk_b[0](22) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:390.29-390.125|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_serial_host0.finish_o I2=sd_cmd_master0.busy_check I3=sd_cmd_master0.go_idle_o O=sd_cmd_master0.next_state_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=sd_cmd_master0.busy_check D=command_reg_cross.out(2) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(39) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(38) D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(29) D=argument_reg_cross.out(29) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(28) D=argument_reg_cross.out(28) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(27) D=argument_reg_cross.out(27) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(26) D=argument_reg_cross.out(26) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(25) D=argument_reg_cross.out(25) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(24) D=argument_reg_cross.out(24) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(23) D=argument_reg_cross.out(23) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(22) D=argument_reg_cross.out(22) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(21) D=argument_reg_cross.out(21) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(20) D=argument_reg_cross.out(20) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(37) D=command_reg_cross.out(13) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(19) D=argument_reg_cross.out(19) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(18) D=argument_reg_cross.out(18) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(17) D=argument_reg_cross.out(17) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(16) D=argument_reg_cross.out(16) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(15) D=argument_reg_cross.out(15) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(14) D=argument_reg_cross.out(14) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(13) D=argument_reg_cross.out(13) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(12) D=argument_reg_cross.out(12) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(11) D=argument_reg_cross.out(11) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(10) D=argument_reg_cross.out(10) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(36) D=command_reg_cross.out(12) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(9) D=argument_reg_cross.out(9) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(8) D=argument_reg_cross.out(8) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(7) D=argument_reg_cross.out(7) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(6) D=argument_reg_cross.out(6) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(5) D=argument_reg_cross.out(5) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(4) D=argument_reg_cross.out(4) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(3) D=argument_reg_cross.out(3) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(2) D=argument_reg_cross.out(2) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(1) D=argument_reg_cross.out(1) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(0) D=argument_reg_cross.out(0) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(35) D=command_reg_cross.out(11) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(34) D=command_reg_cross.out(10) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(33) D=command_reg_cross.out(9) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(32) D=command_reg_cross.out(8) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(31) D=argument_reg_cross.out(31) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd(30) D=argument_reg_cross.out(30) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_o I1=sd_cmd_master0.crc_check I2=sd_cmd_master0.crc_check_LUT4_I1_I2 I3=sd_cmd_master0.int_status_reg_ff_CQZ_4_QEN O=sd_cmd_master0.int_status_reg_ff_CQZ_1_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=cmd_serial_host0.crc_ok_o I1=sd_cmd_master0.crc_check I2=sd_cmd_master0.index_check_LUT4_I2_O I3=sd_cmd_master0.crc_check_LUT4_I1_1_I3 O=sd_cmd_master0.int_status_reg_ff_CQZ_3_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN_LUT4_O_I2 I2=cmd_serial_host0.finish_o I3=sd_cmd_master0.crc_check_LUT4_I1_I2 O=sd_cmd_master0.crc_check_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg_ff_CQZ_D I3=sd_cmd_master0.expect_response_LUT4_I3_I0 O=sd_cmd_master0.crc_check_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_cmd_master0.crc_check D=command_reg_cross.out(3) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0 I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=cmd_serial_host0.finish_o I3=sd_cmd_master0.expect_response O=sd_cmd_master0.expect_response_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I0 I1=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1 I2=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I2 I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=sd_cmd_master0.watchdog(13) I1=sd_cmd_master0.watchdog(12) I2=sd_cmd_master0.timeout_reg(13) I3=sd_cmd_master0.timeout_reg(12) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000101010000
+.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_cmd_master0.watchdog(11) I2=sd_cmd_master0.timeout_reg(11) I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011111111
+.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_cmd_master0.watchdog(10) I3=sd_cmd_master0.timeout_reg(10) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_cmd_master0.timeout_reg(8) I2=sd_cmd_master0.watchdog(8) I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=sd_cmd_master0.watchdog(7) I1=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_cmd_master0.timeout_reg(7) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.watchdog(6) I3=sd_cmd_master0.timeout_reg(6) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_cmd_master0.watchdog(2) I2=sd_cmd_master0.timeout_reg(2) I3=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=sd_cmd_master0.watchdog(1) I1=sd_cmd_master0.timeout_reg(1) I2=sd_cmd_master0.timeout_reg(0) I3=sd_cmd_master0.watchdog(0) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.watchdog(3) I3=sd_cmd_master0.timeout_reg(3) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_cmd_master0.watchdog(3) I1=sd_cmd_master0.timeout_reg(3) I2=sd_cmd_master0.watchdog(4) I3=sd_cmd_master0.timeout_reg(4) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=sd_cmd_master0.timeout_reg(4) I1=sd_cmd_master0.watchdog(4) I2=sd_cmd_master0.timeout_reg(5) I3=sd_cmd_master0.watchdog(5) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=sd_cmd_master0.watchdog(5) I1=sd_cmd_master0.timeout_reg(5) I2=sd_cmd_master0.watchdog(6) I3=sd_cmd_master0.timeout_reg(6) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.timeout_reg(9) I3=sd_cmd_master0.watchdog(9) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_cmd_master0.timeout_reg(9) I1=sd_cmd_master0.watchdog(9) I2=sd_cmd_master0.watchdog(10) I3=sd_cmd_master0.timeout_reg(10) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000001011
+.subckt LUT4 I0=sd_cmd_master0.timeout_reg(12) I1=sd_cmd_master0.watchdog(12) I2=sd_cmd_master0.timeout_reg(13) I3=sd_cmd_master0.watchdog(13) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=sd_cmd_master0.watchdog(15) I1=sd_cmd_master0.timeout_reg(15) I2=sd_cmd_master0.timeout_reg(14) I3=sd_cmd_master0.watchdog(14) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_cmd_master0.watchdog(15) I1=sd_cmd_master0.watchdog(14) I2=sd_cmd_master0.timeout_reg(15) I3=sd_cmd_master0.timeout_reg(14) O=sd_cmd_master0.expect_response_LUT4_I3_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt ff CQZ=sd_cmd_master0.expect_response D=sd_cmd_master0.expect_response_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=command_reg_cross.out(0) I3=command_reg_cross.out(1) O=sd_cmd_master0.expect_response_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=sd_cmd_master0.go_idle_o D=sd_cmd_master0.state(0) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.go_idle_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.state(0) I2=sd_cmd_master0.expect_response_LUT4_I3_I0 I3=sd_cmd_master0.state(1) O=sd_cmd_master0.go_idle_o_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.crc_check_LUT4_I1_I2 I2=sd_cmd_master0.index_check I3=cmd_serial_host0.index_ok_o O=sd_cmd_master0.index_check_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt ff CQZ=sd_cmd_master0.index_check D=command_reg_cross.out(4) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.int_status_reg(4) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.int_status_reg(3) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_1_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.int_status_reg(2) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN_LUT4_O_I2 I3=sd_cmd_master0.crc_check_LUT4_I1_I2 O=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=sd_cmd_master0.int_status_reg(1) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_3_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.int_status_reg(0) D=sd_cmd_master0.int_status_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.int_status_reg_ff_CQZ_4_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.crc_check_LUT4_I1_1_I3 I2=sd_cmd_master0.int_status_reg_ff_CQZ_D I3=sd_cmd_master0.expect_response_LUT4_I3_I0 O=sd_cmd_master0.int_status_reg_ff_CQZ_4_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.int_status_reg_ff_CQZ_4_QEN I3=sd_cmd_master0.index_check_LUT4_I2_O O=sd_cmd_master0.int_status_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_cmd_master0.long_response D=command_reg_cross.out(1) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_cmd_master0.next_state_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_reg(0) I2=sd_cmd_master0.state(1) I3=sd_cmd_master0.state(0) O=sd_cmd_master0.next_state(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000110000
+.subckt LUT4 I0=sd_cmd_master0.go_idle_o I1=cmd_serial_host0.finish_o I2=sd_cmd_master0.next_state_LUT4_O_1_I2 I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.next_state(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000111110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_int_rst_cross.sync_clk_b(1) I2=cmd_int_rst_cross.sync_clk_b(2) I3=sd_cmd_master0.next_state_LUT4_O_1_I2 O=sd_cmd_master0.int_status_reg_ff_CQZ_2_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=sd_cmd_master0.state(0) I1=cmd_start_cross.sync_clk_b(2) I2=cmd_start_cross.sync_clk_b(1) I3=sd_cmd_master0.state(1) O=sd_cmd_master0.next_state_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt ff CQZ=response_0_reg_cross.in(31) D=cmd_response(119) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(30) D=cmd_response(118) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(21) D=cmd_response(109) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(20) D=cmd_response(108) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(19) D=cmd_response(107) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(18) D=cmd_response(106) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(17) D=cmd_response(105) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(16) D=cmd_response(104) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(15) D=cmd_response(103) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(14) D=cmd_response(102) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(13) D=cmd_response(101) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(12) D=cmd_response(100) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(29) D=cmd_response(117) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(11) D=cmd_response(99) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(10) D=cmd_response(98) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(9) D=cmd_response(97) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(8) D=cmd_response(96) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(7) D=cmd_response(95) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(6) D=cmd_response(94) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(5) D=cmd_response(93) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(4) D=cmd_response(92) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(3) D=cmd_response(91) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(2) D=cmd_response(90) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(28) D=cmd_response(116) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(1) D=cmd_response(89) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(0) D=cmd_response(88) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(27) D=cmd_response(115) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(26) D=cmd_response(114) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(25) D=cmd_response(113) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(24) D=cmd_response(112) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(23) D=cmd_response(111) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_0_reg_cross.in(22) D=cmd_response(110) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(31) D=cmd_response(87) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(30) D=cmd_response(86) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(21) D=cmd_response(77) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(20) D=cmd_response(76) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(19) D=cmd_response(75) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(18) D=cmd_response(74) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(17) D=cmd_response(73) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(16) D=cmd_response(72) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(15) D=cmd_response(71) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(14) D=cmd_response(70) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(13) D=cmd_response(69) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(12) D=cmd_response(68) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(29) D=cmd_response(85) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(11) D=cmd_response(67) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(10) D=cmd_response(66) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(9) D=cmd_response(65) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(8) D=cmd_response(64) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(7) D=cmd_response(63) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(6) D=cmd_response(62) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(5) D=cmd_response(61) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(4) D=cmd_response(60) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(3) D=cmd_response(59) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(2) D=cmd_response(58) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(28) D=cmd_response(84) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(1) D=cmd_response(57) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(0) D=cmd_response(56) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(27) D=cmd_response(83) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(26) D=cmd_response(82) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(25) D=cmd_response(81) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(24) D=cmd_response(80) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(23) D=cmd_response(79) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_1_reg_cross.in(22) D=cmd_response(78) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(31) D=cmd_response(55) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(30) D=cmd_response(54) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(21) D=cmd_response(45) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(20) D=cmd_response(44) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(19) D=cmd_response(43) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(18) D=cmd_response(42) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(17) D=cmd_response(41) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(16) D=cmd_response(40) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(15) D=cmd_response(39) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(14) D=cmd_response(38) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(13) D=cmd_response(37) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(12) D=cmd_response(36) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(29) D=cmd_response(53) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(11) D=cmd_response(35) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(10) D=cmd_response(34) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(9) D=cmd_response(33) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(8) D=cmd_response(32) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(7) D=cmd_response(31) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(6) D=cmd_response(30) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(5) D=cmd_response(29) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(4) D=cmd_response(28) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(3) D=cmd_response(27) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(2) D=cmd_response(26) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(28) D=cmd_response(52) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(1) D=cmd_response(25) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(0) D=cmd_response(24) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(27) D=cmd_response(51) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(26) D=cmd_response(50) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(25) D=cmd_response(49) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(24) D=cmd_response(48) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(23) D=cmd_response(47) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_2_reg_cross.in(22) D=cmd_response(46) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(31) D=cmd_response(23) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(30) D=cmd_response(22) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(21) D=cmd_response(13) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(20) D=cmd_response(12) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(19) D=cmd_response(11) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(18) D=cmd_response(10) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(17) D=cmd_response(9) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(16) D=cmd_response(8) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(15) D=cmd_response(7) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(14) D=cmd_response(6) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(13) D=cmd_response(5) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(12) D=cmd_response(4) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(29) D=cmd_response(21) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(11) D=cmd_response(3) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(10) D=cmd_response(2) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(9) D=cmd_response(1) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(8) D=cmd_response(0) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(7) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(6) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(5) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(4) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(3) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(2) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(28) D=cmd_response(20) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(1) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(0) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(27) D=cmd_response(19) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(26) D=cmd_response(18) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(25) D=cmd_response(17) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(24) D=cmd_response(16) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(23) D=cmd_response(15) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=response_3_reg_cross.in(22) D=cmd_response(14) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.expect_response_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=software_reset_reg_cross.out I3=argument_reg_cross.rst O=sd_cmd_master0.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=cmd_serial_host0.start_i D=sd_cmd_master0.start_xfr_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.start_xfr_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.state(1) I3=sd_cmd_master0.state(0) O=sd_cmd_master0.start_xfr_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=cmd_start_cross.sync_clk_b(2) I1=cmd_start_cross.sync_clk_b(1) I2=sd_cmd_master0.state(0) I3=sd_cmd_master0.state(1) O=sd_cmd_master0.start_xfr_o_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111110110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.state(0) I3=sd_cmd_master0.state(1) O=sd_cmd_master0.next_state_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.state(1) I3=sd_cmd_master0.state(0) O=sd_cmd_master0.state_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.busy I3=sd_cmd_master0.state(1) O=sd_cmd_master0.watchdog_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:12.41-12.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01
+.subckt ff CQZ=sd_cmd_master0.state(1) D=sd_cmd_master0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:147.1-155.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.state(0) D=sd_cmd_master0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:147.1-155.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(15) D=sd_cmd_master0.timeout_i(15) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(14) D=sd_cmd_master0.timeout_i(14) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(5) D=sd_cmd_master0.timeout_i(5) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(4) D=sd_cmd_master0.timeout_i(4) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(3) D=sd_cmd_master0.timeout_i(3) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(2) D=sd_cmd_master0.timeout_i(2) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(1) D=sd_cmd_master0.timeout_i(1) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(0) D=sd_cmd_master0.timeout_i(0) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(13) D=sd_cmd_master0.timeout_i(13) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(12) D=sd_cmd_master0.timeout_i(12) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(11) D=sd_cmd_master0.timeout_i(11) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(10) D=sd_cmd_master0.timeout_i(10) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(9) D=sd_cmd_master0.timeout_i(9) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(8) D=sd_cmd_master0.timeout_i(8) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(7) D=sd_cmd_master0.timeout_i(7) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.timeout_reg(6) D=sd_cmd_master0.timeout_i(6) QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.state_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.watchdog(15) D=sd_cmd_master0.watchdog_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.watchdog(14) D=sd_cmd_master0.watchdog_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_cmd_master0.watchdog(5) D=sd_cmd_master0.watchdog_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(4) I2=sd_cmd_master0.watchdog(5) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_cmd_master0.watchdog(4) D=sd_cmd_master0.watchdog_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(4) I3=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_cmd_master0.watchdog(0) I1=sd_cmd_master0.watchdog(1) I2=sd_cmd_master0.watchdog(2) I3=sd_cmd_master0.watchdog(3) O=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_cmd_master0.watchdog(3) D=sd_cmd_master0.watchdog_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_12_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_cmd_master0.watchdog(0) I1=sd_cmd_master0.watchdog(1) I2=sd_cmd_master0.watchdog(2) I3=sd_cmd_master0.watchdog(3) O=sd_cmd_master0.watchdog_ff_CQZ_12_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_cmd_master0.watchdog(2) D=sd_cmd_master0.watchdog_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_cmd_master0.watchdog(0) I1=sd_cmd_master0.watchdog(1) I2=sd_cmd_master0.watchdog(2) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_cmd_master0.watchdog(1) D=sd_cmd_master0.watchdog_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(1) I3=sd_cmd_master0.watchdog(0) O=sd_cmd_master0.watchdog_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_cmd_master0.watchdog(0) D=sd_cmd_master0.watchdog_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog(0) O=sd_cmd_master0.watchdog_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_2_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(13) I2=sd_cmd_master0.watchdog(14) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_cmd_master0.watchdog(13) D=sd_cmd_master0.watchdog_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(13) I3=sd_cmd_master0.watchdog_ff_CQZ_2_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(10) I2=sd_cmd_master0.watchdog(11) I3=sd_cmd_master0.watchdog(12) O=sd_cmd_master0.watchdog_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_cmd_master0.watchdog(12) D=sd_cmd_master0.watchdog_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_3_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(10) I2=sd_cmd_master0.watchdog(11) I3=sd_cmd_master0.watchdog(12) O=sd_cmd_master0.watchdog_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_cmd_master0.watchdog(11) D=sd_cmd_master0.watchdog_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(10) I2=sd_cmd_master0.watchdog(11) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_cmd_master0.watchdog(10) D=sd_cmd_master0.watchdog_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(10) I3=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(7) I2=sd_cmd_master0.watchdog(8) I3=sd_cmd_master0.watchdog(9) O=sd_cmd_master0.watchdog_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_cmd_master0.watchdog(9) D=sd_cmd_master0.watchdog_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_6_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(7) I2=sd_cmd_master0.watchdog(8) I3=sd_cmd_master0.watchdog(9) O=sd_cmd_master0.watchdog_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_cmd_master0.watchdog(8) D=sd_cmd_master0.watchdog_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(7) I2=sd_cmd_master0.watchdog(8) I3=sd_cmd_master0.next_state_LUT4_O_1_I3 O=sd_cmd_master0.watchdog_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_cmd_master0.watchdog(7) D=sd_cmd_master0.watchdog_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_cmd_master0.next_state_LUT4_O_1_I3 I2=sd_cmd_master0.watchdog(7) I3=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(4) I2=sd_cmd_master0.watchdog(5) I3=sd_cmd_master0.watchdog(6) O=sd_cmd_master0.watchdog_ff_CQZ_8_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_cmd_master0.watchdog(6) D=sd_cmd_master0.watchdog_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_cmd_master0.watchdog_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:213.15-236.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_cmd_master.v:157.1-243.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_9_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_cmd_master0.watchdog_ff_CQZ_11_D_LUT4_O_I3 I1=sd_cmd_master0.watchdog(4) I2=sd_cmd_master0.watchdog(5) I3=sd_cmd_master0.watchdog(6) O=sd_cmd_master0.watchdog_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.next_state_LUT4_O_1_I3 I3=sd_cmd_master0.watchdog_ff_CQZ_D_LUT4_O_I3 O=sd_cmd_master0.watchdog_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_cmd_master0.watchdog(13) I1=sd_cmd_master0.watchdog(14) I2=sd_cmd_master0.watchdog_ff_CQZ_2_D_LUT4_O_I3 I3=sd_cmd_master0.watchdog(15) O=sd_cmd_master0.watchdog_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt ff CQZ=argument_reg_cross.in(31) D=sd_controller_wb0.wb_dat_i(31) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(30) D=sd_controller_wb0.wb_dat_i(30) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(21) D=sd_controller_wb0.wb_dat_i(21) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(20) D=sd_controller_wb0.wb_dat_i(20) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(19) D=sd_controller_wb0.wb_dat_i(19) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(18) D=sd_controller_wb0.wb_dat_i(18) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(17) D=sd_controller_wb0.wb_dat_i(17) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(16) D=sd_controller_wb0.wb_dat_i(16) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(29) D=sd_controller_wb0.wb_dat_i(29) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(28) D=sd_controller_wb0.wb_dat_i(28) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(27) D=sd_controller_wb0.wb_dat_i(27) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(26) D=sd_controller_wb0.wb_dat_i(26) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(25) D=sd_controller_wb0.wb_dat_i(25) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(24) D=sd_controller_wb0.wb_dat_i(24) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(23) D=sd_controller_wb0.wb_dat_i(23) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=argument_reg_cross.in(22) D=sd_controller_wb0.wb_dat_i(22) QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_count_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_count_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=argument_reg_cross.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt ff CQZ=block_size_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=block_size_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.block_size_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=clock_divider_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=clock_divider_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=clock_divider_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=clock_divider_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=clock_divider_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=clock_divider_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=clock_divider_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=clock_divider_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.clock_divider_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_int_enable_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_int_enable_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_int_enable_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_int_enable_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_int_enable_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=cmd_int_rst_edge.sig D=sd_controller_wb0.cmd_int_rst_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.cmd_int_rst_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=cmd_start_edge.sig D=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=command_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=command_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.command_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=controll_setting_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=data_int_enable_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=data_int_enable_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=data_int_enable_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.wb_adr_i(2) I1=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=wb_we_i_LUT4_I2_O O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1 O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_adr_i(5) O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.wb_adr_i(2) O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(6) I2=sd_controller_wb0.wb_adr_i(7) I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=data_int_rst_edge.sig D=sd_controller_wb0.data_int_rst_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O O=sd_controller_wb0.data_int_rst_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=dma_addr_reg_cross.in(31) D=sd_controller_wb0.wb_dat_i(31) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(30) D=sd_controller_wb0.wb_dat_i(30) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(21) D=sd_controller_wb0.wb_dat_i(21) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(20) D=sd_controller_wb0.wb_dat_i(20) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(19) D=sd_controller_wb0.wb_dat_i(19) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(18) D=sd_controller_wb0.wb_dat_i(18) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(17) D=sd_controller_wb0.wb_dat_i(17) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(16) D=sd_controller_wb0.wb_dat_i(16) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(29) D=sd_controller_wb0.wb_dat_i(29) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(28) D=sd_controller_wb0.wb_dat_i(28) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(27) D=sd_controller_wb0.wb_dat_i(27) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(26) D=sd_controller_wb0.wb_dat_i(26) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(25) D=sd_controller_wb0.wb_dat_i(25) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(24) D=sd_controller_wb0.wb_dat_i(24) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(23) D=sd_controller_wb0.wb_dat_i(23) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=dma_addr_reg_cross.in(22) D=sd_controller_wb0.wb_dat_i(22) QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_O_LUT4_I2_5_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O I2=sd_controller_wb0.software_reset_reg I3=sd_controller_wb0.timeout_reg(0) O=sd_controller_wb0.software_reset_reg_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=cmd_int_status_reg_cross.out(0) I3=sd_controller_wb0.software_reset_reg_LUT4_I2_O O=sd_controller_wb0.software_reset_reg_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00111010
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_LUT4_I2_O_LUT4_I3_O I1=cmd_int_enable_reg_cross.in(0) I2=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100001010
+.subckt ff CQZ=sd_controller_wb0.software_reset_reg D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 I2=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2 I3=wb_we_i_LUT4_I2_O O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.wb_adr_i(2) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2 I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1 O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(5) I2=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2 O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_controller_wb0.wb_adr_i(5) I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(7) I3=sd_controller_wb0.wb_adr_i(6) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(4) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O O=sd_controller_wb0.cmd_int_enable_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I2=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(3) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2 I3=sd_controller_wb0.wb_adr_i(2) O=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(15) D=sd_controller_wb0.wb_dat_i(15) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(14) D=sd_controller_wb0.wb_dat_i(14) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(5) D=sd_controller_wb0.wb_dat_i(5) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(4) D=sd_controller_wb0.wb_dat_i(4) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(3) D=sd_controller_wb0.wb_dat_i(3) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(2) D=sd_controller_wb0.wb_dat_i(2) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(1) D=sd_controller_wb0.wb_dat_i(1) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(0) D=sd_controller_wb0.wb_dat_i(0) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(13) D=sd_controller_wb0.wb_dat_i(13) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(12) D=sd_controller_wb0.wb_dat_i(12) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(11) D=sd_controller_wb0.wb_dat_i(11) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(10) D=sd_controller_wb0.wb_dat_i(10) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(9) D=sd_controller_wb0.wb_dat_i(9) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(8) D=sd_controller_wb0.wb_dat_i(8) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(7) D=sd_controller_wb0.wb_dat_i(7) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.timeout_reg(6) D=sd_controller_wb0.wb_dat_i(6) QCK=argument_reg_cross.clk_a QEN=sd_controller_wb0.timeout_reg_ff_CQZ_QEN QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.wb_ack_o D=sd_controller_wb0.wb_ack_o_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=wb_we_i_LUT4_I2_I3 QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:116.1-164.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(31) D=sd_controller_wb0.wb_dat_o_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(30) D=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(21) D=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(21) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(21) I1=response_2_reg_cross.out(21) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(21) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(21) I3=response_1_reg_cross.out(21) O=sd_controller_wb0.wb_dat_o_ff_CQZ_10_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(20) D=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(20) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(20) I1=response_2_reg_cross.out(20) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(20) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(20) I3=response_1_reg_cross.out(20) O=sd_controller_wb0.wb_dat_o_ff_CQZ_11_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(19) D=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(19) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(19) I1=response_2_reg_cross.out(19) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(19) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(19) I3=response_1_reg_cross.out(19) O=sd_controller_wb0.wb_dat_o_ff_CQZ_12_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(18) D=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(18) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(18) I1=response_2_reg_cross.out(18) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(18) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(18) I3=response_1_reg_cross.out(18) O=sd_controller_wb0.wb_dat_o_ff_CQZ_13_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(17) D=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(17) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(17) I1=response_2_reg_cross.out(17) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(17) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(17) I3=response_1_reg_cross.out(17) O=sd_controller_wb0.wb_dat_o_ff_CQZ_14_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(16) D=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(16) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(16) I1=response_2_reg_cross.out(16) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(16) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(16) I3=response_1_reg_cross.out(16) O=sd_controller_wb0.wb_dat_o_ff_CQZ_15_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(15) D=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(15) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=controll_setting_reg_cross.in(15) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=response_2_reg_cross.out(15) I3=response_3_reg_cross.out(15) O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(15) I2=sd_controller_wb0.timeout_reg(15) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(15) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(15) I3=response_1_reg_cross.out(15) O=sd_controller_wb0.wb_dat_o_ff_CQZ_16_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(14) D=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(14) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=controll_setting_reg_cross.in(14) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=response_2_reg_cross.out(14) I3=response_3_reg_cross.out(14) O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(14) I2=sd_controller_wb0.timeout_reg(14) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(14) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(14) I3=response_1_reg_cross.out(14) O=sd_controller_wb0.wb_dat_o_ff_CQZ_17_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(13) D=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000011111111
+.subckt LUT4 I0=response_1_reg_cross.out(13) I1=response_0_reg_cross.out(13) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=command_reg_cross.in(13) I1=argument_reg_cross.in(13) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(13) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=controll_setting_reg_cross.in(13) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=response_2_reg_cross.out(13) I3=response_3_reg_cross.out(13) O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(13) I2=sd_controller_wb0.timeout_reg(13) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(12) D=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000011111111
+.subckt LUT4 I0=response_1_reg_cross.out(12) I1=response_0_reg_cross.out(12) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=command_reg_cross.in(12) I1=argument_reg_cross.in(12) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(12) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=controll_setting_reg_cross.in(12) I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I2=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=response_3_reg_cross.out(12) I1=response_2_reg_cross.out(12) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(12) I2=sd_controller_wb0.timeout_reg(12) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(30) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(30) I1=response_2_reg_cross.out(30) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(30) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(30) I3=response_1_reg_cross.out(30) O=sd_controller_wb0.wb_dat_o_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(29) D=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(11) D=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(11) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=response_1_reg_cross.out(11) I1=response_0_reg_cross.out(11) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=command_reg_cross.in(11) I1=argument_reg_cross.in(11) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(11) I1=response_2_reg_cross.out(11) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(11) I2=block_size_reg_cross.in(11) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(11) I2=sd_controller_wb0.timeout_reg(11) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_20_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(10) D=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(10) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=response_1_reg_cross.out(10) I1=response_0_reg_cross.out(10) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=command_reg_cross.in(10) I1=argument_reg_cross.in(10) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(10) I1=response_2_reg_cross.out(10) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(10) I2=block_size_reg_cross.in(10) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(10) I2=sd_controller_wb0.timeout_reg(10) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_21_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(9) D=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(9) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=response_1_reg_cross.out(9) I1=response_0_reg_cross.out(9) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=command_reg_cross.in(9) I1=argument_reg_cross.in(9) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(9) I1=response_2_reg_cross.out(9) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(9) I2=block_size_reg_cross.in(9) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(9) I2=sd_controller_wb0.timeout_reg(9) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_22_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(8) D=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(8) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=response_1_reg_cross.out(8) I1=response_0_reg_cross.out(8) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=command_reg_cross.in(8) I1=argument_reg_cross.in(8) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(8) I1=response_2_reg_cross.out(8) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(8) I2=block_size_reg_cross.in(8) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(8) I2=sd_controller_wb0.timeout_reg(8) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_23_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(7) D=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(7) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(7) I1=response_2_reg_cross.out(7) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(7) I2=block_size_reg_cross.in(7) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=response_1_reg_cross.out(7) I1=response_0_reg_cross.out(7) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=command_reg_cross.in(7) I1=argument_reg_cross.in(7) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I1 I2=block_count_reg_cross.in(7) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I1=clock_divider_reg_cross.in(7) I2=sd_controller_wb0.timeout_reg(7) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_24_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(6) D=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(6) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=response_1_reg_cross.out(6) I1=response_0_reg_cross.out(6) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=command_reg_cross.in(6) I1=argument_reg_cross.in(6) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(6) I1=response_2_reg_cross.out(6) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(6) I2=block_size_reg_cross.in(6) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.timeout_reg(6) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(6) I2=clock_divider_reg_cross.in(6) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_25_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(5) D=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O I1=dma_addr_reg_cross.in(5) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(5) I1=response_2_reg_cross.out(5) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(5) I2=block_size_reg_cross.in(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=response_1_reg_cross.out(5) I1=response_0_reg_cross.out(5) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=command_reg_cross.in(5) I1=argument_reg_cross.in(5) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I3_LUT4_O_I1 I2=block_count_reg_cross.in(5) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I1=clock_divider_reg_cross.in(5) I2=sd_controller_wb0.timeout_reg(5) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_26_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(4) D=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(4) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O I1=cmd_int_enable_reg_cross.in(4) I2=clock_divider_reg_cross.in(4) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=dma_addr_reg_cross.in(4) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O I1=sd_controller_wb0.timeout_reg(4) I2=cmd_int_status_reg_cross.out(4) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(4) I1=response_2_reg_cross.out(4) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(4) I2=block_size_reg_cross.in(4) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I2=argument_reg_cross.in(4) I3=command_reg_cross.in(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(4) I3=response_1_reg_cross.out(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_27_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(3) D=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I1=cmd_int_status_reg_cross.out(3) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O I1=cmd_int_enable_reg_cross.in(3) I2=sd_controller_wb0.timeout_reg(3) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=dma_addr_reg_cross.in(3) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(3) I2=clock_divider_reg_cross.in(3) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(3) I1=response_2_reg_cross.out(3) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(3) I2=block_size_reg_cross.in(3) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I2=argument_reg_cross.in(3) I3=command_reg_cross.in(3) O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(3) I3=response_1_reg_cross.out(3) O=sd_controller_wb0.wb_dat_o_ff_CQZ_28_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(2) D=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111111111111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=response_1_reg_cross.out(2) I1=response_0_reg_cross.out(2) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=command_reg_cross.in(2) I1=argument_reg_cross.in(2) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(2) I1=response_2_reg_cross.out(2) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(2) I2=block_size_reg_cross.in(2) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1_LUT4_O_I1 I2=clock_divider_reg_cross.in(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=cmd_int_status_reg_cross.out(2) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=dma_addr_reg_cross.in(2) I1=data_int_enable_reg_cross.in(2) I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O I1=cmd_int_enable_reg_cross.in(2) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I3=data_int_status_reg_cross.out(2) O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(2) I2=sd_controller_wb0.timeout_reg(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_29_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(29) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(29) I1=response_2_reg_cross.out(29) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(29) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(29) I3=response_1_reg_cross.out(29) O=sd_controller_wb0.wb_dat_o_ff_CQZ_2_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(28) D=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(1) D=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(1) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_1_O I1=cmd_int_enable_reg_cross.in(1) I2=clock_divider_reg_cross.in(1) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O I1=sd_controller_wb0.timeout_reg(1) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=dma_addr_reg_cross.in(1) I1=data_int_enable_reg_cross.in(1) I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I1=data_int_status_reg_cross.out(1) I2=cmd_int_status_reg_cross.out(1) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=response_3_reg_cross.out(1) I1=response_2_reg_cross.out(1) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I1=controll_setting_reg_cross.in(1) I2=block_size_reg_cross.in(1) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I2=argument_reg_cross.in(1) I3=command_reg_cross.in(1) O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(1) I3=response_1_reg_cross.out(1) O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(0) D=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_O_LUT4_I3_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000100001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0 I2=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I1_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_30_D_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_I2_O I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_19_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2 I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_controller_wb0.wb_adr_i(5) I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2 I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(3) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2 I3=block_size_reg_cross.in(0) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=controll_setting_reg_cross.in(0) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=command_reg_cross.in(0) I1=argument_reg_cross.in(0) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=response_0_reg_cross.out(0) I1=response_1_reg_cross.out(0) I2=sd_controller_wb0.wb_adr_i(2) I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010111111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_3_reg_cross.out(0) I3=response_2_reg_cross.out(0) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I0 I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1 I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I2 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I2=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=clock_divider_reg_cross.in(0) I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.wb_adr_i(4) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=dma_addr_reg_cross.in(0) I1=data_int_enable_reg_cross.in(0) I2=sd_controller_wb0.wb_adr_i(5) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O I1=block_count_reg_cross.in(0) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I0_O I3=data_int_status_reg_cross.out(0) O=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(28) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(28) I1=response_2_reg_cross.out(28) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(28) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(28) I3=response_1_reg_cross.out(28) O=sd_controller_wb0.wb_dat_o_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(27) D=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(27) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(27) I1=response_2_reg_cross.out(27) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(27) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(27) I3=response_1_reg_cross.out(27) O=sd_controller_wb0.wb_dat_o_ff_CQZ_4_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(26) D=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(26) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(26) I1=response_2_reg_cross.out(26) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(26) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(26) I3=response_1_reg_cross.out(26) O=sd_controller_wb0.wb_dat_o_ff_CQZ_5_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(25) D=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(25) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(25) I1=response_2_reg_cross.out(25) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(25) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(25) I3=response_1_reg_cross.out(25) O=sd_controller_wb0.wb_dat_o_ff_CQZ_6_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(24) D=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(24) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(24) I1=response_2_reg_cross.out(24) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(24) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(24) I3=response_1_reg_cross.out(24) O=sd_controller_wb0.wb_dat_o_ff_CQZ_7_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(23) D=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(23) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(23) I1=response_2_reg_cross.out(23) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(23) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(23) I3=response_1_reg_cross.out(23) O=sd_controller_wb0.wb_dat_o_ff_CQZ_8_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_controller_wb0.wb_dat_o(22) D=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D QCK=argument_reg_cross.clk_a QEN=wb_cyc_i_LUT4_I1_1_O QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:324.18-355.19|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_controller_wb.v:166.1-193.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(22) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(22) I1=response_2_reg_cross.out(22) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(22) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(22) I3=response_1_reg_cross.out(22) O=sd_controller_wb0.wb_dat_o_ff_CQZ_9_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I3=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I3 O=sd_controller_wb0.wb_dat_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=dma_addr_reg_cross.in(31) I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=response_3_reg_cross.out(31) I1=response_2_reg_cross.out(31) I2=sd_controller_wb0.wb_adr_i(2) I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2_LUT4_I1_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O I1=argument_reg_cross.in(31) I2=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=response_0_reg_cross.out(31) I3=response_1_reg_cross.out(31) O=sd_controller_wb0.wb_dat_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.d_write_o I3=sd_data_master0.d_read_o O=sd_data_serial_host0.next_state_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_data_master0.d_read_o D=sd_data_master0.d_read_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.d_read_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.next_state_LUT4_O_1_I3 I3=sd_data_master0.d_read_o_ff_CQZ_D_LUT4_O_I3 O=sd_data_master0.d_read_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.state(0) I2=sd_data_master0.state(1) I3=sd_data_master0.state(2) O=sd_data_master0.d_read_o_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt ff CQZ=sd_data_master0.d_write_o D=sd_data_master0.d_write_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.d_write_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.tx_cycle_ff_CQZ_D I3=sd_data_master0.d_read_o_ff_CQZ_D_LUT4_O_I3 O=sd_data_master0.d_write_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=data_int_status_reg_cross.in(2) D=sd_data_master0.int_status_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.int_status_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=data_int_status_reg_cross.in(1) D=sd_data_master0.trans_done_LUT4_I3_I1 QCK=argument_reg_cross.clk_b QEN=sd_data_master0.int_status_o_ff_CQZ_1_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=data_int_status_reg_cross.in(0) D=sd_data_master0.trans_done_LUT4_I3_I1 QCK=argument_reg_cross.clk_b QEN=sd_data_master0.int_status_o_ff_CQZ_2_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.trans_done_LUT4_I3_I1 I3=sd_data_master0.tx_cycle_LUT4_I2_O O=sd_data_master0.int_status_o_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.next_state_LUT4_O_I2 I3=sd_data_master0.next_state_LUT4_O_I3 O=sd_data_master0.next_state(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.next_state_LUT4_O_1_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_master0.next_state_LUT4_O_1_I3 O=sd_data_master0.next_state(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.state(1) I2=sd_data_master0.state(2) I3=sd_data_master0.state(0) O=sd_data_master0.next_state_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_master0.state(0) I1=sd_data_master0.start_tx_i I2=sd_data_master0.next_state_LUT4_O_I3 I3=sd_data_master0.next_state_LUT4_O_2_I3 O=sd_data_master0.next_state(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.state(1) I3=sd_data_master0.state(2) O=sd_data_master0.next_state_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.start_rx_fifo_o I3=sd_data_master0.start_tx_fifo_o O=sd_fifo_filler0.offset_ff_CQZ_31_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=sd_data_master0.start_rx_fifo_o D=sd_data_master0.next_state_LUT4_O_2_I3 QCK=argument_reg_cross.clk_b QEN=sd_data_master0.tx_cycle_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I1=sd_data_master0.start_tx_fifo_o I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=m_wb_stb_o_LUT4_I3_O O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I1=sd_data_master0.start_tx_fifo_o I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O O=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=m_wb_stb_o_LUT4_I3_O I1=sd_data_master0.start_tx_fifo_o I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O O=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I1_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_data_master0.start_tx_fifo_o_LUT4_I1_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_master0.start_tx_fifo_o_LUT4_I1_O O=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I2=m_wb_stb_o_LUT4_I3_O I3=sd_data_master0.start_tx_fifo_o O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=m_wb_stb_o_LUT4_I3_O I3=sd_data_master0.start_tx_fifo_o O=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I3_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.start_tx_fifo_o_LUT4_I3_O I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_data_master0.start_tx_fifo_o_LUT4_I3_O I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_master0.start_tx_fifo_o_LUT4_I3_O O=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_data_master0.start_tx_fifo_o D=sd_data_master0.tx_cycle_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.tx_cycle_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_master0.state(2) D=sd_data_master0.next_state(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:121.1-129.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_master0.state(1) D=sd_data_master0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:121.1-129.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_master0.state(0) D=sd_data_master0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:121.1-129.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.trans_done_LUT4_I3_I1 I2=data_int_status_reg_cross.in(2) I3=sd_data_master0.trans_done O=sd_data_master0.int_status_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.tx_cycle_LUT4_I2_I3 I3=sd_data_master0.trans_done O=sd_data_master0.next_state_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_data_master0.trans_done D=sd_data_master0.tx_cycle_LUT4_I2_I3 QCK=argument_reg_cross.clk_b QEN=sd_data_master0.trans_done_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I1=sd_data_master0.tx_cycle_LUT4_I2_1_O I2=sd_data_master0.state(0) I3=sd_data_master0.state(1) O=sd_data_master0.trans_done_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=sd_data_master0.tx_fifo_empty_i I1=sd_data_master0.rx_fifo_full_i I2=sd_data_master0.tx_cycle I3=sd_data_master0.tx_cycle_LUT4_I2_I3 O=sd_data_master0.tx_cycle_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_master0.tx_fifo_empty_i I1=sd_data_master0.rx_fifo_full_i I2=sd_data_master0.tx_cycle I3=sd_data_master0.tx_cycle_LUT4_I2_I3 O=sd_data_master0.tx_cycle_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_master0.state(2) I2=sd_data_master0.state(1) I3=sd_data_master0.state(0) O=sd_data_master0.tx_cycle_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.tx_cycle_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O O=sd_data_master0.d_read_o_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_data_master0.tx_cycle D=sd_data_master0.tx_cycle_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_master0.tx_cycle_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:253.16-269.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_master.v:132.1-207.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.state(0) I3=sd_data_master0.next_state_LUT4_O_2_I3 O=sd_data_master0.tx_cycle_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.next_state_LUT4_O_2_I3 I3=sd_data_master0.next_state_LUT4_O_1_I3 O=sd_data_master0.tx_cycle_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.BITVAL D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.BITVAL_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3 I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I2=sd_data_serial_host0.DAT_dat_reg(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.BITVAL_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(15) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(14) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(5) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(4) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(3) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(2) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(1) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(0) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.inv QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(13) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(12) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(11) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(10) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(9) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(8) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(7) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(6) D=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(11) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.BITVAL I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(15) O=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.inv
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.BITVAL D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.BITVAL_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(1) O=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.BITVAL_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010001000100
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(15) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(14) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(5) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(4) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(3) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(2) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(1) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(0) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.inv QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(13) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(12) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(11) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(10) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(9) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(8) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(7) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(6) D=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(11) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.BITVAL I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(15) O=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.inv
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.BITVAL D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.BITVAL_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(2) O=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.BITVAL_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010001000100
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(15) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(14) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(5) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(4) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(3) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(2) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(1) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(0) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.inv QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(13) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(12) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(11) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(10) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(9) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(8) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(7) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(6) D=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(11) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.BITVAL I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(15) O=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.inv
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.BITVAL D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.BITVAL_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(3) O=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.BITVAL_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010001000100
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(15) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(14) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(5) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(4) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(3) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(2) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(1) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(0) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.inv QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(13) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(12) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(11) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(10) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(9) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(8) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(7) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(6) D=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE QRT=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_crc_16.v:17.4-41.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:109.19-109.75|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(11) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.inv O=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.BITVAL I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(15) O=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.inv
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt ff CQZ=sd_data_serial_host0.DAT_dat_o(3) D=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.DAT_dat_o(2) D=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0 I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011101011111111
+.subckt LUT4 I0=sd_data_serial_host0.last_din(2) I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(12) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(0) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(8) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(5) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(13) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(1) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(9) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(11) I1=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(3) I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I3=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(2) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(10) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(6) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(14) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=sd_data_serial_host0.DAT_dat_o(1) D=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0 I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011101011111111
+.subckt LUT4 I0=sd_data_serial_host0.last_din(1) I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111100010001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(7) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(15) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(5) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(13) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.crc_c(0) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001111101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(1) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(9) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.crc_c(2) I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(3) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(11) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(10) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(2) I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.crc_c(3) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(14) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(6) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(12) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(0) I3=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(8) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=sd_data_serial_host0.DAT_dat_o(0) D=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I1=sd_data_serial_host0.last_din(0) I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100011111111
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101011111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(1) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(9) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(5) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(13) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(2) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(10) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(6) I3=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(14) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(8) I1=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(0) I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.crc_c(3) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(12) I1=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(4) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0 I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011101011111111
+.subckt LUT4 I0=sd_data_serial_host0.last_din(3) I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(4) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(12) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(0) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(8) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(5) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(13) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(1) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(9) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c(2) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(11) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(3) I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(2) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(10) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(6) I3=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(14) O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=sd_data_serial_host0.DAT_dat_reg(3) D=sd_data_serial_host0.DAT_dat_i(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:103.1-104.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_data_serial_host0.DAT_dat_reg(2) D=sd_data_serial_host0.DAT_dat_i(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:103.1-104.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_data_serial_host0.DAT_dat_reg(1) D=sd_data_serial_host0.DAT_dat_i(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:103.1-104.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_data_serial_host0.DAT_dat_reg(0) D=sd_data_serial_host0.DAT_dat_i(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:103.1-104.30|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_data_serial_host0.DAT_oe_o D=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.data_cycles(12) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O I1=sd_data_serial_host0.data_cycles(8) I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.data_cycles(9) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(13) I2=sd_data_serial_host0.transf_cnt(14) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011101110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(13) I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=sd_data_serial_host0.data_cycles(13) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110001100111100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(14) I1=sd_data_serial_host0.transf_cnt(15) I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100001000100001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(13) I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(15) I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.transf_cnt(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111101100001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.transf_cnt(10) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.transf_cnt(8) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(6) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1 I3=sd_data_serial_host0.data_cycles(6) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110001100111100
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(10) I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.data_cycles(10) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100001000001101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O I2=sd_data_serial_host0.data_cycles(9) I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(11) I3=sd_data_serial_host0.transf_cnt(11) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001111
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(15) I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(11) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(9) I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(8) I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(7) I1=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(7) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.transf_cnt(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(7) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(10) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(11) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.data_cycles(11) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.transf_cnt(13) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.data_cycles(13) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.rd_ff_CQZ_QEN I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(15) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(14) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(5) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_10_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(5) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(4) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(5) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_10_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000100
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(4) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=block_count_reg_cross.out(4) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(4) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(2) I1=sd_data_serial_host0.blkcnt_reg(1) I2=sd_data_serial_host0.blkcnt_reg(3) I3=sd_data_serial_host0.blkcnt_reg(0) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(3) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_12_D_LUT4_O_I2 I3=block_count_reg_cross.out(3) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(2) I1=sd_data_serial_host0.blkcnt_reg(1) I2=sd_data_serial_host0.blkcnt_reg(0) I3=sd_data_serial_host0.blkcnt_reg(3) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_12_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000001
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(2) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_13_D_LUT4_O_I2 I3=block_count_reg_cross.out(2) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg(2) I2=sd_data_serial_host0.blkcnt_reg(0) I3=sd_data_serial_host0.blkcnt_reg(1) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_13_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(1) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=block_count_reg_cross.out(1) I1=sd_data_serial_host0.blkcnt_reg(1) I2=sd_data_serial_host0.blkcnt_reg(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101011000011
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(0) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg(0) I3=block_count_reg_cross.out(0) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=block_count_reg_cross.out(14) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(14) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(13) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=block_count_reg_cross.out(13) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(13) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D_LUT4_O_I1 I3=sd_data_serial_host0.blkcnt_reg(13) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(12) I1=sd_data_serial_host0.blkcnt_reg(10) I2=sd_data_serial_host0.blkcnt_reg(11) I3=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1 O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(12) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_3_D_LUT4_O_I2 I3=block_count_reg_cross.out(12) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(10) I1=sd_data_serial_host0.blkcnt_reg(11) I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1 I3=sd_data_serial_host0.blkcnt_reg(12) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_3_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100010000
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(11) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_4_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(11) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(10) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(11) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_4_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000100
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(10) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=block_count_reg_cross.out(10) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(10) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(9) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_6_D_LUT4_O_I2 I3=block_count_reg_cross.out(9) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(8) I1=sd_data_serial_host0.blkcnt_reg(7) I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(9) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_6_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100010000
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(8) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_7_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(8) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(7) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(8) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_7_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000100
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(7) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=block_count_reg_cross.out(7) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=sd_data_serial_host0.blkcnt_reg(7) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101000111100
+.subckt ff CQZ=sd_data_serial_host0.blkcnt_reg(6) D=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(6) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1 I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(6) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_11_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1 I3=sd_data_serial_host0.blkcnt_reg(6) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(8) I1=sd_data_serial_host0.blkcnt_reg(9) I2=sd_data_serial_host0.blkcnt_reg(7) I3=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.blkcnt_reg(5) I3=sd_data_serial_host0.blkcnt_reg(4) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=block_count_reg_cross.out(15) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.blkcnt_reg(14) I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.blkcnt_reg(15) O=sd_data_serial_host0.blkcnt_reg_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000100
+.subckt ff CQZ=sd_data_serial_host0.bus_4bit D=controll_setting_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:394.29-394.143|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_serial_host0.bus_4bit_reg D=sd_data_serial_host0.bus_4bit QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.busy_int D=sd_data_serial_host0.busy_int_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.busy_int_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.DAT_dat_reg(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.busy_int_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.busy_int_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=sd_data_serial_host0.crc_c(4) D=sd_data_serial_host0.crc_c_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.crc_c(3) D=sd_data_serial_host0.crc_c_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.crc_c_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt ff CQZ=sd_data_serial_host0.crc_c(2) D=sd_data_serial_host0.crc_c_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.crc_c_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt ff CQZ=sd_data_serial_host0.crc_c(1) D=sd_data_serial_host0.crc_c_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I1=sd_data_serial_host0.crc_c(0) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 O=sd_data_serial_host0.crc_c_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt ff CQZ=sd_data_serial_host0.crc_c(0) D=sd_data_serial_host0.crc_c_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.crc_c_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I1=sd_data_serial_host0.state(4) I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c(4) O=sd_data_serial_host0.crc_c_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101110111010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.crc_c(3) O=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.ENABLE D=sd_data_serial_host0.crc_en_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_en_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=sd_data_serial_host0.crc_en_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O I2=sd_data_serial_host0.crc_c(4) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(0) I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I1_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_master0.crc_ok_i I1=sd_data_master0.next_state_LUT4_O_I2 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_master0.trans_done_LUT4_I3_I1 O=sd_data_master0.int_status_o_ff_CQZ_1_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000011111111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I1=sd_data_master0.crc_ok_i I2=sd_data_master0.next_state_LUT4_O_I2 I3=sd_data_master0.trans_done_LUT4_I3_I1 O=sd_data_master0.int_status_o_ff_CQZ_2_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt ff CQZ=sd_data_master0.crc_ok_i D=sd_data_serial_host0.crc_ok_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=sd_data_serial_host0.crc_s(0) I1=sd_data_serial_host0.crc_s(2) I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=sd_data_serial_host0.crc_s(1) O=sd_data_serial_host0.crc_ok_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010011111111
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din(2) I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din(3) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010000000000
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(8) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(0) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din(1) I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110100
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_2_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_I2_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(8) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(0) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(8) I1=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(0) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(12) I1=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(4) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(12) I1=sd_data_serial_host0.CRC_16_gen[1].CRC_16_i.CRC(4) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(12) I1=sd_data_serial_host0.CRC_16_gen[3].CRC_16_i.CRC(4) I2=sd_data_serial_host0.crc_c(3) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.DAT_dat_o_ff_CQZ_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_1_D_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=sd_data_serial_host0.crc_c(0) I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(2) I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(3) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(11) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c(3) I2=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(7) I3=sd_data_serial_host0.CRC_16_gen[2].CRC_16_i.CRC(15) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.crc_c(0) I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din(0) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111110110000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.crc_c(1) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111101110
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(11) I1=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(3) I2=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(15) I1=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CRC(7) I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I3=sd_data_serial_host0.crc_c_ff_CQZ_2_D_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_c(1) I3=sd_data_serial_host0.crc_c(0) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I1=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 I2=sd_data_serial_host0.crc_c(2) I3=sd_data_serial_host0.DAT_dat_o_ff_CQZ_3_D_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I2 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3 I3=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.last_din_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I1 I1=sd_data_serial_host0.transf_cnt(7) I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I0 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_I2_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(8) I3=sd_data_serial_host0.transf_cnt(9) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000110000010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.transf_cnt(12) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(4) I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(13) I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(11) I3=sd_data_serial_host0.transf_cnt(10) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(10) I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.data_cycles(11) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.transf_cnt(8) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001010100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(9) I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I1=sd_data_serial_host0.transf_cnt(11) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.data_cycles(12) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.transf_cnt(6) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000101000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.data_cycles(4) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(4) I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I3 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I2 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O_LUT4_I2_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0 I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100000011001110
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.data_cycles(5) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100100010110000
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(4) I1=sd_data_serial_host0.transf_cnt(5) I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111011010111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(1) I3=sd_data_serial_host0.data_cycles(1) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(3) I1=sd_data_serial_host0.transf_cnt(2) I2=sd_data_serial_host0.data_cycles(3) I3=sd_data_serial_host0.data_cycles(2) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(2) I1=sd_data_serial_host0.data_cycles(2) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt ff CQZ=sd_data_serial_host0.CRC_16_gen[0].CRC_16_i.CLEAR D=sd_data_serial_host0.crc_rst_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_rst_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_cmd_master0.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:152.8-152.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I0 O=sd_data_serial_host0.crc_rst_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.busy_int I2=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 I3=sd_data_serial_host0.next_block_ff_CQZ_QEN O=sd_data_serial_host0.crc_rst_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_data_serial_host0.crc_s(2) D=sd_data_serial_host0.crc_s_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_s_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.crc_s(1) D=sd_data_serial_host0.crc_s_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_s_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=sd_data_serial_host0.crc_s(1) I2=sd_data_serial_host0.crc_s_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_s_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(0) I2=sd_data_serial_host0.crc_status(2) I3=sd_data_serial_host0.crc_status(1) O=sd_data_serial_host0.crc_s_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=sd_data_serial_host0.crc_s(0) D=sd_data_serial_host0.crc_s_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_s_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=sd_data_serial_host0.crc_s(0) I2=sd_data_serial_host0.crc_s_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_s_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(2) I2=sd_data_serial_host0.crc_status(1) I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_s_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=sd_data_serial_host0.crc_s(2) I2=sd_data_serial_host0.crc_s_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_s_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(1) I2=sd_data_serial_host0.crc_status(2) I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_s_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_serial_host0.crc_s_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.crc_s_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(2) I2=sd_data_serial_host0.crc_status(1) I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_s_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt ff CQZ=sd_data_serial_host0.crc_status(2) D=sd_data_serial_host0.crc_status_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_status_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.crc_status(1) D=sd_data_serial_host0.crc_status_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_status_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.crc_status(1) I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_status_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_data_serial_host0.crc_status(0) D=sd_data_serial_host0.crc_status_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_status_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.crc_status(0) O=sd_data_serial_host0.crc_status_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.crc_status(0) I1=sd_data_serial_host0.crc_status(1) I2=sd_data_serial_host0.crc_status(2) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.crc_status_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.busy_int I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.crc_status_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111101110
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(14) D=sd_data_serial_host0.data_cycles_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(13) D=sd_data_serial_host0.data_cycles_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(4) D=sd_data_serial_host0.data_cycles_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(1) I3=block_size_reg_cross.out(3) O=sd_data_serial_host0.data_cycles_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(3) D=sd_data_serial_host0.data_cycles_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(2) I3=block_size_reg_cross.out(0) O=sd_data_serial_host0.data_cycles_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(2) D=sd_data_serial_host0.data_cycles_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=block_size_reg_cross.out(1) I3=sd_data_serial_host0.bus_4bit O=sd_data_serial_host0.data_cycles_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(1) D=sd_data_serial_host0.data_cycles_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.bus_4bit I3=block_size_reg_cross.out(0) O=sd_data_serial_host0.data_cycles_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(0) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=block_size_reg_cross.out(10) I3=sd_data_serial_host0.bus_4bit O=sd_data_serial_host0.data_cycles_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(12) D=sd_data_serial_host0.data_cycles_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(9) I3=block_size_reg_cross.out(11) O=sd_data_serial_host0.data_cycles_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(11) D=sd_data_serial_host0.data_cycles_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(8) I3=block_size_reg_cross.out(10) O=sd_data_serial_host0.data_cycles_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(10) D=sd_data_serial_host0.data_cycles_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(7) I3=block_size_reg_cross.out(9) O=sd_data_serial_host0.data_cycles_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(9) D=sd_data_serial_host0.data_cycles_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(6) I3=block_size_reg_cross.out(8) O=sd_data_serial_host0.data_cycles_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(8) D=sd_data_serial_host0.data_cycles_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(5) I3=block_size_reg_cross.out(7) O=sd_data_serial_host0.data_cycles_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(7) D=sd_data_serial_host0.data_cycles_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(4) I3=block_size_reg_cross.out(6) O=sd_data_serial_host0.data_cycles_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(6) D=sd_data_serial_host0.data_cycles_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(3) I3=block_size_reg_cross.out(5) O=sd_data_serial_host0.data_cycles_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt ff CQZ=sd_data_serial_host0.data_cycles(5) D=sd_data_serial_host0.data_cycles_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit I2=block_size_reg_cross.out(2) I3=block_size_reg_cross.out(4) O=sd_data_serial_host0.data_cycles_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=block_size_reg_cross.out(11) I3=sd_data_serial_host0.bus_4bit O=sd_data_serial_host0.data_cycles_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=data_in_rx_fifo(31) D=sd_data_serial_host0.data_out_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=data_in_rx_fifo(30) D=sd_data_serial_host0.data_out_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=data_in_rx_fifo(21) D=sd_data_serial_host0.data_out_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_10_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_10_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(21) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_10_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(21) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_10_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt ff CQZ=data_in_rx_fifo(20) D=sd_data_serial_host0.data_out_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_11_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(20) O=sd_data_serial_host0.data_out_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_11_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_11_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_11_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=data_in_rx_fifo(19) D=sd_data_serial_host0.data_out_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_12_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_12_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(19) I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_12_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(19) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_12_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt ff CQZ=data_in_rx_fifo(18) D=sd_data_serial_host0.data_out_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_13_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_13_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(18) I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_13_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(18) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_13_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt ff CQZ=data_in_rx_fifo(17) D=sd_data_serial_host0.data_out_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(17) I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(1) I3=sd_data_serial_host0.transf_cnt(2) O=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(17) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt ff CQZ=data_in_rx_fifo(16) D=sd_data_serial_host0.data_out_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_15_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(16) O=sd_data_serial_host0.data_out_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_15_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_15_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_15_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=data_in_rx_fifo(15) D=sd_data_serial_host0.data_out_ff_CQZ_16_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_16_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_16_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(15) I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_16_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(15) I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_16_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt ff CQZ=data_in_rx_fifo(14) D=sd_data_serial_host0.data_out_ff_CQZ_17_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_17_D_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_17_D_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I2=data_in_rx_fifo(14) I3=sd_data_serial_host0.DAT_dat_reg(2) O=sd_data_serial_host0.data_out_ff_CQZ_17_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(14) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_17_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt ff CQZ=data_in_rx_fifo(13) D=sd_data_serial_host0.data_out_ff_CQZ_18_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I2=data_in_rx_fifo(13) I3=sd_data_serial_host0.DAT_dat_reg(1) O=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(2) I2=sd_data_serial_host0.transf_cnt(0) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(13) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=data_in_rx_fifo(12) D=sd_data_serial_host0.data_out_ff_CQZ_19_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_19_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(12) O=sd_data_serial_host0.data_out_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I3=sd_data_serial_host0.data_out_ff_CQZ_19_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_19_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I3_LUT4_O_I3 I3=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_19_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=data_in_rx_fifo(30) I3=sd_data_serial_host0.DAT_dat_reg(2) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(30) I2=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011001100
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(13) I1=sd_data_serial_host0.transf_cnt(14) I2=sd_data_serial_host0.transf_cnt(15) I3=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(5) I1=sd_data_serial_host0.transf_cnt(6) I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.transf_cnt(8) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(9) I1=sd_data_serial_host0.transf_cnt(10) I2=sd_data_serial_host0.transf_cnt(11) I3=sd_data_serial_host0.transf_cnt(12) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(1) I1=sd_data_serial_host0.transf_cnt(2) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_1_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt ff CQZ=data_in_rx_fifo(29) D=sd_data_serial_host0.data_out_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=data_in_rx_fifo(11) D=sd_data_serial_host0.data_out_ff_CQZ_20_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_20_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_20_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(11) I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_20_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(11) I2=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_20_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt ff CQZ=data_in_rx_fifo(10) D=sd_data_serial_host0.data_out_ff_CQZ_21_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_21_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_21_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(10) I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_21_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(10) I2=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_21_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt ff CQZ=data_in_rx_fifo(9) D=sd_data_serial_host0.data_out_ff_CQZ_22_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(9) I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(9) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt ff CQZ=data_in_rx_fifo(8) D=sd_data_serial_host0.data_out_ff_CQZ_23_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_23_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(8) O=sd_data_serial_host0.data_out_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_23_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_23_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_23_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt ff CQZ=data_in_rx_fifo(7) D=sd_data_serial_host0.data_out_ff_CQZ_24_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_24_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_24_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(7) I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_24_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(7) I2=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_24_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt ff CQZ=data_in_rx_fifo(6) D=sd_data_serial_host0.data_out_ff_CQZ_25_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_25_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_25_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(6) I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_25_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(6) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2_LUT4_O_I3 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_25_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt ff CQZ=data_in_rx_fifo(5) D=sd_data_serial_host0.data_out_ff_CQZ_26_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(5) I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(1) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(5) I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=data_in_rx_fifo(4) D=sd_data_serial_host0.data_out_ff_CQZ_27_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_27_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(4) O=sd_data_serial_host0.data_out_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_27_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_27_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=data_in_rx_fifo(3) D=sd_data_serial_host0.data_out_ff_CQZ_28_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(3) I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(3) I2=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 O=sd_data_serial_host0.data_out_ff_CQZ_28_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=data_in_rx_fifo(2) D=sd_data_serial_host0.data_out_ff_CQZ_29_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(2) I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(2) I2=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_29_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I2=data_in_rx_fifo(29) I3=sd_data_serial_host0.DAT_dat_reg(1) O=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I3_LUT4_O_I1 I2=data_in_rx_fifo(29) I3=sd_data_serial_host0.DAT_dat_reg(0) O=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_2_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=data_in_rx_fifo(28) D=sd_data_serial_host0.data_out_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=data_in_rx_fifo(1) D=sd_data_serial_host0.data_out_ff_CQZ_30_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_30_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(1) I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(1) I2=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_30_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=data_in_rx_fifo(0) D=sd_data_serial_host0.data_out_ff_CQZ_31_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_31_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(0) O=sd_data_serial_host0.data_out_ff_CQZ_31_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_31_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_3_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(28) O=sd_data_serial_host0.data_out_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_3_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_14_D_LUT4_O_I1_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_3_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=data_in_rx_fifo(27) D=sd_data_serial_host0.data_out_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(27) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(27) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_18_D_LUT4_O_I2_LUT4_O_I1 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_4_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=data_in_rx_fifo(26) D=sd_data_serial_host0.data_out_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(26) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(26) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_22_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_5_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=data_in_rx_fifo(25) D=sd_data_serial_host0.data_out_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(1) I1=data_in_rx_fifo(25) I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(25) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_26_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=data_in_rx_fifo(24) D=sd_data_serial_host0.data_out_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_7_D_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=data_in_rx_fifo(24) O=sd_data_serial_host0.data_out_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.data_out_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_7_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_7_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=data_in_rx_fifo(23) D=sd_data_serial_host0.data_out_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(23) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(23) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_8_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=data_in_rx_fifo(22) D=sd_data_serial_host0.data_out_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(2) I1=data_in_rx_fifo(22) I2=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(1) I2=sd_data_serial_host0.transf_cnt(0) I3=sd_data_serial_host0.transf_cnt(2) O=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(22) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_out_ff_CQZ_6_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.data_out_ff_CQZ_9_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(3) I1=data_in_rx_fifo(31) I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.DAT_dat_reg(0) I1=data_in_rx_fifo(31) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100110011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(3) O=sd_data_serial_host0.data_out_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_data_serial_host0.data_send_index(4) D=sd_data_serial_host0.data_send_index_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.data_send_index(3) D=sd_data_serial_host0.data_send_index_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.bus_4bit_reg I1=sd_data_serial_host0.data_send_index(3) I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 O=sd_data_serial_host0.data_send_index_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(0) O=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=sd_data_serial_host0.data_send_index(2) D=sd_data_serial_host0.data_send_index_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.data_send_index(0) I1=sd_data_serial_host0.data_send_index(1) I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 O=sd_data_serial_host0.data_send_index_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_data_serial_host0.data_send_index(1) D=sd_data_serial_host0.data_send_index_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(0) O=sd_data_serial_host0.data_send_index_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_data_serial_host0.data_send_index(0) D=sd_data_serial_host0.data_send_index_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.data_send_index_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.data_send_index(0) I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.data_send_index_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.crc_rst_ff_CQZ_QEN_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index_ff_CQZ_D_LUT4_O_I3 O=sd_data_serial_host0.data_send_index_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.bus_4bit_reg I1=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.data_send_index_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100100010111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.rd_ff_CQZ_QEN I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_I2_I3 O=sd_data_serial_host0.data_send_index_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_data_serial_host0.last_din(3) D=sd_data_serial_host0.last_din_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.last_din_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.last_din(2) D=sd_data_serial_host0.last_din_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.last_din_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1 I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](14) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](14) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](14) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](14) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](14) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](14) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(4) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](26) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](26) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](26) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](26) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](26) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](26) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](30) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](30) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](30) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](30) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](30) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](30) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(0) I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](6) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](6) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](6) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](6) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](6) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](6) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](22) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](22) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](22) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](22) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](22) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](22) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](22) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](22) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](22) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](22) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](22) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](22) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](22) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](22) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](22) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](22) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(4) I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](18) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](18) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](18) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](18) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](18) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](18) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](2) O=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=sd_data_serial_host0.last_din(1) D=sd_data_serial_host0.last_din_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.last_din_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](25) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](25) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](25) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](25) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](25) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](25) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](25) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](25) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](25) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](25) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](25) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](25) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](25) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](25) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](25) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](25) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](13) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](13) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](13) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](13) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](13) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](13) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](29) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](29) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](29) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](29) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](29) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](29) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(0) I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](5) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](5) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](5) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](5) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](5) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](5) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](21) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](21) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](21) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](21) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](21) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](21) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](9) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](9) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](9) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](9) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](9) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](9) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](1) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](1) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](1) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](17) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](17) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](17) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](17) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](17) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](17) O=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=sd_data_serial_host0.last_din(0) D=sd_data_serial_host0.last_din_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.last_din_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.DAT_dat_reg(0) I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(3) I2=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_1_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_I1 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](10) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](10) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](10) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](10) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](10) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](10) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](10) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](10) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](10) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](10) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](10) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](10) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](10) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](10) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](10) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](10) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(4) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(4) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(0) I3=sd_data_serial_host0.data_send_index(3) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010111111100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_I3_O I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_2_D_LUT4_O_I1_LUT4_O_I1_LUT4_I0_O_LUT4_I3_O I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000111110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.bus_4bit_reg O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(4) I3=sd_data_serial_host0.data_send_index(3) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110011111111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](4) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](4) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](20) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](20) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](20) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](20) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](20) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](20) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](20) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](20) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](20) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](20) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](20) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](20) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](20) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](20) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](20) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](20) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(0) I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](8) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](8) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](8) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](8) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](8) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](8) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](24) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](24) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](24) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](24) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](24) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](24) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](24) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](24) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](24) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](24) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](24) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](24) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](24) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](24) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](24) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](24) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(0) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](16) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](16) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](16) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](16) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](16) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](16) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1 I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](12) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](12) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](12) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](12) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](12) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](12) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](28) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](28) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](28) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](28) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](28) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](28) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](28) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](28) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](28) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](28) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](28) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](28) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](28) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](28) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](28) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](28) O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.DAT_dat_reg(3) O=sd_data_serial_host0.last_din_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.bus_4bit_reg I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(1) I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](31) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](31) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](31) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](31) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](31) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](31) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(0) I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=sd_data_serial_host0.data_send_index(2) I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](15) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](15) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](15) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](15) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](15) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](15) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](7) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](7) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](7) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](7) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](7) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](7) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index(2) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](23) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](23) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](23) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](23) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](23) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](23) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](23) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](23) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](23) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](23) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](23) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](23) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](23) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](23) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](23) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](23) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000011101110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](27) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](27) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](27) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](27) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](27) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](27) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](11) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](11) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](11) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](11) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](11) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](11) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](11) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](11) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](11) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](11) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](11) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](11) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](11) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](11) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](11) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](11) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_send_index_ff_CQZ_1_D_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.bus_4bit_reg I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](3) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](3) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](3) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](3) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](3) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](3) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](3) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](3) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(0) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.data_send_index(2) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.data_send_index(1) I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.last_din_ff_CQZ_3_D_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](19) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](19) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](19) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](19) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](19) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](19) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](19) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](19) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011110000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](19) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](19) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](19) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](19) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ I2=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](19) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](19) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](19) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](19) O=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_block I3=sd_data_master0.crc_ok_i O=sd_data_serial_host0.next_block_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_data_serial_host0.next_block D=sd_data_serial_host0.next_block_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.next_block_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.rd_ff_CQZ_QEN I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I3=sd_data_serial_host0.next_block_ff_CQZ_D_LUT4_O_I3 O=sd_data_serial_host0.next_block_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.blkcnt_reg_ff_CQZ_1_D_LUT4_O_I1 I2=sd_data_serial_host0.blkcnt_reg(15) I3=sd_data_serial_host0.blkcnt_reg(14) O=sd_data_serial_host0.next_block_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3 O=sd_data_serial_host0.next_block_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1 I2=sd_data_serial_host0.busy_int I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O I1=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I2_LUT4_I3_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_I3 O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_serial_host0.busy_int I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111101110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O I2=sd_data_serial_host0.crc_c_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_c(4) O=sd_data_serial_host0.next_block_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.busy_int I2=sd_data_serial_host0.next_state_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I3 O=sd_data_serial_host0.next_state(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0 I1=sd_data_serial_host0.next_state_LUT4_O_5_I0 I2=sd_data_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=sd_data_master0.d_read_o I2=sd_data_master0.d_write_o I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O O=sd_data_serial_host0.next_state_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111010101010
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I0 I1=sd_data_serial_host0.state(4) I2=sd_data_serial_host0.state(5) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111010101010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=sd_data_serial_host0.busy_int I3=sd_data_serial_host0.next_block_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3 I2=sd_data_serial_host0.state(4) I3=sd_data_serial_host0.state(5) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.state(5) I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3 I3=sd_data_serial_host0.state(4) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.state(0) I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I2=sd_data_serial_host0.state(1) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.state(1) I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I3=sd_data_serial_host0.state(0) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.state(2) I3=sd_data_serial_host0.state(3) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.state(3) I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 I3=sd_data_serial_host0.state(2) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.state(5) I3=sd_data_serial_host0.state(4) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.state(2) I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I2=sd_data_serial_host0.state(3) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.state(0) I3=sd_data_serial_host0.state(1) O=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.next_block_LUT4_I2_O I1=sd_data_serial_host0.next_state_LUT4_O_5_I0 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O I3=sd_data_serial_host0.DAT_dat_reg(0) O=sd_data_serial_host0.next_state(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_5_I0 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2 O=sd_data_serial_host0.next_state_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I1=sd_data_serial_host0.next_block_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_3_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I3 O=sd_data_serial_host0.next_state(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(15) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.transf_cnt(14) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101101111110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(13) I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(9) I1=sd_data_serial_host0.transf_cnt(8) I2=sd_data_serial_host0.data_cycles(9) I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(11) I1=sd_data_serial_host0.transf_cnt(10) I2=sd_data_serial_host0.data_cycles(11) I3=sd_data_serial_host0.data_cycles(10) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(10) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(9) I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.transf_cnt(6) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101101111110
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(6) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(1) I1=sd_data_serial_host0.data_cycles(2) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(14) I1=sd_data_serial_host0.data_cycles(14) I2=sd_data_serial_host0.transf_cnt(15) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(1) I3=sd_data_serial_host0.data_cycles(1) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100110010000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(1) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.data_cycles(2) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010101010011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0 I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011110000000010
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(3) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000011111
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(0) I1=sd_data_serial_host0.transf_cnt(1) I2=sd_data_serial_host0.data_cycles(0) I3=sd_data_serial_host0.data_cycles(1) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011000100000111
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.data_cycles(2) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(3) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I0_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.transf_cnt(2) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_I1 I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.transf_cnt(5) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1 I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3 O=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(5) I3=sd_data_serial_host0.transf_cnt(5) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(7) I3=sd_data_serial_host0.transf_cnt(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.data_cycles(5) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(0) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(4) I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O_LUT4_I3_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001001000000100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(3) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(1) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.data_cycles(10) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100001100
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(12) I1=sd_data_serial_host0.transf_cnt(13) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(12) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101101111101
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(15) I1=sd_data_serial_host0.transf_cnt(14) I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_I2_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(14) I2=sd_data_serial_host0.data_cycles(14) I3=sd_data_serial_host0.transf_cnt(15) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(13) I1=sd_data_serial_host0.transf_cnt(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(12) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111010101111
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(12) I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.data_cycles(13) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111000001111
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(8) I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.data_cycles(9) I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101101111101
+.subckt LUT4 I0=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=sd_data_serial_host0.transf_cnt(10) I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101001100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 O=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(7) I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I3_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.data_cycles(4) I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.data_cycles(5) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(5) I1=sd_data_serial_host0.transf_cnt(5) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.transf_cnt(6) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(6) I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(9) I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(11) I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.transf_cnt(1) I2=sd_data_serial_host0.data_cycles(1) I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111011010111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.transf_cnt(2) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101111010110111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.transf_cnt(4) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(4) I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_I1 I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I1 I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.data_cycles(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(5) I2=sd_data_serial_host0.data_cycles(4) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_I3_LUT4_O_I1 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_O_LUT4_I3_I2 I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_O O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(6) I2=sd_data_serial_host0.data_cycles(7) I3=sd_data_serial_host0.transf_cnt(7) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=sd_data_serial_host0.data_cycles(0) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(2) I3=sd_data_serial_host0.data_cycles(3) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3 O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(1) I3=sd_data_serial_host0.data_cycles(0) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(1) I1=sd_data_serial_host0.data_cycles(1) I2=sd_data_serial_host0.data_cycles(0) I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(2) I2=sd_data_serial_host0.data_cycles(1) I3=sd_data_serial_host0.data_cycles(0) O=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_3_I3_LUT4_O_I1 I2=sd_data_serial_host0.DAT_dat_reg(0) I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I1_O O=sd_data_serial_host0.next_state_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I2=sd_data_master0.d_read_o I3=sd_data_master0.d_write_o O=sd_data_serial_host0.next_state_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0 I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=sd_data_serial_host0.next_state_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=sd_data_serial_host0.next_state(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111110001000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(15) I3=sd_data_serial_host0.DAT_dat_reg(0) O=sd_data_serial_host0.next_state_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(14) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.data_cycles(13) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(12) I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.data_cycles(12) I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111010100
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(11) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I2=sd_data_serial_host0.data_cycles(10) I3=sd_data_serial_host0.data_cycles(11) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(7) I2=sd_data_serial_host0.data_cycles(6) I3=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_I1_O_LUT4_I3_O_LUT4_I3_O_LUT4_I0_I3_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(9) I2=sd_data_serial_host0.data_cycles(8) I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=sd_data_serial_host0.transf_cnt(8) I2=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=sd_data_serial_host0.data_cycles(8) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_cycles(10) I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.transf_cnt(13) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0 I1=sd_data_serial_host0.data_cycles(12) I2=sd_data_serial_host0.data_cycles(13) I3=sd_data_serial_host0.data_cycles(14) O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 O=sd_data_serial_host0.next_state_LUT4_O_4_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.next_state_LUT4_O_5_I0 I1=sd_data_serial_host0.next_state_LUT4_O_5_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.next_state_LUT4_O_5_I3 O=sd_data_serial_host0.next_state(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000011111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=sd_data_serial_host0.next_state_LUT4_O_4_I0 O=sd_data_serial_host0.next_state_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_master0.d_read_o I1=sd_data_master0.d_write_o I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_serial_host0.next_state_LUT4_O_5_I3_LUT4_O_I3 O=sd_data_serial_host0.next_state_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=sd_data_serial_host0.next_block_LUT4_I2_O I3=sd_data_serial_host0.busy_int O=sd_data_serial_host0.next_state_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.crc_status(0) I2=sd_data_serial_host0.crc_status(1) I3=sd_data_serial_host0.crc_status(2) O=sd_data_serial_host0.next_state_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.rd I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(0) O=sd_data_serial_host0.rd_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I3=sd_data_serial_host0.rd_LUT4_I1_O O=sd_data_serial_host0.rd_LUT4_I1_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I3=sd_data_serial_host0.rd O=sd_data_serial_host0.rd_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=sd_data_serial_host0.rd D=sd_data_serial_host0.rd_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.crc_en_ff_CQZ_QEN_LUT4_O_I0_LUT4_I3_O_LUT4_I3_O O=sd_data_serial_host0.rd_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.data_send_index(2) I2=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.data_send_index(0) I3=sd_data_serial_host0.data_send_index(1) O=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.bus_4bit_reg I2=sd_data_serial_host0.data_send_index(3) I3=sd_data_serial_host0.data_send_index(4) O=sd_data_serial_host0.rd_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O O=sd_data_serial_host0.rd_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=sd_data_serial_host0.state(5) D=sd_data_serial_host0.next_state(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_serial_host0.state(4) D=sd_data_serial_host0.next_state(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_serial_host0.state(3) D=sd_data_serial_host0.next_state(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_serial_host0.state(2) D=sd_data_serial_host0.next_state(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_serial_host0.state(1) D=sd_data_serial_host0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_serial_host0.state(0) D=sd_data_serial_host0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_cmd_master0.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(15) D=sd_data_serial_host0.transf_cnt_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(14) D=sd_data_serial_host0.transf_cnt_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(5) D=sd_data_serial_host0.transf_cnt_ff_CQZ_10_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(4) D=sd_data_serial_host0.transf_cnt_ff_CQZ_11_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I1=sd_data_serial_host0.transf_cnt(3) I2=sd_data_serial_host0.transf_cnt(4) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(3) D=sd_data_serial_host0.transf_cnt_ff_CQZ_12_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 O=sd_data_serial_host0.transf_cnt_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(2) D=sd_data_serial_host0.transf_cnt_ff_CQZ_13_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt(1) I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(1) D=sd_data_serial_host0.transf_cnt_ff_CQZ_14_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(0) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.transf_cnt_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(0) D=sd_data_serial_host0.transf_cnt_ff_CQZ_15_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt(0) O=sd_data_serial_host0.transf_cnt_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D_LUT4_O_I3 I1=sd_data_serial_host0.transf_cnt(13) I2=sd_data_serial_host0.transf_cnt(14) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(13) D=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(13) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(12) D=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(12) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.transf_cnt(11) O=sd_data_serial_host0.transf_cnt_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(11) D=sd_data_serial_host0.transf_cnt_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt_ff_CQZ_4_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.transf_cnt(11) O=sd_data_serial_host0.transf_cnt_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(10) D=sd_data_serial_host0.transf_cnt_ff_CQZ_5_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O I1=sd_data_serial_host0.transf_cnt(9) I2=sd_data_serial_host0.transf_cnt(10) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(9) D=sd_data_serial_host0.transf_cnt_ff_CQZ_6_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(9) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.transf_cnt_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(8) D=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(8) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(8) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(7) I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(7) D=sd_data_serial_host0.transf_cnt_ff_CQZ_8_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D_LUT4_O_I3 I1=sd_data_serial_host0.transf_cnt(6) I2=sd_data_serial_host0.transf_cnt(7) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_data_serial_host0.transf_cnt(6) D=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I2=sd_data_serial_host0.transf_cnt(6) I3=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt(5) I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2 O=sd_data_serial_host0.transf_cnt_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I3 O=sd_data_serial_host0.transf_cnt_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.transf_cnt_ff_CQZ_2_D_LUT4_O_I3 I1=sd_data_serial_host0.transf_cnt(13) I2=sd_data_serial_host0.transf_cnt(14) I3=sd_data_serial_host0.transf_cnt(15) O=sd_data_serial_host0.transf_cnt_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_data_serial_host0.we_LUT4_I1_I3 O=sd_data_serial_host0.we_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_data_serial_host0.we I2=sd_data_serial_host0.we_LUT4_I1_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_data_serial_host0.we_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.we_LUT4_I3_I2 I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_data_serial_host0.we_LUT4_I1_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_data_serial_host0.we_LUT4_I1_I3 I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_data_serial_host0.we_LUT4_I1_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_data_serial_host0.we_LUT4_I3_I2 O=sd_data_serial_host0.we_LUT4_I1_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_data_serial_host0.we I2=sd_data_serial_host0.we_LUT4_I3_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_data_serial_host0.we_LUT4_I1_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) O=sd_data_serial_host0.we_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_data_serial_host0.we_LUT4_I3_I2 I3=sd_data_serial_host0.we O=sd_data_serial_host0.we_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_data_serial_host0.we_LUT4_I1_I3 I3=sd_data_serial_host0.we O=sd_data_serial_host0.we_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_data_serial_host0.we_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_data_serial_host0.we D=sd_data_serial_host0.we_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:271.21-288.22|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_serial_host.v:170.1-367.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.bus_4bit_reg I1=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 I2=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2 I3=sd_data_serial_host0.crc_ok_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O O=sd_data_serial_host0.we_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(0) I2=sd_data_serial_host0.transf_cnt(2) I3=sd_data_serial_host0.transf_cnt(1) O=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.transf_cnt(4) I2=sd_data_serial_host0.transf_cnt(3) I3=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I1 O=sd_data_serial_host0.we_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_I2_O I2=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O I3=sd_data_serial_host0.DAT_oe_o_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=sd_data_serial_host0.we_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01011100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.next_state_LUT4_O_I1 I2=sd_data_xfer_trig0.next_state_LUT4_O_I2 I3=sd_data_xfer_trig0.r_w_i O=sd_data_xfer_trig0.next_state(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=cmd_int_status_reg_cross.in(1) I1=sd_data_xfer_trig0.next_state_LUT4_O_1_I1 I2=sd_data_xfer_trig0.next_state_LUT4_O_I2 I3=command_reg_cross.out(6) O=sd_data_xfer_trig0.next_state(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010001000100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.state(0) I2=sd_data_xfer_trig0.state(1) I3=cmd_int_status_reg_cross.in(0) O=sd_data_xfer_trig0.next_state_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=cmd_int_status_reg_cross.in(0) I2=sd_data_xfer_trig0.state(0) I3=sd_data_xfer_trig0.state(1) O=sd_data_xfer_trig0.next_state_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.r_w_reg_ff_CQZ_QEN I2=cmd_start_cross.sync_clk_b(1) I3=cmd_start_cross.sync_clk_b(2) O=sd_data_xfer_trig0.next_state_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=command_reg_cross.out(5) I3=command_reg_cross.out(6) O=sd_data_xfer_trig0.r_w_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.r_w_reg I2=sd_data_xfer_trig0.state(1) I3=sd_data_xfer_trig0.state(0) O=sd_data_xfer_trig0.start_rx_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_xfer_trig0.state(1) I2=sd_data_xfer_trig0.r_w_reg I3=sd_data_xfer_trig0.state(0) O=sd_data_xfer_trig0.start_tx_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=sd_data_xfer_trig0.r_w_reg D=sd_data_xfer_trig0.r_w_i QCK=argument_reg_cross.clk_b QEN=sd_data_xfer_trig0.r_w_reg_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:100.1-124.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_xfer_trig0.state(1) I3=sd_data_xfer_trig0.state(0) O=sd_data_xfer_trig0.r_w_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_data_master0.next_state_LUT4_O_2_I3 I1=sd_data_master0.state(0) I2=sd_data_master0.start_tx_i I3=sd_data_master0.start_rx_i O=sd_data_master0.next_state_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt ff CQZ=sd_data_master0.start_rx_i D=sd_data_xfer_trig0.start_rx_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_xfer_trig0.start_rx_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:100.1-124.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_xfer_trig0.state(1) I3=sd_data_xfer_trig0.state(0) O=sd_data_xfer_trig0.start_rx_o_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt ff CQZ=sd_data_master0.start_tx_i D=sd_data_xfer_trig0.start_tx_o_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_xfer_trig0.start_rx_o_ff_CQZ_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:100.1-124.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_data_xfer_trig0.state(1) D=sd_data_xfer_trig0.next_state(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:90.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_xfer_trig0.state(0) D=sd_data_xfer_trig0.next_state(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:314.19-322.9|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_data_xfer_trig.v:90.1-98.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.wbm_ack_i I3=sd_fifo_filler0.wbm_cyc_o O=sd_fifo_filler0.fifo_rd
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_fifo_filler0.fifo_rd_ack D=sd_fifo_filler0.fifo_rd_ack_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_cmd_master0.rst
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:86.8-86.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.fifo_rd I3=sd_fifo_filler0.fifo_rd_reg O=sd_fifo_filler0.fifo_rd_ack_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=sd_fifo_filler0.fifo_rd_reg D=sd_fifo_filler0.fifo_rd QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.empty D=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:279.1-280.68|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111101000000
+.subckt LUT4 I0=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D_LUT4_O_I3 I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(4) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(1) O=sd_fifo_filler0.generic_fifo_dc_gray0.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt ff CQZ=sd_data_master0.rx_fifo_full_i D=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:282.1-284.94|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111100010000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100101111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011010011111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) I3=sd_data_serial_host0.we O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110011101111110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) O=sd_fifo_filler0.generic_fifo_dc_gray0.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst_r QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:165.1-168.30|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst_r D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:170.1-172.25|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D_LUT4_O_I3 I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=m_wb_dat_o_LUT4_O_7_I3 D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_1_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_2_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_D_3_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(4) I3=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0 O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=m_wb_we_o_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(0) I1=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) I2=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=m_wb_we_o_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst I3=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin(1) O=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_bin_x(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.rp_s(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.rp_gray(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[0](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[10](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_5_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[11](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[12](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[13](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[14](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[15](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[1](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[2](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[3](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[4](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[5](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[6](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_4_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[7](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[8](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](31) D=data_in_rx_fifo(31) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](30) D=data_in_rx_fifo(30) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](21) D=data_in_rx_fifo(21) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](20) D=data_in_rx_fifo(20) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](19) D=data_in_rx_fifo(19) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](18) D=data_in_rx_fifo(18) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](17) D=data_in_rx_fifo(17) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](16) D=data_in_rx_fifo(16) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](15) D=data_in_rx_fifo(15) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](14) D=data_in_rx_fifo(14) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](13) D=data_in_rx_fifo(13) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](12) D=data_in_rx_fifo(12) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](29) D=data_in_rx_fifo(29) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](11) D=data_in_rx_fifo(11) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](10) D=data_in_rx_fifo(10) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](9) D=data_in_rx_fifo(9) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](8) D=data_in_rx_fifo(8) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](7) D=data_in_rx_fifo(7) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](6) D=data_in_rx_fifo(6) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](5) D=data_in_rx_fifo(5) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](4) D=data_in_rx_fifo(4) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](3) D=data_in_rx_fifo(3) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](2) D=data_in_rx_fifo(2) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](28) D=data_in_rx_fifo(28) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](1) D=data_in_rx_fifo(1) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](0) D=data_in_rx_fifo(0) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](27) D=data_in_rx_fifo(27) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](26) D=data_in_rx_fifo(26) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](25) D=data_in_rx_fifo(25) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](24) D=data_in_rx_fifo(24) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](23) D=data_in_rx_fifo(23) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.mem[9](22) D=data_in_rx_fifo(22) QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.we_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I3=sd_data_serial_host0.we O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_1_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 I3=sd_data_serial_host0.we O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(3) I1=sd_data_serial_host0.we I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I3=sd_fifo_filler0.generic_fifo_dc_gray0.u0.waddr(1) O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(4) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(3) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(2) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(1) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wp_s(0) D=sd_fifo_filler0.generic_fifo_dc_gray0.wp_gray(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst I3=sd_data_serial_host0.we O=sd_fifo_filler0.generic_fifo_dc_gray0.wp_bin_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst_r QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:174.1-177.30|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst_r D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:179.1-181.25|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:96.7-109.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_data_master0.tx_fifo_empty_i D=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:279.1-280.68|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(1) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(4) O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000001001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) I3=sd_data_serial_host0.rd_LUT4_I1_O_LUT4_I3_O O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D_LUT4_O_I3 I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010001000001
+.subckt LUT4 I0=sd_data_master0.tx_fifo_full_i I1=sd_data_master0.tx_cycle_ff_CQZ_D I2=sd_data_master0.next_state_LUT4_O_1_I3 I3=sd_data_serial_host0.next_state_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_1_O O=sd_data_master0.next_state_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=sd_data_master0.state(2) I1=sd_data_master0.tx_fifo_full_i I2=sd_data_master0.state(0) I3=sd_data_master0.state(1) O=sd_data_master0.d_write_o_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_data_master0.start_tx_fifo_o I3=sd_data_master0.tx_fifo_full_i O=m_wb_stb_o_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_data_master0.tx_fifo_full_i D=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:282.1-284.94|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1 I2=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2 I3=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111101000100
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 I2=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001111111110011
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1 I2=m_wb_stb_o_LUT4_I3_O I3=sd_data_master0.start_tx_fifo_o O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011010011111
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110011101111110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0 I1=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001010000000000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.full_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.wr_rst_r QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:165.1-168.30|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:243.1-248.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_data_serial_host0.last_din_ff_CQZ_D_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_1_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_2_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_D_3_CQZ D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_1_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.empty_ff_CQZ_D_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_4_D QCK=argument_reg_cross.clk_b QEN=sd_data_serial_host0.rd_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:250.1-255.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.rd_rst I3=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin(1) O=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_bin_x(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(4) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(3) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(2) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(1) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.rp_s(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.rp_gray(0) QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:269.1-269.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[0](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[10](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[11](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[12](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[13](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[14](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[15](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_2_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[1](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[2](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[3](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[4](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[5](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[6](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I2_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[7](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_O_LUT4_I3_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[8](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](31) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(31) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](30) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(30) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](21) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(21) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](20) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(20) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](19) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(19) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](18) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(18) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](17) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(17) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](16) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(16) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](15) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(15) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](14) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(14) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](13) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(13) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](12) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(12) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](29) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(29) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](11) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(11) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](10) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(10) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](9) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(9) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](8) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(8) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](7) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(7) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](6) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(6) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](5) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(5) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](4) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(4) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](3) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(3) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](2) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(2) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](28) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(28) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](1) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(1) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](0) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(0) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](27) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(27) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](26) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(26) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](25) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(25) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](24) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(24) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](23) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(23) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.mem[9](22) D=sd_fifo_filler0.generic_fifo_dc_gray1.din(22) QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I1_1_O_LUT4_I1_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D_LUT4_O_I3 I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:226.1-231.32|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I2=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin(4) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_1_D_LUT4_O_I3 O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.wp_bin_ff_CQZ_2_D_LUT4_O_I3 I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(3) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(0) I1=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) I2=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(2) I3=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=sd_data_master0.start_tx_fifo_o_LUT4_I3_1_O QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:233.1-238.34|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst I3=sd_fifo_filler0.generic_fifo_dc_gray1.u0.waddr(1) O=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(4) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(3) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(2) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(1) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wp_s(0) D=sd_fifo_filler0.generic_fifo_dc_gray1.wp_gray(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=sd_data_serial_host0.busy QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:266.1-266.42|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst D=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.generic_fifo_dc_gray0.rd_rst_r QRT=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/generic_fifo_dc_gray.v:174.1-177.30|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:114.7-127.6|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_cmd_master0.rst I3=sd_fifo_filler0.offset_ff_CQZ_31_QEN O=sd_fifo_filler0.generic_fifo_dc_gray1.wr_rst_ff_CQZ_QRT
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=sd_fifo_filler0.offset(31) D=sd_fifo_filler0.offset_ff_CQZ_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_fifo_filler0.offset(30) D=sd_fifo_filler0.offset_ff_CQZ_1_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_fifo_filler0.offset(21) D=sd_fifo_filler0.offset_ff_CQZ_10_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_10_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(19) I2=sd_fifo_filler0.offset(20) I3=sd_fifo_filler0.offset(21) O=sd_fifo_filler0.offset_ff_CQZ_10_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_fifo_filler0.offset(20) D=sd_fifo_filler0.offset_ff_CQZ_11_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(19) I2=sd_fifo_filler0.offset(20) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(19) D=sd_fifo_filler0.offset_ff_CQZ_12_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(19) I3=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(16) I2=sd_fifo_filler0.offset(17) I3=sd_fifo_filler0.offset(18) O=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(18) D=sd_fifo_filler0.offset_ff_CQZ_13_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_13_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(16) I2=sd_fifo_filler0.offset(17) I3=sd_fifo_filler0.offset(18) O=sd_fifo_filler0.offset_ff_CQZ_13_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_fifo_filler0.offset(17) D=sd_fifo_filler0.offset_ff_CQZ_14_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(16) I2=sd_fifo_filler0.offset(17) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(16) D=sd_fifo_filler0.offset_ff_CQZ_15_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(16) I3=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(13) I2=sd_fifo_filler0.offset(14) I3=sd_fifo_filler0.offset(15) O=sd_fifo_filler0.offset_ff_CQZ_15_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(15) D=sd_fifo_filler0.offset_ff_CQZ_16_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_16_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(13) I2=sd_fifo_filler0.offset(14) I3=sd_fifo_filler0.offset(15) O=sd_fifo_filler0.offset_ff_CQZ_16_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_fifo_filler0.offset(14) D=sd_fifo_filler0.offset_ff_CQZ_17_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(13) I2=sd_fifo_filler0.offset(14) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(13) D=sd_fifo_filler0.offset_ff_CQZ_18_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(13) I3=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(10) I2=sd_fifo_filler0.offset(11) I3=sd_fifo_filler0.offset(12) O=sd_fifo_filler0.offset_ff_CQZ_18_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(12) D=sd_fifo_filler0.offset_ff_CQZ_19_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_19_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(10) I2=sd_fifo_filler0.offset(11) I3=sd_fifo_filler0.offset(12) O=sd_fifo_filler0.offset_ff_CQZ_19_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(30) I3=sd_fifo_filler0.offset_ff_CQZ_D_LUT4_O_I0 O=sd_fifo_filler0.offset_ff_CQZ_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.offset(29) D=sd_fifo_filler0.offset_ff_CQZ_2_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_fifo_filler0.offset(11) D=sd_fifo_filler0.offset_ff_CQZ_20_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(10) I2=sd_fifo_filler0.offset(11) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(10) D=sd_fifo_filler0.offset_ff_CQZ_21_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(10) I3=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.offset(9) D=sd_fifo_filler0.offset_ff_CQZ_22_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_22_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O I1=sd_fifo_filler0.offset(7) I2=sd_fifo_filler0.offset(8) I3=sd_fifo_filler0.offset(9) O=sd_fifo_filler0.offset_ff_CQZ_22_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_fifo_filler0.offset(8) D=sd_fifo_filler0.offset_ff_CQZ_23_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O I1=sd_fifo_filler0.offset(7) I2=sd_fifo_filler0.offset(8) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(7) D=sd_fifo_filler0.offset_ff_CQZ_24_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(7) I3=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_24_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.offset(6) D=sd_fifo_filler0.offset_ff_CQZ_25_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(6) I3=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_25_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.offset(6) I3=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3_LUT4_I3_O I1=sd_fifo_filler0.offset(7) I2=sd_fifo_filler0.offset(8) I3=sd_fifo_filler0.offset(9) O=sd_fifo_filler0.offset_ff_CQZ_21_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.offset(5) I2=sd_fifo_filler0.offset(4) I3=sd_fifo_filler0.offset_ff_CQZ_27_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_25_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=sd_fifo_filler0.offset(5) D=sd_fifo_filler0.offset_ff_CQZ_26_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_27_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(4) I2=sd_fifo_filler0.offset(5) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_26_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(4) D=sd_fifo_filler0.offset_ff_CQZ_27_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(4) I3=sd_fifo_filler0.offset_ff_CQZ_27_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_27_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.offset(3) I3=sd_fifo_filler0.offset(2) O=sd_fifo_filler0.offset_ff_CQZ_27_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=sd_fifo_filler0.offset(3) D=sd_fifo_filler0.offset_ff_CQZ_28_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(3) I3=sd_fifo_filler0.offset(2) O=sd_fifo_filler0.offset_ff_CQZ_28_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt ff CQZ=sd_fifo_filler0.offset(2) D=sd_fifo_filler0.offset_ff_CQZ_29_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset(2) O=sd_fifo_filler0.offset_ff_CQZ_29_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_3_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(28) I2=sd_fifo_filler0.offset(29) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(28) D=sd_fifo_filler0.offset_ff_CQZ_3_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_fifo_filler0.offset(1) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt ff CQZ=sd_fifo_filler0.offset(0) D=sd_data_serial_host0.busy QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_fifo_filler0.offset_ff_CQZ_31_QEN I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(28) I3=sd_fifo_filler0.offset_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(25) I2=sd_fifo_filler0.offset(26) I3=sd_fifo_filler0.offset(27) O=sd_fifo_filler0.offset_ff_CQZ_3_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(27) D=sd_fifo_filler0.offset_ff_CQZ_4_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_4_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(25) I2=sd_fifo_filler0.offset(26) I3=sd_fifo_filler0.offset(27) O=sd_fifo_filler0.offset_ff_CQZ_4_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_fifo_filler0.offset(26) D=sd_fifo_filler0.offset_ff_CQZ_5_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(25) I2=sd_fifo_filler0.offset(26) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(25) D=sd_fifo_filler0.offset_ff_CQZ_6_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(25) I3=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(22) I2=sd_fifo_filler0.offset(23) I3=sd_fifo_filler0.offset(24) O=sd_fifo_filler0.offset_ff_CQZ_6_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(24) D=sd_fifo_filler0.offset_ff_CQZ_7_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=m_wb_stb_o_LUT4_I3_O I3=sd_fifo_filler0.offset_ff_CQZ_7_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(22) I2=sd_fifo_filler0.offset(23) I3=sd_fifo_filler0.offset(24) O=sd_fifo_filler0.offset_ff_CQZ_7_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000001111111
+.subckt ff CQZ=sd_fifo_filler0.offset(23) D=sd_fifo_filler0.offset_ff_CQZ_8_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(22) I2=sd_fifo_filler0.offset(23) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt ff CQZ=sd_fifo_filler0.offset(22) D=sd_fifo_filler0.offset_ff_CQZ_9_D QCK=argument_reg_cross.clk_a QEN=sd_fifo_filler0.offset_ff_CQZ_31_QEN_LUT4_I2_O QRT=sd_cmd_master0.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:290.16-312.10|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sd_fifo_filler.v:131.1-144.8|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:148.8-148.81"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=m_wb_stb_o_LUT4_I3_O I2=sd_fifo_filler0.offset(22) I3=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_12_D_LUT4_O_I3 I1=sd_fifo_filler0.offset(19) I2=sd_fifo_filler0.offset(20) I3=sd_fifo_filler0.offset(21) O=sd_fifo_filler0.offset_ff_CQZ_9_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=sd_fifo_filler0.offset_ff_CQZ_D_LUT4_O_I0 I1=sd_fifo_filler0.offset(30) I2=sd_fifo_filler0.offset(31) I3=m_wb_stb_o_LUT4_I3_O O=sd_fifo_filler0.offset_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_fifo_filler0.offset(29) I2=sd_fifo_filler0.offset(28) I3=sd_fifo_filler0.offset_ff_CQZ_3_D_LUT4_O_I3 O=sd_fifo_filler0.offset_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt ff CQZ=software_reset_reg_cross.sync_clk_b[0] D=sd_controller_wb0.software_reset_reg QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:391.23-391.131|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=software_reset_reg_cross.out D=software_reset_reg_cross.sync_clk_b[0] QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:391.23-391.131|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](15) D=sd_controller_wb0.timeout_reg(15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](14) D=sd_controller_wb0.timeout_reg(14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](5) D=sd_controller_wb0.timeout_reg(5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](4) D=sd_controller_wb0.timeout_reg(4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](3) D=sd_controller_wb0.timeout_reg(3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](2) D=sd_controller_wb0.timeout_reg(2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](1) D=sd_controller_wb0.timeout_reg(1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](0) D=sd_controller_wb0.timeout_reg(0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](13) D=sd_controller_wb0.timeout_reg(13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](12) D=sd_controller_wb0.timeout_reg(12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](11) D=sd_controller_wb0.timeout_reg(11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](10) D=sd_controller_wb0.timeout_reg(10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](9) D=sd_controller_wb0.timeout_reg(9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](8) D=sd_controller_wb0.timeout_reg(8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](7) D=sd_controller_wb0.timeout_reg(7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=timeout_reg_cross.sync_clk_b[0](6) D=sd_controller_wb0.timeout_reg(6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(15) D=timeout_reg_cross.sync_clk_b[0](15) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(14) D=timeout_reg_cross.sync_clk_b[0](14) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(5) D=timeout_reg_cross.sync_clk_b[0](5) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(4) D=timeout_reg_cross.sync_clk_b[0](4) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(3) D=timeout_reg_cross.sync_clk_b[0](3) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(2) D=timeout_reg_cross.sync_clk_b[0](2) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(1) D=timeout_reg_cross.sync_clk_b[0](1) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(0) D=timeout_reg_cross.sync_clk_b[0](0) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(13) D=timeout_reg_cross.sync_clk_b[0](13) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(12) D=timeout_reg_cross.sync_clk_b[0](12) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(11) D=timeout_reg_cross.sync_clk_b[0](11) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(10) D=timeout_reg_cross.sync_clk_b[0](10) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(9) D=timeout_reg_cross.sync_clk_b[0](9) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(8) D=timeout_reg_cross.sync_clk_b[0](8) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(7) D=timeout_reg_cross.sync_clk_b[0](7) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt ff CQZ=sd_cmd_master0.timeout_i(6) D=timeout_reg_cross.sync_clk_b[0](6) QCK=argument_reg_cross.clk_b QEN=sd_fifo_filler0.generic_fifo_dc_gray0.u0.oe QRT=argument_reg_cross.rst QST=sd_data_serial_host0.busy
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/sdc_controller.v:392.29-392.116|/home/tpagarani/git/yosys-testing/Designs/sdc_controller/rtl/bistable_domain_cross.v:62.1-71.4|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:78.8-78.84"
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_cyc_i I2=sd_controller_wb0.wb_stb_i I3=sd_controller_wb0.wb_ack_o O=sd_controller_wb0.wb_ack_o_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_cyc_i I2=sd_controller_wb0.wb_stb_i I3=wb_cyc_i_LUT4_I1_1_I3 O=wb_cyc_i_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I1 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3 O=wb_cyc_i_LUT4_I1_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(3) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3 O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_adr_i(1) I3=sd_controller_wb0.wb_adr_i(0) O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=sd_controller_wb0.wb_adr_i(2) I1=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3 I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=wb_we_i_LUT4_I2_O O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(2) I2=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2 I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3 O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_adr_i(1) I2=sd_controller_wb0.wb_adr_i(0) I3=sd_controller_wb0.wb_adr_i(3) O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I3_I2 I2=sd_controller_wb0.wb_adr_i(4) I3=sd_controller_wb0.wb_adr_i(5) O=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_controller_wb0.wb_ack_o I2=sd_controller_wb0.wb_stb_i I3=sd_controller_wb0.wb_cyc_i O=wb_we_i_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=sd_controller_wb0.wb_we_i I3=wb_we_i_LUT4_I2_I3 O=wb_we_i_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=wb_cyc_i_LUT4_I1_1_I3_LUT4_O_I3_LUT4_I3_O O=sd_controller_wb0.command_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I1_O O=sd_controller_wb0.timeout_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_I3_O O=sd_controller_wb0.block_size_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.wb_dat_o_ff_CQZ_31_D_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.controll_setting_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.software_reset_reg_ff_CQZ_QEN_LUT4_O_I2_LUT4_I2_O O=sd_controller_wb0.block_count_reg_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=sd_data_serial_host0.busy I1=sd_data_serial_host0.busy I2=wb_we_i_LUT4_I2_O I3=sd_controller_wb0.data_int_enable_reg_ff_CQZ_QEN_LUT4_O_I1_LUT4_O_I2_LUT4_I1_O_LUT4_I3_O O=wb_we_i_LUT4_I2_O_LUT4_I2_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.end
diff --git a/BENCHMARK/sha256/rtl/sha1.v b/BENCHMARK/sha256/rtl/sha1.v
new file mode 100644
index 0000000..972053c
--- /dev/null
+++ b/BENCHMARK/sha256/rtl/sha1.v
@@ -0,0 +1,594 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SHA-160                                                    ////
+////  Secure Hash Algorithm (SHA-160)                            ////
+////                                                             ////
+////  Author: marsgod                                            ////
+////          marsgod@opencores.org                              ////
+////                                                             ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/cores/sha_core/  ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002-2004 marsgod                             ////
+////                         marsgod@opencores.org               ////
+////                                                             ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+`define SHA1_H0 32'h67452301
+`define SHA1_H1 32'hefcdab89
+`define SHA1_H2 32'h98badcfe
+`define SHA1_H3 32'h10325476
+`define SHA1_H4 32'hc3d2e1f0
+
+`define SHA1_K0 32'h5a827999
+`define SHA1_K1 32'h6ed9eba1
+`define SHA1_K2 32'h8f1bbcdc
+`define SHA1_K3 32'hca62c1d6
+
+module sha1 (clk_i, rst_i, text_i, text_o, cmd_i, cmd_w_i, cmd_o);
+
+	input		clk_i; 	// global clock input
+	input		rst_i; 	// global reset input , active high
+	
+	input	[31:0]	text_i;	// text input 32bit
+	output	[31:0]	text_o;	// text output 32bit
+	
+	input	[2:0]	cmd_i;	// command input
+	input		cmd_w_i;// command input write enable
+	output	[3:0]	cmd_o;	// command output(status)
+
+	/*
+		cmd
+		Busy Round W R
+
+		bit3 bit2  bit1 bit0
+		Busy Round W    R
+		
+		Busy:
+		0	idle
+		1	busy
+		
+		Round:
+		0	first round
+		1	internal round
+		
+		W:
+		0       No-op
+		1	write data
+		
+		R:
+		0	No-op
+		1	read data
+			
+	*/
+	
+
+    	reg	[3:0]	cmd;
+    	wire	[3:0]	cmd_o;
+    	
+    	reg	[31:0]	text_o;
+    	
+    	reg	[6:0]	round;
+    	wire	[6:0]	round_plus_1;
+    	
+    	reg	[2:0]	read_counter;
+    	
+    	reg	[31:0]	H0,H1,H2,H3,H4;
+    	reg	[31:0]	W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14;
+    	reg	[31:0]	Wt,Kt;
+    	reg	[31:0]	A,B,C,D,E;
+
+    	reg		busy;
+    	
+    	assign cmd_o = cmd;
+    	always @ (posedge clk_i)
+    	begin
+    		if (rst_i)
+    			cmd <= 'b0;
+    		else
+    		if (cmd_w_i)
+    			cmd[2:0] <= cmd_i[2:0];		// busy bit can't write
+    		else
+    		begin
+    			cmd[3] <= busy;			// update busy bit
+    			if (~busy)
+    				cmd[1:0] <= 2'b00;	// hardware auto clean R/W bits
+    		end
+    	end
+    	
+    	// Hash functions
+	wire [31:0] SHA1_f1_BCD,SHA1_f2_BCD,SHA1_f3_BCD,SHA1_Wt_1;
+	wire [31:0] SHA1_ft_BCD;
+	wire [31:0] next_Wt,next_A,next_C;
+	wire [159:0] SHA1_result;
+	
+	assign SHA1_f1_BCD = (B & C) ^ (~B & D);
+	assign SHA1_f2_BCD = B ^ C ^ D;
+	assign SHA1_f3_BCD = (B & C) ^ (C & D) ^ (B & D);
+	
+	assign SHA1_ft_BCD = (round < 'd21) ? SHA1_f1_BCD : (round < 'd41) ? SHA1_f2_BCD : (round < 'd61) ? SHA1_f3_BCD : SHA1_f2_BCD;
+	
+    	assign SHA1_Wt_1 = {W13 ^ W8 ^ W2 ^ W0};
+
+	assign next_Wt = {SHA1_Wt_1[30:0],SHA1_Wt_1[31]};	// NSA fix added
+	assign next_A = {A[26:0],A[31:27]} + SHA1_ft_BCD + E + Kt + Wt;
+	assign next_C = {B[1:0],B[31:2]};
+	
+	assign SHA1_result   = {A,B,C,D,E};
+	
+	assign round_plus_1 = round + 1;
+	
+	//------------------------------------------------------------------	
+	// SHA round
+	//------------------------------------------------------------------
+	always @(posedge clk_i)
+	begin
+		if (rst_i)
+		begin
+			round <= 'd0;
+			busy <= 'b0;
+
+			W0  <= 'b0;
+			W1  <= 'b0;
+			W2  <= 'b0;
+			W3  <= 'b0;
+			W4  <= 'b0;
+			W5  <= 'b0;
+			W6  <= 'b0;
+			W7  <= 'b0;
+			W8  <= 'b0;
+			W9  <= 'b0;
+			W10 <= 'b0;
+			W11 <= 'b0;
+			W12 <= 'b0;
+			W13 <= 'b0;
+			W14 <= 'b0;
+			Wt  <= 'b0;
+			
+			A <= 'b0;
+			B <= 'b0;
+			C <= 'b0;
+			D <= 'b0;
+			E <= 'b0;
+			
+			H0 <= 'b0;
+			H1 <= 'b0;
+			H2 <= 'b0;
+			H3 <= 'b0;
+			H4 <= 'b0;
+
+		end
+		else
+		begin
+			case (round)
+			
+			'd0:
+				begin
+					if (cmd[1])
+					begin
+						W0 <= text_i;
+						Wt <= text_i;
+						busy <= 'b1;
+						round <= round_plus_1;
+                                               	
+						case (cmd[2])
+							1'b0:	// sha-1 first message
+								begin
+									A <= `SHA1_H0;
+									B <= `SHA1_H1;
+									C <= `SHA1_H2;
+									D <= `SHA1_H3;
+									E <= `SHA1_H4;
+									
+									H0 <= `SHA1_H0;
+									H1 <= `SHA1_H1;
+									H2 <= `SHA1_H2;
+									H3 <= `SHA1_H3;
+									H4 <= `SHA1_H4;
+								end
+							1'b1:	// sha-1 internal message
+								begin
+									H0 <= A;
+									H1 <= B;
+									H2 <= C;
+									H3 <= D;
+									H4 <= E;
+								end
+						endcase
+					end
+					else
+					begin	// IDLE
+						round <= 'd0;
+					end
+				end
+			'd1:
+				begin
+					W1 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd2:
+				begin
+					W2 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd3:
+				begin
+					W3 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd4:
+				begin
+					W4 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd5:
+				begin
+					W5 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd6:
+				begin
+					W6 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd7:
+				begin
+					W7 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd8:
+				begin
+					W8 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd9:
+				begin
+					W9 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd10:
+				begin
+					W10 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd11:
+				begin
+					W11 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd12:
+				begin
+					W12 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd13:
+				begin
+					W13 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd14:
+				begin
+					W14 <= text_i;
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd15:
+				begin
+					Wt <= text_i;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd16,
+			'd17,
+			'd18,
+			'd19,
+			'd20,
+			'd21,
+			'd22,
+			'd23,
+			'd24,
+			'd25,
+			'd26,
+			'd27,
+			'd28,
+			'd29,
+			'd30,
+			'd31,
+			'd32,
+			'd33,
+			'd34,
+			'd35,
+			'd36,
+			'd37,
+			'd38,
+			'd39,
+			'd40,
+			'd41,
+			'd42,
+			'd43,
+			'd44,
+			'd45,
+			'd46,
+			'd47,
+			'd48,
+			'd49,
+			'd50,
+			'd51,
+			'd52,
+			'd53,
+			'd54,
+			'd55,
+			'd56,
+			'd57,
+			'd58,
+			'd59,
+			'd60,
+			'd61,
+			'd62,
+			'd63,
+			'd64,
+			'd65,
+			'd66,
+			'd67,
+			'd68,
+			'd69,
+			'd70,
+			'd71,
+			'd72,
+			'd73,
+			'd74,
+			'd75,
+			'd76,
+			'd77,
+			'd78,
+			'd79:
+				begin
+					W0  <= W1;
+					W1  <= W2;
+					W2  <= W3;
+					W3  <= W4;
+					W4  <= W5;
+					W5  <= W6;
+					W6  <= W7;
+					W7  <= W8;
+					W8  <= W9;
+					W9  <= W10;
+					W10 <= W11;
+					W11 <= W12;
+					W12 <= W13;
+					W13 <= W14;
+					W14 <= Wt;
+					Wt  <= next_Wt;
+					
+					E <= D;
+					D <= C;
+					C <= next_C;
+					B <= A;
+					A <= next_A;
+						
+					round <= round_plus_1;
+				end
+			'd80:
+				begin
+					A <= next_A + H0;
+					B <= A + H1;
+					C <= next_C + H2;
+					D <= C + H3;
+					E <= D + H4;
+					round <= 'd0;
+					busy <= 'b0;
+				end
+			default:
+				begin
+					round <= 'd0;
+					busy <= 'b0;
+				end
+			endcase
+		end	
+	end 
+	
+	
+	//------------------------------------------------------------------	
+	// Kt generator
+	//------------------------------------------------------------------	
+	always @ (posedge clk_i)
+	begin
+		if (rst_i)
+		begin
+			Kt <= 'b0;
+		end
+		else
+		begin
+			if (round < 'd20)
+				Kt <= `SHA1_K0;
+			else
+			if (round < 'd40)
+				Kt <= `SHA1_K1;
+			else
+			if (round < 'd60)
+				Kt <= `SHA1_K2;
+			else
+				Kt <= `SHA1_K3;
+		end
+	end
+
+	//------------------------------------------------------------------	
+	// read result 
+	//------------------------------------------------------------------	
+	always @ (posedge clk_i)
+	begin
+		if (rst_i)
+		begin
+			text_o <= 'b0;
+			read_counter <= 'b0;
+		end
+		else
+		begin
+			if (cmd[0])
+			begin
+				read_counter <= 'd4;	// sha-1 	160/32=5
+			end
+			else
+			begin
+			if (~busy)
+			begin
+				case (read_counter)
+					'd4:	text_o <= SHA1_result[5*32-1:4*32];
+					'd3:	text_o <= SHA1_result[4*32-1:3*32];
+					'd2:	text_o <= SHA1_result[3*32-1:2*32];
+					'd1:	text_o <= SHA1_result[2*32-1:1*32];
+					'd0:	text_o <= SHA1_result[1*32-1:0*32];
+					default:text_o <= 'b0;
+				endcase
+				if (|read_counter)
+					read_counter <= read_counter - 'd1;
+			end
+			else
+			begin
+				text_o <= 'b0;
+			end
+			end
+		end
+	end
+	
+endmodule
+ 
\ No newline at end of file
diff --git a/BENCHMARK/sha256/rtl/sha256.v b/BENCHMARK/sha256/rtl/sha256.v
new file mode 100644
index 0000000..56558b6
--- /dev/null
+++ b/BENCHMARK/sha256/rtl/sha256.v
@@ -0,0 +1,774 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SHA-256                                                    ////
+////  Secure Hash Algorithm (SHA-256)                            ////
+////                                                             ////
+////  Author: marsgod                                            ////
+////          marsgod@opencores.org                              ////
+////                                                             ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/cores/sha_core/  ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2000-2002 marsgod                             ////
+////                         marsgod@opencores.org               ////
+////                                                             ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+`define SHA256_H0 32'h6a09e667
+`define SHA256_H1 32'hbb67ae85
+`define SHA256_H2 32'h00000000
+`define SHA256_H3 32'ha54ff53a
+`define SHA256_H4 32'h510e527f
+`define SHA256_H5 32'h00000000
+`define SHA256_H6 32'h1f83d9ab
+`define SHA256_H7 32'h00000000
+
+`define K00 32'h00000000
+`define K01 32'h71374491
+`define K02 32'hb5c0fbcf
+`define K03 32'he9b5dba5
+`define K04 32'h3956c25b
+`define K05 32'h59f111f1
+`define K06 32'h923f82a4
+`define K07 32'hab1c5ed5
+`define K08 32'hd807aa98
+`define K09 32'h12835b01
+`define K10 32'h243185be
+`define K11 32'h00000000
+`define K12 32'h72be5d74
+`define K13 32'h80deb1fe
+`define K14 32'h9bdc06a7
+`define K15 32'hc19bf174
+`define K16 32'h00000000
+`define K17 32'hefbe4786
+`define K18 32'h0fc19dc6
+`define K19 32'h240ca1cc
+`define K20 32'h2de92c6f
+`define K21 32'h00000000
+`define K22 32'h5cb0a9dc
+`define K23 32'h5cb0a9dc //
+`define K24 32'h983e5152
+`define K25 32'ha831c66d
+`define K26 32'hb00327c8
+`define K27 32'hbf597fc7
+`define K28 32'hc6e00bf3
+`define K29 32'hd5a79147
+`define K30 32'h06ca6351
+`define K31 32'h14292967
+`define K32 32'h27b70a85
+`define K33 32'h2e1b2138
+`define K34 32'h4d2c6dfc
+`define K35 32'h53380d13
+`define K36 32'h650a7354
+`define K37 32'h766a0abb
+`define K38 32'h81c2c92e
+`define K39 32'h92722c85
+`define K40 32'ha2bfe8a1
+`define K41 32'ha81a664b
+`define K42 32'hc24b8b70
+`define K43 32'hc76c51a3
+`define K44 32'hd192e819
+`define K45 32'hd6990624
+`define K46 32'hf40e3585
+`define K47 32'h106aa070
+`define K48 32'h19a4c116
+`define K49 32'h1e376c08
+`define K50 32'h2748774c
+`define K51 32'h34b0bcb5
+`define K52 32'h391c0cb3
+`define K53 32'h4ed8aa4a
+`define K54 32'h5b9cca4f
+`define K55 32'h682e6ff3
+`define K56 32'h748f82ee
+`define K57 32'h78a5636f
+`define K58 32'h84c87814
+`define K59 32'h8cc70208
+`define K60 32'h90befffa
+`define K61 32'ha4506ceb
+`define K62 32'hbef9a3f7
+`define K63 32'hc67178f2
+
+module sha256 (clk_i, rst_i, text_i, text_o, cmd_i, cmd_w_i, cmd_o);
+
+        input           clk_i;  // global clock input
+        input           rst_i;  // global reset input , active high
+        
+        input   [9:0]  text_i; // text input 32bit
+        output  [9:0]  text_o; // text output 32bit
+        
+        input   [2:0]   cmd_i;  // command input
+        input           cmd_w_i;// command input write enable
+        output  [3:0]   cmd_o;  // command output(status)
+
+        /*
+                cmd
+                Busy Round W R
+
+                bit3 bit2  bit1 bit0
+                Busy Round W    R
+                
+                Busy:
+                0       idle
+                1       busy
+                
+                Round:
+                0       first round
+                1       internal round
+                
+                W:
+                0       No-op
+                1       write data
+                
+                R:
+                0       No-op
+                1       read data
+                        
+        */
+        
+
+        reg     [3:0]   cmd;
+        wire    [3:0]   cmd_o;
+        
+        reg     [9:0]  text_o;
+        
+        reg     [6:0]   round;
+        wire    [6:0]   round_plus_1;
+        
+        reg     [2:0]   read_counter;
+        
+        reg     [31:0]  H0,H1,H2,H3,H4,H5,H6,H7;
+        reg     [31:0]  W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14;
+        reg     [31:0]  Wt,Kt;
+        reg     [31:0]  A,B,C,D,E,F,G,H;
+
+        reg             busy;
+        
+        assign cmd_o = cmd;
+        always @ (posedge clk_i)
+        begin
+                if (rst_i)
+                        cmd <= 'b0;
+                else
+                if (cmd_w_i)
+                        cmd[2:0] <= cmd_i[2:0];         // busy bit can't write
+                else
+                begin
+                        cmd[3] <= busy;                 // update busy bit
+                        if (~busy)
+                                cmd[1:0] <= 2'b00;      // hardware auto clean R/W bits
+                end
+        end
+        
+        wire [31:0] f1_EFG_32,f2_ABC_32,f3_A_32,f4_E_32,f5_W1_32,f6_W14_32,T1_32,T2_32;
+        wire [31:0] next_Wt,next_E,next_A;
+        wire [255:0] SHA256_result;
+        
+        assign f1_EFG_32 = (E & F);
+
+        assign f2_ABC_32 = (A & B);
+        
+        assign f3_A_32 = {A[1:0],A[31:2]} ^ {A[12:0],A[31:13]} ^ {A[21:0],A[31:22]};
+        
+        assign f4_E_32 = {E[5:0],E[31:6]} ^ {E[10:0],E[31:11]} ^ {E[24:0],E[31:25]};
+        
+        assign f5_W1_32 = 0;// {W1[6:0],W1[31:7]} ^ {W1[17:0],W1[31:18]} ^ {3'b000,W1[31:3]};
+        
+        assign f6_W14_32 = 0; //{W14[16:0],W14[31:17]} ^ {10'b00_0000_0000,W14[31:10]};
+        
+        
+        assign T1_32 = f4_E_32 + f1_EFG_32 + Kt + Wt;
+        
+        assign T2_32 = f3_A_32 + f2_ABC_32;
+        
+        assign next_Wt = f6_W14_32 + f5_W1_32;
+        assign next_E = D[31:0] + T1_32;
+        assign next_A = T1_32 + T2_32;
+        
+
+        assign SHA256_result = {A,B,C,D,E,F,G,H};
+
+        assign round_plus_1 = round + 1;
+        
+        //------------------------------------------------------------------    
+        // SHA round
+        //------------------------------------------------------------------
+        always @(posedge clk_i)
+        begin
+                if (rst_i)
+                begin
+                        round <= 'd0;
+                        busy <= 'b0;
+
+                        W0  <= 'b0;
+                        W1  <= 'b0;
+                        W2  <= 'b0;
+                        W3  <= 'b0;
+                        W4  <= 'b0;
+                        W5  <= 'b0;
+                        W6  <= 'b0;
+                        W7  <= 'b0;
+                        W8  <= 'b0;
+                        W9  <= 'b0;
+                        W10 <= 'b0;
+                        W11 <= 'b0;
+                        W12 <= 'b0;
+                        W13 <= 'b0;
+                        W14 <= 'b0;
+                        Wt  <= 'b0;
+                        
+                        A <= 'b0;
+                        B <= 'b0;
+                        C <= 'b0;
+                        D <= 'b0;
+                        E <= 'b0;
+                        F <= 'b0;
+                        G <= 'b0;
+                        H <= 'b0;
+
+                        H0 <= 'b0;
+                        H1 <= 'b0;
+                        H2 <= 'b0;
+                        H3 <= 'b0;
+                        H4 <= 'b0;
+                        H5 <= 'b0;
+                        H6 <= 'b0;
+                        H7 <= 'b0;
+                end
+                else
+                begin
+                        case (round)
+                        
+                        'd0:
+                                begin
+                                        if (cmd[1])
+                                        begin
+                                                W0 <= text_i;
+                                                Wt <= text_i;
+                                                busy <= 'b1;
+                                                round <= round_plus_1;
+                                                
+                                                case (cmd[2])
+                                                        1'b0:   // sha-256 first message
+                                                                begin
+                                                                        A <= `SHA256_H0;
+                                                                        B <= `SHA256_H1;
+                                                                        C <= `SHA256_H2;
+                                                                        D <= `SHA256_H3;
+                                                                        E <= `SHA256_H4;
+                                                                        F <= `SHA256_H5;
+                                                                        G <= `SHA256_H6;
+                                                                        H <= `SHA256_H7;
+
+                                                                        H0 <= `SHA256_H0;
+                                                                        H1 <= `SHA256_H1;
+                                                                        H2 <= `SHA256_H2;
+                                                                        H3 <= `SHA256_H3;
+                                                                        H4 <= `SHA256_H4;
+                                                                        H5 <= `SHA256_H5;
+                                                                        H6 <= `SHA256_H6;
+                                                                        H7 <= `SHA256_H7;
+                                                                end
+                                                        1'b1:   // sha-256 internal message
+                                                                begin
+                                                                        H0 <= A;
+                                                                        H1 <= B;
+                                                                        H2 <= C;
+                                                                        H3 <= D;
+                                                                        H4 <= E;
+                                                                        H5 <= F;
+                                                                        H6 <= G;
+                                                                        H7 <= H;
+                                                                end
+                                                endcase
+                                        end
+                                        else
+                                        begin   // IDLE
+                                                round <= 'd0;
+                                        end
+                                end
+                        'd1:
+                                begin
+                                        W1 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd2:
+                                begin
+                                        W2 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd3:
+                                begin
+                                        W3 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd4:
+                                begin
+                                        W4 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd5:
+                                begin
+                                        W5 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd6:
+                                begin
+                                        W6 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd7:
+                                begin
+                                        W7 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd8:
+                                begin
+                                        W8 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd9:
+                                begin
+                                        W9 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd10:
+                                begin
+                                        W10 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd11:
+                                begin
+                                        W11 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd12:
+                                begin
+                                        W12 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd13:
+                                begin
+                                        W13 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd14:
+                                begin
+                                        W14 <= text_i;
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd15:
+                                begin
+                                        Wt <= text_i;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd16,
+                        'd17,
+                        'd18,
+                        'd19,
+                        'd20,
+                        'd21,
+                        'd22,
+                        'd23,
+                        'd24,
+                        'd25,
+                        'd26,
+                        'd27,
+                        'd28,
+                        'd29,
+                        'd30,
+                        'd31,
+                        'd32,
+                        'd33,
+                        'd34,
+                        'd35,
+                        'd36,
+                        'd37,
+                        'd38,
+                        'd39,
+                        'd40,
+                        'd41,
+                        'd42,
+                        'd43,
+                        'd44,
+                        'd45,
+                        'd46,
+                        'd47,
+                        'd48,
+                        'd49,
+                        'd50,
+                        'd51,
+                        'd52,
+                        'd53,
+                        'd54,
+                        'd55,
+                        'd56,
+                        'd57,
+                        'd58,
+                        'd59,
+                        'd60,
+                        'd61,
+                        'd62,
+                        'd63:
+                                begin
+                                        W0  <= W1;
+                                        W1  <= W2;
+                                        W2  <= W3;
+                                        W3  <= W4;
+                                        W4  <= W5;
+                                        W5  <= W6;
+                                        W6  <= W7;
+                                        W7  <= W8;
+                                        W8  <= W9;
+                                        W9  <= W10;
+                                        W10 <= W11;
+                                        W11 <= W12;
+                                        W12 <= W13;
+                                        W13 <= W14;
+                                        W14 <= Wt;
+                                        Wt  <= next_Wt;
+                                        
+                                        H <= G;
+                                        G <= F;
+                                        F <= E;
+                                        E <= next_E;
+                                        D <= C;
+                                        C <= B;
+                                        B <= A;
+                                        A <= next_A;
+                                                
+                                        round <= round_plus_1;
+                                end
+                        'd64:
+                                begin
+                                        A <= next_A + H0;
+                                        B <= A + H1;
+                                        C <= B + H2;
+                                        D <= C + H3;
+                                        E <= next_E + H4;
+                                        F <= E + H5;
+                                        G <= F + H6;
+                                        H <= G + H7;
+                                        round <= 'd0;
+                                        busy <= 'b0;
+                                end
+                        default:
+                                begin
+                                        round <= 'd0;
+                                        busy <= 'b0;
+                                end
+                        endcase
+                end     
+        end 
+        
+        
+        //------------------------------------------------------------------    
+        // Kt generator
+        //------------------------------------------------------------------    
+        always @ (posedge clk_i)
+        begin
+                if (rst_i)
+                begin
+                        Kt <= 'b0;
+                end
+                else
+                begin
+                        case (round)
+                                'd00:   Kt <= `K00;
+                                'd01:   Kt <= `K01;
+                                'd02:   Kt <= `K02;
+                                'd03:   Kt <= `K03;
+                                'd04:   Kt <= `K04;
+                                'd05:   Kt <= `K05;
+                                'd06:   Kt <= `K06;
+                                'd07:   Kt <= `K07;
+                                'd08:   Kt <= `K08;
+                                'd09:   Kt <= `K09;
+                                'd10:   Kt <= `K10;
+                                'd11:   Kt <= `K11;
+                                'd12:   Kt <= `K12;
+                                'd13:   Kt <= `K13;
+                                'd14:   Kt <= `K14;
+                                'd15:   Kt <= `K15;
+                                'd16:   Kt <= `K16;
+                                'd17:   Kt <= `K17;
+                                'd18:   Kt <= `K18;
+                                'd19:   Kt <= `K19;
+                                'd20:   Kt <= `K20;
+                                'd21:   Kt <= `K21;
+                                'd22:   Kt <= `K22;
+                                'd23:   Kt <= `K23;
+                                'd24:   Kt <= `K24;
+                                'd25:   Kt <= `K25;
+                                'd26:   Kt <= `K26;
+                                'd27:   Kt <= `K27;
+                                'd28:   Kt <= `K28;
+                                'd29:   Kt <= `K29;
+                                'd30:   Kt <= `K30;
+                                'd31:   Kt <= `K31;
+                                'd32:   Kt <= `K32;
+                                'd33:   Kt <= `K33;
+                                'd34:   Kt <= `K34;
+                                'd35:   Kt <= `K35;
+                                'd36:   Kt <= `K36;
+                                'd37:   Kt <= `K37;
+                                'd38:   Kt <= `K38;
+                                'd39:   Kt <= `K39;
+                                'd40:   Kt <= `K40;
+                                'd41:   Kt <= `K41;
+                                'd42:   Kt <= `K42;
+                                'd43:   Kt <= `K43;
+                                'd44:   Kt <= `K44;
+                                'd45:   Kt <= `K45;
+                                'd46:   Kt <= `K46;
+                                'd47:   Kt <= `K47;
+                                'd48:   Kt <= `K48;
+                                'd49:   Kt <= `K49;
+                                'd50:   Kt <= `K50;
+                                'd51:   Kt <= `K51;
+                                'd52:   Kt <= `K52;
+                                'd53:   Kt <= `K53;
+                                'd54:   Kt <= `K54;
+                                'd55:   Kt <= `K55;
+                                'd56:   Kt <= `K56;
+                                'd57:   Kt <= `K57;
+                                'd58:   Kt <= `K58;
+                                'd59:   Kt <= `K59;
+                                'd60:   Kt <= `K60;
+                                'd61:   Kt <= `K61;
+                                'd62:   Kt <= `K62;
+                                'd63:   Kt <= `K63;
+                                default:Kt <= 'd0;
+                        endcase
+                end
+        end
+
+        //------------------------------------------------------------------    
+        // read result 
+        //------------------------------------------------------------------    
+        always @ (posedge clk_i)
+        begin
+                if (rst_i)
+                begin
+                        text_o <= 'b0;
+                        read_counter <= 'b0;
+                end
+                else
+                begin
+                        if (cmd[0])
+                        begin
+                                read_counter <= 'd7;    // sha-256      256/32=8
+                        end
+                        else
+                        begin
+                        if (~busy)
+                        begin
+                                case (read_counter)
+                                        'd7:    text_o <= SHA256_result[8*32-1:7*32];
+                                        'd6:    text_o <= SHA256_result[7*32-1:6*32];
+                                        'd5:    text_o <= SHA256_result[6*32-1:5*32];
+                                        'd4:    text_o <= SHA256_result[5*32-1:4*32];
+                                        'd3:    text_o <= SHA256_result[4*32-1:3*32];
+                                        'd2:    text_o <= SHA256_result[3*32-1:2*32];
+                                        'd1:    text_o <= SHA256_result[2*32-1:1*32];
+                                        'd0:    text_o <= SHA256_result[1*32-1:0*32];
+                                        default:text_o <= 'b0;
+                                endcase
+                                if (|read_counter)
+                                        read_counter <= read_counter - 'd1;
+                        end
+                        else
+                        begin
+                                text_o <= 'b0;
+                        end
+                        end
+                end
+        end
+        
+endmodule
+ 
diff --git a/BENCHMARK/sha256/sha256_yosys.blif b/BENCHMARK/sha256/sha256_yosys.blif
new file mode 100644
index 0000000..2202a50
--- /dev/null
+++ b/BENCHMARK/sha256/sha256_yosys.blif
@@ -0,0 +1,12211 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model sha256
+.inputs clk_i rst_i text_i(0) text_i(1) text_i(2) text_i(3) text_i(4) text_i(5) text_i(6) text_i(7) text_i(8) text_i(9) cmd_i(0) cmd_i(1) cmd_i(2) cmd_w_i
+.outputs text_o(0) text_o(1) text_o(2) text_o(3) text_o(4) text_o(5) text_o(6) text_o(7) text_o(8) text_o(9) cmd_o(0) cmd_o(1) cmd_o(2) cmd_o(3)
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_1 a=$auto$hilomap.cc:39:hilomap_worker$30534
+.subckt logic_0 a=G(10)
+.subckt in_buff A=clk_i Q=$iopadmap$clk_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=cmd_i(0) Q=$iopadmap$cmd_i(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=cmd_i(1) Q=$iopadmap$cmd_i(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=cmd_i(2) Q=$iopadmap$cmd_i(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=cmd(0) Q=cmd_o(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cmd(1) Q=cmd_o(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cmd(2) Q=cmd_o(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=cmd(3) Q=cmd_o(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt in_buff A=cmd_w_i Q=$iopadmap$cmd_w_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=rst_i Q=$iopadmap$rst_i
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(0) Q=$iopadmap$text_i(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(1) Q=$iopadmap$text_i(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(2) Q=$iopadmap$text_i(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(3) Q=$iopadmap$text_i(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(4) Q=$iopadmap$text_i(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(5) Q=$iopadmap$text_i(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(6) Q=$iopadmap$text_i(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(7) Q=$iopadmap$text_i(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(8) Q=$iopadmap$text_i(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=text_i(9) Q=$iopadmap$text_i(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=$iopadmap$text_o(0) Q=text_o(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$text_o(1) Q=text_o(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$text_o(2) Q=text_o(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$text_o(3) Q=text_o(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$text_o(4) Q=text_o(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$text_o(5) Q=text_o(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$text_o(6) Q=text_o(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$text_o(7) Q=text_o(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$text_o(8) Q=text_o(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$text_o(9) Q=text_o(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt ff CQZ=A(31) D=A_ff_CQZ_D(31) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(30) D=A_ff_CQZ_D(30) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(21) D=A_ff_CQZ_D(21) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(20) D=A_ff_CQZ_D(20) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(19) D=A_ff_CQZ_D(19) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(18) D=A_ff_CQZ_D(18) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(17) D=A_ff_CQZ_D(17) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(16) D=A_ff_CQZ_D(16) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(15) D=A_ff_CQZ_D(15) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(14) D=A_ff_CQZ_D(14) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(13) D=A_ff_CQZ_D(13) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(12) D=A_ff_CQZ_D(12) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(29) D=A_ff_CQZ_D(29) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(11) D=A_ff_CQZ_D(11) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(10) D=A_ff_CQZ_D(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(9) D=A_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(8) D=A_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(7) D=A_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(6) D=A_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(5) D=A_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(4) D=A_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(3) D=A_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(2) D=A_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(28) D=A_ff_CQZ_D(28) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(1) D=A_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(0) D=A_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(27) D=A_ff_CQZ_D(27) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(26) D=A_ff_CQZ_D(26) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(25) D=A_ff_CQZ_D(25) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(24) D=A_ff_CQZ_D(24) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(23) D=A_ff_CQZ_D(23) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=A(22) D=A_ff_CQZ_D(22) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=$iopadmap$rst_i I1=H0_ff_CQZ_D(14) I2=A_ff_CQZ_D_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110111000000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_1_I1 I2=A_ff_CQZ_D_LUT4_O_1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_10_I1 I2=A_ff_CQZ_D_LUT4_O_10_I2 I3=A_ff_CQZ_D_LUT4_O_10_I3 O=A_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000011
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(0) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(0) I3=A_ff_CQZ_D_LUT4_O_10_I3 O=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=F(0) I1=E(0) I2=Wt(0) I3=Kt(0) O=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=E(25) I2=E(11) I3=E(6) O=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I3 I2=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I0 I3=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(0) I3=B(0) O=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=A(22) I2=A(13) I3=A(2) O=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_11_I1 I2=A_ff_CQZ_D_LUT4_O_11_I2 I3=A_ff_CQZ_D_LUT4_O_11_I3 O=A_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000011
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=H0(31) I3=A_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I1=H0(30) I2=A_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(31) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(22) I2=E(8) I3=E(3) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(29) I1=E(29) I2=Wt(29) I3=Kt(29) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(28) I1=Kt(28) I2=F(28) I3=E(28) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(23) I2=E(9) I3=E(4) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(30) I1=E(30) I2=Wt(30) I3=Kt(30) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(29) I1=Kt(29) I2=F(29) I3=E(29) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=E(5) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(24) I2=E(10) I3=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=F(31) I1=E(31) I2=Wt(31) I3=Kt(31) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=Wt(30) I1=Kt(30) I2=F(30) I3=E(30) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I2_LUT4_O_I1 I2=A(1) I3=A(12) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=B(30) I3=A(30) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A(21) I2=A(31) I3=B(31) O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_12_I2 I3=A_ff_CQZ_D_LUT4_O_12_I3 O=A_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(28) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I2=H0(28) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_13_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_13_I2 I3=A_ff_CQZ_D_LUT4_O_13_I3 O=A_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_13_I0 I1=H0(27) I2=A_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(27) I3=A_ff_CQZ_D_LUT4_O_13_I0 O=A_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I1_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=A(27) I3=B(27) O=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_O_LUT4_I0_O I1=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=B(26) I3=A(26) O=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I3 I2=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_O_LUT4_I0_O I3=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=A(26) I3=B(26) O=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(28) I2=A(16) I3=A(7) O=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_1_O I1=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=B(25) I3=A(25) O=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_14_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(27) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(26) I3=A_ff_CQZ_D_LUT4_O_14_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_14_I1 I2=A_ff_CQZ_D_LUT4_O_14_I2 I3=A_ff_CQZ_D_LUT4_O_14_I3 O=A_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I1 I1=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3 I2=H0(25) I3=A_ff_CQZ_D_LUT4_O_14_I1 O=A_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(26) I3=A_ff_CQZ_D_LUT4_O_14_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_14_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_13_I0_LUT4_O_I2_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_O_LUT4_I0_O O=A_ff_CQZ_D_LUT4_O_14_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=H0(25) I2=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_14_I1_LUT4_O_I3 I2=H_ff_CQZ_D_LUT4_O_I3 I3=H0_ff_CQZ_D(26) O=A_ff_CQZ_D_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101110110000
+.subckt LUT4 I0=$iopadmap$rst_i I1=A_ff_CQZ_D_LUT4_O_15_I1 I2=H0_ff_CQZ_D(25) I3=A_ff_CQZ_D_LUT4_O_I2 O=A_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I1 I2=H0(25) I3=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=B(25) I1=A(25) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_1_O I3=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=G(10) I1=A(27) I2=A(15) I3=A(6) O=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_O_I3 I2=B(24) I3=A(24) O=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_16_I2 I3=A_ff_CQZ_D_LUT4_O_16_I3 O=A_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0 I1=H0(24) I2=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0 I3=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(24) I3=A_ff_CQZ_D_LUT4_O_16_I0 O=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_1_O O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(22) I3=B(22) O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=A(24) I2=A(12) I3=A(3) O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_O I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(30) I2=E(17) I3=E(3) O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(24) I1=E(24) I2=Wt(24) I3=Kt(24) O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(23) I1=Kt(23) I2=F(23) I3=E(23) O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110101011111
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I2_LUT4_O_I1 I2=B(23) I3=A(23) O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I2_LUT4_O_I1 I2=A(23) I3=B(23) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(25) I2=A(13) I3=A(4) O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=B(24) I1=A(24) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=G(10) I1=A(26) I2=A(14) I3=A(5) O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(24) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_16_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(23) I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_17_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I2=H0(22) I3=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I3=H0(23) O=A_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_17_I2 I3=A_ff_CQZ_D_LUT4_O_17_I3 O=A_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(22) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_17_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I2=H0(22) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_18_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_18_I2 I3=A_ff_CQZ_D_LUT4_O_18_I3 O=A_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_18_I0 I1=H0(21) I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_I0_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_17_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I0_O I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(30) I2=E(25) I3=E(12) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(19) I1=E(19) I2=Wt(19) I3=Kt(19) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(18) I1=Kt(18) I2=F(18) I3=E(18) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(31) I2=E(26) I3=E(13) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(20) I1=E(20) I2=Wt(20) I3=Kt(20) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(19) I1=Kt(19) I2=F(19) I3=E(19) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A(23) I2=A(11) I3=A(2) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(21) I3=B(21) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00110101
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A(22) I2=A(10) I3=A(1) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(20) I3=B(20) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_O I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=B(19) I3=A(19) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=A(19) I3=B(19) O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(21) I2=A(9) I3=A(0) O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I0_O O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(21) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_18_I0 I2=H0(21) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_18_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_I0_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_19_I2 I3=A_ff_CQZ_D_LUT4_O_19_I3 O=A_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(19) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_O I2=H0(19) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_19_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_O I2=H0(19) I3=A_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I0_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I0_O I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=H0(20) O=A_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=H_ff_CQZ_D_LUT4_O_I3 I3=H0_ff_CQZ_D(30) O=A_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101110110000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I3=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I1=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=B(29) I3=A(29) O=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A(31) I2=A(19) I3=A(10) O=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=A(30) I3=B(30) O=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(20) I2=A(11) I3=A(0) O=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=H0(30) I3=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I2=H0(28) I3=A_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(29) I3=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_2_I1 I2=A_ff_CQZ_D_LUT4_O_2_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_20_I2 I3=A_ff_CQZ_D_LUT4_O_20_I3 O=A_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I0 I1=H0(18) I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_I0_I2 I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3 I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_I2 I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I0 I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010111000011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_O O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=A(18) I3=B(18) O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(31) I2=A(20) I3=A(8) O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I0 I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=B(17) I3=A(17) O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A(30) I2=A(19) I3=A(7) O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_I2 I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_O O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=B(16) I3=A(16) O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A(29) I2=A(18) I3=A(6) O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(18) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_20_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_20_I0 I2=H0(18) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_I0_I2 I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_20_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_21_I2 I3=A_ff_CQZ_D_LUT4_O_21_I3 O=A_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(16) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I2=H0(16) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I2=H0(16) I3=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I1=H0(15) I2=A_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=$iopadmap$rst_i I1=A_ff_CQZ_D_LUT4_O_22_I1 I2=H0_ff_CQZ_D(13) I3=A_ff_CQZ_D_LUT4_O_I2 O=A_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1 I2=H0(13) I3=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1 I1=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I3 I2=H0(13) I3=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=A(13) I3=B(13) O=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_23_I2 I3=A_ff_CQZ_D_LUT4_O_23_I3 O=A_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0 I1=H0(12) I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_I0_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=H0(11) I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=A_ff_CQZ_D_LUT4_O_24_I2_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(12) I3=B(12) O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=A(25) I2=A(14) I3=A(2) O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011010001001011
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(22) I2=E(17) I3=E(4) O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(11) I1=E(11) I2=Wt(11) I3=Kt(11) O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(10) I1=Kt(10) I2=F(10) I3=E(10) O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=A(10) I2=B(10) I3=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1 I2=A(11) I3=B(11) O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01001011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(12) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_23_I0 I2=H0(12) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_I0_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_23_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_24_I2 I3=A_ff_CQZ_D_LUT4_O_24_I3 O=A_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_24_I2_LUT4_O_I1 I2=H_ff_CQZ_D_LUT4_O_I3 I3=H0_ff_CQZ_D(11) O=A_ff_CQZ_D_LUT4_O_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101110110000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=A_ff_CQZ_D_LUT4_O_24_I2_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_24_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O O=A_ff_CQZ_D_LUT4_O_24_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_24_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_25_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O I2=H0(10) I3=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I1=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=H0(11) O=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=A(10) I3=B(10) O=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(23) I2=A(12) I3=A(0) O=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O I2=H0(10) I3=A_ff_CQZ_D_LUT4_O_25_I2_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_25_I2 I3=A_ff_CQZ_D_LUT4_O_25_I3 O=A_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_25_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O I2=H0(10) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I1=H0(9) I2=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_25_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(10) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_25_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H0_ff_CQZ_D(7) I2=A_ff_CQZ_D_LUT4_O_26_I2 I3=A_ff_CQZ_D_LUT4_O_26_I3 O=A_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_26_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I2=H0(7) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H0(6) I2=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_26_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H0_ff_CQZ_D(5) I2=A_ff_CQZ_D_LUT4_O_27_I2 I3=A_ff_CQZ_D_LUT4_O_27_I3 O=A_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_27_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 I2=H0(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_27_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H0(4) I2=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_27_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I1=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=B(4) I3=A(4) O=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=A(5) I3=B(5) O=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(27) I2=A(18) I3=A(7) O=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H0_ff_CQZ_D(4) I2=A_ff_CQZ_D_LUT4_O_28_I2 I3=A_ff_CQZ_D_LUT4_O_28_I3 O=A_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2 I2=H0(4) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H0(3) I2=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_29_I2_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_28_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I1 I1=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=B(3) I3=A(3) O=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=A(4) I3=B(4) O=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(26) I2=A(17) I3=A(6) O=A_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H0_ff_CQZ_D(3) I2=A_ff_CQZ_D_LUT4_O_29_I2 I3=A_ff_CQZ_D_LUT4_O_29_I3 O=A_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_29_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2 I2=H0(3) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H0(2) I2=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_29_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I1 I1=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=B(2) I3=A(2) O=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=A(3) I3=B(3) O=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(25) I2=A(16) I3=A(5) O=A_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1 I2=H_ff_CQZ_D_LUT4_O_I3 I3=H0_ff_CQZ_D(29) O=A_ff_CQZ_D_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101110110000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=B(27) I3=A(27) O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A(29) I2=A(17) I3=A(8) O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=B(28) I1=A(28) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I3=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=G(10) I1=A(30) I2=A(18) I3=A(9) O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=A(29) I3=B(29) O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I1=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=B(28) I3=A(28) O=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=H0(28) I1=A_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1_LUT4_O_I2_LUT4_I1_1_O I3=A_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(29) I3=A_ff_CQZ_D_LUT4_O_2_I1_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=H0_ff_CQZ_D(23) I1=A_ff_CQZ_D_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_3_I2 I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H0_ff_CQZ_D(2) I2=A_ff_CQZ_D_LUT4_O_30_I2 I3=A_ff_CQZ_D_LUT4_O_30_I3 O=A_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2 I2=H0(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_30_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H0(1) I2=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_30_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_30_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1_LUT4_I2_O I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=A(2) I3=B(2) O=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(24) I2=A(15) I3=A(4) O=A_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$rst_i I1=A_ff_CQZ_D_LUT4_O_31_I1 I2=H0_ff_CQZ_D(1) I3=A_ff_CQZ_D_LUT4_O_I2 O=A_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I1 I2=H0(1) I3=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_31_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I2=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A(23) I2=A(14) I3=A(3) O=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(1) I3=B(1) O=A_ff_CQZ_D_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H0(23) I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=G(10) I1=H0(22) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I2_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_17_I3_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(27) I2=E(14) I3=E(0) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(21) I1=E(21) I2=Wt(21) I3=Kt(21) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(20) I1=Kt(20) I2=F(20) I3=E(20) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I0 I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I0 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(29) I2=E(16) I3=E(2) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(23) I1=E(23) I2=Wt(23) I3=Kt(23) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(22) I1=Kt(22) I2=F(22) I3=E(22) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(28) I2=E(15) I3=E(1) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(22) I1=E(22) I2=Wt(22) I3=Kt(22) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(21) I1=Kt(21) I2=F(21) I3=E(21) O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_1_O O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0 I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I0_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=H0_ff_CQZ_D(20) I1=A_ff_CQZ_D_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_4_I2 I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H0(20) I2=A_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H0(19) I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_I0_O I3=A_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(20) I3=A_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_I0_O O=A_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_5_I2 I3=A_ff_CQZ_D_LUT4_O_5_I3 O=A_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(17) I3=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=A(17) I3=B(17) O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=A(16) I3=B(16) O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I1_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=B(15) I3=A(15) O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=H0(16) I1=A_ff_CQZ_D_LUT4_O_21_I3_LUT4_O_I0 I2=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I1 I3=H0(17) O=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0_ff_CQZ_D(17) I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_6_I2 I3=A_ff_CQZ_D_LUT4_O_6_I3 O=A_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I2=H_ff_CQZ_D_LUT4_O_I3 I3=H0_ff_CQZ_D(15) O=A_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101110110000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=B(14) I3=A(14) O=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A(27) I2=A(16) I3=A(4) O=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=B(15) I1=A(15) I2=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I1_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=G(10) I1=A(28) I2=A(17) I3=A(5) O=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=H0(15) I1=A_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011011111111
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$rst_i I1=A_ff_CQZ_D_LUT4_O_7_I1 I2=A_ff_CQZ_D_LUT4_O_7_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I3=H0(9) O=A_ff_CQZ_D_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(8) I3=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_26_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I2=H0(7) I3=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=B(8) I3=A(8) O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(9) I3=B(9) O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=A(31) I2=A(22) I3=A(11) O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)"
+.param INIT 0000000000101011
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I3 O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010000101011
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111111101110
+.subckt LUT4 I0=$iopadmap$rst_i I1=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2 I2=H0_ff_CQZ_D(9) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=H0_ff_CQZ_D(8) I1=A_ff_CQZ_D_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_8_I2 I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I0 I1=H0(8) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110010100011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O I2=A_ff_CQZ_D_LUT4_O_26_I3_LUT4_O_I0 I3=H0(7) O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2 I3=H0(8) O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3 I2=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=A(7) I3=B(7) O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(29) I2=A(20) I3=A(9) O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=A(8) I3=B(8) O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=A(30) I2=A(21) I3=A(10) O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=B(7) I3=A(7) O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_I2_O I3=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=H0_ff_CQZ_D(6) I1=A_ff_CQZ_D_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_9_I2 I3=H_ff_CQZ_D_LUT4_O_I3 O=A_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100010001000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H0(6) I2=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H0(5) I2=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_27_I2_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I1 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I0 O=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I1=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=B(5) I3=A(5) O=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110111110010
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110110010
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11000101
+.subckt LUT4 I0=H0(13) I1=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=G(10) I1=H0(14) I2=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H0(14) I3=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=B(14) I1=A(14) I2=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=B(13) I3=A(13) O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=G(10) I1=A(26) I2=A(15) I3=A(3) O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_I3_O I1=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_22_I1_LUT4_O_I3_LUT4_O_I3 O=A_ff_CQZ_D_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt ff CQZ=B(31) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(31) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(30) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(30) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(21) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(21) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(20) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(20) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(19) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(19) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(18) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(18) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(17) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(17) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(16) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(16) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(15) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(15) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(14) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(14) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(13) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(13) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(12) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(12) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(29) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(29) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(11) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(11) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(10) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(9) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(9) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(8) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(8) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(7) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(7) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(6) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(6) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(5) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(5) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(4) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(4) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(3) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(3) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(2) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(2) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(28) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(28) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(1) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(1) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(0) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(0) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(27) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(27) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(26) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(26) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(25) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(25) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(24) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(24) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(23) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(23) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=B(22) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(22) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(31) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(30) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(21) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(20) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(19) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(18) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(17) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(16) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(15) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(14) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(13) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(12) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(29) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(11) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(10) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(9) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(8) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(7) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(6) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(5) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(4) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(3) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(2) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(28) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(1) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(0) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(27) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(26) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(25) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(24) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(23) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(22) I3=H_LUT4_I2_I3 O=H2_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=C(31) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(31) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(30) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(30) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(21) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(21) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(20) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(20) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(19) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(19) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(18) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(18) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(17) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(17) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(16) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(16) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(15) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(15) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(14) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(14) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(13) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(13) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(12) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(12) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(29) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(29) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(11) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(11) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(10) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(9) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(9) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(8) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(8) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(7) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(7) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(6) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(6) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(5) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(5) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(4) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(4) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(3) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(3) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(2) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(2) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(28) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(28) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(1) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(1) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(0) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(0) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(27) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(27) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(26) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(26) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(25) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(25) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(24) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(24) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(23) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(23) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=C(22) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(22) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(30) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(28) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(6) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(2) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(0) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(27) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(25) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(23) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(21) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(20) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(11) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(9) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(7) I3=H_LUT4_I2_I3 O=H3_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=D(31) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(31) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(30) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(30) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(21) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(21) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(20) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(20) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(19) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(19) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(18) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(18) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(17) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(17) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(16) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(16) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(15) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(15) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(14) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(14) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(13) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(13) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(12) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(12) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(29) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(29) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(11) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(11) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(10) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(9) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(9) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(8) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(8) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(7) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(7) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(6) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(6) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(5) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(5) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(4) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(4) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(3) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(3) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(2) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(2) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(28) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(28) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(1) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(1) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(0) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(0) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(27) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(27) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(26) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(26) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(25) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(25) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(24) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(24) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(23) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(23) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=D(22) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(22) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(31) D=E_ff_CQZ_D(31) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(30) D=E_ff_CQZ_D(30) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(21) D=E_ff_CQZ_D(21) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(20) D=E_ff_CQZ_D(20) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(19) D=E_ff_CQZ_D(19) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(18) D=E_ff_CQZ_D(18) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(17) D=E_ff_CQZ_D(17) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(16) D=E_ff_CQZ_D(16) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(15) D=E_ff_CQZ_D(15) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(14) D=E_ff_CQZ_D(14) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(13) D=E_ff_CQZ_D(13) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(12) D=E_ff_CQZ_D(12) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(29) D=E_ff_CQZ_D(29) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(11) D=E_ff_CQZ_D(11) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(10) D=E_ff_CQZ_D(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(9) D=E_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(8) D=E_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(7) D=E_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(6) D=E_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(5) D=E_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(4) D=E_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(3) D=E_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(2) D=E_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(28) D=E_ff_CQZ_D(28) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(1) D=E_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(0) D=E_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(27) D=E_ff_CQZ_D(27) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(26) D=E_ff_CQZ_D(26) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(25) D=E_ff_CQZ_D(25) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(24) D=E_ff_CQZ_D(24) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(23) D=E_ff_CQZ_D(23) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=E(22) D=E_ff_CQZ_D(22) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_1_I1 I2=E_ff_CQZ_D_LUT4_O_1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_10_I1 I2=E_ff_CQZ_D_LUT4_O_10_I2 I3=E_ff_CQZ_D_LUT4_O_10_I3 O=E_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110100000000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_10_I1 I1=E_ff_CQZ_D_LUT4_O_10_I2 I2=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_I2_I1 I3=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_I0_I3 O=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=G(10) I1=H4(23) I2=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=H4(23) I2=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(23) I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=D(22) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_1_O I3=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_I2_I1 I2=E_ff_CQZ_D_LUT4_O_10_I2 I3=E_ff_CQZ_D_LUT4_O_10_I1 O=E_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_11_I0 I1=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2 I3=H4(22) O=E_ff_CQZ_D_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0_LUT4_O_I3 I2=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0_LUT4_O_I2 I3=H4(21) O=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I1 I1=H4(20) I2=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0_LUT4_O_I2 I3=H4(21) O=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100000000
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1 I2=H4_ff_CQZ_D(23) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_11_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_11_I2 I3=E_ff_CQZ_D_LUT4_O_11_I3 O=E_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=G(10) I1=D(22) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_1_O I3=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=G(10) I1=D(21) I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(20) I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I2_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0 I3=D(21) O=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(22) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_11_I0 I2=H4(22) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_10_I2_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_12_I2 I3=E_ff_CQZ_D_LUT4_O_12_I3 O=E_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0 I2=H_ff_CQZ_D_LUT4_O_I3 I3=H4_ff_CQZ_D(21) O=E_ff_CQZ_D_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101110110000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I1 I2=H4(21) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=D(21) I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=H4(20) I2=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_12_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$rst_i I1=H4_ff_CQZ_D(20) I2=A_ff_CQZ_D_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_13_I3 O=E_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110111000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I1 I2=H4(20) I3=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_O I2=D(19) I3=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=G(10) I1=D(20) I2=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_14_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_14_I2 I3=E_ff_CQZ_D_LUT4_O_14_I3 O=E_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_14_I0 I1=H4(19) I2=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_I0_I2 I3=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_I0_I3 O=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=D(19) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_O I3=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_O I2=D(19) I3=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I0 I1=D(18) I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O O=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(19) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_14_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_14_I0 I2=H4(19) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_14_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_I0_I3 I3=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_I0_I2 O=E_ff_CQZ_D_LUT4_O_14_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_15_I2 I3=E_ff_CQZ_D_LUT4_O_15_I3 O=E_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(17) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_15_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=H4(17) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_15_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=H4(17) I3=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_16_I2 I3=E_ff_CQZ_D_LUT4_O_16_I3 O=E_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0 I1=H4(16) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_I0_I2 I3=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_15_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=D(16) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I2=D(16) I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3 O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2 I3=D(17) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I0 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1 I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_18_I0_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(28) I2=E(23) I3=E(10) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(17) I1=E(17) I2=Wt(17) I3=Kt(17) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(16) I1=Kt(16) I2=F(16) I3=E(16) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010001000101011
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I1 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I3_I0 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I0_I3 I1=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O_LUT4_I2_I3 O=E_ff_CQZ_D_LUT4_O_13_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(27) I2=E(22) I3=E(9) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(16) I1=E(16) I2=Wt(16) I3=Kt(16) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(15) I1=Kt(15) I2=F(15) I3=E(15) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(24) I2=E(19) I3=E(6) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(13) I1=E(13) I2=Wt(13) I3=Kt(13) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(12) I1=Kt(12) I2=F(12) I3=E(12) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O_LUT4_I1_O I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000000000
+.subckt LUT4 I0=Wt(11) I1=Kt(11) I2=F(11) I3=E(11) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=F(12) I1=E(12) I2=Wt(12) I3=Kt(12) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=G(10) I1=E(23) I2=E(18) I3=E(5) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(25) I2=E(20) I3=E(7) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(14) I1=E(14) I2=Wt(14) I3=Kt(14) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(13) I1=Kt(13) I2=F(13) I3=E(13) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(26) I2=E(21) I3=E(8) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(15) I1=E(15) I2=Wt(15) I3=Kt(15) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(14) I1=Kt(14) I2=F(14) I3=E(14) O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=D(16) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=D(17) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_I2_O I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I1_LUT4_O_I3 I1=D(15) I2=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(16) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_16_I0 I2=H4(16) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_16_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_I0_I2 I3=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_16_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_17_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_17_I2 I3=E_ff_CQZ_D_LUT4_O_17_I3 O=E_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4(15) I3=E_ff_CQZ_D_LUT4_O_17_I0 O=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(15) I3=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(14) I3=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I2=D(13) I3=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I2=D(13) I3=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(14) I3=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(15) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_17_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_17_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=H4(14) I3=E_ff_CQZ_D_LUT4_O_17_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I1 I3=H4(15) O=E_ff_CQZ_D_LUT4_O_17_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=H4(14) I3=E_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_17_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_18_I2 I3=E_ff_CQZ_D_LUT4_O_18_I3 O=E_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(14) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_17_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I3_O I2=H4(14) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_18_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 I1=H4(13) I2=E_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_18_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_19_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=E_ff_CQZ_D_LUT4_O_19_I3 O=E_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H4_ff_CQZ_D(12) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000011101110
+.subckt LUT4 I0=G(10) I1=H4(12) I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_19_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4(12) I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I1 I3=H4(12) O=E_ff_CQZ_D_LUT4_O_20_I2_LUT4_O_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(12) I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(11) I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1 I2=B(11) I3=A(11) O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=G(10) I1=A(24) I2=A(13) I3=A(1) O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O I1=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(21) I2=E(16) I3=E(3) O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(10) I1=E(10) I2=Wt(10) I3=Kt(10) O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(9) I1=Kt(9) I2=F(9) I3=E(9) O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=H4(11) I2=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_1_O I3=E_ff_CQZ_D_LUT4_O_20_I2_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I2=H_ff_CQZ_D_LUT4_O_I3 I3=H4_ff_CQZ_D(28) O=E_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011101110110000
+.subckt LUT4 I0=G(10) I1=D(28) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=D(28) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=D(29) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=D(27) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 I2=H4(28) I3=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4(27) I3=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=H4(26) I3=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=H4(27) O=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I2_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(26) I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_O_LUT4_I0_O O=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_2_I2 I3=E_ff_CQZ_D_LUT4_O_2_I3 O=E_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_20_I2 I3=E_ff_CQZ_D_LUT4_O_20_I3 O=E_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_20_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_1_O I2=H4(11) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_20_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_1_O I2=H4(11) I3=E_ff_CQZ_D_LUT4_O_20_I2_LUT4_O_I0_LUT4_I0_I3 O=E_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(11) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_21_I2 I3=E_ff_CQZ_D_LUT4_O_21_I3 O=E_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I0 I1=H4(10) I2=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_I0_I2 I3=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_I0_I3 O=E_ff_CQZ_D_LUT4_O_20_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=D(10) I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=D(10) I3=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3 O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3 I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O I2=D(10) I3=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=G(10) I1=D(11) I2=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_O_I0 I1=D(9) I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_O_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_I2_O I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_21_I0 I2=H4(10) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_I0_I3 I3=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_I0_I2 O=E_ff_CQZ_D_LUT4_O_21_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(10) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$rst_i I1=H4_ff_CQZ_D(9) I2=A_ff_CQZ_D_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3 O=E_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110111000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt LUT4 I0=G(10) I1=H4(9) I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O I2=D(7) I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=D(8) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(8) I3=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2 I3=H4(9) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=D(9) I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_I2_O I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=A_ff_CQZ_D_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(18) I2=E(13) I3=E(0) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(7) I1=E(7) I2=Wt(7) I3=Kt(7) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(6) I1=Kt(6) I2=F(6) I3=E(6) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I0 I1=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I0 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(20) I2=E(15) I3=E(2) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(9) I1=E(9) I2=Wt(9) I3=Kt(9) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(8) I1=Kt(8) I2=F(8) I3=E(8) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(19) I2=E(14) I3=E(1) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(8) I1=E(8) I2=Wt(8) I3=Kt(8) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(7) I1=Kt(7) I2=F(7) I3=E(7) O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H4_ff_CQZ_D(8) I2=E_ff_CQZ_D_LUT4_O_23_I2 I3=E_ff_CQZ_D_LUT4_O_23_I3 O=E_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_23_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I2=H4(8) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_23_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I2=H4(8) I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_21_I0_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O I2=H4(8) I3=E_ff_CQZ_D_LUT4_O_23_I3_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1 I1=H4(7) I2=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I0_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I0_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_23_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H4_ff_CQZ_D(7) I2=E_ff_CQZ_D_LUT4_O_24_I2 I3=E_ff_CQZ_D_LUT4_O_24_I3 O=E_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1 I2=H4(7) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_24_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=D(7) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O I3=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O I2=D(7) I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=D(6) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H4_ff_CQZ_D(6) I2=E_ff_CQZ_D_LUT4_O_25_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3 O=E_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_25_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I2=H4(5) I3=E_ff_CQZ_D_LUT4_O_25_I2_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1 I3=H4(6) O=E_ff_CQZ_D_LUT4_O_25_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I2=H4(5) I3=E_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_25_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_25_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=G(10) I1=D(6) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O O=A_ff_CQZ_D_LUT4_O_9_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I0 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2 O=A_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(6) I3=B(6) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=A(28) I2=A(19) I3=A(8) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=E_ff_CQZ_D_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E(31) I2=E(17) I3=E(12) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(6) I1=E(6) I2=Wt(6) I3=Kt(6) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(5) I1=Kt(5) I2=F(5) I3=E(5) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(30) I2=E(16) I3=E(11) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(5) I1=E(5) I2=Wt(5) I3=Kt(5) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(4) I1=Kt(4) I2=F(4) I3=E(4) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=H4(6) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_24_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=D(4) I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=D(5) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I1=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(26) I2=E(12) I3=E(7) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(1) I1=E(1) I2=Wt(1) I3=Kt(1) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(0) I1=Kt(0) I2=F(0) I3=E(0) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(28) I2=E(14) I3=E(9) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(3) I1=E(3) I2=Wt(3) I3=Kt(3) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(2) I1=Kt(2) I2=F(2) I3=E(2) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(27) I2=E(13) I3=E(8) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(2) I1=E(2) I2=Wt(2) I3=Kt(2) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(1) I1=Kt(1) I2=F(1) I3=E(1) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(29) I2=E(15) I3=E(10) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(4) I1=E(4) I2=Wt(4) I3=Kt(4) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(3) I1=Kt(3) I2=F(3) I3=E(3) O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(5) I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H4_ff_CQZ_D(5) I2=E_ff_CQZ_D_LUT4_O_26_I2 I3=E_ff_CQZ_D_LUT4_O_26_I3 O=E_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I2=H4(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H4(4) I2=E_ff_CQZ_D_LUT4_O_27_I2_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_26_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H4_ff_CQZ_D(4) I2=E_ff_CQZ_D_LUT4_O_27_I2 I3=E_ff_CQZ_D_LUT4_O_27_I3 O=E_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 I1=E_ff_CQZ_D_LUT4_O_27_I2_LUT4_O_I1 I2=H4(4) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_27_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H4(3) I2=E_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_27_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=D(4) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_I3_O I2=D(4) I3=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=G(10) I1=D(3) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=E_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H4_ff_CQZ_D(3) I2=E_ff_CQZ_D_LUT4_O_28_I2 I3=E_ff_CQZ_D_LUT4_O_28_I3 O=E_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2 I2=H4(3) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H4(2) I2=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_29_I2_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_28_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_28_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=D(3) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=E_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=D(2) I2=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_28_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H4_ff_CQZ_D(2) I2=E_ff_CQZ_D_LUT4_O_29_I2 I3=E_ff_CQZ_D_LUT4_O_29_I3 O=E_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_29_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2 I2=H4(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H4(1) I2=E_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_29_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=D(2) I2=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I3_LUT4_O_I1 I1=D(1) I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_29_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100010001110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(27) I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I2_LUT4_I1_O I2=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(25) I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_1_O O=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=D(25) I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_1_O O=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I2_LUT4_I1_O I1=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_1_O I2=D(25) I3=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(26) I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_O_LUT4_I0_O O=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=H4(26) I1=E_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I2=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(27) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_3_I2 I3=E_ff_CQZ_D_LUT4_O_3_I3 O=E_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$rst_i I1=H4_ff_CQZ_D(1) I2=A_ff_CQZ_D_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_30_I3 O=E_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110111000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I1 I2=H4(1) I3=E_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_30_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H4(0) I2=D(0) I3=E_ff_CQZ_D_LUT4_O_31_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_25_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0_LUT4_O_I0_LUT4_O_I1_LUT4_I1_O I3=D(1) O=E_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100110010110
+.subckt LUT4 I0=G(10) I1=D(0) I2=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_30_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_I3 I1=H4_ff_CQZ_D(0) I2=E_ff_CQZ_D_LUT4_O_31_I2 I3=E_ff_CQZ_D_LUT4_O_31_I3 O=E_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_31_I3_LUT4_O_I2 I1=D(0) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=H4(0) O=E_ff_CQZ_D_LUT4_O_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=G(10) I1=D(0) I2=E_ff_CQZ_D_LUT4_O_31_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_31_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_31_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I1 I3=A_ff_CQZ_D_LUT4_O_10_I3_LUT4_O_I0 O=E_ff_CQZ_D_LUT4_O_31_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=H4(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_31_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4(18) I3=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_14_I0_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=G(10) I1=D(18) I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I3_LUT4_I0_O O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E(29) I2=E(24) I3=E(11) O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(18) I1=E(18) I2=Wt(18) I3=Kt(18) O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(17) I1=Kt(17) I2=F(17) I3=E(17) O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(17) I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I1_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=H4(17) I1=E_ff_CQZ_D_LUT4_O_15_I3_LUT4_O_I0 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I3=H4(18) O=E_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(18) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_4_I2 I3=E_ff_CQZ_D_LUT4_O_4_I3 O=E_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=H_ff_CQZ_D_LUT4_O_I3 I3=H4_ff_CQZ_D(13) O=E_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=G(10) I1=D(13) I2=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I3_LUT4_I0_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_23_I0_LUT4_O_I2_LUT4_O_I3 I1=D(12) I2=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_19_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=H4(13) I1=E_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100111111111
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_4_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=E_ff_CQZ_D_LUT4_O_5_I3 O=E_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0 I1=A_ff_CQZ_D_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111010000000111
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(31) I3=cmd(2) O=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1 I2=H4(31) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=G(10) I1=D(31) I2=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_6_I2 I3=E_ff_CQZ_D_LUT4_O_6_I3 O=E_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(29) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=H4(29) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I2=H4(29) I3=E_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1 I1=H4(28) I2=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I0 I3=E_ff_CQZ_D_LUT4_O_1_I2_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_7_I2 I3=E_ff_CQZ_D_LUT4_O_7_I3 O=E_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(26) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I3_O I2=H4(26) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_8_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_8_I2 I3=E_ff_CQZ_D_LUT4_O_8_I3 O=E_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_8_I0 I1=H4(25) I2=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_I0_O O=E_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101110111010100
+.subckt LUT4 I0=G(10) I1=D(25) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_1_O I3=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I2_LUT4_I1_O O=E_ff_CQZ_D_LUT4_O_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(25) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_8_I0 I2=H4(25) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_I0_O I3=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_9_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E_ff_CQZ_D_LUT4_O_9_I2 I3=E_ff_CQZ_D_LUT4_O_9_I3 O=E_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4(24) I3=E_ff_CQZ_D_LUT4_O_9_I0 O=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I1 I3=H4(24) O=E_ff_CQZ_D_LUT4_O_10_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(24) I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I3_O I1=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I3 I3=D(24) O=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O I3=D(23) O=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_11_I0_LUT4_O_I3 I1=D(22) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_1_O I3=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(23) I3=A_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_9_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H4_ff_CQZ_D(24) I3=H_ff_CQZ_D_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_9_I0 I2=H4(24) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=H4_ff_CQZ_D(30) I1=H_ff_CQZ_D_LUT4_O_I3 I2=E_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011101110
+.subckt LUT4 I0=H4(29) I1=E_ff_CQZ_D_LUT4_O_6_I3_LUT4_O_I0 I2=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=E_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=G(10) I1=D(30) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=D(29) I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_1_I1_LUT4_O_I1_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O I2=D(28) I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I3=D(29) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=H4(30) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_5_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2 I3=H4(30) O=E_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=D(30) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(21) I2=E(7) I3=E(2) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(28) I1=E(28) I2=Wt(28) I3=Kt(28) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(27) I1=Kt(27) I2=F(27) I3=E(27) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=A_ff_CQZ_D_LUT4_O_11_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(20) I2=E(6) I3=E(1) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(27) I1=E(27) I2=Wt(27) I3=Kt(27) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(26) I1=Kt(26) I2=F(26) I3=E(26) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(19) I2=E(5) I3=E(0) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(26) I1=E(26) I2=Wt(26) I3=Kt(26) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(25) I1=Kt(25) I2=F(25) I3=E(25) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_O I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=E(31) I2=E(18) I3=E(4) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=F(25) I1=E(25) I2=Wt(25) I3=Kt(25) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=Wt(24) I1=Kt(24) I2=F(24) I3=E(24) O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=G(10) I2=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 I3=A_ff_CQZ_D_LUT4_O_16_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=E_ff_CQZ_D_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(31) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(30) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(21) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(20) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(19) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(18) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(17) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(16) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(15) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(14) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(13) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(12) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(29) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(11) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(10) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(9) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(8) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(7) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(6) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(5) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(4) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(3) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(2) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(28) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(1) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(0) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(27) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(26) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(25) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(24) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(23) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(22) I3=H_LUT4_I2_I3 O=H5_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=F(31) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(31) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(30) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(30) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(21) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(21) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(20) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(20) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(19) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(19) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(18) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(18) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(17) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(17) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(16) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(16) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(15) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(15) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(14) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(14) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(13) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(13) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(12) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(12) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(29) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(29) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(11) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(11) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(10) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(9) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(9) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(8) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(8) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(7) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(7) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(6) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(6) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(5) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(5) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(4) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(4) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(3) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(3) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(2) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(2) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(28) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(28) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(1) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(1) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(0) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(0) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(27) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(27) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(26) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(26) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(25) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(25) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(24) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(24) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(23) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(23) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=F(22) D=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(22) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(9) D=G_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(8) D=G_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(7) D=G_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(6) D=G_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(5) D=G_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(4) D=G_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(3) D=G_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(2) D=G_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(1) D=G_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=G(0) D=G_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_I1 I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_1_I0 I1=G_ff_CQZ_D_LUT4_O_1_I1 I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=F(0) I1=H6(0) I2=F(1) I3=H6(1) O=G_ff_CQZ_D_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=G(1) I1=cmd(2) I2=F(1) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010000001111
+.subckt LUT4 I0=$iopadmap$rst_i I1=H6_ff_CQZ_D(9) I2=A_ff_CQZ_D_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_2_I3 O=G_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110111000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1 I2=H6(9) I3=F(9) O=G_ff_CQZ_D_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=G(10) I1=H6(8) I2=F(8) I3=G_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_2_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=H6_ff_CQZ_D(8) I2=G_ff_CQZ_D_LUT4_O_3_I2 I3=$iopadmap$rst_i O=G_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100010001111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=F(8) I2=G_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=G(10) I1=H6(8) I2=F(8) I3=G_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_4_I1 I2=H6_ff_CQZ_D(7) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 I2=H6(7) I3=F(7) O=G_ff_CQZ_D_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H6(7) I2=F(7) I3=G_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=H6(6) I2=F(6) I3=G_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=H6_ff_CQZ_D(6) I2=G_ff_CQZ_D_LUT4_O_5_I2 I3=$iopadmap$rst_i O=G_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100010001111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=F(6) I2=G_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=G(10) I1=H6(6) I2=F(6) I3=G_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=F(5) I2=G_ff_CQZ_D_LUT4_O_6_I2 I3=G_ff_CQZ_D_LUT4_O_6_I3 O=G_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 I1=F(5) I2=H6(5) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H6(5) I2=F(5) I3=G_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=H6(4) I2=F(4) I3=G_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_6_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H6_ff_CQZ_D(5) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=F(4) I2=G_ff_CQZ_D_LUT4_O_7_I2 I3=G_ff_CQZ_D_LUT4_O_7_I3 O=G_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0 I1=F(4) I2=H6(4) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H6(3) I2=F(3) I3=G_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=$iopadmap$rst_i I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2 I3=G(4) O=G_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=F(2) I2=G_ff_CQZ_D_LUT4_O_8_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3 O=G_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I0 I1=F(2) I2=H6(2) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=F(1) I1=H6(1) I2=H6(0) I3=F(0) O=G_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=$iopadmap$rst_i I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2 I3=G(2) O=G_ff_CQZ_D_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=B(4) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_I2 I3=$iopadmap$rst_i O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=F(2) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_1_I2 I3=$iopadmap$rst_i O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_1_I2_LUT4_O_I1 I2=E(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I0 I1=E(2) I2=H5(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=E(1) I1=H5(1) I2=H5(0) I3=E(0) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=F(1) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_I2 I3=$iopadmap$rst_i O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=E(1) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=E(0) I1=H5(0) I2=E(1) I3=H5(1) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_I1 I2=H5_ff_CQZ_D(29) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_10_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(27) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_10_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0 I1=E(27) I2=H5(27) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H5(26) I2=E(26) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_10_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_11_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(26) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(26) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_11_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=E(26) I2=H5(26) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_12_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(24) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(24) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_12_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I0 I1=E(24) I2=H5(24) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H5(23) I2=E(23) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_13_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(23) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(23) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_13_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I0 I1=E(23) I2=H5(23) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_14_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(18) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_14_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_14_I1_LUT4_O_I3_LUT4_O_I0 I1=E(18) I2=H5(18) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H5(17) I2=E(17) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_14_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_15_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(17) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(17) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_15_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 I1=E(17) I2=H5(17) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_15_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_16_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(16) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(16) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_16_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_16_I1_LUT4_O_I3_LUT4_O_I0 I1=E(16) I2=H5(16) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_16_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H5(15) I2=E(15) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_17_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_16_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_17_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(15) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(15) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_17_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_17_I1_LUT4_O_I3_LUT4_O_I0 I1=E(15) I2=H5(15) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_17_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H5(14) I2=E(14) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_17_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_18_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(14) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(14) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_18_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0 I1=E(14) I2=H5(14) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H5(13) I2=E(13) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_19_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_19_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(13) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(13) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_19_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_19_I1_LUT4_O_I3_LUT4_O_I0 I1=E(13) I2=H5(13) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_19_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H5(12) I2=E(12) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_19_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I1 I2=E(28) I3=H5(28) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0 I1=E(26) I2=H5(26) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(27) I3=E(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(27) I3=E(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=E(28) I2=H5_ff_CQZ_D(28) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_20_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H5_ff_CQZ_D(12) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=E(12) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_20_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_O_I0 I1=E(12) I2=H5(12) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=H5_ff_CQZ_D(11) I1=A_ff_CQZ_D_LUT4_O_I2 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_21_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_21_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=E(11) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_21_I3_LUT4_O_I0 I1=E(11) I2=H5(11) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H5(11) I2=E(11) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_21_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=H5(10) I2=E(10) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_22_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_21_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_22_I1 I2=H5_ff_CQZ_D(10) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_22_I1_LUT4_O_I1 I2=H5(10) I3=E(10) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=G(10) I1=H5(9) I2=E(9) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_23_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_22_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_23_I1 I2=H5_ff_CQZ_D(9) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_23_I1_LUT4_O_I1 I2=H5(9) I3=E(9) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H5(8) I2=E(8) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_24_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_23_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_24_I1 I2=H5_ff_CQZ_D(8) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_24_I1_LUT4_O_I1 I2=H5(8) I3=E(8) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H5(7) I2=E(7) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_25_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_24_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_25_I1 I2=H5_ff_CQZ_D(7) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_25_I1_LUT4_O_I1 I2=H5(7) I3=E(7) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_25_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H5(6) I2=E(6) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_26_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_25_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_26_I1 I2=H5_ff_CQZ_D(6) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_26_I1_LUT4_O_I1 I2=H5(6) I3=E(6) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_26_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H5(5) I2=E(5) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_27_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_26_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_27_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_27_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_27_I2_LUT4_O_I0 I1=E(5) I2=H5(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_27_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H5(4) I2=E(4) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_28_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_27_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=cmd(2) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_27_I3_LUT4_O_I1 I2=E(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=G(10) I1=G(10) I2=F(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_27_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=E(4) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_28_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_28_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_28_I2_LUT4_O_I0 I1=E(4) I2=H5(4) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H5(3) I2=E(3) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_29_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_28_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5_ff_CQZ_D(4) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_28_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_29_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_29_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_29_I2_LUT4_O_I0 I1=E(3) I2=H5(3) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H5(2) I2=E(2) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_1_I2_LUT4_O_I1_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_29_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I2=E(3) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_29_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=G(10) I1=F(3) I2=cmd(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_29_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I1 I2=E(25) I3=H5(25) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=E(25) I1=H5(25) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I0 I1=E(23) I2=H5(23) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(24) I3=E(24) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(24) I3=E(24) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=E(25) I2=H5_ff_CQZ_D(25) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1_LUT4_O_I1 I2=E(22) I3=H5(22) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_5_I1_LUT4_O_I2 I1=E(20) I2=H5(20) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(21) I3=E(21) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=E(22) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1_LUT4_O_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1_LUT4_O_I0 I3=H5(22) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(21) I3=E(21) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$rst_i I1=E(22) I2=H5_ff_CQZ_D(22) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_4_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_4_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=$iopadmap$rst_i I1=E(21) I2=H5(21) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_4_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=G(10) I1=H5(20) I2=E(20) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_5_I1_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_4_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=E(21) I2=H5_ff_CQZ_D(21) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_5_I1 I2=H5_ff_CQZ_D(20) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H5(20) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_5_I1_LUT4_O_I2 I3=E(20) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=E(19) I1=H5(19) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_5_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I1 I2=E(19) I3=H5(19) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 I1=E(17) I2=H5(17) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=H5(16) I2=E(16) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_16_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(18) I3=E(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(18) I3=E(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=E(19) I2=H5_ff_CQZ_D(19) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_7_I1 I2=H5_ff_CQZ_D(0) I3=H_ff_CQZ_D_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=H5(0) I2=E(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110011111010
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_8_I1 I2=E(31) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_8_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_8_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_8_I1_LUT4_O_I1 I2=H5(31) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_I1_LUT4_O_I2 I1=E(29) I2=H5(29) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_9_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_8_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(30) I3=E(30) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5_ff_CQZ_D(31) I3=H_ff_CQZ_D_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_9_I1 I2=H5_ff_CQZ_D(30) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_9_I1_LUT4_O_I0 I1=$iopadmap$rst_i I2=E(30) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010111000001111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_I1_LUT4_O_I2 I1=E(29) I2=H5(29) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_9_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_9_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H5(30) I3=E(30) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_9_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H5(29) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_I1_LUT4_O_I2 I3=E(29) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=E(28) I1=H5(28) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_1_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_2_O_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_I2_LUT4_O_I1 I2=A(4) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I0 I1=A(4) I2=H1(4) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_10_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H1_ff_CQZ_D(23) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=A(23) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_10_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0 I1=A(23) I2=H1(23) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1 I2=H1_ff_CQZ_D(22) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=A(22) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1 I2=A(22) I3=H1(22) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(21) I3=A(21) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_12_I1 I2=H1_ff_CQZ_D(20) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I1 I2=H1(20) I3=A(20) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I1 I1=A(20) I2=H1(20) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I1_LUT4_I0_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(21) I3=A(21) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=A(19) I1=H1(19) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_13_I1 I2=H1_ff_CQZ_D(18) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=A(18) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_14_I0_LUT4_O_I0 I1=A(17) I2=H1(17) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_14_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_14_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H1_ff_CQZ_D(17) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100010001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_14_I0_LUT4_O_I0 I1=A(17) I2=H1(17) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H1(16) I2=A(16) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_14_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=A(17) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_15_I1 I2=H1_ff_CQZ_D(16) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I1 I2=H1(16) I3=A(16) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=G(10) I1=H1(15) I2=A(15) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_16_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_16_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_16_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H1_ff_CQZ_D(15) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100010001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_16_I0_LUT4_O_I0 I1=A(15) I2=H1(15) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_16_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H1(14) I2=A(14) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_17_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_16_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=A(15) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_17_I1 I2=H1_ff_CQZ_D(14) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_17_I1_LUT4_O_I1 I2=H1(14) I3=A(14) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=G(10) I1=H1(13) I2=A(13) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_18_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_17_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_18_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_18_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H1_ff_CQZ_D(13) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100010001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_18_I0_LUT4_O_I0 I1=A(13) I2=H1(13) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H1(12) I2=A(12) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_19_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_18_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=A(13) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_19_I1 I2=H1_ff_CQZ_D(12) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_19_I1_LUT4_O_I1 I2=H1(12) I3=A(12) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=G(10) I1=H1(11) I2=A(11) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_20_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_19_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I1 I2=A(25) I3=H1(25) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0 I1=A(23) I2=H1(23) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(24) I3=A(24) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=A(25) I2=H1_ff_CQZ_D(25) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_2_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_2_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_20_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_20_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_20_I2_LUT4_O_I0 I1=A(11) I2=H1(11) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H1(10) I2=A(10) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_20_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_20_I3_LUT4_O_I1 I2=A(11) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_I2 I2=B(11) I3=cmd(2) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_20_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_21_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_21_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I0 I1=A(10) I2=H1(10) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H1(9) I2=A(9) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_22_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_21_I3_LUT4_O_I1 I2=A(10) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_I2 I2=B(10) I3=cmd(2) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_21_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_22_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_22_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_22_I2_LUT4_O_I0 I1=A(9) I2=H1(9) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H1(8) I2=A(8) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_23_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_22_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_22_I3_LUT4_O_I1 I2=A(9) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_22_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_I2 I2=B(9) I3=cmd(2) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_22_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=A(8) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_23_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_23_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_23_I2_LUT4_O_I0 I1=A(8) I2=H1(8) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H1(7) I2=A(7) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_23_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1_ff_CQZ_D(8) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_24_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_24_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I0 I1=A(7) I2=H1(7) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H1(6) I2=A(6) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_24_I3_LUT4_O_I1 I2=A(7) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_24_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_I2 I2=B(7) I3=cmd(2) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_24_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_25_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H1_ff_CQZ_D(6) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=A(6) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I2 I3=$iopadmap$rst_i O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_25_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I2_LUT4_O_I0 I1=A(6) I2=H1(6) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H1(5) I2=A(5) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_26_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=A(5) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_26_I3_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_26_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I0 I1=A(5) I2=H1(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_26_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H1(4) I2=A(4) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_26_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=B(5) I2=cmd(2) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_26_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=A(3) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I2_LUT4_O_I0 I1=A(3) I2=H1(3) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H1(3) I2=A(3) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=H1(2) I2=A(2) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I2_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=A(1) I1=H1(1) I2=H1(0) I3=A(0) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=B(3) I2=H_LUT4_I2_I3 I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_28_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=B(2) I1=cmd(2) I2=A_ff_CQZ_D_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_28_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I3_LUT4_O_I1 I2=A(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_27_I2_LUT4_O_I0_LUT4_O_I3 I1=A(2) I2=H1(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=H_LUT4_I2_I3 I1=B(1) I2=A_ff_CQZ_D_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_29_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*I2*I3)"
+.param INIT 1000000011111111
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=A(1) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_29_I3_LUT4_O_I2 I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=A(0) I1=H1(0) I2=A(1) I3=H1(1) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_29_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=$iopadmap$rst_i I1=A(21) I2=H1(21) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_2_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=G(10) I1=H1(20) I2=A(20) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=A(21) I2=H1_ff_CQZ_D(21) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=$iopadmap$rst_i I1=H1_ff_CQZ_D(0) I2=A_ff_CQZ_D_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_30_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110111000000
+.subckt LUT4 I0=G(10) I1=A(0) I2=H1(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_30_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1 I2=A(19) I3=H1(19) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_14_I0_LUT4_O_I0 I1=A(17) I2=H1(17) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(18) I3=A(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(18) I3=A(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=A(19) I2=H1_ff_CQZ_D(19) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_4_I1 I2=A(31) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_4_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I1 I2=H1(31) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1 I1=A(29) I2=H1(29) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_5_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(30) I3=A(30) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1_ff_CQZ_D(31) I3=H_ff_CQZ_D_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_5_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H1_ff_CQZ_D(30) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_5_I1_LUT4_O_I0 I1=A(30) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=H_ff_CQZ_D_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101110000000000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1 I1=A(29) I2=H1(29) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_5_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_5_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011111101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(30) I3=A(30) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_5_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_6_I1 I2=H1_ff_CQZ_D(29) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1 I2=H1(29) I3=A(29) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=A(28) I1=H1(28) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1 I2=H1_ff_CQZ_D(28) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=A(28) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1 I2=A(28) I3=H1(28) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(27) I3=A(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_8_I1 I2=H1_ff_CQZ_D(26) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I1 I2=H1(26) I3=A(26) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I1 I1=A(26) I2=H1(26) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I1_LUT4_I0_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(27) I3=A(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=A(25) I1=H1(25) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1 I2=H1_ff_CQZ_D(24) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=A(24) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10100011
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0 I1=A(23) I2=H1(23) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101111010100
+.subckt LUT4 I0=A(22) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3_LUT4_O_I0 I3=H1(22) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H1(24) I3=A(24) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$rst_i I1=A(27) I2=H1(27) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=G(10) I1=H1(26) I2=A(26) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=A(27) I2=H1_ff_CQZ_D(27) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I1_O_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=C(1) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101110111011
+.subckt LUT4 I0=B(0) I1=H2(0) I2=B(1) I3=H2(1) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=B(1) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100001010
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001000111110000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_10_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(26) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(26) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_10_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I0 I1=B(26) I2=H2(26) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_10_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_11_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(23) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(23) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I1_LUT4_O_I2 I1=B(23) I2=H2(23) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_12_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(20) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(20) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 I1=B(20) I2=H2(20) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_13_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(18) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=G(10) I1=H2(17) I2=B(17) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_14_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(17) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(17) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_14_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 I1=B(17) I2=H2(17) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_15_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(16) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(16) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I0 I1=B(16) I2=H2(16) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H2(15) I2=B(15) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_16_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(15) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(15) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I3_LUT4_O_I0 I1=B(15) I2=H2(15) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H2(14) I2=B(14) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_17_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_17_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(14) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(14) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_17_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_17_I1_LUT4_O_I3_LUT4_O_I0 I1=B(14) I2=H2(14) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_17_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H2(13) I2=B(13) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_17_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_18_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(13) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(13) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0 I1=B(13) I2=H2(13) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H2(12) I2=B(12) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_19_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_19_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(12) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(12) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_19_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_19_I1_LUT4_O_I3_LUT4_O_I0 I1=B(12) I2=H2(12) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_19_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=B(29) I1=H2(29) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=B(28) I1=H2(28) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(30) I3=B(30) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$rst_i I1=B(30) I2=H2_ff_CQZ_D(30) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_20_I1 I2=H2_ff_CQZ_D(11) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I1 I2=H2(11) I3=B(11) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H2(11) I2=B(11) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_19_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=H2(10) I2=B(10) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_21_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=H2_ff_CQZ_D(10) I1=A_ff_CQZ_D_LUT4_O_I2 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_21_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_21_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=B(10) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_21_I3_LUT4_O_I0 I1=B(10) I2=H2(10) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H2(9) I2=B(9) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_22_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_21_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_22_I1 I2=H2_ff_CQZ_D(9) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_22_I1_LUT4_O_I1 I2=H2(9) I3=B(9) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H2(8) I2=B(8) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_22_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_23_I1 I2=H2_ff_CQZ_D(8) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I1 I2=H2(8) I3=B(8) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H2(7) I2=B(7) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_24_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_24_I1 I2=H2_ff_CQZ_D(7) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_24_I1_LUT4_O_I1 I2=H2(7) I3=B(7) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H2(6) I2=B(6) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_24_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_25_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(6) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(6) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_25_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I0 I1=B(6) I2=H2(6) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_26_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_26_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I0 I1=B(5) I2=H2(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H2(5) I2=B(5) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_25_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=H2(4) I2=B(4) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_27_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=cmd(2) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_26_I3_LUT4_O_I1 I2=B(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_26_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=G(10) I1=G(10) I2=C(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_26_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_27_I1 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_27_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_27_I1_LUT4_O_I0 I1=B(4) I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_27_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=G(10) I1=C(4) I2=cmd(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_27_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=G(10) I1=H2(4) I2=B(4) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_27_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=H2(3) I2=B(3) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_27_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_28_I1 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_28_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11110100
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_28_I1_LUT4_O_I0 I1=B(3) I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_28_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=G(10) I1=C(3) I2=cmd(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_28_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=G(10) I1=H2(3) I2=B(3) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_28_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=H2(2) I2=B(2) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_29_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=B(2) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_29_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_29_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_29_I2_LUT4_O_I0 I1=B(2) I2=H2(2) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=B(1) I1=H2(1) I2=H2(0) I3=B(0) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_29_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=C(2) I2=H_LUT4_I2_I3 I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I1 I2=B(28) I3=H2(28) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I0 I1=B(26) I2=H2(26) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(27) I3=B(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(27) I3=B(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=B(28) I2=H2_ff_CQZ_D(28) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=C(0) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I2 I3=$iopadmap$rst_i O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=D(0) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_I2 I3=$iopadmap$rst_i O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=H3(0) I2=C(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110001010000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_10_I1 I2=H3_ff_CQZ_D(14) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H3(14) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_10_I1_LUT4_O_I2 I3=C(14) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110110000010
+.subckt LUT4 I0=G(10) I1=H3(13) I2=C(13) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_10_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_11_I1 I2=H3_ff_CQZ_D(13) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H3(13) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I2 I3=C(13) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=G(10) I1=H3(12) I2=C(12) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_11_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_12_I1 I2=H3_ff_CQZ_D(12) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H3(12) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I2 I3=C(12) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110110000010
+.subckt LUT4 I0=G(10) I1=H3(11) I2=C(11) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_13_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_13_I1 I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=G(10) I1=H3(4) I2=C(4) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_13_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=H3(3) I2=C(3) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_14_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=D(4) I1=cmd(2) I2=C(4) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010000001111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_14_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_14_I1 I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=G(10) I1=H3(3) I2=C(3) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_14_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=H3(2) I2=C(2) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_30_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_14_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=D(3) I1=cmd(2) I2=C(3) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010000001111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_15_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_15_I1 I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=C(0) I1=H3(0) I2=C(1) I3=H3(1) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=D(1) I1=cmd(2) I2=C(1) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010000001111
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_16_I1 I2=C(31) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_16_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I1 I2=H3(31) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I1_LUT4_O_I2 I1=C(29) I2=H3(29) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(30) I3=C(30) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3_ff_CQZ_D(31) I3=H_ff_CQZ_D_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_16_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_17_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_17_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H3_ff_CQZ_D(29) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100010001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I1_LUT4_O_I2 I1=C(29) I2=H3(29) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=C(29) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_18_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H3_ff_CQZ_D(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=C(27) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0 I1=C(27) I2=H3(27) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_19_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_19_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H3_ff_CQZ_D(26) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100010001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_19_I0_LUT4_O_I0 I1=C(26) I2=H3(26) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H3(26) I2=C(26) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_19_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=C(25) I1=H3(25) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_19_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=C(26) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I1 I2=C(28) I3=H3(28) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_19_I0_LUT4_O_I0 I1=C(26) I2=H3(26) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(27) I3=C(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(27) I3=C(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=C(28) I2=H3_ff_CQZ_D(28) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_20_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H3_ff_CQZ_D(23) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=C(23) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2 I1=C(23) I2=H3(23) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_21_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_21_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H3_ff_CQZ_D(16) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100010001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0 I1=C(16) I2=H3(16) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H3(15) I2=C(15) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_22_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=C(16) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_22_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_22_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H3_ff_CQZ_D(15) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100010001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_22_I0_LUT4_O_I0 I1=C(15) I2=H3(15) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H3(14) I2=C(14) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_10_I1_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_22_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=C(15) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_23_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H3_ff_CQZ_D(11) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=C(11) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I3_LUT4_O_I0 I1=C(11) I2=H3(11) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=H3_ff_CQZ_D(10) I1=A_ff_CQZ_D_LUT4_O_I2 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_24_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_24_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=C(10) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_24_I3_LUT4_O_I0 I1=C(10) I2=H3(10) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_24_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H3(10) I2=C(10) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_24_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=H3(9) I2=C(9) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_25_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_24_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=H3_ff_CQZ_D(9) I1=A_ff_CQZ_D_LUT4_O_I2 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_25_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_25_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=C(9) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_25_I3_LUT4_O_I0 I1=C(9) I2=H3(9) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_25_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H3(8) I2=C(8) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_26_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_25_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_26_I1 I2=H3_ff_CQZ_D(8) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_26_I1_LUT4_O_I1 I2=H3(8) I3=C(8) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_26_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H3(7) I2=C(7) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_27_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_26_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_27_I1 I2=H3_ff_CQZ_D(7) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_27_I1_LUT4_O_I1 I2=H3(7) I3=C(7) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_27_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H3(6) I2=C(6) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_27_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=H3_ff_CQZ_D(6) I1=A_ff_CQZ_D_LUT4_O_I2 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_28_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_28_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I2=C(6) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I0 I1=C(6) I2=H3(6) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_28_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H3(5) I2=C(5) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_29_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_28_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=C(5) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_29_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_29_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_29_I2_LUT4_O_I0 I1=C(5) I2=H3(5) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H3(4) I2=C(4) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_13_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_29_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3_ff_CQZ_D(5) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I1 I2=C(25) I3=H3(25) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2 I1=C(23) I2=H3(23) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(24) I3=C(24) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=C(25) I2=H3_ff_CQZ_D(25) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_30_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_30_I1 I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=D(2) I1=cmd(2) I2=C(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_30_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=G(10) I1=H3(2) I2=C(2) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_30_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_30_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=C(1) I1=H3(1) I2=H3(0) I3=C(0) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_30_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=C(23) I1=H3(23) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=C(22) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0 I3=H3(22) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(24) I3=C(24) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$rst_i I1=C(24) I2=H3_ff_CQZ_D(24) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I1 I2=C(22) I3=H3(22) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I2 I1=C(20) I2=H3(20) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(21) I3=C(21) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(21) I3=C(21) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$rst_i I1=C(22) I2=H3_ff_CQZ_D(22) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_5_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_5_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=$iopadmap$rst_i I1=C(21) I2=H3(21) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=G(10) I1=H3(20) I2=C(20) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=C(21) I2=H3_ff_CQZ_D(21) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_6_I1 I2=H3_ff_CQZ_D(20) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H3(20) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I2 I3=C(20) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=C(19) I1=H3(19) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G(10) I1=A_ff_CQZ_D_LUT4_O_I2 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2 I3=H3_ff_CQZ_D(19) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0 I1=C(19) I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1 I2=C(19) I3=H3(19) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(18) I3=C(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_8_I1 I2=H3_ff_CQZ_D(18) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H3(18) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I2 I3=C(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110110000010
+.subckt LUT4 I0=G(10) I1=H3(17) I2=C(17) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_9_I1 I2=H3_ff_CQZ_D(17) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H3(17) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I2 I3=C(17) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I2 I1=C(17) I2=H3(17) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_I0_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_7_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(18) I3=C(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I2_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=H3(16) I2=C(16) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=C(29) I1=H3(29) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I1_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110100000010111
+.subckt LUT4 I0=C(28) I1=H3(28) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H3(30) I3=C(30) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$rst_i I1=C(30) I2=H3_ff_CQZ_D(30) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1_LUT4_I1_O_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=G(10) I1=G(10) I2=cmd(2) I3=A_ff_CQZ_D_LUT4_O_I2 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=H2(0) I2=B(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_30_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110001010000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1 I2=B(25) I3=H2(25) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=B(25) I1=H2(25) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I1_LUT4_O_I2 I1=B(23) I2=H2(23) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(24) I3=B(24) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=B(25) I2=H2_ff_CQZ_D(25) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I1 I2=B(22) I3=H2(22) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 I1=B(20) I2=H2(20) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000010111
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(21) I3=B(21) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(21) I3=B(21) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$rst_i I1=B(22) I2=H2_ff_CQZ_D(22) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11001010
+.subckt LUT4 I0=$iopadmap$rst_i I1=B(21) I2=H2(21) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100010100
+.subckt LUT4 I0=G(10) I1=H2(20) I2=B(20) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=$iopadmap$rst_i I1=B(21) I2=H2_ff_CQZ_D(21) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=$iopadmap$rst_i I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010011110000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1 I2=B(19) I3=H2(19) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=B(19) I1=H2(19) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011101000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0 I1=B(17) I2=H2(17) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=H2(16) I2=B(16) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I3_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(18) I3=B(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(18) I3=B(18) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=B(19) I2=H2_ff_CQZ_D(19) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_7_I1 I2=B(31) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_7_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111110
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I0 I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I1 I2=H2(31) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111000000000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I2 I1=B(29) I2=H2(29) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(30) I3=B(30) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_7_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2_ff_CQZ_D(31) I3=H_ff_CQZ_D_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_8_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(29) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(29) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1_LUT4_O_I2 I1=B(29) I2=H2(29) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_9_I1 I2=A_ff_CQZ_D_LUT4_O_I2 I3=H2_ff_CQZ_D(27) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=B(27) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0 I1=B(27) I2=H2(27) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110100100000000
+.subckt LUT4 I0=G(10) I1=H2(26) I2=B(26) I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=B(23) I1=H2(23) I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I1_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I1_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=B(22) I1=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I1 I2=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I0 I3=H2(22) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101010011111101
+.subckt LUT4 I0=G(10) I1=G(10) I2=H2(24) I3=B(24) O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$rst_i I1=B(24) I2=H2_ff_CQZ_D(24) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2_LUT4_I2_O_LUT4_I3_O_LUT4_I1_O_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=G(10) I1=G(10) I2=cmd(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_8_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$rst_i I1=H6_ff_CQZ_D(0) I2=A_ff_CQZ_D_LUT4_O_I2 I3=G_ff_CQZ_D_LUT4_O_9_I3 O=G_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110111000000
+.subckt LUT4 I0=G(10) I1=F(0) I2=H6(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=G(10) I1=H6(3) I2=F(3) I3=G_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3 O=G_ff_CQZ_D_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=H6(2) I2=F(2) I3=G_ff_CQZ_D_LUT4_O_8_I2_LUT4_O_I0 O=G_ff_CQZ_D_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(3) I1=cmd(2) I2=F(3) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=G_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100010000001111
+.subckt ff CQZ=H0(31) D=H0_ff_CQZ_D(31) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(30) D=H0_ff_CQZ_D(30) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(21) D=H0_ff_CQZ_D(21) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(20) D=H0_ff_CQZ_D(20) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(19) D=H0_ff_CQZ_D(19) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(18) D=H0_ff_CQZ_D(18) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(17) D=H0_ff_CQZ_D(17) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(16) D=H0_ff_CQZ_D(16) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(15) D=H0_ff_CQZ_D(15) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(14) D=H0_ff_CQZ_D(14) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(13) D=H0_ff_CQZ_D(13) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(12) D=H0_ff_CQZ_D(12) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(29) D=H0_ff_CQZ_D(29) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(11) D=H0_ff_CQZ_D(11) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(10) D=H0_ff_CQZ_D(10) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(9) D=H0_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(8) D=H0_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(7) D=H0_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(6) D=H0_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(5) D=H0_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(4) D=H0_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(3) D=H0_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(2) D=H0_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(28) D=H0_ff_CQZ_D(28) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(1) D=H0_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(0) D=H0_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(27) D=H0_ff_CQZ_D(27) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(26) D=H0_ff_CQZ_D(26) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(25) D=H0_ff_CQZ_D(25) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(24) D=H0_ff_CQZ_D(24) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(23) D=H0_ff_CQZ_D(23) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H0(22) D=H0_ff_CQZ_D(22) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(31) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(28) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(12) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(11) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(8) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(7) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(4) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(3) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(26) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(24) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(23) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(22) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(21) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(20) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(18) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=A(17) I3=H_LUT4_I2_I3 O=H0_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=H1(31) D=H1_ff_CQZ_D(31) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(30) D=H1_ff_CQZ_D(30) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(21) D=H1_ff_CQZ_D(21) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(20) D=H1_ff_CQZ_D(20) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(19) D=H1_ff_CQZ_D(19) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(18) D=H1_ff_CQZ_D(18) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(17) D=H1_ff_CQZ_D(17) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(16) D=H1_ff_CQZ_D(16) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(15) D=H1_ff_CQZ_D(15) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(14) D=H1_ff_CQZ_D(14) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(13) D=H1_ff_CQZ_D(13) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(12) D=H1_ff_CQZ_D(12) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(29) D=H1_ff_CQZ_D(29) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(11) D=H1_ff_CQZ_D(11) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(10) D=H1_ff_CQZ_D(10) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(9) D=H1_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(8) D=H1_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(7) D=H1_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(6) D=H1_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(5) D=H1_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(4) D=H1_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(3) D=H1_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(2) D=H1_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(28) D=H1_ff_CQZ_D(28) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(1) D=H1_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(0) D=H1_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(27) D=H1_ff_CQZ_D(27) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(26) D=H1_ff_CQZ_D(26) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(25) D=H1_ff_CQZ_D(25) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(24) D=H1_ff_CQZ_D(24) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(23) D=H1_ff_CQZ_D(23) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H1(22) D=H1_ff_CQZ_D(22) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(30) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(26) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(4) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(3) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(1) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(23) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(20) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(19) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(14) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(12) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(8) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(6) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=B(5) I3=H_LUT4_I2_I3 O=H1_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=H2(31) D=H2_ff_CQZ_D(31) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(30) D=H2_ff_CQZ_D(30) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(21) D=H2_ff_CQZ_D(21) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(20) D=H2_ff_CQZ_D(20) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(19) D=H2_ff_CQZ_D(19) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(18) D=H2_ff_CQZ_D(18) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(17) D=H2_ff_CQZ_D(17) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(16) D=H2_ff_CQZ_D(16) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(15) D=H2_ff_CQZ_D(15) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(14) D=H2_ff_CQZ_D(14) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(13) D=H2_ff_CQZ_D(13) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(12) D=H2_ff_CQZ_D(12) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(29) D=H2_ff_CQZ_D(29) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(11) D=H2_ff_CQZ_D(11) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(10) D=H2_ff_CQZ_D(10) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(9) D=H2_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(8) D=H2_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(7) D=H2_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(6) D=H2_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(5) D=H2_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(4) D=H2_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(3) D=H2_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(2) D=H2_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(28) D=H2_ff_CQZ_D(28) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(1) D=H2_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(0) D=H2_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(27) D=H2_ff_CQZ_D(27) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(26) D=H2_ff_CQZ_D(26) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(25) D=H2_ff_CQZ_D(25) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(24) D=H2_ff_CQZ_D(24) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(23) D=H2_ff_CQZ_D(23) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H2(22) D=H2_ff_CQZ_D(22) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(31) D=H3_ff_CQZ_D(31) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(30) D=H3_ff_CQZ_D(30) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(21) D=H3_ff_CQZ_D(21) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(20) D=H3_ff_CQZ_D(20) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(19) D=H3_ff_CQZ_D(19) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(18) D=H3_ff_CQZ_D(18) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(17) D=H3_ff_CQZ_D(17) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(16) D=H3_ff_CQZ_D(16) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(15) D=H3_ff_CQZ_D(15) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(14) D=H3_ff_CQZ_D(14) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(13) D=H3_ff_CQZ_D(13) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(12) D=H3_ff_CQZ_D(12) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(29) D=H3_ff_CQZ_D(29) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(11) D=H3_ff_CQZ_D(11) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(10) D=H3_ff_CQZ_D(10) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(9) D=H3_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(8) D=H3_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(7) D=H3_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(6) D=H3_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(5) D=H3_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(4) D=H3_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(3) D=H3_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(2) D=H3_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(28) D=H3_ff_CQZ_D(28) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(1) D=H3_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(0) D=H3_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(27) D=H3_ff_CQZ_D(27) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(26) D=H3_ff_CQZ_D(26) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(25) D=H3_ff_CQZ_D(25) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(24) D=H3_ff_CQZ_D(24) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(23) D=H3_ff_CQZ_D(23) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H3(22) D=H3_ff_CQZ_D(22) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(31) D=H4_ff_CQZ_D(31) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(30) D=H4_ff_CQZ_D(30) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(21) D=H4_ff_CQZ_D(21) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(20) D=H4_ff_CQZ_D(20) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(19) D=H4_ff_CQZ_D(19) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(18) D=H4_ff_CQZ_D(18) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(17) D=H4_ff_CQZ_D(17) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(16) D=H4_ff_CQZ_D(16) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(15) D=H4_ff_CQZ_D(15) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(14) D=H4_ff_CQZ_D(14) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(13) D=H4_ff_CQZ_D(13) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(12) D=H4_ff_CQZ_D(12) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(29) D=H4_ff_CQZ_D(29) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(11) D=H4_ff_CQZ_D(11) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(10) D=H4_ff_CQZ_D(10) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(9) D=H4_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(8) D=H4_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(7) D=H4_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(6) D=H4_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(5) D=H4_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(4) D=H4_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(3) D=H4_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(2) D=H4_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(28) D=H4_ff_CQZ_D(28) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(1) D=H4_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(0) D=H4_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(27) D=H4_ff_CQZ_D(27) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(26) D=H4_ff_CQZ_D(26) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(25) D=H4_ff_CQZ_D(25) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(24) D=H4_ff_CQZ_D(24) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(23) D=H4_ff_CQZ_D(23) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H4(22) D=H4_ff_CQZ_D(22) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(31) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(29) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(15) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(13) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(11) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(10) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(8) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(7) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(27) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(26) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(25) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(23) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(22) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(21) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(20) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=E(16) I3=H_LUT4_I2_I3 O=H4_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=H5(31) D=H5_ff_CQZ_D(31) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(30) D=H5_ff_CQZ_D(30) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(21) D=H5_ff_CQZ_D(21) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(20) D=H5_ff_CQZ_D(20) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(19) D=H5_ff_CQZ_D(19) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(18) D=H5_ff_CQZ_D(18) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(17) D=H5_ff_CQZ_D(17) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(16) D=H5_ff_CQZ_D(16) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(15) D=H5_ff_CQZ_D(15) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(14) D=H5_ff_CQZ_D(14) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(13) D=H5_ff_CQZ_D(13) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(12) D=H5_ff_CQZ_D(12) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(29) D=H5_ff_CQZ_D(29) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(11) D=H5_ff_CQZ_D(11) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(10) D=H5_ff_CQZ_D(10) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(9) D=H5_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(8) D=H5_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(7) D=H5_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(6) D=H5_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(5) D=H5_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(4) D=H5_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(3) D=H5_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(2) D=H5_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(28) D=H5_ff_CQZ_D(28) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(1) D=H5_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(0) D=H5_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(27) D=H5_ff_CQZ_D(27) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(26) D=H5_ff_CQZ_D(26) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(25) D=H5_ff_CQZ_D(25) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(24) D=H5_ff_CQZ_D(24) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(23) D=H5_ff_CQZ_D(23) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H5(22) D=H5_ff_CQZ_D(22) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(9) D=H6_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(8) D=H6_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(7) D=H6_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(6) D=H6_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(5) D=H6_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(4) D=H6_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(3) D=H6_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(2) D=H6_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(1) D=H6_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H6(0) D=H6_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=G(9) I3=H_LUT4_I2_I3 O=H6_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G(8) I3=cmd(2) O=H6_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G(7) I3=cmd(2) O=H6_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=G(6) I3=H_LUT4_I2_I3 O=H6_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G(5) I3=cmd(2) O=H6_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=G(4) I3=H_LUT4_I2_I3 O=H6_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G(3) I3=cmd(2) O=H6_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=G(2) I3=H_LUT4_I2_I3 O=H6_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G(1) I3=cmd(2) O=H6_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=G(0) I3=cmd(2) O=H6_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt ff CQZ=H7(9) D=H7_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H7(8) D=H7_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H7(7) D=H7_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H7(6) D=H7_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H7(5) D=H7_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H7(4) D=H7_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H7(3) D=H7_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H7(2) D=H7_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H7(1) D=H7_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H7(0) D=H7_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(9) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(8) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(7) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(6) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(5) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(4) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(3) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(2) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(1) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=H(0) I3=H_LUT4_I2_I3 O=H7_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=H(9) D=H_ff_CQZ_D(9) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H(8) D=H_ff_CQZ_D(8) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H(7) D=H_ff_CQZ_D(7) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H(6) D=H_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H(5) D=H_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H(4) D=H_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H(3) D=H_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H(2) D=H_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H(1) D=H_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=H(0) D=H_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN_LUT4_I3_O QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_I1 I2=H7_ff_CQZ_D(0) I3=H_ff_CQZ_D_LUT4_O_I3 O=H_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=$iopadmap$rst_i I1=H7_ff_CQZ_D(9) I2=A_ff_CQZ_D_LUT4_O_I2 I3=H_ff_CQZ_D_LUT4_O_1_I3 O=H_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110111000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1 I2=H7(9) I3=G(9) O=H_ff_CQZ_D_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100101000
+.subckt LUT4 I0=G(10) I1=H7(8) I2=G(8) I3=H_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=H7_ff_CQZ_D(8) I2=H_ff_CQZ_D_LUT4_O_2_I2 I3=$iopadmap$rst_i O=H_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100010001111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=G(8) I2=H_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=H_ff_CQZ_D_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=G(10) I1=H7(8) I2=G(8) I3=H_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$rst_i I1=H_ff_CQZ_D_LUT4_O_3_I1 I2=H7_ff_CQZ_D(7) I3=A_ff_CQZ_D_LUT4_O_I2 O=H_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000000010001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=H_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1 I2=H7(7) I3=G(7) O=H_ff_CQZ_D_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010100011010111
+.subckt LUT4 I0=G(10) I1=H7(7) I2=G(7) I3=H_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1 O=H_ff_CQZ_D_LUT4_O_2_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=H7(6) I2=G(6) I3=H_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=A_ff_CQZ_D_LUT4_O_I2 I1=H7_ff_CQZ_D(6) I2=H_ff_CQZ_D_LUT4_O_4_I2 I3=$iopadmap$rst_i O=H_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000100010001111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=G(6) I2=H_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=H_ff_CQZ_D_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000010111011
+.subckt LUT4 I0=G(10) I1=H7(6) I2=G(6) I3=H_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I0 I1=G(5) I2=H_ff_CQZ_D_LUT4_O_5_I2 I3=H_ff_CQZ_D_LUT4_O_5_I3 O=H_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111111000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=H_ff_CQZ_D_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0 I1=G(5) I2=H7(5) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=G(10) I1=H7(5) I2=G(5) I3=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0 O=H_ff_CQZ_D_LUT4_O_4_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=H7(4) I2=G(4) I3=H_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=$iopadmap$rst_i O=H_ff_CQZ_D_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=H7_ff_CQZ_D(5) I3=A_ff_CQZ_D_LUT4_O_I2 O=H_ff_CQZ_D_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_6_I0 I1=H_ff_CQZ_D_LUT4_O_6_I1 I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=H_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=H(4) I1=cmd(2) I2=G(4) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=H_ff_CQZ_D_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=G(10) I1=H7(4) I2=G(4) I3=H_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=G(10) I1=H7(3) I2=G(3) I3=H_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=H_ff_CQZ_D_LUT4_O_7_I3 O=H_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cmd(2) I1=H(3) I2=A_ff_CQZ_D_LUT4_O_I2 I3=H_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I1 I2=G(3) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=H_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3 I1=G(3) I2=H7(3) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=H_ff_CQZ_D_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011000000000
+.subckt LUT4 I0=H_ff_CQZ_D_LUT4_O_8_I0 I1=H_ff_CQZ_D_LUT4_O_8_I1 I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=H_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=H(2) I1=cmd(2) I2=G(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O O=H_ff_CQZ_D_LUT4_O_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111011100001111
+.subckt LUT4 I0=G(10) I1=H7(2) I2=G(2) I3=H_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=G(10) I1=H7(2) I2=G(2) I3=H_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_6_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=G(1) I1=H7(1) I2=H7(0) I3=G(0) O=H_ff_CQZ_D_LUT4_O_8_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=H_ff_CQZ_D_LUT4_O_9_I3 O=H_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cmd(2) I1=H(1) I2=A_ff_CQZ_D_LUT4_O_I2 I3=H_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3 O=H_ff_CQZ_D_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=G(1) I2=H_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=H_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=G(0) I1=H7(0) I2=G(1) I3=H7(1) O=H_ff_CQZ_D_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I1=H7(0) I2=G(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=H_ff_CQZ_D_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011110011111010
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=A_ff_CQZ_D_LUT4_O_I2 O=H_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=Kt(31) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(31) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(30) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(30) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(21) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(21) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(20) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(20) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(19) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(19) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(18) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(18) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(17) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(17) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(16) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(16) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(15) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(15) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(14) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(14) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(13) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(13) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(12) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(12) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(29) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(29) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(11) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(11) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(10) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(10) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(9) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(9) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(8) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(8) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(7) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(7) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(6) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(6) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(5) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(5) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(4) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(4) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(3) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(3) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(2) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(2) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(28) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(28) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(1) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(1) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(0) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(0) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(27) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(27) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(26) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(26) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(25) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(25) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(24) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(24) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(23) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(23) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Kt(22) D=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(22) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:653.9-729.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=Wt(31) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(30) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(21) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(20) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(19) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(18) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(17) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(16) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(15) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(14) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(13) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(12) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(29) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(11) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(10) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(9) D=text_i_LUT4_I2_O(9) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(8) D=text_i_LUT4_I2_O(8) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(7) D=text_i_LUT4_I2_O(7) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(6) D=text_i_LUT4_I2_O(6) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(5) D=text_i_LUT4_I2_O(5) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(4) D=text_i_LUT4_I2_O(4) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(3) D=text_i_LUT4_I2_O(3) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(2) D=text_i_LUT4_I2_O(2) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(28) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(1) D=text_i_LUT4_I2_O(1) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(0) D=text_i_LUT4_I2_O(0) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(27) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(26) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(25) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(24) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(23) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=Wt(22) D=G(10) QCK=$iopadmap$clk_i QEN=Wt_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=Wt_ff_CQZ_QEN O=Wt_ff_CQZ_QEN_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O O=Wt_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=busy O=busy_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_LUT4_I3_O I2=busy_LUT4_I3_O_LUT4_I1_I2 I3=busy_LUT4_I3_O_LUT4_I1_I3 O=busy_LUT4_I3_O_LUT4_I1_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I1_I2_LUT4_O_I0 I1=busy_LUT4_I3_O_LUT4_I1_I2_LUT4_O_I1 I2=read_counter(1) I3=read_counter(2) O=busy_LUT4_I3_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100101000000000
+.subckt LUT4 I0=G(10) I1=read_counter(0) I2=D(7) I3=C(7) O=busy_LUT4_I3_O_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=G(10) I1=read_counter(0) I2=B(7) I3=A(7) O=busy_LUT4_I3_O_LUT4_I1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I0 I1=busy_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I1 I2=read_counter(2) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110000001010
+.subckt LUT4 I0=G(10) I1=read_counter(0) I2=H(7) I3=G(7) O=busy_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=G(10) I1=read_counter(0) I2=F(7) I3=E(7) O=busy_LUT4_I3_O_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10101100
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_I0 I1=read_counter(2) I2=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_I2 I3=busy_LUT4_I3_O_LUT4_I3_1_O O=busy_LUT4_I3_O_LUT4_I1_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I0 I1=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1 I2=read_counter(2) I3=busy_LUT4_I3_O_LUT4_I3_3_O O=busy_LUT4_I3_O_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=F(5) I1=E(5) I2=read_counter_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=G(5) I1=H(5) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I0 I1=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1 I2=read_counter(2) I3=busy_LUT4_I3_O_LUT4_I3_4_O O=busy_LUT4_I3_O_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=F(4) I1=E(4) I2=read_counter_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=G(4) I1=H(4) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I0 I1=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1 I2=read_counter(2) I3=busy_LUT4_I3_O_LUT4_I3_5_O O=busy_LUT4_I3_O_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=F(3) I1=E(3) I2=read_counter_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=G(3) I1=H(3) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I0 I1=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1 I2=read_counter(2) I3=busy_LUT4_I3_O_LUT4_I3_6_O O=busy_LUT4_I3_O_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=F(2) I1=E(2) I2=read_counter_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=G(2) I1=H(2) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I0 I1=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I1 I2=read_counter(2) I3=busy_LUT4_I3_O_LUT4_I3_7_O O=busy_LUT4_I3_O_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=F(1) I1=E(1) I2=read_counter_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=G(1) I1=H(1) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I0 I1=read_counter(2) I2=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I2 I3=busy_LUT4_I3_O_LUT4_I3_8_O O=busy_LUT4_I3_O_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=G(0) I1=H(0) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=E(0) I1=F(0) I2=read_counter(0) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=G(8) I1=H(8) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=E(8) I1=F(8) I2=read_counter(0) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I1_O_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_I0 I1=busy_LUT4_I3_O_LUT4_I3_I1 I2=busy_LUT4_I3_O_LUT4_I3_I2 I3=busy_LUT4_I3_O O=busy_LUT4_I3_O_LUT4_I1_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_1_I0 I1=busy_LUT4_I3_O_LUT4_I3_1_I1 I2=read_counter(2) I3=busy_LUT4_I3_O O=busy_LUT4_I3_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=C(8) I1=D(8) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=A(8) I1=B(8) I2=read_counter(0) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_2_I0 I1=busy_LUT4_I3_O_LUT4_I3_2_I1 I2=busy_LUT4_I3_O_LUT4_I3_2_I2 I3=busy_LUT4_I3_O O=busy_LUT4_I3_O_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=F(6) I1=E(6) I2=read_counter_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I3_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=read_counter(1) I1=H(6) I2=read_counter(0) I3=busy_LUT4_I3_O_LUT4_I3_2_I1_LUT4_O_I3 O=busy_LUT4_I3_O_LUT4_I3_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=G(6) I1=read_counter(1) I2=read_counter(0) I3=read_counter(2) O=busy_LUT4_I3_O_LUT4_I3_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_2_I2_LUT4_O_I0 I1=busy_LUT4_I3_O_LUT4_I3_2_I2_LUT4_O_I1 I2=read_counter(1) I3=read_counter(2) O=busy_LUT4_I3_O_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=G(10) I1=read_counter(0) I2=B(6) I3=A(6) O=busy_LUT4_I3_O_LUT4_I3_2_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=G(10) I1=read_counter(0) I2=D(6) I3=C(6) O=busy_LUT4_I3_O_LUT4_I3_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_3_I0 I1=busy_LUT4_I3_O_LUT4_I3_3_I1 I2=read_counter(2) I3=busy_LUT4_I3_O O=busy_LUT4_I3_O_LUT4_I3_3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=A(5) I1=B(5) I2=read_counter(0) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I3_3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=C(5) I1=D(5) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I3_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_4_I0 I1=busy_LUT4_I3_O_LUT4_I3_4_I1 I2=read_counter(2) I3=busy_LUT4_I3_O O=busy_LUT4_I3_O_LUT4_I3_4_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=A(4) I1=B(4) I2=read_counter(0) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I3_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=C(4) I1=D(4) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I3_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_5_I0 I1=busy_LUT4_I3_O_LUT4_I3_5_I1 I2=read_counter(2) I3=busy_LUT4_I3_O O=busy_LUT4_I3_O_LUT4_I3_5_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=A(3) I1=B(3) I2=read_counter(0) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I3_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=C(3) I1=D(3) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I3_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_6_I0 I1=busy_LUT4_I3_O_LUT4_I3_6_I1 I2=read_counter(2) I3=busy_LUT4_I3_O O=busy_LUT4_I3_O_LUT4_I3_6_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=A(2) I1=B(2) I2=read_counter(0) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I3_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=C(2) I1=D(2) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I3_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_7_I0 I1=busy_LUT4_I3_O_LUT4_I3_7_I1 I2=read_counter(2) I3=busy_LUT4_I3_O O=busy_LUT4_I3_O_LUT4_I3_7_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=A(1) I1=B(1) I2=read_counter(0) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I3_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010110000000000
+.subckt LUT4 I0=C(1) I1=D(1) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I3_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101000001100
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_8_I0 I1=busy_LUT4_I3_O_LUT4_I3_8_I1 I2=read_counter(2) I3=busy_LUT4_I3_O O=busy_LUT4_I3_O_LUT4_I3_8_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=A(0) I1=B(0) I2=read_counter(0) I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I3_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=C(0) I1=D(0) I2=read_counter(1) I3=read_counter(0) O=busy_LUT4_I3_O_LUT4_I3_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000010100000011
+.subckt LUT4 I0=G(9) I1=read_counter(0) I2=busy_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I2 I3=read_counter(1) O=busy_LUT4_I3_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000001000100
+.subckt LUT4 I0=G(10) I1=read_counter_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 I2=E(9) I3=F(9) O=busy_LUT4_I3_O_LUT4_I3_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=read_counter(1) I1=H(9) I2=read_counter(0) I3=read_counter(2) O=busy_LUT4_I3_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=busy_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I0 I1=busy_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1 I2=read_counter(1) I3=read_counter(2) O=busy_LUT4_I3_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=G(10) I1=read_counter(0) I2=B(9) I3=A(9) O=busy_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt LUT4 I0=G(10) I1=read_counter(0) I2=D(9) I3=C(9) O=busy_LUT4_I3_O_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01010011
+.subckt ff CQZ=busy D=busy_ff_CQZ_D QCK=$iopadmap$clk_i QEN=busy_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=busy_ff_CQZ_D_LUT4_O_I2 I3=cmd(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=round(1) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=round(5) I2=round(4) I3=round(6) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=round(4) I1=round(5) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 I3=round(6) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=round(0) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I2=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_27_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_I1_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O I3=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001111111
+.subckt LUT4 I0=round(0) I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010001111
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1 I3=round_ff_CQZ_D_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=round(0) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(3) I3=round(2) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I1=round(4) I2=round(5) I3=round(6) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111111110001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_I2_LUT4_O_I0 I1=round(0) I2=round(1) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101011100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=A_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I3=round_ff_CQZ_D_LUT4_O_4_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I2 I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2_LUT4_I3_O I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1_LUT4_O_I1 I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000010111011
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=G(10) I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_10_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_10_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_10_I0_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_10_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O I2=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_11_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I0_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I2_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I0_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I1_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I1_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_12_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2_LUT4_O_I1_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I2_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I2_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_13_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_14_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I0_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0 I3=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011111111111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I2_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2_LUT4_O_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I0_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I0_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I1=round(0) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I0_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_2_O_LUT4_I1_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I1 I1=round(0) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_19_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2_LUT4_O_I3 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=round(0) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)"
+.param INIT 0000001100000101
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O I1=round_ff_CQZ_D_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_O_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I0_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=G(10) I1=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I2_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_9_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_I1_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_22_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_22_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_22_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I0_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I0_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=G(10) I1=G(10) I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I0_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_I1_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011111000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O I2=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100110011
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_25_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_25_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_25_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101001100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0_LUT4_O_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I0_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_25_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I0_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I0_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_O_LUT4_I2_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I0_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I3_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1 I3=round_ff_CQZ_D_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_24_I2_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_27_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_27_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_27_I0_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_27_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1100110000001110
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_27_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010001100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I2_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_29_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_O_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_29_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001110
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_29_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000011
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I0_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=round(1) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I2 I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110001011111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I3 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I0_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_I1_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2_LUT4_O_I1_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110100000000
+.subckt LUT4 I0=round(0) I1=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I1=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_2_I1_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I0_LUT4_O_I0_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_18_I1_LUT4_O_I0_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=round(2) I2=round(3) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111111111111
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I1 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_I1_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3_LUT4_I1_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000101100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2_LUT4_O_I1_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I0_LUT4_O_I2_LUT4_I2_O I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2 I3=$iopadmap$rst_i O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)"
+.param INIT 0000000000011111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I3 I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_1_I3 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I2_LUT4_O_I1_LUT4_O_I1_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_I2_I0_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I2_LUT4_O_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110111011100000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_17_I0_LUT4_O_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_21_I2_LUT4_O_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_7_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011010100000000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I1_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2_LUT4_O_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=round(0) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)"
+.param INIT 0000000000001011
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=G(10) I2=round_ff_CQZ_D_LUT4_O_4_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_9_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_9_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_9_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_23_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I3_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_9_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I0_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_26_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_O_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_20_I2_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I1_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I3=round(0) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111101110111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I3=round(0) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)"
+.param INIT 0000000000000111
+.subckt LUT4 I0=round(0) I1=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110100
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=round(1) I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1 I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_30_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1 I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2 I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_1_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_1_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_1_O_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_2_O_LUT4_I1_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_2_O_LUT4_I1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_8_I3_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I1_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_2_O_LUT4_I1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_16_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_2_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_O_I2_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I3 I2=round(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_6_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I2_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I1_LUT4_I1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_1_O_LUT4_I1_O_LUT4_I3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 00000001
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1 I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_O_LUT4_I3_I1 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(0) I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I2=round(1) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O I2=$iopadmap$rst_i I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(1) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2 I3=round_ff_CQZ_D_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=round(0) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_I2 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)"
+.param INIT 0000000100000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_I2_I0_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_1_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_O_LUT4_I2_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I3_LUT4_O_I0 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_O_LUT4_I3_I0 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=G(10) I1=round(1) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(2) I3=round(3) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I0_LUT4_I2_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0 I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I1 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_O_LUT4_I1_O_LUT4_I0_I1_LUT4_O_I1_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O I3=round(0) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=round(0) I1=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I2=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I3=round(1) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O_LUT4_I0_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111000000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3_LUT4_I2_O I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2_LUT4_I3_O O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3_LUT4_I2_O I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I0_O_LUT4_I1_O_LUT4_O_28_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_O_LUT4_I2_O_LUT4_I0_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_I1_LUT4_O_I2_LUT4_O_I2 I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_O_LUT4_I2_I0_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=round(1) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=round(1) I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=round(1) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I2_1_O_LUT4_I0_I2_LUT4_I3_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=round(4) I2=round(5) I3=round(6) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=round(5) I2=round(4) I3=round(6) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(2) I3=round(3) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_4_I2 I2=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(1) I3=round(0) O=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=cmd(1) I3=busy_ff_CQZ_D O=busy_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=cmd(2) I3=$iopadmap$rst_i O=H_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(30) I3=cmd(2) O=H0_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(29) I3=cmd(2) O=H0_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(9) I3=cmd(2) O=H0_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(6) I3=cmd(2) O=H0_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(5) I3=cmd(2) O=H0_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(2) I3=cmd(2) O=H0_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(1) I3=cmd(2) O=H0_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(0) I3=cmd(2) O=H0_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(31) I3=cmd(2) O=H1_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(29) I3=cmd(2) O=H1_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(28) I3=cmd(2) O=H1_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(27) I3=cmd(2) O=H1_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(27) I3=cmd(2) O=H0_ff_CQZ_D(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(25) I3=cmd(2) O=H1_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(24) I3=cmd(2) O=H1_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(22) I3=cmd(2) O=H1_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(21) I3=cmd(2) O=H1_ff_CQZ_D(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(18) I3=cmd(2) O=H1_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(17) I3=cmd(2) O=H1_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(16) I3=cmd(2) O=H1_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(15) I3=cmd(2) O=H1_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(13) I3=cmd(2) O=H1_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(11) I3=cmd(2) O=H1_ff_CQZ_D(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(25) I3=cmd(2) O=H0_ff_CQZ_D(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(10) I3=cmd(2) O=H1_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(9) I3=cmd(2) O=H1_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(7) I3=cmd(2) O=H1_ff_CQZ_D(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(2) I3=cmd(2) O=H1_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=B(0) I3=cmd(2) O=H1_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(31) I3=cmd(2) O=H3_ff_CQZ_D(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(29) I3=cmd(2) O=H3_ff_CQZ_D(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(26) I3=cmd(2) O=H3_ff_CQZ_D(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(24) I3=cmd(2) O=H3_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(22) I3=cmd(2) O=H3_ff_CQZ_D(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(19) I3=cmd(2) O=H0_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(19) I3=cmd(2) O=H3_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(18) I3=cmd(2) O=H3_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(17) I3=cmd(2) O=H3_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(16) I3=cmd(2) O=H3_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(15) I3=cmd(2) O=H3_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(14) I3=cmd(2) O=H3_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(13) I3=cmd(2) O=H3_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(12) I3=cmd(2) O=H3_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(10) I3=cmd(2) O=H3_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(8) I3=cmd(2) O=H3_ff_CQZ_D(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(16) I3=cmd(2) O=H0_ff_CQZ_D(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(5) I3=cmd(2) O=H3_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(4) I3=cmd(2) O=H3_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(3) I3=cmd(2) O=H3_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=D(1) I3=cmd(2) O=H3_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(30) I3=cmd(2) O=H4_ff_CQZ_D(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(28) I3=cmd(2) O=H4_ff_CQZ_D(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(24) I3=cmd(2) O=H4_ff_CQZ_D(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(19) I3=cmd(2) O=H4_ff_CQZ_D(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(18) I3=cmd(2) O=H4_ff_CQZ_D(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(17) I3=cmd(2) O=H4_ff_CQZ_D(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(15) I3=cmd(2) O=H0_ff_CQZ_D(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(14) I3=cmd(2) O=H4_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(12) I3=cmd(2) O=H4_ff_CQZ_D(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(9) I3=cmd(2) O=H4_ff_CQZ_D(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(6) I3=cmd(2) O=H4_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(5) I3=cmd(2) O=H4_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(4) I3=cmd(2) O=H4_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(3) I3=cmd(2) O=H4_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(2) I3=cmd(2) O=H4_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(1) I3=cmd(2) O=H4_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=E(0) I3=cmd(2) O=H4_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(14) I3=cmd(2) O=H0_ff_CQZ_D(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(13) I3=cmd(2) O=H0_ff_CQZ_D(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=A(10) I3=cmd(2) O=H0_ff_CQZ_D(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt ff CQZ=cmd(3) D=cmd_i_LUT4_I2_O(3) QCK=$iopadmap$clk_i QEN=cmd_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:169.9-182.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=cmd(2) D=cmd_i_LUT4_I2_O(2) QCK=$iopadmap$clk_i QEN=cmd_ff_CQZ_1_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:169.9-182.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=cmd(1) D=cmd_i_LUT4_I2_O(1) QCK=$iopadmap$clk_i QEN=cmd_ff_CQZ_3_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:169.9-182.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=cmd(0) D=cmd_i_LUT4_I2_O(0) QCK=$iopadmap$clk_i QEN=cmd_ff_CQZ_3_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:169.9-182.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy I3=cmd_ff_CQZ_1_QEN O=cmd_ff_CQZ_3_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$cmd_i(1) I3=cmd_ff_CQZ_QEN O=cmd_i_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$cmd_i(0) I3=cmd_ff_CQZ_QEN O=cmd_i_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$cmd_i(2) I3=$iopadmap$rst_i O=cmd_i_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=busy I3=$iopadmap$rst_i O=cmd_i_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$cmd_w_i I3=$iopadmap$rst_i O=cmd_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=$iopadmap$cmd_w_i O=cmd_ff_CQZ_1_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt ff CQZ=read_counter(2) D=read_counter_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=read_counter_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=read_counter(1) D=read_counter_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=read_counter_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=read_counter(0) D=read_counter_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=read_counter_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$rst_i I3=read_counter_ff_CQZ_D_LUT4_O_I3 O=read_counter_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=cmd(0) I1=read_counter(1) I2=read_counter(0) I3=$iopadmap$rst_i O=read_counter_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101011
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=cmd(0) I3=read_counter(0) O=read_counter_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=read_counter(0) I1=read_counter(1) I2=cmd(0) I3=read_counter(2) O=read_counter_ff_CQZ_D_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100001110
+.subckt LUT4 I0=G(10) I1=$iopadmap$rst_i I2=cmd(0) I3=read_counter_ff_CQZ_QEN_LUT4_O_I3 O=read_counter_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11111110
+.subckt LUT4 I0=G(10) I1=busy I2=read_counter(1) I3=read_counter_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3 O=read_counter_ff_CQZ_QEN_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=G(10) I1=G(10) I2=read_counter(2) I3=read_counter(0) O=read_counter_ff_CQZ_QEN_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt ff CQZ=round(6) D=round_ff_CQZ_D(6) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=round(5) D=round_ff_CQZ_D(5) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=round(4) D=round_ff_CQZ_D(4) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=round(3) D=round_ff_CQZ_D(3) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=round(2) D=round_ff_CQZ_D(2) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=round(1) D=round_ff_CQZ_D(1) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt ff CQZ=round(0) D=round_ff_CQZ_D(0) QCK=$iopadmap$clk_i QEN=$auto$hilomap.cc:39:hilomap_worker$30534 QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:217.9-647.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:22.8-22.87"
+.subckt LUT4 I0=G(10) I1=G(10) I2=round_ff_CQZ_D_LUT4_O_I2 I3=$iopadmap$rst_i O=round_ff_CQZ_D(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O I1=round(4) I2=round(5) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=round_ff_CQZ_D(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=round(4) I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O O=round_ff_CQZ_D(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=round_ff_CQZ_D_LUT4_O_4_I3 I1=round(2) I2=round(3) I3=H_ff_CQZ_D_LUT4_O_5_I0 O=round_ff_CQZ_D(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=round(2) I3=round_ff_CQZ_D_LUT4_O_4_I3 O=round_ff_CQZ_D(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round_ff_CQZ_D_LUT4_O_4_I3 I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3 O=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(2) I3=round(3) O=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round(1) I3=round(0) O=round_ff_CQZ_D_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=H_ff_CQZ_D_LUT4_O_5_I0 I2=round(1) I3=round(0) O=round_ff_CQZ_D(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01100000
+.subckt LUT4 I0=G(10) I1=Wt_ff_CQZ_QEN I2=$iopadmap$rst_i I3=round(0) O=round_ff_CQZ_D(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=G(10) I1=G(10) I2=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2 I3=round_ff_CQZ_D_LUT4_O_4_I3_LUT4_I2_O O=round_ff_CQZ_D_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=round(5) I2=round(4) I3=round(6) O=round_ff_CQZ_D_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(9) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(8) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(7) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(6) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(5) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(4) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(3) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(2) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(1) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=G(10) I1=G(10) I2=$iopadmap$text_i(0) I3=busy_ff_CQZ_D_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I3_2_O_LUT4_I2_O_LUT4_I3_1_O_LUT4_I1_O O=text_i_LUT4_I2_O(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt ff CQZ=$iopadmap$text_o(9) D=busy_LUT4_I3_O_LUT4_I1_O(9) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$text_o(8) D=busy_LUT4_I3_O_LUT4_I1_O(8) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$text_o(7) D=busy_LUT4_I3_O_LUT4_I1_O(7) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$text_o(6) D=busy_LUT4_I3_O_LUT4_I1_O(6) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$text_o(5) D=busy_LUT4_I3_O_LUT4_I1_O(5) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$text_o(4) D=busy_LUT4_I3_O_LUT4_I1_O(4) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$text_o(3) D=busy_LUT4_I3_O_LUT4_I1_O(3) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$text_o(2) D=busy_LUT4_I3_O_LUT4_I1_O(2) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$text_o(1) D=busy_LUT4_I3_O_LUT4_I1_O(1) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt ff CQZ=$iopadmap$text_o(0) D=busy_LUT4_I3_O_LUT4_I1_O(0) QCK=$iopadmap$clk_i QEN=text_o_ff_CQZ_QEN QRT=G(10) QST=G(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/git/yosys-testing/Designs/sha256/rtl/sha256.v:734.9-771.12|/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_ffs_map.v:120.8-120.84"
+.subckt LUT4 I0=G(10) I1=G(10) I2=cmd(0) I3=$iopadmap$rst_i O=text_o_ff_CQZ_QEN
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.end
diff --git a/BENCHMARK/unsigned_mult_80/rtl/unsigned_mult_80.v b/BENCHMARK/unsigned_mult_80/rtl/unsigned_mult_80.v
new file mode 100644
index 0000000..f88347f
--- /dev/null
+++ b/BENCHMARK/unsigned_mult_80/rtl/unsigned_mult_80.v
@@ -0,0 +1,10 @@
+module unsigned_mult_80 (out, a, b);
+output [40:0] out;
+wire [80:0] mult_wire;
+	input  [40:0] a;
+	input  [40:0] b;
+
+	assign mult_wire = a * b;
+    assign out = mult_wire[80:40] | mult_wire[39:0];
+
+endmodule
diff --git a/BENCHMARK/unsigned_mult_80/unsigned_mult_80_yosys.blif b/BENCHMARK/unsigned_mult_80/unsigned_mult_80_yosys.blif
new file mode 100644
index 0000000..96b585b
--- /dev/null
+++ b/BENCHMARK/unsigned_mult_80/unsigned_mult_80_yosys.blif
@@ -0,0 +1,23940 @@
+# Generated by Yosys 0.9+2406 (git sha1 470f9532, gcc 9.3.0 -fPIC -Os)
+
+.model unsigned_mult_80
+.inputs a(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7) a(8) a(9) a(10) a(11) a(12) a(13) a(14) a(15) a(16) a(17) a(18) a(19) a(20) a(21) a(22) a(23) a(24) a(25) a(26) a(27) a(28) a(29) a(30) a(31) a(32) a(33) a(34) a(35) a(36) a(37) a(38) a(39) a(40) b(0) b(1) b(2) b(3) b(4) b(5) b(6) b(7) b(8) b(9) b(10) b(11) b(12) b(13) b(14) b(15) b(16) b(17) b(18) b(19) b(20) b(21) b(22) b(23) b(24) b(25) b(26) b(27) b(28) b(29) b(30) b(31) b(32) b(33) b(34) b(35) b(36) b(37) b(38) b(39) b(40)
+.outputs out(0) out(1) out(2) out(3) out(4) out(5) out(6) out(7) out(8) out(9) out(10) out(11) out(12) out(13) out(14) out(15) out(16) out(17) out(18) out(19) out(20) out(21) out(22) out(23) out(24) out(25) out(26) out(27) out(28) out(29) out(30) out(31) out(32) out(33) out(34) out(35) out(36) out(37) out(38) out(39) out(40)
+.names $false
+.names $true
+1
+.names $undef
+.subckt logic_0 a=mult_wire(0)
+.subckt in_buff A=a(0) Q=$iopadmap$a(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(1) Q=$iopadmap$a(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(10) Q=$iopadmap$a(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(11) Q=$iopadmap$a(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(12) Q=$iopadmap$a(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(13) Q=$iopadmap$a(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(14) Q=$iopadmap$a(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(15) Q=$iopadmap$a(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(16) Q=$iopadmap$a(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(17) Q=$iopadmap$a(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(18) Q=$iopadmap$a(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(19) Q=$iopadmap$a(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(2) Q=$iopadmap$a(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(20) Q=$iopadmap$a(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(21) Q=$iopadmap$a(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(22) Q=$iopadmap$a(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(23) Q=$iopadmap$a(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(24) Q=$iopadmap$a(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(25) Q=$iopadmap$a(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(26) Q=$iopadmap$a(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(27) Q=$iopadmap$a(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(28) Q=$iopadmap$a(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(29) Q=$iopadmap$a(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(3) Q=$iopadmap$a(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(30) Q=$iopadmap$a(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(31) Q=$iopadmap$a(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(32) Q=$iopadmap$a(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(33) Q=$iopadmap$a(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(34) Q=$iopadmap$a(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(35) Q=$iopadmap$a(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(36) Q=$iopadmap$a(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(37) Q=$iopadmap$a(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(38) Q=$iopadmap$a(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(39) Q=$iopadmap$a(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(4) Q=$iopadmap$a(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(40) Q=$iopadmap$a(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(5) Q=$iopadmap$a(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(6) Q=$iopadmap$a(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(7) Q=$iopadmap$a(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(8) Q=$iopadmap$a(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=a(9) Q=$iopadmap$a(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(0) Q=$iopadmap$b(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(1) Q=$iopadmap$b(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(10) Q=$iopadmap$b(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(11) Q=$iopadmap$b(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(12) Q=$iopadmap$b(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(13) Q=$iopadmap$b(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(14) Q=$iopadmap$b(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(15) Q=$iopadmap$b(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(16) Q=$iopadmap$b(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(17) Q=$iopadmap$b(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(18) Q=$iopadmap$b(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(19) Q=$iopadmap$b(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(2) Q=$iopadmap$b(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(20) Q=$iopadmap$b(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(21) Q=$iopadmap$b(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(22) Q=$iopadmap$b(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(23) Q=$iopadmap$b(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(24) Q=$iopadmap$b(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(25) Q=$iopadmap$b(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(26) Q=$iopadmap$b(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(27) Q=$iopadmap$b(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(28) Q=$iopadmap$b(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(29) Q=$iopadmap$b(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(3) Q=$iopadmap$b(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(30) Q=$iopadmap$b(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(31) Q=$iopadmap$b(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(32) Q=$iopadmap$b(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(33) Q=$iopadmap$b(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(34) Q=$iopadmap$b(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(35) Q=$iopadmap$b(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(36) Q=$iopadmap$b(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(37) Q=$iopadmap$b(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(38) Q=$iopadmap$b(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(39) Q=$iopadmap$b(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(4) Q=$iopadmap$b(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(40) Q=$iopadmap$b(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(5) Q=$iopadmap$b(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(6) Q=$iopadmap$b(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(7) Q=$iopadmap$b(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(8) Q=$iopadmap$b(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt in_buff A=b(9) Q=$iopadmap$b(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:12.13-12.45"
+.subckt out_buff A=$iopadmap$out(0) Q=out(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(1) Q=out(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(10) Q=out(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(11) Q=out(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(12) Q=out(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(13) Q=out(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(14) Q=out(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(15) Q=out(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(16) Q=out(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(17) Q=out(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(18) Q=out(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(19) Q=out(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(2) Q=out(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(20) Q=out(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(21) Q=out(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(22) Q=out(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(23) Q=out(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(24) Q=out(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(25) Q=out(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(26) Q=out(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(27) Q=out(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(28) Q=out(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(29) Q=out(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(3) Q=out(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(30) Q=out(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(31) Q=out(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(32) Q=out(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(33) Q=out(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(34) Q=out(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(35) Q=out(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(36) Q=out(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(37) Q=out(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(38) Q=out(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(39) Q=out(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(4) Q=out(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=mult_wire(80) Q=out(40)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(5) Q=out(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(6) Q=out(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(7) Q=out(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(8) Q=out(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt out_buff A=$iopadmap$out(9) Q=out(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_io_map.v:5.14-5.46"
+.subckt LUT4 I0=out_LUT4_O_I0 I1=out_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=$iopadmap$out(37)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101110111110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1 I2=out_LUT4_O_1_I2 I3=out_LUT4_O_1_I3 O=$iopadmap$out(31)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111110
+.subckt LUT4 I0=out_LUT4_O_10_I0 I1=out_LUT4_O_10_I1 I2=out_LUT4_O_10_I2 I3=out_LUT4_O_10_I3 O=$iopadmap$out(34)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110111111110110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_8_I0_LUT4_O_I2 I2=out_LUT4_O_8_I0_LUT4_O_I1 I3=out_LUT4_O_13_I2_LUT4_I3_O_LUT4_I2_O O=out_LUT4_O_10_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I3 I3=out_LUT4_O_9_I1_LUT4_O_I2 O=out_LUT4_O_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I2_LUT4_O_I1 I2=out_LUT4_O_11_I3 I3=out_LUT4_O_11_I0 O=out_LUT4_O_10_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I3_LUT4_O_I2_LUT4_I3_O I2=out_LUT4_O_10_I2_LUT4_O_I1 I3=out_LUT4_O_10_I3_LUT4_I2_O O=out_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I3 I3=out_LUT4_O_9_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3 O=out_LUT4_O_10_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I2=$iopadmap$a(0) I3=$iopadmap$b(30) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(15) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(13) I2=$iopadmap$a(17) I3=$iopadmap$b(12) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(18) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(10) I2=$iopadmap$a(20) I3=$iopadmap$b(9) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(17) I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(9) I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(7) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(22) I2=$iopadmap$a(9) I3=$iopadmap$b(21) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(10) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(19) I2=$iopadmap$a(12) I3=$iopadmap$b(18) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(15) I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(12) I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(13) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(16) I2=$iopadmap$a(15) I3=$iopadmap$b(15) O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000100010
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_38_I1_LUT4_O_I2_LUT4_O_I3 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(31) I2=$iopadmap$a(1) I3=$iopadmap$b(30) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(1) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(29) I3=$iopadmap$a(2) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(29) I2=$iopadmap$a(2) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(28) I2=$iopadmap$a(4) I3=$iopadmap$b(27) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=$iopadmap$b(32) I3=$iopadmap$a(0) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(3) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(28) I2=$iopadmap$a(5) I3=$iopadmap$b(27) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(31) I3=$iopadmap$b(30) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(4) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(26) I3=$iopadmap$a(5) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(7) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(23) I2=$iopadmap$a(8) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(22) I2=$iopadmap$a(10) I3=$iopadmap$b(21) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(26) I2=$iopadmap$a(5) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(25) I2=$iopadmap$a(7) I3=$iopadmap$b(24) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(6) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(25) I2=$iopadmap$a(8) I3=$iopadmap$b(24) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(23) I3=$iopadmap$a(8) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(11) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(19) I2=$iopadmap$a(13) I3=$iopadmap$b(18) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(10) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(21) I3=$iopadmap$b(8) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(7) I2=$iopadmap$a(23) I3=$iopadmap$b(6) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(23) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(20) I2=$iopadmap$b(8) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(18) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(16) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(13) I2=$iopadmap$a(18) I3=$iopadmap$b(12) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(19) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(10) I2=$iopadmap$a(21) I3=$iopadmap$b(9) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(13) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(14) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(16) I2=$iopadmap$a(16) I3=$iopadmap$b(15) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(16) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(32) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(1) I2=$iopadmap$a(34) I3=$iopadmap$b(0) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(31) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(29) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(28) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(31) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(1) I2=$iopadmap$a(33) I3=$iopadmap$b(0) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(30) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(29) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(27) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(30) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(1) I2=$iopadmap$a(32) I3=$iopadmap$b(0) O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_11_I0 I1=out_LUT4_O_11_I1 I2=out_LUT4_O_11_I2 I3=out_LUT4_O_11_I3 O=$iopadmap$out(33)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I3 I3=out_LUT4_O_12_I2 O=out_LUT4_O_11_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_11_I3_LUT4_O_I3 I2=out_LUT4_O_11_I3_LUT4_O_I2 I3=out_LUT4_O_11_I1 O=out_LUT4_O_10_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I2_LUT4_O_I3 I3=out_LUT4_O_12_I2_LUT4_O_I2 O=out_LUT4_O_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_13_I2_LUT4_I3_O_LUT4_I2_O I1=out_LUT4_O_12_I1_LUT4_O_I3 I2=out_LUT4_O_12_I1_LUT4_O_I2 I3=out_LUT4_O_11_I2_LUT4_O_I3 O=out_LUT4_O_11_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I0 O=out_LUT4_O_11_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_I2_O I2=out_LUT4_O_11_I3 I3=out_LUT4_O_12_I2 O=out_LUT4_O_11_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_11_I3_LUT4_O_I2 I3=out_LUT4_O_11_I3_LUT4_O_I3 O=out_LUT4_O_11_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_11_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_11_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_13_I2_LUT4_I3_O_LUT4_I2_O I1=out_LUT4_O_12_I1 I2=out_LUT4_O_12_I2 I3=out_LUT4_O_12_I3 O=$iopadmap$out(32)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011001101111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_11_I2_LUT4_O_I3 I3=out_LUT4_O_12_I1 O=out_LUT4_O_8_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I1_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3 O=out_LUT4_O_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(40) I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(30) I3=$iopadmap$b(40) O=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(40) I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(29) I3=$iopadmap$b(40) O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(32) I3=$iopadmap$a(39) O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(31) I3=$iopadmap$a(40) O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(35) I3=$iopadmap$a(36) O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(35) I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I3 O=out_LUT4_O_12_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111110110000010
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(30) I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(0) I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$a(2) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(1) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(28) I2=$iopadmap$a(3) I3=$iopadmap$b(27) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(28) I2=$iopadmap$a(2) I3=$iopadmap$b(27) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(29) I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(28) I2=$iopadmap$b(27) I3=out_LUT4_O_38_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(6) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(22) I2=$iopadmap$a(8) I3=$iopadmap$b(21) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(9) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(19) I2=$iopadmap$a(11) I3=$iopadmap$b(18) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(8) I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(11) I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(12) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(16) I2=$iopadmap$a(14) I3=$iopadmap$b(15) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(14) I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(6) I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(3) I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(4) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(25) I2=$iopadmap$a(6) I3=$iopadmap$b(24) O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_12_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I3 I2=out_LUT4_O_1_I1_LUT4_O_I2 I3=out_LUT4_O_12_I3_LUT4_O_I3 O=out_LUT4_O_12_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=out_LUT4_O_1_I2_LUT4_O_I0 I1=out_LUT4_O_1_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3 O=out_LUT4_O_12_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_13_I1 I2=out_LUT4_O_13_I2 I3=out_LUT4_O_13_I3 O=$iopadmap$out(30)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=out_LUT4_O_14_I1 I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=out_LUT4_O_2_I1_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_13_I1_LUT4_O_I3 O=out_LUT4_O_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I2_LUT4_O_I3 I3=out_LUT4_O_1_I2_LUT4_O_I0 O=out_LUT4_O_13_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I3_LUT4_O_I3 I3=out_LUT4_O_13_I2 O=out_LUT4_O_13_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=out_LUT4_O_13_I3_LUT4_O_I3 I1=out_LUT4_O_13_I3_LUT4_O_I2 I2=out_LUT4_O_13_I2_LUT4_I3_O I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_I2_O O=out_LUT4_O_13_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I3_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1 O=out_LUT4_O_13_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_13_I3_LUT4_O_I2 I3=out_LUT4_O_13_I3_LUT4_O_I3 O=out_LUT4_O_13_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_14_I0_LUT4_O_I2 O=out_LUT4_O_13_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=out_LUT4_O_17_I2_LUT4_I3_O_LUT4_I2_O I1=out_LUT4_O_2_I2_LUT4_O_I2 I2=out_LUT4_O_2_I2_LUT4_O_I1 I3=out_LUT4_O_2_I3_LUT4_I3_O O=out_LUT4_O_13_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=out_LUT4_O_14_I0 I1=out_LUT4_O_14_I1 I2=out_LUT4_O_2_I1_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=$iopadmap$out(29)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111010101011
+.subckt LUT4 I0=out_LUT4_O_2_I2 I1=out_LUT4_O_2_I3 I2=out_LUT4_O_14_I0_LUT4_O_I2 I3=out_LUT4_O_14_I0_LUT4_O_I3 O=out_LUT4_O_14_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3 I3=out_LUT4_O_2_I3_LUT4_O_I2 O=out_LUT4_O_14_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_14_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_14_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_14_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1 I3=out_LUT4_O_14_I1_LUT4_O_I3 O=out_LUT4_O_14_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I1 I3=out_LUT4_O_2_I0_LUT4_O_I2 O=out_LUT4_O_14_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I0 I1=out_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_14_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_14_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=out_LUT4_O_15_I0 I1=out_LUT4_O_15_I1 I2=out_LUT4_O_15_I2 I3=out_LUT4_O_15_I3 O=$iopadmap$out(27)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_16_I2 I3=out_LUT4_O_17_I2_LUT4_I3_O_LUT4_I2_O O=out_LUT4_O_15_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_15_I3_LUT4_O_I3 I2=out_LUT4_O_15_I3_LUT4_O_I2 I3=out_LUT4_O_15_I1 O=out_LUT4_O_2_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_16_I2_LUT4_O_I3 I3=out_LUT4_O_16_I2_LUT4_O_I2 O=out_LUT4_O_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_16_I1_LUT4_O_I3 I1=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_15_I2_LUT4_O_I3 O=out_LUT4_O_15_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_14_I1_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_2_I0_LUT4_O_I0 O=out_LUT4_O_15_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_15_I3 I3=out_LUT4_O_16_I2 O=out_LUT4_O_2_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_15_I3_LUT4_O_I2 I3=out_LUT4_O_15_I3_LUT4_O_I3 O=out_LUT4_O_15_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_15_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_15_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_16_I1 I2=out_LUT4_O_16_I2 I3=out_LUT4_O_17_I2_LUT4_I3_O_LUT4_I2_O O=$iopadmap$out(26)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_16_I1_LUT4_O_I3 O=out_LUT4_O_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I1_LUT4_O_I3 I2=out_LUT4_O_3_I1_LUT4_O_I2 I3=out_LUT4_O_16_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_16_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_16_I2_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I3 O=out_LUT4_O_16_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(40) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(24) I3=$iopadmap$b(40) O=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(40) I2=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(23) I3=$iopadmap$b(40) O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_17_I1 I2=out_LUT4_O_17_I2 I3=out_LUT4_O_17_I3 O=$iopadmap$out(24)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=out_LUT4_O_18_I1 I1=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_17_I1_LUT4_O_I3 O=out_LUT4_O_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I3 I3=out_LUT4_O_3_I2_LUT4_O_I0 O=out_LUT4_O_17_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I3 I3=out_LUT4_O_17_I2 O=out_LUT4_O_17_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=out_LUT4_O_17_I3_LUT4_O_I3 I1=out_LUT4_O_17_I3_LUT4_O_I2 I2=out_LUT4_O_17_I2_LUT4_I3_O I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_I2_O O=out_LUT4_O_17_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111100000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1 O=out_LUT4_O_17_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_17_I3_LUT4_O_I2 I3=out_LUT4_O_17_I3_LUT4_O_I3 O=out_LUT4_O_17_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_18_I0_LUT4_O_I3_LUT4_O_I3 I2=out_LUT4_O_18_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_18_I0_LUT4_O_I2 O=out_LUT4_O_17_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_21_I3_LUT4_I2_O_LUT4_I2_O I1=out_LUT4_O_4_I2_LUT4_O_I2 I2=out_LUT4_O_4_I2_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_I3_O O=out_LUT4_O_17_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=out_LUT4_O_18_I0 I1=out_LUT4_O_18_I1 I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=$iopadmap$out(23)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111011101011
+.subckt LUT4 I0=out_LUT4_O_4_I2 I1=out_LUT4_O_4_I3 I2=out_LUT4_O_18_I0_LUT4_O_I2 I3=out_LUT4_O_18_I0_LUT4_O_I3 O=out_LUT4_O_18_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I3 I3=out_LUT4_O_4_I3_LUT4_O_I2 O=out_LUT4_O_18_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_18_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_18_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_18_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_18_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_18_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1 I2=out_LUT4_O_4_I0_LUT4_O_I3 I3=out_LUT4_O_18_I1_LUT4_O_I3 O=out_LUT4_O_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_19_I1 I2=out_LUT4_O_19_I2 I3=out_LUT4_O_19_I3 O=$iopadmap$out(21)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I0_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I1 O=out_LUT4_O_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I0_LUT4_O_I2 I2=out_LUT4_O_4_I0_LUT4_O_I1 I3=out_LUT4_O_19_I2 O=out_LUT4_O_18_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_19_I2_LUT4_O_I0 I1=out_LUT4_O_19_I2_LUT4_O_I1 I2=out_LUT4_O_20_I3 I3=out_LUT4_O_19_I2_LUT4_O_I3 O=out_LUT4_O_19_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011110001
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I2_LUT4_I0_O I1=out_LUT4_O_22_I2_LUT4_O_I2 I2=out_LUT4_O_22_I2_LUT4_O_I1 I3=out_LUT4_O_22_I3_LUT4_I2_O O=out_LUT4_O_19_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111100000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I2_LUT4_O_I2 I2=out_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_19_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_20_I3_LUT4_O_I3 I3=out_LUT4_O_20_I3_LUT4_O_I1 O=out_LUT4_O_19_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_21_I3_LUT4_I2_O_LUT4_I2_O I1=out_LUT4_O_20_I1_LUT4_O_I3 I2=out_LUT4_O_20_I1_LUT4_O_I2 I3=out_LUT4_O_19_I3_LUT4_O_I3 O=out_LUT4_O_19_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I0 O=out_LUT4_O_19_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I1_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I3 O=out_LUT4_O_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(28) I3=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(26) O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(29) O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(1) I2=$iopadmap$a(31) I3=$iopadmap$b(0) O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_1_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_1_I2_LUT4_O_I0 I1=out_LUT4_O_1_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3 O=out_LUT4_O_1_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I2 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(26) I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(24) O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(27) O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(1) I2=$iopadmap$a(29) I3=$iopadmap$b(0) O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I1_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=out_LUT4_O_1_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(2) I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(3) O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(25) I2=$iopadmap$a(5) I3=$iopadmap$b(24) O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(5) I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_10_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(25) O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(28) O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(1) I2=$iopadmap$a(30) I3=$iopadmap$b(0) O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(27) I3=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_12_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=out_LUT4_O_13_I3 I1=out_LUT4_O_1_I3_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I3 O=out_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(27) I3=$iopadmap$b(40) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(40) I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(39) I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(29) I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(30) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(37) I2=$iopadmap$a(32) I3=$iopadmap$b(36) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(28) I3=$iopadmap$b(39) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$a(40) I2=$iopadmap$b(29) I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(28) I3=$iopadmap$a(39) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(32) I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(31) I3=$iopadmap$a(38) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(30) I3=$iopadmap$a(39) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(29) I2=$iopadmap$a(40) I3=$iopadmap$b(28) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(36) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(31) I2=$iopadmap$a(38) I3=$iopadmap$b(30) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(40) I3=$iopadmap$b(27) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(29) I3=$iopadmap$a(38) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(34) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(34) I2=$iopadmap$a(36) I3=$iopadmap$b(33) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(35) I2=$iopadmap$a(33) I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(34) I2=$iopadmap$a(35) I3=$iopadmap$b(33) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(36) I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(30) I2=$iopadmap$a(37) I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3 I1=out_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_1_I3_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(40) I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(39) I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(30) I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=$iopadmap$b(38) I3=$iopadmap$a(31) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(29) I3=$iopadmap$b(39) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(28) I3=$iopadmap$b(40) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(38) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(32) I2=$iopadmap$a(38) I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 O=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(31) I2=$iopadmap$a(40) I3=$iopadmap$b(30) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(35) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(34) I2=$iopadmap$a(37) I3=$iopadmap$b(33) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$a(37) I3=$iopadmap$b(32) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(34) I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$a(40) I3=$iopadmap$b(29) O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_1_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_2_I0 I1=out_LUT4_O_2_I1 I2=out_LUT4_O_2_I2 I3=out_LUT4_O_2_I3 O=$iopadmap$out(28)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110111111110110
+.subckt LUT4 I0=out_LUT4_O_21_I3_LUT4_I2_O_LUT4_I2_O I1=out_LUT4_O_20_I1 I2=out_LUT4_O_20_I2 I3=out_LUT4_O_20_I3 O=$iopadmap$out(20)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110111111110110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_19_I3_LUT4_O_I3 I3=out_LUT4_O_20_I1 O=out_LUT4_O_4_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_20_I1_LUT4_O_I2 I3=out_LUT4_O_20_I1_LUT4_O_I3 O=out_LUT4_O_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_20_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(40) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(18) I3=$iopadmap$b(40) O=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_20_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_19_I2_LUT4_O_I1 I3=out_LUT4_O_19_I2_LUT4_O_I0 O=out_LUT4_O_20_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_20_I3_LUT4_O_I1 I2=out_LUT4_O_20_I3_LUT4_O_I2 I3=out_LUT4_O_20_I3_LUT4_O_I3 O=out_LUT4_O_20_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_20_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_20_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_20_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_20_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_21_I0 I1=out_LUT4_O_21_I1 I2=out_LUT4_O_21_I2 I3=out_LUT4_O_21_I3 O=$iopadmap$out(19)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I1 I3=out_LUT4_O_22_I0 O=out_LUT4_O_21_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2 I2=out_LUT4_O_21_I3_LUT4_O_I3 I3=out_LUT4_O_21_I1 O=out_LUT4_O_21_I1_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I1_LUT4_O_I3 I3=out_LUT4_O_22_I1_LUT4_O_I2 O=out_LUT4_O_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_22_I2 I1=out_LUT4_O_22_I3 I2=out_LUT4_O_21_I2_LUT4_O_I2 I3=out_LUT4_O_21_I2_LUT4_O_I3 O=out_LUT4_O_21_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3 O=out_LUT4_O_21_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_21_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_20_I3_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_21_I3 I3=out_LUT4_O_22_I1 O=out_LUT4_O_21_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=out_LUT4_O_22_I0_LUT4_O_I3 I1=out_LUT4_O_22_I0_LUT4_O_I2 I2=out_LUT4_O_21_I3_LUT4_I2_O I3=out_LUT4_O_21_I1_LUT4_I3_O O=out_LUT4_O_21_I3_LUT4_I2_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_21_I3_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I3 O=out_LUT4_O_21_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(40) I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(17) I3=$iopadmap$b(40) O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_21_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_22_I0 I1=out_LUT4_O_22_I1 I2=out_LUT4_O_22_I2 I3=out_LUT4_O_22_I3 O=$iopadmap$out(18)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110111111110110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I0_LUT4_O_I2 I3=out_LUT4_O_22_I0_LUT4_O_I3 O=out_LUT4_O_22_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_I3_O_LUT4_I2_O I1=out_LUT4_O_24_I0_LUT4_O_I2 I2=out_LUT4_O_24_I0_LUT4_O_I1 I3=out_LUT4_O_23_I3_LUT4_I2_O O=out_LUT4_O_22_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I1_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I3 O=out_LUT4_O_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(40) I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(16) I3=$iopadmap$b(40) O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I2_LUT4_O_I1 I2=out_LUT4_O_22_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I2_LUT4_I0_O O=out_LUT4_O_22_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I2_LUT4_O_I3_LUT4_O_I3 I2=out_LUT4_O_23_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I2_LUT4_O_I2 O=out_LUT4_O_22_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3 I3=out_LUT4_O_21_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3 O=out_LUT4_O_22_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I1 I3=out_LUT4_O_22_I3_LUT4_O_I3 O=out_LUT4_O_21_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(2) I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(0) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(13) I2=$iopadmap$a(2) I3=$iopadmap$b(12) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(3) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(10) I2=$iopadmap$a(5) I3=$iopadmap$b(9) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(5) I3=$iopadmap$b(8) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(7) I2=$iopadmap$a(7) I3=$iopadmap$b(6) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(7) I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(4) I2=$iopadmap$a(9) I3=$iopadmap$b(3) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(4) I2=$iopadmap$b(8) I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(15) I3=$iopadmap$a(0) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(0) I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$a(2) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(3) I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(14) I3=$iopadmap$a(1) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(11) I3=$iopadmap$a(4) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(5) I2=$iopadmap$b(8) I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(6) I3=$iopadmap$b(8) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(7) I2=$iopadmap$a(8) I3=$iopadmap$b(6) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(8) I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(4) I2=$iopadmap$a(10) I3=$iopadmap$b(3) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(15) I2=$iopadmap$a(0) I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(6) I2=$iopadmap$b(8) I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$a(7) I3=$iopadmap$b(8) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(9) I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(4) I2=$iopadmap$a(11) I3=$iopadmap$b(3) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(0) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(16) I2=$iopadmap$a(2) I3=$iopadmap$b(15) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(14) I2=$iopadmap$a(2) I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(13) I2=$iopadmap$a(4) I3=$iopadmap$b(12) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_23_I0 I1=out_LUT4_O_23_I1 I2=out_LUT4_O_23_I2 I3=out_LUT4_O_23_I3 O=$iopadmap$out(17)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I1 I3=out_LUT4_O_24_I0 O=out_LUT4_O_23_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2 I2=out_LUT4_O_23_I3_LUT4_O_I3 I3=out_LUT4_O_23_I1 O=out_LUT4_O_22_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I1_LUT4_O_I3 I3=out_LUT4_O_24_I1_LUT4_O_I2 O=out_LUT4_O_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I2_LUT4_I0_O I1=out_LUT4_O_24_I3 I2=out_LUT4_O_23_I2_LUT4_O_I2 I3=out_LUT4_O_23_I2_LUT4_O_I3 O=out_LUT4_O_23_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001000001101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I3_LUT4_O_I3 I3=out_LUT4_O_24_I3_LUT4_O_I1 O=out_LUT4_O_23_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_22_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_23_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I3 I3=out_LUT4_O_24_I1 O=out_LUT4_O_23_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I3_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I3 O=out_LUT4_O_23_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(40) I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(39) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(16) I3=$iopadmap$b(39) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(15) I3=$iopadmap$b(40) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(26) I3=$iopadmap$a(29) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(31) I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(28) I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(32) I3=$iopadmap$a(23) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(29) I3=$iopadmap$a(26) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(25) I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(35) I3=$iopadmap$a(20) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(19) I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(22) I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(24) I2=$iopadmap$a(23) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(36) I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$a(38) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(37) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(16) I2=$iopadmap$a(39) I3=$iopadmap$b(15) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(31) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(22) I2=$iopadmap$a(33) I3=$iopadmap$b(21) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(34) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(19) I2=$iopadmap$a(36) I3=$iopadmap$b(18) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(33) I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_21_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_23_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_24_I0 I1=out_LUT4_O_24_I1 I2=out_LUT4_O_25_I2_LUT4_O_I2_LUT4_I0_O I3=out_LUT4_O_24_I3 O=$iopadmap$out(16)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111011001101111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I0_LUT4_O_I1 I2=out_LUT4_O_24_I0_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_I3_O_LUT4_I2_O O=out_LUT4_O_24_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=out_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3 I1=out_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3 O=out_LUT4_O_24_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3 O=out_LUT4_O_24_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(40) I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(39) I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(16) I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=$iopadmap$b(38) I3=$iopadmap$a(17) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(15) I3=$iopadmap$b(39) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(14) I3=$iopadmap$b(40) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(28) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(25) I2=$iopadmap$a(30) I3=$iopadmap$b(24) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(30) I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(27) I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(22) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(31) I2=$iopadmap$a(24) I3=$iopadmap$b(30) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(25) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(28) I2=$iopadmap$a(27) I3=$iopadmap$b(27) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(24) I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(19) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(34) I2=$iopadmap$a(21) I3=$iopadmap$b(33) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(18) I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(21) I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(23) I2=$iopadmap$a(22) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(14) I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(30) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(22) I2=$iopadmap$a(32) I3=$iopadmap$b(21) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(33) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(19) I2=$iopadmap$a(35) I3=$iopadmap$b(18) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(32) I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(36) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(16) I2=$iopadmap$a(38) I3=$iopadmap$b(15) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(35) I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(17) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_22_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(40) I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(39) I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(15) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(16) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(37) I2=$iopadmap$a(18) I3=$iopadmap$b(36) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(14) I3=$iopadmap$b(39) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(13) I3=$iopadmap$b(40) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(27) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(25) I2=$iopadmap$a(29) I3=$iopadmap$b(24) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(29) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(26) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(21) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(31) I2=$iopadmap$a(23) I3=$iopadmap$b(30) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(24) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(28) I2=$iopadmap$a(26) I3=$iopadmap$b(27) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(23) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(18) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(34) I2=$iopadmap$a(20) I3=$iopadmap$b(33) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(17) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(20) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(22) I2=$iopadmap$a(21) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(29) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(22) I2=$iopadmap$a(31) I3=$iopadmap$b(21) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(32) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(19) I2=$iopadmap$a(34) I3=$iopadmap$b(18) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(31) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(35) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(16) I2=$iopadmap$a(37) I3=$iopadmap$b(15) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$a(37) I3=$iopadmap$b(14) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(34) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(23) I3=$iopadmap$a(32) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(20) I3=$iopadmap$a(35) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(34) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(17) I3=$iopadmap$a(38) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(15) I3=$iopadmap$a(40) O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(37) I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(15) I2=$iopadmap$a(38) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(14) I2=$iopadmap$a(40) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I2_LUT4_O_I3 I3=out_LUT4_O_24_I3 O=out_LUT4_O_22_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I3_LUT4_O_I1 I2=out_LUT4_O_24_I3_LUT4_O_I2 I3=out_LUT4_O_24_I3_LUT4_O_I3 O=out_LUT4_O_24_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00011110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_24_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_24_I3_LUT4_O_I2 I3=out_LUT4_O_24_I3_LUT4_O_I1 O=out_LUT4_O_23_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_24_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_24_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_25_I2 I3=out_LUT4_O_25_I3 O=$iopadmap$out(15)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I0 I1=out_LUT4_O_25_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3 O=out_LUT4_O_25_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001111011100001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I2_LUT4_O_I3 I2=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I2 I1=out_LUT4_O_25_I2_LUT4_O_I0 I2=out_LUT4_O_25_I2_LUT4_O_I1 I3=out_LUT4_O_25_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I2_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I2_LUT4_O_I1 I2=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100000000
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=$iopadmap$a(0) I3=$iopadmap$b(12) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I1=$iopadmap$b(11) I2=$iopadmap$a(0) I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$a(2) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(1) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(10) I2=$iopadmap$a(3) I3=$iopadmap$b(9) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(13) I2=$iopadmap$a(1) I3=$iopadmap$b(12) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(2) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(10) I2=$iopadmap$a(4) I3=$iopadmap$b(9) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(1) I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(4) I3=$iopadmap$b(8) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(7) I2=$iopadmap$a(6) I3=$iopadmap$b(6) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(6) I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(4) I2=$iopadmap$a(8) I3=$iopadmap$b(3) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$a(3) I2=$iopadmap$b(8) I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(7) I2=$iopadmap$a(5) I3=$iopadmap$b(6) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(13) I2=$iopadmap$b(12) I3=out_LUT4_O_38_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000110001110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(10) I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(8) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(11) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(1) I2=$iopadmap$a(13) I3=$iopadmap$b(0) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(11) I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(9) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(2) I3=$iopadmap$a(12) O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_I3_O_LUT4_I2_O I1=out_LUT4_O_26_I2_LUT4_O_I3 I2=out_LUT4_O_26_I2_LUT4_O_I2 I3=out_LUT4_O_25_I3_LUT4_O_I3 O=out_LUT4_O_25_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_25_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I1 I2=out_LUT4_O_26_I2 I3=out_LUT4_O_28_I2_LUT4_I3_O_LUT4_I2_O O=$iopadmap$out(14)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=out_LUT4_O_27_I1 I1=out_LUT4_O_27_I2 I2=out_LUT4_O_27_I3 I3=out_LUT4_O_26_I1_LUT4_O_I3 O=out_LUT4_O_26_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=out_LUT4_O_27_I2_LUT4_O_I3 I1=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=out_LUT4_O_27_I2_LUT4_O_I1 I3=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_25_I3_LUT4_O_I3 I3=out_LUT4_O_26_I2 O=out_LUT4_O_24_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_26_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3 O=out_LUT4_O_26_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(40) I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(39) I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(14) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(15) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(37) I2=$iopadmap$a(17) I3=$iopadmap$b(36) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(13) I3=$iopadmap$b(39) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(12) I3=$iopadmap$b(40) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(26) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(25) I2=$iopadmap$a(28) I3=$iopadmap$b(24) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(28) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(25) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(20) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(31) I2=$iopadmap$a(22) I3=$iopadmap$b(30) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(23) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(28) I2=$iopadmap$a(25) I3=$iopadmap$b(27) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(22) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(17) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(34) I2=$iopadmap$a(19) I3=$iopadmap$b(33) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(16) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(19) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(21) I2=$iopadmap$a(20) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(28) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(22) I2=$iopadmap$a(30) I3=$iopadmap$b(21) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(31) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(19) I2=$iopadmap$a(33) I3=$iopadmap$b(18) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(30) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(34) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(16) I2=$iopadmap$a(36) I3=$iopadmap$b(15) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(33) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(36) I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(12) I2=$iopadmap$a(37) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(40) O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_23_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(40) I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(39) I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(13) I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(14) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(37) I2=$iopadmap$a(16) I3=$iopadmap$b(36) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(12) I3=$iopadmap$b(39) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(11) I3=$iopadmap$b(40) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(25) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(25) I2=$iopadmap$a(27) I3=$iopadmap$b(24) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(27) I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(24) I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(19) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(31) I2=$iopadmap$a(21) I3=$iopadmap$b(30) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(22) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(28) I2=$iopadmap$a(24) I3=$iopadmap$b(27) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(21) I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(16) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(34) I2=$iopadmap$a(18) I3=$iopadmap$b(33) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(15) I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(18) I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(20) I2=$iopadmap$a(19) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(27) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(22) I2=$iopadmap$a(29) I3=$iopadmap$b(21) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(30) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(19) I2=$iopadmap$a(32) I3=$iopadmap$b(18) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(29) I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(33) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(16) I2=$iopadmap$a(35) I3=$iopadmap$b(15) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(35) I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(32) I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(14) I3=$iopadmap$a(39) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(13) I3=$iopadmap$a(40) O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_27_I0 I1=out_LUT4_O_27_I1 I2=out_LUT4_O_27_I2 I3=out_LUT4_O_27_I3 O=$iopadmap$out(13)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111011101011
+.subckt LUT4 I0=out_LUT4_O_28_I3 I1=out_LUT4_O_28_I2 I2=out_LUT4_O_27_I0_LUT4_O_I2 I3=out_LUT4_O_27_I0_LUT4_O_I3 O=out_LUT4_O_27_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I0_LUT4_O_I3_LUT4_O_I3 I2=out_LUT4_O_27_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I0_LUT4_O_I2 O=out_LUT4_O_27_I0_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_28_I2_LUT4_O_I3 I3=out_LUT4_O_28_I2_LUT4_O_I2 O=out_LUT4_O_27_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_27_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_27_I1 I1=out_LUT4_O_27_I2 I2=out_LUT4_O_27_I3 I3=out_LUT4_O_26_I1_LUT4_O_I3 O=out_LUT4_O_25_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=out_LUT4_O_27_I1_LUT4_O_I0 I1=out_LUT4_O_27_I1_LUT4_O_I1 I2=out_LUT4_O_27_I1_LUT4_O_I2 I3=out_LUT4_O_27_I1_LUT4_O_I3 O=out_LUT4_O_27_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010100011111110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=out_LUT4_O_30_I1_LUT4_O_I3 I1=out_LUT4_O_30_I1_LUT4_O_I2 I2=out_LUT4_O_30_I1_LUT4_O_I1 I3=out_LUT4_O_29_I2_LUT4_O_I3 O=out_LUT4_O_27_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I0 I2=out_LUT4_O_30_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2 I2=out_LUT4_O_27_I3_LUT4_O_I3 I3=out_LUT4_O_27_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I2_LUT4_O_I1 I2=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_27_I2_LUT4_O_I3 O=out_LUT4_O_27_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_27_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_27_I1_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_27_I3_LUT4_O_I3 O=out_LUT4_O_27_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_27_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3 O=out_LUT4_O_27_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(10) I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(10) I2=$iopadmap$a(0) I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(9) I3=$iopadmap$a(1) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(8) I2=$iopadmap$a(0) I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(7) I2=$iopadmap$a(2) I3=$iopadmap$b(6) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$a(2) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$a(1) I3=$iopadmap$b(8) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(3) I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(4) I2=$iopadmap$a(5) I3=$iopadmap$b(3) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(10) I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(7) I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(5) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(4) I2=$iopadmap$a(7) I3=$iopadmap$b(3) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(8) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(1) I2=$iopadmap$a(10) I3=$iopadmap$b(0) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$a(3) I3=$iopadmap$b(8) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(5) I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(2) I2=$iopadmap$b(8) I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(6) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(9) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(1) I2=$iopadmap$a(11) I3=$iopadmap$b(0) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(8) I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_26_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$a(1) I2=$iopadmap$b(8) I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(7) I2=$iopadmap$a(3) I3=$iopadmap$b(6) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(2) I3=$iopadmap$b(8) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(7) I2=$iopadmap$a(4) I3=$iopadmap$b(6) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(4) I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(4) I2=$iopadmap$a(6) I3=$iopadmap$b(3) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(11) I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(10) I2=$iopadmap$a(2) I3=$iopadmap$b(9) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(12) I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I0 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=$iopadmap$b(11) I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_25_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(7) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(10) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(1) I2=$iopadmap$a(12) I3=$iopadmap$b(0) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(9) I3=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I1 I2=out_LUT4_O_28_I2 I3=out_LUT4_O_28_I3 O=$iopadmap$out(12)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=out_LUT4_O_27_I1_LUT4_O_I1 I1=out_LUT4_O_27_I1_LUT4_O_I2 I2=out_LUT4_O_27_I1_LUT4_O_I0 I3=out_LUT4_O_27_I1_LUT4_O_I3 O=out_LUT4_O_28_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_27_I0_LUT4_O_I3 I3=out_LUT4_O_28_I2 O=out_LUT4_O_28_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=out_LUT4_O_28_I3_LUT4_O_I3 I1=out_LUT4_O_28_I3_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_I3_O I3=out_LUT4_O_27_I0_LUT4_O_I2_LUT4_I3_O O=out_LUT4_O_28_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_28_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3 O=out_LUT4_O_28_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(34) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(13) I2=$iopadmap$a(36) I3=$iopadmap$b(12) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(37) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(10) I2=$iopadmap$a(39) I3=$iopadmap$b(9) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(36) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$a(38) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$b(8) I1=$iopadmap$a(39) I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(26) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(22) I2=$iopadmap$a(28) I3=$iopadmap$b(21) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(29) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(19) I2=$iopadmap$a(31) I3=$iopadmap$b(18) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(28) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(32) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(16) I2=$iopadmap$a(34) I3=$iopadmap$b(15) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(34) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(31) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(24) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(25) I2=$iopadmap$a(26) I3=$iopadmap$b(24) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(26) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(23) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(18) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(31) I2=$iopadmap$a(20) I3=$iopadmap$b(30) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(21) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(28) I2=$iopadmap$a(23) I3=$iopadmap$b(27) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(20) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(15) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(34) I2=$iopadmap$a(17) I3=$iopadmap$b(33) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(14) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(17) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(19) I2=$iopadmap$a(18) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(40) I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(39) I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(12) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(13) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(37) I2=$iopadmap$a(15) I3=$iopadmap$b(36) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(11) I3=$iopadmap$b(39) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(10) I3=$iopadmap$b(40) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(14) I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$a(40) I3=$iopadmap$b(11) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(14) I2=$iopadmap$a(38) I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(13) I2=$iopadmap$a(40) I3=$iopadmap$b(12) O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(40) I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(39) I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(11) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(12) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(37) I2=$iopadmap$a(14) I3=$iopadmap$b(36) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(10) I3=$iopadmap$b(39) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(9) I3=$iopadmap$b(40) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(23) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(25) I2=$iopadmap$a(25) I3=$iopadmap$b(24) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(25) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(22) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(17) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(31) I2=$iopadmap$a(19) I3=$iopadmap$b(30) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(20) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(28) I2=$iopadmap$a(22) I3=$iopadmap$b(27) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(19) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(14) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(34) I2=$iopadmap$a(16) I3=$iopadmap$b(33) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(13) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(16) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(18) I2=$iopadmap$a(17) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(25) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(22) I2=$iopadmap$a(27) I3=$iopadmap$b(21) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(28) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(19) I2=$iopadmap$a(30) I3=$iopadmap$b(18) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(27) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(31) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(16) I2=$iopadmap$a(33) I3=$iopadmap$b(15) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(33) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(30) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(33) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(13) I2=$iopadmap$a(35) I3=$iopadmap$b(12) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(36) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(10) I2=$iopadmap$a(38) I3=$iopadmap$b(9) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(35) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$a(40) I2=$iopadmap$b(11) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(10) I3=$iopadmap$a(39) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(14) I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(13) I3=$iopadmap$a(38) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(12) I3=$iopadmap$a(39) O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_26_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_28_I3_LUT4_O_I2 I3=out_LUT4_O_28_I3_LUT4_O_I3 O=out_LUT4_O_28_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_29_I3_LUT4_O_I2 O=out_LUT4_O_28_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_I3_O_LUT4_I2_O I1=out_LUT4_O_30_I3_LUT4_O_I2 I2=out_LUT4_O_30_I3_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_I3_O O=out_LUT4_O_28_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100111100000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_29_I2 I3=out_LUT4_O_29_I3 O=$iopadmap$out(11)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=out_LUT4_O_30_I1_LUT4_O_I3 I1=out_LUT4_O_30_I1_LUT4_O_I1 I2=out_LUT4_O_30_I1_LUT4_O_I2 I3=out_LUT4_O_29_I2_LUT4_O_I3 O=out_LUT4_O_29_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111001110001
+.subckt LUT4 I0=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I2=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_29_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(9) I2=$iopadmap$a(0) I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_30_I3 I1=out_LUT4_O_30_I2 I2=out_LUT4_O_29_I3_LUT4_O_I2 I3=out_LUT4_O_29_I3_LUT4_O_I3 O=out_LUT4_O_29_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_30_I2_LUT4_O_I3 I3=out_LUT4_O_30_I2_LUT4_O_I2 O=out_LUT4_O_29_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_29_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_29_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I0 I1=out_LUT4_O_2_I0_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I3 O=out_LUT4_O_2_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000110001110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3 I3=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I2 O=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(14) I2=$iopadmap$a(7) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(13) I2=$iopadmap$a(9) I3=$iopadmap$b(12) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(17) I2=$iopadmap$a(4) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(16) I2=$iopadmap$a(6) I3=$iopadmap$b(15) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(5) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(16) I2=$iopadmap$a(7) I3=$iopadmap$b(15) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I1=$iopadmap$b(20) I2=$iopadmap$a(2) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(23) I3=$iopadmap$a(0) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(3) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(19) I2=$iopadmap$a(5) I3=$iopadmap$b(18) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(8) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(5) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(6) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(16) I2=$iopadmap$a(8) I3=$iopadmap$b(15) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(11) I2=$iopadmap$a(10) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(10) I2=$iopadmap$a(12) I3=$iopadmap$b(9) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(8) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(13) I2=$iopadmap$a(10) I3=$iopadmap$b(12) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(11) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(10) I2=$iopadmap$a(13) I3=$iopadmap$b(9) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$a(13) I2=$iopadmap$b(8) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(7) I2=$iopadmap$a(15) I3=$iopadmap$b(6) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(16) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(4) I2=$iopadmap$a(18) I3=$iopadmap$b(3) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(14) I3=$iopadmap$b(8) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(7) I2=$iopadmap$a(16) I3=$iopadmap$b(6) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(11) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(9) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(13) I2=$iopadmap$a(11) I3=$iopadmap$b(12) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(12) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(10) I2=$iopadmap$a(14) I3=$iopadmap$b(9) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(3) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(1) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(22) I2=$iopadmap$a(3) I3=$iopadmap$b(21) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(4) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(19) I2=$iopadmap$a(6) I3=$iopadmap$b(18) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(9) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(6) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(7) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(16) I2=$iopadmap$a(9) I3=$iopadmap$b(15) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(24) I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(23) I2=$iopadmap$a(0) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(22) I2=$iopadmap$a(2) I3=$iopadmap$b(21) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(22) I2=$iopadmap$a(2) I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(24) I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011100000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(25) I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(1) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(24) I3=$iopadmap$a(1) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(24) I2=$iopadmap$a(0) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(19) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(17) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(20) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(1) I2=$iopadmap$a(22) I3=$iopadmap$b(0) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(20) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(18) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(21) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(1) I2=$iopadmap$a(23) I3=$iopadmap$b(0) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(21) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(19) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(4) I2=$iopadmap$a(21) I3=$iopadmap$b(3) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(22) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(1) I2=$iopadmap$a(24) I3=$iopadmap$b(0) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(16) I2=$iopadmap$b(8) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(19) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(17) I3=$iopadmap$b(8) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(7) I2=$iopadmap$a(19) I3=$iopadmap$b(6) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(22) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(20) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(4) I2=$iopadmap$a(22) I3=$iopadmap$b(3) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(23) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(1) I2=$iopadmap$a(25) I3=$iopadmap$b(0) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(14) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(12) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(13) I2=$iopadmap$a(14) I3=$iopadmap$b(12) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(15) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(10) I2=$iopadmap$a(17) I3=$iopadmap$b(9) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$a(17) I2=$iopadmap$b(8) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(18) I3=$iopadmap$b(8) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(7) I2=$iopadmap$a(20) I3=$iopadmap$b(6) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(20) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(23) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(21) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(4) I2=$iopadmap$a(23) I3=$iopadmap$b(3) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(24) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(1) I2=$iopadmap$a(26) I3=$iopadmap$b(0) O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1 O=out_LUT4_O_14_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(4) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(2) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(22) I2=$iopadmap$a(4) I3=$iopadmap$b(21) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(5) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(19) I2=$iopadmap$a(7) I3=$iopadmap$b(18) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(10) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(7) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(8) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(16) I2=$iopadmap$a(10) I3=$iopadmap$b(15) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(12) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(10) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(13) I2=$iopadmap$a(12) I3=$iopadmap$b(12) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(13) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(10) I2=$iopadmap$a(15) I3=$iopadmap$b(9) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$a(14) I2=$iopadmap$b(8) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(15) I3=$iopadmap$b(8) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(7) I2=$iopadmap$a(17) I3=$iopadmap$b(6) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(17) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(4) I2=$iopadmap$a(19) I3=$iopadmap$b(3) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(25) I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(2) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(25) I2=$iopadmap$a(0) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(0) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(25) I2=$iopadmap$a(2) I3=$iopadmap$b(24) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(6) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(4) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(22) I2=$iopadmap$a(6) I3=$iopadmap$b(21) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(7) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(19) I2=$iopadmap$a(9) I3=$iopadmap$b(18) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(12) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(9) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(10) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(16) I2=$iopadmap$a(12) I3=$iopadmap$b(15) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(13) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(13) I2=$iopadmap$a(15) I3=$iopadmap$b(12) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(16) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(10) I2=$iopadmap$a(18) I3=$iopadmap$b(9) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(15) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(19) I3=$iopadmap$b(8) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(7) I2=$iopadmap$a(21) I3=$iopadmap$b(6) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(21) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(18) I2=$iopadmap$b(8) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(22) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(4) I2=$iopadmap$a(24) I3=$iopadmap$b(3) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(25) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(1) I2=$iopadmap$a(27) I3=$iopadmap$b(0) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(24) I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_15_I2_LUT4_O_I3 I2=out_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=out_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_14_I1_LUT4_O_I3 I1=out_LUT4_O_2_I1 I2=out_LUT4_O_14_I1_LUT4_O_I1 I3=out_LUT4_O_2_I1_LUT4_I1_I3 O=out_LUT4_O_1_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_1_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_2_I1_LUT4_O_I3_LUT4_I2_O O=out_LUT4_O_2_I1_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I3 O=out_LUT4_O_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(5) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(3) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(22) I2=$iopadmap$a(5) I3=$iopadmap$b(21) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(6) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(19) I2=$iopadmap$a(8) I3=$iopadmap$b(18) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(11) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(8) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(9) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(16) I2=$iopadmap$a(11) I3=$iopadmap$b(15) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(13) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(11) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(13) I2=$iopadmap$a(13) I3=$iopadmap$b(12) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(14) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(10) I2=$iopadmap$a(16) I3=$iopadmap$b(9) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(15) I2=$iopadmap$b(8) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(16) I3=$iopadmap$b(8) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(7) I2=$iopadmap$a(18) I3=$iopadmap$b(6) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(18) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(4) I2=$iopadmap$a(20) I3=$iopadmap$b(3) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(27) I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(1) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(25) I2=$iopadmap$a(3) I3=$iopadmap$b(24) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(3) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(0) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(25) I2=$iopadmap$a(2) I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(7) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(5) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(22) I2=$iopadmap$a(7) I3=$iopadmap$b(21) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(8) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(19) I2=$iopadmap$a(10) I3=$iopadmap$b(18) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(10) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(11) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(16) I2=$iopadmap$a(13) I3=$iopadmap$b(15) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(13) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(14) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(13) I2=$iopadmap$a(16) I3=$iopadmap$b(12) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(17) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(10) I2=$iopadmap$a(19) I3=$iopadmap$b(9) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(16) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(20) I3=$iopadmap$b(8) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(7) I2=$iopadmap$a(22) I3=$iopadmap$b(6) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(22) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(19) I2=$iopadmap$b(8) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(23) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(4) I2=$iopadmap$a(25) I3=$iopadmap$b(3) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(26) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(1) I2=$iopadmap$a(28) I3=$iopadmap$b(0) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(25) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$a(0) I3=$iopadmap$b(27) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101110111011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(28) I2=$iopadmap$a(1) I3=$iopadmap$b(27) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(1) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(2) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(25) I2=$iopadmap$a(4) I3=$iopadmap$b(24) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(4) I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I1_LUT4_O_I3 I3=out_LUT4_O_2_I1_LUT4_O_I2 O=out_LUT4_O_2_I1_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I2_LUT4_O_I1 I2=out_LUT4_O_2_I2_LUT4_O_I2 I3=out_LUT4_O_17_I2_LUT4_I3_O_LUT4_I2_O O=out_LUT4_O_2_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_14_I0_LUT4_O_I3 I3=out_LUT4_O_2_I3 O=out_LUT4_O_2_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3 O=out_LUT4_O_2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(40) I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(39) I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(28) I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(29) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(37) I2=$iopadmap$a(31) I3=$iopadmap$b(36) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(27) I3=$iopadmap$b(39) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(26) I3=$iopadmap$b(40) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(35) I3=$iopadmap$a(33) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(35) I2=$iopadmap$a(32) I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(34) I2=$iopadmap$a(34) I3=$iopadmap$b(33) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(35) I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(37) I2=$iopadmap$a(36) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(35) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(31) I2=$iopadmap$a(37) I3=$iopadmap$b(30) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(40) I1=$iopadmap$b(27) I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(29) I2=$iopadmap$a(37) I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(28) I2=$iopadmap$a(39) I3=$iopadmap$b(27) O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(27) I2=$iopadmap$a(38) I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(40) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(39) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(27) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(28) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(37) I2=$iopadmap$a(30) I3=$iopadmap$b(36) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(26) I3=$iopadmap$b(39) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(25) I3=$iopadmap$b(40) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(39) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(25) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(26) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(37) I2=$iopadmap$a(28) I3=$iopadmap$b(36) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(24) I3=$iopadmap$b(39) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(39) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(26) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(27) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(37) I2=$iopadmap$a(29) I3=$iopadmap$b(36) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(25) I3=$iopadmap$b(39) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(33) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(31) I2=$iopadmap$a(35) I3=$iopadmap$b(30) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(36) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(28) I2=$iopadmap$a(38) I3=$iopadmap$b(27) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(35) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(30) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(34) I2=$iopadmap$a(32) I3=$iopadmap$b(33) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(29) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(32) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(34) I2=$iopadmap$a(33) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(26) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$a(40) I3=$iopadmap$b(26) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(35) I3=$iopadmap$a(32) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(31) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(34) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(36) I2=$iopadmap$a(35) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1010101100001110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(26) I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(40) I3=$iopadmap$b(24) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(25) I3=$iopadmap$a(40) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(34) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(31) I2=$iopadmap$a(36) I3=$iopadmap$b(30) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(29) I3=$iopadmap$a(37) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(36) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$a(38) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(31) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(34) I2=$iopadmap$a(33) I3=$iopadmap$b(33) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(30) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(33) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(35) I2=$iopadmap$a(34) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(26) I2=$iopadmap$a(40) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(25) I3=$iopadmap$a(39) O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I1 I2=out_LUT4_O_3_I2 I3=out_LUT4_O_3_I3 O=$iopadmap$out(25)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10111110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I1 I2=out_LUT4_O_30_I2 I3=out_LUT4_O_30_I3 O=$iopadmap$out(10)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I1_LUT4_O_I1 I2=out_LUT4_O_30_I1_LUT4_O_I2 I3=out_LUT4_O_30_I1_LUT4_O_I3 O=out_LUT4_O_30_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=out_LUT4_O_31_I1_LUT4_O_I3 O=out_LUT4_O_30_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_30_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I0 O=out_LUT4_O_30_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=out_LUT4_O_30_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_29_I3_LUT4_O_I3 I3=out_LUT4_O_30_I2 O=out_LUT4_O_30_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_30_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3 O=out_LUT4_O_30_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010001
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(36) I2=$iopadmap$b(8) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$a(38) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(37) I3=$iopadmap$b(8) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(7) I2=$iopadmap$a(39) I3=$iopadmap$b(6) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(32) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(13) I2=$iopadmap$a(34) I3=$iopadmap$b(12) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(35) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(10) I2=$iopadmap$a(37) I3=$iopadmap$b(9) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(34) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(24) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(22) I2=$iopadmap$a(26) I3=$iopadmap$b(21) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(27) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(19) I2=$iopadmap$a(29) I3=$iopadmap$b(18) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(26) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(30) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(16) I2=$iopadmap$a(32) I3=$iopadmap$b(15) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(32) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(29) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(22) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(25) I2=$iopadmap$a(24) I3=$iopadmap$b(24) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(24) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(21) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(16) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(31) I2=$iopadmap$a(18) I3=$iopadmap$b(30) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(19) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(28) I2=$iopadmap$a(21) I3=$iopadmap$b(27) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(18) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(13) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(34) I2=$iopadmap$a(15) I3=$iopadmap$b(33) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(12) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(15) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(17) I2=$iopadmap$a(16) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(40) I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(39) I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(10) I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(11) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(37) I2=$iopadmap$a(13) I3=$iopadmap$b(36) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(9) I3=$iopadmap$b(39) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(8) I3=$iopadmap$b(40) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(11) I2=$iopadmap$a(40) I3=$iopadmap$b(10) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(36) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(13) I2=$iopadmap$a(38) I3=$iopadmap$b(12) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(40) I3=$iopadmap$b(9) O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_26_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(36) I3=$iopadmap$b(8) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(7) I2=$iopadmap$a(38) I3=$iopadmap$b(6) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000001110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(35) I2=$iopadmap$b(8) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(31) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(13) I2=$iopadmap$a(33) I3=$iopadmap$b(12) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(34) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(10) I2=$iopadmap$a(36) I3=$iopadmap$b(9) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(33) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(23) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(22) I2=$iopadmap$a(25) I3=$iopadmap$b(21) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(26) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(19) I2=$iopadmap$a(28) I3=$iopadmap$b(18) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(25) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(29) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(16) I2=$iopadmap$a(31) I3=$iopadmap$b(15) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(31) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(28) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(21) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(25) I2=$iopadmap$a(23) I3=$iopadmap$b(24) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(23) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(20) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(15) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(31) I2=$iopadmap$a(17) I3=$iopadmap$b(30) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(18) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(28) I2=$iopadmap$a(20) I3=$iopadmap$b(27) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(17) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(12) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(34) I2=$iopadmap$a(14) I3=$iopadmap$b(33) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(11) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(14) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(16) I2=$iopadmap$a(15) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(40) I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(39) I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(9) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(10) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(37) I2=$iopadmap$a(12) I3=$iopadmap$b(36) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(8) I3=$iopadmap$b(39) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(7) I3=$iopadmap$b(40) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(39) I2=$iopadmap$b(8) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(35) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(13) I2=$iopadmap$a(37) I3=$iopadmap$b(12) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(40) I1=$iopadmap$b(9) I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(11) I3=$iopadmap$a(38) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(37) I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(9) I2=$iopadmap$a(38) I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(8) I3=$iopadmap$a(40) O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I3_LUT4_O_I1 I2=out_LUT4_O_30_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_I3_O_LUT4_I2_O O=out_LUT4_O_30_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=out_LUT4_O_31_I3_LUT4_O_I3_LUT4_O_I3 I1=out_LUT4_O_31_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3 O=out_LUT4_O_30_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1 I2=out_LUT4_O_31_I2 I3=out_LUT4_O_31_I3 O=$iopadmap$out(9)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101011
+.subckt LUT4 I0=out_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I1=out_LUT4_O_31_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3 O=out_LUT4_O_31_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_33_I2_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=out_LUT4_O_31_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_31_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3 O=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=out_LUT4_O_31_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O I1=out_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=out_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_35_I3_LUT4_I1_I3 O=out_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I3 I3=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I2 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0 I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1 I2=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I2 I3=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(7) I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(1) I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(7) I2=$iopadmap$a(0) I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(6) I3=$iopadmap$a(1) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(7) I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_29_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(4) I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(2) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(2) I3=$iopadmap$a(5) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(9) I3=$iopadmap$a(0) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(8) I3=$iopadmap$a(0) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(2) I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(4) I2=$iopadmap$a(4) I3=$iopadmap$b(3) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(2) I2=$iopadmap$a(5) I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(1) I2=$iopadmap$a(7) I3=$iopadmap$b(0) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(3) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(2) I3=$iopadmap$a(6) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_27_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(2) I2=$iopadmap$a(6) I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(1) I2=$iopadmap$a(8) I3=$iopadmap$b(0) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_27_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(4) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(7) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(1) I2=$iopadmap$a(9) I3=$iopadmap$b(0) O=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_31_I2 I3=out_LUT4_O_31_I1 O=out_LUT4_O_30_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_33_I1 I2=out_LUT4_O_31_I2_LUT4_O_I2 I3=out_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O O=out_LUT4_O_31_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_31_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_I1_O O=out_LUT4_O_31_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_I3_O_LUT4_I2_O I1=out_LUT4_O_32_I2_LUT4_O_I3 I2=out_LUT4_O_32_I2_LUT4_O_I2 I3=out_LUT4_O_31_I3_LUT4_O_I3 O=out_LUT4_O_31_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_31_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_31_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_31_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_31_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_31_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I1 I2=out_LUT4_O_32_I2 I3=out_LUT4_O_34_I2_LUT4_I3_O_LUT4_I2_O O=$iopadmap$out(8)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=out_LUT4_O_33_I2 I1=out_LUT4_O_33_I1 I2=out_LUT4_O_31_I1_LUT4_O_I2_LUT4_O_I1_LUT4_I1_O I3=out_LUT4_O_31_I1_LUT4_O_I1 O=out_LUT4_O_32_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100101110110100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_31_I3_LUT4_O_I3 I3=out_LUT4_O_32_I2 O=out_LUT4_O_30_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_32_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3 O=out_LUT4_O_32_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(35) I3=$iopadmap$b(8) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(7) I2=$iopadmap$a(37) I3=$iopadmap$b(6) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(37) I3=$iopadmap$b(5) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(4) I3=$iopadmap$a(38) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(3) I3=$iopadmap$a(39) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(34) I2=$iopadmap$b(8) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(30) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(13) I2=$iopadmap$a(32) I3=$iopadmap$b(12) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(33) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(10) I2=$iopadmap$a(35) I3=$iopadmap$b(9) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(32) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(22) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(22) I2=$iopadmap$a(24) I3=$iopadmap$b(21) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(25) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(19) I2=$iopadmap$a(27) I3=$iopadmap$b(18) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(24) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(28) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(16) I2=$iopadmap$a(30) I3=$iopadmap$b(15) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(30) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(27) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(20) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(25) I2=$iopadmap$a(22) I3=$iopadmap$b(24) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(22) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(19) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(14) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(31) I2=$iopadmap$a(16) I3=$iopadmap$b(30) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(17) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(28) I2=$iopadmap$a(19) I3=$iopadmap$b(27) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(16) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(11) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(34) I2=$iopadmap$a(13) I3=$iopadmap$b(33) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(10) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(13) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(15) I2=$iopadmap$a(14) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(40) I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(39) I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(8) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(9) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(37) I2=$iopadmap$a(11) I3=$iopadmap$b(36) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(7) I3=$iopadmap$b(39) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(6) I3=$iopadmap$b(40) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(8) I2=$iopadmap$a(40) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(7) I3=$iopadmap$a(39) O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(40) I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(39) I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(7) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(8) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(37) I2=$iopadmap$a(10) I3=$iopadmap$b(36) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(6) I3=$iopadmap$b(39) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(5) I3=$iopadmap$b(40) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(19) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(25) I2=$iopadmap$a(21) I3=$iopadmap$b(24) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(21) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(18) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(13) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(31) I2=$iopadmap$a(15) I3=$iopadmap$b(30) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(16) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(28) I2=$iopadmap$a(18) I3=$iopadmap$b(27) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(15) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(10) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(34) I2=$iopadmap$a(12) I3=$iopadmap$b(33) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(9) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(12) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(14) I2=$iopadmap$a(13) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(21) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(22) I2=$iopadmap$a(23) I3=$iopadmap$b(21) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(24) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(19) I2=$iopadmap$a(26) I3=$iopadmap$b(18) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(23) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(27) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(16) I2=$iopadmap$a(29) I3=$iopadmap$b(15) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(29) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(26) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(29) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(13) I2=$iopadmap$a(31) I3=$iopadmap$b(12) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(32) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(10) I2=$iopadmap$a(34) I3=$iopadmap$b(9) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(31) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(34) I3=$iopadmap$b(8) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(7) I2=$iopadmap$a(36) I3=$iopadmap$b(6) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(33) I2=$iopadmap$b(8) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(36) I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(4) I2=$iopadmap$a(38) I3=$iopadmap$b(3) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(3) I2=$iopadmap$a(37) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$b(8) I1=$iopadmap$a(39) I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(40) I3=$iopadmap$b(6) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(7) I3=$iopadmap$a(40) O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_28_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_33_I1 I2=out_LUT4_O_33_I2 I3=out_LUT4_O_33_I3 O=$iopadmap$out(7)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I1 I2=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=out_LUT4_O_33_I1_LUT4_O_I3 O=out_LUT4_O_33_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_35_I3_LUT4_I1_I3 I3=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_33_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$a(1) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_33_I2_LUT4_O_I2 I3=out_LUT4_O_31_I2_LUT4_O_I2 O=out_LUT4_O_33_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_34_I3 I1=out_LUT4_O_34_I2 I2=out_LUT4_O_33_I3_LUT4_O_I2 I3=out_LUT4_O_33_I3_LUT4_O_I3 O=out_LUT4_O_33_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_33_I3_LUT4_O_I3_LUT4_O_I3 I2=out_LUT4_O_33_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_33_I3_LUT4_O_I2 O=out_LUT4_O_33_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_34_I2_LUT4_O_I3 I3=out_LUT4_O_34_I2_LUT4_O_I2 O=out_LUT4_O_33_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_33_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_33_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_33_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_33_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_33_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I1 I2=out_LUT4_O_34_I2 I3=out_LUT4_O_34_I3 O=$iopadmap$out(6)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I1=out_LUT4_O_35_I1 I2=out_LUT4_O_35_I3 I3=out_LUT4_O_33_I1_LUT4_O_I3 O=out_LUT4_O_34_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110101100010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_33_I3_LUT4_O_I3 I3=out_LUT4_O_34_I2 O=out_LUT4_O_34_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=out_LUT4_O_34_I3_LUT4_O_I3 I1=out_LUT4_O_34_I3_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_I3_O I3=out_LUT4_O_33_I3_LUT4_O_I2_LUT4_I3_O O=out_LUT4_O_34_I2_LUT4_I3_O_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001001111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_34_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3 O=out_LUT4_O_34_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(33) I3=$iopadmap$b(8) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(7) I2=$iopadmap$a(35) I3=$iopadmap$b(6) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(35) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(4) I2=$iopadmap$a(37) I3=$iopadmap$b(3) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(32) I2=$iopadmap$b(8) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(28) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(13) I2=$iopadmap$a(30) I3=$iopadmap$b(12) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(31) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(10) I2=$iopadmap$a(33) I3=$iopadmap$b(9) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(30) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(20) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(22) I2=$iopadmap$a(22) I3=$iopadmap$b(21) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(23) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(19) I2=$iopadmap$a(25) I3=$iopadmap$b(18) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(22) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(26) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(16) I2=$iopadmap$a(28) I3=$iopadmap$b(15) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(28) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(25) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(18) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(25) I2=$iopadmap$a(20) I3=$iopadmap$b(24) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(20) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(17) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(12) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(31) I2=$iopadmap$a(14) I3=$iopadmap$b(30) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(15) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(28) I2=$iopadmap$a(17) I3=$iopadmap$b(27) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(14) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(9) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(34) I2=$iopadmap$a(11) I3=$iopadmap$b(33) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(8) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(11) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(13) I2=$iopadmap$a(12) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(40) I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(39) I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(6) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(7) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(37) I2=$iopadmap$a(9) I3=$iopadmap$b(36) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(5) I3=$iopadmap$b(39) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(4) I3=$iopadmap$b(40) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$a(38) I3=$iopadmap$b(8) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(6) I3=$iopadmap$a(40) O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(37) I2=$iopadmap$b(8) I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(6) I2=$iopadmap$a(38) I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(5) I2=$iopadmap$a(40) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(32) I3=$iopadmap$b(8) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(7) I2=$iopadmap$a(34) I3=$iopadmap$b(6) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(34) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(4) I2=$iopadmap$a(36) I3=$iopadmap$b(3) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(31) I2=$iopadmap$b(8) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(27) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(13) I2=$iopadmap$a(29) I3=$iopadmap$b(12) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(30) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(10) I2=$iopadmap$a(32) I3=$iopadmap$b(9) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(29) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(19) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(22) I2=$iopadmap$a(21) I3=$iopadmap$b(21) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(22) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(19) I2=$iopadmap$a(24) I3=$iopadmap$b(18) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(21) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(25) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(16) I2=$iopadmap$a(27) I3=$iopadmap$b(15) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(27) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(24) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(17) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(25) I2=$iopadmap$a(19) I3=$iopadmap$b(24) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(19) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(16) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(11) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(31) I2=$iopadmap$a(13) I3=$iopadmap$b(30) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(14) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(28) I2=$iopadmap$a(16) I3=$iopadmap$b(27) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(13) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(8) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(34) I2=$iopadmap$a(10) I3=$iopadmap$b(33) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(7) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(10) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(12) I2=$iopadmap$a(11) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(40) I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(39) I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(5) I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(6) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(37) I2=$iopadmap$a(8) I3=$iopadmap$b(36) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(4) I3=$iopadmap$b(39) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(3) I3=$iopadmap$b(40) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(40) O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I3=out_LUT4_O_30_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_34_I3_LUT4_O_I2 I3=out_LUT4_O_34_I3_LUT4_O_I3 O=out_LUT4_O_34_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I0_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_35_I0_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_35_I0_LUT4_O_I2 O=out_LUT4_O_34_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=out_LUT4_O_36_I3_LUT4_O_I2 I1=out_LUT4_O_38_I3_LUT4_O_I3 I2=out_LUT4_O_36_I3_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_I3_O O=out_LUT4_O_34_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=out_LUT4_O_35_I0 I1=out_LUT4_O_35_I1 I2=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=out_LUT4_O_35_I3 O=$iopadmap$out(5)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111011101011
+.subckt LUT4 I0=out_LUT4_O_36_I3 I1=out_LUT4_O_36_I2 I2=out_LUT4_O_35_I0_LUT4_O_I2 I3=out_LUT4_O_35_I0_LUT4_O_I3 O=out_LUT4_O_35_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_36_I2_LUT4_O_I3 I3=out_LUT4_O_36_I2_LUT4_O_I2 O=out_LUT4_O_35_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_35_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_35_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_35_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_35_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_35_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I1_LUT4_O_I1 I2=out_LUT4_O_35_I1_LUT4_O_I2 I3=out_LUT4_O_35_I1_LUT4_O_I3 O=out_LUT4_O_35_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=out_LUT4_O_37_I2_LUT4_O_I3 I1=out_LUT4_O_38_I1_LUT4_O_I3 I2=$iopadmap$b(2) I3=out_LUT4_O_38_I1_LUT4_O_I2 O=out_LUT4_O_35_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100000100000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_35_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(4) I2=$iopadmap$a(1) I3=$iopadmap$b(3) O=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(2) I2=$iopadmap$a(1) I3=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(1) I2=$iopadmap$a(3) I3=$iopadmap$b(0) O=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(2) O=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(2) I3=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3 O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(1) I2=$iopadmap$a(4) I3=$iopadmap$b(0) O=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_37_I2_LUT4_O_I3_LUT4_O_I2 I1=out_LUT4_O_37_I2_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$a(0) I3=$iopadmap$b(3) O=out_LUT4_O_35_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I3 I2=out_LUT4_O_33_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_I1_O I3=out_LUT4_O_35_I3_LUT4_I1_I3 O=out_LUT4_O_33_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 00010000
+.subckt LUT4 I0=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0 I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1 I2=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I2 I3=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I3 O=out_LUT4_O_35_I3_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(0) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(2) I3=$iopadmap$a(3) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(2) I2=$iopadmap$a(3) I3=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(1) I2=$iopadmap$a(5) I3=$iopadmap$b(0) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(1) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(4) I2=$iopadmap$a(3) I3=$iopadmap$b(3) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(4) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(1) I2=$iopadmap$a(6) I3=$iopadmap$b(0) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(0) I3=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(4) I2=$iopadmap$a(2) I3=$iopadmap$b(3) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$a(2) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(6) I3=$iopadmap$a(0) O=out_LUT4_O_35_I3_LUT4_I1_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_35_I1_LUT4_O_I3 I3=out_LUT4_O_35_I1_LUT4_O_I2 O=out_LUT4_O_35_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I1 I2=out_LUT4_O_36_I2 I3=out_LUT4_O_36_I3 O=$iopadmap$out(4)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I1_LUT4_O_I2 I2=out_LUT4_O_35_I1_LUT4_O_I3 I3=out_LUT4_O_35_I1_LUT4_O_I1 O=out_LUT4_O_36_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_35_I0_LUT4_O_I3 I3=out_LUT4_O_36_I2 O=out_LUT4_O_36_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_36_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3 O=out_LUT4_O_36_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(31) I3=$iopadmap$b(8) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(7) I2=$iopadmap$a(33) I3=$iopadmap$b(6) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(33) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(4) I2=$iopadmap$a(35) I3=$iopadmap$b(3) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(30) I2=$iopadmap$b(8) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(26) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(13) I2=$iopadmap$a(28) I3=$iopadmap$b(12) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(29) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(10) I2=$iopadmap$a(31) I3=$iopadmap$b(9) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(28) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(18) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(22) I2=$iopadmap$a(20) I3=$iopadmap$b(21) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(21) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(19) I2=$iopadmap$a(23) I3=$iopadmap$b(18) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(20) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(24) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(16) I2=$iopadmap$a(26) I3=$iopadmap$b(15) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(26) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(23) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(16) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(25) I2=$iopadmap$a(18) I3=$iopadmap$b(24) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(18) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(15) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(10) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(31) I2=$iopadmap$a(12) I3=$iopadmap$b(30) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(13) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(28) I2=$iopadmap$a(15) I3=$iopadmap$b(27) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(12) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(7) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(34) I2=$iopadmap$a(9) I3=$iopadmap$b(33) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(6) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(9) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(11) I2=$iopadmap$a(10) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(40) I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(39) I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(4) I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(5) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(37) I2=$iopadmap$a(7) I3=$iopadmap$b(36) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(3) I3=$iopadmap$b(39) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(2) I3=$iopadmap$b(40) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(5) I3=$iopadmap$a(39) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(4) I3=$iopadmap$a(40) O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_30_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011001000101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(30) I3=$iopadmap$b(8) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(7) I2=$iopadmap$a(32) I3=$iopadmap$b(6) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(32) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(4) I2=$iopadmap$a(34) I3=$iopadmap$b(3) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(29) I2=$iopadmap$b(8) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(28) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(10) I2=$iopadmap$a(30) I3=$iopadmap$b(9) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(27) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(25) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(13) I2=$iopadmap$a(27) I3=$iopadmap$b(12) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(17) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(22) I2=$iopadmap$a(19) I3=$iopadmap$b(21) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(20) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(19) I2=$iopadmap$a(22) I3=$iopadmap$b(18) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(19) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(23) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(16) I2=$iopadmap$a(25) I3=$iopadmap$b(15) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(25) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(22) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(15) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(25) I2=$iopadmap$a(17) I3=$iopadmap$b(24) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(17) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(14) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(9) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(31) I2=$iopadmap$a(11) I3=$iopadmap$b(30) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(12) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(28) I2=$iopadmap$a(14) I3=$iopadmap$b(27) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(11) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(6) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(34) I2=$iopadmap$a(8) I3=$iopadmap$b(33) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(5) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(8) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(10) I2=$iopadmap$a(9) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(40) I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(39) I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(3) I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(4) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(37) I2=$iopadmap$a(6) I3=$iopadmap$b(36) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(2) I3=$iopadmap$b(39) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(1) I3=$iopadmap$b(40) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$a(40) I3=$iopadmap$b(2) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(5) I3=$iopadmap$a(38) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(4) I2=$iopadmap$a(40) I3=$iopadmap$b(3) O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I3_LUT4_O_I1 I2=out_LUT4_O_36_I3_LUT4_O_I2 I3=out_LUT4_O_38_I3_LUT4_O_I3 O=out_LUT4_O_36_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I3_LUT4_O_I2 I3=out_LUT4_O_36_I3_LUT4_O_I2 O=out_LUT4_O_36_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_37_I2 I3=out_LUT4_O_37_I3 O=$iopadmap$out(3)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110
+.subckt LUT4 I0=out_LUT4_O_38_I1_LUT4_O_I2 I1=out_LUT4_O_38_I1_LUT4_O_I3 I2=$iopadmap$b(2) I3=out_LUT4_O_37_I2_LUT4_O_I3 O=out_LUT4_O_37_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(3) I2=out_LUT4_O_37_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_37_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_37_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_38_I1_LUT4_O_I3 I1=$iopadmap$b(2) I2=$iopadmap$a(0) I3=out_LUT4_O_37_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_37_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$a(2) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_37_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_35_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(2) I3=$iopadmap$a(1) O=out_LUT4_O_37_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_38_I3 I1=out_LUT4_O_38_I2 I2=out_LUT4_O_37_I3_LUT4_O_I2 I3=out_LUT4_O_37_I3_LUT4_O_I3 O=out_LUT4_O_37_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111000100001110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_37_I3_LUT4_O_I3_LUT4_O_I3 I2=out_LUT4_O_37_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_37_I3_LUT4_O_I2 O=out_LUT4_O_36_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_38_I2_LUT4_O_I3 I3=out_LUT4_O_38_I2_LUT4_O_I2 O=out_LUT4_O_37_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_37_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_37_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_37_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_37_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_37_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I1 I2=out_LUT4_O_38_I2 I3=out_LUT4_O_38_I3 O=$iopadmap$out(2)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101111
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(2) I2=out_LUT4_O_38_I1_LUT4_O_I2 I3=out_LUT4_O_38_I1_LUT4_O_I3 O=out_LUT4_O_38_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(1) I2=$iopadmap$b(0) I3=out_LUT4_O_38_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$a(1) I3=$iopadmap$a(0) O=out_LUT4_O_38_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(1) I2=$iopadmap$a(2) I3=$iopadmap$b(0) O=out_LUT4_O_38_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_37_I3_LUT4_O_I3 I3=out_LUT4_O_38_I2 O=out_LUT4_O_36_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_38_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3 O=out_LUT4_O_38_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(29) I3=$iopadmap$b(8) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(7) I2=$iopadmap$a(31) I3=$iopadmap$b(6) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(31) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(4) I2=$iopadmap$a(33) I3=$iopadmap$b(3) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(28) I2=$iopadmap$b(8) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(27) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(10) I2=$iopadmap$a(29) I3=$iopadmap$b(9) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(26) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(24) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(13) I2=$iopadmap$a(26) I3=$iopadmap$b(12) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(22) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(16) I2=$iopadmap$a(24) I3=$iopadmap$b(15) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(24) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(21) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(16) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(22) I2=$iopadmap$a(18) I3=$iopadmap$b(21) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(19) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(19) I2=$iopadmap$a(21) I3=$iopadmap$b(18) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(18) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(14) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(25) I2=$iopadmap$a(16) I3=$iopadmap$b(24) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(16) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(13) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(8) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(31) I2=$iopadmap$a(10) I3=$iopadmap$b(30) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(11) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(28) I2=$iopadmap$a(13) I3=$iopadmap$b(27) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(10) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(5) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(34) I2=$iopadmap$a(7) I3=$iopadmap$b(33) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(4) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(7) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(9) I2=$iopadmap$a(8) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(40) I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(39) I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(2) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(3) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(37) I2=$iopadmap$a(5) I3=$iopadmap$b(36) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(1) I3=$iopadmap$b(39) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(0) I3=$iopadmap$b(40) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$a(40) I2=$iopadmap$b(2) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(1) I3=$iopadmap$a(39) O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(5) I2=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_32_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(28) I3=$iopadmap$b(8) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(7) I2=$iopadmap$a(30) I3=$iopadmap$b(6) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(30) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(4) I2=$iopadmap$a(32) I3=$iopadmap$b(3) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(27) I2=$iopadmap$b(8) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(26) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(10) I2=$iopadmap$a(28) I3=$iopadmap$b(9) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(25) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(23) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(13) I2=$iopadmap$a(25) I3=$iopadmap$b(12) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(21) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(16) I2=$iopadmap$a(23) I3=$iopadmap$b(15) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(23) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(20) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(15) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(22) I2=$iopadmap$a(17) I3=$iopadmap$b(21) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(18) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(19) I2=$iopadmap$a(20) I3=$iopadmap$b(18) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(17) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(13) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(25) I2=$iopadmap$a(15) I3=$iopadmap$b(24) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(15) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(12) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(10) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(28) I2=$iopadmap$a(12) I3=$iopadmap$b(27) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(9) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(7) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(31) I2=$iopadmap$a(9) I3=$iopadmap$b(30) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(4) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(34) I2=$iopadmap$a(6) I3=$iopadmap$b(33) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(3) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(6) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(8) I2=$iopadmap$a(7) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(40) I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(39) I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(1) I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(2) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(37) I2=$iopadmap$a(4) I3=$iopadmap$b(36) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$a(0) I3=$iopadmap$b(39) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(2) I2=$iopadmap$a(40) I3=$iopadmap$b(1) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_32_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(36) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(40) I3=$iopadmap$b(0) O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_38_I3_LUT4_O_I2 I3=out_LUT4_O_38_I3_LUT4_O_I3 O=out_LUT4_O_38_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_39_I3_LUT4_O_I3_LUT4_O_I3 I1=out_LUT4_O_39_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3 O=out_LUT4_O_38_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=out_LUT4_O_40_I2_LUT4_O_I2 I1=out_LUT4_O_40_I2_LUT4_O_I3 I2=out_LUT4_O_40_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_I3_O O=out_LUT4_O_38_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111100000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_39_I2 I3=out_LUT4_O_39_I3 O=$iopadmap$out(1)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(1) I2=$iopadmap$a(1) I3=$iopadmap$b(0) O=out_LUT4_O_39_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I2 I1=out_LUT4_O_40_I3_LUT4_O_I3 I2=out_LUT4_O_40_I3_LUT4_O_I2 I3=out_LUT4_O_39_I3_LUT4_O_I3 O=out_LUT4_O_39_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_39_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_39_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_39_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_39_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_39_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I1_LUT4_O_I2 I3=out_LUT4_O_3_I1_LUT4_O_I3 O=out_LUT4_O_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_16_I1_LUT4_O_I3_LUT4_O_I3 I1=out_LUT4_O_3_I1_LUT4_O_I2 I2=out_LUT4_O_3_I1_LUT4_O_I3 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_I1_I3 O=out_LUT4_O_2_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_I1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_3_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_3_I2_LUT4_O_I0 I1=out_LUT4_O_3_I2_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3 O=out_LUT4_O_3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I2 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(0) I3=$iopadmap$b(21) O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(21) I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(0) I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$a(2) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(1) O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(19) I2=$iopadmap$a(3) I3=$iopadmap$b(18) O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=out_LUT4_O_3_I2_LUT4_O_I0 I1=out_LUT4_O_3_I2_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3 O=out_LUT4_O_16_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O O=out_LUT4_O_3_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0011111111010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(20) I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(1) I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(19) I2=$iopadmap$a(4) I3=$iopadmap$b(18) O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(21) I3=$iopadmap$a(1) O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(22) I3=$iopadmap$a(0) O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(20) I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=out_LUT4_O_17_I3 I1=out_LUT4_O_3_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I3 O=out_LUT4_O_3_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(40) I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(39) I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(23) I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(24) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(37) I2=$iopadmap$a(26) I3=$iopadmap$b(36) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(22) I3=$iopadmap$b(39) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(21) I3=$iopadmap$b(40) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(29) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(31) I2=$iopadmap$a(31) I3=$iopadmap$b(30) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(32) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(28) I2=$iopadmap$a(34) I3=$iopadmap$b(27) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(31) I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(26) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(34) I2=$iopadmap$a(28) I3=$iopadmap$b(33) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(25) I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(28) I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(30) I2=$iopadmap$a(29) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(35) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(25) I2=$iopadmap$a(37) I3=$iopadmap$b(24) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(34) I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(40) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 I1=out_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_3_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(40) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(39) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(24) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(25) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(37) I2=$iopadmap$a(27) I3=$iopadmap$b(36) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(23) I3=$iopadmap$b(39) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(22) I3=$iopadmap$b(40) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(30) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(31) I2=$iopadmap$a(32) I3=$iopadmap$b(30) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(33) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(28) I2=$iopadmap$a(35) I3=$iopadmap$b(27) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(32) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(27) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(34) I2=$iopadmap$a(29) I3=$iopadmap$b(33) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(26) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(29) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(31) I2=$iopadmap$a(30) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(36) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(25) I2=$iopadmap$a(38) I3=$iopadmap$b(24) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(35) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(32) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(31) I2=$iopadmap$a(34) I3=$iopadmap$b(30) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(35) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(28) I2=$iopadmap$a(37) I3=$iopadmap$b(27) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(34) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(29) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(34) I2=$iopadmap$a(31) I3=$iopadmap$b(33) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(28) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(31) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(33) I2=$iopadmap$a(32) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(26) I3=$iopadmap$a(38) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$b(24) I3=$iopadmap$a(40) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(37) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(24) I2=$iopadmap$a(38) I3=out_LUT4_O_2_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(31) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(31) I2=$iopadmap$a(33) I3=$iopadmap$b(30) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(34) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(28) I2=$iopadmap$a(36) I3=$iopadmap$b(27) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(33) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(28) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(34) I2=$iopadmap$a(30) I3=$iopadmap$b(33) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(27) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(30) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(32) I2=$iopadmap$a(31) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(36) I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$a(38) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(37) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(25) I2=$iopadmap$a(39) I3=$iopadmap$b(24) O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(23) I2=$iopadmap$a(40) I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_16_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_3_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_4_I0 I1=out_LUT4_O_4_I1 I2=out_LUT4_O_4_I2 I3=out_LUT4_O_4_I3 O=$iopadmap$out(22)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110111111110110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(0) I2=out_LUT4_O_40_I2 I3=out_LUT4_O_40_I3 O=$iopadmap$out(0)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111111111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I2_LUT4_O_I1 I2=out_LUT4_O_40_I2_LUT4_O_I2 I3=out_LUT4_O_40_I2_LUT4_O_I3 O=out_LUT4_O_40_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I2_LUT4_O_I2 I3=out_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_40_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I1=out_LUT4_O_8_I2_LUT4_O_I2 I2=out_LUT4_O_6_I3_LUT4_O_I3 I3=out_LUT4_O_I0_LUT4_O_I1 O=out_LUT4_O_40_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)"
+.param INIT 0000000000000001
+.subckt LUT4 I0=out_LUT4_O_12_I3_LUT4_O_I3 I1=out_LUT4_O_1_I1_LUT4_O_I2 I2=out_LUT4_O_1_I1_LUT4_O_I3 I3=out_LUT4_O_11_I3_LUT4_I2_O O=out_LUT4_O_40_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_39_I3_LUT4_O_I3 I3=out_LUT4_O_40_I3 O=out_LUT4_O_40_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3 O=out_LUT4_O_40_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(27) I3=$iopadmap$b(8) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(7) I2=$iopadmap$a(29) I3=$iopadmap$b(6) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(29) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(4) I2=$iopadmap$a(31) I3=$iopadmap$b(3) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(26) I2=$iopadmap$b(8) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(25) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(10) I2=$iopadmap$a(27) I3=$iopadmap$b(9) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(24) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(22) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(13) I2=$iopadmap$a(24) I3=$iopadmap$b(12) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(20) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(16) I2=$iopadmap$a(22) I3=$iopadmap$b(15) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(22) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(19) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(17) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(19) I2=$iopadmap$a(19) I3=$iopadmap$b(18) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(16) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(14) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(22) I2=$iopadmap$a(16) I3=$iopadmap$b(21) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(12) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(25) I2=$iopadmap$a(14) I3=$iopadmap$b(24) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(14) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(11) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(9) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(28) I2=$iopadmap$a(11) I3=$iopadmap$b(27) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(8) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(6) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(31) I2=$iopadmap$a(8) I3=$iopadmap$b(30) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(3) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(34) I2=$iopadmap$a(5) I3=$iopadmap$b(33) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(2) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(5) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(7) I2=$iopadmap$a(6) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=$iopadmap$b(38) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(39) I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=$iopadmap$b(38) I2=$iopadmap$a(0) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(37) I2=$iopadmap$a(2) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(1) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(37) I2=$iopadmap$a(3) I3=$iopadmap$b(36) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(35) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(40) I1=$iopadmap$b(0) I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(2) I3=$iopadmap$a(38) O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(37) I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(0) I2=$iopadmap$a(38) I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(20) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(13) I2=$iopadmap$a(22) I3=$iopadmap$b(12) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(23) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(10) I2=$iopadmap$a(25) I3=$iopadmap$b(9) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(11) I2=$iopadmap$a(22) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(10) I2=$iopadmap$a(24) I3=$iopadmap$b(9) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(24) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(10) I2=$iopadmap$a(26) I3=$iopadmap$b(9) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(23) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(21) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(13) I2=$iopadmap$a(23) I3=$iopadmap$b(12) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$a(25) I2=$iopadmap$b(8) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(7) I2=$iopadmap$a(27) I3=$iopadmap$b(6) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(26) I3=$iopadmap$b(8) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(7) I2=$iopadmap$a(28) I3=$iopadmap$b(6) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(28) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(4) I2=$iopadmap$a(30) I3=$iopadmap$b(3) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(19) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(16) I2=$iopadmap$a(21) I3=$iopadmap$b(15) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(21) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(18) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(16) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(19) I2=$iopadmap$a(18) I3=$iopadmap$b(18) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(15) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(13) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(22) I2=$iopadmap$a(15) I3=$iopadmap$b(21) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(15) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(19) I2=$iopadmap$a(17) I3=$iopadmap$b(18) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(14) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(12) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(22) I2=$iopadmap$a(14) I3=$iopadmap$b(21) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(18) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(16) I2=$iopadmap$a(20) I3=$iopadmap$b(15) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(20) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(17) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(17) I2=$iopadmap$a(16) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(16) I2=$iopadmap$a(18) I3=$iopadmap$b(15) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(17) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(16) I2=$iopadmap$a(19) I3=$iopadmap$b(15) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(14) I2=$iopadmap$a(19) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(13) I2=$iopadmap$a(21) I3=$iopadmap$b(12) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(11) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(25) I2=$iopadmap$a(13) I3=$iopadmap$b(24) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(13) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(10) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(8) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(28) I2=$iopadmap$a(10) I3=$iopadmap$b(27) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(7) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(5) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(31) I2=$iopadmap$a(7) I3=$iopadmap$b(30) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(2) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(34) I2=$iopadmap$a(4) I3=$iopadmap$b(33) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(1) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(4) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(6) I2=$iopadmap$a(5) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(26) I2=$iopadmap$a(7) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(25) I2=$iopadmap$a(9) I3=$iopadmap$b(24) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(8) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(25) I2=$iopadmap$a(10) I3=$iopadmap$b(24) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(23) I2=$iopadmap$a(10) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(22) I2=$iopadmap$a(12) I3=$iopadmap$b(21) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(9) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(25) I2=$iopadmap$a(11) I3=$iopadmap$b(24) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(11) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(8) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(14) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(19) I2=$iopadmap$a(16) I3=$iopadmap$b(18) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(20) I2=$iopadmap$a(13) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(19) I2=$iopadmap$a(15) I3=$iopadmap$b(18) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(11) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(22) I2=$iopadmap$a(13) I3=$iopadmap$b(21) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(10) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(25) I2=$iopadmap$a(12) I3=$iopadmap$b(24) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(12) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(9) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(7) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(28) I2=$iopadmap$a(9) I3=$iopadmap$b(27) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(6) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(4) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(31) I2=$iopadmap$a(6) I3=$iopadmap$b(30) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(1) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(34) I2=$iopadmap$a(3) I3=$iopadmap$b(33) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(3) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(5) I2=$iopadmap$a(4) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(0) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(34) I2=$iopadmap$a(2) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(38) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(37) I2=$iopadmap$a(0) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(37) I2=$iopadmap$a(2) I3=$iopadmap$b(36) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(37) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(3) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(31) I2=$iopadmap$a(5) I3=$iopadmap$b(30) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(6) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(28) I2=$iopadmap$a(8) I3=$iopadmap$b(27) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(5) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(2) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(4) I2=$iopadmap$a(3) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(0) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(34) I2=$iopadmap$a(2) I3=$iopadmap$b(33) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(36) I3=$iopadmap$a(0) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(36) I2=$iopadmap$a(0) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(37) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(36) I3=$iopadmap$a(1) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(37) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(1) I2=$iopadmap$a(39) I3=$iopadmap$b(0) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(36) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$a(38) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_34_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(34) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(33) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(1) I2=$iopadmap$a(35) I3=$iopadmap$b(0) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(32) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(30) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(34) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(1) I2=$iopadmap$a(36) I3=$iopadmap$b(0) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(33) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(31) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(35) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(1) I2=$iopadmap$a(37) I3=$iopadmap$b(0) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(34) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(32) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(36) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(1) I2=$iopadmap$a(38) I3=$iopadmap$b(0) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(35) I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(33) O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_36_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_38_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_19_I2 I1=out_LUT4_O_4_I0_LUT4_O_I1 I2=out_LUT4_O_4_I0_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I3 O=out_LUT4_O_4_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110110110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_20_I3_LUT4_O_I2 I3=out_LUT4_O_20_I3_LUT4_O_I1 O=out_LUT4_O_4_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I1_LUT4_O_I3 I3=out_LUT4_O_4_I1_LUT4_O_I2 O=out_LUT4_O_4_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(20) I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_3_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_18_I1_LUT4_O_I3 I1=out_LUT4_O_4_I0_LUT4_O_I3 I2=out_LUT4_O_4_I1 I3=out_LUT4_O_4_I1_LUT4_I2_I3 O=out_LUT4_O_3_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I2_LUT4_O_I0_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_4_I0_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O O=out_LUT4_O_4_I1_LUT4_I2_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3 O=out_LUT4_O_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(11) I2=$iopadmap$a(4) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(10) I2=$iopadmap$a(6) I3=$iopadmap$b(9) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(14) I3=$iopadmap$a(2) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(11) I3=$iopadmap$a(5) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$a(7) I2=$iopadmap$b(8) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(7) I2=$iopadmap$a(9) I3=$iopadmap$b(6) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(10) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(4) I2=$iopadmap$a(12) I3=$iopadmap$b(3) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(8) I3=$iopadmap$b(8) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(7) I2=$iopadmap$a(10) I3=$iopadmap$b(6) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(11) I2=$iopadmap$a(5) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(10) I2=$iopadmap$a(7) I3=$iopadmap$b(9) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(14) I3=$iopadmap$a(3) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(6) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(10) I2=$iopadmap$a(8) I3=$iopadmap$b(9) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)"
+.param INIT 0000000100010000
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(14) I2=$iopadmap$a(1) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(13) I2=$iopadmap$a(3) I3=$iopadmap$b(12) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(15) I3=$iopadmap$a(1) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(16) I3=$iopadmap$a(0) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(18) I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(1) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(16) I2=$iopadmap$a(3) I3=$iopadmap$b(15) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(14) I2=$iopadmap$a(3) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(13) I2=$iopadmap$a(5) I3=$iopadmap$b(12) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(0) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(16) I2=$iopadmap$a(2) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I1=out_LUT4_O_22_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(2) I2=$iopadmap$a(12) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(1) I2=$iopadmap$a(14) I3=$iopadmap$b(0) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(10) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(13) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(1) I2=$iopadmap$a(15) I3=$iopadmap$b(0) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(13) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(11) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(2) I3=$iopadmap$a(14) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(2) I2=$iopadmap$a(14) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(1) I2=$iopadmap$a(16) I3=$iopadmap$b(0) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(12) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(2) I3=$iopadmap$a(15) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(9) I2=$iopadmap$b(8) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(10) I3=$iopadmap$b(8) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$b(7) I2=$iopadmap$a(12) I3=$iopadmap$b(6) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(12) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(4) I2=$iopadmap$a(14) I3=$iopadmap$b(3) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(2) I2=$iopadmap$a(15) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(1) I2=$iopadmap$a(17) I3=$iopadmap$b(0) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(13) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$b(4) I2=$iopadmap$a(15) I3=$iopadmap$b(3) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(16) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$b(1) I2=$iopadmap$a(18) I3=$iopadmap$b(0) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(7) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$a(9) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(5) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(13) I2=$iopadmap$a(7) I3=$iopadmap$b(12) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(8) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$b(10) I2=$iopadmap$a(10) I3=$iopadmap$b(9) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(10) I2=$iopadmap$b(8) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(11) I1=$iopadmap$a(12) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(13) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(14) I1=$iopadmap$a(15) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(11) I3=$iopadmap$b(8) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(7) I2=$iopadmap$a(13) I3=$iopadmap$b(6) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(16) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(17) I1=$iopadmap$a(18) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(14) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$b(4) I2=$iopadmap$a(16) I3=$iopadmap$b(3) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(17) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(1) I2=$iopadmap$a(19) I3=$iopadmap$b(0) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(6) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(4) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(13) I2=$iopadmap$a(6) I3=$iopadmap$b(12) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(7) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(8) I1=$iopadmap$b(10) I2=$iopadmap$a(9) I3=$iopadmap$b(9) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$a(8) I2=$iopadmap$b(8) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(9) I3=$iopadmap$b(8) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(7) I2=$iopadmap$a(11) I3=$iopadmap$b(6) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(11) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$b(4) I2=$iopadmap$a(13) I3=$iopadmap$b(3) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(19) I2=$iopadmap$a(1) I3=$iopadmap$b(18) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(4) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(1) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$a(3) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(2) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(16) I2=$iopadmap$a(4) I3=$iopadmap$b(15) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$a(0) I3=$iopadmap$b(18) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(8) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(9) I1=$iopadmap$a(10) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(6) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$b(13) I2=$iopadmap$a(8) I3=$iopadmap$b(12) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(9) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(10) I2=$iopadmap$a(11) I3=$iopadmap$b(9) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$a(11) I2=$iopadmap$b(8) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(14) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(12) I3=$iopadmap$b(8) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(7) I2=$iopadmap$a(14) I3=$iopadmap$b(6) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(17) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(5) I3=$iopadmap$a(15) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(4) I2=$iopadmap$a(17) I3=$iopadmap$b(3) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(18) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(1) I2=$iopadmap$a(20) I3=$iopadmap$b(0) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(5) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$a(7) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(2) I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$a(4) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(3) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$b(16) I2=$iopadmap$a(5) I3=$iopadmap$b(15) O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(6) I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(3) I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(17) I3=$iopadmap$a(4) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(9) I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(14) I3=$iopadmap$a(7) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(11) I3=$iopadmap$a(10) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$a(12) I2=$iopadmap$b(8) I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$a(13) I3=$iopadmap$b(8) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(5) I2=$iopadmap$a(15) I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(2) I2=$iopadmap$a(18) I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(0) I3=$iopadmap$b(1) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_2_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(5) I3=$iopadmap$a(16) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(2) I3=$iopadmap$a(19) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(1) I2=$iopadmap$a(21) I3=$iopadmap$b(0) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(20) I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000001001111101
+.subckt LUT4 I0=$iopadmap$a(0) I1=$iopadmap$b(20) I2=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(19) I2=$iopadmap$b(18) I3=out_LUT4_O_38_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(19) I2=$iopadmap$a(2) I3=$iopadmap$b(18) O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I2_LUT4_O_I1 I2=out_LUT4_O_4_I2_LUT4_O_I2 I3=out_LUT4_O_21_I3_LUT4_I2_O_LUT4_I2_O O=out_LUT4_O_4_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110000
+.subckt LUT4 I0=out_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_20_I1_LUT4_O_I2 I3=out_LUT4_O_20_I1_LUT4_O_I3 O=out_LUT4_O_4_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101010011011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_20_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_18_I0_LUT4_O_I3 I3=out_LUT4_O_4_I3 O=out_LUT4_O_4_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3 O=out_LUT4_O_4_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(40) I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(39) I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(22) I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(23) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(37) I2=$iopadmap$a(25) I3=$iopadmap$b(36) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(21) I3=$iopadmap$b(39) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(20) I3=$iopadmap$b(40) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(28) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(31) I2=$iopadmap$a(30) I3=$iopadmap$b(30) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(31) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(28) I2=$iopadmap$a(33) I3=$iopadmap$b(27) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(30) I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(25) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(34) I2=$iopadmap$a(27) I3=$iopadmap$b(33) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(24) I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(27) I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(29) I2=$iopadmap$a(28) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(34) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(25) I2=$iopadmap$a(36) I3=$iopadmap$b(24) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(33) I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(36) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(23) I3=$iopadmap$a(39) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(22) I3=$iopadmap$a(40) O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_3_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(23) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*I3)"
+.param INIT 0000100000000111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(40) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(39) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(21) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(22) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(37) I2=$iopadmap$a(24) I3=$iopadmap$b(36) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(20) I3=$iopadmap$b(39) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(19) I3=$iopadmap$b(40) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(24) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(31) I2=$iopadmap$a(26) I3=$iopadmap$b(30) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(27) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(28) I2=$iopadmap$a(29) I3=$iopadmap$b(27) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(29) I2=$iopadmap$a(26) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(28) I2=$iopadmap$a(28) I3=$iopadmap$b(27) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(25) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(31) I2=$iopadmap$a(27) I3=$iopadmap$b(30) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(28) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$b(28) I2=$iopadmap$a(30) I3=$iopadmap$b(27) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(27) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(22) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(34) I2=$iopadmap$a(24) I3=$iopadmap$b(33) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(21) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(24) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(26) I2=$iopadmap$a(25) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(39) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(19) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(20) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(37) I2=$iopadmap$a(22) I3=$iopadmap$b(36) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(18) I3=$iopadmap$b(39) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(39) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(18) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(19) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(37) I2=$iopadmap$a(21) I3=$iopadmap$b(36) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(17) I3=$iopadmap$b(39) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$b(38) I2=$iopadmap$a(17) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(37) I2=$iopadmap$a(19) I3=$iopadmap$b(36) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(18) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(37) I2=$iopadmap$a(20) I3=$iopadmap$b(36) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(21) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(34) I2=$iopadmap$a(23) I3=$iopadmap$b(33) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(35) I2=$iopadmap$a(20) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(34) I2=$iopadmap$a(22) I3=$iopadmap$b(33) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(32) I2=$iopadmap$a(23) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(31) I2=$iopadmap$a(25) I3=$iopadmap$b(30) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(25) I2=$iopadmap$a(24) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$b(39) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(20) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(21) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(37) I2=$iopadmap$a(23) I3=$iopadmap$b(36) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(19) I3=$iopadmap$b(39) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(33) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(22) I2=$iopadmap$a(35) I3=$iopadmap$b(21) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(36) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(19) I2=$iopadmap$a(38) I3=$iopadmap$b(18) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(20) I2=$iopadmap$a(35) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(19) I2=$iopadmap$a(37) I3=$iopadmap$b(18) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(31) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(25) I2=$iopadmap$a(33) I3=$iopadmap$b(24) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(33) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(30) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$a(32) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(30) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(25) I2=$iopadmap$a(32) I3=$iopadmap$b(24) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(23) I2=$iopadmap$a(32) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(22) I2=$iopadmap$a(34) I3=$iopadmap$b(21) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(26) I2=$iopadmap$a(29) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(25) I2=$iopadmap$a(31) I3=$iopadmap$b(24) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(32) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(25) I2=$iopadmap$a(34) I3=$iopadmap$b(24) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(34) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(31) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(26) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(31) I2=$iopadmap$a(28) I3=$iopadmap$b(30) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(29) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$b(28) I2=$iopadmap$a(31) I3=$iopadmap$b(27) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(28) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(29) I1=$iopadmap$a(30) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(23) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(34) I2=$iopadmap$a(25) I3=$iopadmap$b(33) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(22) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(25) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(27) I2=$iopadmap$a(26) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(27) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(31) I2=$iopadmap$a(29) I3=$iopadmap$b(30) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(30) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(28) I2=$iopadmap$a(32) I3=$iopadmap$b(27) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(29) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(30) I1=$iopadmap$a(31) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(35) I3=$iopadmap$a(24) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(34) I2=$iopadmap$a(26) I3=$iopadmap$b(33) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(35) I2=$iopadmap$a(23) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(26) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(28) I2=$iopadmap$a(27) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(26) I3=$iopadmap$a(33) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(25) I2=$iopadmap$a(35) I3=$iopadmap$b(24) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(23) I2=$iopadmap$a(35) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(32) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(17) I2=$iopadmap$a(40) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(34) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(22) I2=$iopadmap$a(36) I3=$iopadmap$b(21) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(20) I3=$iopadmap$a(37) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(19) I2=$iopadmap$a(39) I3=$iopadmap$b(18) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(36) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$a(38) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(17) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_24_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(40) I3=$iopadmap$b(15) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(16) I3=$iopadmap$a(40) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$a(40) I2=$iopadmap$b(17) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111111110000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(16) I3=$iopadmap$a(39) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(35) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(22) I2=$iopadmap$a(37) I3=$iopadmap$b(21) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(40) I1=$iopadmap$b(18) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(37) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(18) I2=$iopadmap$a(38) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(23) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(23) I2=$iopadmap$a(38) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_I3_O_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 00000111
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(22) I2=$iopadmap$a(40) I3=$iopadmap$b(21) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$a(40) I2=$iopadmap$b(20) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(19) I3=$iopadmap$a(39) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$a(40) I3=$iopadmap$b(20) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1101000000000000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(23) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I2=$iopadmap$a(37) I3=$iopadmap$b(23) O=out_LUT4_O_3_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(21) I2=$iopadmap$a(37) I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(22) I3=$iopadmap$a(38) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(21) I3=$iopadmap$a(39) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_4_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(20) I2=$iopadmap$a(40) I3=$iopadmap$b(19) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(23) I3=$iopadmap$a(36) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(22) I2=$iopadmap$a(38) I3=$iopadmap$b(21) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(40) I3=$iopadmap$b(18) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(20) I3=$iopadmap$a(38) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$a(40) I3=$iopadmap$b(17) O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_4_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_5_I0 I1=out_LUT4_O_5_I1 I2=out_LUT4_O_5_I2 I3=out_LUT4_O_5_I3 O=mult_wire(80)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000100011110
+.subckt LUT4 I0=out_LUT4_O_7_I0_LUT4_O_I3 I1=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=out_LUT4_O_5_I0_LUT4_O_I3 O=out_LUT4_O_5_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I2_LUT4_O_I2 I2=out_LUT4_O_6_I2_LUT4_O_I3 I3=out_LUT4_O_6_I1 O=out_LUT4_O_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I2_LUT4_O_I1 I2=out_LUT4_O_5_I2_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I3 O=out_LUT4_O_5_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(40) I2=out_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=$iopadmap$a(40) I1=$iopadmap$b(39) I2=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0 I3=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(38) I3=$iopadmap$b(40) O=out_LUT4_O_5_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(35) I2=$iopadmap$a(39) I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(39) I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(37) I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$a(39) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=$iopadmap$b(38) I3=$iopadmap$a(38) O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(36) I3=$iopadmap$b(39) O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$b(38) I2=$iopadmap$a(36) I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(37) I2=$iopadmap$a(38) I3=$iopadmap$b(36) O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$a(38) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(37) O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(37) I2=$iopadmap$a(39) I3=$iopadmap$b(36) O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(39) I2=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(37) I3=$iopadmap$b(39) O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(39) I2=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(40) I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(37) I3=$iopadmap$b(40) O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(39) I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(35) I3=$iopadmap$b(39) O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$b(38) I2=$iopadmap$a(35) I3=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(37) I2=$iopadmap$a(37) I3=$iopadmap$b(36) O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$a(37) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I2=$iopadmap$b(38) I3=$iopadmap$a(36) O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 I3=out_LUT4_O_5_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I2 O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=$iopadmap$a(40) I1=$iopadmap$b(40) I2=out_LUT4_O_5_I3_LUT4_O_I2 I3=out_LUT4_O_5_I3_LUT4_O_I3 O=out_LUT4_O_5_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_5_I2_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(39) I3=$iopadmap$b(40) O=out_LUT4_O_5_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(40) I3=$iopadmap$b(39) O=out_LUT4_O_5_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(39) I2=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(38) I3=$iopadmap$b(39) O=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$b(38) I2=$iopadmap$a(38) I3=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(37) I2=$iopadmap$a(40) I3=$iopadmap$b(36) O=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$a(40) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(38) I2=$iopadmap$a(40) I3=$iopadmap$b(37) O=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(37) I2=$iopadmap$a(40) I3=$iopadmap$b(38) O=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(39) I3=$iopadmap$b(37) O=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(38) I2=$iopadmap$a(40) I3=$iopadmap$a(39) O=out_LUT4_O_5_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=out_LUT4_O_6_I0 I1=out_LUT4_O_6_I1 I2=out_LUT4_O_6_I2 I3=out_LUT4_O_6_I3 O=$iopadmap$out(39)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000111111111
+.subckt LUT4 I0=out_LUT4_O_7_I0_LUT4_O_I3 I1=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I3=out_LUT4_O_7_I1 O=out_LUT4_O_6_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)"
+.param INIT 0000000001110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_7_I1_LUT4_O_I3 I3=out_LUT4_O_7_I1_LUT4_O_I2 O=out_LUT4_O_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_6_I2 I3=out_LUT4_O_7_I1 O=out_LUT4_O_5_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_6_I2_LUT4_O_I2 I3=out_LUT4_O_6_I2_LUT4_O_I3 O=out_LUT4_O_6_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I2_LUT4_O_I1 I2=out_LUT4_O_5_I2_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I3 O=out_LUT4_O_6_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_6_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=out_LUT4_O_7_I2 I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=out_LUT4_O_6_I3_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I3 O=out_LUT4_O_6_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 I2=out_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(24) I2=$iopadmap$b(8) I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$a(25) I3=$iopadmap$b(8) O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(27) I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$b(4) I2=$iopadmap$a(29) I3=$iopadmap$b(3) O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(28) I1=$iopadmap$a(29) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_6_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_7_I0 I1=out_LUT4_O_7_I1 I2=out_LUT4_O_7_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O O=$iopadmap$out(38)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001111111111001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O I2=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O I3=out_LUT4_O_7_I0_LUT4_O_I3 O=out_LUT4_O_7_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_7_I1_LUT4_O_I2 I3=out_LUT4_O_7_I1_LUT4_O_I3 O=out_LUT4_O_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_7_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_7_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_7_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(40) I2=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I3=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(36) I3=$iopadmap$b(40) O=out_LUT4_O_7_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_7_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1 I3=out_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_7_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 00001101
+.subckt LUT4 I0=out_LUT4_O_6_I3_LUT4_O_I3 I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_I2_O I2=out_LUT4_O_7_I2_LUT4_O_I1 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_I3_O O=out_LUT4_O_40_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000011101111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2 O=out_LUT4_O_7_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_8_I0 I1=out_LUT4_O_8_I1 I2=out_LUT4_O_8_I2 I3=out_LUT4_O_8_I3 O=$iopadmap$out(36)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111111011110001
+.subckt LUT4 I0=out_LUT4_O_13_I2_LUT4_I3_O_LUT4_I2_O I1=out_LUT4_O_8_I0_LUT4_O_I1 I2=out_LUT4_O_8_I0_LUT4_O_I2 I3=out_LUT4_O_8_I0_LUT4_O_I3 O=out_LUT4_O_8_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111010000000000
+.subckt LUT4 I0=out_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3 O=out_LUT4_O_8_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 0010101100100010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_8_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_8_I1 I2=out_LUT4_O_8_I0 I3=out_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_7_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I2_LUT4_O_I3 I2=out_LUT4_O_9_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1 O=out_LUT4_O_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_8_I2_LUT4_O_I2 I3=out_LUT4_O_8_I2_LUT4_O_I3 O=out_LUT4_O_8_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_8_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_8_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I2_LUT4_O_I3 O=out_LUT4_O_8_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_I1_LUT4_O_I0 O=out_LUT4_O_8_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_9_I0 I1=out_LUT4_O_9_I1 I2=out_LUT4_O_9_I2 I3=out_LUT4_O_9_I3 O=$iopadmap$out(35)
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110000111111111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I1 I3=out_LUT4_O_10_I0 O=out_LUT4_O_9_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I3 O=out_LUT4_O_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(40) I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(31) I3=$iopadmap$b(40) O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(31) I1=$iopadmap$b(39) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_1_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(30) I3=$iopadmap$b(39) O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(35) I3=$iopadmap$a(38) O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01000001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(33) I3=$iopadmap$a(40) O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10000111
+.subckt LUT4 I0=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(35) I2=$iopadmap$a(37) I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(38) I1=$iopadmap$b(34) I2=$iopadmap$a(39) I3=$iopadmap$b(33) O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(33) I2=$iopadmap$a(38) I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(40) O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$b(32) I2=$iopadmap$a(40) I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_12_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111000100010001
+.subckt LUT4 I0=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(35) I2=$iopadmap$a(36) I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$b(34) I2=$iopadmap$a(38) I3=$iopadmap$b(33) O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(37) I1=$iopadmap$a(38) I2=$iopadmap$b(33) I3=$iopadmap$b(34) O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(35) I3=$iopadmap$a(37) O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(40) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 O=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(32) I3=$iopadmap$b(40) O=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I2 I3=out_LUT4_O_10_I1 O=out_LUT4_O_8_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I2_LUT4_O_I2 I3=out_LUT4_O_9_I2_LUT4_O_I3 O=out_LUT4_O_9_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_9_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_9_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=out_LUT4_O_10_I2 I1=out_LUT4_O_10_I3 I2=out_LUT4_O_9_I3_LUT4_O_I2 I3=out_LUT4_O_9_I3_LUT4_O_I3 O=out_LUT4_O_9_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)"
+.param INIT 0000111011110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3 I2=out_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_9_I3_LUT4_O_I2 O=out_LUT4_O_9_I3_LUT4_O_I2_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_10_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3 O=out_LUT4_O_9_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_9_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_9_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11100001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(21) I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(14) I3=$iopadmap$a(19) O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(11) I3=$iopadmap$a(22) O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(23) I2=$iopadmap$b(8) I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$a(25) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(24) I3=$iopadmap$b(8) O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(7) I2=$iopadmap$a(26) I3=$iopadmap$b(6) O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(26) I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$b(4) I2=$iopadmap$a(28) I3=$iopadmap$b(3) O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(27) I1=$iopadmap$a(28) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 01000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1110011101110001
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$b(32) I2=$iopadmap$a(0) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(1) I1=$iopadmap$b(31) I2=$iopadmap$a(2) I3=$iopadmap$b(30) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(2) I2=$iopadmap$a(1) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(3) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(4) I1=$iopadmap$a(5) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(1) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(2) I1=$iopadmap$b(31) I2=$iopadmap$a(3) I3=$iopadmap$b(30) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(4) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$b(28) I2=$iopadmap$a(6) I3=$iopadmap$b(27) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001011001101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(33) I3=$iopadmap$a(0) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$a(21) I2=$iopadmap$b(8) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$a(23) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(22) I3=$iopadmap$b(8) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$b(7) I2=$iopadmap$a(24) I3=$iopadmap$b(6) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(24) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$b(4) I2=$iopadmap$a(26) I3=$iopadmap$b(3) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(25) I1=$iopadmap$a(26) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$a(23) I3=$iopadmap$b(8) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(24) I1=$iopadmap$b(7) I2=$iopadmap$a(25) I3=$iopadmap$b(6) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$b(5) I2=$iopadmap$a(25) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$b(4) I2=$iopadmap$a(27) I3=$iopadmap$b(3) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(26) I1=$iopadmap$a(27) I2=$iopadmap$b(3) I3=$iopadmap$b(4) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$a(22) I2=$iopadmap$b(8) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(23) I1=$iopadmap$a(24) I2=$iopadmap$b(6) I3=$iopadmap$b(7) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(20) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$a(22) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(14) I3=$iopadmap$a(18) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$b(13) I2=$iopadmap$a(20) I3=$iopadmap$b(12) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(21) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(22) I1=$iopadmap$b(10) I2=$iopadmap$a(23) I3=$iopadmap$b(9) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(14) I3=$iopadmap$a(17) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(11) I3=$iopadmap$a(20) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(21) I1=$iopadmap$b(10) I2=$iopadmap$a(22) I3=$iopadmap$b(9) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(11) I2=$iopadmap$a(19) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(20) I1=$iopadmap$a(21) I2=$iopadmap$b(9) I3=$iopadmap$b(10) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(14) I2=$iopadmap$a(18) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(19) I1=$iopadmap$a(20) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(15) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$a(17) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(17) I3=$iopadmap$a(16) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(14) I2=$iopadmap$a(17) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$b(13) I2=$iopadmap$a(19) I3=$iopadmap$b(12) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(18) I1=$iopadmap$a(19) I2=$iopadmap$b(12) I3=$iopadmap$b(13) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(17) I2=$iopadmap$a(14) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(15) I1=$iopadmap$a(16) I2=$iopadmap$b(15) I3=$iopadmap$b(16) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(17) I3=$iopadmap$a(15) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(16) I1=$iopadmap$b(16) I2=$iopadmap$a(17) I3=$iopadmap$b(15) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 11010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(20) I2=$iopadmap$a(11) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(12) I1=$iopadmap$a(13) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(23) I3=$iopadmap$a(9) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(20) I3=$iopadmap$a(12) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(20) I2=$iopadmap$a(12) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$b(19) I2=$iopadmap$a(14) I3=$iopadmap$b(18) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(13) I1=$iopadmap$a(14) I2=$iopadmap$b(18) I3=$iopadmap$b(19) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I2=$iopadmap$b(23) I3=$iopadmap$a(10) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$b(20) I3=$iopadmap$a(13) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0 I1=$iopadmap$b(23) I2=$iopadmap$a(9) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$b(22) I2=$iopadmap$a(11) I3=$iopadmap$b(21) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(10) I1=$iopadmap$a(11) I2=$iopadmap$b(21) I3=$iopadmap$b(22) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(26) I2=$iopadmap$a(6) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(7) I1=$iopadmap$a(8) I2=$iopadmap$b(24) I3=$iopadmap$b(25) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I0 I2=$iopadmap$b(26) I3=$iopadmap$a(7) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1111001101001101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(34) I3=$iopadmap$a(0) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(33) I3=$iopadmap$a(1) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1 I1=$iopadmap$b(32) I2=$iopadmap$a(1) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=mult_wire(0) I1=$iopadmap$a(3) I2=$iopadmap$a(2) I3=out_LUT4_O_10_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 10000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(29) I2=$iopadmap$a(4) I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(5) I1=$iopadmap$a(6) I2=$iopadmap$b(27) I3=$iopadmap$b(28) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$b(32) I3=$iopadmap$a(2) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(3) I1=$iopadmap$b(31) I2=$iopadmap$a(4) I3=$iopadmap$b(30) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(29) I3=$iopadmap$a(5) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(6) I1=$iopadmap$b(28) I2=$iopadmap$a(7) I3=$iopadmap$b(27) O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 00010100
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_40_I3_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_6_I3_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_8_I2_LUT4_O_I2 I3=out_LUT4_O_8_I2_LUT4_O_I3 O=out_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0 I1=out_LUT4_O_8_I1 I2=out_LUT4_O_8_I0 I3=out_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0101011100000001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(40) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(39) I2=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0 I3=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(34) I3=$iopadmap$b(39) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(33) I3=$iopadmap$b(40) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01110001
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(39) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(32) I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$a(34) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(33) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(37) I2=$iopadmap$a(35) I3=$iopadmap$b(36) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0 I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$a(31) I3=$iopadmap$b(39) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0 I1=$iopadmap$b(38) I2=$iopadmap$a(31) I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$b(37) I2=$iopadmap$a(33) I3=$iopadmap$b(36) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=$iopadmap$a(32) I1=$iopadmap$a(33) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(32) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(37) I2=$iopadmap$a(34) I3=$iopadmap$b(36) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(33) I1=$iopadmap$b(39) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(33) I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$a(35) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=$iopadmap$b(38) I3=$iopadmap$a(34) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(37) I2=$iopadmap$a(36) I3=$iopadmap$b(36) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101110111
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(32) I3=$iopadmap$b(39) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=$iopadmap$a(34) I1=$iopadmap$b(39) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*I2*~I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0111100010000111
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I1=$iopadmap$b(38) I2=$iopadmap$a(34) I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(I0*I1*I2*~I3)"
+.param INIT 0000000010111111
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$a(36) I2=$iopadmap$b(36) I3=$iopadmap$b(37) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000000000000000
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2_LUT4_O_I0_LUT4_O_I0 I2=$iopadmap$b(38) I3=$iopadmap$a(35) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01111000
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I2 I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1_LUT4_O_I3 I2=$iopadmap$a(33) I3=$iopadmap$b(39) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000111011101110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=$iopadmap$a(40) I2=$iopadmap$b(35) I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1011111101000000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(34) I3=$iopadmap$a(39) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(35) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=$iopadmap$a(39) I1=$iopadmap$b(35) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)"
+.param INIT 0000011100001000
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I1=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I1 I2=$iopadmap$a(40) I3=$iopadmap$b(33) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)"
+.param INIT 0001011101110111
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=$iopadmap$b(34) I3=$iopadmap$a(40) O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*I1*I2*I3)"
+.param INIT 1000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10010110
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1001
+.subckt LUT4 I0=$iopadmap$a(36) I1=$iopadmap$b(40) I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I3 I3=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(35) I3=$iopadmap$b(40) O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2 I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I1 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(I0*~I1*~I2*I3)+(~I0*~I1*I2*I3)+(I0*~I1*I2*I3)+(I0*I1*I2*I3)"
+.param INIT 10110010
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001
+.subckt LUT4 I0=$iopadmap$a(35) I1=$iopadmap$b(40) I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*I2*I3)"
+.param INIT 1000011101111000
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(~I0*I1*I2*I3)"
+.param INIT 0100
+.subckt LUT4 I0=mult_wire(0) I1=mult_wire(0) I2=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:16.41-16.110"
+.param EQN "(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0110
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I1 I2=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I2 I3=out_LUT4_O_5_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 01101001
+.subckt LUT4 I0=mult_wire(0) I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I1 I2=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3_LUT4_O_I2 I3=out_LUT4_O_9_I1_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_O_I2_LUT4_I2_O O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I2_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:20.41-20.110"
+.param EQN "(~I0*~I1*~I2*I3)+(I0*~I1*~I2*I3)+(I0*I1*~I2*I3)+(I0*~I1*I2*I3)"
+.param INIT 00101011
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I2 I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I1_LUT4_O_I2_LUT4_O_I3 I2=$iopadmap$a(34) I3=$iopadmap$b(40) O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I2_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*~I2*~I3)+(~I0*I1*~I2*~I3)+(I0*I1*~I2*~I3)+(~I0*~I1*I2*~I3)+(~I0*I1*I2*~I3)+(I0*I1*I2*~I3)+(~I0*~I1*~I2*I3)+(~I0*I1*~I2*I3)+(I0*I1*~I2*I3)+(~I0*I1*I2*I3)"
+.param INIT 0100110111011101
+.subckt LUT4 I0=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I3 I1=out_LUT4_O_I1_LUT4_O_I0_LUT4_O_I2_LUT4_O_I0 I2=$iopadmap$a(40) I3=$iopadmap$b(35) O=out_LUT4_O_I1_LUT4_O_I3_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/home/tpagarani/antmicro_install/bin/../share/yosys/quicklogic/ap3_lut_map.v:23.41-23.109"
+.param EQN "(~I0*~I1*I2*I3)"
+.param INIT 0001000000000000
+.end